1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 for (MVT VT : MVT::integer_valuetypes())
296 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
298 // We don't accept any truncstore of integer registers.
299 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
302 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
303 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
304 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
306 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
308 // SETOEQ and SETUNE require checking two conditions.
309 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
311 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
316 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
318 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
320 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
322 if (Subtarget->is64Bit()) {
323 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
324 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 } else if (!TM.Options.UseSoftFloat) {
326 // We have an algorithm for SSE2->double, and we turn this into a
327 // 64-bit FILD followed by conditional FADD for other targets.
328 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
329 // We have an algorithm for SSE2, and we turn this into a 64-bit
330 // FILD for other targets.
331 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
334 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
336 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
337 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
339 if (!TM.Options.UseSoftFloat) {
340 // SSE has no i16 to fp conversion, only i32
341 if (X86ScalarSSEf32) {
342 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
343 // f32 and f64 cases are Legal, f80 case is not
344 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
354 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
355 // are Legal, f80 is custom lowered.
356 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
359 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
361 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
362 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
364 if (X86ScalarSSEf32) {
365 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
366 // f32 and f64 cases are Legal, f80 case is not
367 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
370 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
373 // Handle FP_TO_UINT by promoting the destination to a larger signed
375 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
377 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
379 if (Subtarget->is64Bit()) {
380 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
381 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
382 } else if (!TM.Options.UseSoftFloat) {
383 // Since AVX is a superset of SSE3, only check for SSE here.
384 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
385 // Expand FP_TO_UINT into a select.
386 // FIXME: We would like to use a Custom expander here eventually to do
387 // the optimal thing for SSE vs. the default expansion in the legalizer.
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
390 // With SSE3 we can use fisttpll to convert to a signed i64; without
391 // SSE, we're stuck with a fistpll.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
395 if (isTargetFTOL()) {
396 // Use the _ftol2 runtime function, which has a pseudo-instruction
397 // to handle its weird calling convention.
398 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
401 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
402 if (!X86ScalarSSEf64) {
403 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
404 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
405 if (Subtarget->is64Bit()) {
406 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
407 // Without SSE, i64->f64 goes through memory.
408 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
412 // Scalar integer divide and remainder are lowered to use operations that
413 // produce two results, to match the available instructions. This exposes
414 // the two-result form to trivial CSE, which is able to combine x/y and x%y
415 // into a single instruction.
417 // Scalar integer multiply-high is also lowered to use two-result
418 // operations, to match the available instructions. However, plain multiply
419 // (low) operations are left as Legal, as there are single-result
420 // instructions for this in x86. Using the two-result multiply instructions
421 // when both high and low results are needed must be arranged by dagcombine.
422 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
424 setOperationAction(ISD::MULHS, VT, Expand);
425 setOperationAction(ISD::MULHU, VT, Expand);
426 setOperationAction(ISD::SDIV, VT, Expand);
427 setOperationAction(ISD::UDIV, VT, Expand);
428 setOperationAction(ISD::SREM, VT, Expand);
429 setOperationAction(ISD::UREM, VT, Expand);
431 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
432 setOperationAction(ISD::ADDC, VT, Custom);
433 setOperationAction(ISD::ADDE, VT, Custom);
434 setOperationAction(ISD::SUBC, VT, Custom);
435 setOperationAction(ISD::SUBE, VT, Custom);
438 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
439 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
440 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
442 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
454 if (Subtarget->is64Bit())
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
459 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f32 , Expand);
461 setOperationAction(ISD::FREM , MVT::f64 , Expand);
462 setOperationAction(ISD::FREM , MVT::f80 , Expand);
463 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
465 // Promote the i8 variants and force them on up to i32 which has a shorter
467 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
468 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
469 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
470 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
471 if (Subtarget->hasBMI()) {
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
474 if (Subtarget->is64Bit())
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
477 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
478 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
479 if (Subtarget->is64Bit())
480 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
483 if (Subtarget->hasLZCNT()) {
484 // When promoting the i8 variants, force them to i32 for a shorter
486 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
487 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
489 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
492 if (Subtarget->is64Bit())
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
495 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
497 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
507 // Special handling for half-precision floating point conversions.
508 // If we don't have F16C support, then lower half float conversions
509 // into library calls.
510 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
511 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
512 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
515 // There's never any support for operations beyond MVT::f32.
516 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
517 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
519 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
521 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
522 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
523 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
524 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
528 if (Subtarget->hasPOPCNT()) {
529 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
531 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
532 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
534 if (Subtarget->is64Bit())
535 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
538 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
540 if (!Subtarget->hasMOVBE())
541 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
543 // These should be promoted to a larger select which is supported.
544 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
545 // X86 wants to expand cmov itself.
546 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
547 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
562 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
563 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
564 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
565 // support continuation, user-level threading, and etc.. As a result, no
566 // other SjLj exception interfaces are implemented and please don't build
567 // your own exception handling based on them.
568 // LLVM/Clang supports zero-cost DWARF exception handling.
569 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
570 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
573 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
574 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
575 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
577 if (Subtarget->is64Bit())
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
579 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
580 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
581 if (Subtarget->is64Bit()) {
582 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
585 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
586 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
588 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
589 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
590 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
592 if (Subtarget->is64Bit()) {
593 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
594 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
598 if (Subtarget->hasSSE1())
599 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
601 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
603 // Expand certain atomics
604 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
606 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
607 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
608 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
611 if (Subtarget->hasCmpxchg16b()) {
612 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
615 // FIXME - use subtarget debug flags
616 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
617 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
618 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
621 if (Subtarget->is64Bit()) {
622 setExceptionPointerRegister(X86::RAX);
623 setExceptionSelectorRegister(X86::RDX);
625 setExceptionPointerRegister(X86::EAX);
626 setExceptionSelectorRegister(X86::EDX);
628 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
631 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::TRAP, MVT::Other, Legal);
635 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
637 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
638 setOperationAction(ISD::VASTART , MVT::Other, Custom);
639 setOperationAction(ISD::VAEND , MVT::Other, Expand);
640 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
641 // TargetInfo::X86_64ABIBuiltinVaList
642 setOperationAction(ISD::VAARG , MVT::Other, Custom);
643 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
645 // TargetInfo::CharPtrBuiltinVaList
646 setOperationAction(ISD::VAARG , MVT::Other, Expand);
647 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
650 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
651 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
653 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
655 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
656 // f32 and f64 use SSE.
657 // Set up the FP register classes.
658 addRegisterClass(MVT::f32, &X86::FR32RegClass);
659 addRegisterClass(MVT::f64, &X86::FR64RegClass);
661 // Use ANDPD to simulate FABS.
662 setOperationAction(ISD::FABS , MVT::f64, Custom);
663 setOperationAction(ISD::FABS , MVT::f32, Custom);
665 // Use XORP to simulate FNEG.
666 setOperationAction(ISD::FNEG , MVT::f64, Custom);
667 setOperationAction(ISD::FNEG , MVT::f32, Custom);
669 // Use ANDPD and ORPD to simulate FCOPYSIGN.
670 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
673 // Lower this to FGETSIGNx86 plus an AND.
674 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
675 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
677 // We don't support sin/cos/fmod
678 setOperationAction(ISD::FSIN , MVT::f64, Expand);
679 setOperationAction(ISD::FCOS , MVT::f64, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
681 setOperationAction(ISD::FSIN , MVT::f32, Expand);
682 setOperationAction(ISD::FCOS , MVT::f32, Expand);
683 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
685 // Expand FP immediates into loads from the stack, except for the special
687 addLegalFPImmediate(APFloat(+0.0)); // xorpd
688 addLegalFPImmediate(APFloat(+0.0f)); // xorps
689 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
690 // Use SSE for f32, x87 for f64.
691 // Set up the FP register classes.
692 addRegisterClass(MVT::f32, &X86::FR32RegClass);
693 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
695 // Use ANDPS to simulate FABS.
696 setOperationAction(ISD::FABS , MVT::f32, Custom);
698 // Use XORP to simulate FNEG.
699 setOperationAction(ISD::FNEG , MVT::f32, Custom);
701 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
703 // Use ANDPS and ORPS to simulate FCOPYSIGN.
704 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
705 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
707 // We don't support sin/cos/fmod
708 setOperationAction(ISD::FSIN , MVT::f32, Expand);
709 setOperationAction(ISD::FCOS , MVT::f32, Expand);
710 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
712 // Special cases we handle for FP constants.
713 addLegalFPImmediate(APFloat(+0.0f)); // xorps
714 addLegalFPImmediate(APFloat(+0.0)); // FLD0
715 addLegalFPImmediate(APFloat(+1.0)); // FLD1
716 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
717 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
719 if (!TM.Options.UnsafeFPMath) {
720 setOperationAction(ISD::FSIN , MVT::f64, Expand);
721 setOperationAction(ISD::FCOS , MVT::f64, Expand);
722 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
724 } else if (!TM.Options.UseSoftFloat) {
725 // f32 and f64 in x87.
726 // Set up the FP register classes.
727 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
728 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
730 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
731 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
735 if (!TM.Options.UnsafeFPMath) {
736 setOperationAction(ISD::FSIN , MVT::f64, Expand);
737 setOperationAction(ISD::FSIN , MVT::f32, Expand);
738 setOperationAction(ISD::FCOS , MVT::f64, Expand);
739 setOperationAction(ISD::FCOS , MVT::f32, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
743 addLegalFPImmediate(APFloat(+0.0)); // FLD0
744 addLegalFPImmediate(APFloat(+1.0)); // FLD1
745 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
746 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
747 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
748 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
749 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
750 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
753 // We don't support FMA.
754 setOperationAction(ISD::FMA, MVT::f64, Expand);
755 setOperationAction(ISD::FMA, MVT::f32, Expand);
757 // Long double always uses X87.
758 if (!TM.Options.UseSoftFloat) {
759 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
760 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
761 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
763 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
764 addLegalFPImmediate(TmpFlt); // FLD0
766 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
769 APFloat TmpFlt2(+1.0);
770 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
772 addLegalFPImmediate(TmpFlt2); // FLD1
773 TmpFlt2.changeSign();
774 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
777 if (!TM.Options.UnsafeFPMath) {
778 setOperationAction(ISD::FSIN , MVT::f80, Expand);
779 setOperationAction(ISD::FCOS , MVT::f80, Expand);
780 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
783 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
784 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
785 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
786 setOperationAction(ISD::FRINT, MVT::f80, Expand);
787 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
788 setOperationAction(ISD::FMA, MVT::f80, Expand);
791 // Always use a library call for pow.
792 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
796 setOperationAction(ISD::FLOG, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
802 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
804 // First set operation action for all vector types to either promote
805 // (for widening) or expand (for scalarization). Then we will selectively
806 // turn on ones that can be effectively codegen'd.
807 for (MVT VT : MVT::vector_valuetypes()) {
808 setOperationAction(ISD::ADD , VT, Expand);
809 setOperationAction(ISD::SUB , VT, Expand);
810 setOperationAction(ISD::FADD, VT, Expand);
811 setOperationAction(ISD::FNEG, VT, Expand);
812 setOperationAction(ISD::FSUB, VT, Expand);
813 setOperationAction(ISD::MUL , VT, Expand);
814 setOperationAction(ISD::FMUL, VT, Expand);
815 setOperationAction(ISD::SDIV, VT, Expand);
816 setOperationAction(ISD::UDIV, VT, Expand);
817 setOperationAction(ISD::FDIV, VT, Expand);
818 setOperationAction(ISD::SREM, VT, Expand);
819 setOperationAction(ISD::UREM, VT, Expand);
820 setOperationAction(ISD::LOAD, VT, Expand);
821 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
823 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
824 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
826 setOperationAction(ISD::FABS, VT, Expand);
827 setOperationAction(ISD::FSIN, VT, Expand);
828 setOperationAction(ISD::FSINCOS, VT, Expand);
829 setOperationAction(ISD::FCOS, VT, Expand);
830 setOperationAction(ISD::FSINCOS, VT, Expand);
831 setOperationAction(ISD::FREM, VT, Expand);
832 setOperationAction(ISD::FMA, VT, Expand);
833 setOperationAction(ISD::FPOWI, VT, Expand);
834 setOperationAction(ISD::FSQRT, VT, Expand);
835 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
836 setOperationAction(ISD::FFLOOR, VT, Expand);
837 setOperationAction(ISD::FCEIL, VT, Expand);
838 setOperationAction(ISD::FTRUNC, VT, Expand);
839 setOperationAction(ISD::FRINT, VT, Expand);
840 setOperationAction(ISD::FNEARBYINT, VT, Expand);
841 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
842 setOperationAction(ISD::MULHS, VT, Expand);
843 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
844 setOperationAction(ISD::MULHU, VT, Expand);
845 setOperationAction(ISD::SDIVREM, VT, Expand);
846 setOperationAction(ISD::UDIVREM, VT, Expand);
847 setOperationAction(ISD::FPOW, VT, Expand);
848 setOperationAction(ISD::CTPOP, VT, Expand);
849 setOperationAction(ISD::CTTZ, VT, Expand);
850 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
851 setOperationAction(ISD::CTLZ, VT, Expand);
852 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
853 setOperationAction(ISD::SHL, VT, Expand);
854 setOperationAction(ISD::SRA, VT, Expand);
855 setOperationAction(ISD::SRL, VT, Expand);
856 setOperationAction(ISD::ROTL, VT, Expand);
857 setOperationAction(ISD::ROTR, VT, Expand);
858 setOperationAction(ISD::BSWAP, VT, Expand);
859 setOperationAction(ISD::SETCC, VT, Expand);
860 setOperationAction(ISD::FLOG, VT, Expand);
861 setOperationAction(ISD::FLOG2, VT, Expand);
862 setOperationAction(ISD::FLOG10, VT, Expand);
863 setOperationAction(ISD::FEXP, VT, Expand);
864 setOperationAction(ISD::FEXP2, VT, Expand);
865 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
866 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
867 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
869 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
870 setOperationAction(ISD::TRUNCATE, VT, Expand);
871 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
872 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
873 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
874 setOperationAction(ISD::VSELECT, VT, Expand);
875 setOperationAction(ISD::SELECT_CC, VT, Expand);
876 for (MVT InnerVT : MVT::vector_valuetypes()) {
877 setTruncStoreAction(InnerVT, VT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
890 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
891 // with -msoft-float, disable use of MMX as well.
892 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
893 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
894 // No operations on x86mmx supported, everything uses intrinsics.
897 // MMX-sized vectors (other than x86mmx) are expected to be expanded
898 // into smaller operations.
899 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
900 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
901 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
902 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
903 setOperationAction(ISD::AND, MVT::v8i8, Expand);
904 setOperationAction(ISD::AND, MVT::v4i16, Expand);
905 setOperationAction(ISD::AND, MVT::v2i32, Expand);
906 setOperationAction(ISD::AND, MVT::v1i64, Expand);
907 setOperationAction(ISD::OR, MVT::v8i8, Expand);
908 setOperationAction(ISD::OR, MVT::v4i16, Expand);
909 setOperationAction(ISD::OR, MVT::v2i32, Expand);
910 setOperationAction(ISD::OR, MVT::v1i64, Expand);
911 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
912 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
913 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
914 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
920 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
921 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
922 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
923 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
930 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
932 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
933 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
934 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
935 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
936 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
937 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
938 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
939 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
940 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
941 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
942 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
943 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
944 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
947 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
948 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
950 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
951 // registers cannot be used even for integer operations.
952 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
953 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
954 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
955 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
957 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
958 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
959 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
960 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
961 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
962 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
963 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
965 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
966 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
967 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
968 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
969 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
970 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
971 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
972 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
973 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
974 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
975 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
976 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
977 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
978 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
981 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
982 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
983 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
986 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
991 // Only provide customized ctpop vector bit twiddling for vector types we
992 // know to perform better than using the popcnt instructions on each vector
993 // element. If popcnt isn't supported, always provide the custom version.
994 if (!Subtarget->hasPOPCNT()) {
995 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
996 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
999 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1000 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1001 MVT VT = (MVT::SimpleValueType)i;
1002 // Do not attempt to custom lower non-power-of-2 vectors
1003 if (!isPowerOf2_32(VT.getVectorNumElements()))
1005 // Do not attempt to custom lower non-128-bit vectors
1006 if (!VT.is128BitVector())
1008 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1009 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1013 // We support custom legalizing of sext and anyext loads for specific
1014 // memory vector types which we can load as a scalar (or sequence of
1015 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1016 // loads these must work with a single scalar load.
1017 for (MVT VT : MVT::integer_vector_valuetypes()) {
1018 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
1029 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1031 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1033 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1034 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1036 if (Subtarget->is64Bit()) {
1037 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1042 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1043 MVT VT = (MVT::SimpleValueType)i;
1045 // Do not attempt to promote non-128-bit vectors
1046 if (!VT.is128BitVector())
1049 setOperationAction(ISD::AND, VT, Promote);
1050 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1051 setOperationAction(ISD::OR, VT, Promote);
1052 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1053 setOperationAction(ISD::XOR, VT, Promote);
1054 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1055 setOperationAction(ISD::LOAD, VT, Promote);
1056 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1057 setOperationAction(ISD::SELECT, VT, Promote);
1058 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 // Custom lower v2i64 and v2f64 selects.
1062 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1064 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1067 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1068 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1070 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1071 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1072 // As there is no 64-bit GPR available, we need build a special custom
1073 // sequence to convert from v2i32 to v2f32.
1074 if (!Subtarget->is64Bit())
1075 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1077 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1078 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1080 for (MVT VT : MVT::fp_vector_valuetypes())
1081 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
1083 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1084 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1088 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1089 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1090 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1091 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1092 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1093 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1095 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1096 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1097 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1098 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1100 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1106 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1111 // FIXME: Do we need to handle scalar-to-vector here?
1112 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1114 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1115 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1119 // There is no BLENDI for byte vectors. We don't need to custom lower
1120 // some vselects for now.
1121 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1123 // SSE41 brings specific instructions for doing vector sign extend even in
1124 // cases where we don't have SRA.
1125 for (MVT VT : MVT::integer_vector_valuetypes()) {
1126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
1131 // i8 and i16 vectors are custom because the source register and source
1132 // source memory operand types are not the same width. f32 vectors are
1133 // custom since the immediate controlling the insert encodes additional
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1145 // FIXME: these should be Legal, but that's only for the case where
1146 // the index is constant. For now custom expand to deal with that.
1147 if (Subtarget->is64Bit()) {
1148 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1153 if (Subtarget->hasSSE2()) {
1154 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1157 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1158 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1160 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1161 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1163 // In the customized shift lowering, the legal cases in AVX2 will be
1165 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1166 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1168 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1169 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1171 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1174 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1175 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1180 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1182 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1184 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1186 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1197 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1199 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1210 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1212 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1213 // even though v8i16 is a legal type.
1214 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1216 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1219 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1220 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1223 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1225 for (MVT VT : MVT::fp_vector_valuetypes())
1226 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1228 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1234 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1235 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1239 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1243 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1244 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1248 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1249 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1253 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1255 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1256 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1258 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1259 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1261 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1262 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1264 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1265 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1269 setOperationAction(ISD::FMA, MVT::f32, Legal);
1270 setOperationAction(ISD::FMA, MVT::f64, Legal);
1273 if (Subtarget->hasInt256()) {
1274 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1275 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1276 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1277 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1279 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1280 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1281 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1282 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1284 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1285 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1286 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1287 // Don't lower v32i8 because there is no 128-bit byte mul
1289 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1290 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1291 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1292 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1294 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1295 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1297 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1298 // when we have a 256bit-wide blend with immediate.
1299 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1301 // Only provide customized ctpop vector bit twiddling for vector types we
1302 // know to perform better than using the popcnt instructions on each
1303 // vector element. If popcnt isn't supported, always provide the custom
1305 if (!Subtarget->hasPOPCNT())
1306 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1308 // Custom CTPOP always performs better on natively supported v8i32
1309 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1311 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1312 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1313 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1314 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1316 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1318 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1319 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1321 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1322 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1323 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1324 // Don't lower v32i8 because there is no 128-bit byte mul
1327 // In the customized shift lowering, the legal cases in AVX2 will be
1329 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1330 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1332 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1333 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1335 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1337 // Custom lower several nodes for 256-bit types.
1338 for (MVT VT : MVT::vector_valuetypes()) {
1339 if (VT.getScalarSizeInBits() >= 32) {
1340 setOperationAction(ISD::MLOAD, VT, Legal);
1341 setOperationAction(ISD::MSTORE, VT, Legal);
1343 // Extract subvector is special because the value type
1344 // (result) is 128-bit but the source is 256-bit wide.
1345 if (VT.is128BitVector()) {
1346 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1348 // Do not attempt to custom lower other non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1353 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1354 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1355 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1356 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1357 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1361 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1362 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1363 MVT VT = (MVT::SimpleValueType)i;
1365 // Do not attempt to promote non-256-bit vectors
1366 if (!VT.is256BitVector())
1369 setOperationAction(ISD::AND, VT, Promote);
1370 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1371 setOperationAction(ISD::OR, VT, Promote);
1372 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1373 setOperationAction(ISD::XOR, VT, Promote);
1374 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1375 setOperationAction(ISD::LOAD, VT, Promote);
1376 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1377 setOperationAction(ISD::SELECT, VT, Promote);
1378 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1382 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1383 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1384 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1385 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1386 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1388 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1389 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1390 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1392 for (MVT VT : MVT::fp_vector_valuetypes())
1393 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1395 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1396 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1397 setOperationAction(ISD::XOR, MVT::i1, Legal);
1398 setOperationAction(ISD::OR, MVT::i1, Legal);
1399 setOperationAction(ISD::AND, MVT::i1, Legal);
1400 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1401 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1402 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1403 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1404 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1406 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1407 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1408 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1409 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1410 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1411 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1413 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1414 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1415 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1416 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1417 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1418 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1419 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1420 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1423 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1426 if (Subtarget->is64Bit()) {
1427 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1428 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1429 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1430 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1432 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1433 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1434 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1435 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1436 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1438 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1439 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1440 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1441 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1442 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1443 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1444 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1445 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1447 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1448 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1449 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1450 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1451 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1452 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1453 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1454 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1455 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1456 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1458 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1459 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1461 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1462 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1463 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1464 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1465 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1466 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1468 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1469 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1471 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1473 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1474 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1475 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1477 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1478 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1479 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1480 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1481 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1483 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1484 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1486 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1487 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1489 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1491 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1494 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1495 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1497 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1498 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1500 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1501 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1502 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1503 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1504 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1505 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1507 if (Subtarget->hasCDI()) {
1508 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1509 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1512 // Custom lower several nodes.
1513 for (MVT VT : MVT::vector_valuetypes()) {
1514 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1515 // Extract subvector is special because the value type
1516 // (result) is 256/128-bit but the source is 512-bit wide.
1517 if (VT.is128BitVector() || VT.is256BitVector()) {
1518 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1520 if (VT.getVectorElementType() == MVT::i1)
1521 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1523 // Do not attempt to custom lower other non-512-bit vectors
1524 if (!VT.is512BitVector())
1527 if ( EltSize >= 32) {
1528 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1529 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1530 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1531 setOperationAction(ISD::VSELECT, VT, Legal);
1532 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1533 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1534 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1535 setOperationAction(ISD::MLOAD, VT, Legal);
1536 setOperationAction(ISD::MSTORE, VT, Legal);
1539 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1540 MVT VT = (MVT::SimpleValueType)i;
1542 // Do not attempt to promote non-512-bit vectors.
1543 if (!VT.is512BitVector())
1546 setOperationAction(ISD::SELECT, VT, Promote);
1547 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1551 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1552 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1553 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1555 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1556 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1558 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1559 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1560 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1562 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1563 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1564 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1565 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1566 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1568 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1569 const MVT VT = (MVT::SimpleValueType)i;
1571 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1573 // Do not attempt to promote non-512-bit vectors.
1574 if (!VT.is512BitVector())
1578 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1579 setOperationAction(ISD::VSELECT, VT, Legal);
1584 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1585 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1586 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1588 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1589 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1590 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1592 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1593 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1594 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1595 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1596 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1597 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1600 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1601 // of this type with custom code.
1602 for (MVT VT : MVT::vector_valuetypes())
1603 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
1605 // We want to custom lower some of our intrinsics.
1606 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1607 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1608 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1609 if (!Subtarget->is64Bit())
1610 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1612 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1613 // handle type legalization for these operations here.
1615 // FIXME: We really should do custom legalization for addition and
1616 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1617 // than generic legalization for 64-bit multiplication-with-overflow, though.
1618 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1619 // Add/Sub/Mul with overflow operations are custom lowered.
1621 setOperationAction(ISD::SADDO, VT, Custom);
1622 setOperationAction(ISD::UADDO, VT, Custom);
1623 setOperationAction(ISD::SSUBO, VT, Custom);
1624 setOperationAction(ISD::USUBO, VT, Custom);
1625 setOperationAction(ISD::SMULO, VT, Custom);
1626 setOperationAction(ISD::UMULO, VT, Custom);
1630 if (!Subtarget->is64Bit()) {
1631 // These libcalls are not available in 32-bit.
1632 setLibcallName(RTLIB::SHL_I128, nullptr);
1633 setLibcallName(RTLIB::SRL_I128, nullptr);
1634 setLibcallName(RTLIB::SRA_I128, nullptr);
1637 // Combine sin / cos into one node or libcall if possible.
1638 if (Subtarget->hasSinCos()) {
1639 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1640 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1641 if (Subtarget->isTargetDarwin()) {
1642 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1643 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1644 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1645 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1649 if (Subtarget->isTargetWin64()) {
1650 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1651 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1652 setOperationAction(ISD::SREM, MVT::i128, Custom);
1653 setOperationAction(ISD::UREM, MVT::i128, Custom);
1654 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1655 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1658 // We have target-specific dag combine patterns for the following nodes:
1659 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1660 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1661 setTargetDAGCombine(ISD::VSELECT);
1662 setTargetDAGCombine(ISD::SELECT);
1663 setTargetDAGCombine(ISD::SHL);
1664 setTargetDAGCombine(ISD::SRA);
1665 setTargetDAGCombine(ISD::SRL);
1666 setTargetDAGCombine(ISD::OR);
1667 setTargetDAGCombine(ISD::AND);
1668 setTargetDAGCombine(ISD::ADD);
1669 setTargetDAGCombine(ISD::FADD);
1670 setTargetDAGCombine(ISD::FSUB);
1671 setTargetDAGCombine(ISD::FMA);
1672 setTargetDAGCombine(ISD::SUB);
1673 setTargetDAGCombine(ISD::LOAD);
1674 setTargetDAGCombine(ISD::STORE);
1675 setTargetDAGCombine(ISD::ZERO_EXTEND);
1676 setTargetDAGCombine(ISD::ANY_EXTEND);
1677 setTargetDAGCombine(ISD::SIGN_EXTEND);
1678 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1679 setTargetDAGCombine(ISD::TRUNCATE);
1680 setTargetDAGCombine(ISD::SINT_TO_FP);
1681 setTargetDAGCombine(ISD::SETCC);
1682 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1683 setTargetDAGCombine(ISD::BUILD_VECTOR);
1684 if (Subtarget->is64Bit())
1685 setTargetDAGCombine(ISD::MUL);
1686 setTargetDAGCombine(ISD::XOR);
1688 computeRegisterProperties();
1690 // On Darwin, -Os means optimize for size without hurting performance,
1691 // do not reduce the limit.
1692 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1693 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1694 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1695 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1696 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1697 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1698 setPrefLoopAlignment(4); // 2^4 bytes.
1700 // Predictable cmov don't hurt on atom because it's in-order.
1701 PredictableSelectIsExpensive = !Subtarget->isAtom();
1702 EnableExtLdPromotion = true;
1703 setPrefFunctionAlignment(4); // 2^4 bytes.
1705 verifyIntrinsicTables();
1708 // This has so far only been implemented for 64-bit MachO.
1709 bool X86TargetLowering::useLoadStackGuardNode() const {
1710 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1713 TargetLoweringBase::LegalizeTypeAction
1714 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1715 if (ExperimentalVectorWideningLegalization &&
1716 VT.getVectorNumElements() != 1 &&
1717 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1718 return TypeWidenVector;
1720 return TargetLoweringBase::getPreferredVectorAction(VT);
1723 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1725 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1727 const unsigned NumElts = VT.getVectorNumElements();
1728 const EVT EltVT = VT.getVectorElementType();
1729 if (VT.is512BitVector()) {
1730 if (Subtarget->hasAVX512())
1731 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1732 EltVT == MVT::f32 || EltVT == MVT::f64)
1734 case 8: return MVT::v8i1;
1735 case 16: return MVT::v16i1;
1737 if (Subtarget->hasBWI())
1738 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1740 case 32: return MVT::v32i1;
1741 case 64: return MVT::v64i1;
1745 if (VT.is256BitVector() || VT.is128BitVector()) {
1746 if (Subtarget->hasVLX())
1747 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1748 EltVT == MVT::f32 || EltVT == MVT::f64)
1750 case 2: return MVT::v2i1;
1751 case 4: return MVT::v4i1;
1752 case 8: return MVT::v8i1;
1754 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1755 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1757 case 8: return MVT::v8i1;
1758 case 16: return MVT::v16i1;
1759 case 32: return MVT::v32i1;
1763 return VT.changeVectorElementTypeToInteger();
1766 /// Helper for getByValTypeAlignment to determine
1767 /// the desired ByVal argument alignment.
1768 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1771 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1772 if (VTy->getBitWidth() == 128)
1774 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1775 unsigned EltAlign = 0;
1776 getMaxByValAlign(ATy->getElementType(), EltAlign);
1777 if (EltAlign > MaxAlign)
1778 MaxAlign = EltAlign;
1779 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1780 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1781 unsigned EltAlign = 0;
1782 getMaxByValAlign(STy->getElementType(i), EltAlign);
1783 if (EltAlign > MaxAlign)
1784 MaxAlign = EltAlign;
1791 /// Return the desired alignment for ByVal aggregate
1792 /// function arguments in the caller parameter area. For X86, aggregates
1793 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1794 /// are at 4-byte boundaries.
1795 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1796 if (Subtarget->is64Bit()) {
1797 // Max of 8 and alignment of type.
1798 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1805 if (Subtarget->hasSSE1())
1806 getMaxByValAlign(Ty, Align);
1810 /// Returns the target specific optimal type for load
1811 /// and store operations as a result of memset, memcpy, and memmove
1812 /// lowering. If DstAlign is zero that means it's safe to destination
1813 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1814 /// means there isn't a need to check it against alignment requirement,
1815 /// probably because the source does not need to be loaded. If 'IsMemset' is
1816 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1817 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1818 /// source is constant so it does not need to be loaded.
1819 /// It returns EVT::Other if the type should be determined using generic
1820 /// target-independent logic.
1822 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1823 unsigned DstAlign, unsigned SrcAlign,
1824 bool IsMemset, bool ZeroMemset,
1826 MachineFunction &MF) const {
1827 const Function *F = MF.getFunction();
1828 if ((!IsMemset || ZeroMemset) &&
1829 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1830 Attribute::NoImplicitFloat)) {
1832 (Subtarget->isUnalignedMemAccessFast() ||
1833 ((DstAlign == 0 || DstAlign >= 16) &&
1834 (SrcAlign == 0 || SrcAlign >= 16)))) {
1836 if (Subtarget->hasInt256())
1838 if (Subtarget->hasFp256())
1841 if (Subtarget->hasSSE2())
1843 if (Subtarget->hasSSE1())
1845 } else if (!MemcpyStrSrc && Size >= 8 &&
1846 !Subtarget->is64Bit() &&
1847 Subtarget->hasSSE2()) {
1848 // Do not use f64 to lower memcpy if source is string constant. It's
1849 // better to use i32 to avoid the loads.
1853 if (Subtarget->is64Bit() && Size >= 8)
1858 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1860 return X86ScalarSSEf32;
1861 else if (VT == MVT::f64)
1862 return X86ScalarSSEf64;
1867 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1872 *Fast = Subtarget->isUnalignedMemAccessFast();
1876 /// Return the entry encoding for a jump table in the
1877 /// current function. The returned value is a member of the
1878 /// MachineJumpTableInfo::JTEntryKind enum.
1879 unsigned X86TargetLowering::getJumpTableEncoding() const {
1880 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1882 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1883 Subtarget->isPICStyleGOT())
1884 return MachineJumpTableInfo::EK_Custom32;
1886 // Otherwise, use the normal jump table encoding heuristics.
1887 return TargetLowering::getJumpTableEncoding();
1891 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1892 const MachineBasicBlock *MBB,
1893 unsigned uid,MCContext &Ctx) const{
1894 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1895 Subtarget->isPICStyleGOT());
1896 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1898 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1899 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1902 /// Returns relocation base for the given PIC jumptable.
1903 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1904 SelectionDAG &DAG) const {
1905 if (!Subtarget->is64Bit())
1906 // This doesn't have SDLoc associated with it, but is not really the
1907 // same as a Register.
1908 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1912 /// This returns the relocation base for the given PIC jumptable,
1913 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1914 const MCExpr *X86TargetLowering::
1915 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1916 MCContext &Ctx) const {
1917 // X86-64 uses RIP relative addressing based on the jump table label.
1918 if (Subtarget->isPICStyleRIPRel())
1919 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1921 // Otherwise, the reference is relative to the PIC base.
1922 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1925 // FIXME: Why this routine is here? Move to RegInfo!
1926 std::pair<const TargetRegisterClass*, uint8_t>
1927 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1928 const TargetRegisterClass *RRC = nullptr;
1930 switch (VT.SimpleTy) {
1932 return TargetLowering::findRepresentativeClass(VT);
1933 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1934 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1937 RRC = &X86::VR64RegClass;
1939 case MVT::f32: case MVT::f64:
1940 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1941 case MVT::v4f32: case MVT::v2f64:
1942 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1944 RRC = &X86::VR128RegClass;
1947 return std::make_pair(RRC, Cost);
1950 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1951 unsigned &Offset) const {
1952 if (!Subtarget->isTargetLinux())
1955 if (Subtarget->is64Bit()) {
1956 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1958 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1970 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1971 unsigned DestAS) const {
1972 assert(SrcAS != DestAS && "Expected different address spaces!");
1974 return SrcAS < 256 && DestAS < 256;
1977 //===----------------------------------------------------------------------===//
1978 // Return Value Calling Convention Implementation
1979 //===----------------------------------------------------------------------===//
1981 #include "X86GenCallingConv.inc"
1984 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1985 MachineFunction &MF, bool isVarArg,
1986 const SmallVectorImpl<ISD::OutputArg> &Outs,
1987 LLVMContext &Context) const {
1988 SmallVector<CCValAssign, 16> RVLocs;
1989 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1990 return CCInfo.CheckReturn(Outs, RetCC_X86);
1993 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1994 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1999 X86TargetLowering::LowerReturn(SDValue Chain,
2000 CallingConv::ID CallConv, bool isVarArg,
2001 const SmallVectorImpl<ISD::OutputArg> &Outs,
2002 const SmallVectorImpl<SDValue> &OutVals,
2003 SDLoc dl, SelectionDAG &DAG) const {
2004 MachineFunction &MF = DAG.getMachineFunction();
2005 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2007 SmallVector<CCValAssign, 16> RVLocs;
2008 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2009 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2012 SmallVector<SDValue, 6> RetOps;
2013 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2014 // Operand #1 = Bytes To Pop
2015 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2018 // Copy the result values into the output registers.
2019 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2020 CCValAssign &VA = RVLocs[i];
2021 assert(VA.isRegLoc() && "Can only return in registers!");
2022 SDValue ValToCopy = OutVals[i];
2023 EVT ValVT = ValToCopy.getValueType();
2025 // Promote values to the appropriate types.
2026 if (VA.getLocInfo() == CCValAssign::SExt)
2027 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 else if (VA.getLocInfo() == CCValAssign::ZExt)
2029 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 else if (VA.getLocInfo() == CCValAssign::AExt)
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2032 else if (VA.getLocInfo() == CCValAssign::BCvt)
2033 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2035 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2036 "Unexpected FP-extend for return value.");
2038 // If this is x86-64, and we disabled SSE, we can't return FP values,
2039 // or SSE or MMX vectors.
2040 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2041 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2042 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2043 report_fatal_error("SSE register return with SSE disabled");
2045 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2046 // llvm-gcc has never done it right and no one has noticed, so this
2047 // should be OK for now.
2048 if (ValVT == MVT::f64 &&
2049 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2050 report_fatal_error("SSE2 register return with SSE2 disabled");
2052 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2053 // the RET instruction and handled by the FP Stackifier.
2054 if (VA.getLocReg() == X86::FP0 ||
2055 VA.getLocReg() == X86::FP1) {
2056 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2057 // change the value to the FP stack register class.
2058 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2059 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2060 RetOps.push_back(ValToCopy);
2061 // Don't emit a copytoreg.
2065 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2066 // which is returned in RAX / RDX.
2067 if (Subtarget->is64Bit()) {
2068 if (ValVT == MVT::x86mmx) {
2069 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2070 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2071 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2073 // If we don't have SSE2 available, convert to v4f32 so the generated
2074 // register is legal.
2075 if (!Subtarget->hasSSE2())
2076 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2082 Flag = Chain.getValue(1);
2083 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2086 // The x86-64 ABIs require that for returning structs by value we copy
2087 // the sret argument into %rax/%eax (depending on ABI) for the return.
2088 // Win32 requires us to put the sret argument to %eax as well.
2089 // We saved the argument into a virtual register in the entry block,
2090 // so now we copy the value out and into %rax/%eax.
2091 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2092 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2093 MachineFunction &MF = DAG.getMachineFunction();
2094 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2095 unsigned Reg = FuncInfo->getSRetReturnReg();
2097 "SRetReturnReg should have been set in LowerFormalArguments().");
2098 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2101 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2102 X86::RAX : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2104 Flag = Chain.getValue(1);
2106 // RAX/EAX now acts like a return value.
2107 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2110 RetOps[0] = Chain; // Update chain.
2112 // Add the flag if we have it.
2114 RetOps.push_back(Flag);
2116 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2119 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2120 if (N->getNumValues() != 1)
2122 if (!N->hasNUsesOfValue(1, 0))
2125 SDValue TCChain = Chain;
2126 SDNode *Copy = *N->use_begin();
2127 if (Copy->getOpcode() == ISD::CopyToReg) {
2128 // If the copy has a glue operand, we conservatively assume it isn't safe to
2129 // perform a tail call.
2130 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2132 TCChain = Copy->getOperand(0);
2133 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2136 bool HasRet = false;
2137 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2139 if (UI->getOpcode() != X86ISD::RET_FLAG)
2141 // If we are returning more than one value, we can definitely
2142 // not make a tail call see PR19530
2143 if (UI->getNumOperands() > 4)
2145 if (UI->getNumOperands() == 4 &&
2146 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2159 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2160 ISD::NodeType ExtendKind) const {
2162 // TODO: Is this also valid on 32-bit?
2163 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2164 ReturnMVT = MVT::i8;
2166 ReturnMVT = MVT::i32;
2168 EVT MinVT = getRegisterType(Context, ReturnMVT);
2169 return VT.bitsLT(MinVT) ? MinVT : VT;
2172 /// Lower the result values of a call into the
2173 /// appropriate copies out of appropriate physical registers.
2176 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::InputArg> &Ins,
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2182 // Assign locations to each value returned by this call.
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 bool Is64Bit = Subtarget->is64Bit();
2185 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2189 // Copy all of the result registers out of their specified physreg.
2190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2191 CCValAssign &VA = RVLocs[i];
2192 EVT CopyVT = VA.getValVT();
2194 // If this is x86-64, and we disabled SSE, we can't return FP values
2195 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2196 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2197 report_fatal_error("SSE register return with SSE disabled");
2200 // If we prefer to use the value in xmm registers, copy it out as f80 and
2201 // use a truncate to move it from fp stack reg to xmm reg.
2202 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2203 isScalarFPTypeInSSEReg(VA.getValVT()))
2206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2207 CopyVT, InFlag).getValue(1);
2208 SDValue Val = Chain.getValue(0);
2210 if (CopyVT != VA.getValVT())
2211 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2212 // This truncation won't change the value.
2213 DAG.getIntPtrConstant(1));
2215 InFlag = Chain.getValue(2);
2216 InVals.push_back(Val);
2222 //===----------------------------------------------------------------------===//
2223 // C & StdCall & Fast Calling Convention implementation
2224 //===----------------------------------------------------------------------===//
2225 // StdCall calling convention seems to be standard for many Windows' API
2226 // routines and around. It differs from C calling convention just a little:
2227 // callee should clean up the stack, not caller. Symbols should be also
2228 // decorated in some fancy way :) It doesn't support any vector arguments.
2229 // For info on fast calling convention see Fast Calling Convention (tail call)
2230 // implementation LowerX86_32FastCCCallTo.
2232 /// CallIsStructReturn - Determines whether a call uses struct return
2234 enum StructReturnType {
2239 static StructReturnType
2240 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2242 return NotStructReturn;
2244 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2245 if (!Flags.isSRet())
2246 return NotStructReturn;
2247 if (Flags.isInReg())
2248 return RegStructReturn;
2249 return StackStructReturn;
2252 /// Determines whether a function uses struct return semantics.
2253 static StructReturnType
2254 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2256 return NotStructReturn;
2258 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2259 if (!Flags.isSRet())
2260 return NotStructReturn;
2261 if (Flags.isInReg())
2262 return RegStructReturn;
2263 return StackStructReturn;
2266 /// Make a copy of an aggregate at address specified by "Src" to address
2267 /// "Dst" with size and alignment information specified by the specific
2268 /// parameter attribute. The copy will be passed as a byval function parameter.
2270 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2271 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2273 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2275 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2276 /*isVolatile*/false, /*AlwaysInline=*/true,
2277 MachinePointerInfo(), MachinePointerInfo());
2280 /// Return true if the calling convention is one that
2281 /// supports tail call optimization.
2282 static bool IsTailCallConvention(CallingConv::ID CC) {
2283 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2284 CC == CallingConv::HiPE);
2287 /// \brief Return true if the calling convention is a C calling convention.
2288 static bool IsCCallConvention(CallingConv::ID CC) {
2289 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2290 CC == CallingConv::X86_64_SysV);
2293 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2294 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2298 CallingConv::ID CalleeCC = CS.getCallingConv();
2299 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2305 /// Return true if the function is being made into
2306 /// a tailcall target by changing its ABI.
2307 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2308 bool GuaranteedTailCallOpt) {
2309 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2313 X86TargetLowering::LowerMemArgument(SDValue Chain,
2314 CallingConv::ID CallConv,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 const CCValAssign &VA,
2318 MachineFrameInfo *MFI,
2320 // Create the nodes corresponding to a load from this parameter slot.
2321 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2322 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2323 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2324 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2327 // If value is passed by pointer we have address passed instead of the value
2329 if (VA.getLocInfo() == CCValAssign::Indirect)
2330 ValVT = VA.getLocVT();
2332 ValVT = VA.getValVT();
2334 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2335 // changed with more analysis.
2336 // In case of tail call optimization mark all arguments mutable. Since they
2337 // could be overwritten by lowering of arguments in case of a tail call.
2338 if (Flags.isByVal()) {
2339 unsigned Bytes = Flags.getByValSize();
2340 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2341 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2342 return DAG.getFrameIndex(FI, getPointerTy());
2344 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2345 VA.getLocMemOffset(), isImmutable);
2346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2347 return DAG.getLoad(ValVT, dl, Chain, FIN,
2348 MachinePointerInfo::getFixedStack(FI),
2349 false, false, false, 0);
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2355 const X86Subtarget *Subtarget) {
2356 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 static const MCPhysReg GPR64ArgRegsWin64[] = {
2360 X86::RCX, X86::RDX, X86::R8, X86::R9
2362 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2365 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2366 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2368 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2371 // FIXME: Get this from tablegen.
2372 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2373 CallingConv::ID CallConv,
2374 const X86Subtarget *Subtarget) {
2375 assert(Subtarget->is64Bit());
2376 if (Subtarget->isCallingConvWin64(CallConv)) {
2377 // The XMM registers which might contain var arg parameters are shadowed
2378 // in their paired GPR. So we only need to save the GPR to their home
2380 // TODO: __vectorcall will change this.
2384 const Function *Fn = MF.getFunction();
2385 bool NoImplicitFloatOps = Fn->getAttributes().
2386 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2387 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2388 "SSE register cannot be used when SSE is disabled!");
2389 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2390 !Subtarget->hasSSE1())
2391 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2395 static const MCPhysReg XMMArgRegs64Bit[] = {
2396 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2397 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2399 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2403 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2404 CallingConv::ID CallConv,
2406 const SmallVectorImpl<ISD::InputArg> &Ins,
2409 SmallVectorImpl<SDValue> &InVals)
2411 MachineFunction &MF = DAG.getMachineFunction();
2412 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2414 const Function* Fn = MF.getFunction();
2415 if (Fn->hasExternalLinkage() &&
2416 Subtarget->isTargetCygMing() &&
2417 Fn->getName() == "main")
2418 FuncInfo->setForceFramePointer(true);
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 bool Is64Bit = Subtarget->is64Bit();
2422 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2424 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2425 "Var args not supported with calling convention fastcc, ghc or hipe");
2427 // Assign locations to all of the incoming arguments.
2428 SmallVector<CCValAssign, 16> ArgLocs;
2429 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2431 // Allocate shadow area for Win64
2433 CCInfo.AllocateStack(32, 8);
2435 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2437 unsigned LastVal = ~0U;
2439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2440 CCValAssign &VA = ArgLocs[i];
2441 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2443 assert(VA.getValNo() != LastVal &&
2444 "Don't support value assigned to multiple locs yet");
2446 LastVal = VA.getValNo();
2448 if (VA.isRegLoc()) {
2449 EVT RegVT = VA.getLocVT();
2450 const TargetRegisterClass *RC;
2451 if (RegVT == MVT::i32)
2452 RC = &X86::GR32RegClass;
2453 else if (Is64Bit && RegVT == MVT::i64)
2454 RC = &X86::GR64RegClass;
2455 else if (RegVT == MVT::f32)
2456 RC = &X86::FR32RegClass;
2457 else if (RegVT == MVT::f64)
2458 RC = &X86::FR64RegClass;
2459 else if (RegVT.is512BitVector())
2460 RC = &X86::VR512RegClass;
2461 else if (RegVT.is256BitVector())
2462 RC = &X86::VR256RegClass;
2463 else if (RegVT.is128BitVector())
2464 RC = &X86::VR128RegClass;
2465 else if (RegVT == MVT::x86mmx)
2466 RC = &X86::VR64RegClass;
2467 else if (RegVT == MVT::i1)
2468 RC = &X86::VK1RegClass;
2469 else if (RegVT == MVT::v8i1)
2470 RC = &X86::VK8RegClass;
2471 else if (RegVT == MVT::v16i1)
2472 RC = &X86::VK16RegClass;
2473 else if (RegVT == MVT::v32i1)
2474 RC = &X86::VK32RegClass;
2475 else if (RegVT == MVT::v64i1)
2476 RC = &X86::VK64RegClass;
2478 llvm_unreachable("Unknown argument type!");
2480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2483 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2484 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2486 if (VA.getLocInfo() == CCValAssign::SExt)
2487 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2488 DAG.getValueType(VA.getValVT()));
2489 else if (VA.getLocInfo() == CCValAssign::ZExt)
2490 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2491 DAG.getValueType(VA.getValVT()));
2492 else if (VA.getLocInfo() == CCValAssign::BCvt)
2493 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2495 if (VA.isExtInLoc()) {
2496 // Handle MMX values passed in XMM regs.
2497 if (RegVT.isVector())
2498 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2500 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2503 assert(VA.isMemLoc());
2504 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2507 // If value is passed via pointer - do a load.
2508 if (VA.getLocInfo() == CCValAssign::Indirect)
2509 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2510 MachinePointerInfo(), false, false, false, 0);
2512 InVals.push_back(ArgValue);
2515 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2517 // The x86-64 ABIs require that for returning structs by value we copy
2518 // the sret argument into %rax/%eax (depending on ABI) for the return.
2519 // Win32 requires us to put the sret argument to %eax as well.
2520 // Save the argument into a virtual register so that we can access it
2521 // from the return points.
2522 if (Ins[i].Flags.isSRet()) {
2523 unsigned Reg = FuncInfo->getSRetReturnReg();
2525 MVT PtrTy = getPointerTy();
2526 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2527 FuncInfo->setSRetReturnReg(Reg);
2529 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2530 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2536 unsigned StackSize = CCInfo.getNextStackOffset();
2537 // Align stack specially for tail calls.
2538 if (FuncIsMadeTailCallSafe(CallConv,
2539 MF.getTarget().Options.GuaranteedTailCallOpt))
2540 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2542 // If the function takes variable number of arguments, make a frame index for
2543 // the start of the first vararg value... for expansion of llvm.va_start. We
2544 // can skip this if there are no va_start calls.
2545 if (MFI->hasVAStart() &&
2546 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2547 CallConv != CallingConv::X86_ThisCall))) {
2548 FuncInfo->setVarArgsFrameIndex(
2549 MFI->CreateFixedObject(1, StackSize, true));
2552 // Figure out if XMM registers are in use.
2553 assert(!(MF.getTarget().Options.UseSoftFloat &&
2554 Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2555 Attribute::NoImplicitFloat)) &&
2556 "SSE register cannot be used when SSE is disabled!");
2558 // 64-bit calling conventions support varargs and register parameters, so we
2559 // have to do extra work to spill them in the prologue.
2560 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2561 // Find the first unallocated argument registers.
2562 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2563 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2564 unsigned NumIntRegs =
2565 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2566 unsigned NumXMMRegs =
2567 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2568 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2569 "SSE register cannot be used when SSE is disabled!");
2571 // Gather all the live in physical registers.
2572 SmallVector<SDValue, 6> LiveGPRs;
2573 SmallVector<SDValue, 8> LiveXMMRegs;
2575 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2576 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2578 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2580 if (!ArgXMMs.empty()) {
2581 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2582 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2583 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2584 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2585 LiveXMMRegs.push_back(
2586 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2591 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2592 // Get to the caller-allocated home save location. Add 8 to account
2593 // for the return address.
2594 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2595 FuncInfo->setRegSaveFrameIndex(
2596 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2597 // Fixup to set vararg frame on shadow area (4 x i64).
2599 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2601 // For X86-64, if there are vararg parameters that are passed via
2602 // registers, then we must store them to their spots on the stack so
2603 // they may be loaded by deferencing the result of va_next.
2604 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2605 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2606 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2607 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2610 // Store the integer parameter registers.
2611 SmallVector<SDValue, 8> MemOps;
2612 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2614 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2615 for (SDValue Val : LiveGPRs) {
2616 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2617 DAG.getIntPtrConstant(Offset));
2619 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2620 MachinePointerInfo::getFixedStack(
2621 FuncInfo->getRegSaveFrameIndex(), Offset),
2623 MemOps.push_back(Store);
2627 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2628 // Now store the XMM (fp + vector) parameter registers.
2629 SmallVector<SDValue, 12> SaveXMMOps;
2630 SaveXMMOps.push_back(Chain);
2631 SaveXMMOps.push_back(ALVal);
2632 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2633 FuncInfo->getRegSaveFrameIndex()));
2634 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2635 FuncInfo->getVarArgsFPOffset()));
2636 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2638 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2639 MVT::Other, SaveXMMOps));
2642 if (!MemOps.empty())
2643 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2646 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2647 // Find the largest legal vector type.
2648 MVT VecVT = MVT::Other;
2649 // FIXME: Only some x86_32 calling conventions support AVX512.
2650 if (Subtarget->hasAVX512() &&
2651 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2652 CallConv == CallingConv::Intel_OCL_BI)))
2653 VecVT = MVT::v16f32;
2654 else if (Subtarget->hasAVX())
2656 else if (Subtarget->hasSSE2())
2659 // We forward some GPRs and some vector types.
2660 SmallVector<MVT, 2> RegParmTypes;
2661 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2662 RegParmTypes.push_back(IntVT);
2663 if (VecVT != MVT::Other)
2664 RegParmTypes.push_back(VecVT);
2666 // Compute the set of forwarded registers. The rest are scratch.
2667 SmallVectorImpl<ForwardedRegister> &Forwards =
2668 FuncInfo->getForwardedMustTailRegParms();
2669 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2671 // Conservatively forward AL on x86_64, since it might be used for varargs.
2672 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2673 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2674 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2677 // Copy all forwards from physical to virtual registers.
2678 for (ForwardedRegister &F : Forwards) {
2679 // FIXME: Can we use a less constrained schedule?
2680 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2681 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2682 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2686 // Some CCs need callee pop.
2687 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2688 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2689 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2691 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2692 // If this is an sret function, the return should pop the hidden pointer.
2693 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2694 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2695 argsAreStructReturn(Ins) == StackStructReturn)
2696 FuncInfo->setBytesToPopOnReturn(4);
2700 // RegSaveFrameIndex is X86-64 only.
2701 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2702 if (CallConv == CallingConv::X86_FastCall ||
2703 CallConv == CallingConv::X86_ThisCall)
2704 // fastcc functions can't have varargs.
2705 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2708 FuncInfo->setArgumentStackSize(StackSize);
2714 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2715 SDValue StackPtr, SDValue Arg,
2716 SDLoc dl, SelectionDAG &DAG,
2717 const CCValAssign &VA,
2718 ISD::ArgFlagsTy Flags) const {
2719 unsigned LocMemOffset = VA.getLocMemOffset();
2720 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2721 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2722 if (Flags.isByVal())
2723 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2725 return DAG.getStore(Chain, dl, Arg, PtrOff,
2726 MachinePointerInfo::getStack(LocMemOffset),
2730 /// Emit a load of return address if tail call
2731 /// optimization is performed and it is required.
2733 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2734 SDValue &OutRetAddr, SDValue Chain,
2735 bool IsTailCall, bool Is64Bit,
2736 int FPDiff, SDLoc dl) const {
2737 // Adjust the Return address stack slot.
2738 EVT VT = getPointerTy();
2739 OutRetAddr = getReturnAddressFrameIndex(DAG);
2741 // Load the "old" Return address.
2742 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2743 false, false, false, 0);
2744 return SDValue(OutRetAddr.getNode(), 1);
2747 /// Emit a store of the return address if tail call
2748 /// optimization is performed and it is required (FPDiff!=0).
2749 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2750 SDValue Chain, SDValue RetAddrFrIdx,
2751 EVT PtrVT, unsigned SlotSize,
2752 int FPDiff, SDLoc dl) {
2753 // Store the return address to the appropriate stack slot.
2754 if (!FPDiff) return Chain;
2755 // Calculate the new stack slot for the return address.
2756 int NewReturnAddrFI =
2757 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2759 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2760 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2761 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2767 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2768 SmallVectorImpl<SDValue> &InVals) const {
2769 SelectionDAG &DAG = CLI.DAG;
2771 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2772 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2773 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2774 SDValue Chain = CLI.Chain;
2775 SDValue Callee = CLI.Callee;
2776 CallingConv::ID CallConv = CLI.CallConv;
2777 bool &isTailCall = CLI.IsTailCall;
2778 bool isVarArg = CLI.IsVarArg;
2780 MachineFunction &MF = DAG.getMachineFunction();
2781 bool Is64Bit = Subtarget->is64Bit();
2782 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2783 StructReturnType SR = callIsStructReturn(Outs);
2784 bool IsSibcall = false;
2785 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2787 if (MF.getTarget().Options.DisableTailCalls)
2790 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2792 // Force this to be a tail call. The verifier rules are enough to ensure
2793 // that we can lower this successfully without moving the return address
2796 } else if (isTailCall) {
2797 // Check if it's really possible to do a tail call.
2798 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2799 isVarArg, SR != NotStructReturn,
2800 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2801 Outs, OutVals, Ins, DAG);
2803 // Sibcalls are automatically detected tailcalls which do not require
2805 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2812 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2813 "Var args not supported with calling convention fastcc, ghc or hipe");
2815 // Analyze operands of the call, assigning locations to each operand.
2816 SmallVector<CCValAssign, 16> ArgLocs;
2817 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2819 // Allocate shadow area for Win64
2821 CCInfo.AllocateStack(32, 8);
2823 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2825 // Get a count of how many bytes are to be pushed on the stack.
2826 unsigned NumBytes = CCInfo.getNextStackOffset();
2828 // This is a sibcall. The memory operands are available in caller's
2829 // own caller's stack.
2831 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2832 IsTailCallConvention(CallConv))
2833 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2836 if (isTailCall && !IsSibcall && !IsMustTail) {
2837 // Lower arguments at fp - stackoffset + fpdiff.
2838 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2840 FPDiff = NumBytesCallerPushed - NumBytes;
2842 // Set the delta of movement of the returnaddr stackslot.
2843 // But only set if delta is greater than previous delta.
2844 if (FPDiff < X86Info->getTCReturnAddrDelta())
2845 X86Info->setTCReturnAddrDelta(FPDiff);
2848 unsigned NumBytesToPush = NumBytes;
2849 unsigned NumBytesToPop = NumBytes;
2851 // If we have an inalloca argument, all stack space has already been allocated
2852 // for us and be right at the top of the stack. We don't support multiple
2853 // arguments passed in memory when using inalloca.
2854 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2856 if (!ArgLocs.back().isMemLoc())
2857 report_fatal_error("cannot use inalloca attribute on a register "
2859 if (ArgLocs.back().getLocMemOffset() != 0)
2860 report_fatal_error("any parameter with the inalloca attribute must be "
2861 "the only memory argument");
2865 Chain = DAG.getCALLSEQ_START(
2866 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2868 SDValue RetAddrFrIdx;
2869 // Load return address for tail calls.
2870 if (isTailCall && FPDiff)
2871 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2872 Is64Bit, FPDiff, dl);
2874 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2875 SmallVector<SDValue, 8> MemOpChains;
2878 // Walk the register/memloc assignments, inserting copies/loads. In the case
2879 // of tail call optimization arguments are handle later.
2880 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2881 DAG.getSubtarget().getRegisterInfo());
2882 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2883 // Skip inalloca arguments, they have already been written.
2884 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2885 if (Flags.isInAlloca())
2888 CCValAssign &VA = ArgLocs[i];
2889 EVT RegVT = VA.getLocVT();
2890 SDValue Arg = OutVals[i];
2891 bool isByVal = Flags.isByVal();
2893 // Promote the value if needed.
2894 switch (VA.getLocInfo()) {
2895 default: llvm_unreachable("Unknown loc info!");
2896 case CCValAssign::Full: break;
2897 case CCValAssign::SExt:
2898 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2900 case CCValAssign::ZExt:
2901 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2903 case CCValAssign::AExt:
2904 if (RegVT.is128BitVector()) {
2905 // Special case: passing MMX values in XMM registers.
2906 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2907 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2908 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2910 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2912 case CCValAssign::BCvt:
2913 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2915 case CCValAssign::Indirect: {
2916 // Store the argument.
2917 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2918 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2919 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2920 MachinePointerInfo::getFixedStack(FI),
2927 if (VA.isRegLoc()) {
2928 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2929 if (isVarArg && IsWin64) {
2930 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2931 // shadow reg if callee is a varargs function.
2932 unsigned ShadowReg = 0;
2933 switch (VA.getLocReg()) {
2934 case X86::XMM0: ShadowReg = X86::RCX; break;
2935 case X86::XMM1: ShadowReg = X86::RDX; break;
2936 case X86::XMM2: ShadowReg = X86::R8; break;
2937 case X86::XMM3: ShadowReg = X86::R9; break;
2940 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2942 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2943 assert(VA.isMemLoc());
2944 if (!StackPtr.getNode())
2945 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2947 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2948 dl, DAG, VA, Flags));
2952 if (!MemOpChains.empty())
2953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2955 if (Subtarget->isPICStyleGOT()) {
2956 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2960 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2962 // If we are tail calling and generating PIC/GOT style code load the
2963 // address of the callee into ECX. The value in ecx is used as target of
2964 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2965 // for tail calls on PIC/GOT architectures. Normally we would just put the
2966 // address of GOT into ebx and then call target@PLT. But for tail calls
2967 // ebx would be restored (since ebx is callee saved) before jumping to the
2970 // Note: The actual moving to ECX is done further down.
2971 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2972 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2973 !G->getGlobal()->hasProtectedVisibility())
2974 Callee = LowerGlobalAddress(Callee, DAG);
2975 else if (isa<ExternalSymbolSDNode>(Callee))
2976 Callee = LowerExternalSymbol(Callee, DAG);
2980 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2981 // From AMD64 ABI document:
2982 // For calls that may call functions that use varargs or stdargs
2983 // (prototype-less calls or calls to functions containing ellipsis (...) in
2984 // the declaration) %al is used as hidden argument to specify the number
2985 // of SSE registers used. The contents of %al do not need to match exactly
2986 // the number of registers, but must be an ubound on the number of SSE
2987 // registers used and is in the range 0 - 8 inclusive.
2989 // Count the number of XMM registers allocated.
2990 static const MCPhysReg XMMArgRegs[] = {
2991 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2992 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2994 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2995 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2996 && "SSE registers cannot be used when SSE is disabled");
2998 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2999 DAG.getConstant(NumXMMRegs, MVT::i8)));
3002 if (isVarArg && IsMustTail) {
3003 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3004 for (const auto &F : Forwards) {
3005 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3006 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3010 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3011 // don't need this because the eligibility check rejects calls that require
3012 // shuffling arguments passed in memory.
3013 if (!IsSibcall && isTailCall) {
3014 // Force all the incoming stack arguments to be loaded from the stack
3015 // before any new outgoing arguments are stored to the stack, because the
3016 // outgoing stack slots may alias the incoming argument stack slots, and
3017 // the alias isn't otherwise explicit. This is slightly more conservative
3018 // than necessary, because it means that each store effectively depends
3019 // on every argument instead of just those arguments it would clobber.
3020 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3022 SmallVector<SDValue, 8> MemOpChains2;
3025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3026 CCValAssign &VA = ArgLocs[i];
3029 assert(VA.isMemLoc());
3030 SDValue Arg = OutVals[i];
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 // Skip inalloca arguments. They don't require any work.
3033 if (Flags.isInAlloca())
3035 // Create frame index.
3036 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3037 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3038 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3039 FIN = DAG.getFrameIndex(FI, getPointerTy());
3041 if (Flags.isByVal()) {
3042 // Copy relative to framepointer.
3043 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3044 if (!StackPtr.getNode())
3045 StackPtr = DAG.getCopyFromReg(Chain, dl,
3046 RegInfo->getStackRegister(),
3048 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3050 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3054 // Store relative to framepointer.
3055 MemOpChains2.push_back(
3056 DAG.getStore(ArgChain, dl, Arg, FIN,
3057 MachinePointerInfo::getFixedStack(FI),
3062 if (!MemOpChains2.empty())
3063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3065 // Store the return address to the appropriate stack slot.
3066 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3067 getPointerTy(), RegInfo->getSlotSize(),
3071 // Build a sequence of copy-to-reg nodes chained together with token chain
3072 // and flag operands which copy the outgoing args into registers.
3074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3076 RegsToPass[i].second, InFlag);
3077 InFlag = Chain.getValue(1);
3080 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3081 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3082 // In the 64-bit large code model, we have to make all calls
3083 // through a register, since the call instruction's 32-bit
3084 // pc-relative offset may not be large enough to hold the whole
3086 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3087 // If the callee is a GlobalAddress node (quite common, every direct call
3088 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3091 // We should use extra load for direct calls to dllimported functions in
3093 const GlobalValue *GV = G->getGlobal();
3094 if (!GV->hasDLLImportStorageClass()) {
3095 unsigned char OpFlags = 0;
3096 bool ExtraLoad = false;
3097 unsigned WrapperKind = ISD::DELETED_NODE;
3099 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3100 // external symbols most go through the PLT in PIC mode. If the symbol
3101 // has hidden or protected visibility, or if it is static or local, then
3102 // we don't need to use the PLT - we can directly call it.
3103 if (Subtarget->isTargetELF() &&
3104 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3105 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3106 OpFlags = X86II::MO_PLT;
3107 } else if (Subtarget->isPICStyleStubAny() &&
3108 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3109 (!Subtarget->getTargetTriple().isMacOSX() ||
3110 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3111 // PC-relative references to external symbols should go through $stub,
3112 // unless we're building with the leopard linker or later, which
3113 // automatically synthesizes these stubs.
3114 OpFlags = X86II::MO_DARWIN_STUB;
3115 } else if (Subtarget->isPICStyleRIPRel() &&
3116 isa<Function>(GV) &&
3117 cast<Function>(GV)->getAttributes().
3118 hasAttribute(AttributeSet::FunctionIndex,
3119 Attribute::NonLazyBind)) {
3120 // If the function is marked as non-lazy, generate an indirect call
3121 // which loads from the GOT directly. This avoids runtime overhead
3122 // at the cost of eager binding (and one extra byte of encoding).
3123 OpFlags = X86II::MO_GOTPCREL;
3124 WrapperKind = X86ISD::WrapperRIP;
3128 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3129 G->getOffset(), OpFlags);
3131 // Add a wrapper if needed.
3132 if (WrapperKind != ISD::DELETED_NODE)
3133 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3134 // Add extra indirection if needed.
3136 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3137 MachinePointerInfo::getGOT(),
3138 false, false, false, 0);
3140 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3141 unsigned char OpFlags = 0;
3143 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3144 // external symbols should go through the PLT.
3145 if (Subtarget->isTargetELF() &&
3146 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3147 OpFlags = X86II::MO_PLT;
3148 } else if (Subtarget->isPICStyleStubAny() &&
3149 (!Subtarget->getTargetTriple().isMacOSX() ||
3150 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3151 // PC-relative references to external symbols should go through $stub,
3152 // unless we're building with the leopard linker or later, which
3153 // automatically synthesizes these stubs.
3154 OpFlags = X86II::MO_DARWIN_STUB;
3157 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3159 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3160 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3161 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3164 // Returns a chain & a flag for retval copy to use.
3165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3166 SmallVector<SDValue, 8> Ops;
3168 if (!IsSibcall && isTailCall) {
3169 Chain = DAG.getCALLSEQ_END(Chain,
3170 DAG.getIntPtrConstant(NumBytesToPop, true),
3171 DAG.getIntPtrConstant(0, true), InFlag, dl);
3172 InFlag = Chain.getValue(1);
3175 Ops.push_back(Chain);
3176 Ops.push_back(Callee);
3179 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3181 // Add argument registers to the end of the list so that they are known live
3183 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3184 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3185 RegsToPass[i].second.getValueType()));
3187 // Add a register mask operand representing the call-preserved registers.
3188 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3189 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3190 assert(Mask && "Missing call preserved mask for calling convention");
3191 Ops.push_back(DAG.getRegisterMask(Mask));
3193 if (InFlag.getNode())
3194 Ops.push_back(InFlag);
3198 //// If this is the first return lowered for this function, add the regs
3199 //// to the liveout set for the function.
3200 // This isn't right, although it's probably harmless on x86; liveouts
3201 // should be computed from returns not tail calls. Consider a void
3202 // function making a tail call to a function returning int.
3203 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3206 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3207 InFlag = Chain.getValue(1);
3209 // Create the CALLSEQ_END node.
3210 unsigned NumBytesForCalleeToPop;
3211 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3212 DAG.getTarget().Options.GuaranteedTailCallOpt))
3213 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3214 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3215 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3216 SR == StackStructReturn)
3217 // If this is a call to a struct-return function, the callee
3218 // pops the hidden struct pointer, so we have to push it back.
3219 // This is common for Darwin/X86, Linux & Mingw32 targets.
3220 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3221 NumBytesForCalleeToPop = 4;
3223 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3225 // Returns a flag for retval copy to use.
3227 Chain = DAG.getCALLSEQ_END(Chain,
3228 DAG.getIntPtrConstant(NumBytesToPop, true),
3229 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3232 InFlag = Chain.getValue(1);
3235 // Handle result values, copying them out of physregs into vregs that we
3237 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3238 Ins, dl, DAG, InVals);
3241 //===----------------------------------------------------------------------===//
3242 // Fast Calling Convention (tail call) implementation
3243 //===----------------------------------------------------------------------===//
3245 // Like std call, callee cleans arguments, convention except that ECX is
3246 // reserved for storing the tail called function address. Only 2 registers are
3247 // free for argument passing (inreg). Tail call optimization is performed
3249 // * tailcallopt is enabled
3250 // * caller/callee are fastcc
3251 // On X86_64 architecture with GOT-style position independent code only local
3252 // (within module) calls are supported at the moment.
3253 // To keep the stack aligned according to platform abi the function
3254 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3255 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3256 // If a tail called function callee has more arguments than the caller the
3257 // caller needs to make sure that there is room to move the RETADDR to. This is
3258 // achieved by reserving an area the size of the argument delta right after the
3259 // original RETADDR, but before the saved framepointer or the spilled registers
3260 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3272 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3273 /// for a 16 byte align requirement.
3275 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3276 SelectionDAG& DAG) const {
3277 MachineFunction &MF = DAG.getMachineFunction();
3278 const TargetMachine &TM = MF.getTarget();
3279 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3280 TM.getSubtargetImpl()->getRegisterInfo());
3281 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3282 unsigned StackAlignment = TFI.getStackAlignment();
3283 uint64_t AlignMask = StackAlignment - 1;
3284 int64_t Offset = StackSize;
3285 unsigned SlotSize = RegInfo->getSlotSize();
3286 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3287 // Number smaller than 12 so just add the difference.
3288 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3290 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3291 Offset = ((~AlignMask) & Offset) + StackAlignment +
3292 (StackAlignment-SlotSize);
3297 /// MatchingStackOffset - Return true if the given stack call argument is
3298 /// already available in the same position (relatively) of the caller's
3299 /// incoming argument stack.
3301 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3302 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3303 const X86InstrInfo *TII) {
3304 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3306 if (Arg.getOpcode() == ISD::CopyFromReg) {
3307 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3308 if (!TargetRegisterInfo::isVirtualRegister(VR))
3310 MachineInstr *Def = MRI->getVRegDef(VR);
3313 if (!Flags.isByVal()) {
3314 if (!TII->isLoadFromStackSlot(Def, FI))
3317 unsigned Opcode = Def->getOpcode();
3318 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3319 Def->getOperand(1).isFI()) {
3320 FI = Def->getOperand(1).getIndex();
3321 Bytes = Flags.getByValSize();
3325 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3326 if (Flags.isByVal())
3327 // ByVal argument is passed in as a pointer but it's now being
3328 // dereferenced. e.g.
3329 // define @foo(%struct.X* %A) {
3330 // tail call @bar(%struct.X* byval %A)
3333 SDValue Ptr = Ld->getBasePtr();
3334 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3337 FI = FINode->getIndex();
3338 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3339 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3340 FI = FINode->getIndex();
3341 Bytes = Flags.getByValSize();
3345 assert(FI != INT_MAX);
3346 if (!MFI->isFixedObjectIndex(FI))
3348 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3351 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3352 /// for tail call optimization. Targets which want to do tail call
3353 /// optimization should implement this function.
3355 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3356 CallingConv::ID CalleeCC,
3358 bool isCalleeStructRet,
3359 bool isCallerStructRet,
3361 const SmallVectorImpl<ISD::OutputArg> &Outs,
3362 const SmallVectorImpl<SDValue> &OutVals,
3363 const SmallVectorImpl<ISD::InputArg> &Ins,
3364 SelectionDAG &DAG) const {
3365 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3368 // If -tailcallopt is specified, make fastcc functions tail-callable.
3369 const MachineFunction &MF = DAG.getMachineFunction();
3370 const Function *CallerF = MF.getFunction();
3372 // If the function return type is x86_fp80 and the callee return type is not,
3373 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3374 // perform a tailcall optimization here.
3375 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3378 CallingConv::ID CallerCC = CallerF->getCallingConv();
3379 bool CCMatch = CallerCC == CalleeCC;
3380 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3381 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3383 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3384 if (IsTailCallConvention(CalleeCC) && CCMatch)
3389 // Look for obvious safe cases to perform tail call optimization that do not
3390 // require ABI changes. This is what gcc calls sibcall.
3392 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3393 // emit a special epilogue.
3394 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3395 DAG.getSubtarget().getRegisterInfo());
3396 if (RegInfo->needsStackRealignment(MF))
3399 // Also avoid sibcall optimization if either caller or callee uses struct
3400 // return semantics.
3401 if (isCalleeStructRet || isCallerStructRet)
3404 // An stdcall/thiscall caller is expected to clean up its arguments; the
3405 // callee isn't going to do that.
3406 // FIXME: this is more restrictive than needed. We could produce a tailcall
3407 // when the stack adjustment matches. For example, with a thiscall that takes
3408 // only one argument.
3409 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3410 CallerCC == CallingConv::X86_ThisCall))
3413 // Do not sibcall optimize vararg calls unless all arguments are passed via
3415 if (isVarArg && !Outs.empty()) {
3417 // Optimizing for varargs on Win64 is unlikely to be safe without
3418 // additional testing.
3419 if (IsCalleeWin64 || IsCallerWin64)
3422 SmallVector<CCValAssign, 16> ArgLocs;
3423 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3426 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3427 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3428 if (!ArgLocs[i].isRegLoc())
3432 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3433 // stack. Therefore, if it's not used by the call it is not safe to optimize
3434 // this into a sibcall.
3435 bool Unused = false;
3436 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3443 SmallVector<CCValAssign, 16> RVLocs;
3444 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3446 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3447 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3448 CCValAssign &VA = RVLocs[i];
3449 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3454 // If the calling conventions do not match, then we'd better make sure the
3455 // results are returned in the same way as what the caller expects.
3457 SmallVector<CCValAssign, 16> RVLocs1;
3458 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3460 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3462 SmallVector<CCValAssign, 16> RVLocs2;
3463 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3465 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3467 if (RVLocs1.size() != RVLocs2.size())
3469 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3470 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3472 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3474 if (RVLocs1[i].isRegLoc()) {
3475 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3478 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3484 // If the callee takes no arguments then go on to check the results of the
3486 if (!Outs.empty()) {
3487 // Check if stack adjustment is needed. For now, do not do this if any
3488 // argument is passed on the stack.
3489 SmallVector<CCValAssign, 16> ArgLocs;
3490 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3493 // Allocate shadow area for Win64
3495 CCInfo.AllocateStack(32, 8);
3497 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3498 if (CCInfo.getNextStackOffset()) {
3499 MachineFunction &MF = DAG.getMachineFunction();
3500 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3503 // Check if the arguments are already laid out in the right way as
3504 // the caller's fixed stack objects.
3505 MachineFrameInfo *MFI = MF.getFrameInfo();
3506 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3507 const X86InstrInfo *TII =
3508 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3509 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3510 CCValAssign &VA = ArgLocs[i];
3511 SDValue Arg = OutVals[i];
3512 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3513 if (VA.getLocInfo() == CCValAssign::Indirect)
3515 if (!VA.isRegLoc()) {
3516 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3523 // If the tailcall address may be in a register, then make sure it's
3524 // possible to register allocate for it. In 32-bit, the call address can
3525 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3526 // callee-saved registers are restored. These happen to be the same
3527 // registers used to pass 'inreg' arguments so watch out for those.
3528 if (!Subtarget->is64Bit() &&
3529 ((!isa<GlobalAddressSDNode>(Callee) &&
3530 !isa<ExternalSymbolSDNode>(Callee)) ||
3531 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3532 unsigned NumInRegs = 0;
3533 // In PIC we need an extra register to formulate the address computation
3535 unsigned MaxInRegs =
3536 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3538 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3539 CCValAssign &VA = ArgLocs[i];
3542 unsigned Reg = VA.getLocReg();
3545 case X86::EAX: case X86::EDX: case X86::ECX:
3546 if (++NumInRegs == MaxInRegs)
3558 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3559 const TargetLibraryInfo *libInfo) const {
3560 return X86::createFastISel(funcInfo, libInfo);
3563 //===----------------------------------------------------------------------===//
3564 // Other Lowering Hooks
3565 //===----------------------------------------------------------------------===//
3567 static bool MayFoldLoad(SDValue Op) {
3568 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3571 static bool MayFoldIntoStore(SDValue Op) {
3572 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3575 static bool isTargetShuffle(unsigned Opcode) {
3577 default: return false;
3578 case X86ISD::BLENDI:
3579 case X86ISD::PSHUFB:
3580 case X86ISD::PSHUFD:
3581 case X86ISD::PSHUFHW:
3582 case X86ISD::PSHUFLW:
3584 case X86ISD::PALIGNR:
3585 case X86ISD::MOVLHPS:
3586 case X86ISD::MOVLHPD:
3587 case X86ISD::MOVHLPS:
3588 case X86ISD::MOVLPS:
3589 case X86ISD::MOVLPD:
3590 case X86ISD::MOVSHDUP:
3591 case X86ISD::MOVSLDUP:
3592 case X86ISD::MOVDDUP:
3595 case X86ISD::UNPCKL:
3596 case X86ISD::UNPCKH:
3597 case X86ISD::VPERMILPI:
3598 case X86ISD::VPERM2X128:
3599 case X86ISD::VPERMI:
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVSHDUP:
3609 case X86ISD::MOVSLDUP:
3610 case X86ISD::MOVDDUP:
3611 return DAG.getNode(Opc, dl, VT, V1);
3615 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3616 SDValue V1, unsigned TargetMask,
3617 SelectionDAG &DAG) {
3619 default: llvm_unreachable("Unknown x86 shuffle node");
3620 case X86ISD::PSHUFD:
3621 case X86ISD::PSHUFHW:
3622 case X86ISD::PSHUFLW:
3623 case X86ISD::VPERMILPI:
3624 case X86ISD::VPERMI:
3625 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3629 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3630 SDValue V1, SDValue V2, unsigned TargetMask,
3631 SelectionDAG &DAG) {
3633 default: llvm_unreachable("Unknown x86 shuffle node");
3634 case X86ISD::PALIGNR:
3635 case X86ISD::VALIGN:
3637 case X86ISD::VPERM2X128:
3638 return DAG.getNode(Opc, dl, VT, V1, V2,
3639 DAG.getConstant(TargetMask, MVT::i8));
3643 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3644 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3646 default: llvm_unreachable("Unknown x86 shuffle node");
3647 case X86ISD::MOVLHPS:
3648 case X86ISD::MOVLHPD:
3649 case X86ISD::MOVHLPS:
3650 case X86ISD::MOVLPS:
3651 case X86ISD::MOVLPD:
3654 case X86ISD::UNPCKL:
3655 case X86ISD::UNPCKH:
3656 return DAG.getNode(Opc, dl, VT, V1, V2);
3660 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3661 MachineFunction &MF = DAG.getMachineFunction();
3662 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3663 DAG.getSubtarget().getRegisterInfo());
3664 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3665 int ReturnAddrIndex = FuncInfo->getRAIndex();
3667 if (ReturnAddrIndex == 0) {
3668 // Set up a frame object for the return address.
3669 unsigned SlotSize = RegInfo->getSlotSize();
3670 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3673 FuncInfo->setRAIndex(ReturnAddrIndex);
3676 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3679 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3680 bool hasSymbolicDisplacement) {
3681 // Offset should fit into 32 bit immediate field.
3682 if (!isInt<32>(Offset))
3685 // If we don't have a symbolic displacement - we don't have any extra
3687 if (!hasSymbolicDisplacement)
3690 // FIXME: Some tweaks might be needed for medium code model.
3691 if (M != CodeModel::Small && M != CodeModel::Kernel)
3694 // For small code model we assume that latest object is 16MB before end of 31
3695 // bits boundary. We may also accept pretty large negative constants knowing
3696 // that all objects are in the positive half of address space.
3697 if (M == CodeModel::Small && Offset < 16*1024*1024)
3700 // For kernel code model we know that all object resist in the negative half
3701 // of 32bits address space. We may not accept negative offsets, since they may
3702 // be just off and we may accept pretty large positive ones.
3703 if (M == CodeModel::Kernel && Offset >= 0)
3709 /// isCalleePop - Determines whether the callee is required to pop its
3710 /// own arguments. Callee pop is necessary to support tail calls.
3711 bool X86::isCalleePop(CallingConv::ID CallingConv,
3712 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3713 switch (CallingConv) {
3716 case CallingConv::X86_StdCall:
3717 case CallingConv::X86_FastCall:
3718 case CallingConv::X86_ThisCall:
3720 case CallingConv::Fast:
3721 case CallingConv::GHC:
3722 case CallingConv::HiPE:
3729 /// \brief Return true if the condition is an unsigned comparison operation.
3730 static bool isX86CCUnsigned(unsigned X86CC) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case X86::COND_E: return true;
3734 case X86::COND_G: return false;
3735 case X86::COND_GE: return false;
3736 case X86::COND_L: return false;
3737 case X86::COND_LE: return false;
3738 case X86::COND_NE: return true;
3739 case X86::COND_B: return true;
3740 case X86::COND_A: return true;
3741 case X86::COND_BE: return true;
3742 case X86::COND_AE: return true;
3744 llvm_unreachable("covered switch fell through?!");
3747 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3748 /// specific condition code, returning the condition code and the LHS/RHS of the
3749 /// comparison to make.
3750 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3751 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3753 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3754 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3755 // X > -1 -> X == 0, jump !sign.
3756 RHS = DAG.getConstant(0, RHS.getValueType());
3757 return X86::COND_NS;
3759 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3760 // X < 0 -> X == 0, jump on sign.
3763 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3765 RHS = DAG.getConstant(0, RHS.getValueType());
3766 return X86::COND_LE;
3770 switch (SetCCOpcode) {
3771 default: llvm_unreachable("Invalid integer condition!");
3772 case ISD::SETEQ: return X86::COND_E;
3773 case ISD::SETGT: return X86::COND_G;
3774 case ISD::SETGE: return X86::COND_GE;
3775 case ISD::SETLT: return X86::COND_L;
3776 case ISD::SETLE: return X86::COND_LE;
3777 case ISD::SETNE: return X86::COND_NE;
3778 case ISD::SETULT: return X86::COND_B;
3779 case ISD::SETUGT: return X86::COND_A;
3780 case ISD::SETULE: return X86::COND_BE;
3781 case ISD::SETUGE: return X86::COND_AE;
3785 // First determine if it is required or is profitable to flip the operands.
3787 // If LHS is a foldable load, but RHS is not, flip the condition.
3788 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3789 !ISD::isNON_EXTLoad(RHS.getNode())) {
3790 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3791 std::swap(LHS, RHS);
3794 switch (SetCCOpcode) {
3800 std::swap(LHS, RHS);
3804 // On a floating point condition, the flags are set as follows:
3806 // 0 | 0 | 0 | X > Y
3807 // 0 | 0 | 1 | X < Y
3808 // 1 | 0 | 0 | X == Y
3809 // 1 | 1 | 1 | unordered
3810 switch (SetCCOpcode) {
3811 default: llvm_unreachable("Condcode should be pre-legalized away");
3813 case ISD::SETEQ: return X86::COND_E;
3814 case ISD::SETOLT: // flipped
3816 case ISD::SETGT: return X86::COND_A;
3817 case ISD::SETOLE: // flipped
3819 case ISD::SETGE: return X86::COND_AE;
3820 case ISD::SETUGT: // flipped
3822 case ISD::SETLT: return X86::COND_B;
3823 case ISD::SETUGE: // flipped
3825 case ISD::SETLE: return X86::COND_BE;
3827 case ISD::SETNE: return X86::COND_NE;
3828 case ISD::SETUO: return X86::COND_P;
3829 case ISD::SETO: return X86::COND_NP;
3831 case ISD::SETUNE: return X86::COND_INVALID;
3835 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3836 /// code. Current x86 isa includes the following FP cmov instructions:
3837 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3838 static bool hasFPCMov(unsigned X86CC) {
3854 /// isFPImmLegal - Returns true if the target can instruction select the
3855 /// specified FP immediate natively. If false, the legalizer will
3856 /// materialize the FP immediate as a load from a constant pool.
3857 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3858 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3859 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3865 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3866 ISD::LoadExtType ExtTy,
3868 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3869 // relocation target a movq or addq instruction: don't let the load shrink.
3870 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3871 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3872 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3873 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3877 /// \brief Returns true if it is beneficial to convert a load of a constant
3878 /// to just the constant itself.
3879 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3881 assert(Ty->isIntegerTy());
3883 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3884 if (BitSize == 0 || BitSize > 64)
3889 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3890 unsigned Index) const {
3891 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3894 return (Index == 0 || Index == ResVT.getVectorNumElements());
3897 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3898 // Speculate cttz only if we can directly use TZCNT.
3899 return Subtarget->hasBMI();
3902 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3903 // Speculate ctlz only if we can directly use LZCNT.
3904 return Subtarget->hasLZCNT();
3907 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3908 /// the specified range (L, H].
3909 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3910 return (Val < 0) || (Val >= Low && Val < Hi);
3913 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3914 /// specified value.
3915 static bool isUndefOrEqual(int Val, int CmpVal) {
3916 return (Val < 0 || Val == CmpVal);
3919 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3920 /// from position Pos and ending in Pos+Size, falls within the specified
3921 /// sequential range (Low, Low+Size]. or is undef.
3922 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3923 unsigned Pos, unsigned Size, int Low) {
3924 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3925 if (!isUndefOrEqual(Mask[i], Low))
3930 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3931 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3932 /// operand - by default will match for first operand.
3933 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3934 bool TestSecondOperand = false) {
3935 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3936 VT != MVT::v2f64 && VT != MVT::v2i64)
3939 unsigned NumElems = VT.getVectorNumElements();
3940 unsigned Lo = TestSecondOperand ? NumElems : 0;
3941 unsigned Hi = Lo + NumElems;
3943 for (unsigned i = 0; i < NumElems; ++i)
3944 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3950 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3951 /// is suitable for input to PSHUFHW.
3952 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3953 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3956 // Lower quadword copied in order or undef.
3957 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3960 // Upper quadword shuffled.
3961 for (unsigned i = 4; i != 8; ++i)
3962 if (!isUndefOrInRange(Mask[i], 4, 8))
3965 if (VT == MVT::v16i16) {
3966 // Lower quadword copied in order or undef.
3967 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3970 // Upper quadword shuffled.
3971 for (unsigned i = 12; i != 16; ++i)
3972 if (!isUndefOrInRange(Mask[i], 12, 16))
3979 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3980 /// is suitable for input to PSHUFLW.
3981 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3982 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3985 // Upper quadword copied in order.
3986 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3989 // Lower quadword shuffled.
3990 for (unsigned i = 0; i != 4; ++i)
3991 if (!isUndefOrInRange(Mask[i], 0, 4))
3994 if (VT == MVT::v16i16) {
3995 // Upper quadword copied in order.
3996 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3999 // Lower quadword shuffled.
4000 for (unsigned i = 8; i != 12; ++i)
4001 if (!isUndefOrInRange(Mask[i], 8, 12))
4008 /// \brief Return true if the mask specifies a shuffle of elements that is
4009 /// suitable for input to intralane (palignr) or interlane (valign) vector
4011 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
4012 unsigned NumElts = VT.getVectorNumElements();
4013 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
4014 unsigned NumLaneElts = NumElts/NumLanes;
4016 // Do not handle 64-bit element shuffles with palignr.
4017 if (NumLaneElts == 2)
4020 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4022 for (i = 0; i != NumLaneElts; ++i) {
4027 // Lane is all undef, go to next lane
4028 if (i == NumLaneElts)
4031 int Start = Mask[i+l];
4033 // Make sure its in this lane in one of the sources
4034 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4035 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4038 // If not lane 0, then we must match lane 0
4039 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4042 // Correct second source to be contiguous with first source
4043 if (Start >= (int)NumElts)
4044 Start -= NumElts - NumLaneElts;
4046 // Make sure we're shifting in the right direction.
4047 if (Start <= (int)(i+l))
4052 // Check the rest of the elements to see if they are consecutive.
4053 for (++i; i != NumLaneElts; ++i) {
4054 int Idx = Mask[i+l];
4056 // Make sure its in this lane
4057 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4058 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4061 // If not lane 0, then we must match lane 0
4062 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4065 if (Idx >= (int)NumElts)
4066 Idx -= NumElts - NumLaneElts;
4068 if (!isUndefOrEqual(Idx, Start+i))
4077 /// \brief Return true if the node specifies a shuffle of elements that is
4078 /// suitable for input to PALIGNR.
4079 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4080 const X86Subtarget *Subtarget) {
4081 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4082 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4083 VT.is512BitVector())
4084 // FIXME: Add AVX512BW.
4087 return isAlignrMask(Mask, VT, false);
4090 /// \brief Return true if the node specifies a shuffle of elements that is
4091 /// suitable for input to VALIGN.
4092 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4093 const X86Subtarget *Subtarget) {
4094 // FIXME: Add AVX512VL.
4095 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4097 return isAlignrMask(Mask, VT, true);
4100 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4101 /// the two vector operands have swapped position.
4102 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4103 unsigned NumElems) {
4104 for (unsigned i = 0; i != NumElems; ++i) {
4108 else if (idx < (int)NumElems)
4109 Mask[i] = idx + NumElems;
4111 Mask[i] = idx - NumElems;
4115 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4116 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4117 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4118 /// reverse of what x86 shuffles want.
4119 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4121 unsigned NumElems = VT.getVectorNumElements();
4122 unsigned NumLanes = VT.getSizeInBits()/128;
4123 unsigned NumLaneElems = NumElems/NumLanes;
4125 if (NumLaneElems != 2 && NumLaneElems != 4)
4128 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4129 bool symetricMaskRequired =
4130 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4132 // VSHUFPSY divides the resulting vector into 4 chunks.
4133 // The sources are also splitted into 4 chunks, and each destination
4134 // chunk must come from a different source chunk.
4136 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4137 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4139 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4140 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4142 // VSHUFPDY divides the resulting vector into 4 chunks.
4143 // The sources are also splitted into 4 chunks, and each destination
4144 // chunk must come from a different source chunk.
4146 // SRC1 => X3 X2 X1 X0
4147 // SRC2 => Y3 Y2 Y1 Y0
4149 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4151 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4152 unsigned HalfLaneElems = NumLaneElems/2;
4153 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4154 for (unsigned i = 0; i != NumLaneElems; ++i) {
4155 int Idx = Mask[i+l];
4156 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4157 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4159 // For VSHUFPSY, the mask of the second half must be the same as the
4160 // first but with the appropriate offsets. This works in the same way as
4161 // VPERMILPS works with masks.
4162 if (!symetricMaskRequired || Idx < 0)
4164 if (MaskVal[i] < 0) {
4165 MaskVal[i] = Idx - l;
4168 if ((signed)(Idx - l) != MaskVal[i])
4176 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4177 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4178 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4179 if (!VT.is128BitVector())
4182 unsigned NumElems = VT.getVectorNumElements();
4187 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4188 return isUndefOrEqual(Mask[0], 6) &&
4189 isUndefOrEqual(Mask[1], 7) &&
4190 isUndefOrEqual(Mask[2], 2) &&
4191 isUndefOrEqual(Mask[3], 3);
4194 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4195 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4197 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4198 if (!VT.is128BitVector())
4201 unsigned NumElems = VT.getVectorNumElements();
4206 return isUndefOrEqual(Mask[0], 2) &&
4207 isUndefOrEqual(Mask[1], 3) &&
4208 isUndefOrEqual(Mask[2], 2) &&
4209 isUndefOrEqual(Mask[3], 3);
4212 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4213 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4214 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4215 if (!VT.is128BitVector())
4218 unsigned NumElems = VT.getVectorNumElements();
4220 if (NumElems != 2 && NumElems != 4)
4223 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4224 if (!isUndefOrEqual(Mask[i], i + NumElems))
4227 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4228 if (!isUndefOrEqual(Mask[i], i))
4234 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4235 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4236 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4237 if (!VT.is128BitVector())
4240 unsigned NumElems = VT.getVectorNumElements();
4242 if (NumElems != 2 && NumElems != 4)
4245 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4246 if (!isUndefOrEqual(Mask[i], i))
4249 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4250 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4256 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4257 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4258 /// i. e: If all but one element come from the same vector.
4259 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4260 // TODO: Deal with AVX's VINSERTPS
4261 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4264 unsigned CorrectPosV1 = 0;
4265 unsigned CorrectPosV2 = 0;
4266 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4267 if (Mask[i] == -1) {
4275 else if (Mask[i] == i + 4)
4279 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4280 // We have 3 elements (undefs count as elements from any vector) from one
4281 // vector, and one from another.
4288 // Some special combinations that can be optimized.
4291 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4292 SelectionDAG &DAG) {
4293 MVT VT = SVOp->getSimpleValueType(0);
4296 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4299 ArrayRef<int> Mask = SVOp->getMask();
4301 // These are the special masks that may be optimized.
4302 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4303 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4304 bool MatchEvenMask = true;
4305 bool MatchOddMask = true;
4306 for (int i=0; i<8; ++i) {
4307 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4308 MatchEvenMask = false;
4309 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4310 MatchOddMask = false;
4313 if (!MatchEvenMask && !MatchOddMask)
4316 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4318 SDValue Op0 = SVOp->getOperand(0);
4319 SDValue Op1 = SVOp->getOperand(1);
4321 if (MatchEvenMask) {
4322 // Shift the second operand right to 32 bits.
4323 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4324 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4326 // Shift the first operand left to 32 bits.
4327 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4328 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4330 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4331 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4334 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4335 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4336 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4337 bool HasInt256, bool V2IsSplat = false) {
4339 assert(VT.getSizeInBits() >= 128 &&
4340 "Unsupported vector type for unpckl");
4342 unsigned NumElts = VT.getVectorNumElements();
4343 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4344 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4347 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4348 "Unsupported vector type for unpckh");
4350 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4351 unsigned NumLanes = VT.getSizeInBits()/128;
4352 unsigned NumLaneElts = NumElts/NumLanes;
4354 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4355 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4356 int BitI = Mask[l+i];
4357 int BitI1 = Mask[l+i+1];
4358 if (!isUndefOrEqual(BitI, j))
4361 if (!isUndefOrEqual(BitI1, NumElts))
4364 if (!isUndefOrEqual(BitI1, j + NumElts))
4373 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4374 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4375 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4376 bool HasInt256, bool V2IsSplat = false) {
4377 assert(VT.getSizeInBits() >= 128 &&
4378 "Unsupported vector type for unpckh");
4380 unsigned NumElts = VT.getVectorNumElements();
4381 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4382 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4385 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4386 "Unsupported vector type for unpckh");
4388 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4389 unsigned NumLanes = VT.getSizeInBits()/128;
4390 unsigned NumLaneElts = NumElts/NumLanes;
4392 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4393 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4394 int BitI = Mask[l+i];
4395 int BitI1 = Mask[l+i+1];
4396 if (!isUndefOrEqual(BitI, j))
4399 if (isUndefOrEqual(BitI1, NumElts))
4402 if (!isUndefOrEqual(BitI1, j+NumElts))
4410 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4411 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4413 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4414 unsigned NumElts = VT.getVectorNumElements();
4415 bool Is256BitVec = VT.is256BitVector();
4417 if (VT.is512BitVector())
4419 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4420 "Unsupported vector type for unpckh");
4422 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4423 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4426 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4427 // FIXME: Need a better way to get rid of this, there's no latency difference
4428 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4429 // the former later. We should also remove the "_undef" special mask.
4430 if (NumElts == 4 && Is256BitVec)
4433 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4434 // independently on 128-bit lanes.
4435 unsigned NumLanes = VT.getSizeInBits()/128;
4436 unsigned NumLaneElts = NumElts/NumLanes;
4438 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4439 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4440 int BitI = Mask[l+i];
4441 int BitI1 = Mask[l+i+1];
4443 if (!isUndefOrEqual(BitI, j))
4445 if (!isUndefOrEqual(BitI1, j))
4453 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4454 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4456 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4457 unsigned NumElts = VT.getVectorNumElements();
4459 if (VT.is512BitVector())
4462 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4463 "Unsupported vector type for unpckh");
4465 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4466 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4469 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4470 // independently on 128-bit lanes.
4471 unsigned NumLanes = VT.getSizeInBits()/128;
4472 unsigned NumLaneElts = NumElts/NumLanes;
4474 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4475 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4476 int BitI = Mask[l+i];
4477 int BitI1 = Mask[l+i+1];
4478 if (!isUndefOrEqual(BitI, j))
4480 if (!isUndefOrEqual(BitI1, j))
4487 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4488 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4489 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4490 if (!VT.is512BitVector())
4493 unsigned NumElts = VT.getVectorNumElements();
4494 unsigned HalfSize = NumElts/2;
4495 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4496 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4501 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4502 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4510 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4511 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4512 /// MOVSD, and MOVD, i.e. setting the lowest element.
4513 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4514 if (VT.getVectorElementType().getSizeInBits() < 32)
4516 if (!VT.is128BitVector())
4519 unsigned NumElts = VT.getVectorNumElements();
4521 if (!isUndefOrEqual(Mask[0], NumElts))
4524 for (unsigned i = 1; i != NumElts; ++i)
4525 if (!isUndefOrEqual(Mask[i], i))
4531 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4532 /// as permutations between 128-bit chunks or halves. As an example: this
4534 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4535 /// The first half comes from the second half of V1 and the second half from the
4536 /// the second half of V2.
4537 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4538 if (!HasFp256 || !VT.is256BitVector())
4541 // The shuffle result is divided into half A and half B. In total the two
4542 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4543 // B must come from C, D, E or F.
4544 unsigned HalfSize = VT.getVectorNumElements()/2;
4545 bool MatchA = false, MatchB = false;
4547 // Check if A comes from one of C, D, E, F.
4548 for (unsigned Half = 0; Half != 4; ++Half) {
4549 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4555 // Check if B comes from one of C, D, E, F.
4556 for (unsigned Half = 0; Half != 4; ++Half) {
4557 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4563 return MatchA && MatchB;
4566 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4567 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4568 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4569 MVT VT = SVOp->getSimpleValueType(0);
4571 unsigned HalfSize = VT.getVectorNumElements()/2;
4573 unsigned FstHalf = 0, SndHalf = 0;
4574 for (unsigned i = 0; i < HalfSize; ++i) {
4575 if (SVOp->getMaskElt(i) > 0) {
4576 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4580 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4581 if (SVOp->getMaskElt(i) > 0) {
4582 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4587 return (FstHalf | (SndHalf << 4));
4590 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4591 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4592 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4596 unsigned NumElts = VT.getVectorNumElements();
4598 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4599 for (unsigned i = 0; i != NumElts; ++i) {
4602 Imm8 |= Mask[i] << (i*2);
4607 unsigned LaneSize = 4;
4608 SmallVector<int, 4> MaskVal(LaneSize, -1);
4610 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4611 for (unsigned i = 0; i != LaneSize; ++i) {
4612 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4616 if (MaskVal[i] < 0) {
4617 MaskVal[i] = Mask[i+l] - l;
4618 Imm8 |= MaskVal[i] << (i*2);
4621 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4628 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4629 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4630 /// Note that VPERMIL mask matching is different depending whether theunderlying
4631 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4632 /// to the same elements of the low, but to the higher half of the source.
4633 /// In VPERMILPD the two lanes could be shuffled independently of each other
4634 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4635 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4636 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4637 if (VT.getSizeInBits() < 256 || EltSize < 32)
4639 bool symetricMaskRequired = (EltSize == 32);
4640 unsigned NumElts = VT.getVectorNumElements();
4642 unsigned NumLanes = VT.getSizeInBits()/128;
4643 unsigned LaneSize = NumElts/NumLanes;
4644 // 2 or 4 elements in one lane
4646 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4647 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4648 for (unsigned i = 0; i != LaneSize; ++i) {
4649 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4651 if (symetricMaskRequired) {
4652 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4653 ExpectedMaskVal[i] = Mask[i+l] - l;
4656 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4664 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4665 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4666 /// element of vector 2 and the other elements to come from vector 1 in order.
4667 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4668 bool V2IsSplat = false, bool V2IsUndef = false) {
4669 if (!VT.is128BitVector())
4672 unsigned NumOps = VT.getVectorNumElements();
4673 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4676 if (!isUndefOrEqual(Mask[0], 0))
4679 for (unsigned i = 1; i != NumOps; ++i)
4680 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4681 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4682 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4688 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4689 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4690 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4691 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4692 const X86Subtarget *Subtarget) {
4693 if (!Subtarget->hasSSE3())
4696 unsigned NumElems = VT.getVectorNumElements();
4698 if ((VT.is128BitVector() && NumElems != 4) ||
4699 (VT.is256BitVector() && NumElems != 8) ||
4700 (VT.is512BitVector() && NumElems != 16))
4703 // "i+1" is the value the indexed mask element must have
4704 for (unsigned i = 0; i != NumElems; i += 2)
4705 if (!isUndefOrEqual(Mask[i], i+1) ||
4706 !isUndefOrEqual(Mask[i+1], i+1))
4712 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4713 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4714 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4715 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4716 const X86Subtarget *Subtarget) {
4717 if (!Subtarget->hasSSE3())
4720 unsigned NumElems = VT.getVectorNumElements();
4722 if ((VT.is128BitVector() && NumElems != 4) ||
4723 (VT.is256BitVector() && NumElems != 8) ||
4724 (VT.is512BitVector() && NumElems != 16))
4727 // "i" is the value the indexed mask element must have
4728 for (unsigned i = 0; i != NumElems; i += 2)
4729 if (!isUndefOrEqual(Mask[i], i) ||
4730 !isUndefOrEqual(Mask[i+1], i))
4736 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4737 /// specifies a shuffle of elements that is suitable for input to 256-bit
4738 /// version of MOVDDUP.
4739 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4740 if (!HasFp256 || !VT.is256BitVector())
4743 unsigned NumElts = VT.getVectorNumElements();
4747 for (unsigned i = 0; i != NumElts/2; ++i)
4748 if (!isUndefOrEqual(Mask[i], 0))
4750 for (unsigned i = NumElts/2; i != NumElts; ++i)
4751 if (!isUndefOrEqual(Mask[i], NumElts/2))
4756 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4757 /// specifies a shuffle of elements that is suitable for input to 128-bit
4758 /// version of MOVDDUP.
4759 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4760 if (!VT.is128BitVector())
4763 unsigned e = VT.getVectorNumElements() / 2;
4764 for (unsigned i = 0; i != e; ++i)
4765 if (!isUndefOrEqual(Mask[i], i))
4767 for (unsigned i = 0; i != e; ++i)
4768 if (!isUndefOrEqual(Mask[e+i], i))
4773 /// isVEXTRACTIndex - Return true if the specified
4774 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4775 /// suitable for instruction that extract 128 or 256 bit vectors
4776 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4777 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4778 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4781 // The index should be aligned on a vecWidth-bit boundary.
4783 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4785 MVT VT = N->getSimpleValueType(0);
4786 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4787 bool Result = (Index * ElSize) % vecWidth == 0;
4792 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4793 /// operand specifies a subvector insert that is suitable for input to
4794 /// insertion of 128 or 256-bit subvectors
4795 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4796 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4797 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4799 // The index should be aligned on a vecWidth-bit boundary.
4801 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4803 MVT VT = N->getSimpleValueType(0);
4804 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4805 bool Result = (Index * ElSize) % vecWidth == 0;
4810 bool X86::isVINSERT128Index(SDNode *N) {
4811 return isVINSERTIndex(N, 128);
4814 bool X86::isVINSERT256Index(SDNode *N) {
4815 return isVINSERTIndex(N, 256);
4818 bool X86::isVEXTRACT128Index(SDNode *N) {
4819 return isVEXTRACTIndex(N, 128);
4822 bool X86::isVEXTRACT256Index(SDNode *N) {
4823 return isVEXTRACTIndex(N, 256);
4826 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4827 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4828 /// Handles 128-bit and 256-bit.
4829 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4830 MVT VT = N->getSimpleValueType(0);
4832 assert((VT.getSizeInBits() >= 128) &&
4833 "Unsupported vector type for PSHUF/SHUFP");
4835 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4836 // independently on 128-bit lanes.
4837 unsigned NumElts = VT.getVectorNumElements();
4838 unsigned NumLanes = VT.getSizeInBits()/128;
4839 unsigned NumLaneElts = NumElts/NumLanes;
4841 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4842 "Only supports 2, 4 or 8 elements per lane");
4844 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4846 for (unsigned i = 0; i != NumElts; ++i) {
4847 int Elt = N->getMaskElt(i);
4848 if (Elt < 0) continue;
4849 Elt &= NumLaneElts - 1;
4850 unsigned ShAmt = (i << Shift) % 8;
4851 Mask |= Elt << ShAmt;
4857 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4858 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4859 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4860 MVT VT = N->getSimpleValueType(0);
4862 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4863 "Unsupported vector type for PSHUFHW");
4865 unsigned NumElts = VT.getVectorNumElements();
4868 for (unsigned l = 0; l != NumElts; l += 8) {
4869 // 8 nodes per lane, but we only care about the last 4.
4870 for (unsigned i = 0; i < 4; ++i) {
4871 int Elt = N->getMaskElt(l+i+4);
4872 if (Elt < 0) continue;
4873 Elt &= 0x3; // only 2-bits.
4874 Mask |= Elt << (i * 2);
4881 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4882 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4883 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4884 MVT VT = N->getSimpleValueType(0);
4886 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4887 "Unsupported vector type for PSHUFHW");
4889 unsigned NumElts = VT.getVectorNumElements();
4892 for (unsigned l = 0; l != NumElts; l += 8) {
4893 // 8 nodes per lane, but we only care about the first 4.
4894 for (unsigned i = 0; i < 4; ++i) {
4895 int Elt = N->getMaskElt(l+i);
4896 if (Elt < 0) continue;
4897 Elt &= 0x3; // only 2-bits
4898 Mask |= Elt << (i * 2);
4905 /// \brief Return the appropriate immediate to shuffle the specified
4906 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4907 /// VALIGN (if Interlane is true) instructions.
4908 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4910 MVT VT = SVOp->getSimpleValueType(0);
4911 unsigned EltSize = InterLane ? 1 :
4912 VT.getVectorElementType().getSizeInBits() >> 3;
4914 unsigned NumElts = VT.getVectorNumElements();
4915 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4916 unsigned NumLaneElts = NumElts/NumLanes;
4920 for (i = 0; i != NumElts; ++i) {
4921 Val = SVOp->getMaskElt(i);
4925 if (Val >= (int)NumElts)
4926 Val -= NumElts - NumLaneElts;
4928 assert(Val - i > 0 && "PALIGNR imm should be positive");
4929 return (Val - i) * EltSize;
4932 /// \brief Return the appropriate immediate to shuffle the specified
4933 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4934 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4935 return getShuffleAlignrImmediate(SVOp, false);
4938 /// \brief Return the appropriate immediate to shuffle the specified
4939 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4940 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4941 return getShuffleAlignrImmediate(SVOp, true);
4945 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4946 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4947 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4948 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4951 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4953 MVT VecVT = N->getOperand(0).getSimpleValueType();
4954 MVT ElVT = VecVT.getVectorElementType();
4956 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4957 return Index / NumElemsPerChunk;
4960 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4961 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4962 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4963 llvm_unreachable("Illegal insert subvector for VINSERT");
4966 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4968 MVT VecVT = N->getSimpleValueType(0);
4969 MVT ElVT = VecVT.getVectorElementType();
4971 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4972 return Index / NumElemsPerChunk;
4975 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4976 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4977 /// and VINSERTI128 instructions.
4978 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4979 return getExtractVEXTRACTImmediate(N, 128);
4982 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4983 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4984 /// and VINSERTI64x4 instructions.
4985 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4986 return getExtractVEXTRACTImmediate(N, 256);
4989 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4990 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4991 /// and VINSERTI128 instructions.
4992 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4993 return getInsertVINSERTImmediate(N, 128);
4996 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4997 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4998 /// and VINSERTI64x4 instructions.
4999 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
5000 return getInsertVINSERTImmediate(N, 256);
5003 /// isZero - Returns true if Elt is a constant integer zero
5004 static bool isZero(SDValue V) {
5005 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
5006 return C && C->isNullValue();
5009 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
5011 bool X86::isZeroNode(SDValue Elt) {
5014 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
5015 return CFP->getValueAPF().isPosZero();
5019 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5020 /// match movhlps. The lower half elements should come from upper half of
5021 /// V1 (and in order), and the upper half elements should come from the upper
5022 /// half of V2 (and in order).
5023 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5024 if (!VT.is128BitVector())
5026 if (VT.getVectorNumElements() != 4)
5028 for (unsigned i = 0, e = 2; i != e; ++i)
5029 if (!isUndefOrEqual(Mask[i], i+2))
5031 for (unsigned i = 2; i != 4; ++i)
5032 if (!isUndefOrEqual(Mask[i], i+4))
5037 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5038 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5040 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5041 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5043 N = N->getOperand(0).getNode();
5044 if (!ISD::isNON_EXTLoad(N))
5047 *LD = cast<LoadSDNode>(N);
5051 // Test whether the given value is a vector value which will be legalized
5053 static bool WillBeConstantPoolLoad(SDNode *N) {
5054 if (N->getOpcode() != ISD::BUILD_VECTOR)
5057 // Check for any non-constant elements.
5058 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5059 switch (N->getOperand(i).getNode()->getOpcode()) {
5061 case ISD::ConstantFP:
5068 // Vectors of all-zeros and all-ones are materialized with special
5069 // instructions rather than being loaded.
5070 return !ISD::isBuildVectorAllZeros(N) &&
5071 !ISD::isBuildVectorAllOnes(N);
5074 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5075 /// match movlp{s|d}. The lower half elements should come from lower half of
5076 /// V1 (and in order), and the upper half elements should come from the upper
5077 /// half of V2 (and in order). And since V1 will become the source of the
5078 /// MOVLP, it must be either a vector load or a scalar load to vector.
5079 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5080 ArrayRef<int> Mask, MVT VT) {
5081 if (!VT.is128BitVector())
5084 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5086 // Is V2 is a vector load, don't do this transformation. We will try to use
5087 // load folding shufps op.
5088 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5091 unsigned NumElems = VT.getVectorNumElements();
5093 if (NumElems != 2 && NumElems != 4)
5095 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5096 if (!isUndefOrEqual(Mask[i], i))
5098 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5099 if (!isUndefOrEqual(Mask[i], i+NumElems))
5104 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5105 /// to an zero vector.
5106 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5107 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5108 SDValue V1 = N->getOperand(0);
5109 SDValue V2 = N->getOperand(1);
5110 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5111 for (unsigned i = 0; i != NumElems; ++i) {
5112 int Idx = N->getMaskElt(i);
5113 if (Idx >= (int)NumElems) {
5114 unsigned Opc = V2.getOpcode();
5115 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5117 if (Opc != ISD::BUILD_VECTOR ||
5118 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5120 } else if (Idx >= 0) {
5121 unsigned Opc = V1.getOpcode();
5122 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5124 if (Opc != ISD::BUILD_VECTOR ||
5125 !X86::isZeroNode(V1.getOperand(Idx)))
5132 /// getZeroVector - Returns a vector of specified type with all zero elements.
5134 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5135 SelectionDAG &DAG, SDLoc dl) {
5136 assert(VT.isVector() && "Expected a vector type");
5138 // Always build SSE zero vectors as <4 x i32> bitcasted
5139 // to their dest type. This ensures they get CSE'd.
5141 if (VT.is128BitVector()) { // SSE
5142 if (Subtarget->hasSSE2()) { // SSE2
5143 SDValue Cst = DAG.getConstant(0, MVT::i32);
5144 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5146 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5147 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5149 } else if (VT.is256BitVector()) { // AVX
5150 if (Subtarget->hasInt256()) { // AVX2
5151 SDValue Cst = DAG.getConstant(0, MVT::i32);
5152 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5153 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5155 // 256-bit logic and arithmetic instructions in AVX are all
5156 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5157 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5158 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5159 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5161 } else if (VT.is512BitVector()) { // AVX-512
5162 SDValue Cst = DAG.getConstant(0, MVT::i32);
5163 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5164 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5165 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5166 } else if (VT.getScalarType() == MVT::i1) {
5167 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5168 SDValue Cst = DAG.getConstant(0, MVT::i1);
5169 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5170 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5172 llvm_unreachable("Unexpected vector type");
5174 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5177 /// getOnesVector - Returns a vector of specified type with all bits set.
5178 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5179 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5180 /// Then bitcast to their original type, ensuring they get CSE'd.
5181 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5183 assert(VT.isVector() && "Expected a vector type");
5185 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5187 if (VT.is256BitVector()) {
5188 if (HasInt256) { // AVX2
5189 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5190 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5192 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5193 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5195 } else if (VT.is128BitVector()) {
5196 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5198 llvm_unreachable("Unexpected vector type");
5200 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5203 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5204 /// that point to V2 points to its first element.
5205 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5206 for (unsigned i = 0; i != NumElems; ++i) {
5207 if (Mask[i] > (int)NumElems) {
5213 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5214 /// operation of specified width.
5215 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5217 unsigned NumElems = VT.getVectorNumElements();
5218 SmallVector<int, 8> Mask;
5219 Mask.push_back(NumElems);
5220 for (unsigned i = 1; i != NumElems; ++i)
5222 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5225 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5226 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5228 unsigned NumElems = VT.getVectorNumElements();
5229 SmallVector<int, 8> Mask;
5230 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5232 Mask.push_back(i + NumElems);
5234 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5237 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5238 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5240 unsigned NumElems = VT.getVectorNumElements();
5241 SmallVector<int, 8> Mask;
5242 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5243 Mask.push_back(i + Half);
5244 Mask.push_back(i + NumElems + Half);
5246 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5249 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5250 // a generic shuffle instruction because the target has no such instructions.
5251 // Generate shuffles which repeat i16 and i8 several times until they can be
5252 // represented by v4f32 and then be manipulated by target suported shuffles.
5253 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5254 MVT VT = V.getSimpleValueType();
5255 int NumElems = VT.getVectorNumElements();
5258 while (NumElems > 4) {
5259 if (EltNo < NumElems/2) {
5260 V = getUnpackl(DAG, dl, VT, V, V);
5262 V = getUnpackh(DAG, dl, VT, V, V);
5263 EltNo -= NumElems/2;
5270 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5271 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5272 MVT VT = V.getSimpleValueType();
5275 if (VT.is128BitVector()) {
5276 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5277 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5278 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5280 } else if (VT.is256BitVector()) {
5281 // To use VPERMILPS to splat scalars, the second half of indicies must
5282 // refer to the higher part, which is a duplication of the lower one,
5283 // because VPERMILPS can only handle in-lane permutations.
5284 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5285 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5287 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5288 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5291 llvm_unreachable("Vector size not supported");
5293 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5296 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5297 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5298 MVT SrcVT = SV->getSimpleValueType(0);
5299 SDValue V1 = SV->getOperand(0);
5302 int EltNo = SV->getSplatIndex();
5303 int NumElems = SrcVT.getVectorNumElements();
5304 bool Is256BitVec = SrcVT.is256BitVector();
5306 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5307 "Unknown how to promote splat for type");
5309 // Extract the 128-bit part containing the splat element and update
5310 // the splat element index when it refers to the higher register.
5312 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5313 if (EltNo >= NumElems/2)
5314 EltNo -= NumElems/2;
5317 // All i16 and i8 vector types can't be used directly by a generic shuffle
5318 // instruction because the target has no such instruction. Generate shuffles
5319 // which repeat i16 and i8 several times until they fit in i32, and then can
5320 // be manipulated by target suported shuffles.
5321 MVT EltVT = SrcVT.getVectorElementType();
5322 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5323 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5325 // Recreate the 256-bit vector and place the same 128-bit vector
5326 // into the low and high part. This is necessary because we want
5327 // to use VPERM* to shuffle the vectors
5329 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5332 return getLegalSplat(DAG, V1, EltNo);
5335 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5336 /// vector of zero or undef vector. This produces a shuffle where the low
5337 /// element of V2 is swizzled into the zero/undef vector, landing at element
5338 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5339 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5341 const X86Subtarget *Subtarget,
5342 SelectionDAG &DAG) {
5343 MVT VT = V2.getSimpleValueType();
5345 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5346 unsigned NumElems = VT.getVectorNumElements();
5347 SmallVector<int, 16> MaskVec;
5348 for (unsigned i = 0; i != NumElems; ++i)
5349 // If this is the insertion idx, put the low elt of V2 here.
5350 MaskVec.push_back(i == Idx ? NumElems : i);
5351 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5354 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5355 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5356 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5357 /// shuffles which use a single input multiple times, and in those cases it will
5358 /// adjust the mask to only have indices within that single input.
5359 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5360 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5361 unsigned NumElems = VT.getVectorNumElements();
5365 bool IsFakeUnary = false;
5366 switch(N->getOpcode()) {
5367 case X86ISD::BLENDI:
5368 ImmN = N->getOperand(N->getNumOperands()-1);
5369 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5372 ImmN = N->getOperand(N->getNumOperands()-1);
5373 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5374 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5376 case X86ISD::UNPCKH:
5377 DecodeUNPCKHMask(VT, Mask);
5378 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5380 case X86ISD::UNPCKL:
5381 DecodeUNPCKLMask(VT, Mask);
5382 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5384 case X86ISD::MOVHLPS:
5385 DecodeMOVHLPSMask(NumElems, Mask);
5386 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5388 case X86ISD::MOVLHPS:
5389 DecodeMOVLHPSMask(NumElems, Mask);
5390 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5392 case X86ISD::PALIGNR:
5393 ImmN = N->getOperand(N->getNumOperands()-1);
5394 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5396 case X86ISD::PSHUFD:
5397 case X86ISD::VPERMILPI:
5398 ImmN = N->getOperand(N->getNumOperands()-1);
5399 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5402 case X86ISD::PSHUFHW:
5403 ImmN = N->getOperand(N->getNumOperands()-1);
5404 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5407 case X86ISD::PSHUFLW:
5408 ImmN = N->getOperand(N->getNumOperands()-1);
5409 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5412 case X86ISD::PSHUFB: {
5414 SDValue MaskNode = N->getOperand(1);
5415 while (MaskNode->getOpcode() == ISD::BITCAST)
5416 MaskNode = MaskNode->getOperand(0);
5418 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5419 // If we have a build-vector, then things are easy.
5420 EVT VT = MaskNode.getValueType();
5421 assert(VT.isVector() &&
5422 "Can't produce a non-vector with a build_vector!");
5423 if (!VT.isInteger())
5426 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5428 SmallVector<uint64_t, 32> RawMask;
5429 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5430 SDValue Op = MaskNode->getOperand(i);
5431 if (Op->getOpcode() == ISD::UNDEF) {
5432 RawMask.push_back((uint64_t)SM_SentinelUndef);
5435 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5438 APInt MaskElement = CN->getAPIntValue();
5440 // We now have to decode the element which could be any integer size and
5441 // extract each byte of it.
5442 for (int j = 0; j < NumBytesPerElement; ++j) {
5443 // Note that this is x86 and so always little endian: the low byte is
5444 // the first byte of the mask.
5445 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5446 MaskElement = MaskElement.lshr(8);
5449 DecodePSHUFBMask(RawMask, Mask);
5453 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5457 SDValue Ptr = MaskLoad->getBasePtr();
5458 if (Ptr->getOpcode() == X86ISD::Wrapper)
5459 Ptr = Ptr->getOperand(0);
5461 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5462 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5465 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5466 // FIXME: Support AVX-512 here.
5467 Type *Ty = C->getType();
5468 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5469 Ty->getVectorNumElements() != 32))
5472 DecodePSHUFBMask(C, Mask);
5478 case X86ISD::VPERMI:
5479 ImmN = N->getOperand(N->getNumOperands()-1);
5480 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5484 case X86ISD::MOVSD: {
5485 // The index 0 always comes from the first element of the second source,
5486 // this is why MOVSS and MOVSD are used in the first place. The other
5487 // elements come from the other positions of the first source vector
5488 Mask.push_back(NumElems);
5489 for (unsigned i = 1; i != NumElems; ++i) {
5494 case X86ISD::VPERM2X128:
5495 ImmN = N->getOperand(N->getNumOperands()-1);
5496 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5497 if (Mask.empty()) return false;
5499 case X86ISD::MOVSLDUP:
5500 DecodeMOVSLDUPMask(VT, Mask);
5502 case X86ISD::MOVSHDUP:
5503 DecodeMOVSHDUPMask(VT, Mask);
5505 case X86ISD::MOVDDUP:
5506 case X86ISD::MOVLHPD:
5507 case X86ISD::MOVLPD:
5508 case X86ISD::MOVLPS:
5509 // Not yet implemented
5511 default: llvm_unreachable("unknown target shuffle node");
5514 // If we have a fake unary shuffle, the shuffle mask is spread across two
5515 // inputs that are actually the same node. Re-map the mask to always point
5516 // into the first input.
5519 if (M >= (int)Mask.size())
5525 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5526 /// element of the result of the vector shuffle.
5527 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5530 return SDValue(); // Limit search depth.
5532 SDValue V = SDValue(N, 0);
5533 EVT VT = V.getValueType();
5534 unsigned Opcode = V.getOpcode();
5536 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5537 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5538 int Elt = SV->getMaskElt(Index);
5541 return DAG.getUNDEF(VT.getVectorElementType());
5543 unsigned NumElems = VT.getVectorNumElements();
5544 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5545 : SV->getOperand(1);
5546 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5549 // Recurse into target specific vector shuffles to find scalars.
5550 if (isTargetShuffle(Opcode)) {
5551 MVT ShufVT = V.getSimpleValueType();
5552 unsigned NumElems = ShufVT.getVectorNumElements();
5553 SmallVector<int, 16> ShuffleMask;
5556 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5559 int Elt = ShuffleMask[Index];
5561 return DAG.getUNDEF(ShufVT.getVectorElementType());
5563 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5565 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5569 // Actual nodes that may contain scalar elements
5570 if (Opcode == ISD::BITCAST) {
5571 V = V.getOperand(0);
5572 EVT SrcVT = V.getValueType();
5573 unsigned NumElems = VT.getVectorNumElements();
5575 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5579 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5580 return (Index == 0) ? V.getOperand(0)
5581 : DAG.getUNDEF(VT.getVectorElementType());
5583 if (V.getOpcode() == ISD::BUILD_VECTOR)
5584 return V.getOperand(Index);
5589 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5590 /// shuffle operation which come from a consecutively from a zero. The
5591 /// search can start in two different directions, from left or right.
5592 /// We count undefs as zeros until PreferredNum is reached.
5593 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5594 unsigned NumElems, bool ZerosFromLeft,
5596 unsigned PreferredNum = -1U) {
5597 unsigned NumZeros = 0;
5598 for (unsigned i = 0; i != NumElems; ++i) {
5599 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5600 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5604 if (X86::isZeroNode(Elt))
5606 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5607 NumZeros = std::min(NumZeros + 1, PreferredNum);
5615 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5616 /// correspond consecutively to elements from one of the vector operands,
5617 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5619 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5620 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5621 unsigned NumElems, unsigned &OpNum) {
5622 bool SeenV1 = false;
5623 bool SeenV2 = false;
5625 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5626 int Idx = SVOp->getMaskElt(i);
5627 // Ignore undef indicies
5631 if (Idx < (int)NumElems)
5636 // Only accept consecutive elements from the same vector
5637 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5641 OpNum = SeenV1 ? 0 : 1;
5645 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5646 /// logical left shift of a vector.
5647 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5648 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5650 SVOp->getSimpleValueType(0).getVectorNumElements();
5651 unsigned NumZeros = getNumOfConsecutiveZeros(
5652 SVOp, NumElems, false /* check zeros from right */, DAG,
5653 SVOp->getMaskElt(0));
5659 // Considering the elements in the mask that are not consecutive zeros,
5660 // check if they consecutively come from only one of the source vectors.
5662 // V1 = {X, A, B, C} 0
5664 // vector_shuffle V1, V2 <1, 2, 3, X>
5666 if (!isShuffleMaskConsecutive(SVOp,
5667 0, // Mask Start Index
5668 NumElems-NumZeros, // Mask End Index(exclusive)
5669 NumZeros, // Where to start looking in the src vector
5670 NumElems, // Number of elements in vector
5671 OpSrc)) // Which source operand ?
5676 ShVal = SVOp->getOperand(OpSrc);
5680 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5681 /// logical left shift of a vector.
5682 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5683 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5685 SVOp->getSimpleValueType(0).getVectorNumElements();
5686 unsigned NumZeros = getNumOfConsecutiveZeros(
5687 SVOp, NumElems, true /* check zeros from left */, DAG,
5688 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5694 // Considering the elements in the mask that are not consecutive zeros,
5695 // check if they consecutively come from only one of the source vectors.
5697 // 0 { A, B, X, X } = V2
5699 // vector_shuffle V1, V2 <X, X, 4, 5>
5701 if (!isShuffleMaskConsecutive(SVOp,
5702 NumZeros, // Mask Start Index
5703 NumElems, // Mask End Index(exclusive)
5704 0, // Where to start looking in the src vector
5705 NumElems, // Number of elements in vector
5706 OpSrc)) // Which source operand ?
5711 ShVal = SVOp->getOperand(OpSrc);
5715 /// isVectorShift - Returns true if the shuffle can be implemented as a
5716 /// logical left or right shift of a vector.
5717 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5718 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5719 // Although the logic below support any bitwidth size, there are no
5720 // shift instructions which handle more than 128-bit vectors.
5721 if (!SVOp->getSimpleValueType(0).is128BitVector())
5724 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5725 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5731 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5733 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5734 unsigned NumNonZero, unsigned NumZero,
5736 const X86Subtarget* Subtarget,
5737 const TargetLowering &TLI) {
5744 for (unsigned i = 0; i < 16; ++i) {
5745 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5746 if (ThisIsNonZero && First) {
5748 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5750 V = DAG.getUNDEF(MVT::v8i16);
5755 SDValue ThisElt, LastElt;
5756 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5757 if (LastIsNonZero) {
5758 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5759 MVT::i16, Op.getOperand(i-1));
5761 if (ThisIsNonZero) {
5762 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5763 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5764 ThisElt, DAG.getConstant(8, MVT::i8));
5766 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5770 if (ThisElt.getNode())
5771 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5772 DAG.getIntPtrConstant(i/2));
5776 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5779 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5781 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5782 unsigned NumNonZero, unsigned NumZero,
5784 const X86Subtarget* Subtarget,
5785 const TargetLowering &TLI) {
5792 for (unsigned i = 0; i < 8; ++i) {
5793 bool isNonZero = (NonZeros & (1 << i)) != 0;
5797 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5799 V = DAG.getUNDEF(MVT::v8i16);
5802 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5803 MVT::v8i16, V, Op.getOperand(i),
5804 DAG.getIntPtrConstant(i));
5811 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5812 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5813 const X86Subtarget *Subtarget,
5814 const TargetLowering &TLI) {
5815 // Find all zeroable elements.
5817 for (int i=0; i < 4; ++i) {
5818 SDValue Elt = Op->getOperand(i);
5819 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5821 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5822 [](bool M) { return !M; }) > 1 &&
5823 "We expect at least two non-zero elements!");
5825 // We only know how to deal with build_vector nodes where elements are either
5826 // zeroable or extract_vector_elt with constant index.
5827 SDValue FirstNonZero;
5828 unsigned FirstNonZeroIdx;
5829 for (unsigned i=0; i < 4; ++i) {
5832 SDValue Elt = Op->getOperand(i);
5833 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5834 !isa<ConstantSDNode>(Elt.getOperand(1)))
5836 // Make sure that this node is extracting from a 128-bit vector.
5837 MVT VT = Elt.getOperand(0).getSimpleValueType();
5838 if (!VT.is128BitVector())
5840 if (!FirstNonZero.getNode()) {
5842 FirstNonZeroIdx = i;
5846 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5847 SDValue V1 = FirstNonZero.getOperand(0);
5848 MVT VT = V1.getSimpleValueType();
5850 // See if this build_vector can be lowered as a blend with zero.
5852 unsigned EltMaskIdx, EltIdx;
5854 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5855 if (Zeroable[EltIdx]) {
5856 // The zero vector will be on the right hand side.
5857 Mask[EltIdx] = EltIdx+4;
5861 Elt = Op->getOperand(EltIdx);
5862 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5863 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5864 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5866 Mask[EltIdx] = EltIdx;
5870 // Let the shuffle legalizer deal with blend operations.
5871 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5872 if (V1.getSimpleValueType() != VT)
5873 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5874 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5877 // See if we can lower this build_vector to a INSERTPS.
5878 if (!Subtarget->hasSSE41())
5881 SDValue V2 = Elt.getOperand(0);
5882 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5885 bool CanFold = true;
5886 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5890 SDValue Current = Op->getOperand(i);
5891 SDValue SrcVector = Current->getOperand(0);
5894 CanFold = SrcVector == V1 &&
5895 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5901 assert(V1.getNode() && "Expected at least two non-zero elements!");
5902 if (V1.getSimpleValueType() != MVT::v4f32)
5903 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5904 if (V2.getSimpleValueType() != MVT::v4f32)
5905 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5907 // Ok, we can emit an INSERTPS instruction.
5909 for (int i = 0; i < 4; ++i)
5913 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5914 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5915 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5916 DAG.getIntPtrConstant(InsertPSMask));
5917 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5920 /// getVShift - Return a vector logical shift node.
5922 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5923 unsigned NumBits, SelectionDAG &DAG,
5924 const TargetLowering &TLI, SDLoc dl) {
5925 assert(VT.is128BitVector() && "Unknown type for VShift");
5926 EVT ShVT = MVT::v2i64;
5927 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5928 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5929 return DAG.getNode(ISD::BITCAST, dl, VT,
5930 DAG.getNode(Opc, dl, ShVT, SrcOp,
5931 DAG.getConstant(NumBits,
5932 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5936 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5938 // Check if the scalar load can be widened into a vector load. And if
5939 // the address is "base + cst" see if the cst can be "absorbed" into
5940 // the shuffle mask.
5941 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5942 SDValue Ptr = LD->getBasePtr();
5943 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5945 EVT PVT = LD->getValueType(0);
5946 if (PVT != MVT::i32 && PVT != MVT::f32)
5951 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5952 FI = FINode->getIndex();
5954 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5955 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5956 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5957 Offset = Ptr.getConstantOperandVal(1);
5958 Ptr = Ptr.getOperand(0);
5963 // FIXME: 256-bit vector instructions don't require a strict alignment,
5964 // improve this code to support it better.
5965 unsigned RequiredAlign = VT.getSizeInBits()/8;
5966 SDValue Chain = LD->getChain();
5967 // Make sure the stack object alignment is at least 16 or 32.
5968 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5969 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5970 if (MFI->isFixedObjectIndex(FI)) {
5971 // Can't change the alignment. FIXME: It's possible to compute
5972 // the exact stack offset and reference FI + adjust offset instead.
5973 // If someone *really* cares about this. That's the way to implement it.
5976 MFI->setObjectAlignment(FI, RequiredAlign);
5980 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5981 // Ptr + (Offset & ~15).
5984 if ((Offset % RequiredAlign) & 3)
5986 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5988 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5989 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5991 int EltNo = (Offset - StartOffset) >> 2;
5992 unsigned NumElems = VT.getVectorNumElements();
5994 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5995 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5996 LD->getPointerInfo().getWithOffset(StartOffset),
5997 false, false, false, 0);
5999 SmallVector<int, 8> Mask;
6000 for (unsigned i = 0; i != NumElems; ++i)
6001 Mask.push_back(EltNo);
6003 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
6009 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
6010 /// vector of type 'VT', see if the elements can be replaced by a single large
6011 /// load which has the same value as a build_vector whose operands are 'elts'.
6013 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
6015 /// FIXME: we'd also like to handle the case where the last elements are zero
6016 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
6017 /// There's even a handy isZeroNode for that purpose.
6018 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6019 SDLoc &DL, SelectionDAG &DAG,
6020 bool isAfterLegalize) {
6021 EVT EltVT = VT.getVectorElementType();
6022 unsigned NumElems = Elts.size();
6024 LoadSDNode *LDBase = nullptr;
6025 unsigned LastLoadedElt = -1U;
6027 // For each element in the initializer, see if we've found a load or an undef.
6028 // If we don't find an initial load element, or later load elements are
6029 // non-consecutive, bail out.
6030 for (unsigned i = 0; i < NumElems; ++i) {
6031 SDValue Elt = Elts[i];
6033 if (!Elt.getNode() ||
6034 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6037 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6039 LDBase = cast<LoadSDNode>(Elt.getNode());
6043 if (Elt.getOpcode() == ISD::UNDEF)
6046 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6047 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6052 // If we have found an entire vector of loads and undefs, then return a large
6053 // load of the entire vector width starting at the base pointer. If we found
6054 // consecutive loads for the low half, generate a vzext_load node.
6055 if (LastLoadedElt == NumElems - 1) {
6057 if (isAfterLegalize &&
6058 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6061 SDValue NewLd = SDValue();
6063 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6064 LDBase->getPointerInfo(), LDBase->isVolatile(),
6065 LDBase->isNonTemporal(), LDBase->isInvariant(),
6066 LDBase->getAlignment());
6068 if (LDBase->hasAnyUseOfValue(1)) {
6069 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6071 SDValue(NewLd.getNode(), 1));
6072 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6073 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6074 SDValue(NewLd.getNode(), 1));
6080 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6081 //of a v4i32 / v4f32. It's probably worth generalizing.
6082 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6083 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6084 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6085 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6087 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6088 LDBase->getPointerInfo(),
6089 LDBase->getAlignment(),
6090 false/*isVolatile*/, true/*ReadMem*/,
6093 // Make sure the newly-created LOAD is in the same position as LDBase in
6094 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6095 // update uses of LDBase's output chain to use the TokenFactor.
6096 if (LDBase->hasAnyUseOfValue(1)) {
6097 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6098 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6099 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6100 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6101 SDValue(ResNode.getNode(), 1));
6104 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6109 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6110 /// to generate a splat value for the following cases:
6111 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6112 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6113 /// a scalar load, or a constant.
6114 /// The VBROADCAST node is returned when a pattern is found,
6115 /// or SDValue() otherwise.
6116 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6117 SelectionDAG &DAG) {
6118 // VBROADCAST requires AVX.
6119 // TODO: Splats could be generated for non-AVX CPUs using SSE
6120 // instructions, but there's less potential gain for only 128-bit vectors.
6121 if (!Subtarget->hasAVX())
6124 MVT VT = Op.getSimpleValueType();
6127 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6128 "Unsupported vector type for broadcast.");
6133 switch (Op.getOpcode()) {
6135 // Unknown pattern found.
6138 case ISD::BUILD_VECTOR: {
6139 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6140 BitVector UndefElements;
6141 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6143 // We need a splat of a single value to use broadcast, and it doesn't
6144 // make any sense if the value is only in one element of the vector.
6145 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6149 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6150 Ld.getOpcode() == ISD::ConstantFP);
6152 // Make sure that all of the users of a non-constant load are from the
6153 // BUILD_VECTOR node.
6154 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6159 case ISD::VECTOR_SHUFFLE: {
6160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6162 // Shuffles must have a splat mask where the first element is
6164 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6167 SDValue Sc = Op.getOperand(0);
6168 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6169 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6171 if (!Subtarget->hasInt256())
6174 // Use the register form of the broadcast instruction available on AVX2.
6175 if (VT.getSizeInBits() >= 256)
6176 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6177 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6180 Ld = Sc.getOperand(0);
6181 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6182 Ld.getOpcode() == ISD::ConstantFP);
6184 // The scalar_to_vector node and the suspected
6185 // load node must have exactly one user.
6186 // Constants may have multiple users.
6188 // AVX-512 has register version of the broadcast
6189 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6190 Ld.getValueType().getSizeInBits() >= 32;
6191 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6198 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6199 bool IsGE256 = (VT.getSizeInBits() >= 256);
6201 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6202 // instruction to save 8 or more bytes of constant pool data.
6203 // TODO: If multiple splats are generated to load the same constant,
6204 // it may be detrimental to overall size. There needs to be a way to detect
6205 // that condition to know if this is truly a size win.
6206 const Function *F = DAG.getMachineFunction().getFunction();
6207 bool OptForSize = F->getAttributes().
6208 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6210 // Handle broadcasting a single constant scalar from the constant pool
6212 // On Sandybridge (no AVX2), it is still better to load a constant vector
6213 // from the constant pool and not to broadcast it from a scalar.
6214 // But override that restriction when optimizing for size.
6215 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6216 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6217 EVT CVT = Ld.getValueType();
6218 assert(!CVT.isVector() && "Must not broadcast a vector type");
6220 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6221 // For size optimization, also splat v2f64 and v2i64, and for size opt
6222 // with AVX2, also splat i8 and i16.
6223 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6224 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6225 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6226 const Constant *C = nullptr;
6227 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6228 C = CI->getConstantIntValue();
6229 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6230 C = CF->getConstantFPValue();
6232 assert(C && "Invalid constant type");
6234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6235 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6236 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6237 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6238 MachinePointerInfo::getConstantPool(),
6239 false, false, false, Alignment);
6241 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6245 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6247 // Handle AVX2 in-register broadcasts.
6248 if (!IsLoad && Subtarget->hasInt256() &&
6249 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6250 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6252 // The scalar source must be a normal load.
6256 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6257 (Subtarget->hasVLX() && ScalarSize == 64))
6258 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6260 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6261 // double since there is no vbroadcastsd xmm
6262 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6263 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6264 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6267 // Unsupported broadcast.
6271 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6272 /// underlying vector and index.
6274 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6276 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6278 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6279 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6282 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6284 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6286 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6287 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6290 // In this case the vector is the extract_subvector expression and the index
6291 // is 2, as specified by the shuffle.
6292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6293 SDValue ShuffleVec = SVOp->getOperand(0);
6294 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6295 assert(ShuffleVecVT.getVectorElementType() ==
6296 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6298 int ShuffleIdx = SVOp->getMaskElt(Idx);
6299 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6300 ExtractedFromVec = ShuffleVec;
6306 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6307 MVT VT = Op.getSimpleValueType();
6309 // Skip if insert_vec_elt is not supported.
6310 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6311 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6315 unsigned NumElems = Op.getNumOperands();
6319 SmallVector<unsigned, 4> InsertIndices;
6320 SmallVector<int, 8> Mask(NumElems, -1);
6322 for (unsigned i = 0; i != NumElems; ++i) {
6323 unsigned Opc = Op.getOperand(i).getOpcode();
6325 if (Opc == ISD::UNDEF)
6328 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6329 // Quit if more than 1 elements need inserting.
6330 if (InsertIndices.size() > 1)
6333 InsertIndices.push_back(i);
6337 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6338 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6339 // Quit if non-constant index.
6340 if (!isa<ConstantSDNode>(ExtIdx))
6342 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6344 // Quit if extracted from vector of different type.
6345 if (ExtractedFromVec.getValueType() != VT)
6348 if (!VecIn1.getNode())
6349 VecIn1 = ExtractedFromVec;
6350 else if (VecIn1 != ExtractedFromVec) {
6351 if (!VecIn2.getNode())
6352 VecIn2 = ExtractedFromVec;
6353 else if (VecIn2 != ExtractedFromVec)
6354 // Quit if more than 2 vectors to shuffle
6358 if (ExtractedFromVec == VecIn1)
6360 else if (ExtractedFromVec == VecIn2)
6361 Mask[i] = Idx + NumElems;
6364 if (!VecIn1.getNode())
6367 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6368 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6369 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6370 unsigned Idx = InsertIndices[i];
6371 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6372 DAG.getIntPtrConstant(Idx));
6378 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6380 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6382 MVT VT = Op.getSimpleValueType();
6383 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6384 "Unexpected type in LowerBUILD_VECTORvXi1!");
6387 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6388 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6389 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6390 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6393 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6394 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6395 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6396 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6399 bool AllContants = true;
6400 uint64_t Immediate = 0;
6401 int NonConstIdx = -1;
6402 bool IsSplat = true;
6403 unsigned NumNonConsts = 0;
6404 unsigned NumConsts = 0;
6405 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6406 SDValue In = Op.getOperand(idx);
6407 if (In.getOpcode() == ISD::UNDEF)
6409 if (!isa<ConstantSDNode>(In)) {
6410 AllContants = false;
6415 if (cast<ConstantSDNode>(In)->getZExtValue())
6416 Immediate |= (1ULL << idx);
6418 if (In != Op.getOperand(0))
6423 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6424 DAG.getConstant(Immediate, MVT::i16));
6425 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6426 DAG.getIntPtrConstant(0));
6429 if (NumNonConsts == 1 && NonConstIdx != 0) {
6432 SDValue VecAsImm = DAG.getConstant(Immediate,
6433 MVT::getIntegerVT(VT.getSizeInBits()));
6434 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6437 DstVec = DAG.getUNDEF(VT);
6438 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6439 Op.getOperand(NonConstIdx),
6440 DAG.getIntPtrConstant(NonConstIdx));
6442 if (!IsSplat && (NonConstIdx != 0))
6443 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6444 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6447 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6448 DAG.getConstant(-1, SelectVT),
6449 DAG.getConstant(0, SelectVT));
6451 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6452 DAG.getConstant((Immediate | 1), SelectVT),
6453 DAG.getConstant(Immediate, SelectVT));
6454 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6457 /// \brief Return true if \p N implements a horizontal binop and return the
6458 /// operands for the horizontal binop into V0 and V1.
6460 /// This is a helper function of PerformBUILD_VECTORCombine.
6461 /// This function checks that the build_vector \p N in input implements a
6462 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6463 /// operation to match.
6464 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6465 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6466 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6469 /// This function only analyzes elements of \p N whose indices are
6470 /// in range [BaseIdx, LastIdx).
6471 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6473 unsigned BaseIdx, unsigned LastIdx,
6474 SDValue &V0, SDValue &V1) {
6475 EVT VT = N->getValueType(0);
6477 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6478 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6479 "Invalid Vector in input!");
6481 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6482 bool CanFold = true;
6483 unsigned ExpectedVExtractIdx = BaseIdx;
6484 unsigned NumElts = LastIdx - BaseIdx;
6485 V0 = DAG.getUNDEF(VT);
6486 V1 = DAG.getUNDEF(VT);
6488 // Check if N implements a horizontal binop.
6489 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6490 SDValue Op = N->getOperand(i + BaseIdx);
6493 if (Op->getOpcode() == ISD::UNDEF) {
6494 // Update the expected vector extract index.
6495 if (i * 2 == NumElts)
6496 ExpectedVExtractIdx = BaseIdx;
6497 ExpectedVExtractIdx += 2;
6501 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6506 SDValue Op0 = Op.getOperand(0);
6507 SDValue Op1 = Op.getOperand(1);
6509 // Try to match the following pattern:
6510 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6511 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6512 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6513 Op0.getOperand(0) == Op1.getOperand(0) &&
6514 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6515 isa<ConstantSDNode>(Op1.getOperand(1)));
6519 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6520 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6522 if (i * 2 < NumElts) {
6523 if (V0.getOpcode() == ISD::UNDEF)
6524 V0 = Op0.getOperand(0);
6526 if (V1.getOpcode() == ISD::UNDEF)
6527 V1 = Op0.getOperand(0);
6528 if (i * 2 == NumElts)
6529 ExpectedVExtractIdx = BaseIdx;
6532 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6533 if (I0 == ExpectedVExtractIdx)
6534 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6535 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6536 // Try to match the following dag sequence:
6537 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6538 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6542 ExpectedVExtractIdx += 2;
6548 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6549 /// a concat_vector.
6551 /// This is a helper function of PerformBUILD_VECTORCombine.
6552 /// This function expects two 256-bit vectors called V0 and V1.
6553 /// At first, each vector is split into two separate 128-bit vectors.
6554 /// Then, the resulting 128-bit vectors are used to implement two
6555 /// horizontal binary operations.
6557 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6559 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6560 /// the two new horizontal binop.
6561 /// When Mode is set, the first horizontal binop dag node would take as input
6562 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6563 /// horizontal binop dag node would take as input the lower 128-bit of V1
6564 /// and the upper 128-bit of V1.
6566 /// HADD V0_LO, V0_HI
6567 /// HADD V1_LO, V1_HI
6569 /// Otherwise, the first horizontal binop dag node takes as input the lower
6570 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6571 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6573 /// HADD V0_LO, V1_LO
6574 /// HADD V0_HI, V1_HI
6576 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6577 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6578 /// the upper 128-bits of the result.
6579 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6580 SDLoc DL, SelectionDAG &DAG,
6581 unsigned X86Opcode, bool Mode,
6582 bool isUndefLO, bool isUndefHI) {
6583 EVT VT = V0.getValueType();
6584 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6585 "Invalid nodes in input!");
6587 unsigned NumElts = VT.getVectorNumElements();
6588 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6589 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6590 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6591 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6592 EVT NewVT = V0_LO.getValueType();
6594 SDValue LO = DAG.getUNDEF(NewVT);
6595 SDValue HI = DAG.getUNDEF(NewVT);
6598 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6599 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6600 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6601 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6602 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6604 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6605 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6606 V1_LO->getOpcode() != ISD::UNDEF))
6607 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6609 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6610 V1_HI->getOpcode() != ISD::UNDEF))
6611 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6614 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6617 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6618 /// sequence of 'vadd + vsub + blendi'.
6619 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6620 const X86Subtarget *Subtarget) {
6622 EVT VT = BV->getValueType(0);
6623 unsigned NumElts = VT.getVectorNumElements();
6624 SDValue InVec0 = DAG.getUNDEF(VT);
6625 SDValue InVec1 = DAG.getUNDEF(VT);
6627 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6628 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6630 // Odd-numbered elements in the input build vector are obtained from
6631 // adding two integer/float elements.
6632 // Even-numbered elements in the input build vector are obtained from
6633 // subtracting two integer/float elements.
6634 unsigned ExpectedOpcode = ISD::FSUB;
6635 unsigned NextExpectedOpcode = ISD::FADD;
6636 bool AddFound = false;
6637 bool SubFound = false;
6639 for (unsigned i = 0, e = NumElts; i != e; i++) {
6640 SDValue Op = BV->getOperand(i);
6642 // Skip 'undef' values.
6643 unsigned Opcode = Op.getOpcode();
6644 if (Opcode == ISD::UNDEF) {
6645 std::swap(ExpectedOpcode, NextExpectedOpcode);
6649 // Early exit if we found an unexpected opcode.
6650 if (Opcode != ExpectedOpcode)
6653 SDValue Op0 = Op.getOperand(0);
6654 SDValue Op1 = Op.getOperand(1);
6656 // Try to match the following pattern:
6657 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6658 // Early exit if we cannot match that sequence.
6659 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6660 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6661 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6662 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6663 Op0.getOperand(1) != Op1.getOperand(1))
6666 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6670 // We found a valid add/sub node. Update the information accordingly.
6676 // Update InVec0 and InVec1.
6677 if (InVec0.getOpcode() == ISD::UNDEF)
6678 InVec0 = Op0.getOperand(0);
6679 if (InVec1.getOpcode() == ISD::UNDEF)
6680 InVec1 = Op1.getOperand(0);
6682 // Make sure that operands in input to each add/sub node always
6683 // come from a same pair of vectors.
6684 if (InVec0 != Op0.getOperand(0)) {
6685 if (ExpectedOpcode == ISD::FSUB)
6688 // FADD is commutable. Try to commute the operands
6689 // and then test again.
6690 std::swap(Op0, Op1);
6691 if (InVec0 != Op0.getOperand(0))
6695 if (InVec1 != Op1.getOperand(0))
6698 // Update the pair of expected opcodes.
6699 std::swap(ExpectedOpcode, NextExpectedOpcode);
6702 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6703 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6704 InVec1.getOpcode() != ISD::UNDEF)
6705 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6710 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6711 const X86Subtarget *Subtarget) {
6713 EVT VT = N->getValueType(0);
6714 unsigned NumElts = VT.getVectorNumElements();
6715 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6716 SDValue InVec0, InVec1;
6718 // Try to match an ADDSUB.
6719 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6720 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6721 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6722 if (Value.getNode())
6726 // Try to match horizontal ADD/SUB.
6727 unsigned NumUndefsLO = 0;
6728 unsigned NumUndefsHI = 0;
6729 unsigned Half = NumElts/2;
6731 // Count the number of UNDEF operands in the build_vector in input.
6732 for (unsigned i = 0, e = Half; i != e; ++i)
6733 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6736 for (unsigned i = Half, e = NumElts; i != e; ++i)
6737 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6740 // Early exit if this is either a build_vector of all UNDEFs or all the
6741 // operands but one are UNDEF.
6742 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6745 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6746 // Try to match an SSE3 float HADD/HSUB.
6747 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6748 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6750 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6751 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6752 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6753 // Try to match an SSSE3 integer HADD/HSUB.
6754 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6755 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6757 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6758 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6761 if (!Subtarget->hasAVX())
6764 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6765 // Try to match an AVX horizontal add/sub of packed single/double
6766 // precision floating point values from 256-bit vectors.
6767 SDValue InVec2, InVec3;
6768 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6769 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6770 ((InVec0.getOpcode() == ISD::UNDEF ||
6771 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6772 ((InVec1.getOpcode() == ISD::UNDEF ||
6773 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6774 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6776 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6777 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6778 ((InVec0.getOpcode() == ISD::UNDEF ||
6779 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6780 ((InVec1.getOpcode() == ISD::UNDEF ||
6781 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6782 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6783 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6784 // Try to match an AVX2 horizontal add/sub of signed integers.
6785 SDValue InVec2, InVec3;
6787 bool CanFold = true;
6789 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6790 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6791 ((InVec0.getOpcode() == ISD::UNDEF ||
6792 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6793 ((InVec1.getOpcode() == ISD::UNDEF ||
6794 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6795 X86Opcode = X86ISD::HADD;
6796 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6797 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6798 ((InVec0.getOpcode() == ISD::UNDEF ||
6799 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6800 ((InVec1.getOpcode() == ISD::UNDEF ||
6801 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6802 X86Opcode = X86ISD::HSUB;
6807 // Fold this build_vector into a single horizontal add/sub.
6808 // Do this only if the target has AVX2.
6809 if (Subtarget->hasAVX2())
6810 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6812 // Do not try to expand this build_vector into a pair of horizontal
6813 // add/sub if we can emit a pair of scalar add/sub.
6814 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6817 // Convert this build_vector into a pair of horizontal binop followed by
6819 bool isUndefLO = NumUndefsLO == Half;
6820 bool isUndefHI = NumUndefsHI == Half;
6821 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6822 isUndefLO, isUndefHI);
6826 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6827 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6829 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6830 X86Opcode = X86ISD::HADD;
6831 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6832 X86Opcode = X86ISD::HSUB;
6833 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6834 X86Opcode = X86ISD::FHADD;
6835 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6836 X86Opcode = X86ISD::FHSUB;
6840 // Don't try to expand this build_vector into a pair of horizontal add/sub
6841 // if we can simply emit a pair of scalar add/sub.
6842 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6845 // Convert this build_vector into two horizontal add/sub followed by
6847 bool isUndefLO = NumUndefsLO == Half;
6848 bool isUndefHI = NumUndefsHI == Half;
6849 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6850 isUndefLO, isUndefHI);
6857 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6860 MVT VT = Op.getSimpleValueType();
6861 MVT ExtVT = VT.getVectorElementType();
6862 unsigned NumElems = Op.getNumOperands();
6864 // Generate vectors for predicate vectors.
6865 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6866 return LowerBUILD_VECTORvXi1(Op, DAG);
6868 // Vectors containing all zeros can be matched by pxor and xorps later
6869 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6870 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6871 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6872 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6875 return getZeroVector(VT, Subtarget, DAG, dl);
6878 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6879 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6880 // vpcmpeqd on 256-bit vectors.
6881 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6882 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6885 if (!VT.is512BitVector())
6886 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6889 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6890 if (Broadcast.getNode())
6893 unsigned EVTBits = ExtVT.getSizeInBits();
6895 unsigned NumZero = 0;
6896 unsigned NumNonZero = 0;
6897 unsigned NonZeros = 0;
6898 bool IsAllConstants = true;
6899 SmallSet<SDValue, 8> Values;
6900 for (unsigned i = 0; i < NumElems; ++i) {
6901 SDValue Elt = Op.getOperand(i);
6902 if (Elt.getOpcode() == ISD::UNDEF)
6905 if (Elt.getOpcode() != ISD::Constant &&
6906 Elt.getOpcode() != ISD::ConstantFP)
6907 IsAllConstants = false;
6908 if (X86::isZeroNode(Elt))
6911 NonZeros |= (1 << i);
6916 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6917 if (NumNonZero == 0)
6918 return DAG.getUNDEF(VT);
6920 // Special case for single non-zero, non-undef, element.
6921 if (NumNonZero == 1) {
6922 unsigned Idx = countTrailingZeros(NonZeros);
6923 SDValue Item = Op.getOperand(Idx);
6925 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6926 // the value are obviously zero, truncate the value to i32 and do the
6927 // insertion that way. Only do this if the value is non-constant or if the
6928 // value is a constant being inserted into element 0. It is cheaper to do
6929 // a constant pool load than it is to do a movd + shuffle.
6930 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6931 (!IsAllConstants || Idx == 0)) {
6932 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6934 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6935 EVT VecVT = MVT::v4i32;
6936 unsigned VecElts = 4;
6938 // Truncate the value (which may itself be a constant) to i32, and
6939 // convert it to a vector with movd (S2V+shuffle to zero extend).
6940 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6941 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6943 // If using the new shuffle lowering, just directly insert this.
6944 if (ExperimentalVectorShuffleLowering)
6946 ISD::BITCAST, dl, VT,
6947 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6949 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6951 // Now we have our 32-bit value zero extended in the low element of
6952 // a vector. If Idx != 0, swizzle it into place.
6954 SmallVector<int, 4> Mask;
6955 Mask.push_back(Idx);
6956 for (unsigned i = 1; i != VecElts; ++i)
6958 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6961 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6965 // If we have a constant or non-constant insertion into the low element of
6966 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6967 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6968 // depending on what the source datatype is.
6971 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6973 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6974 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6975 if (VT.is256BitVector() || VT.is512BitVector()) {
6976 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6977 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6978 Item, DAG.getIntPtrConstant(0));
6980 assert(VT.is128BitVector() && "Expected an SSE value type!");
6981 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6982 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6983 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6986 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6987 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6988 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6989 if (VT.is256BitVector()) {
6990 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6991 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6993 assert(VT.is128BitVector() && "Expected an SSE value type!");
6994 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6996 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
7000 // Is it a vector logical left shift?
7001 if (NumElems == 2 && Idx == 1 &&
7002 X86::isZeroNode(Op.getOperand(0)) &&
7003 !X86::isZeroNode(Op.getOperand(1))) {
7004 unsigned NumBits = VT.getSizeInBits();
7005 return getVShift(true, VT,
7006 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7007 VT, Op.getOperand(1)),
7008 NumBits/2, DAG, *this, dl);
7011 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7014 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7015 // is a non-constant being inserted into an element other than the low one,
7016 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7017 // movd/movss) to move this into the low element, then shuffle it into
7019 if (EVTBits == 32) {
7020 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7022 // If using the new shuffle lowering, just directly insert this.
7023 if (ExperimentalVectorShuffleLowering)
7024 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7026 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7027 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7028 SmallVector<int, 8> MaskVec;
7029 for (unsigned i = 0; i != NumElems; ++i)
7030 MaskVec.push_back(i == Idx ? 0 : 1);
7031 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7035 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7036 if (Values.size() == 1) {
7037 if (EVTBits == 32) {
7038 // Instead of a shuffle like this:
7039 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7040 // Check if it's possible to issue this instead.
7041 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7042 unsigned Idx = countTrailingZeros(NonZeros);
7043 SDValue Item = Op.getOperand(Idx);
7044 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7045 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7050 // A vector full of immediates; various special cases are already
7051 // handled, so this is best done with a single constant-pool load.
7055 // For AVX-length vectors, see if we can use a vector load to get all of the
7056 // elements, otherwise build the individual 128-bit pieces and use
7057 // shuffles to put them in place.
7058 if (VT.is256BitVector() || VT.is512BitVector()) {
7059 SmallVector<SDValue, 64> V;
7060 for (unsigned i = 0; i != NumElems; ++i)
7061 V.push_back(Op.getOperand(i));
7063 // Check for a build vector of consecutive loads.
7064 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7067 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7069 // Build both the lower and upper subvector.
7070 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7071 makeArrayRef(&V[0], NumElems/2));
7072 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7073 makeArrayRef(&V[NumElems / 2], NumElems/2));
7075 // Recreate the wider vector with the lower and upper part.
7076 if (VT.is256BitVector())
7077 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7078 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7081 // Let legalizer expand 2-wide build_vectors.
7082 if (EVTBits == 64) {
7083 if (NumNonZero == 1) {
7084 // One half is zero or undef.
7085 unsigned Idx = countTrailingZeros(NonZeros);
7086 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7087 Op.getOperand(Idx));
7088 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7093 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7094 if (EVTBits == 8 && NumElems == 16) {
7095 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7097 if (V.getNode()) return V;
7100 if (EVTBits == 16 && NumElems == 8) {
7101 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7103 if (V.getNode()) return V;
7106 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7107 if (EVTBits == 32 && NumElems == 4) {
7108 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7113 // If element VT is == 32 bits, turn it into a number of shuffles.
7114 SmallVector<SDValue, 8> V(NumElems);
7115 if (NumElems == 4 && NumZero > 0) {
7116 for (unsigned i = 0; i < 4; ++i) {
7117 bool isZero = !(NonZeros & (1 << i));
7119 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7121 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7124 for (unsigned i = 0; i < 2; ++i) {
7125 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7128 V[i] = V[i*2]; // Must be a zero vector.
7131 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7134 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7137 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7142 bool Reverse1 = (NonZeros & 0x3) == 2;
7143 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7147 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7148 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7150 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7153 if (Values.size() > 1 && VT.is128BitVector()) {
7154 // Check for a build vector of consecutive loads.
7155 for (unsigned i = 0; i < NumElems; ++i)
7156 V[i] = Op.getOperand(i);
7158 // Check for elements which are consecutive loads.
7159 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7163 // Check for a build vector from mostly shuffle plus few inserting.
7164 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7168 // For SSE 4.1, use insertps to put the high elements into the low element.
7169 if (getSubtarget()->hasSSE41()) {
7171 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7172 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7174 Result = DAG.getUNDEF(VT);
7176 for (unsigned i = 1; i < NumElems; ++i) {
7177 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7178 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7179 Op.getOperand(i), DAG.getIntPtrConstant(i));
7184 // Otherwise, expand into a number of unpckl*, start by extending each of
7185 // our (non-undef) elements to the full vector width with the element in the
7186 // bottom slot of the vector (which generates no code for SSE).
7187 for (unsigned i = 0; i < NumElems; ++i) {
7188 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7189 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7191 V[i] = DAG.getUNDEF(VT);
7194 // Next, we iteratively mix elements, e.g. for v4f32:
7195 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7196 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7197 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7198 unsigned EltStride = NumElems >> 1;
7199 while (EltStride != 0) {
7200 for (unsigned i = 0; i < EltStride; ++i) {
7201 // If V[i+EltStride] is undef and this is the first round of mixing,
7202 // then it is safe to just drop this shuffle: V[i] is already in the
7203 // right place, the one element (since it's the first round) being
7204 // inserted as undef can be dropped. This isn't safe for successive
7205 // rounds because they will permute elements within both vectors.
7206 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7207 EltStride == NumElems/2)
7210 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7219 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7220 // to create 256-bit vectors from two other 128-bit ones.
7221 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7223 MVT ResVT = Op.getSimpleValueType();
7225 assert((ResVT.is256BitVector() ||
7226 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7228 SDValue V1 = Op.getOperand(0);
7229 SDValue V2 = Op.getOperand(1);
7230 unsigned NumElems = ResVT.getVectorNumElements();
7231 if(ResVT.is256BitVector())
7232 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7234 if (Op.getNumOperands() == 4) {
7235 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7236 ResVT.getVectorNumElements()/2);
7237 SDValue V3 = Op.getOperand(2);
7238 SDValue V4 = Op.getOperand(3);
7239 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7240 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7242 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7245 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7246 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7247 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7248 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7249 Op.getNumOperands() == 4)));
7251 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7252 // from two other 128-bit ones.
7254 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7255 return LowerAVXCONCAT_VECTORS(Op, DAG);
7259 //===----------------------------------------------------------------------===//
7260 // Vector shuffle lowering
7262 // This is an experimental code path for lowering vector shuffles on x86. It is
7263 // designed to handle arbitrary vector shuffles and blends, gracefully
7264 // degrading performance as necessary. It works hard to recognize idiomatic
7265 // shuffles and lower them to optimal instruction patterns without leaving
7266 // a framework that allows reasonably efficient handling of all vector shuffle
7268 //===----------------------------------------------------------------------===//
7270 /// \brief Tiny helper function to identify a no-op mask.
7272 /// This is a somewhat boring predicate function. It checks whether the mask
7273 /// array input, which is assumed to be a single-input shuffle mask of the kind
7274 /// used by the X86 shuffle instructions (not a fully general
7275 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7276 /// in-place shuffle are 'no-op's.
7277 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7278 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7279 if (Mask[i] != -1 && Mask[i] != i)
7284 /// \brief Helper function to classify a mask as a single-input mask.
7286 /// This isn't a generic single-input test because in the vector shuffle
7287 /// lowering we canonicalize single inputs to be the first input operand. This
7288 /// means we can more quickly test for a single input by only checking whether
7289 /// an input from the second operand exists. We also assume that the size of
7290 /// mask corresponds to the size of the input vectors which isn't true in the
7291 /// fully general case.
7292 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7294 if (M >= (int)Mask.size())
7299 /// \brief Test whether there are elements crossing 128-bit lanes in this
7302 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7303 /// and we routinely test for these.
7304 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7305 int LaneSize = 128 / VT.getScalarSizeInBits();
7306 int Size = Mask.size();
7307 for (int i = 0; i < Size; ++i)
7308 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7313 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7315 /// This checks a shuffle mask to see if it is performing the same
7316 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7317 /// that it is also not lane-crossing. It may however involve a blend from the
7318 /// same lane of a second vector.
7320 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7321 /// non-trivial to compute in the face of undef lanes. The representation is
7322 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7323 /// entries from both V1 and V2 inputs to the wider mask.
7325 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7326 SmallVectorImpl<int> &RepeatedMask) {
7327 int LaneSize = 128 / VT.getScalarSizeInBits();
7328 RepeatedMask.resize(LaneSize, -1);
7329 int Size = Mask.size();
7330 for (int i = 0; i < Size; ++i) {
7333 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7334 // This entry crosses lanes, so there is no way to model this shuffle.
7337 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7338 if (RepeatedMask[i % LaneSize] == -1)
7339 // This is the first non-undef entry in this slot of a 128-bit lane.
7340 RepeatedMask[i % LaneSize] =
7341 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7342 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7343 // Found a mismatch with the repeated mask.
7349 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7350 // 2013 will allow us to use it as a non-type template parameter.
7353 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7355 /// See its documentation for details.
7356 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7357 if (Mask.size() != Args.size())
7359 for (int i = 0, e = Mask.size(); i < e; ++i) {
7360 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7361 if (Mask[i] != -1 && Mask[i] != *Args[i])
7369 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7372 /// This is a fast way to test a shuffle mask against a fixed pattern:
7374 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7376 /// It returns true if the mask is exactly as wide as the argument list, and
7377 /// each element of the mask is either -1 (signifying undef) or the value given
7378 /// in the argument.
7379 static const VariadicFunction1<
7380 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7382 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7384 /// This helper function produces an 8-bit shuffle immediate corresponding to
7385 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7386 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7389 /// NB: We rely heavily on "undef" masks preserving the input lane.
7390 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7391 SelectionDAG &DAG) {
7392 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7393 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7394 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7395 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7396 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7399 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7400 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7401 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7402 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7403 return DAG.getConstant(Imm, MVT::i8);
7406 /// \brief Try to emit a blend instruction for a shuffle.
7408 /// This doesn't do any checks for the availability of instructions for blending
7409 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7410 /// be matched in the backend with the type given. What it does check for is
7411 /// that the shuffle mask is in fact a blend.
7412 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7413 SDValue V2, ArrayRef<int> Mask,
7414 const X86Subtarget *Subtarget,
7415 SelectionDAG &DAG) {
7417 unsigned BlendMask = 0;
7418 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7419 if (Mask[i] >= Size) {
7420 if (Mask[i] != i + Size)
7421 return SDValue(); // Shuffled V2 input!
7422 BlendMask |= 1u << i;
7425 if (Mask[i] >= 0 && Mask[i] != i)
7426 return SDValue(); // Shuffled V1 input!
7428 switch (VT.SimpleTy) {
7433 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7434 DAG.getConstant(BlendMask, MVT::i8));
7438 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7442 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7443 // that instruction.
7444 if (Subtarget->hasAVX2()) {
7445 // Scale the blend by the number of 32-bit dwords per element.
7446 int Scale = VT.getScalarSizeInBits() / 32;
7448 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7449 if (Mask[i] >= Size)
7450 for (int j = 0; j < Scale; ++j)
7451 BlendMask |= 1u << (i * Scale + j);
7453 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7454 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7455 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7456 return DAG.getNode(ISD::BITCAST, DL, VT,
7457 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7458 DAG.getConstant(BlendMask, MVT::i8)));
7462 // For integer shuffles we need to expand the mask and cast the inputs to
7463 // v8i16s prior to blending.
7464 int Scale = 8 / VT.getVectorNumElements();
7466 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7467 if (Mask[i] >= Size)
7468 for (int j = 0; j < Scale; ++j)
7469 BlendMask |= 1u << (i * Scale + j);
7471 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7472 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7473 return DAG.getNode(ISD::BITCAST, DL, VT,
7474 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7475 DAG.getConstant(BlendMask, MVT::i8)));
7479 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7480 SmallVector<int, 8> RepeatedMask;
7481 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7482 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7483 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7485 for (int i = 0; i < 8; ++i)
7486 if (RepeatedMask[i] >= 16)
7487 BlendMask |= 1u << i;
7488 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7489 DAG.getConstant(BlendMask, MVT::i8));
7494 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7495 // Scale the blend by the number of bytes per element.
7496 int Scale = VT.getScalarSizeInBits() / 8;
7497 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7499 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7500 // mix of LLVM's code generator and the x86 backend. We tell the code
7501 // generator that boolean values in the elements of an x86 vector register
7502 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7503 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7504 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7505 // of the element (the remaining are ignored) and 0 in that high bit would
7506 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7507 // the LLVM model for boolean values in vector elements gets the relevant
7508 // bit set, it is set backwards and over constrained relative to x86's
7510 SDValue VSELECTMask[32];
7511 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7512 for (int j = 0; j < Scale; ++j)
7513 VSELECTMask[Scale * i + j] =
7514 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7515 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7517 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7518 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7520 ISD::BITCAST, DL, VT,
7521 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7522 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7527 llvm_unreachable("Not a supported integer vector type!");
7531 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7532 /// unblended shuffles followed by an unshuffled blend.
7534 /// This matches the extremely common pattern for handling combined
7535 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7537 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7541 SelectionDAG &DAG) {
7542 // Shuffle the input elements into the desired positions in V1 and V2 and
7543 // blend them together.
7544 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7545 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7546 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7547 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7548 if (Mask[i] >= 0 && Mask[i] < Size) {
7549 V1Mask[i] = Mask[i];
7551 } else if (Mask[i] >= Size) {
7552 V2Mask[i] = Mask[i] - Size;
7553 BlendMask[i] = i + Size;
7556 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7557 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7558 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7561 /// \brief Try to lower a vector shuffle as a byte rotation.
7563 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7564 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7565 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7566 /// try to generically lower a vector shuffle through such an pattern. It
7567 /// does not check for the profitability of lowering either as PALIGNR or
7568 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7569 /// This matches shuffle vectors that look like:
7571 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7573 /// Essentially it concatenates V1 and V2, shifts right by some number of
7574 /// elements, and takes the low elements as the result. Note that while this is
7575 /// specified as a *right shift* because x86 is little-endian, it is a *left
7576 /// rotate* of the vector lanes.
7578 /// Note that this only handles 128-bit vector widths currently.
7579 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7582 const X86Subtarget *Subtarget,
7583 SelectionDAG &DAG) {
7584 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7586 // We need to detect various ways of spelling a rotation:
7587 // [11, 12, 13, 14, 15, 0, 1, 2]
7588 // [-1, 12, 13, 14, -1, -1, 1, -1]
7589 // [-1, -1, -1, -1, -1, -1, 1, 2]
7590 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7591 // [-1, 4, 5, 6, -1, -1, 9, -1]
7592 // [-1, 4, 5, 6, -1, -1, -1, -1]
7595 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7598 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7600 // Based on the mod-Size value of this mask element determine where
7601 // a rotated vector would have started.
7602 int StartIdx = i - (Mask[i] % Size);
7604 // The identity rotation isn't interesting, stop.
7607 // If we found the tail of a vector the rotation must be the missing
7608 // front. If we found the head of a vector, it must be how much of the head.
7609 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7612 Rotation = CandidateRotation;
7613 else if (Rotation != CandidateRotation)
7614 // The rotations don't match, so we can't match this mask.
7617 // Compute which value this mask is pointing at.
7618 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7620 // Compute which of the two target values this index should be assigned to.
7621 // This reflects whether the high elements are remaining or the low elements
7623 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7625 // Either set up this value if we've not encountered it before, or check
7626 // that it remains consistent.
7629 else if (TargetV != MaskV)
7630 // This may be a rotation, but it pulls from the inputs in some
7631 // unsupported interleaving.
7635 // Check that we successfully analyzed the mask, and normalize the results.
7636 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7637 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7643 assert(VT.getSizeInBits() == 128 &&
7644 "Rotate-based lowering only supports 128-bit lowering!");
7645 assert(Mask.size() <= 16 &&
7646 "Can shuffle at most 16 bytes in a 128-bit vector!");
7648 // The actual rotate instruction rotates bytes, so we need to scale the
7649 // rotation based on how many bytes are in the vector.
7650 int Scale = 16 / Mask.size();
7652 // SSSE3 targets can use the palignr instruction
7653 if (Subtarget->hasSSSE3()) {
7654 // Cast the inputs to v16i8 to match PALIGNR.
7655 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7656 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7658 return DAG.getNode(ISD::BITCAST, DL, VT,
7659 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7660 DAG.getConstant(Rotation * Scale, MVT::i8)));
7663 // Default SSE2 implementation
7664 int LoByteShift = 16 - Rotation * Scale;
7665 int HiByteShift = Rotation * Scale;
7667 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7668 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7669 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7671 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7672 DAG.getConstant(8 * LoByteShift, MVT::i8));
7673 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7674 DAG.getConstant(8 * HiByteShift, MVT::i8));
7675 return DAG.getNode(ISD::BITCAST, DL, VT,
7676 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7679 /// \brief Compute whether each element of a shuffle is zeroable.
7681 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7682 /// Either it is an undef element in the shuffle mask, the element of the input
7683 /// referenced is undef, or the element of the input referenced is known to be
7684 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7685 /// as many lanes with this technique as possible to simplify the remaining
7687 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7688 SDValue V1, SDValue V2) {
7689 SmallBitVector Zeroable(Mask.size(), false);
7691 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7692 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7694 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7696 // Handle the easy cases.
7697 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7702 // If this is an index into a build_vector node, dig out the input value and
7704 SDValue V = M < Size ? V1 : V2;
7705 if (V.getOpcode() != ISD::BUILD_VECTOR)
7708 SDValue Input = V.getOperand(M % Size);
7709 // The UNDEF opcode check really should be dead code here, but not quite
7710 // worth asserting on (it isn't invalid, just unexpected).
7711 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7718 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7720 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7721 /// byte-shift instructions. The mask must consist of a shifted sequential
7722 /// shuffle from one of the input vectors and zeroable elements for the
7723 /// remaining 'shifted in' elements.
7725 /// Note that this only handles 128-bit vector widths currently.
7726 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7727 SDValue V2, ArrayRef<int> Mask,
7728 SelectionDAG &DAG) {
7729 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7731 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7733 int Size = Mask.size();
7734 int Scale = 16 / Size;
7736 for (int Shift = 1; Shift < Size; Shift++) {
7737 int ByteShift = Shift * Scale;
7739 // PSRLDQ : (little-endian) right byte shift
7740 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7741 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7742 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7743 bool ZeroableRight = true;
7744 for (int i = Size - Shift; i < Size; i++) {
7745 ZeroableRight &= Zeroable[i];
7748 if (ZeroableRight) {
7749 bool ValidShiftRight1 =
7750 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Shift);
7751 bool ValidShiftRight2 =
7752 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Size + Shift);
7754 if (ValidShiftRight1 || ValidShiftRight2) {
7755 // Cast the inputs to v2i64 to match PSRLDQ.
7756 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7757 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7758 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7759 DAG.getConstant(ByteShift * 8, MVT::i8));
7760 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7764 // PSLLDQ : (little-endian) left byte shift
7765 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7766 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7767 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7768 bool ZeroableLeft = true;
7769 for (int i = 0; i < Shift; i++) {
7770 ZeroableLeft &= Zeroable[i];
7774 bool ValidShiftLeft1 =
7775 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, 0);
7776 bool ValidShiftLeft2 =
7777 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, Size);
7779 if (ValidShiftLeft1 || ValidShiftLeft2) {
7780 // Cast the inputs to v2i64 to match PSLLDQ.
7781 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7782 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7783 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7784 DAG.getConstant(ByteShift * 8, MVT::i8));
7785 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7793 /// \brief Lower a vector shuffle as a zero or any extension.
7795 /// Given a specific number of elements, element bit width, and extension
7796 /// stride, produce either a zero or any extension based on the available
7797 /// features of the subtarget.
7798 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7799 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7800 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7801 assert(Scale > 1 && "Need a scale to extend.");
7802 int EltBits = VT.getSizeInBits() / NumElements;
7803 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7804 "Only 8, 16, and 32 bit elements can be extended.");
7805 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7807 // Found a valid zext mask! Try various lowering strategies based on the
7808 // input type and available ISA extensions.
7809 if (Subtarget->hasSSE41()) {
7810 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7811 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7812 NumElements / Scale);
7813 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7814 return DAG.getNode(ISD::BITCAST, DL, VT,
7815 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7818 // For any extends we can cheat for larger element sizes and use shuffle
7819 // instructions that can fold with a load and/or copy.
7820 if (AnyExt && EltBits == 32) {
7821 int PSHUFDMask[4] = {0, -1, 1, -1};
7823 ISD::BITCAST, DL, VT,
7824 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7825 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7826 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7828 if (AnyExt && EltBits == 16 && Scale > 2) {
7829 int PSHUFDMask[4] = {0, -1, 0, -1};
7830 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7831 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7832 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7833 int PSHUFHWMask[4] = {1, -1, -1, -1};
7835 ISD::BITCAST, DL, VT,
7836 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7837 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7838 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7841 // If this would require more than 2 unpack instructions to expand, use
7842 // pshufb when available. We can only use more than 2 unpack instructions
7843 // when zero extending i8 elements which also makes it easier to use pshufb.
7844 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7845 assert(NumElements == 16 && "Unexpected byte vector width!");
7846 SDValue PSHUFBMask[16];
7847 for (int i = 0; i < 16; ++i)
7849 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7850 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7851 return DAG.getNode(ISD::BITCAST, DL, VT,
7852 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7853 DAG.getNode(ISD::BUILD_VECTOR, DL,
7854 MVT::v16i8, PSHUFBMask)));
7857 // Otherwise emit a sequence of unpacks.
7859 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7860 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7861 : getZeroVector(InputVT, Subtarget, DAG, DL);
7862 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7863 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7867 } while (Scale > 1);
7868 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7871 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7873 /// This routine will try to do everything in its power to cleverly lower
7874 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7875 /// check for the profitability of this lowering, it tries to aggressively
7876 /// match this pattern. It will use all of the micro-architectural details it
7877 /// can to emit an efficient lowering. It handles both blends with all-zero
7878 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7879 /// masking out later).
7881 /// The reason we have dedicated lowering for zext-style shuffles is that they
7882 /// are both incredibly common and often quite performance sensitive.
7883 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7884 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7885 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7886 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7888 int Bits = VT.getSizeInBits();
7889 int NumElements = Mask.size();
7891 // Define a helper function to check a particular ext-scale and lower to it if
7893 auto Lower = [&](int Scale) -> SDValue {
7896 for (int i = 0; i < NumElements; ++i) {
7898 continue; // Valid anywhere but doesn't tell us anything.
7899 if (i % Scale != 0) {
7900 // Each of the extend elements needs to be zeroable.
7904 // We no lorger are in the anyext case.
7909 // Each of the base elements needs to be consecutive indices into the
7910 // same input vector.
7911 SDValue V = Mask[i] < NumElements ? V1 : V2;
7914 else if (InputV != V)
7915 return SDValue(); // Flip-flopping inputs.
7917 if (Mask[i] % NumElements != i / Scale)
7918 return SDValue(); // Non-consecutive strided elemenst.
7921 // If we fail to find an input, we have a zero-shuffle which should always
7922 // have already been handled.
7923 // FIXME: Maybe handle this here in case during blending we end up with one?
7927 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7928 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7931 // The widest scale possible for extending is to a 64-bit integer.
7932 assert(Bits % 64 == 0 &&
7933 "The number of bits in a vector must be divisible by 64 on x86!");
7934 int NumExtElements = Bits / 64;
7936 // Each iteration, try extending the elements half as much, but into twice as
7938 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7939 assert(NumElements % NumExtElements == 0 &&
7940 "The input vector size must be divisble by the extended size.");
7941 if (SDValue V = Lower(NumElements / NumExtElements))
7945 // No viable ext lowering found.
7949 /// \brief Try to get a scalar value for a specific element of a vector.
7951 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7952 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7953 SelectionDAG &DAG) {
7954 MVT VT = V.getSimpleValueType();
7955 MVT EltVT = VT.getVectorElementType();
7956 while (V.getOpcode() == ISD::BITCAST)
7957 V = V.getOperand(0);
7958 // If the bitcasts shift the element size, we can't extract an equivalent
7960 MVT NewVT = V.getSimpleValueType();
7961 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7964 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7965 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7966 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7971 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7973 /// This is particularly important because the set of instructions varies
7974 /// significantly based on whether the operand is a load or not.
7975 static bool isShuffleFoldableLoad(SDValue V) {
7976 while (V.getOpcode() == ISD::BITCAST)
7977 V = V.getOperand(0);
7979 return ISD::isNON_EXTLoad(V.getNode());
7982 /// \brief Try to lower insertion of a single element into a zero vector.
7984 /// This is a common pattern that we have especially efficient patterns to lower
7985 /// across all subtarget feature sets.
7986 static SDValue lowerVectorShuffleAsElementInsertion(
7987 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7988 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7989 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7991 MVT EltVT = VT.getVectorElementType();
7993 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7994 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7996 bool IsV1Zeroable = true;
7997 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7998 if (i != V2Index && !Zeroable[i]) {
7999 IsV1Zeroable = false;
8003 // Check for a single input from a SCALAR_TO_VECTOR node.
8004 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
8005 // all the smarts here sunk into that routine. However, the current
8006 // lowering of BUILD_VECTOR makes that nearly impossible until the old
8007 // vector shuffle lowering is dead.
8008 if (SDValue V2S = getScalarValueForVectorElement(
8009 V2, Mask[V2Index] - Mask.size(), DAG)) {
8010 // We need to zext the scalar if it is smaller than an i32.
8011 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8012 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8013 // Using zext to expand a narrow element won't work for non-zero
8018 // Zero-extend directly to i32.
8020 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8022 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8023 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8024 EltVT == MVT::i16) {
8025 // Either not inserting from the low element of the input or the input
8026 // element size is too small to use VZEXT_MOVL to clear the high bits.
8030 if (!IsV1Zeroable) {
8031 // If V1 can't be treated as a zero vector we have fewer options to lower
8032 // this. We can't support integer vectors or non-zero targets cheaply, and
8033 // the V1 elements can't be permuted in any way.
8034 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8035 if (!VT.isFloatingPoint() || V2Index != 0)
8037 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8038 V1Mask[V2Index] = -1;
8039 if (!isNoopShuffleMask(V1Mask))
8041 // This is essentially a special case blend operation, but if we have
8042 // general purpose blend operations, they are always faster. Bail and let
8043 // the rest of the lowering handle these as blends.
8044 if (Subtarget->hasSSE41())
8047 // Otherwise, use MOVSD or MOVSS.
8048 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8049 "Only two types of floating point element types to handle!");
8050 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8054 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8056 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8059 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8060 // the desired position. Otherwise it is more efficient to do a vector
8061 // shift left. We know that we can do a vector shift left because all
8062 // the inputs are zero.
8063 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8064 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8065 V2Shuffle[V2Index] = 0;
8066 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8068 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8070 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8072 V2Index * EltVT.getSizeInBits(),
8073 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8074 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8080 /// \brief Try to lower broadcast of a single element.
8082 /// For convenience, this code also bundles all of the subtarget feature set
8083 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8084 /// a convenient way to factor it out.
8085 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8087 const X86Subtarget *Subtarget,
8088 SelectionDAG &DAG) {
8089 if (!Subtarget->hasAVX())
8091 if (VT.isInteger() && !Subtarget->hasAVX2())
8094 // Check that the mask is a broadcast.
8095 int BroadcastIdx = -1;
8097 if (M >= 0 && BroadcastIdx == -1)
8099 else if (M >= 0 && M != BroadcastIdx)
8102 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8103 "a sorted mask where the broadcast "
8106 // Go up the chain of (vector) values to try and find a scalar load that
8107 // we can combine with the broadcast.
8109 switch (V.getOpcode()) {
8110 case ISD::CONCAT_VECTORS: {
8111 int OperandSize = Mask.size() / V.getNumOperands();
8112 V = V.getOperand(BroadcastIdx / OperandSize);
8113 BroadcastIdx %= OperandSize;
8117 case ISD::INSERT_SUBVECTOR: {
8118 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8119 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8123 int BeginIdx = (int)ConstantIdx->getZExtValue();
8125 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8126 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8127 BroadcastIdx -= BeginIdx;
8138 // Check if this is a broadcast of a scalar. We special case lowering
8139 // for scalars so that we can more effectively fold with loads.
8140 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8141 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8142 V = V.getOperand(BroadcastIdx);
8144 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8146 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8148 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8149 // We can't broadcast from a vector register w/o AVX2, and we can only
8150 // broadcast from the zero-element of a vector register.
8154 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8157 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8159 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8160 /// support for floating point shuffles but not integer shuffles. These
8161 /// instructions will incur a domain crossing penalty on some chips though so
8162 /// it is better to avoid lowering through this for integer vectors where
8164 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8165 const X86Subtarget *Subtarget,
8166 SelectionDAG &DAG) {
8168 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8169 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8170 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8171 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8172 ArrayRef<int> Mask = SVOp->getMask();
8173 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8175 if (isSingleInputShuffleMask(Mask)) {
8176 // Straight shuffle of a single input vector. Simulate this by using the
8177 // single input as both of the "inputs" to this instruction..
8178 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8180 if (Subtarget->hasAVX()) {
8181 // If we have AVX, we can use VPERMILPS which will allow folding a load
8182 // into the shuffle.
8183 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8184 DAG.getConstant(SHUFPDMask, MVT::i8));
8187 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8188 DAG.getConstant(SHUFPDMask, MVT::i8));
8190 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8191 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8193 // Use dedicated unpack instructions for masks that match their pattern.
8194 if (isShuffleEquivalent(Mask, 0, 2))
8195 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8196 if (isShuffleEquivalent(Mask, 1, 3))
8197 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8199 // If we have a single input, insert that into V1 if we can do so cheaply.
8200 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8201 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8202 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8204 // Try inverting the insertion since for v2 masks it is easy to do and we
8205 // can't reliably sort the mask one way or the other.
8206 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8207 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8208 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8209 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8213 // Try to use one of the special instruction patterns to handle two common
8214 // blend patterns if a zero-blend above didn't work.
8215 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8216 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8217 // We can either use a special instruction to load over the low double or
8218 // to move just the low double.
8220 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8222 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8224 if (Subtarget->hasSSE41())
8225 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8229 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8230 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8231 DAG.getConstant(SHUFPDMask, MVT::i8));
8234 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8236 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8237 /// the integer unit to minimize domain crossing penalties. However, for blends
8238 /// it falls back to the floating point shuffle operation with appropriate bit
8240 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8241 const X86Subtarget *Subtarget,
8242 SelectionDAG &DAG) {
8244 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8245 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8246 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8247 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8248 ArrayRef<int> Mask = SVOp->getMask();
8249 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8251 if (isSingleInputShuffleMask(Mask)) {
8252 // Check for being able to broadcast a single element.
8253 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8254 Mask, Subtarget, DAG))
8257 // Straight shuffle of a single input vector. For everything from SSE2
8258 // onward this has a single fast instruction with no scary immediates.
8259 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8260 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8261 int WidenedMask[4] = {
8262 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8263 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8265 ISD::BITCAST, DL, MVT::v2i64,
8266 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8267 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8270 // Try to use byte shift instructions.
8271 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8272 DL, MVT::v2i64, V1, V2, Mask, DAG))
8275 // If we have a single input from V2 insert that into V1 if we can do so
8277 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8278 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8279 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8281 // Try inverting the insertion since for v2 masks it is easy to do and we
8282 // can't reliably sort the mask one way or the other.
8283 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8284 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8285 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8286 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8290 // Use dedicated unpack instructions for masks that match their pattern.
8291 if (isShuffleEquivalent(Mask, 0, 2))
8292 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8293 if (isShuffleEquivalent(Mask, 1, 3))
8294 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8296 if (Subtarget->hasSSE41())
8297 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8301 // Try to use byte rotation instructions.
8302 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8303 if (Subtarget->hasSSSE3())
8304 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8305 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8308 // We implement this with SHUFPD which is pretty lame because it will likely
8309 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8310 // However, all the alternatives are still more cycles and newer chips don't
8311 // have this problem. It would be really nice if x86 had better shuffles here.
8312 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8313 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8314 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8315 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8318 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8320 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8321 /// It makes no assumptions about whether this is the *best* lowering, it simply
8323 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8324 ArrayRef<int> Mask, SDValue V1,
8325 SDValue V2, SelectionDAG &DAG) {
8326 SDValue LowV = V1, HighV = V2;
8327 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8330 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8332 if (NumV2Elements == 1) {
8334 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8337 // Compute the index adjacent to V2Index and in the same half by toggling
8339 int V2AdjIndex = V2Index ^ 1;
8341 if (Mask[V2AdjIndex] == -1) {
8342 // Handles all the cases where we have a single V2 element and an undef.
8343 // This will only ever happen in the high lanes because we commute the
8344 // vector otherwise.
8346 std::swap(LowV, HighV);
8347 NewMask[V2Index] -= 4;
8349 // Handle the case where the V2 element ends up adjacent to a V1 element.
8350 // To make this work, blend them together as the first step.
8351 int V1Index = V2AdjIndex;
8352 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8353 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8354 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8356 // Now proceed to reconstruct the final blend as we have the necessary
8357 // high or low half formed.
8364 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8365 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8367 } else if (NumV2Elements == 2) {
8368 if (Mask[0] < 4 && Mask[1] < 4) {
8369 // Handle the easy case where we have V1 in the low lanes and V2 in the
8373 } else if (Mask[2] < 4 && Mask[3] < 4) {
8374 // We also handle the reversed case because this utility may get called
8375 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8376 // arrange things in the right direction.
8382 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8383 // trying to place elements directly, just blend them and set up the final
8384 // shuffle to place them.
8386 // The first two blend mask elements are for V1, the second two are for
8388 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8389 Mask[2] < 4 ? Mask[2] : Mask[3],
8390 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8391 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8392 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8393 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8395 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8398 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8399 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8400 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8401 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8404 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8405 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8408 /// \brief Lower 4-lane 32-bit floating point shuffles.
8410 /// Uses instructions exclusively from the floating point unit to minimize
8411 /// domain crossing penalties, as these are sufficient to implement all v4f32
8413 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8414 const X86Subtarget *Subtarget,
8415 SelectionDAG &DAG) {
8417 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8418 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8419 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8420 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8421 ArrayRef<int> Mask = SVOp->getMask();
8422 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8425 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8427 if (NumV2Elements == 0) {
8428 // Check for being able to broadcast a single element.
8429 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8430 Mask, Subtarget, DAG))
8433 if (Subtarget->hasAVX()) {
8434 // If we have AVX, we can use VPERMILPS which will allow folding a load
8435 // into the shuffle.
8436 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8437 getV4X86ShuffleImm8ForMask(Mask, DAG));
8440 // Otherwise, use a straight shuffle of a single input vector. We pass the
8441 // input vector to both operands to simulate this with a SHUFPS.
8442 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8443 getV4X86ShuffleImm8ForMask(Mask, DAG));
8446 // Use dedicated unpack instructions for masks that match their pattern.
8447 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8448 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8449 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8450 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8452 // There are special ways we can lower some single-element blends. However, we
8453 // have custom ways we can lower more complex single-element blends below that
8454 // we defer to if both this and BLENDPS fail to match, so restrict this to
8455 // when the V2 input is targeting element 0 of the mask -- that is the fast
8457 if (NumV2Elements == 1 && Mask[0] >= 4)
8458 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8459 Mask, Subtarget, DAG))
8462 if (Subtarget->hasSSE41())
8463 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8467 // Check for whether we can use INSERTPS to perform the blend. We only use
8468 // INSERTPS when the V1 elements are already in the correct locations
8469 // because otherwise we can just always use two SHUFPS instructions which
8470 // are much smaller to encode than a SHUFPS and an INSERTPS.
8471 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8473 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8476 // When using INSERTPS we can zero any lane of the destination. Collect
8477 // the zero inputs into a mask and drop them from the lanes of V1 which
8478 // actually need to be present as inputs to the INSERTPS.
8479 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8481 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8482 bool InsertNeedsShuffle = false;
8484 for (int i = 0; i < 4; ++i)
8488 } else if (Mask[i] != i) {
8489 InsertNeedsShuffle = true;
8494 // We don't want to use INSERTPS or other insertion techniques if it will
8495 // require shuffling anyways.
8496 if (!InsertNeedsShuffle) {
8497 // If all of V1 is zeroable, replace it with undef.
8498 if ((ZMask | 1 << V2Index) == 0xF)
8499 V1 = DAG.getUNDEF(MVT::v4f32);
8501 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8502 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8504 // Insert the V2 element into the desired position.
8505 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8506 DAG.getConstant(InsertPSMask, MVT::i8));
8510 // Otherwise fall back to a SHUFPS lowering strategy.
8511 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8514 /// \brief Lower 4-lane i32 vector shuffles.
8516 /// We try to handle these with integer-domain shuffles where we can, but for
8517 /// blends we use the floating point domain blend instructions.
8518 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8519 const X86Subtarget *Subtarget,
8520 SelectionDAG &DAG) {
8522 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8523 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8524 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8525 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8526 ArrayRef<int> Mask = SVOp->getMask();
8527 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8529 // Whenever we can lower this as a zext, that instruction is strictly faster
8530 // than any alternative. It also allows us to fold memory operands into the
8531 // shuffle in many cases.
8532 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8533 Mask, Subtarget, DAG))
8537 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8539 if (NumV2Elements == 0) {
8540 // Check for being able to broadcast a single element.
8541 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8542 Mask, Subtarget, DAG))
8545 // Straight shuffle of a single input vector. For everything from SSE2
8546 // onward this has a single fast instruction with no scary immediates.
8547 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8548 // but we aren't actually going to use the UNPCK instruction because doing
8549 // so prevents folding a load into this instruction or making a copy.
8550 const int UnpackLoMask[] = {0, 0, 1, 1};
8551 const int UnpackHiMask[] = {2, 2, 3, 3};
8552 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8553 Mask = UnpackLoMask;
8554 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8555 Mask = UnpackHiMask;
8557 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8558 getV4X86ShuffleImm8ForMask(Mask, DAG));
8561 // Try to use byte shift instructions.
8562 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8563 DL, MVT::v4i32, V1, V2, Mask, DAG))
8566 // There are special ways we can lower some single-element blends.
8567 if (NumV2Elements == 1)
8568 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8569 Mask, Subtarget, DAG))
8572 // Use dedicated unpack instructions for masks that match their pattern.
8573 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8574 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8575 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8576 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8578 if (Subtarget->hasSSE41())
8579 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8583 // Try to use byte rotation instructions.
8584 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8585 if (Subtarget->hasSSSE3())
8586 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8587 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8590 // We implement this with SHUFPS because it can blend from two vectors.
8591 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8592 // up the inputs, bypassing domain shift penalties that we would encur if we
8593 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8595 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8596 DAG.getVectorShuffle(
8598 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8599 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8602 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8603 /// shuffle lowering, and the most complex part.
8605 /// The lowering strategy is to try to form pairs of input lanes which are
8606 /// targeted at the same half of the final vector, and then use a dword shuffle
8607 /// to place them onto the right half, and finally unpack the paired lanes into
8608 /// their final position.
8610 /// The exact breakdown of how to form these dword pairs and align them on the
8611 /// correct sides is really tricky. See the comments within the function for
8612 /// more of the details.
8613 static SDValue lowerV8I16SingleInputVectorShuffle(
8614 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8615 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8616 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8617 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8618 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8620 SmallVector<int, 4> LoInputs;
8621 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8622 [](int M) { return M >= 0; });
8623 std::sort(LoInputs.begin(), LoInputs.end());
8624 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8625 SmallVector<int, 4> HiInputs;
8626 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8627 [](int M) { return M >= 0; });
8628 std::sort(HiInputs.begin(), HiInputs.end());
8629 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8631 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8632 int NumHToL = LoInputs.size() - NumLToL;
8634 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8635 int NumHToH = HiInputs.size() - NumLToH;
8636 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8637 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8638 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8639 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8641 // Check for being able to broadcast a single element.
8642 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8643 Mask, Subtarget, DAG))
8646 // Try to use byte shift instructions.
8647 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8648 DL, MVT::v8i16, V, V, Mask, DAG))
8651 // Use dedicated unpack instructions for masks that match their pattern.
8652 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8653 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8654 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8655 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8657 // Try to use byte rotation instructions.
8658 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8659 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8662 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8663 // such inputs we can swap two of the dwords across the half mark and end up
8664 // with <=2 inputs to each half in each half. Once there, we can fall through
8665 // to the generic code below. For example:
8667 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8668 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8670 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8671 // and an existing 2-into-2 on the other half. In this case we may have to
8672 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8673 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8674 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8675 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8676 // half than the one we target for fixing) will be fixed when we re-enter this
8677 // path. We will also combine away any sequence of PSHUFD instructions that
8678 // result into a single instruction. Here is an example of the tricky case:
8680 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8681 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8683 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8685 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8686 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8688 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8689 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8691 // The result is fine to be handled by the generic logic.
8692 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8693 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8694 int AOffset, int BOffset) {
8695 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8696 "Must call this with A having 3 or 1 inputs from the A half.");
8697 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8698 "Must call this with B having 1 or 3 inputs from the B half.");
8699 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8700 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8702 // Compute the index of dword with only one word among the three inputs in
8703 // a half by taking the sum of the half with three inputs and subtracting
8704 // the sum of the actual three inputs. The difference is the remaining
8707 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8708 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8709 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8710 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8711 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8712 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8713 int TripleNonInputIdx =
8714 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8715 TripleDWord = TripleNonInputIdx / 2;
8717 // We use xor with one to compute the adjacent DWord to whichever one the
8719 OneInputDWord = (OneInput / 2) ^ 1;
8721 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8722 // and BToA inputs. If there is also such a problem with the BToB and AToB
8723 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8724 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8725 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8726 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8727 // Compute how many inputs will be flipped by swapping these DWords. We
8729 // to balance this to ensure we don't form a 3-1 shuffle in the other
8731 int NumFlippedAToBInputs =
8732 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8733 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8734 int NumFlippedBToBInputs =
8735 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8736 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8737 if ((NumFlippedAToBInputs == 1 &&
8738 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8739 (NumFlippedBToBInputs == 1 &&
8740 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8741 // We choose whether to fix the A half or B half based on whether that
8742 // half has zero flipped inputs. At zero, we may not be able to fix it
8743 // with that half. We also bias towards fixing the B half because that
8744 // will more commonly be the high half, and we have to bias one way.
8745 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8746 ArrayRef<int> Inputs) {
8747 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8748 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8749 PinnedIdx ^ 1) != Inputs.end();
8750 // Determine whether the free index is in the flipped dword or the
8751 // unflipped dword based on where the pinned index is. We use this bit
8752 // in an xor to conditionally select the adjacent dword.
8753 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8754 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8755 FixFreeIdx) != Inputs.end();
8756 if (IsFixIdxInput == IsFixFreeIdxInput)
8758 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8759 FixFreeIdx) != Inputs.end();
8760 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8761 "We need to be changing the number of flipped inputs!");
8762 int PSHUFHalfMask[] = {0, 1, 2, 3};
8763 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8764 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8766 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8769 if (M != -1 && M == FixIdx)
8771 else if (M != -1 && M == FixFreeIdx)
8774 if (NumFlippedBToBInputs != 0) {
8776 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8777 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8779 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8781 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8782 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8787 int PSHUFDMask[] = {0, 1, 2, 3};
8788 PSHUFDMask[ADWord] = BDWord;
8789 PSHUFDMask[BDWord] = ADWord;
8790 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8791 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8792 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8793 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8795 // Adjust the mask to match the new locations of A and B.
8797 if (M != -1 && M/2 == ADWord)
8798 M = 2 * BDWord + M % 2;
8799 else if (M != -1 && M/2 == BDWord)
8800 M = 2 * ADWord + M % 2;
8802 // Recurse back into this routine to re-compute state now that this isn't
8803 // a 3 and 1 problem.
8804 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8807 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8808 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8809 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8810 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8812 // At this point there are at most two inputs to the low and high halves from
8813 // each half. That means the inputs can always be grouped into dwords and
8814 // those dwords can then be moved to the correct half with a dword shuffle.
8815 // We use at most one low and one high word shuffle to collect these paired
8816 // inputs into dwords, and finally a dword shuffle to place them.
8817 int PSHUFLMask[4] = {-1, -1, -1, -1};
8818 int PSHUFHMask[4] = {-1, -1, -1, -1};
8819 int PSHUFDMask[4] = {-1, -1, -1, -1};
8821 // First fix the masks for all the inputs that are staying in their
8822 // original halves. This will then dictate the targets of the cross-half
8824 auto fixInPlaceInputs =
8825 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8826 MutableArrayRef<int> SourceHalfMask,
8827 MutableArrayRef<int> HalfMask, int HalfOffset) {
8828 if (InPlaceInputs.empty())
8830 if (InPlaceInputs.size() == 1) {
8831 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8832 InPlaceInputs[0] - HalfOffset;
8833 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8836 if (IncomingInputs.empty()) {
8837 // Just fix all of the in place inputs.
8838 for (int Input : InPlaceInputs) {
8839 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8840 PSHUFDMask[Input / 2] = Input / 2;
8845 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8846 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8847 InPlaceInputs[0] - HalfOffset;
8848 // Put the second input next to the first so that they are packed into
8849 // a dword. We find the adjacent index by toggling the low bit.
8850 int AdjIndex = InPlaceInputs[0] ^ 1;
8851 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8852 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8853 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8855 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8856 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8858 // Now gather the cross-half inputs and place them into a free dword of
8859 // their target half.
8860 // FIXME: This operation could almost certainly be simplified dramatically to
8861 // look more like the 3-1 fixing operation.
8862 auto moveInputsToRightHalf = [&PSHUFDMask](
8863 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8864 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8865 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8867 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8868 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8870 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8872 int LowWord = Word & ~1;
8873 int HighWord = Word | 1;
8874 return isWordClobbered(SourceHalfMask, LowWord) ||
8875 isWordClobbered(SourceHalfMask, HighWord);
8878 if (IncomingInputs.empty())
8881 if (ExistingInputs.empty()) {
8882 // Map any dwords with inputs from them into the right half.
8883 for (int Input : IncomingInputs) {
8884 // If the source half mask maps over the inputs, turn those into
8885 // swaps and use the swapped lane.
8886 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8887 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8888 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8889 Input - SourceOffset;
8890 // We have to swap the uses in our half mask in one sweep.
8891 for (int &M : HalfMask)
8892 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8894 else if (M == Input)
8895 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8897 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8898 Input - SourceOffset &&
8899 "Previous placement doesn't match!");
8901 // Note that this correctly re-maps both when we do a swap and when
8902 // we observe the other side of the swap above. We rely on that to
8903 // avoid swapping the members of the input list directly.
8904 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8907 // Map the input's dword into the correct half.
8908 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8909 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8911 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8913 "Previous placement doesn't match!");
8916 // And just directly shift any other-half mask elements to be same-half
8917 // as we will have mirrored the dword containing the element into the
8918 // same position within that half.
8919 for (int &M : HalfMask)
8920 if (M >= SourceOffset && M < SourceOffset + 4) {
8921 M = M - SourceOffset + DestOffset;
8922 assert(M >= 0 && "This should never wrap below zero!");
8927 // Ensure we have the input in a viable dword of its current half. This
8928 // is particularly tricky because the original position may be clobbered
8929 // by inputs being moved and *staying* in that half.
8930 if (IncomingInputs.size() == 1) {
8931 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8932 int InputFixed = std::find(std::begin(SourceHalfMask),
8933 std::end(SourceHalfMask), -1) -
8934 std::begin(SourceHalfMask) + SourceOffset;
8935 SourceHalfMask[InputFixed - SourceOffset] =
8936 IncomingInputs[0] - SourceOffset;
8937 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8939 IncomingInputs[0] = InputFixed;
8941 } else if (IncomingInputs.size() == 2) {
8942 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8943 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8944 // We have two non-adjacent or clobbered inputs we need to extract from
8945 // the source half. To do this, we need to map them into some adjacent
8946 // dword slot in the source mask.
8947 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8948 IncomingInputs[1] - SourceOffset};
8950 // If there is a free slot in the source half mask adjacent to one of
8951 // the inputs, place the other input in it. We use (Index XOR 1) to
8952 // compute an adjacent index.
8953 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8954 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8955 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8956 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8957 InputsFixed[1] = InputsFixed[0] ^ 1;
8958 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8959 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8960 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8961 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8962 InputsFixed[0] = InputsFixed[1] ^ 1;
8963 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8964 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8965 // The two inputs are in the same DWord but it is clobbered and the
8966 // adjacent DWord isn't used at all. Move both inputs to the free
8968 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8969 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8970 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8971 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8973 // The only way we hit this point is if there is no clobbering
8974 // (because there are no off-half inputs to this half) and there is no
8975 // free slot adjacent to one of the inputs. In this case, we have to
8976 // swap an input with a non-input.
8977 for (int i = 0; i < 4; ++i)
8978 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8979 "We can't handle any clobbers here!");
8980 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8981 "Cannot have adjacent inputs here!");
8983 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8984 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8986 // We also have to update the final source mask in this case because
8987 // it may need to undo the above swap.
8988 for (int &M : FinalSourceHalfMask)
8989 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8990 M = InputsFixed[1] + SourceOffset;
8991 else if (M == InputsFixed[1] + SourceOffset)
8992 M = (InputsFixed[0] ^ 1) + SourceOffset;
8994 InputsFixed[1] = InputsFixed[0] ^ 1;
8997 // Point everything at the fixed inputs.
8998 for (int &M : HalfMask)
8999 if (M == IncomingInputs[0])
9000 M = InputsFixed[0] + SourceOffset;
9001 else if (M == IncomingInputs[1])
9002 M = InputsFixed[1] + SourceOffset;
9004 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9005 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9008 llvm_unreachable("Unhandled input size!");
9011 // Now hoist the DWord down to the right half.
9012 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9013 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9014 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9015 for (int &M : HalfMask)
9016 for (int Input : IncomingInputs)
9018 M = FreeDWord * 2 + Input % 2;
9020 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9021 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9022 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9023 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9025 // Now enact all the shuffles we've computed to move the inputs into their
9027 if (!isNoopShuffleMask(PSHUFLMask))
9028 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9029 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9030 if (!isNoopShuffleMask(PSHUFHMask))
9031 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9032 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9033 if (!isNoopShuffleMask(PSHUFDMask))
9034 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9035 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9036 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9037 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9039 // At this point, each half should contain all its inputs, and we can then
9040 // just shuffle them into their final position.
9041 assert(std::count_if(LoMask.begin(), LoMask.end(),
9042 [](int M) { return M >= 4; }) == 0 &&
9043 "Failed to lift all the high half inputs to the low mask!");
9044 assert(std::count_if(HiMask.begin(), HiMask.end(),
9045 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9046 "Failed to lift all the low half inputs to the high mask!");
9048 // Do a half shuffle for the low mask.
9049 if (!isNoopShuffleMask(LoMask))
9050 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9051 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9053 // Do a half shuffle with the high mask after shifting its values down.
9054 for (int &M : HiMask)
9057 if (!isNoopShuffleMask(HiMask))
9058 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9059 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9064 /// \brief Detect whether the mask pattern should be lowered through
9067 /// This essentially tests whether viewing the mask as an interleaving of two
9068 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9069 /// lowering it through interleaving is a significantly better strategy.
9070 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9071 int NumEvenInputs[2] = {0, 0};
9072 int NumOddInputs[2] = {0, 0};
9073 int NumLoInputs[2] = {0, 0};
9074 int NumHiInputs[2] = {0, 0};
9075 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9079 int InputIdx = Mask[i] >= Size;
9082 ++NumLoInputs[InputIdx];
9084 ++NumHiInputs[InputIdx];
9087 ++NumEvenInputs[InputIdx];
9089 ++NumOddInputs[InputIdx];
9092 // The minimum number of cross-input results for both the interleaved and
9093 // split cases. If interleaving results in fewer cross-input results, return
9095 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9096 NumEvenInputs[0] + NumOddInputs[1]);
9097 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9098 NumLoInputs[0] + NumHiInputs[1]);
9099 return InterleavedCrosses < SplitCrosses;
9102 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9104 /// This strategy only works when the inputs from each vector fit into a single
9105 /// half of that vector, and generally there are not so many inputs as to leave
9106 /// the in-place shuffles required highly constrained (and thus expensive). It
9107 /// shifts all the inputs into a single side of both input vectors and then
9108 /// uses an unpack to interleave these inputs in a single vector. At that
9109 /// point, we will fall back on the generic single input shuffle lowering.
9110 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9112 MutableArrayRef<int> Mask,
9113 const X86Subtarget *Subtarget,
9114 SelectionDAG &DAG) {
9115 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9116 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9117 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9118 for (int i = 0; i < 8; ++i)
9119 if (Mask[i] >= 0 && Mask[i] < 4)
9120 LoV1Inputs.push_back(i);
9121 else if (Mask[i] >= 4 && Mask[i] < 8)
9122 HiV1Inputs.push_back(i);
9123 else if (Mask[i] >= 8 && Mask[i] < 12)
9124 LoV2Inputs.push_back(i);
9125 else if (Mask[i] >= 12)
9126 HiV2Inputs.push_back(i);
9128 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9129 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9132 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9133 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9134 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9136 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9137 HiV1Inputs.size() + HiV2Inputs.size();
9139 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9140 ArrayRef<int> HiInputs, bool MoveToLo,
9142 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9143 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9144 if (BadInputs.empty())
9147 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9148 int MoveOffset = MoveToLo ? 0 : 4;
9150 if (GoodInputs.empty()) {
9151 for (int BadInput : BadInputs) {
9152 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9153 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9156 if (GoodInputs.size() == 2) {
9157 // If the low inputs are spread across two dwords, pack them into
9159 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9160 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9161 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9162 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9164 // Otherwise pin the good inputs.
9165 for (int GoodInput : GoodInputs)
9166 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9169 if (BadInputs.size() == 2) {
9170 // If we have two bad inputs then there may be either one or two good
9171 // inputs fixed in place. Find a fixed input, and then find the *other*
9172 // two adjacent indices by using modular arithmetic.
9174 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9175 [](int M) { return M >= 0; }) -
9176 std::begin(MoveMask);
9178 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9179 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9180 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9181 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9182 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9183 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9184 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9186 assert(BadInputs.size() == 1 && "All sizes handled");
9187 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9188 std::end(MoveMask), -1) -
9189 std::begin(MoveMask);
9190 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9191 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9195 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9198 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9200 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9203 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9204 // cross-half traffic in the final shuffle.
9206 // Munge the mask to be a single-input mask after the unpack merges the
9210 M = 2 * (M % 4) + (M / 8);
9212 return DAG.getVectorShuffle(
9213 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9214 DL, MVT::v8i16, V1, V2),
9215 DAG.getUNDEF(MVT::v8i16), Mask);
9218 /// \brief Generic lowering of 8-lane i16 shuffles.
9220 /// This handles both single-input shuffles and combined shuffle/blends with
9221 /// two inputs. The single input shuffles are immediately delegated to
9222 /// a dedicated lowering routine.
9224 /// The blends are lowered in one of three fundamental ways. If there are few
9225 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9226 /// of the input is significantly cheaper when lowered as an interleaving of
9227 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9228 /// halves of the inputs separately (making them have relatively few inputs)
9229 /// and then concatenate them.
9230 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9231 const X86Subtarget *Subtarget,
9232 SelectionDAG &DAG) {
9234 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9235 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9236 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9237 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9238 ArrayRef<int> OrigMask = SVOp->getMask();
9239 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9240 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9241 MutableArrayRef<int> Mask(MaskStorage);
9243 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9245 // Whenever we can lower this as a zext, that instruction is strictly faster
9246 // than any alternative.
9247 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9248 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9251 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9252 auto isV2 = [](int M) { return M >= 8; };
9254 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9255 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9257 if (NumV2Inputs == 0)
9258 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9260 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9261 "to be V1-input shuffles.");
9263 // Try to use byte shift instructions.
9264 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9265 DL, MVT::v8i16, V1, V2, Mask, DAG))
9268 // There are special ways we can lower some single-element blends.
9269 if (NumV2Inputs == 1)
9270 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9271 Mask, Subtarget, DAG))
9274 // Use dedicated unpack instructions for masks that match their pattern.
9275 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9276 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9277 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9278 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9280 if (Subtarget->hasSSE41())
9281 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9285 // Try to use byte rotation instructions.
9286 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9287 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9290 if (NumV1Inputs + NumV2Inputs <= 4)
9291 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9293 // Check whether an interleaving lowering is likely to be more efficient.
9294 // This isn't perfect but it is a strong heuristic that tends to work well on
9295 // the kinds of shuffles that show up in practice.
9297 // FIXME: Handle 1x, 2x, and 4x interleaving.
9298 if (shouldLowerAsInterleaving(Mask)) {
9299 // FIXME: Figure out whether we should pack these into the low or high
9302 int EMask[8], OMask[8];
9303 for (int i = 0; i < 4; ++i) {
9304 EMask[i] = Mask[2*i];
9305 OMask[i] = Mask[2*i + 1];
9310 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9311 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9313 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9316 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9317 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9319 for (int i = 0; i < 4; ++i) {
9320 LoBlendMask[i] = Mask[i];
9321 HiBlendMask[i] = Mask[i + 4];
9324 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9325 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9326 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9327 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9329 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9330 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9333 /// \brief Check whether a compaction lowering can be done by dropping even
9334 /// elements and compute how many times even elements must be dropped.
9336 /// This handles shuffles which take every Nth element where N is a power of
9337 /// two. Example shuffle masks:
9339 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9340 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9341 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9342 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9343 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9344 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9346 /// Any of these lanes can of course be undef.
9348 /// This routine only supports N <= 3.
9349 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9352 /// \returns N above, or the number of times even elements must be dropped if
9353 /// there is such a number. Otherwise returns zero.
9354 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9355 // Figure out whether we're looping over two inputs or just one.
9356 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9358 // The modulus for the shuffle vector entries is based on whether this is
9359 // a single input or not.
9360 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9361 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9362 "We should only be called with masks with a power-of-2 size!");
9364 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9366 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9367 // and 2^3 simultaneously. This is because we may have ambiguity with
9368 // partially undef inputs.
9369 bool ViableForN[3] = {true, true, true};
9371 for (int i = 0, e = Mask.size(); i < e; ++i) {
9372 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9377 bool IsAnyViable = false;
9378 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9379 if (ViableForN[j]) {
9382 // The shuffle mask must be equal to (i * 2^N) % M.
9383 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9386 ViableForN[j] = false;
9388 // Early exit if we exhaust the possible powers of two.
9393 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9397 // Return 0 as there is no viable power of two.
9401 /// \brief Generic lowering of v16i8 shuffles.
9403 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9404 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9405 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9406 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9408 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9409 const X86Subtarget *Subtarget,
9410 SelectionDAG &DAG) {
9412 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9413 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9414 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9415 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9416 ArrayRef<int> OrigMask = SVOp->getMask();
9417 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9419 // Try to use byte shift instructions.
9420 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9421 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9424 // Try to use byte rotation instructions.
9425 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9426 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9429 // Try to use a zext lowering.
9430 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9431 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9434 int MaskStorage[16] = {
9435 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9436 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9437 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9438 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9439 MutableArrayRef<int> Mask(MaskStorage);
9440 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9441 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9444 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9446 // For single-input shuffles, there are some nicer lowering tricks we can use.
9447 if (NumV2Elements == 0) {
9448 // Check for being able to broadcast a single element.
9449 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9450 Mask, Subtarget, DAG))
9453 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9454 // Notably, this handles splat and partial-splat shuffles more efficiently.
9455 // However, it only makes sense if the pre-duplication shuffle simplifies
9456 // things significantly. Currently, this means we need to be able to
9457 // express the pre-duplication shuffle as an i16 shuffle.
9459 // FIXME: We should check for other patterns which can be widened into an
9460 // i16 shuffle as well.
9461 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9462 for (int i = 0; i < 16; i += 2)
9463 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9468 auto tryToWidenViaDuplication = [&]() -> SDValue {
9469 if (!canWidenViaDuplication(Mask))
9471 SmallVector<int, 4> LoInputs;
9472 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9473 [](int M) { return M >= 0 && M < 8; });
9474 std::sort(LoInputs.begin(), LoInputs.end());
9475 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9477 SmallVector<int, 4> HiInputs;
9478 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9479 [](int M) { return M >= 8; });
9480 std::sort(HiInputs.begin(), HiInputs.end());
9481 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9484 bool TargetLo = LoInputs.size() >= HiInputs.size();
9485 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9486 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9488 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9489 SmallDenseMap<int, int, 8> LaneMap;
9490 for (int I : InPlaceInputs) {
9491 PreDupI16Shuffle[I/2] = I/2;
9494 int j = TargetLo ? 0 : 4, je = j + 4;
9495 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9496 // Check if j is already a shuffle of this input. This happens when
9497 // there are two adjacent bytes after we move the low one.
9498 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9499 // If we haven't yet mapped the input, search for a slot into which
9501 while (j < je && PreDupI16Shuffle[j] != -1)
9505 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9508 // Map this input with the i16 shuffle.
9509 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9512 // Update the lane map based on the mapping we ended up with.
9513 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9516 ISD::BITCAST, DL, MVT::v16i8,
9517 DAG.getVectorShuffle(MVT::v8i16, DL,
9518 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9519 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9521 // Unpack the bytes to form the i16s that will be shuffled into place.
9522 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9523 MVT::v16i8, V1, V1);
9525 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9526 for (int i = 0; i < 16; ++i)
9527 if (Mask[i] != -1) {
9528 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9529 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9530 if (PostDupI16Shuffle[i / 2] == -1)
9531 PostDupI16Shuffle[i / 2] = MappedMask;
9533 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9534 "Conflicting entrties in the original shuffle!");
9537 ISD::BITCAST, DL, MVT::v16i8,
9538 DAG.getVectorShuffle(MVT::v8i16, DL,
9539 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9540 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9542 if (SDValue V = tryToWidenViaDuplication())
9546 // Check whether an interleaving lowering is likely to be more efficient.
9547 // This isn't perfect but it is a strong heuristic that tends to work well on
9548 // the kinds of shuffles that show up in practice.
9550 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9551 if (shouldLowerAsInterleaving(Mask)) {
9552 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9553 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9555 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9556 return (M >= 8 && M < 16) || M >= 24;
9558 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9559 -1, -1, -1, -1, -1, -1, -1, -1};
9560 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9561 -1, -1, -1, -1, -1, -1, -1, -1};
9562 bool UnpackLo = NumLoHalf >= NumHiHalf;
9563 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9564 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9565 for (int i = 0; i < 8; ++i) {
9566 TargetEMask[i] = Mask[2 * i];
9567 TargetOMask[i] = Mask[2 * i + 1];
9570 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9571 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9573 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9574 MVT::v16i8, Evens, Odds);
9577 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9578 // with PSHUFB. It is important to do this before we attempt to generate any
9579 // blends but after all of the single-input lowerings. If the single input
9580 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9581 // want to preserve that and we can DAG combine any longer sequences into
9582 // a PSHUFB in the end. But once we start blending from multiple inputs,
9583 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9584 // and there are *very* few patterns that would actually be faster than the
9585 // PSHUFB approach because of its ability to zero lanes.
9587 // FIXME: The only exceptions to the above are blends which are exact
9588 // interleavings with direct instructions supporting them. We currently don't
9589 // handle those well here.
9590 if (Subtarget->hasSSSE3()) {
9593 for (int i = 0; i < 16; ++i)
9594 if (Mask[i] == -1) {
9595 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9597 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9599 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9601 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9602 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9603 if (isSingleInputShuffleMask(Mask))
9604 return V1; // Single inputs are easy.
9606 // Otherwise, blend the two.
9607 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9608 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9609 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9612 // There are special ways we can lower some single-element blends.
9613 if (NumV2Elements == 1)
9614 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9615 Mask, Subtarget, DAG))
9618 // Check whether a compaction lowering can be done. This handles shuffles
9619 // which take every Nth element for some even N. See the helper function for
9622 // We special case these as they can be particularly efficiently handled with
9623 // the PACKUSB instruction on x86 and they show up in common patterns of
9624 // rearranging bytes to truncate wide elements.
9625 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9626 // NumEvenDrops is the power of two stride of the elements. Another way of
9627 // thinking about it is that we need to drop the even elements this many
9628 // times to get the original input.
9629 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9631 // First we need to zero all the dropped bytes.
9632 assert(NumEvenDrops <= 3 &&
9633 "No support for dropping even elements more than 3 times.");
9634 // We use the mask type to pick which bytes are preserved based on how many
9635 // elements are dropped.
9636 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9637 SDValue ByteClearMask =
9638 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9639 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9640 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9642 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9644 // Now pack things back together.
9645 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9646 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9647 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9648 for (int i = 1; i < NumEvenDrops; ++i) {
9649 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9650 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9656 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9657 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9658 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9659 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9661 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9662 MutableArrayRef<int> V1HalfBlendMask,
9663 MutableArrayRef<int> V2HalfBlendMask) {
9664 for (int i = 0; i < 8; ++i)
9665 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9666 V1HalfBlendMask[i] = HalfMask[i];
9668 } else if (HalfMask[i] >= 16) {
9669 V2HalfBlendMask[i] = HalfMask[i] - 16;
9670 HalfMask[i] = i + 8;
9673 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9674 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9676 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9678 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9679 MutableArrayRef<int> HiBlendMask) {
9681 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9682 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9684 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9685 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9686 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9687 [](int M) { return M >= 0 && M % 2 == 1; })) {
9688 // Use a mask to drop the high bytes.
9689 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9690 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9691 DAG.getConstant(0x00FF, MVT::v8i16));
9693 // This will be a single vector shuffle instead of a blend so nuke V2.
9694 V2 = DAG.getUNDEF(MVT::v8i16);
9696 // Squash the masks to point directly into V1.
9697 for (int &M : LoBlendMask)
9700 for (int &M : HiBlendMask)
9704 // Otherwise just unpack the low half of V into V1 and the high half into
9705 // V2 so that we can blend them as i16s.
9706 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9707 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9708 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9709 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9712 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9713 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9714 return std::make_pair(BlendedLo, BlendedHi);
9716 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9717 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9718 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9720 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9721 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9723 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9726 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9728 /// This routine breaks down the specific type of 128-bit shuffle and
9729 /// dispatches to the lowering routines accordingly.
9730 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9731 MVT VT, const X86Subtarget *Subtarget,
9732 SelectionDAG &DAG) {
9733 switch (VT.SimpleTy) {
9735 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9737 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9739 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9741 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9743 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9745 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9748 llvm_unreachable("Unimplemented!");
9752 /// \brief Helper function to test whether a shuffle mask could be
9753 /// simplified by widening the elements being shuffled.
9755 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9756 /// leaves it in an unspecified state.
9758 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9759 /// shuffle masks. The latter have the special property of a '-2' representing
9760 /// a zero-ed lane of a vector.
9761 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9762 SmallVectorImpl<int> &WidenedMask) {
9763 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9764 // If both elements are undef, its trivial.
9765 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9766 WidenedMask.push_back(SM_SentinelUndef);
9770 // Check for an undef mask and a mask value properly aligned to fit with
9771 // a pair of values. If we find such a case, use the non-undef mask's value.
9772 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9773 WidenedMask.push_back(Mask[i + 1] / 2);
9776 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9777 WidenedMask.push_back(Mask[i] / 2);
9781 // When zeroing, we need to spread the zeroing across both lanes to widen.
9782 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9783 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9784 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9785 WidenedMask.push_back(SM_SentinelZero);
9791 // Finally check if the two mask values are adjacent and aligned with
9793 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9794 WidenedMask.push_back(Mask[i] / 2);
9798 // Otherwise we can't safely widen the elements used in this shuffle.
9801 assert(WidenedMask.size() == Mask.size() / 2 &&
9802 "Incorrect size of mask after widening the elements!");
9807 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9809 /// This routine just extracts two subvectors, shuffles them independently, and
9810 /// then concatenates them back together. This should work effectively with all
9811 /// AVX vector shuffle types.
9812 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9813 SDValue V2, ArrayRef<int> Mask,
9814 SelectionDAG &DAG) {
9815 assert(VT.getSizeInBits() >= 256 &&
9816 "Only for 256-bit or wider vector shuffles!");
9817 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9818 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9820 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9821 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9823 int NumElements = VT.getVectorNumElements();
9824 int SplitNumElements = NumElements / 2;
9825 MVT ScalarVT = VT.getScalarType();
9826 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9828 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9829 DAG.getIntPtrConstant(0));
9830 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9831 DAG.getIntPtrConstant(SplitNumElements));
9832 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9833 DAG.getIntPtrConstant(0));
9834 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9835 DAG.getIntPtrConstant(SplitNumElements));
9837 // Now create two 4-way blends of these half-width vectors.
9838 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9839 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9840 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9841 for (int i = 0; i < SplitNumElements; ++i) {
9842 int M = HalfMask[i];
9843 if (M >= NumElements) {
9844 if (M >= NumElements + SplitNumElements)
9848 V2BlendMask.push_back(M - NumElements);
9849 V1BlendMask.push_back(-1);
9850 BlendMask.push_back(SplitNumElements + i);
9851 } else if (M >= 0) {
9852 if (M >= SplitNumElements)
9856 V2BlendMask.push_back(-1);
9857 V1BlendMask.push_back(M);
9858 BlendMask.push_back(i);
9860 V2BlendMask.push_back(-1);
9861 V1BlendMask.push_back(-1);
9862 BlendMask.push_back(-1);
9866 // Because the lowering happens after all combining takes place, we need to
9867 // manually combine these blend masks as much as possible so that we create
9868 // a minimal number of high-level vector shuffle nodes.
9870 // First try just blending the halves of V1 or V2.
9871 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9872 return DAG.getUNDEF(SplitVT);
9873 if (!UseLoV2 && !UseHiV2)
9874 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9875 if (!UseLoV1 && !UseHiV1)
9876 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9878 SDValue V1Blend, V2Blend;
9879 if (UseLoV1 && UseHiV1) {
9881 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9883 // We only use half of V1 so map the usage down into the final blend mask.
9884 V1Blend = UseLoV1 ? LoV1 : HiV1;
9885 for (int i = 0; i < SplitNumElements; ++i)
9886 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9887 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9889 if (UseLoV2 && UseHiV2) {
9891 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9893 // We only use half of V2 so map the usage down into the final blend mask.
9894 V2Blend = UseLoV2 ? LoV2 : HiV2;
9895 for (int i = 0; i < SplitNumElements; ++i)
9896 if (BlendMask[i] >= SplitNumElements)
9897 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9899 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9901 SDValue Lo = HalfBlend(LoMask);
9902 SDValue Hi = HalfBlend(HiMask);
9903 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9906 /// \brief Either split a vector in halves or decompose the shuffles and the
9909 /// This is provided as a good fallback for many lowerings of non-single-input
9910 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9911 /// between splitting the shuffle into 128-bit components and stitching those
9912 /// back together vs. extracting the single-input shuffles and blending those
9914 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9915 SDValue V2, ArrayRef<int> Mask,
9916 SelectionDAG &DAG) {
9917 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9918 "lower single-input shuffles as it "
9919 "could then recurse on itself.");
9920 int Size = Mask.size();
9922 // If this can be modeled as a broadcast of two elements followed by a blend,
9923 // prefer that lowering. This is especially important because broadcasts can
9924 // often fold with memory operands.
9925 auto DoBothBroadcast = [&] {
9926 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9929 if (V2BroadcastIdx == -1)
9930 V2BroadcastIdx = M - Size;
9931 else if (M - Size != V2BroadcastIdx)
9933 } else if (M >= 0) {
9934 if (V1BroadcastIdx == -1)
9936 else if (M != V1BroadcastIdx)
9941 if (DoBothBroadcast())
9942 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9945 // If the inputs all stem from a single 128-bit lane of each input, then we
9946 // split them rather than blending because the split will decompose to
9947 // unusually few instructions.
9948 int LaneCount = VT.getSizeInBits() / 128;
9949 int LaneSize = Size / LaneCount;
9950 SmallBitVector LaneInputs[2];
9951 LaneInputs[0].resize(LaneCount, false);
9952 LaneInputs[1].resize(LaneCount, false);
9953 for (int i = 0; i < Size; ++i)
9955 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9956 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9957 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9959 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9960 // that the decomposed single-input shuffles don't end up here.
9961 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9964 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9965 /// a permutation and blend of those lanes.
9967 /// This essentially blends the out-of-lane inputs to each lane into the lane
9968 /// from a permuted copy of the vector. This lowering strategy results in four
9969 /// instructions in the worst case for a single-input cross lane shuffle which
9970 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9971 /// of. Special cases for each particular shuffle pattern should be handled
9972 /// prior to trying this lowering.
9973 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9974 SDValue V1, SDValue V2,
9976 SelectionDAG &DAG) {
9977 // FIXME: This should probably be generalized for 512-bit vectors as well.
9978 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9979 int LaneSize = Mask.size() / 2;
9981 // If there are only inputs from one 128-bit lane, splitting will in fact be
9982 // less expensive. The flags track wether the given lane contains an element
9983 // that crosses to another lane.
9984 bool LaneCrossing[2] = {false, false};
9985 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9986 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9987 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9988 if (!LaneCrossing[0] || !LaneCrossing[1])
9989 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9991 if (isSingleInputShuffleMask(Mask)) {
9992 SmallVector<int, 32> FlippedBlendMask;
9993 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9994 FlippedBlendMask.push_back(
9995 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9997 : Mask[i] % LaneSize +
9998 (i / LaneSize) * LaneSize + Size));
10000 // Flip the vector, and blend the results which should now be in-lane. The
10001 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10002 // 5 for the high source. The value 3 selects the high half of source 2 and
10003 // the value 2 selects the low half of source 2. We only use source 2 to
10004 // allow folding it into a memory operand.
10005 unsigned PERMMask = 3 | 2 << 4;
10006 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10007 V1, DAG.getConstant(PERMMask, MVT::i8));
10008 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10011 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10012 // will be handled by the above logic and a blend of the results, much like
10013 // other patterns in AVX.
10014 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10017 /// \brief Handle lowering 2-lane 128-bit shuffles.
10018 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10019 SDValue V2, ArrayRef<int> Mask,
10020 const X86Subtarget *Subtarget,
10021 SelectionDAG &DAG) {
10022 // Blends are faster and handle all the non-lane-crossing cases.
10023 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10027 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10028 VT.getVectorNumElements() / 2);
10029 // Check for patterns which can be matched with a single insert of a 128-bit
10031 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10032 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10033 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10034 DAG.getIntPtrConstant(0));
10035 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10036 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10037 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10039 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10040 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10041 DAG.getIntPtrConstant(0));
10042 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10043 DAG.getIntPtrConstant(2));
10044 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10047 // Otherwise form a 128-bit permutation.
10048 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10049 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10050 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10051 DAG.getConstant(PermMask, MVT::i8));
10054 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10055 /// shuffling each lane.
10057 /// This will only succeed when the result of fixing the 128-bit lanes results
10058 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10059 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10060 /// the lane crosses early and then use simpler shuffles within each lane.
10062 /// FIXME: It might be worthwhile at some point to support this without
10063 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10064 /// in x86 only floating point has interesting non-repeating shuffles, and even
10065 /// those are still *marginally* more expensive.
10066 static SDValue lowerVectorShuffleByMerging128BitLanes(
10067 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10068 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10069 assert(!isSingleInputShuffleMask(Mask) &&
10070 "This is only useful with multiple inputs.");
10072 int Size = Mask.size();
10073 int LaneSize = 128 / VT.getScalarSizeInBits();
10074 int NumLanes = Size / LaneSize;
10075 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10077 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10078 // check whether the in-128-bit lane shuffles share a repeating pattern.
10079 SmallVector<int, 4> Lanes;
10080 Lanes.resize(NumLanes, -1);
10081 SmallVector<int, 4> InLaneMask;
10082 InLaneMask.resize(LaneSize, -1);
10083 for (int i = 0; i < Size; ++i) {
10087 int j = i / LaneSize;
10089 if (Lanes[j] < 0) {
10090 // First entry we've seen for this lane.
10091 Lanes[j] = Mask[i] / LaneSize;
10092 } else if (Lanes[j] != Mask[i] / LaneSize) {
10093 // This doesn't match the lane selected previously!
10097 // Check that within each lane we have a consistent shuffle mask.
10098 int k = i % LaneSize;
10099 if (InLaneMask[k] < 0) {
10100 InLaneMask[k] = Mask[i] % LaneSize;
10101 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10102 // This doesn't fit a repeating in-lane mask.
10107 // First shuffle the lanes into place.
10108 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10109 VT.getSizeInBits() / 64);
10110 SmallVector<int, 8> LaneMask;
10111 LaneMask.resize(NumLanes * 2, -1);
10112 for (int i = 0; i < NumLanes; ++i)
10113 if (Lanes[i] >= 0) {
10114 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10115 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10118 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10119 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10120 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10122 // Cast it back to the type we actually want.
10123 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10125 // Now do a simple shuffle that isn't lane crossing.
10126 SmallVector<int, 8> NewMask;
10127 NewMask.resize(Size, -1);
10128 for (int i = 0; i < Size; ++i)
10130 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10131 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10132 "Must not introduce lane crosses at this point!");
10134 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10137 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10140 /// This returns true if the elements from a particular input are already in the
10141 /// slot required by the given mask and require no permutation.
10142 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10143 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10144 int Size = Mask.size();
10145 for (int i = 0; i < Size; ++i)
10146 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10152 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10154 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10155 /// isn't available.
10156 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10157 const X86Subtarget *Subtarget,
10158 SelectionDAG &DAG) {
10160 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10161 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10162 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10163 ArrayRef<int> Mask = SVOp->getMask();
10164 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10166 SmallVector<int, 4> WidenedMask;
10167 if (canWidenShuffleElements(Mask, WidenedMask))
10168 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10171 if (isSingleInputShuffleMask(Mask)) {
10172 // Check for being able to broadcast a single element.
10173 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10174 Mask, Subtarget, DAG))
10177 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10178 // Non-half-crossing single input shuffles can be lowerid with an
10179 // interleaved permutation.
10180 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10181 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10182 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10183 DAG.getConstant(VPERMILPMask, MVT::i8));
10186 // With AVX2 we have direct support for this permutation.
10187 if (Subtarget->hasAVX2())
10188 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10189 getV4X86ShuffleImm8ForMask(Mask, DAG));
10191 // Otherwise, fall back.
10192 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10196 // X86 has dedicated unpack instructions that can handle specific blend
10197 // operations: UNPCKH and UNPCKL.
10198 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10199 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10200 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10201 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10203 // If we have a single input to the zero element, insert that into V1 if we
10204 // can do so cheaply.
10205 int NumV2Elements =
10206 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10207 if (NumV2Elements == 1 && Mask[0] >= 4)
10208 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10209 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10212 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10216 // Check if the blend happens to exactly fit that of SHUFPD.
10217 if ((Mask[0] == -1 || Mask[0] < 2) &&
10218 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10219 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10220 (Mask[3] == -1 || Mask[3] >= 6)) {
10221 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10222 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10223 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10224 DAG.getConstant(SHUFPDMask, MVT::i8));
10226 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10227 (Mask[1] == -1 || Mask[1] < 2) &&
10228 (Mask[2] == -1 || Mask[2] >= 6) &&
10229 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10230 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10231 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10232 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10233 DAG.getConstant(SHUFPDMask, MVT::i8));
10236 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10237 // shuffle. However, if we have AVX2 and either inputs are already in place,
10238 // we will be able to shuffle even across lanes the other input in a single
10239 // instruction so skip this pattern.
10240 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10241 isShuffleMaskInputInPlace(1, Mask))))
10242 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10243 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10246 // If we have AVX2 then we always want to lower with a blend because an v4 we
10247 // can fully permute the elements.
10248 if (Subtarget->hasAVX2())
10249 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10252 // Otherwise fall back on generic lowering.
10253 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10256 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10258 /// This routine is only called when we have AVX2 and thus a reasonable
10259 /// instruction set for v4i64 shuffling..
10260 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10261 const X86Subtarget *Subtarget,
10262 SelectionDAG &DAG) {
10264 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10265 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10266 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10267 ArrayRef<int> Mask = SVOp->getMask();
10268 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10269 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10271 SmallVector<int, 4> WidenedMask;
10272 if (canWidenShuffleElements(Mask, WidenedMask))
10273 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10276 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10280 // Check for being able to broadcast a single element.
10281 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10282 Mask, Subtarget, DAG))
10285 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10286 // use lower latency instructions that will operate on both 128-bit lanes.
10287 SmallVector<int, 2> RepeatedMask;
10288 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10289 if (isSingleInputShuffleMask(Mask)) {
10290 int PSHUFDMask[] = {-1, -1, -1, -1};
10291 for (int i = 0; i < 2; ++i)
10292 if (RepeatedMask[i] >= 0) {
10293 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10294 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10296 return DAG.getNode(
10297 ISD::BITCAST, DL, MVT::v4i64,
10298 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10299 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10300 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10303 // Use dedicated unpack instructions for masks that match their pattern.
10304 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10305 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10306 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10307 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10310 // AVX2 provides a direct instruction for permuting a single input across
10312 if (isSingleInputShuffleMask(Mask))
10313 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10314 getV4X86ShuffleImm8ForMask(Mask, DAG));
10316 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10317 // shuffle. However, if we have AVX2 and either inputs are already in place,
10318 // we will be able to shuffle even across lanes the other input in a single
10319 // instruction so skip this pattern.
10320 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10321 isShuffleMaskInputInPlace(1, Mask))))
10322 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10323 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10326 // Otherwise fall back on generic blend lowering.
10327 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10331 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10333 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10334 /// isn't available.
10335 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10336 const X86Subtarget *Subtarget,
10337 SelectionDAG &DAG) {
10339 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10340 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10341 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10342 ArrayRef<int> Mask = SVOp->getMask();
10343 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10345 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10349 // Check for being able to broadcast a single element.
10350 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10351 Mask, Subtarget, DAG))
10354 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10355 // options to efficiently lower the shuffle.
10356 SmallVector<int, 4> RepeatedMask;
10357 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10358 assert(RepeatedMask.size() == 4 &&
10359 "Repeated masks must be half the mask width!");
10360 if (isSingleInputShuffleMask(Mask))
10361 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10362 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10364 // Use dedicated unpack instructions for masks that match their pattern.
10365 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10366 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10367 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10368 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10370 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10371 // have already handled any direct blends. We also need to squash the
10372 // repeated mask into a simulated v4f32 mask.
10373 for (int i = 0; i < 4; ++i)
10374 if (RepeatedMask[i] >= 8)
10375 RepeatedMask[i] -= 4;
10376 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10379 // If we have a single input shuffle with different shuffle patterns in the
10380 // two 128-bit lanes use the variable mask to VPERMILPS.
10381 if (isSingleInputShuffleMask(Mask)) {
10382 SDValue VPermMask[8];
10383 for (int i = 0; i < 8; ++i)
10384 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10385 : DAG.getConstant(Mask[i], MVT::i32);
10386 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10387 return DAG.getNode(
10388 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10389 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10391 if (Subtarget->hasAVX2())
10392 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10393 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10394 DAG.getNode(ISD::BUILD_VECTOR, DL,
10395 MVT::v8i32, VPermMask)),
10398 // Otherwise, fall back.
10399 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10403 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10405 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10406 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10409 // If we have AVX2 then we always want to lower with a blend because at v8 we
10410 // can fully permute the elements.
10411 if (Subtarget->hasAVX2())
10412 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10415 // Otherwise fall back on generic lowering.
10416 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10419 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10421 /// This routine is only called when we have AVX2 and thus a reasonable
10422 /// instruction set for v8i32 shuffling..
10423 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10424 const X86Subtarget *Subtarget,
10425 SelectionDAG &DAG) {
10427 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10428 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10429 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10430 ArrayRef<int> Mask = SVOp->getMask();
10431 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10432 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10434 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10438 // Check for being able to broadcast a single element.
10439 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10440 Mask, Subtarget, DAG))
10443 // If the shuffle mask is repeated in each 128-bit lane we can use more
10444 // efficient instructions that mirror the shuffles across the two 128-bit
10446 SmallVector<int, 4> RepeatedMask;
10447 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10448 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10449 if (isSingleInputShuffleMask(Mask))
10450 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10451 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10453 // Use dedicated unpack instructions for masks that match their pattern.
10454 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10455 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10456 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10457 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10460 // If the shuffle patterns aren't repeated but it is a single input, directly
10461 // generate a cross-lane VPERMD instruction.
10462 if (isSingleInputShuffleMask(Mask)) {
10463 SDValue VPermMask[8];
10464 for (int i = 0; i < 8; ++i)
10465 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10466 : DAG.getConstant(Mask[i], MVT::i32);
10467 return DAG.getNode(
10468 X86ISD::VPERMV, DL, MVT::v8i32,
10469 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10472 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10474 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10475 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10478 // Otherwise fall back on generic blend lowering.
10479 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10483 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10485 /// This routine is only called when we have AVX2 and thus a reasonable
10486 /// instruction set for v16i16 shuffling..
10487 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10488 const X86Subtarget *Subtarget,
10489 SelectionDAG &DAG) {
10491 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10492 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10493 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10494 ArrayRef<int> Mask = SVOp->getMask();
10495 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10496 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10498 // Check for being able to broadcast a single element.
10499 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10500 Mask, Subtarget, DAG))
10503 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10507 // Use dedicated unpack instructions for masks that match their pattern.
10508 if (isShuffleEquivalent(Mask,
10509 // First 128-bit lane:
10510 0, 16, 1, 17, 2, 18, 3, 19,
10511 // Second 128-bit lane:
10512 8, 24, 9, 25, 10, 26, 11, 27))
10513 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10514 if (isShuffleEquivalent(Mask,
10515 // First 128-bit lane:
10516 4, 20, 5, 21, 6, 22, 7, 23,
10517 // Second 128-bit lane:
10518 12, 28, 13, 29, 14, 30, 15, 31))
10519 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10521 if (isSingleInputShuffleMask(Mask)) {
10522 // There are no generalized cross-lane shuffle operations available on i16
10524 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10525 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10528 SDValue PSHUFBMask[32];
10529 for (int i = 0; i < 16; ++i) {
10530 if (Mask[i] == -1) {
10531 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10535 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10536 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10537 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10538 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10540 return DAG.getNode(
10541 ISD::BITCAST, DL, MVT::v16i16,
10543 X86ISD::PSHUFB, DL, MVT::v32i8,
10544 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10545 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10548 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10550 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10551 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10554 // Otherwise fall back on generic lowering.
10555 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10558 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10560 /// This routine is only called when we have AVX2 and thus a reasonable
10561 /// instruction set for v32i8 shuffling..
10562 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10563 const X86Subtarget *Subtarget,
10564 SelectionDAG &DAG) {
10566 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10567 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10568 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10569 ArrayRef<int> Mask = SVOp->getMask();
10570 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10571 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10573 // Check for being able to broadcast a single element.
10574 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10575 Mask, Subtarget, DAG))
10578 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10582 // Use dedicated unpack instructions for masks that match their pattern.
10583 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10585 if (isShuffleEquivalent(
10587 // First 128-bit lane:
10588 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10589 // Second 128-bit lane:
10590 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10591 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10592 if (isShuffleEquivalent(
10594 // First 128-bit lane:
10595 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10596 // Second 128-bit lane:
10597 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10598 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10600 if (isSingleInputShuffleMask(Mask)) {
10601 // There are no generalized cross-lane shuffle operations available on i8
10603 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10604 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10607 SDValue PSHUFBMask[32];
10608 for (int i = 0; i < 32; ++i)
10611 ? DAG.getUNDEF(MVT::i8)
10612 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10614 return DAG.getNode(
10615 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10616 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10619 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10621 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10622 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10625 // Otherwise fall back on generic lowering.
10626 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10629 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10631 /// This routine either breaks down the specific type of a 256-bit x86 vector
10632 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10633 /// together based on the available instructions.
10634 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10635 MVT VT, const X86Subtarget *Subtarget,
10636 SelectionDAG &DAG) {
10638 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10639 ArrayRef<int> Mask = SVOp->getMask();
10641 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10642 // check for those subtargets here and avoid much of the subtarget querying in
10643 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10644 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10645 // floating point types there eventually, just immediately cast everything to
10646 // a float and operate entirely in that domain.
10647 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10648 int ElementBits = VT.getScalarSizeInBits();
10649 if (ElementBits < 32)
10650 // No floating point type available, decompose into 128-bit vectors.
10651 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10653 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10654 VT.getVectorNumElements());
10655 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10656 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10657 return DAG.getNode(ISD::BITCAST, DL, VT,
10658 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10661 switch (VT.SimpleTy) {
10663 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10665 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10667 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10669 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10671 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10673 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10676 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10680 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10681 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10682 const X86Subtarget *Subtarget,
10683 SelectionDAG &DAG) {
10685 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10686 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10687 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10688 ArrayRef<int> Mask = SVOp->getMask();
10689 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10691 // FIXME: Implement direct support for this type!
10692 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10695 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10696 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10697 const X86Subtarget *Subtarget,
10698 SelectionDAG &DAG) {
10700 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10701 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10703 ArrayRef<int> Mask = SVOp->getMask();
10704 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10706 // FIXME: Implement direct support for this type!
10707 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10710 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10711 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10712 const X86Subtarget *Subtarget,
10713 SelectionDAG &DAG) {
10715 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10716 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10717 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10718 ArrayRef<int> Mask = SVOp->getMask();
10719 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10721 // FIXME: Implement direct support for this type!
10722 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10725 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10726 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10727 const X86Subtarget *Subtarget,
10728 SelectionDAG &DAG) {
10730 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10731 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10732 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10733 ArrayRef<int> Mask = SVOp->getMask();
10734 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10736 // FIXME: Implement direct support for this type!
10737 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10740 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10741 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10742 const X86Subtarget *Subtarget,
10743 SelectionDAG &DAG) {
10745 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10746 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10747 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10748 ArrayRef<int> Mask = SVOp->getMask();
10749 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10750 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10752 // FIXME: Implement direct support for this type!
10753 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10756 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10757 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10758 const X86Subtarget *Subtarget,
10759 SelectionDAG &DAG) {
10761 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10762 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10763 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10764 ArrayRef<int> Mask = SVOp->getMask();
10765 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10766 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10768 // FIXME: Implement direct support for this type!
10769 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10772 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10774 /// This routine either breaks down the specific type of a 512-bit x86 vector
10775 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10776 /// together based on the available instructions.
10777 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10778 MVT VT, const X86Subtarget *Subtarget,
10779 SelectionDAG &DAG) {
10781 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10782 ArrayRef<int> Mask = SVOp->getMask();
10783 assert(Subtarget->hasAVX512() &&
10784 "Cannot lower 512-bit vectors w/ basic ISA!");
10786 // Check for being able to broadcast a single element.
10787 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10788 Mask, Subtarget, DAG))
10791 // Dispatch to each element type for lowering. If we don't have supprot for
10792 // specific element type shuffles at 512 bits, immediately split them and
10793 // lower them. Each lowering routine of a given type is allowed to assume that
10794 // the requisite ISA extensions for that element type are available.
10795 switch (VT.SimpleTy) {
10797 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10799 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10801 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10803 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10805 if (Subtarget->hasBWI())
10806 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10809 if (Subtarget->hasBWI())
10810 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10814 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10817 // Otherwise fall back on splitting.
10818 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10821 /// \brief Top-level lowering for x86 vector shuffles.
10823 /// This handles decomposition, canonicalization, and lowering of all x86
10824 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10825 /// above in helper routines. The canonicalization attempts to widen shuffles
10826 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10827 /// s.t. only one of the two inputs needs to be tested, etc.
10828 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10829 SelectionDAG &DAG) {
10830 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10831 ArrayRef<int> Mask = SVOp->getMask();
10832 SDValue V1 = Op.getOperand(0);
10833 SDValue V2 = Op.getOperand(1);
10834 MVT VT = Op.getSimpleValueType();
10835 int NumElements = VT.getVectorNumElements();
10838 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10840 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10841 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10842 if (V1IsUndef && V2IsUndef)
10843 return DAG.getUNDEF(VT);
10845 // When we create a shuffle node we put the UNDEF node to second operand,
10846 // but in some cases the first operand may be transformed to UNDEF.
10847 // In this case we should just commute the node.
10849 return DAG.getCommutedVectorShuffle(*SVOp);
10851 // Check for non-undef masks pointing at an undef vector and make the masks
10852 // undef as well. This makes it easier to match the shuffle based solely on
10856 if (M >= NumElements) {
10857 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10858 for (int &M : NewMask)
10859 if (M >= NumElements)
10861 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10864 // Try to collapse shuffles into using a vector type with fewer elements but
10865 // wider element types. We cap this to not form integers or floating point
10866 // elements wider than 64 bits, but it might be interesting to form i128
10867 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10868 SmallVector<int, 16> WidenedMask;
10869 if (VT.getScalarSizeInBits() < 64 &&
10870 canWidenShuffleElements(Mask, WidenedMask)) {
10871 MVT NewEltVT = VT.isFloatingPoint()
10872 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10873 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10874 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10875 // Make sure that the new vector type is legal. For example, v2f64 isn't
10877 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10878 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10879 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10880 return DAG.getNode(ISD::BITCAST, dl, VT,
10881 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10885 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10886 for (int M : SVOp->getMask())
10888 ++NumUndefElements;
10889 else if (M < NumElements)
10894 // Commute the shuffle as needed such that more elements come from V1 than
10895 // V2. This allows us to match the shuffle pattern strictly on how many
10896 // elements come from V1 without handling the symmetric cases.
10897 if (NumV2Elements > NumV1Elements)
10898 return DAG.getCommutedVectorShuffle(*SVOp);
10900 // When the number of V1 and V2 elements are the same, try to minimize the
10901 // number of uses of V2 in the low half of the vector. When that is tied,
10902 // ensure that the sum of indices for V1 is equal to or lower than the sum
10903 // indices for V2. When those are equal, try to ensure that the number of odd
10904 // indices for V1 is lower than the number of odd indices for V2.
10905 if (NumV1Elements == NumV2Elements) {
10906 int LowV1Elements = 0, LowV2Elements = 0;
10907 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10908 if (M >= NumElements)
10912 if (LowV2Elements > LowV1Elements) {
10913 return DAG.getCommutedVectorShuffle(*SVOp);
10914 } else if (LowV2Elements == LowV1Elements) {
10915 int SumV1Indices = 0, SumV2Indices = 0;
10916 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10917 if (SVOp->getMask()[i] >= NumElements)
10919 else if (SVOp->getMask()[i] >= 0)
10921 if (SumV2Indices < SumV1Indices) {
10922 return DAG.getCommutedVectorShuffle(*SVOp);
10923 } else if (SumV2Indices == SumV1Indices) {
10924 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10925 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10926 if (SVOp->getMask()[i] >= NumElements)
10927 NumV2OddIndices += i % 2;
10928 else if (SVOp->getMask()[i] >= 0)
10929 NumV1OddIndices += i % 2;
10930 if (NumV2OddIndices < NumV1OddIndices)
10931 return DAG.getCommutedVectorShuffle(*SVOp);
10936 // For each vector width, delegate to a specialized lowering routine.
10937 if (VT.getSizeInBits() == 128)
10938 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10940 if (VT.getSizeInBits() == 256)
10941 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10943 // Force AVX-512 vectors to be scalarized for now.
10944 // FIXME: Implement AVX-512 support!
10945 if (VT.getSizeInBits() == 512)
10946 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10948 llvm_unreachable("Unimplemented!");
10952 //===----------------------------------------------------------------------===//
10953 // Legacy vector shuffle lowering
10955 // This code is the legacy code handling vector shuffles until the above
10956 // replaces its functionality and performance.
10957 //===----------------------------------------------------------------------===//
10959 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10960 bool hasInt256, unsigned *MaskOut = nullptr) {
10961 MVT EltVT = VT.getVectorElementType();
10963 // There is no blend with immediate in AVX-512.
10964 if (VT.is512BitVector())
10967 if (!hasSSE41 || EltVT == MVT::i8)
10969 if (!hasInt256 && VT == MVT::v16i16)
10972 unsigned MaskValue = 0;
10973 unsigned NumElems = VT.getVectorNumElements();
10974 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10975 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10976 unsigned NumElemsInLane = NumElems / NumLanes;
10978 // Blend for v16i16 should be symetric for the both lanes.
10979 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10981 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10982 int EltIdx = MaskVals[i];
10984 if ((EltIdx < 0 || EltIdx == (int)i) &&
10985 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10988 if (((unsigned)EltIdx == (i + NumElems)) &&
10989 (SndLaneEltIdx < 0 ||
10990 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10991 MaskValue |= (1 << i);
10997 *MaskOut = MaskValue;
11001 // Try to lower a shuffle node into a simple blend instruction.
11002 // This function assumes isBlendMask returns true for this
11003 // SuffleVectorSDNode
11004 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
11005 unsigned MaskValue,
11006 const X86Subtarget *Subtarget,
11007 SelectionDAG &DAG) {
11008 MVT VT = SVOp->getSimpleValueType(0);
11009 MVT EltVT = VT.getVectorElementType();
11010 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11011 Subtarget->hasInt256() && "Trying to lower a "
11012 "VECTOR_SHUFFLE to a Blend but "
11013 "with the wrong mask"));
11014 SDValue V1 = SVOp->getOperand(0);
11015 SDValue V2 = SVOp->getOperand(1);
11017 unsigned NumElems = VT.getVectorNumElements();
11019 // Convert i32 vectors to floating point if it is not AVX2.
11020 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11022 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11023 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11025 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11026 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11029 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11030 DAG.getConstant(MaskValue, MVT::i32));
11031 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11034 /// In vector type \p VT, return true if the element at index \p InputIdx
11035 /// falls on a different 128-bit lane than \p OutputIdx.
11036 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11037 unsigned OutputIdx) {
11038 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11039 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11042 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11043 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11044 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11045 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11047 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11048 SelectionDAG &DAG) {
11049 MVT VT = V1.getSimpleValueType();
11050 assert(VT.is128BitVector() || VT.is256BitVector());
11052 MVT EltVT = VT.getVectorElementType();
11053 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11054 unsigned NumElts = VT.getVectorNumElements();
11056 SmallVector<SDValue, 32> PshufbMask;
11057 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11058 int InputIdx = MaskVals[OutputIdx];
11059 unsigned InputByteIdx;
11061 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11062 InputByteIdx = 0x80;
11064 // Cross lane is not allowed.
11065 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11067 InputByteIdx = InputIdx * EltSizeInBytes;
11068 // Index is an byte offset within the 128-bit lane.
11069 InputByteIdx &= 0xf;
11072 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11073 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11074 if (InputByteIdx != 0x80)
11079 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11081 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11082 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11083 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11086 // v8i16 shuffles - Prefer shuffles in the following order:
11087 // 1. [all] pshuflw, pshufhw, optional move
11088 // 2. [ssse3] 1 x pshufb
11089 // 3. [ssse3] 2 x pshufb + 1 x por
11090 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11092 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11093 SelectionDAG &DAG) {
11094 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11095 SDValue V1 = SVOp->getOperand(0);
11096 SDValue V2 = SVOp->getOperand(1);
11098 SmallVector<int, 8> MaskVals;
11100 // Determine if more than 1 of the words in each of the low and high quadwords
11101 // of the result come from the same quadword of one of the two inputs. Undef
11102 // mask values count as coming from any quadword, for better codegen.
11104 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11105 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11106 unsigned LoQuad[] = { 0, 0, 0, 0 };
11107 unsigned HiQuad[] = { 0, 0, 0, 0 };
11108 // Indices of quads used.
11109 std::bitset<4> InputQuads;
11110 for (unsigned i = 0; i < 8; ++i) {
11111 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11112 int EltIdx = SVOp->getMaskElt(i);
11113 MaskVals.push_back(EltIdx);
11121 ++Quad[EltIdx / 4];
11122 InputQuads.set(EltIdx / 4);
11125 int BestLoQuad = -1;
11126 unsigned MaxQuad = 1;
11127 for (unsigned i = 0; i < 4; ++i) {
11128 if (LoQuad[i] > MaxQuad) {
11130 MaxQuad = LoQuad[i];
11134 int BestHiQuad = -1;
11136 for (unsigned i = 0; i < 4; ++i) {
11137 if (HiQuad[i] > MaxQuad) {
11139 MaxQuad = HiQuad[i];
11143 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11144 // of the two input vectors, shuffle them into one input vector so only a
11145 // single pshufb instruction is necessary. If there are more than 2 input
11146 // quads, disable the next transformation since it does not help SSSE3.
11147 bool V1Used = InputQuads[0] || InputQuads[1];
11148 bool V2Used = InputQuads[2] || InputQuads[3];
11149 if (Subtarget->hasSSSE3()) {
11150 if (InputQuads.count() == 2 && V1Used && V2Used) {
11151 BestLoQuad = InputQuads[0] ? 0 : 1;
11152 BestHiQuad = InputQuads[2] ? 2 : 3;
11154 if (InputQuads.count() > 2) {
11160 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11161 // the shuffle mask. If a quad is scored as -1, that means that it contains
11162 // words from all 4 input quadwords.
11164 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11166 BestLoQuad < 0 ? 0 : BestLoQuad,
11167 BestHiQuad < 0 ? 1 : BestHiQuad
11169 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11170 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11171 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11172 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11174 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11175 // source words for the shuffle, to aid later transformations.
11176 bool AllWordsInNewV = true;
11177 bool InOrder[2] = { true, true };
11178 for (unsigned i = 0; i != 8; ++i) {
11179 int idx = MaskVals[i];
11181 InOrder[i/4] = false;
11182 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11184 AllWordsInNewV = false;
11188 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11189 if (AllWordsInNewV) {
11190 for (int i = 0; i != 8; ++i) {
11191 int idx = MaskVals[i];
11194 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11195 if ((idx != i) && idx < 4)
11197 if ((idx != i) && idx > 3)
11206 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11207 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11208 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11209 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11210 unsigned TargetMask = 0;
11211 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11212 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11213 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11214 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11215 getShufflePSHUFLWImmediate(SVOp);
11216 V1 = NewV.getOperand(0);
11217 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11221 // Promote splats to a larger type which usually leads to more efficient code.
11222 // FIXME: Is this true if pshufb is available?
11223 if (SVOp->isSplat())
11224 return PromoteSplat(SVOp, DAG);
11226 // If we have SSSE3, and all words of the result are from 1 input vector,
11227 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11228 // is present, fall back to case 4.
11229 if (Subtarget->hasSSSE3()) {
11230 SmallVector<SDValue,16> pshufbMask;
11232 // If we have elements from both input vectors, set the high bit of the
11233 // shuffle mask element to zero out elements that come from V2 in the V1
11234 // mask, and elements that come from V1 in the V2 mask, so that the two
11235 // results can be OR'd together.
11236 bool TwoInputs = V1Used && V2Used;
11237 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11239 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11241 // Calculate the shuffle mask for the second input, shuffle it, and
11242 // OR it with the first shuffled input.
11243 CommuteVectorShuffleMask(MaskVals, 8);
11244 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11245 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11246 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11249 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11250 // and update MaskVals with new element order.
11251 std::bitset<8> InOrder;
11252 if (BestLoQuad >= 0) {
11253 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11254 for (int i = 0; i != 4; ++i) {
11255 int idx = MaskVals[i];
11258 } else if ((idx / 4) == BestLoQuad) {
11259 MaskV[i] = idx & 3;
11263 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11266 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11267 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11268 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11269 NewV.getOperand(0),
11270 getShufflePSHUFLWImmediate(SVOp), DAG);
11274 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11275 // and update MaskVals with the new element order.
11276 if (BestHiQuad >= 0) {
11277 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11278 for (unsigned i = 4; i != 8; ++i) {
11279 int idx = MaskVals[i];
11282 } else if ((idx / 4) == BestHiQuad) {
11283 MaskV[i] = (idx & 3) + 4;
11287 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11290 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11291 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11292 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11293 NewV.getOperand(0),
11294 getShufflePSHUFHWImmediate(SVOp), DAG);
11298 // In case BestHi & BestLo were both -1, which means each quadword has a word
11299 // from each of the four input quadwords, calculate the InOrder bitvector now
11300 // before falling through to the insert/extract cleanup.
11301 if (BestLoQuad == -1 && BestHiQuad == -1) {
11303 for (int i = 0; i != 8; ++i)
11304 if (MaskVals[i] < 0 || MaskVals[i] == i)
11308 // The other elements are put in the right place using pextrw and pinsrw.
11309 for (unsigned i = 0; i != 8; ++i) {
11312 int EltIdx = MaskVals[i];
11315 SDValue ExtOp = (EltIdx < 8) ?
11316 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11317 DAG.getIntPtrConstant(EltIdx)) :
11318 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11319 DAG.getIntPtrConstant(EltIdx - 8));
11320 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11321 DAG.getIntPtrConstant(i));
11326 /// \brief v16i16 shuffles
11328 /// FIXME: We only support generation of a single pshufb currently. We can
11329 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11330 /// well (e.g 2 x pshufb + 1 x por).
11332 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11333 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11334 SDValue V1 = SVOp->getOperand(0);
11335 SDValue V2 = SVOp->getOperand(1);
11338 if (V2.getOpcode() != ISD::UNDEF)
11341 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11342 return getPSHUFB(MaskVals, V1, dl, DAG);
11345 // v16i8 shuffles - Prefer shuffles in the following order:
11346 // 1. [ssse3] 1 x pshufb
11347 // 2. [ssse3] 2 x pshufb + 1 x por
11348 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11349 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11350 const X86Subtarget* Subtarget,
11351 SelectionDAG &DAG) {
11352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11353 SDValue V1 = SVOp->getOperand(0);
11354 SDValue V2 = SVOp->getOperand(1);
11356 ArrayRef<int> MaskVals = SVOp->getMask();
11358 // Promote splats to a larger type which usually leads to more efficient code.
11359 // FIXME: Is this true if pshufb is available?
11360 if (SVOp->isSplat())
11361 return PromoteSplat(SVOp, DAG);
11363 // If we have SSSE3, case 1 is generated when all result bytes come from
11364 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11365 // present, fall back to case 3.
11367 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11368 if (Subtarget->hasSSSE3()) {
11369 SmallVector<SDValue,16> pshufbMask;
11371 // If all result elements are from one input vector, then only translate
11372 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11374 // Otherwise, we have elements from both input vectors, and must zero out
11375 // elements that come from V2 in the first mask, and V1 in the second mask
11376 // so that we can OR them together.
11377 for (unsigned i = 0; i != 16; ++i) {
11378 int EltIdx = MaskVals[i];
11379 if (EltIdx < 0 || EltIdx >= 16)
11381 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11383 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11384 DAG.getNode(ISD::BUILD_VECTOR, dl,
11385 MVT::v16i8, pshufbMask));
11387 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11388 // the 2nd operand if it's undefined or zero.
11389 if (V2.getOpcode() == ISD::UNDEF ||
11390 ISD::isBuildVectorAllZeros(V2.getNode()))
11393 // Calculate the shuffle mask for the second input, shuffle it, and
11394 // OR it with the first shuffled input.
11395 pshufbMask.clear();
11396 for (unsigned i = 0; i != 16; ++i) {
11397 int EltIdx = MaskVals[i];
11398 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11399 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11401 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11402 DAG.getNode(ISD::BUILD_VECTOR, dl,
11403 MVT::v16i8, pshufbMask));
11404 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11407 // No SSSE3 - Calculate in place words and then fix all out of place words
11408 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11409 // the 16 different words that comprise the two doublequadword input vectors.
11410 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11411 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11413 for (int i = 0; i != 8; ++i) {
11414 int Elt0 = MaskVals[i*2];
11415 int Elt1 = MaskVals[i*2+1];
11417 // This word of the result is all undef, skip it.
11418 if (Elt0 < 0 && Elt1 < 0)
11421 // This word of the result is already in the correct place, skip it.
11422 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11425 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11426 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11429 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11430 // using a single extract together, load it and store it.
11431 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11432 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11433 DAG.getIntPtrConstant(Elt1 / 2));
11434 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11435 DAG.getIntPtrConstant(i));
11439 // If Elt1 is defined, extract it from the appropriate source. If the
11440 // source byte is not also odd, shift the extracted word left 8 bits
11441 // otherwise clear the bottom 8 bits if we need to do an or.
11443 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11444 DAG.getIntPtrConstant(Elt1 / 2));
11445 if ((Elt1 & 1) == 0)
11446 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11448 TLI.getShiftAmountTy(InsElt.getValueType())));
11449 else if (Elt0 >= 0)
11450 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11451 DAG.getConstant(0xFF00, MVT::i16));
11453 // If Elt0 is defined, extract it from the appropriate source. If the
11454 // source byte is not also even, shift the extracted word right 8 bits. If
11455 // Elt1 was also defined, OR the extracted values together before
11456 // inserting them in the result.
11458 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11459 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11460 if ((Elt0 & 1) != 0)
11461 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11463 TLI.getShiftAmountTy(InsElt0.getValueType())));
11464 else if (Elt1 >= 0)
11465 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11466 DAG.getConstant(0x00FF, MVT::i16));
11467 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11470 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11471 DAG.getIntPtrConstant(i));
11473 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11476 // v32i8 shuffles - Translate to VPSHUFB if possible.
11478 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11479 const X86Subtarget *Subtarget,
11480 SelectionDAG &DAG) {
11481 MVT VT = SVOp->getSimpleValueType(0);
11482 SDValue V1 = SVOp->getOperand(0);
11483 SDValue V2 = SVOp->getOperand(1);
11485 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11487 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11488 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11489 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11491 // VPSHUFB may be generated if
11492 // (1) one of input vector is undefined or zeroinitializer.
11493 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11494 // And (2) the mask indexes don't cross the 128-bit lane.
11495 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11496 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11499 if (V1IsAllZero && !V2IsAllZero) {
11500 CommuteVectorShuffleMask(MaskVals, 32);
11503 return getPSHUFB(MaskVals, V1, dl, DAG);
11506 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11507 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11508 /// done when every pair / quad of shuffle mask elements point to elements in
11509 /// the right sequence. e.g.
11510 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11512 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11513 SelectionDAG &DAG) {
11514 MVT VT = SVOp->getSimpleValueType(0);
11516 unsigned NumElems = VT.getVectorNumElements();
11519 switch (VT.SimpleTy) {
11520 default: llvm_unreachable("Unexpected!");
11523 return SDValue(SVOp, 0);
11524 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11525 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11526 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11527 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11528 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11529 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11532 SmallVector<int, 8> MaskVec;
11533 for (unsigned i = 0; i != NumElems; i += Scale) {
11535 for (unsigned j = 0; j != Scale; ++j) {
11536 int EltIdx = SVOp->getMaskElt(i+j);
11540 StartIdx = (EltIdx / Scale);
11541 if (EltIdx != (int)(StartIdx*Scale + j))
11544 MaskVec.push_back(StartIdx);
11547 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11548 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11549 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11552 /// getVZextMovL - Return a zero-extending vector move low node.
11554 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11555 SDValue SrcOp, SelectionDAG &DAG,
11556 const X86Subtarget *Subtarget, SDLoc dl) {
11557 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11558 LoadSDNode *LD = nullptr;
11559 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11560 LD = dyn_cast<LoadSDNode>(SrcOp);
11562 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11564 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11565 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11566 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11567 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11568 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11570 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11571 return DAG.getNode(ISD::BITCAST, dl, VT,
11572 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11573 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11575 SrcOp.getOperand(0)
11581 return DAG.getNode(ISD::BITCAST, dl, VT,
11582 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11583 DAG.getNode(ISD::BITCAST, dl,
11587 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11588 /// which could not be matched by any known target speficic shuffle
11590 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11592 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11593 if (NewOp.getNode())
11596 MVT VT = SVOp->getSimpleValueType(0);
11598 unsigned NumElems = VT.getVectorNumElements();
11599 unsigned NumLaneElems = NumElems / 2;
11602 MVT EltVT = VT.getVectorElementType();
11603 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11606 SmallVector<int, 16> Mask;
11607 for (unsigned l = 0; l < 2; ++l) {
11608 // Build a shuffle mask for the output, discovering on the fly which
11609 // input vectors to use as shuffle operands (recorded in InputUsed).
11610 // If building a suitable shuffle vector proves too hard, then bail
11611 // out with UseBuildVector set.
11612 bool UseBuildVector = false;
11613 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11614 unsigned LaneStart = l * NumLaneElems;
11615 for (unsigned i = 0; i != NumLaneElems; ++i) {
11616 // The mask element. This indexes into the input.
11617 int Idx = SVOp->getMaskElt(i+LaneStart);
11619 // the mask element does not index into any input vector.
11620 Mask.push_back(-1);
11624 // The input vector this mask element indexes into.
11625 int Input = Idx / NumLaneElems;
11627 // Turn the index into an offset from the start of the input vector.
11628 Idx -= Input * NumLaneElems;
11630 // Find or create a shuffle vector operand to hold this input.
11632 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11633 if (InputUsed[OpNo] == Input)
11634 // This input vector is already an operand.
11636 if (InputUsed[OpNo] < 0) {
11637 // Create a new operand for this input vector.
11638 InputUsed[OpNo] = Input;
11643 if (OpNo >= array_lengthof(InputUsed)) {
11644 // More than two input vectors used! Give up on trying to create a
11645 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11646 UseBuildVector = true;
11650 // Add the mask index for the new shuffle vector.
11651 Mask.push_back(Idx + OpNo * NumLaneElems);
11654 if (UseBuildVector) {
11655 SmallVector<SDValue, 16> SVOps;
11656 for (unsigned i = 0; i != NumLaneElems; ++i) {
11657 // The mask element. This indexes into the input.
11658 int Idx = SVOp->getMaskElt(i+LaneStart);
11660 SVOps.push_back(DAG.getUNDEF(EltVT));
11664 // The input vector this mask element indexes into.
11665 int Input = Idx / NumElems;
11667 // Turn the index into an offset from the start of the input vector.
11668 Idx -= Input * NumElems;
11670 // Extract the vector element by hand.
11671 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11672 SVOp->getOperand(Input),
11673 DAG.getIntPtrConstant(Idx)));
11676 // Construct the output using a BUILD_VECTOR.
11677 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11678 } else if (InputUsed[0] < 0) {
11679 // No input vectors were used! The result is undefined.
11680 Output[l] = DAG.getUNDEF(NVT);
11682 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11683 (InputUsed[0] % 2) * NumLaneElems,
11685 // If only one input was used, use an undefined vector for the other.
11686 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11687 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11688 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11689 // At least one input vector was used. Create a new shuffle vector.
11690 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11696 // Concatenate the result back
11697 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11700 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11701 /// 4 elements, and match them with several different shuffle types.
11703 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11704 SDValue V1 = SVOp->getOperand(0);
11705 SDValue V2 = SVOp->getOperand(1);
11707 MVT VT = SVOp->getSimpleValueType(0);
11709 assert(VT.is128BitVector() && "Unsupported vector size");
11711 std::pair<int, int> Locs[4];
11712 int Mask1[] = { -1, -1, -1, -1 };
11713 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11715 unsigned NumHi = 0;
11716 unsigned NumLo = 0;
11717 for (unsigned i = 0; i != 4; ++i) {
11718 int Idx = PermMask[i];
11720 Locs[i] = std::make_pair(-1, -1);
11722 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11724 Locs[i] = std::make_pair(0, NumLo);
11725 Mask1[NumLo] = Idx;
11728 Locs[i] = std::make_pair(1, NumHi);
11730 Mask1[2+NumHi] = Idx;
11736 if (NumLo <= 2 && NumHi <= 2) {
11737 // If no more than two elements come from either vector. This can be
11738 // implemented with two shuffles. First shuffle gather the elements.
11739 // The second shuffle, which takes the first shuffle as both of its
11740 // vector operands, put the elements into the right order.
11741 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11743 int Mask2[] = { -1, -1, -1, -1 };
11745 for (unsigned i = 0; i != 4; ++i)
11746 if (Locs[i].first != -1) {
11747 unsigned Idx = (i < 2) ? 0 : 4;
11748 Idx += Locs[i].first * 2 + Locs[i].second;
11752 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11755 if (NumLo == 3 || NumHi == 3) {
11756 // Otherwise, we must have three elements from one vector, call it X, and
11757 // one element from the other, call it Y. First, use a shufps to build an
11758 // intermediate vector with the one element from Y and the element from X
11759 // that will be in the same half in the final destination (the indexes don't
11760 // matter). Then, use a shufps to build the final vector, taking the half
11761 // containing the element from Y from the intermediate, and the other half
11764 // Normalize it so the 3 elements come from V1.
11765 CommuteVectorShuffleMask(PermMask, 4);
11769 // Find the element from V2.
11771 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11772 int Val = PermMask[HiIndex];
11779 Mask1[0] = PermMask[HiIndex];
11781 Mask1[2] = PermMask[HiIndex^1];
11783 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11785 if (HiIndex >= 2) {
11786 Mask1[0] = PermMask[0];
11787 Mask1[1] = PermMask[1];
11788 Mask1[2] = HiIndex & 1 ? 6 : 4;
11789 Mask1[3] = HiIndex & 1 ? 4 : 6;
11790 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11793 Mask1[0] = HiIndex & 1 ? 2 : 0;
11794 Mask1[1] = HiIndex & 1 ? 0 : 2;
11795 Mask1[2] = PermMask[2];
11796 Mask1[3] = PermMask[3];
11801 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11804 // Break it into (shuffle shuffle_hi, shuffle_lo).
11805 int LoMask[] = { -1, -1, -1, -1 };
11806 int HiMask[] = { -1, -1, -1, -1 };
11808 int *MaskPtr = LoMask;
11809 unsigned MaskIdx = 0;
11810 unsigned LoIdx = 0;
11811 unsigned HiIdx = 2;
11812 for (unsigned i = 0; i != 4; ++i) {
11819 int Idx = PermMask[i];
11821 Locs[i] = std::make_pair(-1, -1);
11822 } else if (Idx < 4) {
11823 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11824 MaskPtr[LoIdx] = Idx;
11827 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11828 MaskPtr[HiIdx] = Idx;
11833 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11834 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11835 int MaskOps[] = { -1, -1, -1, -1 };
11836 for (unsigned i = 0; i != 4; ++i)
11837 if (Locs[i].first != -1)
11838 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11839 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11842 static bool MayFoldVectorLoad(SDValue V) {
11843 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11844 V = V.getOperand(0);
11846 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11847 V = V.getOperand(0);
11848 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11849 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11850 // BUILD_VECTOR (load), undef
11851 V = V.getOperand(0);
11853 return MayFoldLoad(V);
11857 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11858 MVT VT = Op.getSimpleValueType();
11860 // Canonizalize to v2f64.
11861 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11862 return DAG.getNode(ISD::BITCAST, dl, VT,
11863 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11868 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11870 SDValue V1 = Op.getOperand(0);
11871 SDValue V2 = Op.getOperand(1);
11872 MVT VT = Op.getSimpleValueType();
11874 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11876 if (HasSSE2 && VT == MVT::v2f64)
11877 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11879 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11880 return DAG.getNode(ISD::BITCAST, dl, VT,
11881 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11882 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11883 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11887 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11888 SDValue V1 = Op.getOperand(0);
11889 SDValue V2 = Op.getOperand(1);
11890 MVT VT = Op.getSimpleValueType();
11892 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11893 "unsupported shuffle type");
11895 if (V2.getOpcode() == ISD::UNDEF)
11899 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11903 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11904 SDValue V1 = Op.getOperand(0);
11905 SDValue V2 = Op.getOperand(1);
11906 MVT VT = Op.getSimpleValueType();
11907 unsigned NumElems = VT.getVectorNumElements();
11909 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11910 // operand of these instructions is only memory, so check if there's a
11911 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11913 bool CanFoldLoad = false;
11915 // Trivial case, when V2 comes from a load.
11916 if (MayFoldVectorLoad(V2))
11917 CanFoldLoad = true;
11919 // When V1 is a load, it can be folded later into a store in isel, example:
11920 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11922 // (MOVLPSmr addr:$src1, VR128:$src2)
11923 // So, recognize this potential and also use MOVLPS or MOVLPD
11924 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11925 CanFoldLoad = true;
11927 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11929 if (HasSSE2 && NumElems == 2)
11930 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11933 // If we don't care about the second element, proceed to use movss.
11934 if (SVOp->getMaskElt(1) != -1)
11935 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11938 // movl and movlp will both match v2i64, but v2i64 is never matched by
11939 // movl earlier because we make it strict to avoid messing with the movlp load
11940 // folding logic (see the code above getMOVLP call). Match it here then,
11941 // this is horrible, but will stay like this until we move all shuffle
11942 // matching to x86 specific nodes. Note that for the 1st condition all
11943 // types are matched with movsd.
11945 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11946 // as to remove this logic from here, as much as possible
11947 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11948 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11949 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11952 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11954 // Invert the operand order and use SHUFPS to match it.
11955 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11956 getShuffleSHUFImmediate(SVOp), DAG);
11959 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11960 SelectionDAG &DAG) {
11962 MVT VT = Load->getSimpleValueType(0);
11963 MVT EVT = VT.getVectorElementType();
11964 SDValue Addr = Load->getOperand(1);
11965 SDValue NewAddr = DAG.getNode(
11966 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11967 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11970 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11971 DAG.getMachineFunction().getMachineMemOperand(
11972 Load->getMemOperand(), 0, EVT.getStoreSize()));
11976 // It is only safe to call this function if isINSERTPSMask is true for
11977 // this shufflevector mask.
11978 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11979 SelectionDAG &DAG) {
11980 // Generate an insertps instruction when inserting an f32 from memory onto a
11981 // v4f32 or when copying a member from one v4f32 to another.
11982 // We also use it for transferring i32 from one register to another,
11983 // since it simply copies the same bits.
11984 // If we're transferring an i32 from memory to a specific element in a
11985 // register, we output a generic DAG that will match the PINSRD
11987 MVT VT = SVOp->getSimpleValueType(0);
11988 MVT EVT = VT.getVectorElementType();
11989 SDValue V1 = SVOp->getOperand(0);
11990 SDValue V2 = SVOp->getOperand(1);
11991 auto Mask = SVOp->getMask();
11992 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11993 "unsupported vector type for insertps/pinsrd");
11995 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11996 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11997 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
12001 unsigned DestIndex;
12005 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
12008 // If we have 1 element from each vector, we have to check if we're
12009 // changing V1's element's place. If so, we're done. Otherwise, we
12010 // should assume we're changing V2's element's place and behave
12012 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12013 assert(DestIndex <= INT32_MAX && "truncated destination index");
12014 if (FromV1 == FromV2 &&
12015 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12019 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12022 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12023 "More than one element from V1 and from V2, or no elements from one "
12024 "of the vectors. This case should not have returned true from "
12029 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12032 // Get an index into the source vector in the range [0,4) (the mask is
12033 // in the range [0,8) because it can address V1 and V2)
12034 unsigned SrcIndex = Mask[DestIndex] % 4;
12035 if (MayFoldLoad(From)) {
12036 // Trivial case, when From comes from a load and is only used by the
12037 // shuffle. Make it use insertps from the vector that we need from that
12040 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12041 if (!NewLoad.getNode())
12044 if (EVT == MVT::f32) {
12045 // Create this as a scalar to vector to match the instruction pattern.
12046 SDValue LoadScalarToVector =
12047 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12048 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12049 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12051 } else { // EVT == MVT::i32
12052 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12053 // instruction, to match the PINSRD instruction, which loads an i32 to a
12054 // certain vector element.
12055 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12056 DAG.getConstant(DestIndex, MVT::i32));
12060 // Vector-element-to-vector
12061 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12062 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12065 // Reduce a vector shuffle to zext.
12066 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12067 SelectionDAG &DAG) {
12068 // PMOVZX is only available from SSE41.
12069 if (!Subtarget->hasSSE41())
12072 MVT VT = Op.getSimpleValueType();
12074 // Only AVX2 support 256-bit vector integer extending.
12075 if (!Subtarget->hasInt256() && VT.is256BitVector())
12078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12080 SDValue V1 = Op.getOperand(0);
12081 SDValue V2 = Op.getOperand(1);
12082 unsigned NumElems = VT.getVectorNumElements();
12084 // Extending is an unary operation and the element type of the source vector
12085 // won't be equal to or larger than i64.
12086 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12087 VT.getVectorElementType() == MVT::i64)
12090 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12091 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12092 while ((1U << Shift) < NumElems) {
12093 if (SVOp->getMaskElt(1U << Shift) == 1)
12096 // The maximal ratio is 8, i.e. from i8 to i64.
12101 // Check the shuffle mask.
12102 unsigned Mask = (1U << Shift) - 1;
12103 for (unsigned i = 0; i != NumElems; ++i) {
12104 int EltIdx = SVOp->getMaskElt(i);
12105 if ((i & Mask) != 0 && EltIdx != -1)
12107 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12111 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12112 MVT NeVT = MVT::getIntegerVT(NBits);
12113 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12115 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12118 return DAG.getNode(ISD::BITCAST, DL, VT,
12119 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12122 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12123 SelectionDAG &DAG) {
12124 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12125 MVT VT = Op.getSimpleValueType();
12127 SDValue V1 = Op.getOperand(0);
12128 SDValue V2 = Op.getOperand(1);
12130 if (isZeroShuffle(SVOp))
12131 return getZeroVector(VT, Subtarget, DAG, dl);
12133 // Handle splat operations
12134 if (SVOp->isSplat()) {
12135 // Use vbroadcast whenever the splat comes from a foldable load
12136 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12137 if (Broadcast.getNode())
12141 // Check integer expanding shuffles.
12142 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12143 if (NewOp.getNode())
12146 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12148 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12149 VT == MVT::v32i8) {
12150 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12151 if (NewOp.getNode())
12152 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12153 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12154 // FIXME: Figure out a cleaner way to do this.
12155 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12156 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12157 if (NewOp.getNode()) {
12158 MVT NewVT = NewOp.getSimpleValueType();
12159 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12160 NewVT, true, false))
12161 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12164 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12165 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12166 if (NewOp.getNode()) {
12167 MVT NewVT = NewOp.getSimpleValueType();
12168 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12169 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12178 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12179 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12180 SDValue V1 = Op.getOperand(0);
12181 SDValue V2 = Op.getOperand(1);
12182 MVT VT = Op.getSimpleValueType();
12184 unsigned NumElems = VT.getVectorNumElements();
12185 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12186 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12187 bool V1IsSplat = false;
12188 bool V2IsSplat = false;
12189 bool HasSSE2 = Subtarget->hasSSE2();
12190 bool HasFp256 = Subtarget->hasFp256();
12191 bool HasInt256 = Subtarget->hasInt256();
12192 MachineFunction &MF = DAG.getMachineFunction();
12193 bool OptForSize = MF.getFunction()->getAttributes().
12194 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12196 // Check if we should use the experimental vector shuffle lowering. If so,
12197 // delegate completely to that code path.
12198 if (ExperimentalVectorShuffleLowering)
12199 return lowerVectorShuffle(Op, Subtarget, DAG);
12201 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12203 if (V1IsUndef && V2IsUndef)
12204 return DAG.getUNDEF(VT);
12206 // When we create a shuffle node we put the UNDEF node to second operand,
12207 // but in some cases the first operand may be transformed to UNDEF.
12208 // In this case we should just commute the node.
12210 return DAG.getCommutedVectorShuffle(*SVOp);
12212 // Vector shuffle lowering takes 3 steps:
12214 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12215 // narrowing and commutation of operands should be handled.
12216 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12218 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12219 // so the shuffle can be broken into other shuffles and the legalizer can
12220 // try the lowering again.
12222 // The general idea is that no vector_shuffle operation should be left to
12223 // be matched during isel, all of them must be converted to a target specific
12226 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12227 // narrowing and commutation of operands should be handled. The actual code
12228 // doesn't include all of those, work in progress...
12229 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12230 if (NewOp.getNode())
12233 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12235 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12236 // unpckh_undef). Only use pshufd if speed is more important than size.
12237 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12238 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12239 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12240 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12242 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12243 V2IsUndef && MayFoldVectorLoad(V1))
12244 return getMOVDDup(Op, dl, V1, DAG);
12246 if (isMOVHLPS_v_undef_Mask(M, VT))
12247 return getMOVHighToLow(Op, dl, DAG);
12249 // Use to match splats
12250 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12251 (VT == MVT::v2f64 || VT == MVT::v2i64))
12252 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12254 if (isPSHUFDMask(M, VT)) {
12255 // The actual implementation will match the mask in the if above and then
12256 // during isel it can match several different instructions, not only pshufd
12257 // as its name says, sad but true, emulate the behavior for now...
12258 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12259 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12261 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12263 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12264 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12266 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12267 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12270 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12274 if (isPALIGNRMask(M, VT, Subtarget))
12275 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12276 getShufflePALIGNRImmediate(SVOp),
12279 if (isVALIGNMask(M, VT, Subtarget))
12280 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12281 getShuffleVALIGNImmediate(SVOp),
12284 // Check if this can be converted into a logical shift.
12285 bool isLeft = false;
12286 unsigned ShAmt = 0;
12288 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12289 if (isShift && ShVal.hasOneUse()) {
12290 // If the shifted value has multiple uses, it may be cheaper to use
12291 // v_set0 + movlhps or movhlps, etc.
12292 MVT EltVT = VT.getVectorElementType();
12293 ShAmt *= EltVT.getSizeInBits();
12294 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12297 if (isMOVLMask(M, VT)) {
12298 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12299 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12300 if (!isMOVLPMask(M, VT)) {
12301 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12302 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12304 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12305 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12309 // FIXME: fold these into legal mask.
12310 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12311 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12313 if (isMOVHLPSMask(M, VT))
12314 return getMOVHighToLow(Op, dl, DAG);
12316 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12317 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12319 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12320 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12322 if (isMOVLPMask(M, VT))
12323 return getMOVLP(Op, dl, DAG, HasSSE2);
12325 if (ShouldXformToMOVHLPS(M, VT) ||
12326 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12327 return DAG.getCommutedVectorShuffle(*SVOp);
12330 // No better options. Use a vshldq / vsrldq.
12331 MVT EltVT = VT.getVectorElementType();
12332 ShAmt *= EltVT.getSizeInBits();
12333 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12336 bool Commuted = false;
12337 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12338 // 1,1,1,1 -> v8i16 though.
12339 BitVector UndefElements;
12340 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12341 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12343 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12344 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12347 // Canonicalize the splat or undef, if present, to be on the RHS.
12348 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12349 CommuteVectorShuffleMask(M, NumElems);
12351 std::swap(V1IsSplat, V2IsSplat);
12355 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12356 // Shuffling low element of v1 into undef, just return v1.
12359 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12360 // the instruction selector will not match, so get a canonical MOVL with
12361 // swapped operands to undo the commute.
12362 return getMOVL(DAG, dl, VT, V2, V1);
12365 if (isUNPCKLMask(M, VT, HasInt256))
12366 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12368 if (isUNPCKHMask(M, VT, HasInt256))
12369 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12372 // Normalize mask so all entries that point to V2 points to its first
12373 // element then try to match unpck{h|l} again. If match, return a
12374 // new vector_shuffle with the corrected mask.p
12375 SmallVector<int, 8> NewMask(M.begin(), M.end());
12376 NormalizeMask(NewMask, NumElems);
12377 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12378 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12379 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12380 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12384 // Commute is back and try unpck* again.
12385 // FIXME: this seems wrong.
12386 CommuteVectorShuffleMask(M, NumElems);
12388 std::swap(V1IsSplat, V2IsSplat);
12390 if (isUNPCKLMask(M, VT, HasInt256))
12391 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12393 if (isUNPCKHMask(M, VT, HasInt256))
12394 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12397 // Normalize the node to match x86 shuffle ops if needed
12398 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12399 return DAG.getCommutedVectorShuffle(*SVOp);
12401 // The checks below are all present in isShuffleMaskLegal, but they are
12402 // inlined here right now to enable us to directly emit target specific
12403 // nodes, and remove one by one until they don't return Op anymore.
12405 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12406 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12407 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12408 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12411 if (isPSHUFHWMask(M, VT, HasInt256))
12412 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12413 getShufflePSHUFHWImmediate(SVOp),
12416 if (isPSHUFLWMask(M, VT, HasInt256))
12417 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12418 getShufflePSHUFLWImmediate(SVOp),
12421 unsigned MaskValue;
12422 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12424 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12426 if (isSHUFPMask(M, VT))
12427 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12428 getShuffleSHUFImmediate(SVOp), DAG);
12430 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12431 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12432 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12433 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12435 //===--------------------------------------------------------------------===//
12436 // Generate target specific nodes for 128 or 256-bit shuffles only
12437 // supported in the AVX instruction set.
12440 // Handle VMOVDDUPY permutations
12441 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12442 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12444 // Handle VPERMILPS/D* permutations
12445 if (isVPERMILPMask(M, VT)) {
12446 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12447 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12448 getShuffleSHUFImmediate(SVOp), DAG);
12449 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12450 getShuffleSHUFImmediate(SVOp), DAG);
12454 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12455 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12456 Idx*(NumElems/2), DAG, dl);
12458 // Handle VPERM2F128/VPERM2I128 permutations
12459 if (isVPERM2X128Mask(M, VT, HasFp256))
12460 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12461 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12463 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12464 return getINSERTPS(SVOp, dl, DAG);
12467 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12468 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12470 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12471 VT.is512BitVector()) {
12472 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12473 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12474 SmallVector<SDValue, 16> permclMask;
12475 for (unsigned i = 0; i != NumElems; ++i) {
12476 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12479 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12481 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12482 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12483 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12484 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12485 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12488 //===--------------------------------------------------------------------===//
12489 // Since no target specific shuffle was selected for this generic one,
12490 // lower it into other known shuffles. FIXME: this isn't true yet, but
12491 // this is the plan.
12494 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12495 if (VT == MVT::v8i16) {
12496 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12497 if (NewOp.getNode())
12501 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12502 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12503 if (NewOp.getNode())
12507 if (VT == MVT::v16i8) {
12508 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12509 if (NewOp.getNode())
12513 if (VT == MVT::v32i8) {
12514 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12515 if (NewOp.getNode())
12519 // Handle all 128-bit wide vectors with 4 elements, and match them with
12520 // several different shuffle types.
12521 if (NumElems == 4 && VT.is128BitVector())
12522 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12524 // Handle general 256-bit shuffles
12525 if (VT.is256BitVector())
12526 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12531 // This function assumes its argument is a BUILD_VECTOR of constants or
12532 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12534 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12535 unsigned &MaskValue) {
12537 unsigned NumElems = BuildVector->getNumOperands();
12538 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12539 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12540 unsigned NumElemsInLane = NumElems / NumLanes;
12542 // Blend for v16i16 should be symetric for the both lanes.
12543 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12544 SDValue EltCond = BuildVector->getOperand(i);
12545 SDValue SndLaneEltCond =
12546 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12548 int Lane1Cond = -1, Lane2Cond = -1;
12549 if (isa<ConstantSDNode>(EltCond))
12550 Lane1Cond = !isZero(EltCond);
12551 if (isa<ConstantSDNode>(SndLaneEltCond))
12552 Lane2Cond = !isZero(SndLaneEltCond);
12554 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12555 // Lane1Cond != 0, means we want the first argument.
12556 // Lane1Cond == 0, means we want the second argument.
12557 // The encoding of this argument is 0 for the first argument, 1
12558 // for the second. Therefore, invert the condition.
12559 MaskValue |= !Lane1Cond << i;
12560 else if (Lane1Cond < 0)
12561 MaskValue |= !Lane2Cond << i;
12568 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12570 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12571 SelectionDAG &DAG) {
12572 SDValue Cond = Op.getOperand(0);
12573 SDValue LHS = Op.getOperand(1);
12574 SDValue RHS = Op.getOperand(2);
12576 MVT VT = Op.getSimpleValueType();
12577 MVT EltVT = VT.getVectorElementType();
12578 unsigned NumElems = VT.getVectorNumElements();
12580 // There is no blend with immediate in AVX-512.
12581 if (VT.is512BitVector())
12584 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12586 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12589 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12592 // Check the mask for BLEND and build the value.
12593 unsigned MaskValue = 0;
12594 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12597 // Convert i32 vectors to floating point if it is not AVX2.
12598 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12600 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12601 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12603 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12604 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12607 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12608 DAG.getConstant(MaskValue, MVT::i32));
12609 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12612 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12613 // A vselect where all conditions and data are constants can be optimized into
12614 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12615 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12616 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12617 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12620 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12621 if (BlendOp.getNode())
12624 // Some types for vselect were previously set to Expand, not Legal or
12625 // Custom. Return an empty SDValue so we fall-through to Expand, after
12626 // the Custom lowering phase.
12627 MVT VT = Op.getSimpleValueType();
12628 switch (VT.SimpleTy) {
12633 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12638 // We couldn't create a "Blend with immediate" node.
12639 // This node should still be legal, but we'll have to emit a blendv*
12644 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12645 MVT VT = Op.getSimpleValueType();
12648 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12651 if (VT.getSizeInBits() == 8) {
12652 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12653 Op.getOperand(0), Op.getOperand(1));
12654 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12655 DAG.getValueType(VT));
12656 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12659 if (VT.getSizeInBits() == 16) {
12660 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12661 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12663 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12664 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12665 DAG.getNode(ISD::BITCAST, dl,
12668 Op.getOperand(1)));
12669 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12670 Op.getOperand(0), Op.getOperand(1));
12671 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12672 DAG.getValueType(VT));
12673 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12676 if (VT == MVT::f32) {
12677 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12678 // the result back to FR32 register. It's only worth matching if the
12679 // result has a single use which is a store or a bitcast to i32. And in
12680 // the case of a store, it's not worth it if the index is a constant 0,
12681 // because a MOVSSmr can be used instead, which is smaller and faster.
12682 if (!Op.hasOneUse())
12684 SDNode *User = *Op.getNode()->use_begin();
12685 if ((User->getOpcode() != ISD::STORE ||
12686 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12687 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12688 (User->getOpcode() != ISD::BITCAST ||
12689 User->getValueType(0) != MVT::i32))
12691 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12692 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12695 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12698 if (VT == MVT::i32 || VT == MVT::i64) {
12699 // ExtractPS/pextrq works with constant index.
12700 if (isa<ConstantSDNode>(Op.getOperand(1)))
12706 /// Extract one bit from mask vector, like v16i1 or v8i1.
12707 /// AVX-512 feature.
12709 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12710 SDValue Vec = Op.getOperand(0);
12712 MVT VecVT = Vec.getSimpleValueType();
12713 SDValue Idx = Op.getOperand(1);
12714 MVT EltVT = Op.getSimpleValueType();
12716 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12718 // variable index can't be handled in mask registers,
12719 // extend vector to VR512
12720 if (!isa<ConstantSDNode>(Idx)) {
12721 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12722 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12723 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12724 ExtVT.getVectorElementType(), Ext, Idx);
12725 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12728 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12729 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12730 unsigned MaxSift = rc->getSize()*8 - 1;
12731 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12732 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12733 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12734 DAG.getConstant(MaxSift, MVT::i8));
12735 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12736 DAG.getIntPtrConstant(0));
12740 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12741 SelectionDAG &DAG) const {
12743 SDValue Vec = Op.getOperand(0);
12744 MVT VecVT = Vec.getSimpleValueType();
12745 SDValue Idx = Op.getOperand(1);
12747 if (Op.getSimpleValueType() == MVT::i1)
12748 return ExtractBitFromMaskVector(Op, DAG);
12750 if (!isa<ConstantSDNode>(Idx)) {
12751 if (VecVT.is512BitVector() ||
12752 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12753 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12756 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12757 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12758 MaskEltVT.getSizeInBits());
12760 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12761 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12762 getZeroVector(MaskVT, Subtarget, DAG, dl),
12763 Idx, DAG.getConstant(0, getPointerTy()));
12764 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12765 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12766 Perm, DAG.getConstant(0, getPointerTy()));
12771 // If this is a 256-bit vector result, first extract the 128-bit vector and
12772 // then extract the element from the 128-bit vector.
12773 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12775 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12776 // Get the 128-bit vector.
12777 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12778 MVT EltVT = VecVT.getVectorElementType();
12780 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12782 //if (IdxVal >= NumElems/2)
12783 // IdxVal -= NumElems/2;
12784 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12786 DAG.getConstant(IdxVal, MVT::i32));
12789 assert(VecVT.is128BitVector() && "Unexpected vector length");
12791 if (Subtarget->hasSSE41()) {
12792 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12797 MVT VT = Op.getSimpleValueType();
12798 // TODO: handle v16i8.
12799 if (VT.getSizeInBits() == 16) {
12800 SDValue Vec = Op.getOperand(0);
12801 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12803 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12804 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12805 DAG.getNode(ISD::BITCAST, dl,
12807 Op.getOperand(1)));
12808 // Transform it so it match pextrw which produces a 32-bit result.
12809 MVT EltVT = MVT::i32;
12810 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12811 Op.getOperand(0), Op.getOperand(1));
12812 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12813 DAG.getValueType(VT));
12814 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12817 if (VT.getSizeInBits() == 32) {
12818 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12822 // SHUFPS the element to the lowest double word, then movss.
12823 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12824 MVT VVT = Op.getOperand(0).getSimpleValueType();
12825 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12826 DAG.getUNDEF(VVT), Mask);
12827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12828 DAG.getIntPtrConstant(0));
12831 if (VT.getSizeInBits() == 64) {
12832 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12833 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12834 // to match extract_elt for f64.
12835 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12839 // UNPCKHPD the element to the lowest double word, then movsd.
12840 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12841 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12842 int Mask[2] = { 1, -1 };
12843 MVT VVT = Op.getOperand(0).getSimpleValueType();
12844 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12845 DAG.getUNDEF(VVT), Mask);
12846 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12847 DAG.getIntPtrConstant(0));
12853 /// Insert one bit to mask vector, like v16i1 or v8i1.
12854 /// AVX-512 feature.
12856 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12858 SDValue Vec = Op.getOperand(0);
12859 SDValue Elt = Op.getOperand(1);
12860 SDValue Idx = Op.getOperand(2);
12861 MVT VecVT = Vec.getSimpleValueType();
12863 if (!isa<ConstantSDNode>(Idx)) {
12864 // Non constant index. Extend source and destination,
12865 // insert element and then truncate the result.
12866 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12867 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12868 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12869 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12870 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12871 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12874 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12875 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12876 if (Vec.getOpcode() == ISD::UNDEF)
12877 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12878 DAG.getConstant(IdxVal, MVT::i8));
12879 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12880 unsigned MaxSift = rc->getSize()*8 - 1;
12881 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12882 DAG.getConstant(MaxSift, MVT::i8));
12883 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12884 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12885 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12888 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12889 SelectionDAG &DAG) const {
12890 MVT VT = Op.getSimpleValueType();
12891 MVT EltVT = VT.getVectorElementType();
12893 if (EltVT == MVT::i1)
12894 return InsertBitToMaskVector(Op, DAG);
12897 SDValue N0 = Op.getOperand(0);
12898 SDValue N1 = Op.getOperand(1);
12899 SDValue N2 = Op.getOperand(2);
12900 if (!isa<ConstantSDNode>(N2))
12902 auto *N2C = cast<ConstantSDNode>(N2);
12903 unsigned IdxVal = N2C->getZExtValue();
12905 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12906 // into that, and then insert the subvector back into the result.
12907 if (VT.is256BitVector() || VT.is512BitVector()) {
12908 // Get the desired 128-bit vector half.
12909 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12911 // Insert the element into the desired half.
12912 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12913 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12915 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12916 DAG.getConstant(IdxIn128, MVT::i32));
12918 // Insert the changed part back to the 256-bit vector
12919 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12921 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12923 if (Subtarget->hasSSE41()) {
12924 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12926 if (VT == MVT::v8i16) {
12927 Opc = X86ISD::PINSRW;
12929 assert(VT == MVT::v16i8);
12930 Opc = X86ISD::PINSRB;
12933 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12935 if (N1.getValueType() != MVT::i32)
12936 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12937 if (N2.getValueType() != MVT::i32)
12938 N2 = DAG.getIntPtrConstant(IdxVal);
12939 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12942 if (EltVT == MVT::f32) {
12943 // Bits [7:6] of the constant are the source select. This will always be
12944 // zero here. The DAG Combiner may combine an extract_elt index into
12946 // bits. For example (insert (extract, 3), 2) could be matched by
12948 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12949 // Bits [5:4] of the constant are the destination select. This is the
12950 // value of the incoming immediate.
12951 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12952 // combine either bitwise AND or insert of float 0.0 to set these bits.
12953 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12954 // Create this as a scalar to vector..
12955 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12956 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12959 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12960 // PINSR* works with constant index.
12965 if (EltVT == MVT::i8)
12968 if (EltVT.getSizeInBits() == 16) {
12969 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12970 // as its second argument.
12971 if (N1.getValueType() != MVT::i32)
12972 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12973 if (N2.getValueType() != MVT::i32)
12974 N2 = DAG.getIntPtrConstant(IdxVal);
12975 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12980 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12982 MVT OpVT = Op.getSimpleValueType();
12984 // If this is a 256-bit vector result, first insert into a 128-bit
12985 // vector and then insert into the 256-bit vector.
12986 if (!OpVT.is128BitVector()) {
12987 // Insert into a 128-bit vector.
12988 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12989 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12990 OpVT.getVectorNumElements() / SizeFactor);
12992 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12994 // Insert the 128-bit vector.
12995 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12998 if (OpVT == MVT::v1i64 &&
12999 Op.getOperand(0).getValueType() == MVT::i64)
13000 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
13002 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
13003 assert(OpVT.is128BitVector() && "Expected an SSE type!");
13004 return DAG.getNode(ISD::BITCAST, dl, OpVT,
13005 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
13008 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
13009 // a simple subregister reference or explicit instructions to grab
13010 // upper bits of a vector.
13011 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13012 SelectionDAG &DAG) {
13014 SDValue In = Op.getOperand(0);
13015 SDValue Idx = Op.getOperand(1);
13016 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13017 MVT ResVT = Op.getSimpleValueType();
13018 MVT InVT = In.getSimpleValueType();
13020 if (Subtarget->hasFp256()) {
13021 if (ResVT.is128BitVector() &&
13022 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13023 isa<ConstantSDNode>(Idx)) {
13024 return Extract128BitVector(In, IdxVal, DAG, dl);
13026 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13027 isa<ConstantSDNode>(Idx)) {
13028 return Extract256BitVector(In, IdxVal, DAG, dl);
13034 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13035 // simple superregister reference or explicit instructions to insert
13036 // the upper bits of a vector.
13037 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13038 SelectionDAG &DAG) {
13039 if (Subtarget->hasFp256()) {
13040 SDLoc dl(Op.getNode());
13041 SDValue Vec = Op.getNode()->getOperand(0);
13042 SDValue SubVec = Op.getNode()->getOperand(1);
13043 SDValue Idx = Op.getNode()->getOperand(2);
13045 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13046 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13047 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13048 isa<ConstantSDNode>(Idx)) {
13049 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13050 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13053 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13054 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13055 isa<ConstantSDNode>(Idx)) {
13056 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13057 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13063 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13064 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13065 // one of the above mentioned nodes. It has to be wrapped because otherwise
13066 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13067 // be used to form addressing mode. These wrapped nodes will be selected
13070 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13071 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13073 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13074 // global base reg.
13075 unsigned char OpFlag = 0;
13076 unsigned WrapperKind = X86ISD::Wrapper;
13077 CodeModel::Model M = DAG.getTarget().getCodeModel();
13079 if (Subtarget->isPICStyleRIPRel() &&
13080 (M == CodeModel::Small || M == CodeModel::Kernel))
13081 WrapperKind = X86ISD::WrapperRIP;
13082 else if (Subtarget->isPICStyleGOT())
13083 OpFlag = X86II::MO_GOTOFF;
13084 else if (Subtarget->isPICStyleStubPIC())
13085 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13087 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13088 CP->getAlignment(),
13089 CP->getOffset(), OpFlag);
13091 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13092 // With PIC, the address is actually $g + Offset.
13094 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13095 DAG.getNode(X86ISD::GlobalBaseReg,
13096 SDLoc(), getPointerTy()),
13103 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13104 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13106 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13107 // global base reg.
13108 unsigned char OpFlag = 0;
13109 unsigned WrapperKind = X86ISD::Wrapper;
13110 CodeModel::Model M = DAG.getTarget().getCodeModel();
13112 if (Subtarget->isPICStyleRIPRel() &&
13113 (M == CodeModel::Small || M == CodeModel::Kernel))
13114 WrapperKind = X86ISD::WrapperRIP;
13115 else if (Subtarget->isPICStyleGOT())
13116 OpFlag = X86II::MO_GOTOFF;
13117 else if (Subtarget->isPICStyleStubPIC())
13118 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13120 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13123 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13125 // With PIC, the address is actually $g + Offset.
13127 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13128 DAG.getNode(X86ISD::GlobalBaseReg,
13129 SDLoc(), getPointerTy()),
13136 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13137 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13139 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13140 // global base reg.
13141 unsigned char OpFlag = 0;
13142 unsigned WrapperKind = X86ISD::Wrapper;
13143 CodeModel::Model M = DAG.getTarget().getCodeModel();
13145 if (Subtarget->isPICStyleRIPRel() &&
13146 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13147 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13148 OpFlag = X86II::MO_GOTPCREL;
13149 WrapperKind = X86ISD::WrapperRIP;
13150 } else if (Subtarget->isPICStyleGOT()) {
13151 OpFlag = X86II::MO_GOT;
13152 } else if (Subtarget->isPICStyleStubPIC()) {
13153 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13154 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13155 OpFlag = X86II::MO_DARWIN_NONLAZY;
13158 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13161 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13163 // With PIC, the address is actually $g + Offset.
13164 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13165 !Subtarget->is64Bit()) {
13166 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13167 DAG.getNode(X86ISD::GlobalBaseReg,
13168 SDLoc(), getPointerTy()),
13172 // For symbols that require a load from a stub to get the address, emit the
13174 if (isGlobalStubReference(OpFlag))
13175 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13176 MachinePointerInfo::getGOT(), false, false, false, 0);
13182 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13183 // Create the TargetBlockAddressAddress node.
13184 unsigned char OpFlags =
13185 Subtarget->ClassifyBlockAddressReference();
13186 CodeModel::Model M = DAG.getTarget().getCodeModel();
13187 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13188 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13190 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13193 if (Subtarget->isPICStyleRIPRel() &&
13194 (M == CodeModel::Small || M == CodeModel::Kernel))
13195 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13197 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13199 // With PIC, the address is actually $g + Offset.
13200 if (isGlobalRelativeToPICBase(OpFlags)) {
13201 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13202 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13210 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13211 int64_t Offset, SelectionDAG &DAG) const {
13212 // Create the TargetGlobalAddress node, folding in the constant
13213 // offset if it is legal.
13214 unsigned char OpFlags =
13215 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13216 CodeModel::Model M = DAG.getTarget().getCodeModel();
13218 if (OpFlags == X86II::MO_NO_FLAG &&
13219 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13220 // A direct static reference to a global.
13221 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13224 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13227 if (Subtarget->isPICStyleRIPRel() &&
13228 (M == CodeModel::Small || M == CodeModel::Kernel))
13229 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13231 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13233 // With PIC, the address is actually $g + Offset.
13234 if (isGlobalRelativeToPICBase(OpFlags)) {
13235 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13236 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13240 // For globals that require a load from a stub to get the address, emit the
13242 if (isGlobalStubReference(OpFlags))
13243 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13244 MachinePointerInfo::getGOT(), false, false, false, 0);
13246 // If there was a non-zero offset that we didn't fold, create an explicit
13247 // addition for it.
13249 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13250 DAG.getConstant(Offset, getPointerTy()));
13256 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13257 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13258 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13259 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13263 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13264 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13265 unsigned char OperandFlags, bool LocalDynamic = false) {
13266 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13267 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13269 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13270 GA->getValueType(0),
13274 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13278 SDValue Ops[] = { Chain, TGA, *InFlag };
13279 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13281 SDValue Ops[] = { Chain, TGA };
13282 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13285 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13286 MFI->setAdjustsStack(true);
13287 MFI->setHasCalls(true);
13289 SDValue Flag = Chain.getValue(1);
13290 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13293 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13295 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13298 SDLoc dl(GA); // ? function entry point might be better
13299 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13300 DAG.getNode(X86ISD::GlobalBaseReg,
13301 SDLoc(), PtrVT), InFlag);
13302 InFlag = Chain.getValue(1);
13304 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13307 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13309 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13311 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13312 X86::RAX, X86II::MO_TLSGD);
13315 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13321 // Get the start address of the TLS block for this module.
13322 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13323 .getInfo<X86MachineFunctionInfo>();
13324 MFI->incNumLocalDynamicTLSAccesses();
13328 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13329 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13332 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13333 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13334 InFlag = Chain.getValue(1);
13335 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13336 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13339 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13343 unsigned char OperandFlags = X86II::MO_DTPOFF;
13344 unsigned WrapperKind = X86ISD::Wrapper;
13345 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13346 GA->getValueType(0),
13347 GA->getOffset(), OperandFlags);
13348 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13350 // Add x@dtpoff with the base.
13351 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13354 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13355 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13356 const EVT PtrVT, TLSModel::Model model,
13357 bool is64Bit, bool isPIC) {
13360 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13361 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13362 is64Bit ? 257 : 256));
13364 SDValue ThreadPointer =
13365 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13366 MachinePointerInfo(Ptr), false, false, false, 0);
13368 unsigned char OperandFlags = 0;
13369 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13371 unsigned WrapperKind = X86ISD::Wrapper;
13372 if (model == TLSModel::LocalExec) {
13373 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13374 } else if (model == TLSModel::InitialExec) {
13376 OperandFlags = X86II::MO_GOTTPOFF;
13377 WrapperKind = X86ISD::WrapperRIP;
13379 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13382 llvm_unreachable("Unexpected model");
13385 // emit "addl x@ntpoff,%eax" (local exec)
13386 // or "addl x@indntpoff,%eax" (initial exec)
13387 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13389 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13390 GA->getOffset(), OperandFlags);
13391 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13393 if (model == TLSModel::InitialExec) {
13394 if (isPIC && !is64Bit) {
13395 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13396 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13400 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13401 MachinePointerInfo::getGOT(), false, false, false, 0);
13404 // The address of the thread local variable is the add of the thread
13405 // pointer with the offset of the variable.
13406 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13410 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13412 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13413 const GlobalValue *GV = GA->getGlobal();
13415 if (Subtarget->isTargetELF()) {
13416 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13419 case TLSModel::GeneralDynamic:
13420 if (Subtarget->is64Bit())
13421 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13422 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13423 case TLSModel::LocalDynamic:
13424 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13425 Subtarget->is64Bit());
13426 case TLSModel::InitialExec:
13427 case TLSModel::LocalExec:
13428 return LowerToTLSExecModel(
13429 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13430 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13432 llvm_unreachable("Unknown TLS model.");
13435 if (Subtarget->isTargetDarwin()) {
13436 // Darwin only has one model of TLS. Lower to that.
13437 unsigned char OpFlag = 0;
13438 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13439 X86ISD::WrapperRIP : X86ISD::Wrapper;
13441 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13442 // global base reg.
13443 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13444 !Subtarget->is64Bit();
13446 OpFlag = X86II::MO_TLVP_PIC_BASE;
13448 OpFlag = X86II::MO_TLVP;
13450 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13451 GA->getValueType(0),
13452 GA->getOffset(), OpFlag);
13453 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13455 // With PIC32, the address is actually $g + Offset.
13457 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13458 DAG.getNode(X86ISD::GlobalBaseReg,
13459 SDLoc(), getPointerTy()),
13462 // Lowering the machine isd will make sure everything is in the right
13464 SDValue Chain = DAG.getEntryNode();
13465 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13466 SDValue Args[] = { Chain, Offset };
13467 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13469 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13470 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13471 MFI->setAdjustsStack(true);
13473 // And our return value (tls address) is in the standard call return value
13475 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13476 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13477 Chain.getValue(1));
13480 if (Subtarget->isTargetKnownWindowsMSVC() ||
13481 Subtarget->isTargetWindowsGNU()) {
13482 // Just use the implicit TLS architecture
13483 // Need to generate someting similar to:
13484 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13486 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13487 // mov rcx, qword [rdx+rcx*8]
13488 // mov eax, .tls$:tlsvar
13489 // [rax+rcx] contains the address
13490 // Windows 64bit: gs:0x58
13491 // Windows 32bit: fs:__tls_array
13494 SDValue Chain = DAG.getEntryNode();
13496 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13497 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13498 // use its literal value of 0x2C.
13499 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13500 ? Type::getInt8PtrTy(*DAG.getContext(),
13502 : Type::getInt32PtrTy(*DAG.getContext(),
13506 Subtarget->is64Bit()
13507 ? DAG.getIntPtrConstant(0x58)
13508 : (Subtarget->isTargetWindowsGNU()
13509 ? DAG.getIntPtrConstant(0x2C)
13510 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13512 SDValue ThreadPointer =
13513 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13514 MachinePointerInfo(Ptr), false, false, false, 0);
13516 // Load the _tls_index variable
13517 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13518 if (Subtarget->is64Bit())
13519 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13520 IDX, MachinePointerInfo(), MVT::i32,
13521 false, false, false, 0);
13523 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13524 false, false, false, 0);
13526 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13528 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13530 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13531 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13532 false, false, false, 0);
13534 // Get the offset of start of .tls section
13535 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13536 GA->getValueType(0),
13537 GA->getOffset(), X86II::MO_SECREL);
13538 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13540 // The address of the thread local variable is the add of the thread
13541 // pointer with the offset of the variable.
13542 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13545 llvm_unreachable("TLS not implemented for this target.");
13548 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13549 /// and take a 2 x i32 value to shift plus a shift amount.
13550 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13551 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13552 MVT VT = Op.getSimpleValueType();
13553 unsigned VTBits = VT.getSizeInBits();
13555 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13556 SDValue ShOpLo = Op.getOperand(0);
13557 SDValue ShOpHi = Op.getOperand(1);
13558 SDValue ShAmt = Op.getOperand(2);
13559 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13560 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13562 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13563 DAG.getConstant(VTBits - 1, MVT::i8));
13564 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13565 DAG.getConstant(VTBits - 1, MVT::i8))
13566 : DAG.getConstant(0, VT);
13568 SDValue Tmp2, Tmp3;
13569 if (Op.getOpcode() == ISD::SHL_PARTS) {
13570 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13571 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13573 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13574 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13577 // If the shift amount is larger or equal than the width of a part we can't
13578 // rely on the results of shld/shrd. Insert a test and select the appropriate
13579 // values for large shift amounts.
13580 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13581 DAG.getConstant(VTBits, MVT::i8));
13582 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13583 AndNode, DAG.getConstant(0, MVT::i8));
13586 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13587 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13588 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13590 if (Op.getOpcode() == ISD::SHL_PARTS) {
13591 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13592 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13594 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13595 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13598 SDValue Ops[2] = { Lo, Hi };
13599 return DAG.getMergeValues(Ops, dl);
13602 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13603 SelectionDAG &DAG) const {
13604 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13607 if (SrcVT.isVector()) {
13608 if (SrcVT.getVectorElementType() == MVT::i1) {
13609 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13610 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13611 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13612 Op.getOperand(0)));
13617 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13618 "Unknown SINT_TO_FP to lower!");
13620 // These are really Legal; return the operand so the caller accepts it as
13622 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13624 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13625 Subtarget->is64Bit()) {
13629 unsigned Size = SrcVT.getSizeInBits()/8;
13630 MachineFunction &MF = DAG.getMachineFunction();
13631 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13632 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13633 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13635 MachinePointerInfo::getFixedStack(SSFI),
13637 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13640 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13642 SelectionDAG &DAG) const {
13646 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13648 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13650 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13652 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13654 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13655 MachineMemOperand *MMO;
13657 int SSFI = FI->getIndex();
13659 DAG.getMachineFunction()
13660 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13661 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13663 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13664 StackSlot = StackSlot.getOperand(1);
13666 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13667 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13669 Tys, Ops, SrcVT, MMO);
13672 Chain = Result.getValue(1);
13673 SDValue InFlag = Result.getValue(2);
13675 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13676 // shouldn't be necessary except that RFP cannot be live across
13677 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13678 MachineFunction &MF = DAG.getMachineFunction();
13679 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13680 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13681 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13682 Tys = DAG.getVTList(MVT::Other);
13684 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13686 MachineMemOperand *MMO =
13687 DAG.getMachineFunction()
13688 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13689 MachineMemOperand::MOStore, SSFISize, SSFISize);
13691 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13692 Ops, Op.getValueType(), MMO);
13693 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13694 MachinePointerInfo::getFixedStack(SSFI),
13695 false, false, false, 0);
13701 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13702 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13703 SelectionDAG &DAG) const {
13704 // This algorithm is not obvious. Here it is what we're trying to output:
13707 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13708 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13710 haddpd %xmm0, %xmm0
13712 pshufd $0x4e, %xmm0, %xmm1
13718 LLVMContext *Context = DAG.getContext();
13720 // Build some magic constants.
13721 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13722 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13723 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13725 SmallVector<Constant*,2> CV1;
13727 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13728 APInt(64, 0x4330000000000000ULL))));
13730 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13731 APInt(64, 0x4530000000000000ULL))));
13732 Constant *C1 = ConstantVector::get(CV1);
13733 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13735 // Load the 64-bit value into an XMM register.
13736 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13738 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13739 MachinePointerInfo::getConstantPool(),
13740 false, false, false, 16);
13741 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13742 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13745 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13746 MachinePointerInfo::getConstantPool(),
13747 false, false, false, 16);
13748 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13749 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13752 if (Subtarget->hasSSE3()) {
13753 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13754 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13756 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13757 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13759 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13760 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13764 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13765 DAG.getIntPtrConstant(0));
13768 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13769 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13770 SelectionDAG &DAG) const {
13772 // FP constant to bias correct the final result.
13773 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13776 // Load the 32-bit value into an XMM register.
13777 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13780 // Zero out the upper parts of the register.
13781 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13783 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13784 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13785 DAG.getIntPtrConstant(0));
13787 // Or the load with the bias.
13788 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13789 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13790 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13791 MVT::v2f64, Load)),
13792 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13793 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13794 MVT::v2f64, Bias)));
13795 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13796 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13797 DAG.getIntPtrConstant(0));
13799 // Subtract the bias.
13800 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13802 // Handle final rounding.
13803 EVT DestVT = Op.getValueType();
13805 if (DestVT.bitsLT(MVT::f64))
13806 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13807 DAG.getIntPtrConstant(0));
13808 if (DestVT.bitsGT(MVT::f64))
13809 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13811 // Handle final rounding.
13815 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13816 const X86Subtarget &Subtarget) {
13817 // The algorithm is the following:
13818 // #ifdef __SSE4_1__
13819 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13820 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13821 // (uint4) 0x53000000, 0xaa);
13823 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13824 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13826 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13827 // return (float4) lo + fhi;
13830 SDValue V = Op->getOperand(0);
13831 EVT VecIntVT = V.getValueType();
13832 bool Is128 = VecIntVT == MVT::v4i32;
13833 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13834 // If we convert to something else than the supported type, e.g., to v4f64,
13836 if (VecFloatVT != Op->getValueType(0))
13839 unsigned NumElts = VecIntVT.getVectorNumElements();
13840 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13841 "Unsupported custom type");
13842 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13844 // In the #idef/#else code, we have in common:
13845 // - The vector of constants:
13851 // Create the splat vector for 0x4b000000.
13852 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13853 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13854 CstLow, CstLow, CstLow, CstLow};
13855 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13856 makeArrayRef(&CstLowArray[0], NumElts));
13857 // Create the splat vector for 0x53000000.
13858 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13859 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13860 CstHigh, CstHigh, CstHigh, CstHigh};
13861 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13862 makeArrayRef(&CstHighArray[0], NumElts));
13864 // Create the right shift.
13865 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13866 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13867 CstShift, CstShift, CstShift, CstShift};
13868 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13869 makeArrayRef(&CstShiftArray[0], NumElts));
13870 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13873 if (Subtarget.hasSSE41()) {
13874 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13875 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13876 SDValue VecCstLowBitcast =
13877 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13878 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13879 // Low will be bitcasted right away, so do not bother bitcasting back to its
13881 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13882 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13883 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13884 // (uint4) 0x53000000, 0xaa);
13885 SDValue VecCstHighBitcast =
13886 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13887 SDValue VecShiftBitcast =
13888 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13889 // High will be bitcasted right away, so do not bother bitcasting back to
13890 // its original type.
13891 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13892 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13894 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13895 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13896 CstMask, CstMask, CstMask);
13897 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13898 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13899 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13901 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13902 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13905 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13906 SDValue CstFAdd = DAG.getConstantFP(
13907 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13908 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13909 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13910 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13911 makeArrayRef(&CstFAddArray[0], NumElts));
13913 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13914 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13916 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13917 // return (float4) lo + fhi;
13918 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13919 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13922 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13923 SelectionDAG &DAG) const {
13924 SDValue N0 = Op.getOperand(0);
13925 MVT SVT = N0.getSimpleValueType();
13928 switch (SVT.SimpleTy) {
13930 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13935 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13936 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13937 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13941 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13943 llvm_unreachable(nullptr);
13946 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13947 SelectionDAG &DAG) const {
13948 SDValue N0 = Op.getOperand(0);
13951 if (Op.getValueType().isVector())
13952 return lowerUINT_TO_FP_vec(Op, DAG);
13954 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13955 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13956 // the optimization here.
13957 if (DAG.SignBitIsZero(N0))
13958 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13960 MVT SrcVT = N0.getSimpleValueType();
13961 MVT DstVT = Op.getSimpleValueType();
13962 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13963 return LowerUINT_TO_FP_i64(Op, DAG);
13964 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13965 return LowerUINT_TO_FP_i32(Op, DAG);
13966 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13969 // Make a 64-bit buffer, and use it to build an FILD.
13970 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13971 if (SrcVT == MVT::i32) {
13972 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13973 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13974 getPointerTy(), StackSlot, WordOff);
13975 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13976 StackSlot, MachinePointerInfo(),
13978 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13979 OffsetSlot, MachinePointerInfo(),
13981 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13985 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13986 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13987 StackSlot, MachinePointerInfo(),
13989 // For i64 source, we need to add the appropriate power of 2 if the input
13990 // was negative. This is the same as the optimization in
13991 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13992 // we must be careful to do the computation in x87 extended precision, not
13993 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13994 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13995 MachineMemOperand *MMO =
13996 DAG.getMachineFunction()
13997 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13998 MachineMemOperand::MOLoad, 8, 8);
14000 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
14001 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
14002 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
14005 APInt FF(32, 0x5F800000ULL);
14007 // Check whether the sign bit is set.
14008 SDValue SignSet = DAG.getSetCC(dl,
14009 getSetCCResultType(*DAG.getContext(), MVT::i64),
14010 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14013 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14014 SDValue FudgePtr = DAG.getConstantPool(
14015 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14018 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14019 SDValue Zero = DAG.getIntPtrConstant(0);
14020 SDValue Four = DAG.getIntPtrConstant(4);
14021 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14023 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14025 // Load the value out, extending it from f32 to f80.
14026 // FIXME: Avoid the extend by constructing the right constant pool?
14027 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14028 FudgePtr, MachinePointerInfo::getConstantPool(),
14029 MVT::f32, false, false, false, 4);
14030 // Extend everything to 80 bits to force it to be done on x87.
14031 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14032 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14035 std::pair<SDValue,SDValue>
14036 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14037 bool IsSigned, bool IsReplace) const {
14040 EVT DstTy = Op.getValueType();
14042 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14043 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14047 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14048 DstTy.getSimpleVT() >= MVT::i16 &&
14049 "Unknown FP_TO_INT to lower!");
14051 // These are really Legal.
14052 if (DstTy == MVT::i32 &&
14053 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14054 return std::make_pair(SDValue(), SDValue());
14055 if (Subtarget->is64Bit() &&
14056 DstTy == MVT::i64 &&
14057 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14058 return std::make_pair(SDValue(), SDValue());
14060 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14061 // stack slot, or into the FTOL runtime function.
14062 MachineFunction &MF = DAG.getMachineFunction();
14063 unsigned MemSize = DstTy.getSizeInBits()/8;
14064 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14065 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14068 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14069 Opc = X86ISD::WIN_FTOL;
14071 switch (DstTy.getSimpleVT().SimpleTy) {
14072 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14073 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14074 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14075 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14078 SDValue Chain = DAG.getEntryNode();
14079 SDValue Value = Op.getOperand(0);
14080 EVT TheVT = Op.getOperand(0).getValueType();
14081 // FIXME This causes a redundant load/store if the SSE-class value is already
14082 // in memory, such as if it is on the callstack.
14083 if (isScalarFPTypeInSSEReg(TheVT)) {
14084 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14085 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14086 MachinePointerInfo::getFixedStack(SSFI),
14088 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14090 Chain, StackSlot, DAG.getValueType(TheVT)
14093 MachineMemOperand *MMO =
14094 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14095 MachineMemOperand::MOLoad, MemSize, MemSize);
14096 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14097 Chain = Value.getValue(1);
14098 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14099 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14102 MachineMemOperand *MMO =
14103 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14104 MachineMemOperand::MOStore, MemSize, MemSize);
14106 if (Opc != X86ISD::WIN_FTOL) {
14107 // Build the FP_TO_INT*_IN_MEM
14108 SDValue Ops[] = { Chain, Value, StackSlot };
14109 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14111 return std::make_pair(FIST, StackSlot);
14113 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14114 DAG.getVTList(MVT::Other, MVT::Glue),
14116 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14117 MVT::i32, ftol.getValue(1));
14118 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14119 MVT::i32, eax.getValue(2));
14120 SDValue Ops[] = { eax, edx };
14121 SDValue pair = IsReplace
14122 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14123 : DAG.getMergeValues(Ops, DL);
14124 return std::make_pair(pair, SDValue());
14128 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14129 const X86Subtarget *Subtarget) {
14130 MVT VT = Op->getSimpleValueType(0);
14131 SDValue In = Op->getOperand(0);
14132 MVT InVT = In.getSimpleValueType();
14135 // Optimize vectors in AVX mode:
14138 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14139 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14140 // Concat upper and lower parts.
14143 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14144 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14145 // Concat upper and lower parts.
14148 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14149 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14150 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14153 if (Subtarget->hasInt256())
14154 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14156 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14157 SDValue Undef = DAG.getUNDEF(InVT);
14158 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14159 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14160 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14162 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14163 VT.getVectorNumElements()/2);
14165 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14166 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14168 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14171 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14172 SelectionDAG &DAG) {
14173 MVT VT = Op->getSimpleValueType(0);
14174 SDValue In = Op->getOperand(0);
14175 MVT InVT = In.getSimpleValueType();
14177 unsigned int NumElts = VT.getVectorNumElements();
14178 if (NumElts != 8 && NumElts != 16)
14181 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14182 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14184 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14185 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14186 // Now we have only mask extension
14187 assert(InVT.getVectorElementType() == MVT::i1);
14188 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14189 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14190 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14191 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14192 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14193 MachinePointerInfo::getConstantPool(),
14194 false, false, false, Alignment);
14196 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14197 if (VT.is512BitVector())
14199 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14202 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14203 SelectionDAG &DAG) {
14204 if (Subtarget->hasFp256()) {
14205 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14213 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14214 SelectionDAG &DAG) {
14216 MVT VT = Op.getSimpleValueType();
14217 SDValue In = Op.getOperand(0);
14218 MVT SVT = In.getSimpleValueType();
14220 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14221 return LowerZERO_EXTEND_AVX512(Op, DAG);
14223 if (Subtarget->hasFp256()) {
14224 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14229 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14230 VT.getVectorNumElements() != SVT.getVectorNumElements());
14234 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14236 MVT VT = Op.getSimpleValueType();
14237 SDValue In = Op.getOperand(0);
14238 MVT InVT = In.getSimpleValueType();
14240 if (VT == MVT::i1) {
14241 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14242 "Invalid scalar TRUNCATE operation");
14243 if (InVT.getSizeInBits() >= 32)
14245 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14246 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14248 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14249 "Invalid TRUNCATE operation");
14251 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14252 if (VT.getVectorElementType().getSizeInBits() >=8)
14253 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14255 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14256 unsigned NumElts = InVT.getVectorNumElements();
14257 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14258 if (InVT.getSizeInBits() < 512) {
14259 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14260 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14264 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14265 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14266 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14267 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14268 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14269 MachinePointerInfo::getConstantPool(),
14270 false, false, false, Alignment);
14271 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14272 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14273 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14276 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14277 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14278 if (Subtarget->hasInt256()) {
14279 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14280 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14281 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14283 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14284 DAG.getIntPtrConstant(0));
14287 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14288 DAG.getIntPtrConstant(0));
14289 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14290 DAG.getIntPtrConstant(2));
14291 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14292 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14293 static const int ShufMask[] = {0, 2, 4, 6};
14294 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14297 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14298 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14299 if (Subtarget->hasInt256()) {
14300 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14302 SmallVector<SDValue,32> pshufbMask;
14303 for (unsigned i = 0; i < 2; ++i) {
14304 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14305 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14306 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14307 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14308 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14309 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14310 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14311 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14312 for (unsigned j = 0; j < 8; ++j)
14313 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14315 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14316 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14317 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14319 static const int ShufMask[] = {0, 2, -1, -1};
14320 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14322 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14323 DAG.getIntPtrConstant(0));
14324 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14327 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14328 DAG.getIntPtrConstant(0));
14330 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14331 DAG.getIntPtrConstant(4));
14333 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14334 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14336 // The PSHUFB mask:
14337 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14338 -1, -1, -1, -1, -1, -1, -1, -1};
14340 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14341 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14342 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14344 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14345 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14347 // The MOVLHPS Mask:
14348 static const int ShufMask2[] = {0, 1, 4, 5};
14349 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14350 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14353 // Handle truncation of V256 to V128 using shuffles.
14354 if (!VT.is128BitVector() || !InVT.is256BitVector())
14357 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14359 unsigned NumElems = VT.getVectorNumElements();
14360 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14362 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14363 // Prepare truncation shuffle mask
14364 for (unsigned i = 0; i != NumElems; ++i)
14365 MaskVec[i] = i * 2;
14366 SDValue V = DAG.getVectorShuffle(NVT, DL,
14367 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14368 DAG.getUNDEF(NVT), &MaskVec[0]);
14369 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14370 DAG.getIntPtrConstant(0));
14373 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14374 SelectionDAG &DAG) const {
14375 assert(!Op.getSimpleValueType().isVector());
14377 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14378 /*IsSigned=*/ true, /*IsReplace=*/ false);
14379 SDValue FIST = Vals.first, StackSlot = Vals.second;
14380 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14381 if (!FIST.getNode()) return Op;
14383 if (StackSlot.getNode())
14384 // Load the result.
14385 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14386 FIST, StackSlot, MachinePointerInfo(),
14387 false, false, false, 0);
14389 // The node is the result.
14393 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14394 SelectionDAG &DAG) const {
14395 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14396 /*IsSigned=*/ false, /*IsReplace=*/ false);
14397 SDValue FIST = Vals.first, StackSlot = Vals.second;
14398 assert(FIST.getNode() && "Unexpected failure");
14400 if (StackSlot.getNode())
14401 // Load the result.
14402 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14403 FIST, StackSlot, MachinePointerInfo(),
14404 false, false, false, 0);
14406 // The node is the result.
14410 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14412 MVT VT = Op.getSimpleValueType();
14413 SDValue In = Op.getOperand(0);
14414 MVT SVT = In.getSimpleValueType();
14416 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14418 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14419 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14420 In, DAG.getUNDEF(SVT)));
14423 /// The only differences between FABS and FNEG are the mask and the logic op.
14424 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14425 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14426 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14427 "Wrong opcode for lowering FABS or FNEG.");
14429 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14431 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14432 // into an FNABS. We'll lower the FABS after that if it is still in use.
14434 for (SDNode *User : Op->uses())
14435 if (User->getOpcode() == ISD::FNEG)
14438 SDValue Op0 = Op.getOperand(0);
14439 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14442 MVT VT = Op.getSimpleValueType();
14443 // Assume scalar op for initialization; update for vector if needed.
14444 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14445 // generate a 16-byte vector constant and logic op even for the scalar case.
14446 // Using a 16-byte mask allows folding the load of the mask with
14447 // the logic op, so it can save (~4 bytes) on code size.
14449 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14450 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14451 // decide if we should generate a 16-byte constant mask when we only need 4 or
14452 // 8 bytes for the scalar case.
14453 if (VT.isVector()) {
14454 EltVT = VT.getVectorElementType();
14455 NumElts = VT.getVectorNumElements();
14458 unsigned EltBits = EltVT.getSizeInBits();
14459 LLVMContext *Context = DAG.getContext();
14460 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14462 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14463 Constant *C = ConstantInt::get(*Context, MaskElt);
14464 C = ConstantVector::getSplat(NumElts, C);
14465 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14466 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14467 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14468 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14469 MachinePointerInfo::getConstantPool(),
14470 false, false, false, Alignment);
14472 if (VT.isVector()) {
14473 // For a vector, cast operands to a vector type, perform the logic op,
14474 // and cast the result back to the original value type.
14475 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14476 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14477 SDValue Operand = IsFNABS ?
14478 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14479 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14480 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14481 return DAG.getNode(ISD::BITCAST, dl, VT,
14482 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14485 // If not vector, then scalar.
14486 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14487 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14488 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14491 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14493 LLVMContext *Context = DAG.getContext();
14494 SDValue Op0 = Op.getOperand(0);
14495 SDValue Op1 = Op.getOperand(1);
14497 MVT VT = Op.getSimpleValueType();
14498 MVT SrcVT = Op1.getSimpleValueType();
14500 // If second operand is smaller, extend it first.
14501 if (SrcVT.bitsLT(VT)) {
14502 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14505 // And if it is bigger, shrink it first.
14506 if (SrcVT.bitsGT(VT)) {
14507 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14511 // At this point the operands and the result should have the same
14512 // type, and that won't be f80 since that is not custom lowered.
14514 const fltSemantics &Sem =
14515 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14516 const unsigned SizeInBits = VT.getSizeInBits();
14518 SmallVector<Constant *, 4> CV(
14519 VT == MVT::f64 ? 2 : 4,
14520 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14522 // First, clear all bits but the sign bit from the second operand (sign).
14523 CV[0] = ConstantFP::get(*Context,
14524 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14525 Constant *C = ConstantVector::get(CV);
14526 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14527 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14528 MachinePointerInfo::getConstantPool(),
14529 false, false, false, 16);
14530 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14532 // Next, clear the sign bit from the first operand (magnitude).
14533 // If it's a constant, we can clear it here.
14534 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
14535 APFloat APF = Op0CN->getValueAPF();
14536 // If the magnitude is a positive zero, the sign bit alone is enough.
14537 if (APF.isPosZero())
14540 CV[0] = ConstantFP::get(*Context, APF);
14542 CV[0] = ConstantFP::get(
14544 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14546 C = ConstantVector::get(CV);
14547 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14548 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14549 MachinePointerInfo::getConstantPool(),
14550 false, false, false, 16);
14551 // If the magnitude operand wasn't a constant, we need to AND out the sign.
14552 if (!isa<ConstantFPSDNode>(Op0))
14553 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
14555 // OR the magnitude value with the sign bit.
14556 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14559 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14560 SDValue N0 = Op.getOperand(0);
14562 MVT VT = Op.getSimpleValueType();
14564 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14565 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14566 DAG.getConstant(1, VT));
14567 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14570 // Check whether an OR'd tree is PTEST-able.
14571 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14572 SelectionDAG &DAG) {
14573 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14575 if (!Subtarget->hasSSE41())
14578 if (!Op->hasOneUse())
14581 SDNode *N = Op.getNode();
14584 SmallVector<SDValue, 8> Opnds;
14585 DenseMap<SDValue, unsigned> VecInMap;
14586 SmallVector<SDValue, 8> VecIns;
14587 EVT VT = MVT::Other;
14589 // Recognize a special case where a vector is casted into wide integer to
14591 Opnds.push_back(N->getOperand(0));
14592 Opnds.push_back(N->getOperand(1));
14594 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14595 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14596 // BFS traverse all OR'd operands.
14597 if (I->getOpcode() == ISD::OR) {
14598 Opnds.push_back(I->getOperand(0));
14599 Opnds.push_back(I->getOperand(1));
14600 // Re-evaluate the number of nodes to be traversed.
14601 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14605 // Quit if a non-EXTRACT_VECTOR_ELT
14606 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14609 // Quit if without a constant index.
14610 SDValue Idx = I->getOperand(1);
14611 if (!isa<ConstantSDNode>(Idx))
14614 SDValue ExtractedFromVec = I->getOperand(0);
14615 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14616 if (M == VecInMap.end()) {
14617 VT = ExtractedFromVec.getValueType();
14618 // Quit if not 128/256-bit vector.
14619 if (!VT.is128BitVector() && !VT.is256BitVector())
14621 // Quit if not the same type.
14622 if (VecInMap.begin() != VecInMap.end() &&
14623 VT != VecInMap.begin()->first.getValueType())
14625 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14626 VecIns.push_back(ExtractedFromVec);
14628 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14631 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14632 "Not extracted from 128-/256-bit vector.");
14634 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14636 for (DenseMap<SDValue, unsigned>::const_iterator
14637 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14638 // Quit if not all elements are used.
14639 if (I->second != FullMask)
14643 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14645 // Cast all vectors into TestVT for PTEST.
14646 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14647 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14649 // If more than one full vectors are evaluated, OR them first before PTEST.
14650 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14651 // Each iteration will OR 2 nodes and append the result until there is only
14652 // 1 node left, i.e. the final OR'd value of all vectors.
14653 SDValue LHS = VecIns[Slot];
14654 SDValue RHS = VecIns[Slot + 1];
14655 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14658 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14659 VecIns.back(), VecIns.back());
14662 /// \brief return true if \c Op has a use that doesn't just read flags.
14663 static bool hasNonFlagsUse(SDValue Op) {
14664 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14666 SDNode *User = *UI;
14667 unsigned UOpNo = UI.getOperandNo();
14668 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14669 // Look pass truncate.
14670 UOpNo = User->use_begin().getOperandNo();
14671 User = *User->use_begin();
14674 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14675 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14681 /// Emit nodes that will be selected as "test Op0,Op0", or something
14683 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14684 SelectionDAG &DAG) const {
14685 if (Op.getValueType() == MVT::i1)
14686 // KORTEST instruction should be selected
14687 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14688 DAG.getConstant(0, Op.getValueType()));
14690 // CF and OF aren't always set the way we want. Determine which
14691 // of these we need.
14692 bool NeedCF = false;
14693 bool NeedOF = false;
14696 case X86::COND_A: case X86::COND_AE:
14697 case X86::COND_B: case X86::COND_BE:
14700 case X86::COND_G: case X86::COND_GE:
14701 case X86::COND_L: case X86::COND_LE:
14702 case X86::COND_O: case X86::COND_NO: {
14703 // Check if we really need to set the
14704 // Overflow flag. If NoSignedWrap is present
14705 // that is not actually needed.
14706 switch (Op->getOpcode()) {
14711 const BinaryWithFlagsSDNode *BinNode =
14712 cast<BinaryWithFlagsSDNode>(Op.getNode());
14713 if (BinNode->hasNoSignedWrap())
14723 // See if we can use the EFLAGS value from the operand instead of
14724 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14725 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14726 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14727 // Emit a CMP with 0, which is the TEST pattern.
14728 //if (Op.getValueType() == MVT::i1)
14729 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14730 // DAG.getConstant(0, MVT::i1));
14731 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14732 DAG.getConstant(0, Op.getValueType()));
14734 unsigned Opcode = 0;
14735 unsigned NumOperands = 0;
14737 // Truncate operations may prevent the merge of the SETCC instruction
14738 // and the arithmetic instruction before it. Attempt to truncate the operands
14739 // of the arithmetic instruction and use a reduced bit-width instruction.
14740 bool NeedTruncation = false;
14741 SDValue ArithOp = Op;
14742 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14743 SDValue Arith = Op->getOperand(0);
14744 // Both the trunc and the arithmetic op need to have one user each.
14745 if (Arith->hasOneUse())
14746 switch (Arith.getOpcode()) {
14753 NeedTruncation = true;
14759 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14760 // which may be the result of a CAST. We use the variable 'Op', which is the
14761 // non-casted variable when we check for possible users.
14762 switch (ArithOp.getOpcode()) {
14764 // Due to an isel shortcoming, be conservative if this add is likely to be
14765 // selected as part of a load-modify-store instruction. When the root node
14766 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14767 // uses of other nodes in the match, such as the ADD in this case. This
14768 // leads to the ADD being left around and reselected, with the result being
14769 // two adds in the output. Alas, even if none our users are stores, that
14770 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14771 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14772 // climbing the DAG back to the root, and it doesn't seem to be worth the
14774 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14775 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14776 if (UI->getOpcode() != ISD::CopyToReg &&
14777 UI->getOpcode() != ISD::SETCC &&
14778 UI->getOpcode() != ISD::STORE)
14781 if (ConstantSDNode *C =
14782 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14783 // An add of one will be selected as an INC.
14784 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14785 Opcode = X86ISD::INC;
14790 // An add of negative one (subtract of one) will be selected as a DEC.
14791 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14792 Opcode = X86ISD::DEC;
14798 // Otherwise use a regular EFLAGS-setting add.
14799 Opcode = X86ISD::ADD;
14804 // If we have a constant logical shift that's only used in a comparison
14805 // against zero turn it into an equivalent AND. This allows turning it into
14806 // a TEST instruction later.
14807 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14808 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14809 EVT VT = Op.getValueType();
14810 unsigned BitWidth = VT.getSizeInBits();
14811 unsigned ShAmt = Op->getConstantOperandVal(1);
14812 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14814 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14815 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14816 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14817 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14819 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14820 DAG.getConstant(Mask, VT));
14821 DAG.ReplaceAllUsesWith(Op, New);
14827 // If the primary and result isn't used, don't bother using X86ISD::AND,
14828 // because a TEST instruction will be better.
14829 if (!hasNonFlagsUse(Op))
14835 // Due to the ISEL shortcoming noted above, be conservative if this op is
14836 // likely to be selected as part of a load-modify-store instruction.
14837 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14838 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14839 if (UI->getOpcode() == ISD::STORE)
14842 // Otherwise use a regular EFLAGS-setting instruction.
14843 switch (ArithOp.getOpcode()) {
14844 default: llvm_unreachable("unexpected operator!");
14845 case ISD::SUB: Opcode = X86ISD::SUB; break;
14846 case ISD::XOR: Opcode = X86ISD::XOR; break;
14847 case ISD::AND: Opcode = X86ISD::AND; break;
14849 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14850 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14851 if (EFLAGS.getNode())
14854 Opcode = X86ISD::OR;
14868 return SDValue(Op.getNode(), 1);
14874 // If we found that truncation is beneficial, perform the truncation and
14876 if (NeedTruncation) {
14877 EVT VT = Op.getValueType();
14878 SDValue WideVal = Op->getOperand(0);
14879 EVT WideVT = WideVal.getValueType();
14880 unsigned ConvertedOp = 0;
14881 // Use a target machine opcode to prevent further DAGCombine
14882 // optimizations that may separate the arithmetic operations
14883 // from the setcc node.
14884 switch (WideVal.getOpcode()) {
14886 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14887 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14888 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14889 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14890 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14894 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14895 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14896 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14897 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14898 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14904 // Emit a CMP with 0, which is the TEST pattern.
14905 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14906 DAG.getConstant(0, Op.getValueType()));
14908 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14909 SmallVector<SDValue, 4> Ops;
14910 for (unsigned i = 0; i != NumOperands; ++i)
14911 Ops.push_back(Op.getOperand(i));
14913 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14914 DAG.ReplaceAllUsesWith(Op, New);
14915 return SDValue(New.getNode(), 1);
14918 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14920 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14921 SDLoc dl, SelectionDAG &DAG) const {
14922 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14923 if (C->getAPIntValue() == 0)
14924 return EmitTest(Op0, X86CC, dl, DAG);
14926 if (Op0.getValueType() == MVT::i1)
14927 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14930 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14931 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14932 // Do the comparison at i32 if it's smaller, besides the Atom case.
14933 // This avoids subregister aliasing issues. Keep the smaller reference
14934 // if we're optimizing for size, however, as that'll allow better folding
14935 // of memory operations.
14936 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14937 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14938 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14939 !Subtarget->isAtom()) {
14940 unsigned ExtendOp =
14941 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14942 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14943 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14945 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14946 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14947 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14949 return SDValue(Sub.getNode(), 1);
14951 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14954 /// Convert a comparison if required by the subtarget.
14955 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14956 SelectionDAG &DAG) const {
14957 // If the subtarget does not support the FUCOMI instruction, floating-point
14958 // comparisons have to be converted.
14959 if (Subtarget->hasCMov() ||
14960 Cmp.getOpcode() != X86ISD::CMP ||
14961 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14962 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14965 // The instruction selector will select an FUCOM instruction instead of
14966 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14967 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14968 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14970 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14971 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14972 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14973 DAG.getConstant(8, MVT::i8));
14974 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14975 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14978 /// The minimum architected relative accuracy is 2^-12. We need one
14979 /// Newton-Raphson step to have a good float result (24 bits of precision).
14980 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14981 DAGCombinerInfo &DCI,
14982 unsigned &RefinementSteps,
14983 bool &UseOneConstNR) const {
14984 // FIXME: We should use instruction latency models to calculate the cost of
14985 // each potential sequence, but this is very hard to do reliably because
14986 // at least Intel's Core* chips have variable timing based on the number of
14987 // significant digits in the divisor and/or sqrt operand.
14988 if (!Subtarget->useSqrtEst())
14991 EVT VT = Op.getValueType();
14993 // SSE1 has rsqrtss and rsqrtps.
14994 // TODO: Add support for AVX512 (v16f32).
14995 // It is likely not profitable to do this for f64 because a double-precision
14996 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14997 // instructions: convert to single, rsqrtss, convert back to double, refine
14998 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14999 // along with FMA, this could be a throughput win.
15000 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15001 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15002 RefinementSteps = 1;
15003 UseOneConstNR = false;
15004 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
15009 /// The minimum architected relative accuracy is 2^-12. We need one
15010 /// Newton-Raphson step to have a good float result (24 bits of precision).
15011 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
15012 DAGCombinerInfo &DCI,
15013 unsigned &RefinementSteps) const {
15014 // FIXME: We should use instruction latency models to calculate the cost of
15015 // each potential sequence, but this is very hard to do reliably because
15016 // at least Intel's Core* chips have variable timing based on the number of
15017 // significant digits in the divisor.
15018 if (!Subtarget->useReciprocalEst())
15021 EVT VT = Op.getValueType();
15023 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15024 // TODO: Add support for AVX512 (v16f32).
15025 // It is likely not profitable to do this for f64 because a double-precision
15026 // reciprocal estimate with refinement on x86 prior to FMA requires
15027 // 15 instructions: convert to single, rcpss, convert back to double, refine
15028 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15029 // along with FMA, this could be a throughput win.
15030 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15031 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15032 RefinementSteps = ReciprocalEstimateRefinementSteps;
15033 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15038 static bool isAllOnes(SDValue V) {
15039 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15040 return C && C->isAllOnesValue();
15043 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15044 /// if it's possible.
15045 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15046 SDLoc dl, SelectionDAG &DAG) const {
15047 SDValue Op0 = And.getOperand(0);
15048 SDValue Op1 = And.getOperand(1);
15049 if (Op0.getOpcode() == ISD::TRUNCATE)
15050 Op0 = Op0.getOperand(0);
15051 if (Op1.getOpcode() == ISD::TRUNCATE)
15052 Op1 = Op1.getOperand(0);
15055 if (Op1.getOpcode() == ISD::SHL)
15056 std::swap(Op0, Op1);
15057 if (Op0.getOpcode() == ISD::SHL) {
15058 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15059 if (And00C->getZExtValue() == 1) {
15060 // If we looked past a truncate, check that it's only truncating away
15062 unsigned BitWidth = Op0.getValueSizeInBits();
15063 unsigned AndBitWidth = And.getValueSizeInBits();
15064 if (BitWidth > AndBitWidth) {
15066 DAG.computeKnownBits(Op0, Zeros, Ones);
15067 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15071 RHS = Op0.getOperand(1);
15073 } else if (Op1.getOpcode() == ISD::Constant) {
15074 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15075 uint64_t AndRHSVal = AndRHS->getZExtValue();
15076 SDValue AndLHS = Op0;
15078 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15079 LHS = AndLHS.getOperand(0);
15080 RHS = AndLHS.getOperand(1);
15083 // Use BT if the immediate can't be encoded in a TEST instruction.
15084 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15086 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15090 if (LHS.getNode()) {
15091 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15092 // instruction. Since the shift amount is in-range-or-undefined, we know
15093 // that doing a bittest on the i32 value is ok. We extend to i32 because
15094 // the encoding for the i16 version is larger than the i32 version.
15095 // Also promote i16 to i32 for performance / code size reason.
15096 if (LHS.getValueType() == MVT::i8 ||
15097 LHS.getValueType() == MVT::i16)
15098 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15100 // If the operand types disagree, extend the shift amount to match. Since
15101 // BT ignores high bits (like shifts) we can use anyextend.
15102 if (LHS.getValueType() != RHS.getValueType())
15103 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15105 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15106 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15107 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15108 DAG.getConstant(Cond, MVT::i8), BT);
15114 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15116 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15121 // SSE Condition code mapping:
15130 switch (SetCCOpcode) {
15131 default: llvm_unreachable("Unexpected SETCC condition");
15133 case ISD::SETEQ: SSECC = 0; break;
15135 case ISD::SETGT: Swap = true; // Fallthrough
15137 case ISD::SETOLT: SSECC = 1; break;
15139 case ISD::SETGE: Swap = true; // Fallthrough
15141 case ISD::SETOLE: SSECC = 2; break;
15142 case ISD::SETUO: SSECC = 3; break;
15144 case ISD::SETNE: SSECC = 4; break;
15145 case ISD::SETULE: Swap = true; // Fallthrough
15146 case ISD::SETUGE: SSECC = 5; break;
15147 case ISD::SETULT: Swap = true; // Fallthrough
15148 case ISD::SETUGT: SSECC = 6; break;
15149 case ISD::SETO: SSECC = 7; break;
15151 case ISD::SETONE: SSECC = 8; break;
15154 std::swap(Op0, Op1);
15159 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15160 // ones, and then concatenate the result back.
15161 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15162 MVT VT = Op.getSimpleValueType();
15164 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15165 "Unsupported value type for operation");
15167 unsigned NumElems = VT.getVectorNumElements();
15169 SDValue CC = Op.getOperand(2);
15171 // Extract the LHS vectors
15172 SDValue LHS = Op.getOperand(0);
15173 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15174 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15176 // Extract the RHS vectors
15177 SDValue RHS = Op.getOperand(1);
15178 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15179 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15181 // Issue the operation on the smaller types and concatenate the result back
15182 MVT EltVT = VT.getVectorElementType();
15183 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15184 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15185 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15186 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15189 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15190 const X86Subtarget *Subtarget) {
15191 SDValue Op0 = Op.getOperand(0);
15192 SDValue Op1 = Op.getOperand(1);
15193 SDValue CC = Op.getOperand(2);
15194 MVT VT = Op.getSimpleValueType();
15197 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15198 Op.getValueType().getScalarType() == MVT::i1 &&
15199 "Cannot set masked compare for this operation");
15201 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15203 bool Unsigned = false;
15206 switch (SetCCOpcode) {
15207 default: llvm_unreachable("Unexpected SETCC condition");
15208 case ISD::SETNE: SSECC = 4; break;
15209 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15210 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15211 case ISD::SETLT: Swap = true; //fall-through
15212 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15213 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15214 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15215 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15216 case ISD::SETULE: Unsigned = true; //fall-through
15217 case ISD::SETLE: SSECC = 2; break;
15221 std::swap(Op0, Op1);
15223 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15224 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15225 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15226 DAG.getConstant(SSECC, MVT::i8));
15229 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15230 /// operand \p Op1. If non-trivial (for example because it's not constant)
15231 /// return an empty value.
15232 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15234 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15238 MVT VT = Op1.getSimpleValueType();
15239 MVT EVT = VT.getVectorElementType();
15240 unsigned n = VT.getVectorNumElements();
15241 SmallVector<SDValue, 8> ULTOp1;
15243 for (unsigned i = 0; i < n; ++i) {
15244 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15245 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15248 // Avoid underflow.
15249 APInt Val = Elt->getAPIntValue();
15253 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15256 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15259 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15260 SelectionDAG &DAG) {
15261 SDValue Op0 = Op.getOperand(0);
15262 SDValue Op1 = Op.getOperand(1);
15263 SDValue CC = Op.getOperand(2);
15264 MVT VT = Op.getSimpleValueType();
15265 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15266 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15271 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15272 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15275 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15276 unsigned Opc = X86ISD::CMPP;
15277 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15278 assert(VT.getVectorNumElements() <= 16);
15279 Opc = X86ISD::CMPM;
15281 // In the two special cases we can't handle, emit two comparisons.
15284 unsigned CombineOpc;
15285 if (SetCCOpcode == ISD::SETUEQ) {
15286 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15288 assert(SetCCOpcode == ISD::SETONE);
15289 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15292 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15293 DAG.getConstant(CC0, MVT::i8));
15294 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15295 DAG.getConstant(CC1, MVT::i8));
15296 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15298 // Handle all other FP comparisons here.
15299 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15300 DAG.getConstant(SSECC, MVT::i8));
15303 // Break 256-bit integer vector compare into smaller ones.
15304 if (VT.is256BitVector() && !Subtarget->hasInt256())
15305 return Lower256IntVSETCC(Op, DAG);
15307 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15308 EVT OpVT = Op1.getValueType();
15309 if (Subtarget->hasAVX512()) {
15310 if (Op1.getValueType().is512BitVector() ||
15311 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15312 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15313 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15315 // In AVX-512 architecture setcc returns mask with i1 elements,
15316 // But there is no compare instruction for i8 and i16 elements in KNL.
15317 // We are not talking about 512-bit operands in this case, these
15318 // types are illegal.
15320 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15321 OpVT.getVectorElementType().getSizeInBits() >= 8))
15322 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15323 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15326 // We are handling one of the integer comparisons here. Since SSE only has
15327 // GT and EQ comparisons for integer, swapping operands and multiple
15328 // operations may be required for some comparisons.
15330 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15331 bool Subus = false;
15333 switch (SetCCOpcode) {
15334 default: llvm_unreachable("Unexpected SETCC condition");
15335 case ISD::SETNE: Invert = true;
15336 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15337 case ISD::SETLT: Swap = true;
15338 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15339 case ISD::SETGE: Swap = true;
15340 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15341 Invert = true; break;
15342 case ISD::SETULT: Swap = true;
15343 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15344 FlipSigns = true; break;
15345 case ISD::SETUGE: Swap = true;
15346 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15347 FlipSigns = true; Invert = true; break;
15350 // Special case: Use min/max operations for SETULE/SETUGE
15351 MVT VET = VT.getVectorElementType();
15353 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15354 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15357 switch (SetCCOpcode) {
15359 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15360 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15363 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15366 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15367 if (!MinMax && hasSubus) {
15368 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15370 // t = psubus Op0, Op1
15371 // pcmpeq t, <0..0>
15372 switch (SetCCOpcode) {
15374 case ISD::SETULT: {
15375 // If the comparison is against a constant we can turn this into a
15376 // setule. With psubus, setule does not require a swap. This is
15377 // beneficial because the constant in the register is no longer
15378 // destructed as the destination so it can be hoisted out of a loop.
15379 // Only do this pre-AVX since vpcmp* is no longer destructive.
15380 if (Subtarget->hasAVX())
15382 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15383 if (ULEOp1.getNode()) {
15385 Subus = true; Invert = false; Swap = false;
15389 // Psubus is better than flip-sign because it requires no inversion.
15390 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15391 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15395 Opc = X86ISD::SUBUS;
15401 std::swap(Op0, Op1);
15403 // Check that the operation in question is available (most are plain SSE2,
15404 // but PCMPGTQ and PCMPEQQ have different requirements).
15405 if (VT == MVT::v2i64) {
15406 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15407 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15409 // First cast everything to the right type.
15410 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15411 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15413 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15414 // bits of the inputs before performing those operations. The lower
15415 // compare is always unsigned.
15418 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15420 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15421 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15422 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15423 Sign, Zero, Sign, Zero);
15425 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15426 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15428 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15429 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15430 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15432 // Create masks for only the low parts/high parts of the 64 bit integers.
15433 static const int MaskHi[] = { 1, 1, 3, 3 };
15434 static const int MaskLo[] = { 0, 0, 2, 2 };
15435 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15436 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15437 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15439 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15440 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15443 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15445 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15448 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15449 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15450 // pcmpeqd + pshufd + pand.
15451 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15453 // First cast everything to the right type.
15454 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15455 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15458 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15460 // Make sure the lower and upper halves are both all-ones.
15461 static const int Mask[] = { 1, 0, 3, 2 };
15462 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15463 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15466 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15468 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15472 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15473 // bits of the inputs before performing those operations.
15475 EVT EltVT = VT.getVectorElementType();
15476 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15477 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15478 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15481 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15483 // If the logical-not of the result is required, perform that now.
15485 Result = DAG.getNOT(dl, Result, VT);
15488 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15491 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15492 getZeroVector(VT, Subtarget, DAG, dl));
15497 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15499 MVT VT = Op.getSimpleValueType();
15501 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15503 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15504 && "SetCC type must be 8-bit or 1-bit integer");
15505 SDValue Op0 = Op.getOperand(0);
15506 SDValue Op1 = Op.getOperand(1);
15508 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15510 // Optimize to BT if possible.
15511 // Lower (X & (1 << N)) == 0 to BT(X, N).
15512 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15513 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15514 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15515 Op1.getOpcode() == ISD::Constant &&
15516 cast<ConstantSDNode>(Op1)->isNullValue() &&
15517 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15518 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15519 if (NewSetCC.getNode()) {
15521 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15526 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15528 if (Op1.getOpcode() == ISD::Constant &&
15529 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15530 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15531 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15533 // If the input is a setcc, then reuse the input setcc or use a new one with
15534 // the inverted condition.
15535 if (Op0.getOpcode() == X86ISD::SETCC) {
15536 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15537 bool Invert = (CC == ISD::SETNE) ^
15538 cast<ConstantSDNode>(Op1)->isNullValue();
15542 CCode = X86::GetOppositeBranchCondition(CCode);
15543 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15544 DAG.getConstant(CCode, MVT::i8),
15545 Op0.getOperand(1));
15547 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15551 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15552 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15553 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15555 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15556 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15559 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15560 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15561 if (X86CC == X86::COND_INVALID)
15564 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15565 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15566 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15567 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15569 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15573 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15574 static bool isX86LogicalCmp(SDValue Op) {
15575 unsigned Opc = Op.getNode()->getOpcode();
15576 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15577 Opc == X86ISD::SAHF)
15579 if (Op.getResNo() == 1 &&
15580 (Opc == X86ISD::ADD ||
15581 Opc == X86ISD::SUB ||
15582 Opc == X86ISD::ADC ||
15583 Opc == X86ISD::SBB ||
15584 Opc == X86ISD::SMUL ||
15585 Opc == X86ISD::UMUL ||
15586 Opc == X86ISD::INC ||
15587 Opc == X86ISD::DEC ||
15588 Opc == X86ISD::OR ||
15589 Opc == X86ISD::XOR ||
15590 Opc == X86ISD::AND))
15593 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15599 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15600 if (V.getOpcode() != ISD::TRUNCATE)
15603 SDValue VOp0 = V.getOperand(0);
15604 unsigned InBits = VOp0.getValueSizeInBits();
15605 unsigned Bits = V.getValueSizeInBits();
15606 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15609 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15610 bool addTest = true;
15611 SDValue Cond = Op.getOperand(0);
15612 SDValue Op1 = Op.getOperand(1);
15613 SDValue Op2 = Op.getOperand(2);
15615 EVT VT = Op1.getValueType();
15618 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15619 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15620 // sequence later on.
15621 if (Cond.getOpcode() == ISD::SETCC &&
15622 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15623 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15624 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15625 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15626 int SSECC = translateX86FSETCC(
15627 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15630 if (Subtarget->hasAVX512()) {
15631 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15632 DAG.getConstant(SSECC, MVT::i8));
15633 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15635 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15636 DAG.getConstant(SSECC, MVT::i8));
15637 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15638 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15639 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15643 if (Cond.getOpcode() == ISD::SETCC) {
15644 SDValue NewCond = LowerSETCC(Cond, DAG);
15645 if (NewCond.getNode())
15649 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15650 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15651 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15652 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15653 if (Cond.getOpcode() == X86ISD::SETCC &&
15654 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15655 isZero(Cond.getOperand(1).getOperand(1))) {
15656 SDValue Cmp = Cond.getOperand(1);
15658 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15660 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15661 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15662 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15664 SDValue CmpOp0 = Cmp.getOperand(0);
15665 // Apply further optimizations for special cases
15666 // (select (x != 0), -1, 0) -> neg & sbb
15667 // (select (x == 0), 0, -1) -> neg & sbb
15668 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15669 if (YC->isNullValue() &&
15670 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15671 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15672 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15673 DAG.getConstant(0, CmpOp0.getValueType()),
15675 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15676 DAG.getConstant(X86::COND_B, MVT::i8),
15677 SDValue(Neg.getNode(), 1));
15681 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15682 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15683 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15685 SDValue Res = // Res = 0 or -1.
15686 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15687 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15689 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15690 Res = DAG.getNOT(DL, Res, Res.getValueType());
15692 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15693 if (!N2C || !N2C->isNullValue())
15694 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15699 // Look past (and (setcc_carry (cmp ...)), 1).
15700 if (Cond.getOpcode() == ISD::AND &&
15701 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15702 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15703 if (C && C->getAPIntValue() == 1)
15704 Cond = Cond.getOperand(0);
15707 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15708 // setting operand in place of the X86ISD::SETCC.
15709 unsigned CondOpcode = Cond.getOpcode();
15710 if (CondOpcode == X86ISD::SETCC ||
15711 CondOpcode == X86ISD::SETCC_CARRY) {
15712 CC = Cond.getOperand(0);
15714 SDValue Cmp = Cond.getOperand(1);
15715 unsigned Opc = Cmp.getOpcode();
15716 MVT VT = Op.getSimpleValueType();
15718 bool IllegalFPCMov = false;
15719 if (VT.isFloatingPoint() && !VT.isVector() &&
15720 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15721 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15723 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15724 Opc == X86ISD::BT) { // FIXME
15728 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15729 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15730 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15731 Cond.getOperand(0).getValueType() != MVT::i8)) {
15732 SDValue LHS = Cond.getOperand(0);
15733 SDValue RHS = Cond.getOperand(1);
15734 unsigned X86Opcode;
15737 switch (CondOpcode) {
15738 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15739 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15740 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15741 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15742 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15743 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15744 default: llvm_unreachable("unexpected overflowing operator");
15746 if (CondOpcode == ISD::UMULO)
15747 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15750 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15752 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15754 if (CondOpcode == ISD::UMULO)
15755 Cond = X86Op.getValue(2);
15757 Cond = X86Op.getValue(1);
15759 CC = DAG.getConstant(X86Cond, MVT::i8);
15764 // Look pass the truncate if the high bits are known zero.
15765 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15766 Cond = Cond.getOperand(0);
15768 // We know the result of AND is compared against zero. Try to match
15770 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15771 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15772 if (NewSetCC.getNode()) {
15773 CC = NewSetCC.getOperand(0);
15774 Cond = NewSetCC.getOperand(1);
15781 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15782 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15785 // a < b ? -1 : 0 -> RES = ~setcc_carry
15786 // a < b ? 0 : -1 -> RES = setcc_carry
15787 // a >= b ? -1 : 0 -> RES = setcc_carry
15788 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15789 if (Cond.getOpcode() == X86ISD::SUB) {
15790 Cond = ConvertCmpIfNecessary(Cond, DAG);
15791 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15793 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15794 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15795 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15796 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15797 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15798 return DAG.getNOT(DL, Res, Res.getValueType());
15803 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15804 // widen the cmov and push the truncate through. This avoids introducing a new
15805 // branch during isel and doesn't add any extensions.
15806 if (Op.getValueType() == MVT::i8 &&
15807 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15808 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15809 if (T1.getValueType() == T2.getValueType() &&
15810 // Blacklist CopyFromReg to avoid partial register stalls.
15811 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15812 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15813 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15814 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15818 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15819 // condition is true.
15820 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15821 SDValue Ops[] = { Op2, Op1, CC, Cond };
15822 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15825 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15826 SelectionDAG &DAG) {
15827 MVT VT = Op->getSimpleValueType(0);
15828 SDValue In = Op->getOperand(0);
15829 MVT InVT = In.getSimpleValueType();
15830 MVT VTElt = VT.getVectorElementType();
15831 MVT InVTElt = InVT.getVectorElementType();
15835 if ((InVTElt == MVT::i1) &&
15836 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15837 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15839 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15840 VTElt.getSizeInBits() <= 16)) ||
15842 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15843 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15845 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15846 VTElt.getSizeInBits() >= 32))))
15847 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15849 unsigned int NumElts = VT.getVectorNumElements();
15851 if (NumElts != 8 && NumElts != 16)
15854 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15855 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15856 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15857 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15861 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15863 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15864 Constant *C = ConstantInt::get(*DAG.getContext(),
15865 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15867 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15868 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15869 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15870 MachinePointerInfo::getConstantPool(),
15871 false, false, false, Alignment);
15872 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15873 if (VT.is512BitVector())
15875 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15878 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15879 SelectionDAG &DAG) {
15880 MVT VT = Op->getSimpleValueType(0);
15881 SDValue In = Op->getOperand(0);
15882 MVT InVT = In.getSimpleValueType();
15885 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15886 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15888 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15889 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15890 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15893 if (Subtarget->hasInt256())
15894 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15896 // Optimize vectors in AVX mode
15897 // Sign extend v8i16 to v8i32 and
15900 // Divide input vector into two parts
15901 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15902 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15903 // concat the vectors to original VT
15905 unsigned NumElems = InVT.getVectorNumElements();
15906 SDValue Undef = DAG.getUNDEF(InVT);
15908 SmallVector<int,8> ShufMask1(NumElems, -1);
15909 for (unsigned i = 0; i != NumElems/2; ++i)
15912 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15914 SmallVector<int,8> ShufMask2(NumElems, -1);
15915 for (unsigned i = 0; i != NumElems/2; ++i)
15916 ShufMask2[i] = i + NumElems/2;
15918 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15920 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15921 VT.getVectorNumElements()/2);
15923 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15924 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15926 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15929 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15930 // may emit an illegal shuffle but the expansion is still better than scalar
15931 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15932 // we'll emit a shuffle and a arithmetic shift.
15933 // TODO: It is possible to support ZExt by zeroing the undef values during
15934 // the shuffle phase or after the shuffle.
15935 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15936 SelectionDAG &DAG) {
15937 MVT RegVT = Op.getSimpleValueType();
15938 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15939 assert(RegVT.isInteger() &&
15940 "We only custom lower integer vector sext loads.");
15942 // Nothing useful we can do without SSE2 shuffles.
15943 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15945 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15947 EVT MemVT = Ld->getMemoryVT();
15948 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15949 unsigned RegSz = RegVT.getSizeInBits();
15951 ISD::LoadExtType Ext = Ld->getExtensionType();
15953 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15954 && "Only anyext and sext are currently implemented.");
15955 assert(MemVT != RegVT && "Cannot extend to the same type");
15956 assert(MemVT.isVector() && "Must load a vector from memory");
15958 unsigned NumElems = RegVT.getVectorNumElements();
15959 unsigned MemSz = MemVT.getSizeInBits();
15960 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15962 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15963 // The only way in which we have a legal 256-bit vector result but not the
15964 // integer 256-bit operations needed to directly lower a sextload is if we
15965 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15966 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15967 // correctly legalized. We do this late to allow the canonical form of
15968 // sextload to persist throughout the rest of the DAG combiner -- it wants
15969 // to fold together any extensions it can, and so will fuse a sign_extend
15970 // of an sextload into a sextload targeting a wider value.
15972 if (MemSz == 128) {
15973 // Just switch this to a normal load.
15974 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15975 "it must be a legal 128-bit vector "
15977 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15978 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15979 Ld->isInvariant(), Ld->getAlignment());
15981 assert(MemSz < 128 &&
15982 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15983 // Do an sext load to a 128-bit vector type. We want to use the same
15984 // number of elements, but elements half as wide. This will end up being
15985 // recursively lowered by this routine, but will succeed as we definitely
15986 // have all the necessary features if we're using AVX1.
15988 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15989 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15991 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15992 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15993 Ld->isNonTemporal(), Ld->isInvariant(),
15994 Ld->getAlignment());
15997 // Replace chain users with the new chain.
15998 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15999 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
16001 // Finally, do a normal sign-extend to the desired register.
16002 return DAG.getSExtOrTrunc(Load, dl, RegVT);
16005 // All sizes must be a power of two.
16006 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
16007 "Non-power-of-two elements are not custom lowered!");
16009 // Attempt to load the original value using scalar loads.
16010 // Find the largest scalar type that divides the total loaded size.
16011 MVT SclrLoadTy = MVT::i8;
16012 for (MVT Tp : MVT::integer_valuetypes()) {
16013 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16018 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16019 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16021 SclrLoadTy = MVT::f64;
16023 // Calculate the number of scalar loads that we need to perform
16024 // in order to load our vector from memory.
16025 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16027 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16028 "Can only lower sext loads with a single scalar load!");
16030 unsigned loadRegZize = RegSz;
16031 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16034 // Represent our vector as a sequence of elements which are the
16035 // largest scalar that we can load.
16036 EVT LoadUnitVecVT = EVT::getVectorVT(
16037 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16039 // Represent the data using the same element type that is stored in
16040 // memory. In practice, we ''widen'' MemVT.
16042 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16043 loadRegZize / MemVT.getScalarType().getSizeInBits());
16045 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16046 "Invalid vector type");
16048 // We can't shuffle using an illegal type.
16049 assert(TLI.isTypeLegal(WideVecVT) &&
16050 "We only lower types that form legal widened vector types");
16052 SmallVector<SDValue, 8> Chains;
16053 SDValue Ptr = Ld->getBasePtr();
16054 SDValue Increment =
16055 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16056 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16058 for (unsigned i = 0; i < NumLoads; ++i) {
16059 // Perform a single load.
16060 SDValue ScalarLoad =
16061 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16062 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16063 Ld->getAlignment());
16064 Chains.push_back(ScalarLoad.getValue(1));
16065 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16066 // another round of DAGCombining.
16068 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16070 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16071 ScalarLoad, DAG.getIntPtrConstant(i));
16073 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16076 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16078 // Bitcast the loaded value to a vector of the original element type, in
16079 // the size of the target vector type.
16080 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16081 unsigned SizeRatio = RegSz / MemSz;
16083 if (Ext == ISD::SEXTLOAD) {
16084 // If we have SSE4.1, we can directly emit a VSEXT node.
16085 if (Subtarget->hasSSE41()) {
16086 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16087 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16091 // Otherwise we'll shuffle the small elements in the high bits of the
16092 // larger type and perform an arithmetic shift. If the shift is not legal
16093 // it's better to scalarize.
16094 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16095 "We can't implement a sext load without an arithmetic right shift!");
16097 // Redistribute the loaded elements into the different locations.
16098 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16099 for (unsigned i = 0; i != NumElems; ++i)
16100 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16102 SDValue Shuff = DAG.getVectorShuffle(
16103 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16105 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16107 // Build the arithmetic shift.
16108 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16109 MemVT.getVectorElementType().getSizeInBits();
16111 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16113 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16117 // Redistribute the loaded elements into the different locations.
16118 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16119 for (unsigned i = 0; i != NumElems; ++i)
16120 ShuffleVec[i * SizeRatio] = i;
16122 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16123 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16125 // Bitcast to the requested type.
16126 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16127 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16131 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16132 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16133 // from the AND / OR.
16134 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16135 Opc = Op.getOpcode();
16136 if (Opc != ISD::OR && Opc != ISD::AND)
16138 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16139 Op.getOperand(0).hasOneUse() &&
16140 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16141 Op.getOperand(1).hasOneUse());
16144 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16145 // 1 and that the SETCC node has a single use.
16146 static bool isXor1OfSetCC(SDValue Op) {
16147 if (Op.getOpcode() != ISD::XOR)
16149 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16150 if (N1C && N1C->getAPIntValue() == 1) {
16151 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16152 Op.getOperand(0).hasOneUse();
16157 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16158 bool addTest = true;
16159 SDValue Chain = Op.getOperand(0);
16160 SDValue Cond = Op.getOperand(1);
16161 SDValue Dest = Op.getOperand(2);
16164 bool Inverted = false;
16166 if (Cond.getOpcode() == ISD::SETCC) {
16167 // Check for setcc([su]{add,sub,mul}o == 0).
16168 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16169 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16170 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16171 Cond.getOperand(0).getResNo() == 1 &&
16172 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16173 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16174 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16175 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16176 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16177 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16179 Cond = Cond.getOperand(0);
16181 SDValue NewCond = LowerSETCC(Cond, DAG);
16182 if (NewCond.getNode())
16187 // FIXME: LowerXALUO doesn't handle these!!
16188 else if (Cond.getOpcode() == X86ISD::ADD ||
16189 Cond.getOpcode() == X86ISD::SUB ||
16190 Cond.getOpcode() == X86ISD::SMUL ||
16191 Cond.getOpcode() == X86ISD::UMUL)
16192 Cond = LowerXALUO(Cond, DAG);
16195 // Look pass (and (setcc_carry (cmp ...)), 1).
16196 if (Cond.getOpcode() == ISD::AND &&
16197 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16198 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16199 if (C && C->getAPIntValue() == 1)
16200 Cond = Cond.getOperand(0);
16203 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16204 // setting operand in place of the X86ISD::SETCC.
16205 unsigned CondOpcode = Cond.getOpcode();
16206 if (CondOpcode == X86ISD::SETCC ||
16207 CondOpcode == X86ISD::SETCC_CARRY) {
16208 CC = Cond.getOperand(0);
16210 SDValue Cmp = Cond.getOperand(1);
16211 unsigned Opc = Cmp.getOpcode();
16212 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16213 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16217 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16221 // These can only come from an arithmetic instruction with overflow,
16222 // e.g. SADDO, UADDO.
16223 Cond = Cond.getNode()->getOperand(1);
16229 CondOpcode = Cond.getOpcode();
16230 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16231 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16232 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16233 Cond.getOperand(0).getValueType() != MVT::i8)) {
16234 SDValue LHS = Cond.getOperand(0);
16235 SDValue RHS = Cond.getOperand(1);
16236 unsigned X86Opcode;
16239 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16240 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16242 switch (CondOpcode) {
16243 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16245 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16247 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16250 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16251 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16255 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16258 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16259 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16260 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16261 default: llvm_unreachable("unexpected overflowing operator");
16264 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16265 if (CondOpcode == ISD::UMULO)
16266 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16269 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16271 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16273 if (CondOpcode == ISD::UMULO)
16274 Cond = X86Op.getValue(2);
16276 Cond = X86Op.getValue(1);
16278 CC = DAG.getConstant(X86Cond, MVT::i8);
16282 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16283 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16284 if (CondOpc == ISD::OR) {
16285 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16286 // two branches instead of an explicit OR instruction with a
16288 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16289 isX86LogicalCmp(Cmp)) {
16290 CC = Cond.getOperand(0).getOperand(0);
16291 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16292 Chain, Dest, CC, Cmp);
16293 CC = Cond.getOperand(1).getOperand(0);
16297 } else { // ISD::AND
16298 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16299 // two branches instead of an explicit AND instruction with a
16300 // separate test. However, we only do this if this block doesn't
16301 // have a fall-through edge, because this requires an explicit
16302 // jmp when the condition is false.
16303 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16304 isX86LogicalCmp(Cmp) &&
16305 Op.getNode()->hasOneUse()) {
16306 X86::CondCode CCode =
16307 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16308 CCode = X86::GetOppositeBranchCondition(CCode);
16309 CC = DAG.getConstant(CCode, MVT::i8);
16310 SDNode *User = *Op.getNode()->use_begin();
16311 // Look for an unconditional branch following this conditional branch.
16312 // We need this because we need to reverse the successors in order
16313 // to implement FCMP_OEQ.
16314 if (User->getOpcode() == ISD::BR) {
16315 SDValue FalseBB = User->getOperand(1);
16317 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16318 assert(NewBR == User);
16322 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16323 Chain, Dest, CC, Cmp);
16324 X86::CondCode CCode =
16325 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16326 CCode = X86::GetOppositeBranchCondition(CCode);
16327 CC = DAG.getConstant(CCode, MVT::i8);
16333 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16334 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16335 // It should be transformed during dag combiner except when the condition
16336 // is set by a arithmetics with overflow node.
16337 X86::CondCode CCode =
16338 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16339 CCode = X86::GetOppositeBranchCondition(CCode);
16340 CC = DAG.getConstant(CCode, MVT::i8);
16341 Cond = Cond.getOperand(0).getOperand(1);
16343 } else if (Cond.getOpcode() == ISD::SETCC &&
16344 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16345 // For FCMP_OEQ, we can emit
16346 // two branches instead of an explicit AND instruction with a
16347 // separate test. However, we only do this if this block doesn't
16348 // have a fall-through edge, because this requires an explicit
16349 // jmp when the condition is false.
16350 if (Op.getNode()->hasOneUse()) {
16351 SDNode *User = *Op.getNode()->use_begin();
16352 // Look for an unconditional branch following this conditional branch.
16353 // We need this because we need to reverse the successors in order
16354 // to implement FCMP_OEQ.
16355 if (User->getOpcode() == ISD::BR) {
16356 SDValue FalseBB = User->getOperand(1);
16358 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16359 assert(NewBR == User);
16363 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16364 Cond.getOperand(0), Cond.getOperand(1));
16365 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16366 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16367 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16368 Chain, Dest, CC, Cmp);
16369 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16374 } else if (Cond.getOpcode() == ISD::SETCC &&
16375 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16376 // For FCMP_UNE, we can emit
16377 // two branches instead of an explicit AND instruction with a
16378 // separate test. However, we only do this if this block doesn't
16379 // have a fall-through edge, because this requires an explicit
16380 // jmp when the condition is false.
16381 if (Op.getNode()->hasOneUse()) {
16382 SDNode *User = *Op.getNode()->use_begin();
16383 // Look for an unconditional branch following this conditional branch.
16384 // We need this because we need to reverse the successors in order
16385 // to implement FCMP_UNE.
16386 if (User->getOpcode() == ISD::BR) {
16387 SDValue FalseBB = User->getOperand(1);
16389 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16390 assert(NewBR == User);
16393 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16394 Cond.getOperand(0), Cond.getOperand(1));
16395 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16396 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16397 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16398 Chain, Dest, CC, Cmp);
16399 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16409 // Look pass the truncate if the high bits are known zero.
16410 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16411 Cond = Cond.getOperand(0);
16413 // We know the result of AND is compared against zero. Try to match
16415 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16416 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16417 if (NewSetCC.getNode()) {
16418 CC = NewSetCC.getOperand(0);
16419 Cond = NewSetCC.getOperand(1);
16426 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16427 CC = DAG.getConstant(X86Cond, MVT::i8);
16428 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16430 Cond = ConvertCmpIfNecessary(Cond, DAG);
16431 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16432 Chain, Dest, CC, Cond);
16435 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16436 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16437 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16438 // that the guard pages used by the OS virtual memory manager are allocated in
16439 // correct sequence.
16441 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16442 SelectionDAG &DAG) const {
16443 MachineFunction &MF = DAG.getMachineFunction();
16444 bool SplitStack = MF.shouldSplitStack();
16445 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16451 SDNode* Node = Op.getNode();
16453 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16454 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16455 " not tell us which reg is the stack pointer!");
16456 EVT VT = Node->getValueType(0);
16457 SDValue Tmp1 = SDValue(Node, 0);
16458 SDValue Tmp2 = SDValue(Node, 1);
16459 SDValue Tmp3 = Node->getOperand(2);
16460 SDValue Chain = Tmp1.getOperand(0);
16462 // Chain the dynamic stack allocation so that it doesn't modify the stack
16463 // pointer when other instructions are using the stack.
16464 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16467 SDValue Size = Tmp2.getOperand(1);
16468 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16469 Chain = SP.getValue(1);
16470 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16471 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16472 unsigned StackAlign = TFI.getStackAlignment();
16473 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16474 if (Align > StackAlign)
16475 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16476 DAG.getConstant(-(uint64_t)Align, VT));
16477 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16479 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16480 DAG.getIntPtrConstant(0, true), SDValue(),
16483 SDValue Ops[2] = { Tmp1, Tmp2 };
16484 return DAG.getMergeValues(Ops, dl);
16488 SDValue Chain = Op.getOperand(0);
16489 SDValue Size = Op.getOperand(1);
16490 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16491 EVT VT = Op.getNode()->getValueType(0);
16493 bool Is64Bit = Subtarget->is64Bit();
16494 EVT SPTy = getPointerTy();
16497 MachineRegisterInfo &MRI = MF.getRegInfo();
16500 // The 64 bit implementation of segmented stacks needs to clobber both r10
16501 // r11. This makes it impossible to use it along with nested parameters.
16502 const Function *F = MF.getFunction();
16504 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16506 if (I->hasNestAttr())
16507 report_fatal_error("Cannot use segmented stacks with functions that "
16508 "have nested arguments.");
16511 const TargetRegisterClass *AddrRegClass =
16512 getRegClassFor(getPointerTy());
16513 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16514 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16515 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16516 DAG.getRegister(Vreg, SPTy));
16517 SDValue Ops1[2] = { Value, Chain };
16518 return DAG.getMergeValues(Ops1, dl);
16521 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16523 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16524 Flag = Chain.getValue(1);
16525 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16527 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16529 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16530 DAG.getSubtarget().getRegisterInfo());
16531 unsigned SPReg = RegInfo->getStackRegister();
16532 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16533 Chain = SP.getValue(1);
16536 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16537 DAG.getConstant(-(uint64_t)Align, VT));
16538 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16541 SDValue Ops1[2] = { SP, Chain };
16542 return DAG.getMergeValues(Ops1, dl);
16546 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16547 MachineFunction &MF = DAG.getMachineFunction();
16548 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16550 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16553 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16554 // vastart just stores the address of the VarArgsFrameIndex slot into the
16555 // memory location argument.
16556 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16558 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16559 MachinePointerInfo(SV), false, false, 0);
16563 // gp_offset (0 - 6 * 8)
16564 // fp_offset (48 - 48 + 8 * 16)
16565 // overflow_arg_area (point to parameters coming in memory).
16567 SmallVector<SDValue, 8> MemOps;
16568 SDValue FIN = Op.getOperand(1);
16570 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16571 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16573 FIN, MachinePointerInfo(SV), false, false, 0);
16574 MemOps.push_back(Store);
16577 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16578 FIN, DAG.getIntPtrConstant(4));
16579 Store = DAG.getStore(Op.getOperand(0), DL,
16580 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16582 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16583 MemOps.push_back(Store);
16585 // Store ptr to overflow_arg_area
16586 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16587 FIN, DAG.getIntPtrConstant(4));
16588 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16590 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16591 MachinePointerInfo(SV, 8),
16593 MemOps.push_back(Store);
16595 // Store ptr to reg_save_area.
16596 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16597 FIN, DAG.getIntPtrConstant(8));
16598 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16600 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16601 MachinePointerInfo(SV, 16), false, false, 0);
16602 MemOps.push_back(Store);
16603 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16606 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16607 assert(Subtarget->is64Bit() &&
16608 "LowerVAARG only handles 64-bit va_arg!");
16609 assert((Subtarget->isTargetLinux() ||
16610 Subtarget->isTargetDarwin()) &&
16611 "Unhandled target in LowerVAARG");
16612 assert(Op.getNode()->getNumOperands() == 4);
16613 SDValue Chain = Op.getOperand(0);
16614 SDValue SrcPtr = Op.getOperand(1);
16615 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16616 unsigned Align = Op.getConstantOperandVal(3);
16619 EVT ArgVT = Op.getNode()->getValueType(0);
16620 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16621 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16624 // Decide which area this value should be read from.
16625 // TODO: Implement the AMD64 ABI in its entirety. This simple
16626 // selection mechanism works only for the basic types.
16627 if (ArgVT == MVT::f80) {
16628 llvm_unreachable("va_arg for f80 not yet implemented");
16629 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16630 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16631 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16632 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16634 llvm_unreachable("Unhandled argument type in LowerVAARG");
16637 if (ArgMode == 2) {
16638 // Sanity Check: Make sure using fp_offset makes sense.
16639 assert(!DAG.getTarget().Options.UseSoftFloat &&
16640 !(DAG.getMachineFunction()
16641 .getFunction()->getAttributes()
16642 .hasAttribute(AttributeSet::FunctionIndex,
16643 Attribute::NoImplicitFloat)) &&
16644 Subtarget->hasSSE1());
16647 // Insert VAARG_64 node into the DAG
16648 // VAARG_64 returns two values: Variable Argument Address, Chain
16649 SmallVector<SDValue, 11> InstOps;
16650 InstOps.push_back(Chain);
16651 InstOps.push_back(SrcPtr);
16652 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16653 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16654 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16655 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16656 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16657 VTs, InstOps, MVT::i64,
16658 MachinePointerInfo(SV),
16660 /*Volatile=*/false,
16662 /*WriteMem=*/true);
16663 Chain = VAARG.getValue(1);
16665 // Load the next argument and return it
16666 return DAG.getLoad(ArgVT, dl,
16669 MachinePointerInfo(),
16670 false, false, false, 0);
16673 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16674 SelectionDAG &DAG) {
16675 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16676 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16677 SDValue Chain = Op.getOperand(0);
16678 SDValue DstPtr = Op.getOperand(1);
16679 SDValue SrcPtr = Op.getOperand(2);
16680 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16681 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16684 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16685 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16687 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16690 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16691 // amount is a constant. Takes immediate version of shift as input.
16692 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16693 SDValue SrcOp, uint64_t ShiftAmt,
16694 SelectionDAG &DAG) {
16695 MVT ElementType = VT.getVectorElementType();
16697 // Fold this packed shift into its first operand if ShiftAmt is 0.
16701 // Check for ShiftAmt >= element width
16702 if (ShiftAmt >= ElementType.getSizeInBits()) {
16703 if (Opc == X86ISD::VSRAI)
16704 ShiftAmt = ElementType.getSizeInBits() - 1;
16706 return DAG.getConstant(0, VT);
16709 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16710 && "Unknown target vector shift-by-constant node");
16712 // Fold this packed vector shift into a build vector if SrcOp is a
16713 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16714 if (VT == SrcOp.getSimpleValueType() &&
16715 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16716 SmallVector<SDValue, 8> Elts;
16717 unsigned NumElts = SrcOp->getNumOperands();
16718 ConstantSDNode *ND;
16721 default: llvm_unreachable(nullptr);
16722 case X86ISD::VSHLI:
16723 for (unsigned i=0; i!=NumElts; ++i) {
16724 SDValue CurrentOp = SrcOp->getOperand(i);
16725 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16726 Elts.push_back(CurrentOp);
16729 ND = cast<ConstantSDNode>(CurrentOp);
16730 const APInt &C = ND->getAPIntValue();
16731 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16734 case X86ISD::VSRLI:
16735 for (unsigned i=0; i!=NumElts; ++i) {
16736 SDValue CurrentOp = SrcOp->getOperand(i);
16737 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16738 Elts.push_back(CurrentOp);
16741 ND = cast<ConstantSDNode>(CurrentOp);
16742 const APInt &C = ND->getAPIntValue();
16743 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16746 case X86ISD::VSRAI:
16747 for (unsigned i=0; i!=NumElts; ++i) {
16748 SDValue CurrentOp = SrcOp->getOperand(i);
16749 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16750 Elts.push_back(CurrentOp);
16753 ND = cast<ConstantSDNode>(CurrentOp);
16754 const APInt &C = ND->getAPIntValue();
16755 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16760 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16763 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16766 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16767 // may or may not be a constant. Takes immediate version of shift as input.
16768 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16769 SDValue SrcOp, SDValue ShAmt,
16770 SelectionDAG &DAG) {
16771 MVT SVT = ShAmt.getSimpleValueType();
16772 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16774 // Catch shift-by-constant.
16775 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16776 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16777 CShAmt->getZExtValue(), DAG);
16779 // Change opcode to non-immediate version
16781 default: llvm_unreachable("Unknown target vector shift node");
16782 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16783 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16784 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16787 const X86Subtarget &Subtarget =
16788 DAG.getTarget().getSubtarget<X86Subtarget>();
16789 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16790 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16791 // Let the shuffle legalizer expand this shift amount node.
16792 SDValue Op0 = ShAmt.getOperand(0);
16793 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16794 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16796 // Need to build a vector containing shift amount.
16797 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16798 SmallVector<SDValue, 4> ShOps;
16799 ShOps.push_back(ShAmt);
16800 if (SVT == MVT::i32) {
16801 ShOps.push_back(DAG.getConstant(0, SVT));
16802 ShOps.push_back(DAG.getUNDEF(SVT));
16804 ShOps.push_back(DAG.getUNDEF(SVT));
16806 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16807 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16810 // The return type has to be a 128-bit type with the same element
16811 // type as the input type.
16812 MVT EltVT = VT.getVectorElementType();
16813 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16815 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16816 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16819 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16820 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16821 /// necessary casting for \p Mask when lowering masking intrinsics.
16822 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16823 SDValue PreservedSrc,
16824 const X86Subtarget *Subtarget,
16825 SelectionDAG &DAG) {
16826 EVT VT = Op.getValueType();
16827 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16828 MVT::i1, VT.getVectorNumElements());
16829 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16830 Mask.getValueType().getSizeInBits());
16833 assert(MaskVT.isSimple() && "invalid mask type");
16835 if (isAllOnes(Mask))
16838 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16839 // are extracted by EXTRACT_SUBVECTOR.
16840 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16841 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16842 DAG.getIntPtrConstant(0));
16844 switch (Op.getOpcode()) {
16846 case X86ISD::PCMPEQM:
16847 case X86ISD::PCMPGTM:
16849 case X86ISD::CMPMU:
16850 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16852 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16853 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16854 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16857 /// \brief Creates an SDNode for a predicated scalar operation.
16858 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16859 /// The mask is comming as MVT::i8 and it should be truncated
16860 /// to MVT::i1 while lowering masking intrinsics.
16861 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16862 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16863 /// a scalar instruction.
16864 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16865 SDValue PreservedSrc,
16866 const X86Subtarget *Subtarget,
16867 SelectionDAG &DAG) {
16868 if (isAllOnes(Mask))
16871 EVT VT = Op.getValueType();
16873 // The mask should be of type MVT::i1
16874 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16876 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16877 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16878 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16881 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16883 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16884 case Intrinsic::x86_fma_vfmadd_ps:
16885 case Intrinsic::x86_fma_vfmadd_pd:
16886 case Intrinsic::x86_fma_vfmadd_ps_256:
16887 case Intrinsic::x86_fma_vfmadd_pd_256:
16888 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16889 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16890 return X86ISD::FMADD;
16891 case Intrinsic::x86_fma_vfmsub_ps:
16892 case Intrinsic::x86_fma_vfmsub_pd:
16893 case Intrinsic::x86_fma_vfmsub_ps_256:
16894 case Intrinsic::x86_fma_vfmsub_pd_256:
16895 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16896 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16897 return X86ISD::FMSUB;
16898 case Intrinsic::x86_fma_vfnmadd_ps:
16899 case Intrinsic::x86_fma_vfnmadd_pd:
16900 case Intrinsic::x86_fma_vfnmadd_ps_256:
16901 case Intrinsic::x86_fma_vfnmadd_pd_256:
16902 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16903 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16904 return X86ISD::FNMADD;
16905 case Intrinsic::x86_fma_vfnmsub_ps:
16906 case Intrinsic::x86_fma_vfnmsub_pd:
16907 case Intrinsic::x86_fma_vfnmsub_ps_256:
16908 case Intrinsic::x86_fma_vfnmsub_pd_256:
16909 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16910 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16911 return X86ISD::FNMSUB;
16912 case Intrinsic::x86_fma_vfmaddsub_ps:
16913 case Intrinsic::x86_fma_vfmaddsub_pd:
16914 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16915 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16916 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16917 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16918 return X86ISD::FMADDSUB;
16919 case Intrinsic::x86_fma_vfmsubadd_ps:
16920 case Intrinsic::x86_fma_vfmsubadd_pd:
16921 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16922 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16923 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16924 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16925 return X86ISD::FMSUBADD;
16929 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16930 SelectionDAG &DAG) {
16932 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16933 EVT VT = Op.getValueType();
16934 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16936 switch(IntrData->Type) {
16937 case INTR_TYPE_1OP:
16938 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16939 case INTR_TYPE_2OP:
16940 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16942 case INTR_TYPE_3OP:
16943 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16944 Op.getOperand(2), Op.getOperand(3));
16945 case INTR_TYPE_1OP_MASK_RM: {
16946 SDValue Src = Op.getOperand(1);
16947 SDValue Src0 = Op.getOperand(2);
16948 SDValue Mask = Op.getOperand(3);
16949 SDValue RoundingMode = Op.getOperand(4);
16950 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16952 Mask, Src0, Subtarget, DAG);
16954 case INTR_TYPE_SCALAR_MASK_RM: {
16955 SDValue Src1 = Op.getOperand(1);
16956 SDValue Src2 = Op.getOperand(2);
16957 SDValue Src0 = Op.getOperand(3);
16958 SDValue Mask = Op.getOperand(4);
16959 SDValue RoundingMode = Op.getOperand(5);
16960 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16962 Mask, Src0, Subtarget, DAG);
16964 case INTR_TYPE_2OP_MASK: {
16965 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16967 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16970 case CMP_MASK_CC: {
16971 // Comparison intrinsics with masks.
16972 // Example of transformation:
16973 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16974 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16976 // (v8i1 (insert_subvector undef,
16977 // (v2i1 (and (PCMPEQM %a, %b),
16978 // (extract_subvector
16979 // (v8i1 (bitcast %mask)), 0))), 0))))
16980 EVT VT = Op.getOperand(1).getValueType();
16981 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16982 VT.getVectorNumElements());
16983 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16984 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16985 Mask.getValueType().getSizeInBits());
16987 if (IntrData->Type == CMP_MASK_CC) {
16988 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16989 Op.getOperand(2), Op.getOperand(3));
16991 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16992 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16995 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16996 DAG.getTargetConstant(0, MaskVT),
16998 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16999 DAG.getUNDEF(BitcastVT), CmpMask,
17000 DAG.getIntPtrConstant(0));
17001 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
17003 case COMI: { // Comparison intrinsics
17004 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
17005 SDValue LHS = Op.getOperand(1);
17006 SDValue RHS = Op.getOperand(2);
17007 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
17008 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
17009 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
17010 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17011 DAG.getConstant(X86CC, MVT::i8), Cond);
17012 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17015 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
17016 Op.getOperand(1), Op.getOperand(2), DAG);
17018 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
17019 Op.getSimpleValueType(),
17021 Op.getOperand(2), DAG),
17022 Op.getOperand(4), Op.getOperand(3), Subtarget,
17024 case COMPRESS_EXPAND_IN_REG: {
17025 SDValue Mask = Op.getOperand(3);
17026 SDValue DataToCompress = Op.getOperand(1);
17027 SDValue PassThru = Op.getOperand(2);
17028 if (isAllOnes(Mask)) // return data as is
17029 return Op.getOperand(1);
17030 EVT VT = Op.getValueType();
17031 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17032 VT.getVectorNumElements());
17033 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17034 Mask.getValueType().getSizeInBits());
17036 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17037 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17038 DAG.getIntPtrConstant(0));
17040 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17044 SDValue Mask = Op.getOperand(3);
17045 EVT VT = Op.getValueType();
17046 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17047 VT.getVectorNumElements());
17048 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17049 Mask.getValueType().getSizeInBits());
17051 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17052 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17053 DAG.getIntPtrConstant(0));
17054 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17059 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17060 dl, Op.getValueType(),
17064 Op.getOperand(4), Op.getOperand(1),
17073 default: return SDValue(); // Don't custom lower most intrinsics.
17075 case Intrinsic::x86_avx512_mask_valign_q_512:
17076 case Intrinsic::x86_avx512_mask_valign_d_512:
17077 // Vector source operands are swapped.
17078 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17079 Op.getValueType(), Op.getOperand(2),
17082 Op.getOperand(5), Op.getOperand(4),
17085 // ptest and testp intrinsics. The intrinsic these come from are designed to
17086 // return an integer value, not just an instruction so lower it to the ptest
17087 // or testp pattern and a setcc for the result.
17088 case Intrinsic::x86_sse41_ptestz:
17089 case Intrinsic::x86_sse41_ptestc:
17090 case Intrinsic::x86_sse41_ptestnzc:
17091 case Intrinsic::x86_avx_ptestz_256:
17092 case Intrinsic::x86_avx_ptestc_256:
17093 case Intrinsic::x86_avx_ptestnzc_256:
17094 case Intrinsic::x86_avx_vtestz_ps:
17095 case Intrinsic::x86_avx_vtestc_ps:
17096 case Intrinsic::x86_avx_vtestnzc_ps:
17097 case Intrinsic::x86_avx_vtestz_pd:
17098 case Intrinsic::x86_avx_vtestc_pd:
17099 case Intrinsic::x86_avx_vtestnzc_pd:
17100 case Intrinsic::x86_avx_vtestz_ps_256:
17101 case Intrinsic::x86_avx_vtestc_ps_256:
17102 case Intrinsic::x86_avx_vtestnzc_ps_256:
17103 case Intrinsic::x86_avx_vtestz_pd_256:
17104 case Intrinsic::x86_avx_vtestc_pd_256:
17105 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17106 bool IsTestPacked = false;
17109 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17110 case Intrinsic::x86_avx_vtestz_ps:
17111 case Intrinsic::x86_avx_vtestz_pd:
17112 case Intrinsic::x86_avx_vtestz_ps_256:
17113 case Intrinsic::x86_avx_vtestz_pd_256:
17114 IsTestPacked = true; // Fallthrough
17115 case Intrinsic::x86_sse41_ptestz:
17116 case Intrinsic::x86_avx_ptestz_256:
17118 X86CC = X86::COND_E;
17120 case Intrinsic::x86_avx_vtestc_ps:
17121 case Intrinsic::x86_avx_vtestc_pd:
17122 case Intrinsic::x86_avx_vtestc_ps_256:
17123 case Intrinsic::x86_avx_vtestc_pd_256:
17124 IsTestPacked = true; // Fallthrough
17125 case Intrinsic::x86_sse41_ptestc:
17126 case Intrinsic::x86_avx_ptestc_256:
17128 X86CC = X86::COND_B;
17130 case Intrinsic::x86_avx_vtestnzc_ps:
17131 case Intrinsic::x86_avx_vtestnzc_pd:
17132 case Intrinsic::x86_avx_vtestnzc_ps_256:
17133 case Intrinsic::x86_avx_vtestnzc_pd_256:
17134 IsTestPacked = true; // Fallthrough
17135 case Intrinsic::x86_sse41_ptestnzc:
17136 case Intrinsic::x86_avx_ptestnzc_256:
17138 X86CC = X86::COND_A;
17142 SDValue LHS = Op.getOperand(1);
17143 SDValue RHS = Op.getOperand(2);
17144 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17145 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17146 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17147 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17148 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17150 case Intrinsic::x86_avx512_kortestz_w:
17151 case Intrinsic::x86_avx512_kortestc_w: {
17152 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17153 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17154 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17155 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17156 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17157 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17158 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17161 case Intrinsic::x86_sse42_pcmpistria128:
17162 case Intrinsic::x86_sse42_pcmpestria128:
17163 case Intrinsic::x86_sse42_pcmpistric128:
17164 case Intrinsic::x86_sse42_pcmpestric128:
17165 case Intrinsic::x86_sse42_pcmpistrio128:
17166 case Intrinsic::x86_sse42_pcmpestrio128:
17167 case Intrinsic::x86_sse42_pcmpistris128:
17168 case Intrinsic::x86_sse42_pcmpestris128:
17169 case Intrinsic::x86_sse42_pcmpistriz128:
17170 case Intrinsic::x86_sse42_pcmpestriz128: {
17174 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17175 case Intrinsic::x86_sse42_pcmpistria128:
17176 Opcode = X86ISD::PCMPISTRI;
17177 X86CC = X86::COND_A;
17179 case Intrinsic::x86_sse42_pcmpestria128:
17180 Opcode = X86ISD::PCMPESTRI;
17181 X86CC = X86::COND_A;
17183 case Intrinsic::x86_sse42_pcmpistric128:
17184 Opcode = X86ISD::PCMPISTRI;
17185 X86CC = X86::COND_B;
17187 case Intrinsic::x86_sse42_pcmpestric128:
17188 Opcode = X86ISD::PCMPESTRI;
17189 X86CC = X86::COND_B;
17191 case Intrinsic::x86_sse42_pcmpistrio128:
17192 Opcode = X86ISD::PCMPISTRI;
17193 X86CC = X86::COND_O;
17195 case Intrinsic::x86_sse42_pcmpestrio128:
17196 Opcode = X86ISD::PCMPESTRI;
17197 X86CC = X86::COND_O;
17199 case Intrinsic::x86_sse42_pcmpistris128:
17200 Opcode = X86ISD::PCMPISTRI;
17201 X86CC = X86::COND_S;
17203 case Intrinsic::x86_sse42_pcmpestris128:
17204 Opcode = X86ISD::PCMPESTRI;
17205 X86CC = X86::COND_S;
17207 case Intrinsic::x86_sse42_pcmpistriz128:
17208 Opcode = X86ISD::PCMPISTRI;
17209 X86CC = X86::COND_E;
17211 case Intrinsic::x86_sse42_pcmpestriz128:
17212 Opcode = X86ISD::PCMPESTRI;
17213 X86CC = X86::COND_E;
17216 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17217 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17218 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17219 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17220 DAG.getConstant(X86CC, MVT::i8),
17221 SDValue(PCMP.getNode(), 1));
17222 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17225 case Intrinsic::x86_sse42_pcmpistri128:
17226 case Intrinsic::x86_sse42_pcmpestri128: {
17228 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17229 Opcode = X86ISD::PCMPISTRI;
17231 Opcode = X86ISD::PCMPESTRI;
17233 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17234 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17235 return DAG.getNode(Opcode, dl, VTs, NewOps);
17238 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17239 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17240 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17241 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17242 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17243 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17244 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17245 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17246 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17247 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17248 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17249 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17250 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17251 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17252 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17253 dl, Op.getValueType(),
17257 Op.getOperand(4), Op.getOperand(1),
17263 case Intrinsic::x86_fma_vfmadd_ps:
17264 case Intrinsic::x86_fma_vfmadd_pd:
17265 case Intrinsic::x86_fma_vfmsub_ps:
17266 case Intrinsic::x86_fma_vfmsub_pd:
17267 case Intrinsic::x86_fma_vfnmadd_ps:
17268 case Intrinsic::x86_fma_vfnmadd_pd:
17269 case Intrinsic::x86_fma_vfnmsub_ps:
17270 case Intrinsic::x86_fma_vfnmsub_pd:
17271 case Intrinsic::x86_fma_vfmaddsub_ps:
17272 case Intrinsic::x86_fma_vfmaddsub_pd:
17273 case Intrinsic::x86_fma_vfmsubadd_ps:
17274 case Intrinsic::x86_fma_vfmsubadd_pd:
17275 case Intrinsic::x86_fma_vfmadd_ps_256:
17276 case Intrinsic::x86_fma_vfmadd_pd_256:
17277 case Intrinsic::x86_fma_vfmsub_ps_256:
17278 case Intrinsic::x86_fma_vfmsub_pd_256:
17279 case Intrinsic::x86_fma_vfnmadd_ps_256:
17280 case Intrinsic::x86_fma_vfnmadd_pd_256:
17281 case Intrinsic::x86_fma_vfnmsub_ps_256:
17282 case Intrinsic::x86_fma_vfnmsub_pd_256:
17283 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17284 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17285 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17286 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17287 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17288 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17292 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17293 SDValue Src, SDValue Mask, SDValue Base,
17294 SDValue Index, SDValue ScaleOp, SDValue Chain,
17295 const X86Subtarget * Subtarget) {
17297 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17298 assert(C && "Invalid scale type");
17299 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17300 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17301 Index.getSimpleValueType().getVectorNumElements());
17303 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17305 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17307 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17308 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17309 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17310 SDValue Segment = DAG.getRegister(0, MVT::i32);
17311 if (Src.getOpcode() == ISD::UNDEF)
17312 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17313 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17314 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17315 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17316 return DAG.getMergeValues(RetOps, dl);
17319 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17320 SDValue Src, SDValue Mask, SDValue Base,
17321 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17323 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17324 assert(C && "Invalid scale type");
17325 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17326 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17327 SDValue Segment = DAG.getRegister(0, MVT::i32);
17328 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17329 Index.getSimpleValueType().getVectorNumElements());
17331 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17333 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17335 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17336 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17337 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17338 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17339 return SDValue(Res, 1);
17342 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17343 SDValue Mask, SDValue Base, SDValue Index,
17344 SDValue ScaleOp, SDValue Chain) {
17346 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17347 assert(C && "Invalid scale type");
17348 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17349 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17350 SDValue Segment = DAG.getRegister(0, MVT::i32);
17352 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17354 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17356 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17358 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17359 //SDVTList VTs = DAG.getVTList(MVT::Other);
17360 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17361 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17362 return SDValue(Res, 0);
17365 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17366 // read performance monitor counters (x86_rdpmc).
17367 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17368 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17369 SmallVectorImpl<SDValue> &Results) {
17370 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17371 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17374 // The ECX register is used to select the index of the performance counter
17376 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17378 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17380 // Reads the content of a 64-bit performance counter and returns it in the
17381 // registers EDX:EAX.
17382 if (Subtarget->is64Bit()) {
17383 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17384 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17387 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17388 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17391 Chain = HI.getValue(1);
17393 if (Subtarget->is64Bit()) {
17394 // The EAX register is loaded with the low-order 32 bits. The EDX register
17395 // is loaded with the supported high-order bits of the counter.
17396 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17397 DAG.getConstant(32, MVT::i8));
17398 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17399 Results.push_back(Chain);
17403 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17404 SDValue Ops[] = { LO, HI };
17405 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17406 Results.push_back(Pair);
17407 Results.push_back(Chain);
17410 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17411 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17412 // also used to custom lower READCYCLECOUNTER nodes.
17413 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17414 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17415 SmallVectorImpl<SDValue> &Results) {
17416 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17417 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17420 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17421 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17422 // and the EAX register is loaded with the low-order 32 bits.
17423 if (Subtarget->is64Bit()) {
17424 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17425 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17428 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17429 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17432 SDValue Chain = HI.getValue(1);
17434 if (Opcode == X86ISD::RDTSCP_DAG) {
17435 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17437 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17438 // the ECX register. Add 'ecx' explicitly to the chain.
17439 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17441 // Explicitly store the content of ECX at the location passed in input
17442 // to the 'rdtscp' intrinsic.
17443 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17444 MachinePointerInfo(), false, false, 0);
17447 if (Subtarget->is64Bit()) {
17448 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17449 // the EAX register is loaded with the low-order 32 bits.
17450 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17451 DAG.getConstant(32, MVT::i8));
17452 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17453 Results.push_back(Chain);
17457 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17458 SDValue Ops[] = { LO, HI };
17459 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17460 Results.push_back(Pair);
17461 Results.push_back(Chain);
17464 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17465 SelectionDAG &DAG) {
17466 SmallVector<SDValue, 2> Results;
17468 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17470 return DAG.getMergeValues(Results, DL);
17474 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17475 SelectionDAG &DAG) {
17476 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17478 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17483 switch(IntrData->Type) {
17485 llvm_unreachable("Unknown Intrinsic Type");
17489 // Emit the node with the right value type.
17490 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17491 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17493 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17494 // Otherwise return the value from Rand, which is always 0, casted to i32.
17495 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17496 DAG.getConstant(1, Op->getValueType(1)),
17497 DAG.getConstant(X86::COND_B, MVT::i32),
17498 SDValue(Result.getNode(), 1) };
17499 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17500 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17503 // Return { result, isValid, chain }.
17504 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17505 SDValue(Result.getNode(), 2));
17508 //gather(v1, mask, index, base, scale);
17509 SDValue Chain = Op.getOperand(0);
17510 SDValue Src = Op.getOperand(2);
17511 SDValue Base = Op.getOperand(3);
17512 SDValue Index = Op.getOperand(4);
17513 SDValue Mask = Op.getOperand(5);
17514 SDValue Scale = Op.getOperand(6);
17515 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17519 //scatter(base, mask, index, v1, scale);
17520 SDValue Chain = Op.getOperand(0);
17521 SDValue Base = Op.getOperand(2);
17522 SDValue Mask = Op.getOperand(3);
17523 SDValue Index = Op.getOperand(4);
17524 SDValue Src = Op.getOperand(5);
17525 SDValue Scale = Op.getOperand(6);
17526 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17529 SDValue Hint = Op.getOperand(6);
17531 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17532 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17533 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17534 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17535 SDValue Chain = Op.getOperand(0);
17536 SDValue Mask = Op.getOperand(2);
17537 SDValue Index = Op.getOperand(3);
17538 SDValue Base = Op.getOperand(4);
17539 SDValue Scale = Op.getOperand(5);
17540 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17542 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17544 SmallVector<SDValue, 2> Results;
17545 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17546 return DAG.getMergeValues(Results, dl);
17548 // Read Performance Monitoring Counters.
17550 SmallVector<SDValue, 2> Results;
17551 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17552 return DAG.getMergeValues(Results, dl);
17554 // XTEST intrinsics.
17556 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17557 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17558 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17559 DAG.getConstant(X86::COND_NE, MVT::i8),
17561 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17562 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17563 Ret, SDValue(InTrans.getNode(), 1));
17567 SmallVector<SDValue, 2> Results;
17568 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17569 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17570 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17571 DAG.getConstant(-1, MVT::i8));
17572 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17573 Op.getOperand(4), GenCF.getValue(1));
17574 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17575 Op.getOperand(5), MachinePointerInfo(),
17577 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17578 DAG.getConstant(X86::COND_B, MVT::i8),
17580 Results.push_back(SetCC);
17581 Results.push_back(Store);
17582 return DAG.getMergeValues(Results, dl);
17584 case COMPRESS_TO_MEM: {
17586 SDValue Mask = Op.getOperand(4);
17587 SDValue DataToCompress = Op.getOperand(3);
17588 SDValue Addr = Op.getOperand(2);
17589 SDValue Chain = Op.getOperand(0);
17591 if (isAllOnes(Mask)) // return just a store
17592 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17593 MachinePointerInfo(), false, false, 0);
17595 EVT VT = DataToCompress.getValueType();
17596 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17597 VT.getVectorNumElements());
17598 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17599 Mask.getValueType().getSizeInBits());
17600 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17601 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17602 DAG.getIntPtrConstant(0));
17604 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17605 DataToCompress, DAG.getUNDEF(VT));
17606 return DAG.getStore(Chain, dl, Compressed, Addr,
17607 MachinePointerInfo(), false, false, 0);
17609 case EXPAND_FROM_MEM: {
17611 SDValue Mask = Op.getOperand(4);
17612 SDValue PathThru = Op.getOperand(3);
17613 SDValue Addr = Op.getOperand(2);
17614 SDValue Chain = Op.getOperand(0);
17615 EVT VT = Op.getValueType();
17617 if (isAllOnes(Mask)) // return just a load
17618 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17620 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17621 VT.getVectorNumElements());
17622 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17623 Mask.getValueType().getSizeInBits());
17624 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17625 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17626 DAG.getIntPtrConstant(0));
17628 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17629 false, false, false, 0);
17631 SmallVector<SDValue, 2> Results;
17632 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17634 Results.push_back(Chain);
17635 return DAG.getMergeValues(Results, dl);
17640 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17641 SelectionDAG &DAG) const {
17642 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17643 MFI->setReturnAddressIsTaken(true);
17645 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17648 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17650 EVT PtrVT = getPointerTy();
17653 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17654 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17655 DAG.getSubtarget().getRegisterInfo());
17656 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17657 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17658 DAG.getNode(ISD::ADD, dl, PtrVT,
17659 FrameAddr, Offset),
17660 MachinePointerInfo(), false, false, false, 0);
17663 // Just load the return address.
17664 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17665 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17666 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17669 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17670 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17671 MFI->setFrameAddressIsTaken(true);
17673 EVT VT = Op.getValueType();
17674 SDLoc dl(Op); // FIXME probably not meaningful
17675 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17676 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17677 DAG.getSubtarget().getRegisterInfo());
17678 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17679 DAG.getMachineFunction());
17680 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17681 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17682 "Invalid Frame Register!");
17683 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17685 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17686 MachinePointerInfo(),
17687 false, false, false, 0);
17691 // FIXME? Maybe this could be a TableGen attribute on some registers and
17692 // this table could be generated automatically from RegInfo.
17693 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17695 unsigned Reg = StringSwitch<unsigned>(RegName)
17696 .Case("esp", X86::ESP)
17697 .Case("rsp", X86::RSP)
17701 report_fatal_error("Invalid register name global variable");
17704 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17705 SelectionDAG &DAG) const {
17706 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17707 DAG.getSubtarget().getRegisterInfo());
17708 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17711 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17712 SDValue Chain = Op.getOperand(0);
17713 SDValue Offset = Op.getOperand(1);
17714 SDValue Handler = Op.getOperand(2);
17717 EVT PtrVT = getPointerTy();
17718 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17719 DAG.getSubtarget().getRegisterInfo());
17720 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17721 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17722 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17723 "Invalid Frame Register!");
17724 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17725 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17727 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17728 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17729 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17730 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17732 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17734 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17735 DAG.getRegister(StoreAddrReg, PtrVT));
17738 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17739 SelectionDAG &DAG) const {
17741 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17742 DAG.getVTList(MVT::i32, MVT::Other),
17743 Op.getOperand(0), Op.getOperand(1));
17746 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17747 SelectionDAG &DAG) const {
17749 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17750 Op.getOperand(0), Op.getOperand(1));
17753 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17754 return Op.getOperand(0);
17757 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17758 SelectionDAG &DAG) const {
17759 SDValue Root = Op.getOperand(0);
17760 SDValue Trmp = Op.getOperand(1); // trampoline
17761 SDValue FPtr = Op.getOperand(2); // nested function
17762 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17765 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17766 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17768 if (Subtarget->is64Bit()) {
17769 SDValue OutChains[6];
17771 // Large code-model.
17772 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17773 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17775 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17776 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17778 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17780 // Load the pointer to the nested function into R11.
17781 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17782 SDValue Addr = Trmp;
17783 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17784 Addr, MachinePointerInfo(TrmpAddr),
17787 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17788 DAG.getConstant(2, MVT::i64));
17789 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17790 MachinePointerInfo(TrmpAddr, 2),
17793 // Load the 'nest' parameter value into R10.
17794 // R10 is specified in X86CallingConv.td
17795 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17796 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17797 DAG.getConstant(10, MVT::i64));
17798 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17799 Addr, MachinePointerInfo(TrmpAddr, 10),
17802 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17803 DAG.getConstant(12, MVT::i64));
17804 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17805 MachinePointerInfo(TrmpAddr, 12),
17808 // Jump to the nested function.
17809 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17810 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17811 DAG.getConstant(20, MVT::i64));
17812 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17813 Addr, MachinePointerInfo(TrmpAddr, 20),
17816 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17817 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17818 DAG.getConstant(22, MVT::i64));
17819 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17820 MachinePointerInfo(TrmpAddr, 22),
17823 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17825 const Function *Func =
17826 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17827 CallingConv::ID CC = Func->getCallingConv();
17832 llvm_unreachable("Unsupported calling convention");
17833 case CallingConv::C:
17834 case CallingConv::X86_StdCall: {
17835 // Pass 'nest' parameter in ECX.
17836 // Must be kept in sync with X86CallingConv.td
17837 NestReg = X86::ECX;
17839 // Check that ECX wasn't needed by an 'inreg' parameter.
17840 FunctionType *FTy = Func->getFunctionType();
17841 const AttributeSet &Attrs = Func->getAttributes();
17843 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17844 unsigned InRegCount = 0;
17847 for (FunctionType::param_iterator I = FTy->param_begin(),
17848 E = FTy->param_end(); I != E; ++I, ++Idx)
17849 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17850 // FIXME: should only count parameters that are lowered to integers.
17851 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17853 if (InRegCount > 2) {
17854 report_fatal_error("Nest register in use - reduce number of inreg"
17860 case CallingConv::X86_FastCall:
17861 case CallingConv::X86_ThisCall:
17862 case CallingConv::Fast:
17863 // Pass 'nest' parameter in EAX.
17864 // Must be kept in sync with X86CallingConv.td
17865 NestReg = X86::EAX;
17869 SDValue OutChains[4];
17870 SDValue Addr, Disp;
17872 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17873 DAG.getConstant(10, MVT::i32));
17874 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17876 // This is storing the opcode for MOV32ri.
17877 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17878 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17879 OutChains[0] = DAG.getStore(Root, dl,
17880 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17881 Trmp, MachinePointerInfo(TrmpAddr),
17884 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17885 DAG.getConstant(1, MVT::i32));
17886 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17887 MachinePointerInfo(TrmpAddr, 1),
17890 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17891 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17892 DAG.getConstant(5, MVT::i32));
17893 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17894 MachinePointerInfo(TrmpAddr, 5),
17897 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17898 DAG.getConstant(6, MVT::i32));
17899 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17900 MachinePointerInfo(TrmpAddr, 6),
17903 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17907 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17908 SelectionDAG &DAG) const {
17910 The rounding mode is in bits 11:10 of FPSR, and has the following
17912 00 Round to nearest
17917 FLT_ROUNDS, on the other hand, expects the following:
17924 To perform the conversion, we do:
17925 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17928 MachineFunction &MF = DAG.getMachineFunction();
17929 const TargetMachine &TM = MF.getTarget();
17930 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17931 unsigned StackAlignment = TFI.getStackAlignment();
17932 MVT VT = Op.getSimpleValueType();
17935 // Save FP Control Word to stack slot
17936 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17937 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17939 MachineMemOperand *MMO =
17940 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17941 MachineMemOperand::MOStore, 2, 2);
17943 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17944 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17945 DAG.getVTList(MVT::Other),
17946 Ops, MVT::i16, MMO);
17948 // Load FP Control Word from stack slot
17949 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17950 MachinePointerInfo(), false, false, false, 0);
17952 // Transform as necessary
17954 DAG.getNode(ISD::SRL, DL, MVT::i16,
17955 DAG.getNode(ISD::AND, DL, MVT::i16,
17956 CWD, DAG.getConstant(0x800, MVT::i16)),
17957 DAG.getConstant(11, MVT::i8));
17959 DAG.getNode(ISD::SRL, DL, MVT::i16,
17960 DAG.getNode(ISD::AND, DL, MVT::i16,
17961 CWD, DAG.getConstant(0x400, MVT::i16)),
17962 DAG.getConstant(9, MVT::i8));
17965 DAG.getNode(ISD::AND, DL, MVT::i16,
17966 DAG.getNode(ISD::ADD, DL, MVT::i16,
17967 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17968 DAG.getConstant(1, MVT::i16)),
17969 DAG.getConstant(3, MVT::i16));
17971 return DAG.getNode((VT.getSizeInBits() < 16 ?
17972 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17975 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17976 MVT VT = Op.getSimpleValueType();
17978 unsigned NumBits = VT.getSizeInBits();
17981 Op = Op.getOperand(0);
17982 if (VT == MVT::i8) {
17983 // Zero extend to i32 since there is not an i8 bsr.
17985 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17988 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17989 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17990 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17992 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17995 DAG.getConstant(NumBits+NumBits-1, OpVT),
17996 DAG.getConstant(X86::COND_E, MVT::i8),
17999 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
18001 // Finally xor with NumBits-1.
18002 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18005 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18009 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
18010 MVT VT = Op.getSimpleValueType();
18012 unsigned NumBits = VT.getSizeInBits();
18015 Op = Op.getOperand(0);
18016 if (VT == MVT::i8) {
18017 // Zero extend to i32 since there is not an i8 bsr.
18019 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18022 // Issue a bsr (scan bits in reverse).
18023 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18024 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18026 // And xor with NumBits-1.
18027 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18030 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18034 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18035 MVT VT = Op.getSimpleValueType();
18036 unsigned NumBits = VT.getSizeInBits();
18038 Op = Op.getOperand(0);
18040 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18041 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18042 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18044 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18047 DAG.getConstant(NumBits, VT),
18048 DAG.getConstant(X86::COND_E, MVT::i8),
18051 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18054 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18055 // ones, and then concatenate the result back.
18056 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18057 MVT VT = Op.getSimpleValueType();
18059 assert(VT.is256BitVector() && VT.isInteger() &&
18060 "Unsupported value type for operation");
18062 unsigned NumElems = VT.getVectorNumElements();
18065 // Extract the LHS vectors
18066 SDValue LHS = Op.getOperand(0);
18067 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18068 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18070 // Extract the RHS vectors
18071 SDValue RHS = Op.getOperand(1);
18072 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18073 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18075 MVT EltVT = VT.getVectorElementType();
18076 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18078 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18079 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18080 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18083 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18084 assert(Op.getSimpleValueType().is256BitVector() &&
18085 Op.getSimpleValueType().isInteger() &&
18086 "Only handle AVX 256-bit vector integer operation");
18087 return Lower256IntArith(Op, DAG);
18090 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18091 assert(Op.getSimpleValueType().is256BitVector() &&
18092 Op.getSimpleValueType().isInteger() &&
18093 "Only handle AVX 256-bit vector integer operation");
18094 return Lower256IntArith(Op, DAG);
18097 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18098 SelectionDAG &DAG) {
18100 MVT VT = Op.getSimpleValueType();
18102 // Decompose 256-bit ops into smaller 128-bit ops.
18103 if (VT.is256BitVector() && !Subtarget->hasInt256())
18104 return Lower256IntArith(Op, DAG);
18106 SDValue A = Op.getOperand(0);
18107 SDValue B = Op.getOperand(1);
18109 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18110 if (VT == MVT::v4i32) {
18111 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18112 "Should not custom lower when pmuldq is available!");
18114 // Extract the odd parts.
18115 static const int UnpackMask[] = { 1, -1, 3, -1 };
18116 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18117 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18119 // Multiply the even parts.
18120 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18121 // Now multiply odd parts.
18122 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18124 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18125 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18127 // Merge the two vectors back together with a shuffle. This expands into 2
18129 static const int ShufMask[] = { 0, 4, 2, 6 };
18130 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18133 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18134 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18136 // Ahi = psrlqi(a, 32);
18137 // Bhi = psrlqi(b, 32);
18139 // AloBlo = pmuludq(a, b);
18140 // AloBhi = pmuludq(a, Bhi);
18141 // AhiBlo = pmuludq(Ahi, b);
18143 // AloBhi = psllqi(AloBhi, 32);
18144 // AhiBlo = psllqi(AhiBlo, 32);
18145 // return AloBlo + AloBhi + AhiBlo;
18147 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18148 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18150 // Bit cast to 32-bit vectors for MULUDQ
18151 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18152 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18153 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18154 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18155 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18156 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18158 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18159 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18160 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18162 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18163 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18165 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18166 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18169 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18170 assert(Subtarget->isTargetWin64() && "Unexpected target");
18171 EVT VT = Op.getValueType();
18172 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18173 "Unexpected return type for lowering");
18177 switch (Op->getOpcode()) {
18178 default: llvm_unreachable("Unexpected request for libcall!");
18179 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18180 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18181 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18182 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18183 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18184 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18188 SDValue InChain = DAG.getEntryNode();
18190 TargetLowering::ArgListTy Args;
18191 TargetLowering::ArgListEntry Entry;
18192 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18193 EVT ArgVT = Op->getOperand(i).getValueType();
18194 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18195 "Unexpected argument type for lowering");
18196 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18197 Entry.Node = StackPtr;
18198 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18200 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18201 Entry.Ty = PointerType::get(ArgTy,0);
18202 Entry.isSExt = false;
18203 Entry.isZExt = false;
18204 Args.push_back(Entry);
18207 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18210 TargetLowering::CallLoweringInfo CLI(DAG);
18211 CLI.setDebugLoc(dl).setChain(InChain)
18212 .setCallee(getLibcallCallingConv(LC),
18213 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18214 Callee, std::move(Args), 0)
18215 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18217 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18218 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18221 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18222 SelectionDAG &DAG) {
18223 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18224 EVT VT = Op0.getValueType();
18227 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18228 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18230 // PMULxD operations multiply each even value (starting at 0) of LHS with
18231 // the related value of RHS and produce a widen result.
18232 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18233 // => <2 x i64> <ae|cg>
18235 // In other word, to have all the results, we need to perform two PMULxD:
18236 // 1. one with the even values.
18237 // 2. one with the odd values.
18238 // To achieve #2, with need to place the odd values at an even position.
18240 // Place the odd value at an even position (basically, shift all values 1
18241 // step to the left):
18242 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18243 // <a|b|c|d> => <b|undef|d|undef>
18244 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18245 // <e|f|g|h> => <f|undef|h|undef>
18246 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18248 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18250 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18251 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18253 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18254 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18255 // => <2 x i64> <ae|cg>
18256 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18257 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18258 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18259 // => <2 x i64> <bf|dh>
18260 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18261 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18263 // Shuffle it back into the right order.
18264 SDValue Highs, Lows;
18265 if (VT == MVT::v8i32) {
18266 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18267 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18268 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18269 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18271 const int HighMask[] = {1, 5, 3, 7};
18272 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18273 const int LowMask[] = {0, 4, 2, 6};
18274 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18277 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18278 // unsigned multiply.
18279 if (IsSigned && !Subtarget->hasSSE41()) {
18281 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18282 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18283 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18284 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18285 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18287 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18288 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18291 // The first result of MUL_LOHI is actually the low value, followed by the
18293 SDValue Ops[] = {Lows, Highs};
18294 return DAG.getMergeValues(Ops, dl);
18297 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18298 const X86Subtarget *Subtarget) {
18299 MVT VT = Op.getSimpleValueType();
18301 SDValue R = Op.getOperand(0);
18302 SDValue Amt = Op.getOperand(1);
18304 // Optimize shl/srl/sra with constant shift amount.
18305 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18306 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18307 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18309 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18310 (Subtarget->hasInt256() &&
18311 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18312 (Subtarget->hasAVX512() &&
18313 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18314 if (Op.getOpcode() == ISD::SHL)
18315 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18317 if (Op.getOpcode() == ISD::SRL)
18318 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18320 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18321 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18325 if (VT == MVT::v16i8) {
18326 if (Op.getOpcode() == ISD::SHL) {
18327 // Make a large shift.
18328 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18329 MVT::v8i16, R, ShiftAmt,
18331 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18332 // Zero out the rightmost bits.
18333 SmallVector<SDValue, 16> V(16,
18334 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18336 return DAG.getNode(ISD::AND, dl, VT, SHL,
18337 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18339 if (Op.getOpcode() == ISD::SRL) {
18340 // Make a large shift.
18341 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18342 MVT::v8i16, R, ShiftAmt,
18344 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18345 // Zero out the leftmost bits.
18346 SmallVector<SDValue, 16> V(16,
18347 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18349 return DAG.getNode(ISD::AND, dl, VT, SRL,
18350 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18352 if (Op.getOpcode() == ISD::SRA) {
18353 if (ShiftAmt == 7) {
18354 // R s>> 7 === R s< 0
18355 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18356 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18359 // R s>> a === ((R u>> a) ^ m) - m
18360 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18361 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18363 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18364 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18365 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18368 llvm_unreachable("Unknown shift opcode.");
18371 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18372 if (Op.getOpcode() == ISD::SHL) {
18373 // Make a large shift.
18374 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18375 MVT::v16i16, R, ShiftAmt,
18377 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18378 // Zero out the rightmost bits.
18379 SmallVector<SDValue, 32> V(32,
18380 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18382 return DAG.getNode(ISD::AND, dl, VT, SHL,
18383 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18385 if (Op.getOpcode() == ISD::SRL) {
18386 // Make a large shift.
18387 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18388 MVT::v16i16, R, ShiftAmt,
18390 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18391 // Zero out the leftmost bits.
18392 SmallVector<SDValue, 32> V(32,
18393 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18395 return DAG.getNode(ISD::AND, dl, VT, SRL,
18396 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18398 if (Op.getOpcode() == ISD::SRA) {
18399 if (ShiftAmt == 7) {
18400 // R s>> 7 === R s< 0
18401 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18402 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18405 // R s>> a === ((R u>> a) ^ m) - m
18406 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18407 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18409 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18410 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18411 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18414 llvm_unreachable("Unknown shift opcode.");
18419 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18420 if (!Subtarget->is64Bit() &&
18421 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18422 Amt.getOpcode() == ISD::BITCAST &&
18423 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18424 Amt = Amt.getOperand(0);
18425 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18426 VT.getVectorNumElements();
18427 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18428 uint64_t ShiftAmt = 0;
18429 for (unsigned i = 0; i != Ratio; ++i) {
18430 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18434 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18436 // Check remaining shift amounts.
18437 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18438 uint64_t ShAmt = 0;
18439 for (unsigned j = 0; j != Ratio; ++j) {
18440 ConstantSDNode *C =
18441 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18445 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18447 if (ShAmt != ShiftAmt)
18450 switch (Op.getOpcode()) {
18452 llvm_unreachable("Unknown shift opcode!");
18454 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18457 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18460 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18468 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18469 const X86Subtarget* Subtarget) {
18470 MVT VT = Op.getSimpleValueType();
18472 SDValue R = Op.getOperand(0);
18473 SDValue Amt = Op.getOperand(1);
18475 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18476 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18477 (Subtarget->hasInt256() &&
18478 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18479 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18480 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18482 EVT EltVT = VT.getVectorElementType();
18484 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18485 // Check if this build_vector node is doing a splat.
18486 // If so, then set BaseShAmt equal to the splat value.
18487 BaseShAmt = BV->getSplatValue();
18488 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18489 BaseShAmt = SDValue();
18491 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18492 Amt = Amt.getOperand(0);
18494 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18495 if (SVN && SVN->isSplat()) {
18496 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18497 SDValue InVec = Amt.getOperand(0);
18498 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18499 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18500 "Unexpected shuffle index found!");
18501 BaseShAmt = InVec.getOperand(SplatIdx);
18502 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18503 if (ConstantSDNode *C =
18504 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18505 if (C->getZExtValue() == SplatIdx)
18506 BaseShAmt = InVec.getOperand(1);
18511 // Avoid introducing an extract element from a shuffle.
18512 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18513 DAG.getIntPtrConstant(SplatIdx));
18517 if (BaseShAmt.getNode()) {
18518 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18519 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18520 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18521 else if (EltVT.bitsLT(MVT::i32))
18522 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18524 switch (Op.getOpcode()) {
18526 llvm_unreachable("Unknown shift opcode!");
18528 switch (VT.SimpleTy) {
18529 default: return SDValue();
18538 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18541 switch (VT.SimpleTy) {
18542 default: return SDValue();
18549 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18552 switch (VT.SimpleTy) {
18553 default: return SDValue();
18562 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18568 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18569 if (!Subtarget->is64Bit() &&
18570 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18571 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18572 Amt.getOpcode() == ISD::BITCAST &&
18573 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18574 Amt = Amt.getOperand(0);
18575 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18576 VT.getVectorNumElements();
18577 std::vector<SDValue> Vals(Ratio);
18578 for (unsigned i = 0; i != Ratio; ++i)
18579 Vals[i] = Amt.getOperand(i);
18580 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18581 for (unsigned j = 0; j != Ratio; ++j)
18582 if (Vals[j] != Amt.getOperand(i + j))
18585 switch (Op.getOpcode()) {
18587 llvm_unreachable("Unknown shift opcode!");
18589 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18591 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18593 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18600 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18601 SelectionDAG &DAG) {
18602 MVT VT = Op.getSimpleValueType();
18604 SDValue R = Op.getOperand(0);
18605 SDValue Amt = Op.getOperand(1);
18608 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18609 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18611 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18615 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18619 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18621 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18622 if (Subtarget->hasInt256()) {
18623 if (Op.getOpcode() == ISD::SRL &&
18624 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18625 VT == MVT::v4i64 || VT == MVT::v8i32))
18627 if (Op.getOpcode() == ISD::SHL &&
18628 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18629 VT == MVT::v4i64 || VT == MVT::v8i32))
18631 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18635 // If possible, lower this packed shift into a vector multiply instead of
18636 // expanding it into a sequence of scalar shifts.
18637 // Do this only if the vector shift count is a constant build_vector.
18638 if (Op.getOpcode() == ISD::SHL &&
18639 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18640 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18641 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18642 SmallVector<SDValue, 8> Elts;
18643 EVT SVT = VT.getScalarType();
18644 unsigned SVTBits = SVT.getSizeInBits();
18645 const APInt &One = APInt(SVTBits, 1);
18646 unsigned NumElems = VT.getVectorNumElements();
18648 for (unsigned i=0; i !=NumElems; ++i) {
18649 SDValue Op = Amt->getOperand(i);
18650 if (Op->getOpcode() == ISD::UNDEF) {
18651 Elts.push_back(Op);
18655 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18656 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18657 uint64_t ShAmt = C.getZExtValue();
18658 if (ShAmt >= SVTBits) {
18659 Elts.push_back(DAG.getUNDEF(SVT));
18662 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18664 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18665 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18668 // Lower SHL with variable shift amount.
18669 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18670 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18672 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18673 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18674 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18675 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18678 // If possible, lower this shift as a sequence of two shifts by
18679 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18681 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18683 // Could be rewritten as:
18684 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18686 // The advantage is that the two shifts from the example would be
18687 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18688 // the vector shift into four scalar shifts plus four pairs of vector
18690 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18691 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18692 unsigned TargetOpcode = X86ISD::MOVSS;
18693 bool CanBeSimplified;
18694 // The splat value for the first packed shift (the 'X' from the example).
18695 SDValue Amt1 = Amt->getOperand(0);
18696 // The splat value for the second packed shift (the 'Y' from the example).
18697 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18698 Amt->getOperand(2);
18700 // See if it is possible to replace this node with a sequence of
18701 // two shifts followed by a MOVSS/MOVSD
18702 if (VT == MVT::v4i32) {
18703 // Check if it is legal to use a MOVSS.
18704 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18705 Amt2 == Amt->getOperand(3);
18706 if (!CanBeSimplified) {
18707 // Otherwise, check if we can still simplify this node using a MOVSD.
18708 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18709 Amt->getOperand(2) == Amt->getOperand(3);
18710 TargetOpcode = X86ISD::MOVSD;
18711 Amt2 = Amt->getOperand(2);
18714 // Do similar checks for the case where the machine value type
18716 CanBeSimplified = Amt1 == Amt->getOperand(1);
18717 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18718 CanBeSimplified = Amt2 == Amt->getOperand(i);
18720 if (!CanBeSimplified) {
18721 TargetOpcode = X86ISD::MOVSD;
18722 CanBeSimplified = true;
18723 Amt2 = Amt->getOperand(4);
18724 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18725 CanBeSimplified = Amt1 == Amt->getOperand(i);
18726 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18727 CanBeSimplified = Amt2 == Amt->getOperand(j);
18731 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18732 isa<ConstantSDNode>(Amt2)) {
18733 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18734 EVT CastVT = MVT::v4i32;
18736 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18737 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18739 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18740 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18741 if (TargetOpcode == X86ISD::MOVSD)
18742 CastVT = MVT::v2i64;
18743 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18744 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18745 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18747 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18751 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18752 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18755 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18756 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18758 // Turn 'a' into a mask suitable for VSELECT
18759 SDValue VSelM = DAG.getConstant(0x80, VT);
18760 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18761 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18763 SDValue CM1 = DAG.getConstant(0x0f, VT);
18764 SDValue CM2 = DAG.getConstant(0x3f, VT);
18766 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18767 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18768 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18769 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18770 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18773 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18774 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18775 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18777 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18778 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18779 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18780 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18781 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18784 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18785 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18786 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18788 // return VSELECT(r, r+r, a);
18789 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18790 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18794 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18795 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18796 // solution better.
18797 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18798 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18800 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18801 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18802 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18803 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18804 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18807 // Decompose 256-bit shifts into smaller 128-bit shifts.
18808 if (VT.is256BitVector()) {
18809 unsigned NumElems = VT.getVectorNumElements();
18810 MVT EltVT = VT.getVectorElementType();
18811 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18813 // Extract the two vectors
18814 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18815 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18817 // Recreate the shift amount vectors
18818 SDValue Amt1, Amt2;
18819 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18820 // Constant shift amount
18821 SmallVector<SDValue, 4> Amt1Csts;
18822 SmallVector<SDValue, 4> Amt2Csts;
18823 for (unsigned i = 0; i != NumElems/2; ++i)
18824 Amt1Csts.push_back(Amt->getOperand(i));
18825 for (unsigned i = NumElems/2; i != NumElems; ++i)
18826 Amt2Csts.push_back(Amt->getOperand(i));
18828 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18829 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18831 // Variable shift amount
18832 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18833 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18836 // Issue new vector shifts for the smaller types
18837 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18838 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18840 // Concatenate the result back
18841 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18847 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18848 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18849 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18850 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18851 // has only one use.
18852 SDNode *N = Op.getNode();
18853 SDValue LHS = N->getOperand(0);
18854 SDValue RHS = N->getOperand(1);
18855 unsigned BaseOp = 0;
18858 switch (Op.getOpcode()) {
18859 default: llvm_unreachable("Unknown ovf instruction!");
18861 // A subtract of one will be selected as a INC. Note that INC doesn't
18862 // set CF, so we can't do this for UADDO.
18863 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18865 BaseOp = X86ISD::INC;
18866 Cond = X86::COND_O;
18869 BaseOp = X86ISD::ADD;
18870 Cond = X86::COND_O;
18873 BaseOp = X86ISD::ADD;
18874 Cond = X86::COND_B;
18877 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18878 // set CF, so we can't do this for USUBO.
18879 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18881 BaseOp = X86ISD::DEC;
18882 Cond = X86::COND_O;
18885 BaseOp = X86ISD::SUB;
18886 Cond = X86::COND_O;
18889 BaseOp = X86ISD::SUB;
18890 Cond = X86::COND_B;
18893 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18894 Cond = X86::COND_O;
18896 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18897 if (N->getValueType(0) == MVT::i8) {
18898 BaseOp = X86ISD::UMUL8;
18899 Cond = X86::COND_O;
18902 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18904 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18907 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18908 DAG.getConstant(X86::COND_O, MVT::i32),
18909 SDValue(Sum.getNode(), 2));
18911 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18915 // Also sets EFLAGS.
18916 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18917 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18920 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18921 DAG.getConstant(Cond, MVT::i32),
18922 SDValue(Sum.getNode(), 1));
18924 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18927 // Sign extension of the low part of vector elements. This may be used either
18928 // when sign extend instructions are not available or if the vector element
18929 // sizes already match the sign-extended size. If the vector elements are in
18930 // their pre-extended size and sign extend instructions are available, that will
18931 // be handled by LowerSIGN_EXTEND.
18932 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18933 SelectionDAG &DAG) const {
18935 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18936 MVT VT = Op.getSimpleValueType();
18938 if (!Subtarget->hasSSE2() || !VT.isVector())
18941 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18942 ExtraVT.getScalarType().getSizeInBits();
18944 switch (VT.SimpleTy) {
18945 default: return SDValue();
18948 if (!Subtarget->hasFp256())
18950 if (!Subtarget->hasInt256()) {
18951 // needs to be split
18952 unsigned NumElems = VT.getVectorNumElements();
18954 // Extract the LHS vectors
18955 SDValue LHS = Op.getOperand(0);
18956 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18957 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18959 MVT EltVT = VT.getVectorElementType();
18960 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18962 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18963 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18964 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18966 SDValue Extra = DAG.getValueType(ExtraVT);
18968 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18969 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18971 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18976 SDValue Op0 = Op.getOperand(0);
18978 // This is a sign extension of some low part of vector elements without
18979 // changing the size of the vector elements themselves:
18980 // Shift-Left + Shift-Right-Algebraic.
18981 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18983 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18989 /// Returns true if the operand type is exactly twice the native width, and
18990 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18991 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18992 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18993 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18994 const X86Subtarget &Subtarget =
18995 getTargetMachine().getSubtarget<X86Subtarget>();
18996 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18999 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19000 else if (OpWidth == 128)
19001 return Subtarget.hasCmpxchg16b();
19006 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19007 return needsCmpXchgNb(SI->getValueOperand()->getType());
19010 // Note: this turns large loads into lock cmpxchg8b/16b.
19011 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19012 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19013 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19014 return needsCmpXchgNb(PTy->getElementType());
19017 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19018 const X86Subtarget &Subtarget =
19019 getTargetMachine().getSubtarget<X86Subtarget>();
19020 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19021 const Type *MemType = AI->getType();
19023 // If the operand is too big, we must see if cmpxchg8/16b is available
19024 // and default to library calls otherwise.
19025 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19026 return needsCmpXchgNb(MemType);
19028 AtomicRMWInst::BinOp Op = AI->getOperation();
19031 llvm_unreachable("Unknown atomic operation");
19032 case AtomicRMWInst::Xchg:
19033 case AtomicRMWInst::Add:
19034 case AtomicRMWInst::Sub:
19035 // It's better to use xadd, xsub or xchg for these in all cases.
19037 case AtomicRMWInst::Or:
19038 case AtomicRMWInst::And:
19039 case AtomicRMWInst::Xor:
19040 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19041 // prefix to a normal instruction for these operations.
19042 return !AI->use_empty();
19043 case AtomicRMWInst::Nand:
19044 case AtomicRMWInst::Max:
19045 case AtomicRMWInst::Min:
19046 case AtomicRMWInst::UMax:
19047 case AtomicRMWInst::UMin:
19048 // These always require a non-trivial set of data operations on x86. We must
19049 // use a cmpxchg loop.
19054 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19055 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19056 // no-sse2). There isn't any reason to disable it if the target processor
19058 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19062 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19063 const X86Subtarget &Subtarget =
19064 getTargetMachine().getSubtarget<X86Subtarget>();
19065 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19066 const Type *MemType = AI->getType();
19067 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19068 // there is no benefit in turning such RMWs into loads, and it is actually
19069 // harmful as it introduces a mfence.
19070 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19073 auto Builder = IRBuilder<>(AI);
19074 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19075 auto SynchScope = AI->getSynchScope();
19076 // We must restrict the ordering to avoid generating loads with Release or
19077 // ReleaseAcquire orderings.
19078 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19079 auto Ptr = AI->getPointerOperand();
19081 // Before the load we need a fence. Here is an example lifted from
19082 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19085 // x.store(1, relaxed);
19086 // r1 = y.fetch_add(0, release);
19088 // y.fetch_add(42, acquire);
19089 // r2 = x.load(relaxed);
19090 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19091 // lowered to just a load without a fence. A mfence flushes the store buffer,
19092 // making the optimization clearly correct.
19093 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19094 // otherwise, we might be able to be more agressive on relaxed idempotent
19095 // rmw. In practice, they do not look useful, so we don't try to be
19096 // especially clever.
19097 if (SynchScope == SingleThread) {
19098 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19099 // the IR level, so we must wrap it in an intrinsic.
19101 } else if (hasMFENCE(Subtarget)) {
19102 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19103 Intrinsic::x86_sse2_mfence);
19104 Builder.CreateCall(MFence);
19106 // FIXME: it might make sense to use a locked operation here but on a
19107 // different cache-line to prevent cache-line bouncing. In practice it
19108 // is probably a small win, and x86 processors without mfence are rare
19109 // enough that we do not bother.
19113 // Finally we can emit the atomic load.
19114 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19115 AI->getType()->getPrimitiveSizeInBits());
19116 Loaded->setAtomic(Order, SynchScope);
19117 AI->replaceAllUsesWith(Loaded);
19118 AI->eraseFromParent();
19122 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19123 SelectionDAG &DAG) {
19125 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19126 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19127 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19128 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19130 // The only fence that needs an instruction is a sequentially-consistent
19131 // cross-thread fence.
19132 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19133 if (hasMFENCE(*Subtarget))
19134 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19136 SDValue Chain = Op.getOperand(0);
19137 SDValue Zero = DAG.getConstant(0, MVT::i32);
19139 DAG.getRegister(X86::ESP, MVT::i32), // Base
19140 DAG.getTargetConstant(1, MVT::i8), // Scale
19141 DAG.getRegister(0, MVT::i32), // Index
19142 DAG.getTargetConstant(0, MVT::i32), // Disp
19143 DAG.getRegister(0, MVT::i32), // Segment.
19147 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19148 return SDValue(Res, 0);
19151 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19152 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19155 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19156 SelectionDAG &DAG) {
19157 MVT T = Op.getSimpleValueType();
19161 switch(T.SimpleTy) {
19162 default: llvm_unreachable("Invalid value type!");
19163 case MVT::i8: Reg = X86::AL; size = 1; break;
19164 case MVT::i16: Reg = X86::AX; size = 2; break;
19165 case MVT::i32: Reg = X86::EAX; size = 4; break;
19167 assert(Subtarget->is64Bit() && "Node not type legal!");
19168 Reg = X86::RAX; size = 8;
19171 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19172 Op.getOperand(2), SDValue());
19173 SDValue Ops[] = { cpIn.getValue(0),
19176 DAG.getTargetConstant(size, MVT::i8),
19177 cpIn.getValue(1) };
19178 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19179 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19180 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19184 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19185 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19186 MVT::i32, cpOut.getValue(2));
19187 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19188 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19190 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19191 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19192 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19196 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19197 SelectionDAG &DAG) {
19198 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19199 MVT DstVT = Op.getSimpleValueType();
19201 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19202 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19203 if (DstVT != MVT::f64)
19204 // This conversion needs to be expanded.
19207 SDValue InVec = Op->getOperand(0);
19209 unsigned NumElts = SrcVT.getVectorNumElements();
19210 EVT SVT = SrcVT.getVectorElementType();
19212 // Widen the vector in input in the case of MVT::v2i32.
19213 // Example: from MVT::v2i32 to MVT::v4i32.
19214 SmallVector<SDValue, 16> Elts;
19215 for (unsigned i = 0, e = NumElts; i != e; ++i)
19216 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19217 DAG.getIntPtrConstant(i)));
19219 // Explicitly mark the extra elements as Undef.
19220 SDValue Undef = DAG.getUNDEF(SVT);
19221 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19222 Elts.push_back(Undef);
19224 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19225 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19226 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19227 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19228 DAG.getIntPtrConstant(0));
19231 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19232 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19233 assert((DstVT == MVT::i64 ||
19234 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19235 "Unexpected custom BITCAST");
19236 // i64 <=> MMX conversions are Legal.
19237 if (SrcVT==MVT::i64 && DstVT.isVector())
19239 if (DstVT==MVT::i64 && SrcVT.isVector())
19241 // MMX <=> MMX conversions are Legal.
19242 if (SrcVT.isVector() && DstVT.isVector())
19244 // All other conversions need to be expanded.
19248 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19249 SelectionDAG &DAG) {
19250 SDNode *Node = Op.getNode();
19253 Op = Op.getOperand(0);
19254 EVT VT = Op.getValueType();
19255 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19256 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19258 unsigned NumElts = VT.getVectorNumElements();
19259 EVT EltVT = VT.getVectorElementType();
19260 unsigned Len = EltVT.getSizeInBits();
19262 // This is the vectorized version of the "best" algorithm from
19263 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19264 // with a minor tweak to use a series of adds + shifts instead of vector
19265 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19267 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19268 // v8i32 => Always profitable
19270 // FIXME: There a couple of possible improvements:
19272 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19273 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19275 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19276 "CTPOP not implemented for this vector element type.");
19278 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19279 // extra legalization.
19280 bool NeedsBitcast = EltVT == MVT::i32;
19281 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19283 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19284 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19285 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19287 // v = v - ((v >> 1) & 0x55555555...)
19288 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19289 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19290 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19292 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19294 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19295 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19297 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19299 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19300 if (VT != And.getValueType())
19301 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19302 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19304 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19305 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19306 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19307 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19308 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19310 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19311 if (NeedsBitcast) {
19312 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19313 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19314 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19317 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19318 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19319 if (VT != AndRHS.getValueType()) {
19320 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19321 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19323 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19325 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19326 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19327 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19328 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19329 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19331 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19332 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19333 if (NeedsBitcast) {
19334 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19335 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19337 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19338 if (VT != And.getValueType())
19339 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19341 // The algorithm mentioned above uses:
19342 // v = (v * 0x01010101...) >> (Len - 8)
19344 // Change it to use vector adds + vector shifts which yield faster results on
19345 // Haswell than using vector integer multiplication.
19347 // For i32 elements:
19348 // v = v + (v >> 8)
19349 // v = v + (v >> 16)
19351 // For i64 elements:
19352 // v = v + (v >> 8)
19353 // v = v + (v >> 16)
19354 // v = v + (v >> 32)
19357 SmallVector<SDValue, 8> Csts;
19358 for (unsigned i = 8; i <= Len/2; i *= 2) {
19359 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19360 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19361 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19362 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19366 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19367 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19368 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19369 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19370 if (NeedsBitcast) {
19371 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19372 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19374 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19375 if (VT != And.getValueType())
19376 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19381 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19382 SDNode *Node = Op.getNode();
19384 EVT T = Node->getValueType(0);
19385 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19386 DAG.getConstant(0, T), Node->getOperand(2));
19387 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19388 cast<AtomicSDNode>(Node)->getMemoryVT(),
19389 Node->getOperand(0),
19390 Node->getOperand(1), negOp,
19391 cast<AtomicSDNode>(Node)->getMemOperand(),
19392 cast<AtomicSDNode>(Node)->getOrdering(),
19393 cast<AtomicSDNode>(Node)->getSynchScope());
19396 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19397 SDNode *Node = Op.getNode();
19399 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19401 // Convert seq_cst store -> xchg
19402 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19403 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19404 // (The only way to get a 16-byte store is cmpxchg16b)
19405 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19406 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19407 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19408 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19409 cast<AtomicSDNode>(Node)->getMemoryVT(),
19410 Node->getOperand(0),
19411 Node->getOperand(1), Node->getOperand(2),
19412 cast<AtomicSDNode>(Node)->getMemOperand(),
19413 cast<AtomicSDNode>(Node)->getOrdering(),
19414 cast<AtomicSDNode>(Node)->getSynchScope());
19415 return Swap.getValue(1);
19417 // Other atomic stores have a simple pattern.
19421 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19422 EVT VT = Op.getNode()->getSimpleValueType(0);
19424 // Let legalize expand this if it isn't a legal type yet.
19425 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19428 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19431 bool ExtraOp = false;
19432 switch (Op.getOpcode()) {
19433 default: llvm_unreachable("Invalid code");
19434 case ISD::ADDC: Opc = X86ISD::ADD; break;
19435 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19436 case ISD::SUBC: Opc = X86ISD::SUB; break;
19437 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19441 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19443 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19444 Op.getOperand(1), Op.getOperand(2));
19447 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19448 SelectionDAG &DAG) {
19449 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19451 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19452 // which returns the values as { float, float } (in XMM0) or
19453 // { double, double } (which is returned in XMM0, XMM1).
19455 SDValue Arg = Op.getOperand(0);
19456 EVT ArgVT = Arg.getValueType();
19457 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19459 TargetLowering::ArgListTy Args;
19460 TargetLowering::ArgListEntry Entry;
19464 Entry.isSExt = false;
19465 Entry.isZExt = false;
19466 Args.push_back(Entry);
19468 bool isF64 = ArgVT == MVT::f64;
19469 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19470 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19471 // the results are returned via SRet in memory.
19472 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19474 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19476 Type *RetTy = isF64
19477 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19478 : (Type*)VectorType::get(ArgTy, 4);
19480 TargetLowering::CallLoweringInfo CLI(DAG);
19481 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19482 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19484 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19487 // Returned in xmm0 and xmm1.
19488 return CallResult.first;
19490 // Returned in bits 0:31 and 32:64 xmm0.
19491 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19492 CallResult.first, DAG.getIntPtrConstant(0));
19493 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19494 CallResult.first, DAG.getIntPtrConstant(1));
19495 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19496 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19499 /// LowerOperation - Provide custom lowering hooks for some operations.
19501 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19502 switch (Op.getOpcode()) {
19503 default: llvm_unreachable("Should not custom lower this!");
19504 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19505 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19506 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19507 return LowerCMP_SWAP(Op, Subtarget, DAG);
19508 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19509 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19510 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19511 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19512 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19513 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19514 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19515 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19516 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19517 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19518 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19519 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19520 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19521 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19522 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19523 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19524 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19525 case ISD::SHL_PARTS:
19526 case ISD::SRA_PARTS:
19527 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19528 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19529 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19530 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19531 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19532 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19533 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19534 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19535 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19536 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19537 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19539 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19540 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19541 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19542 case ISD::SETCC: return LowerSETCC(Op, DAG);
19543 case ISD::SELECT: return LowerSELECT(Op, DAG);
19544 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19545 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19546 case ISD::VASTART: return LowerVASTART(Op, DAG);
19547 case ISD::VAARG: return LowerVAARG(Op, DAG);
19548 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19549 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19550 case ISD::INTRINSIC_VOID:
19551 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19552 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19553 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19554 case ISD::FRAME_TO_ARGS_OFFSET:
19555 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19556 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19557 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19558 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19559 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19560 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19561 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19562 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19563 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19564 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19565 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19566 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19567 case ISD::UMUL_LOHI:
19568 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19571 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19577 case ISD::UMULO: return LowerXALUO(Op, DAG);
19578 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19579 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19583 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19584 case ISD::ADD: return LowerADD(Op, DAG);
19585 case ISD::SUB: return LowerSUB(Op, DAG);
19586 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19590 /// ReplaceNodeResults - Replace a node with an illegal result type
19591 /// with a new node built out of custom code.
19592 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19593 SmallVectorImpl<SDValue>&Results,
19594 SelectionDAG &DAG) const {
19596 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19597 switch (N->getOpcode()) {
19599 llvm_unreachable("Do not know how to custom type legalize this operation!");
19600 case ISD::SIGN_EXTEND_INREG:
19605 // We don't want to expand or promote these.
19612 case ISD::UDIVREM: {
19613 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19614 Results.push_back(V);
19617 case ISD::FP_TO_SINT:
19618 case ISD::FP_TO_UINT: {
19619 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19621 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19624 std::pair<SDValue,SDValue> Vals =
19625 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19626 SDValue FIST = Vals.first, StackSlot = Vals.second;
19627 if (FIST.getNode()) {
19628 EVT VT = N->getValueType(0);
19629 // Return a load from the stack slot.
19630 if (StackSlot.getNode())
19631 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19632 MachinePointerInfo(),
19633 false, false, false, 0));
19635 Results.push_back(FIST);
19639 case ISD::UINT_TO_FP: {
19640 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19641 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19642 N->getValueType(0) != MVT::v2f32)
19644 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19646 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19648 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19649 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19650 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19651 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19652 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19653 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19656 case ISD::FP_ROUND: {
19657 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19659 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19660 Results.push_back(V);
19663 case ISD::INTRINSIC_W_CHAIN: {
19664 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19666 default : llvm_unreachable("Do not know how to custom type "
19667 "legalize this intrinsic operation!");
19668 case Intrinsic::x86_rdtsc:
19669 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19671 case Intrinsic::x86_rdtscp:
19672 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19674 case Intrinsic::x86_rdpmc:
19675 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19678 case ISD::READCYCLECOUNTER: {
19679 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19682 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19683 EVT T = N->getValueType(0);
19684 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19685 bool Regs64bit = T == MVT::i128;
19686 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19687 SDValue cpInL, cpInH;
19688 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19689 DAG.getConstant(0, HalfT));
19690 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19691 DAG.getConstant(1, HalfT));
19692 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19693 Regs64bit ? X86::RAX : X86::EAX,
19695 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19696 Regs64bit ? X86::RDX : X86::EDX,
19697 cpInH, cpInL.getValue(1));
19698 SDValue swapInL, swapInH;
19699 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19700 DAG.getConstant(0, HalfT));
19701 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19702 DAG.getConstant(1, HalfT));
19703 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19704 Regs64bit ? X86::RBX : X86::EBX,
19705 swapInL, cpInH.getValue(1));
19706 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19707 Regs64bit ? X86::RCX : X86::ECX,
19708 swapInH, swapInL.getValue(1));
19709 SDValue Ops[] = { swapInH.getValue(0),
19711 swapInH.getValue(1) };
19712 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19713 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19714 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19715 X86ISD::LCMPXCHG8_DAG;
19716 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19717 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19718 Regs64bit ? X86::RAX : X86::EAX,
19719 HalfT, Result.getValue(1));
19720 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19721 Regs64bit ? X86::RDX : X86::EDX,
19722 HalfT, cpOutL.getValue(2));
19723 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19725 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19726 MVT::i32, cpOutH.getValue(2));
19728 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19729 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19730 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19732 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19733 Results.push_back(Success);
19734 Results.push_back(EFLAGS.getValue(1));
19737 case ISD::ATOMIC_SWAP:
19738 case ISD::ATOMIC_LOAD_ADD:
19739 case ISD::ATOMIC_LOAD_SUB:
19740 case ISD::ATOMIC_LOAD_AND:
19741 case ISD::ATOMIC_LOAD_OR:
19742 case ISD::ATOMIC_LOAD_XOR:
19743 case ISD::ATOMIC_LOAD_NAND:
19744 case ISD::ATOMIC_LOAD_MIN:
19745 case ISD::ATOMIC_LOAD_MAX:
19746 case ISD::ATOMIC_LOAD_UMIN:
19747 case ISD::ATOMIC_LOAD_UMAX:
19748 case ISD::ATOMIC_LOAD: {
19749 // Delegate to generic TypeLegalization. Situations we can really handle
19750 // should have already been dealt with by AtomicExpandPass.cpp.
19753 case ISD::BITCAST: {
19754 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19755 EVT DstVT = N->getValueType(0);
19756 EVT SrcVT = N->getOperand(0)->getValueType(0);
19758 if (SrcVT != MVT::f64 ||
19759 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19762 unsigned NumElts = DstVT.getVectorNumElements();
19763 EVT SVT = DstVT.getVectorElementType();
19764 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19765 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19766 MVT::v2f64, N->getOperand(0));
19767 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19769 if (ExperimentalVectorWideningLegalization) {
19770 // If we are legalizing vectors by widening, we already have the desired
19771 // legal vector type, just return it.
19772 Results.push_back(ToVecInt);
19776 SmallVector<SDValue, 8> Elts;
19777 for (unsigned i = 0, e = NumElts; i != e; ++i)
19778 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19779 ToVecInt, DAG.getIntPtrConstant(i)));
19781 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19786 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19788 default: return nullptr;
19789 case X86ISD::BSF: return "X86ISD::BSF";
19790 case X86ISD::BSR: return "X86ISD::BSR";
19791 case X86ISD::SHLD: return "X86ISD::SHLD";
19792 case X86ISD::SHRD: return "X86ISD::SHRD";
19793 case X86ISD::FAND: return "X86ISD::FAND";
19794 case X86ISD::FANDN: return "X86ISD::FANDN";
19795 case X86ISD::FOR: return "X86ISD::FOR";
19796 case X86ISD::FXOR: return "X86ISD::FXOR";
19797 case X86ISD::FSRL: return "X86ISD::FSRL";
19798 case X86ISD::FILD: return "X86ISD::FILD";
19799 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19800 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19801 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19802 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19803 case X86ISD::FLD: return "X86ISD::FLD";
19804 case X86ISD::FST: return "X86ISD::FST";
19805 case X86ISD::CALL: return "X86ISD::CALL";
19806 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19807 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19808 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19809 case X86ISD::BT: return "X86ISD::BT";
19810 case X86ISD::CMP: return "X86ISD::CMP";
19811 case X86ISD::COMI: return "X86ISD::COMI";
19812 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19813 case X86ISD::CMPM: return "X86ISD::CMPM";
19814 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19815 case X86ISD::SETCC: return "X86ISD::SETCC";
19816 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19817 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19818 case X86ISD::CMOV: return "X86ISD::CMOV";
19819 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19820 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19821 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19822 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19823 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19824 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19825 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19826 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19827 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19828 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19829 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19830 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19831 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19832 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19833 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19834 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19835 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19836 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19837 case X86ISD::HADD: return "X86ISD::HADD";
19838 case X86ISD::HSUB: return "X86ISD::HSUB";
19839 case X86ISD::FHADD: return "X86ISD::FHADD";
19840 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19841 case X86ISD::UMAX: return "X86ISD::UMAX";
19842 case X86ISD::UMIN: return "X86ISD::UMIN";
19843 case X86ISD::SMAX: return "X86ISD::SMAX";
19844 case X86ISD::SMIN: return "X86ISD::SMIN";
19845 case X86ISD::FMAX: return "X86ISD::FMAX";
19846 case X86ISD::FMIN: return "X86ISD::FMIN";
19847 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19848 case X86ISD::FMINC: return "X86ISD::FMINC";
19849 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19850 case X86ISD::FRCP: return "X86ISD::FRCP";
19851 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19852 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19853 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19854 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19855 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19856 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19857 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19858 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19859 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19860 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19861 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19862 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19863 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19864 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19865 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19866 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19867 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19868 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19869 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19870 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19871 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19872 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19873 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19874 case X86ISD::VSHL: return "X86ISD::VSHL";
19875 case X86ISD::VSRL: return "X86ISD::VSRL";
19876 case X86ISD::VSRA: return "X86ISD::VSRA";
19877 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19878 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19879 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19880 case X86ISD::CMPP: return "X86ISD::CMPP";
19881 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19882 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19883 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19884 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19885 case X86ISD::ADD: return "X86ISD::ADD";
19886 case X86ISD::SUB: return "X86ISD::SUB";
19887 case X86ISD::ADC: return "X86ISD::ADC";
19888 case X86ISD::SBB: return "X86ISD::SBB";
19889 case X86ISD::SMUL: return "X86ISD::SMUL";
19890 case X86ISD::UMUL: return "X86ISD::UMUL";
19891 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19892 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19893 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19894 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19895 case X86ISD::INC: return "X86ISD::INC";
19896 case X86ISD::DEC: return "X86ISD::DEC";
19897 case X86ISD::OR: return "X86ISD::OR";
19898 case X86ISD::XOR: return "X86ISD::XOR";
19899 case X86ISD::AND: return "X86ISD::AND";
19900 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19901 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19902 case X86ISD::PTEST: return "X86ISD::PTEST";
19903 case X86ISD::TESTP: return "X86ISD::TESTP";
19904 case X86ISD::TESTM: return "X86ISD::TESTM";
19905 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19906 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19907 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19908 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19909 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19910 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19911 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19912 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19913 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19914 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19915 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19916 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19917 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19918 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19919 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19920 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19921 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19922 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19923 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19924 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19925 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19926 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19927 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19928 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19929 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19930 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19931 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19932 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19933 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19934 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19935 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19936 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19937 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19938 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19939 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19940 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19941 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19942 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19943 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19944 case X86ISD::SAHF: return "X86ISD::SAHF";
19945 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19946 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19947 case X86ISD::FMADD: return "X86ISD::FMADD";
19948 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19949 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19950 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19951 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19952 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19953 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19954 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19955 case X86ISD::XTEST: return "X86ISD::XTEST";
19956 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19957 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19958 case X86ISD::SELECT: return "X86ISD::SELECT";
19962 // isLegalAddressingMode - Return true if the addressing mode represented
19963 // by AM is legal for this target, for a load/store of the specified type.
19964 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19966 // X86 supports extremely general addressing modes.
19967 CodeModel::Model M = getTargetMachine().getCodeModel();
19968 Reloc::Model R = getTargetMachine().getRelocationModel();
19970 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19971 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19976 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19978 // If a reference to this global requires an extra load, we can't fold it.
19979 if (isGlobalStubReference(GVFlags))
19982 // If BaseGV requires a register for the PIC base, we cannot also have a
19983 // BaseReg specified.
19984 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19987 // If lower 4G is not available, then we must use rip-relative addressing.
19988 if ((M != CodeModel::Small || R != Reloc::Static) &&
19989 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19993 switch (AM.Scale) {
19999 // These scales always work.
20004 // These scales are formed with basereg+scalereg. Only accept if there is
20009 default: // Other stuff never works.
20016 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20017 unsigned Bits = Ty->getScalarSizeInBits();
20019 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20020 // particularly cheaper than those without.
20024 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20025 // variable shifts just as cheap as scalar ones.
20026 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20029 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20030 // fully general vector.
20034 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20035 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20037 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20038 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20039 return NumBits1 > NumBits2;
20042 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20043 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20046 if (!isTypeLegal(EVT::getEVT(Ty1)))
20049 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20051 // Assuming the caller doesn't have a zeroext or signext return parameter,
20052 // truncation all the way down to i1 is valid.
20056 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20057 return isInt<32>(Imm);
20060 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20061 // Can also use sub to handle negated immediates.
20062 return isInt<32>(Imm);
20065 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20066 if (!VT1.isInteger() || !VT2.isInteger())
20068 unsigned NumBits1 = VT1.getSizeInBits();
20069 unsigned NumBits2 = VT2.getSizeInBits();
20070 return NumBits1 > NumBits2;
20073 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20074 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20075 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20078 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20079 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20080 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20083 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20084 EVT VT1 = Val.getValueType();
20085 if (isZExtFree(VT1, VT2))
20088 if (Val.getOpcode() != ISD::LOAD)
20091 if (!VT1.isSimple() || !VT1.isInteger() ||
20092 !VT2.isSimple() || !VT2.isInteger())
20095 switch (VT1.getSimpleVT().SimpleTy) {
20100 // X86 has 8, 16, and 32-bit zero-extending loads.
20108 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20109 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20112 VT = VT.getScalarType();
20114 if (!VT.isSimple())
20117 switch (VT.getSimpleVT().SimpleTy) {
20128 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20129 // i16 instructions are longer (0x66 prefix) and potentially slower.
20130 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20133 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20134 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20135 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20136 /// are assumed to be legal.
20138 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20140 if (!VT.isSimple())
20143 MVT SVT = VT.getSimpleVT();
20145 // Very little shuffling can be done for 64-bit vectors right now.
20146 if (VT.getSizeInBits() == 64)
20149 // If this is a single-input shuffle with no 128 bit lane crossings we can
20150 // lower it into pshufb.
20151 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20152 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20153 bool isLegal = true;
20154 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20155 if (M[I] >= (int)SVT.getVectorNumElements() ||
20156 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20165 // FIXME: blends, shifts.
20166 return (SVT.getVectorNumElements() == 2 ||
20167 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20168 isMOVLMask(M, SVT) ||
20169 isCommutedMOVLMask(M, SVT) ||
20170 isMOVHLPSMask(M, SVT) ||
20171 isSHUFPMask(M, SVT) ||
20172 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20173 isPSHUFDMask(M, SVT) ||
20174 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20175 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20176 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20177 isPALIGNRMask(M, SVT, Subtarget) ||
20178 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20179 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20180 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20181 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20182 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20183 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20187 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20189 if (!VT.isSimple())
20192 MVT SVT = VT.getSimpleVT();
20193 unsigned NumElts = SVT.getVectorNumElements();
20194 // FIXME: This collection of masks seems suspect.
20197 if (NumElts == 4 && SVT.is128BitVector()) {
20198 return (isMOVLMask(Mask, SVT) ||
20199 isCommutedMOVLMask(Mask, SVT, true) ||
20200 isSHUFPMask(Mask, SVT) ||
20201 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20202 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20203 Subtarget->hasInt256()));
20208 //===----------------------------------------------------------------------===//
20209 // X86 Scheduler Hooks
20210 //===----------------------------------------------------------------------===//
20212 /// Utility function to emit xbegin specifying the start of an RTM region.
20213 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20214 const TargetInstrInfo *TII) {
20215 DebugLoc DL = MI->getDebugLoc();
20217 const BasicBlock *BB = MBB->getBasicBlock();
20218 MachineFunction::iterator I = MBB;
20221 // For the v = xbegin(), we generate
20232 MachineBasicBlock *thisMBB = MBB;
20233 MachineFunction *MF = MBB->getParent();
20234 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20235 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20236 MF->insert(I, mainMBB);
20237 MF->insert(I, sinkMBB);
20239 // Transfer the remainder of BB and its successor edges to sinkMBB.
20240 sinkMBB->splice(sinkMBB->begin(), MBB,
20241 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20242 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20246 // # fallthrough to mainMBB
20247 // # abortion to sinkMBB
20248 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20249 thisMBB->addSuccessor(mainMBB);
20250 thisMBB->addSuccessor(sinkMBB);
20254 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20255 mainMBB->addSuccessor(sinkMBB);
20258 // EAX is live into the sinkMBB
20259 sinkMBB->addLiveIn(X86::EAX);
20260 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20261 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20264 MI->eraseFromParent();
20268 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20269 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20270 // in the .td file.
20271 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20272 const TargetInstrInfo *TII) {
20274 switch (MI->getOpcode()) {
20275 default: llvm_unreachable("illegal opcode!");
20276 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20277 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20278 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20279 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20280 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20281 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20282 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20283 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20286 DebugLoc dl = MI->getDebugLoc();
20287 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20289 unsigned NumArgs = MI->getNumOperands();
20290 for (unsigned i = 1; i < NumArgs; ++i) {
20291 MachineOperand &Op = MI->getOperand(i);
20292 if (!(Op.isReg() && Op.isImplicit()))
20293 MIB.addOperand(Op);
20295 if (MI->hasOneMemOperand())
20296 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20298 BuildMI(*BB, MI, dl,
20299 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20300 .addReg(X86::XMM0);
20302 MI->eraseFromParent();
20306 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20307 // defs in an instruction pattern
20308 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20309 const TargetInstrInfo *TII) {
20311 switch (MI->getOpcode()) {
20312 default: llvm_unreachable("illegal opcode!");
20313 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20314 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20315 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20316 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20317 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20318 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20319 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20320 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20323 DebugLoc dl = MI->getDebugLoc();
20324 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20326 unsigned NumArgs = MI->getNumOperands(); // remove the results
20327 for (unsigned i = 1; i < NumArgs; ++i) {
20328 MachineOperand &Op = MI->getOperand(i);
20329 if (!(Op.isReg() && Op.isImplicit()))
20330 MIB.addOperand(Op);
20332 if (MI->hasOneMemOperand())
20333 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20335 BuildMI(*BB, MI, dl,
20336 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20339 MI->eraseFromParent();
20343 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20344 const TargetInstrInfo *TII,
20345 const X86Subtarget* Subtarget) {
20346 DebugLoc dl = MI->getDebugLoc();
20348 // Address into RAX/EAX, other two args into ECX, EDX.
20349 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20350 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20351 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20352 for (int i = 0; i < X86::AddrNumOperands; ++i)
20353 MIB.addOperand(MI->getOperand(i));
20355 unsigned ValOps = X86::AddrNumOperands;
20356 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20357 .addReg(MI->getOperand(ValOps).getReg());
20358 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20359 .addReg(MI->getOperand(ValOps+1).getReg());
20361 // The instruction doesn't actually take any operands though.
20362 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20364 MI->eraseFromParent(); // The pseudo is gone now.
20368 MachineBasicBlock *
20369 X86TargetLowering::EmitVAARG64WithCustomInserter(
20371 MachineBasicBlock *MBB) const {
20372 // Emit va_arg instruction on X86-64.
20374 // Operands to this pseudo-instruction:
20375 // 0 ) Output : destination address (reg)
20376 // 1-5) Input : va_list address (addr, i64mem)
20377 // 6 ) ArgSize : Size (in bytes) of vararg type
20378 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20379 // 8 ) Align : Alignment of type
20380 // 9 ) EFLAGS (implicit-def)
20382 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20383 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20385 unsigned DestReg = MI->getOperand(0).getReg();
20386 MachineOperand &Base = MI->getOperand(1);
20387 MachineOperand &Scale = MI->getOperand(2);
20388 MachineOperand &Index = MI->getOperand(3);
20389 MachineOperand &Disp = MI->getOperand(4);
20390 MachineOperand &Segment = MI->getOperand(5);
20391 unsigned ArgSize = MI->getOperand(6).getImm();
20392 unsigned ArgMode = MI->getOperand(7).getImm();
20393 unsigned Align = MI->getOperand(8).getImm();
20395 // Memory Reference
20396 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20397 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20398 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20400 // Machine Information
20401 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20402 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20403 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20404 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20405 DebugLoc DL = MI->getDebugLoc();
20407 // struct va_list {
20410 // i64 overflow_area (address)
20411 // i64 reg_save_area (address)
20413 // sizeof(va_list) = 24
20414 // alignment(va_list) = 8
20416 unsigned TotalNumIntRegs = 6;
20417 unsigned TotalNumXMMRegs = 8;
20418 bool UseGPOffset = (ArgMode == 1);
20419 bool UseFPOffset = (ArgMode == 2);
20420 unsigned MaxOffset = TotalNumIntRegs * 8 +
20421 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20423 /* Align ArgSize to a multiple of 8 */
20424 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20425 bool NeedsAlign = (Align > 8);
20427 MachineBasicBlock *thisMBB = MBB;
20428 MachineBasicBlock *overflowMBB;
20429 MachineBasicBlock *offsetMBB;
20430 MachineBasicBlock *endMBB;
20432 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20433 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20434 unsigned OffsetReg = 0;
20436 if (!UseGPOffset && !UseFPOffset) {
20437 // If we only pull from the overflow region, we don't create a branch.
20438 // We don't need to alter control flow.
20439 OffsetDestReg = 0; // unused
20440 OverflowDestReg = DestReg;
20442 offsetMBB = nullptr;
20443 overflowMBB = thisMBB;
20446 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20447 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20448 // If not, pull from overflow_area. (branch to overflowMBB)
20453 // offsetMBB overflowMBB
20458 // Registers for the PHI in endMBB
20459 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20460 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20462 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20463 MachineFunction *MF = MBB->getParent();
20464 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20465 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20466 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20468 MachineFunction::iterator MBBIter = MBB;
20471 // Insert the new basic blocks
20472 MF->insert(MBBIter, offsetMBB);
20473 MF->insert(MBBIter, overflowMBB);
20474 MF->insert(MBBIter, endMBB);
20476 // Transfer the remainder of MBB and its successor edges to endMBB.
20477 endMBB->splice(endMBB->begin(), thisMBB,
20478 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20479 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20481 // Make offsetMBB and overflowMBB successors of thisMBB
20482 thisMBB->addSuccessor(offsetMBB);
20483 thisMBB->addSuccessor(overflowMBB);
20485 // endMBB is a successor of both offsetMBB and overflowMBB
20486 offsetMBB->addSuccessor(endMBB);
20487 overflowMBB->addSuccessor(endMBB);
20489 // Load the offset value into a register
20490 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20491 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20495 .addDisp(Disp, UseFPOffset ? 4 : 0)
20496 .addOperand(Segment)
20497 .setMemRefs(MMOBegin, MMOEnd);
20499 // Check if there is enough room left to pull this argument.
20500 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20502 .addImm(MaxOffset + 8 - ArgSizeA8);
20504 // Branch to "overflowMBB" if offset >= max
20505 // Fall through to "offsetMBB" otherwise
20506 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20507 .addMBB(overflowMBB);
20510 // In offsetMBB, emit code to use the reg_save_area.
20512 assert(OffsetReg != 0);
20514 // Read the reg_save_area address.
20515 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20516 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20521 .addOperand(Segment)
20522 .setMemRefs(MMOBegin, MMOEnd);
20524 // Zero-extend the offset
20525 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20526 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20529 .addImm(X86::sub_32bit);
20531 // Add the offset to the reg_save_area to get the final address.
20532 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20533 .addReg(OffsetReg64)
20534 .addReg(RegSaveReg);
20536 // Compute the offset for the next argument
20537 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20538 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20540 .addImm(UseFPOffset ? 16 : 8);
20542 // Store it back into the va_list.
20543 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20547 .addDisp(Disp, UseFPOffset ? 4 : 0)
20548 .addOperand(Segment)
20549 .addReg(NextOffsetReg)
20550 .setMemRefs(MMOBegin, MMOEnd);
20553 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20558 // Emit code to use overflow area
20561 // Load the overflow_area address into a register.
20562 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20563 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20568 .addOperand(Segment)
20569 .setMemRefs(MMOBegin, MMOEnd);
20571 // If we need to align it, do so. Otherwise, just copy the address
20572 // to OverflowDestReg.
20574 // Align the overflow address
20575 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20576 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20578 // aligned_addr = (addr + (align-1)) & ~(align-1)
20579 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20580 .addReg(OverflowAddrReg)
20583 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20585 .addImm(~(uint64_t)(Align-1));
20587 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20588 .addReg(OverflowAddrReg);
20591 // Compute the next overflow address after this argument.
20592 // (the overflow address should be kept 8-byte aligned)
20593 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20594 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20595 .addReg(OverflowDestReg)
20596 .addImm(ArgSizeA8);
20598 // Store the new overflow address.
20599 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20604 .addOperand(Segment)
20605 .addReg(NextAddrReg)
20606 .setMemRefs(MMOBegin, MMOEnd);
20608 // If we branched, emit the PHI to the front of endMBB.
20610 BuildMI(*endMBB, endMBB->begin(), DL,
20611 TII->get(X86::PHI), DestReg)
20612 .addReg(OffsetDestReg).addMBB(offsetMBB)
20613 .addReg(OverflowDestReg).addMBB(overflowMBB);
20616 // Erase the pseudo instruction
20617 MI->eraseFromParent();
20622 MachineBasicBlock *
20623 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20625 MachineBasicBlock *MBB) const {
20626 // Emit code to save XMM registers to the stack. The ABI says that the
20627 // number of registers to save is given in %al, so it's theoretically
20628 // possible to do an indirect jump trick to avoid saving all of them,
20629 // however this code takes a simpler approach and just executes all
20630 // of the stores if %al is non-zero. It's less code, and it's probably
20631 // easier on the hardware branch predictor, and stores aren't all that
20632 // expensive anyway.
20634 // Create the new basic blocks. One block contains all the XMM stores,
20635 // and one block is the final destination regardless of whether any
20636 // stores were performed.
20637 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20638 MachineFunction *F = MBB->getParent();
20639 MachineFunction::iterator MBBIter = MBB;
20641 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20642 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20643 F->insert(MBBIter, XMMSaveMBB);
20644 F->insert(MBBIter, EndMBB);
20646 // Transfer the remainder of MBB and its successor edges to EndMBB.
20647 EndMBB->splice(EndMBB->begin(), MBB,
20648 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20649 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20651 // The original block will now fall through to the XMM save block.
20652 MBB->addSuccessor(XMMSaveMBB);
20653 // The XMMSaveMBB will fall through to the end block.
20654 XMMSaveMBB->addSuccessor(EndMBB);
20656 // Now add the instructions.
20657 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20658 DebugLoc DL = MI->getDebugLoc();
20660 unsigned CountReg = MI->getOperand(0).getReg();
20661 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20662 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20664 if (!Subtarget->isTargetWin64()) {
20665 // If %al is 0, branch around the XMM save block.
20666 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20667 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20668 MBB->addSuccessor(EndMBB);
20671 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20672 // that was just emitted, but clearly shouldn't be "saved".
20673 assert((MI->getNumOperands() <= 3 ||
20674 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20675 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20676 && "Expected last argument to be EFLAGS");
20677 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20678 // In the XMM save block, save all the XMM argument registers.
20679 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20680 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20681 MachineMemOperand *MMO =
20682 F->getMachineMemOperand(
20683 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20684 MachineMemOperand::MOStore,
20685 /*Size=*/16, /*Align=*/16);
20686 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20687 .addFrameIndex(RegSaveFrameIndex)
20688 .addImm(/*Scale=*/1)
20689 .addReg(/*IndexReg=*/0)
20690 .addImm(/*Disp=*/Offset)
20691 .addReg(/*Segment=*/0)
20692 .addReg(MI->getOperand(i).getReg())
20693 .addMemOperand(MMO);
20696 MI->eraseFromParent(); // The pseudo instruction is gone now.
20701 // The EFLAGS operand of SelectItr might be missing a kill marker
20702 // because there were multiple uses of EFLAGS, and ISel didn't know
20703 // which to mark. Figure out whether SelectItr should have had a
20704 // kill marker, and set it if it should. Returns the correct kill
20706 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20707 MachineBasicBlock* BB,
20708 const TargetRegisterInfo* TRI) {
20709 // Scan forward through BB for a use/def of EFLAGS.
20710 MachineBasicBlock::iterator miI(std::next(SelectItr));
20711 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20712 const MachineInstr& mi = *miI;
20713 if (mi.readsRegister(X86::EFLAGS))
20715 if (mi.definesRegister(X86::EFLAGS))
20716 break; // Should have kill-flag - update below.
20719 // If we hit the end of the block, check whether EFLAGS is live into a
20721 if (miI == BB->end()) {
20722 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20723 sEnd = BB->succ_end();
20724 sItr != sEnd; ++sItr) {
20725 MachineBasicBlock* succ = *sItr;
20726 if (succ->isLiveIn(X86::EFLAGS))
20731 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20732 // out. SelectMI should have a kill flag on EFLAGS.
20733 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20737 MachineBasicBlock *
20738 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20739 MachineBasicBlock *BB) const {
20740 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20741 DebugLoc DL = MI->getDebugLoc();
20743 // To "insert" a SELECT_CC instruction, we actually have to insert the
20744 // diamond control-flow pattern. The incoming instruction knows the
20745 // destination vreg to set, the condition code register to branch on, the
20746 // true/false values to select between, and a branch opcode to use.
20747 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20748 MachineFunction::iterator It = BB;
20754 // cmpTY ccX, r1, r2
20756 // fallthrough --> copy0MBB
20757 MachineBasicBlock *thisMBB = BB;
20758 MachineFunction *F = BB->getParent();
20759 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20760 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20761 F->insert(It, copy0MBB);
20762 F->insert(It, sinkMBB);
20764 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20765 // live into the sink and copy blocks.
20766 const TargetRegisterInfo *TRI =
20767 BB->getParent()->getSubtarget().getRegisterInfo();
20768 if (!MI->killsRegister(X86::EFLAGS) &&
20769 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20770 copy0MBB->addLiveIn(X86::EFLAGS);
20771 sinkMBB->addLiveIn(X86::EFLAGS);
20774 // Transfer the remainder of BB and its successor edges to sinkMBB.
20775 sinkMBB->splice(sinkMBB->begin(), BB,
20776 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20777 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20779 // Add the true and fallthrough blocks as its successors.
20780 BB->addSuccessor(copy0MBB);
20781 BB->addSuccessor(sinkMBB);
20783 // Create the conditional branch instruction.
20785 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20786 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20789 // %FalseValue = ...
20790 // # fallthrough to sinkMBB
20791 copy0MBB->addSuccessor(sinkMBB);
20794 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20796 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20797 TII->get(X86::PHI), MI->getOperand(0).getReg())
20798 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20799 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20801 MI->eraseFromParent(); // The pseudo instruction is gone now.
20805 MachineBasicBlock *
20806 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20807 MachineBasicBlock *BB) const {
20808 MachineFunction *MF = BB->getParent();
20809 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20810 DebugLoc DL = MI->getDebugLoc();
20811 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20813 assert(MF->shouldSplitStack());
20815 const bool Is64Bit = Subtarget->is64Bit();
20816 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20818 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20819 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20822 // ... [Till the alloca]
20823 // If stacklet is not large enough, jump to mallocMBB
20826 // Allocate by subtracting from RSP
20827 // Jump to continueMBB
20830 // Allocate by call to runtime
20834 // [rest of original BB]
20837 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20838 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20839 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20841 MachineRegisterInfo &MRI = MF->getRegInfo();
20842 const TargetRegisterClass *AddrRegClass =
20843 getRegClassFor(getPointerTy());
20845 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20846 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20847 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20848 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20849 sizeVReg = MI->getOperand(1).getReg(),
20850 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20852 MachineFunction::iterator MBBIter = BB;
20855 MF->insert(MBBIter, bumpMBB);
20856 MF->insert(MBBIter, mallocMBB);
20857 MF->insert(MBBIter, continueMBB);
20859 continueMBB->splice(continueMBB->begin(), BB,
20860 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20861 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20863 // Add code to the main basic block to check if the stack limit has been hit,
20864 // and if so, jump to mallocMBB otherwise to bumpMBB.
20865 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20866 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20867 .addReg(tmpSPVReg).addReg(sizeVReg);
20868 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20869 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20870 .addReg(SPLimitVReg);
20871 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20873 // bumpMBB simply decreases the stack pointer, since we know the current
20874 // stacklet has enough space.
20875 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20876 .addReg(SPLimitVReg);
20877 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20878 .addReg(SPLimitVReg);
20879 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20881 // Calls into a routine in libgcc to allocate more space from the heap.
20882 const uint32_t *RegMask = MF->getTarget()
20883 .getSubtargetImpl()
20884 ->getRegisterInfo()
20885 ->getCallPreservedMask(CallingConv::C);
20887 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20889 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20890 .addExternalSymbol("__morestack_allocate_stack_space")
20891 .addRegMask(RegMask)
20892 .addReg(X86::RDI, RegState::Implicit)
20893 .addReg(X86::RAX, RegState::ImplicitDefine);
20894 } else if (Is64Bit) {
20895 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20897 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20898 .addExternalSymbol("__morestack_allocate_stack_space")
20899 .addRegMask(RegMask)
20900 .addReg(X86::EDI, RegState::Implicit)
20901 .addReg(X86::EAX, RegState::ImplicitDefine);
20903 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20905 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20906 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20907 .addExternalSymbol("__morestack_allocate_stack_space")
20908 .addRegMask(RegMask)
20909 .addReg(X86::EAX, RegState::ImplicitDefine);
20913 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20916 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20917 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20918 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20920 // Set up the CFG correctly.
20921 BB->addSuccessor(bumpMBB);
20922 BB->addSuccessor(mallocMBB);
20923 mallocMBB->addSuccessor(continueMBB);
20924 bumpMBB->addSuccessor(continueMBB);
20926 // Take care of the PHI nodes.
20927 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20928 MI->getOperand(0).getReg())
20929 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20930 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20932 // Delete the original pseudo instruction.
20933 MI->eraseFromParent();
20936 return continueMBB;
20939 MachineBasicBlock *
20940 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20941 MachineBasicBlock *BB) const {
20942 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20943 DebugLoc DL = MI->getDebugLoc();
20945 assert(!Subtarget->isTargetMachO());
20947 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20948 // non-trivial part is impdef of ESP.
20950 if (Subtarget->isTargetWin64()) {
20951 if (Subtarget->isTargetCygMing()) {
20952 // ___chkstk(Mingw64):
20953 // Clobbers R10, R11, RAX and EFLAGS.
20955 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20956 .addExternalSymbol("___chkstk")
20957 .addReg(X86::RAX, RegState::Implicit)
20958 .addReg(X86::RSP, RegState::Implicit)
20959 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20960 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20961 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20963 // __chkstk(MSVCRT): does not update stack pointer.
20964 // Clobbers R10, R11 and EFLAGS.
20965 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20966 .addExternalSymbol("__chkstk")
20967 .addReg(X86::RAX, RegState::Implicit)
20968 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20969 // RAX has the offset to be subtracted from RSP.
20970 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20975 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20976 Subtarget->isTargetWindowsItanium())
20980 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20981 .addExternalSymbol(StackProbeSymbol)
20982 .addReg(X86::EAX, RegState::Implicit)
20983 .addReg(X86::ESP, RegState::Implicit)
20984 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20985 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20986 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20989 MI->eraseFromParent(); // The pseudo instruction is gone now.
20993 MachineBasicBlock *
20994 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20995 MachineBasicBlock *BB) const {
20996 // This is pretty easy. We're taking the value that we received from
20997 // our load from the relocation, sticking it in either RDI (x86-64)
20998 // or EAX and doing an indirect call. The return value will then
20999 // be in the normal return register.
21000 MachineFunction *F = BB->getParent();
21001 const X86InstrInfo *TII =
21002 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
21003 DebugLoc DL = MI->getDebugLoc();
21005 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21006 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21008 // Get a register mask for the lowered call.
21009 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21010 // proper register mask.
21011 const uint32_t *RegMask = F->getTarget()
21012 .getSubtargetImpl()
21013 ->getRegisterInfo()
21014 ->getCallPreservedMask(CallingConv::C);
21015 if (Subtarget->is64Bit()) {
21016 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21017 TII->get(X86::MOV64rm), X86::RDI)
21019 .addImm(0).addReg(0)
21020 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21021 MI->getOperand(3).getTargetFlags())
21023 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21024 addDirectMem(MIB, X86::RDI);
21025 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21026 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21027 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21028 TII->get(X86::MOV32rm), X86::EAX)
21030 .addImm(0).addReg(0)
21031 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21032 MI->getOperand(3).getTargetFlags())
21034 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21035 addDirectMem(MIB, X86::EAX);
21036 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21038 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21039 TII->get(X86::MOV32rm), X86::EAX)
21040 .addReg(TII->getGlobalBaseReg(F))
21041 .addImm(0).addReg(0)
21042 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21043 MI->getOperand(3).getTargetFlags())
21045 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21046 addDirectMem(MIB, X86::EAX);
21047 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21050 MI->eraseFromParent(); // The pseudo instruction is gone now.
21054 MachineBasicBlock *
21055 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21056 MachineBasicBlock *MBB) const {
21057 DebugLoc DL = MI->getDebugLoc();
21058 MachineFunction *MF = MBB->getParent();
21059 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21060 MachineRegisterInfo &MRI = MF->getRegInfo();
21062 const BasicBlock *BB = MBB->getBasicBlock();
21063 MachineFunction::iterator I = MBB;
21066 // Memory Reference
21067 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21068 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21071 unsigned MemOpndSlot = 0;
21073 unsigned CurOp = 0;
21075 DstReg = MI->getOperand(CurOp++).getReg();
21076 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21077 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21078 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21079 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21081 MemOpndSlot = CurOp;
21083 MVT PVT = getPointerTy();
21084 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21085 "Invalid Pointer Size!");
21087 // For v = setjmp(buf), we generate
21090 // buf[LabelOffset] = restoreMBB
21091 // SjLjSetup restoreMBB
21097 // v = phi(main, restore)
21100 // if base pointer being used, load it from frame
21103 MachineBasicBlock *thisMBB = MBB;
21104 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21105 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21106 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21107 MF->insert(I, mainMBB);
21108 MF->insert(I, sinkMBB);
21109 MF->push_back(restoreMBB);
21111 MachineInstrBuilder MIB;
21113 // Transfer the remainder of BB and its successor edges to sinkMBB.
21114 sinkMBB->splice(sinkMBB->begin(), MBB,
21115 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21116 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21119 unsigned PtrStoreOpc = 0;
21120 unsigned LabelReg = 0;
21121 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21122 Reloc::Model RM = MF->getTarget().getRelocationModel();
21123 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21124 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21126 // Prepare IP either in reg or imm.
21127 if (!UseImmLabel) {
21128 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21129 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21130 LabelReg = MRI.createVirtualRegister(PtrRC);
21131 if (Subtarget->is64Bit()) {
21132 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21136 .addMBB(restoreMBB)
21139 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21140 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21141 .addReg(XII->getGlobalBaseReg(MF))
21144 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21148 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21150 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21151 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21152 if (i == X86::AddrDisp)
21153 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21155 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21158 MIB.addReg(LabelReg);
21160 MIB.addMBB(restoreMBB);
21161 MIB.setMemRefs(MMOBegin, MMOEnd);
21163 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21164 .addMBB(restoreMBB);
21166 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21167 MF->getSubtarget().getRegisterInfo());
21168 MIB.addRegMask(RegInfo->getNoPreservedMask());
21169 thisMBB->addSuccessor(mainMBB);
21170 thisMBB->addSuccessor(restoreMBB);
21174 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21175 mainMBB->addSuccessor(sinkMBB);
21178 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21179 TII->get(X86::PHI), DstReg)
21180 .addReg(mainDstReg).addMBB(mainMBB)
21181 .addReg(restoreDstReg).addMBB(restoreMBB);
21184 if (RegInfo->hasBasePointer(*MF)) {
21185 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21186 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21187 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21188 X86FI->setRestoreBasePointer(MF);
21189 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21190 unsigned BasePtr = RegInfo->getBaseRegister();
21191 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21192 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21193 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21194 .setMIFlag(MachineInstr::FrameSetup);
21196 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21197 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21198 restoreMBB->addSuccessor(sinkMBB);
21200 MI->eraseFromParent();
21204 MachineBasicBlock *
21205 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21206 MachineBasicBlock *MBB) const {
21207 DebugLoc DL = MI->getDebugLoc();
21208 MachineFunction *MF = MBB->getParent();
21209 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21210 MachineRegisterInfo &MRI = MF->getRegInfo();
21212 // Memory Reference
21213 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21214 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21216 MVT PVT = getPointerTy();
21217 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21218 "Invalid Pointer Size!");
21220 const TargetRegisterClass *RC =
21221 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21222 unsigned Tmp = MRI.createVirtualRegister(RC);
21223 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21224 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21225 MF->getSubtarget().getRegisterInfo());
21226 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21227 unsigned SP = RegInfo->getStackRegister();
21229 MachineInstrBuilder MIB;
21231 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21232 const int64_t SPOffset = 2 * PVT.getStoreSize();
21234 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21235 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21238 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21239 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21240 MIB.addOperand(MI->getOperand(i));
21241 MIB.setMemRefs(MMOBegin, MMOEnd);
21243 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21244 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21245 if (i == X86::AddrDisp)
21246 MIB.addDisp(MI->getOperand(i), LabelOffset);
21248 MIB.addOperand(MI->getOperand(i));
21250 MIB.setMemRefs(MMOBegin, MMOEnd);
21252 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21253 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21254 if (i == X86::AddrDisp)
21255 MIB.addDisp(MI->getOperand(i), SPOffset);
21257 MIB.addOperand(MI->getOperand(i));
21259 MIB.setMemRefs(MMOBegin, MMOEnd);
21261 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21263 MI->eraseFromParent();
21267 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21268 // accumulator loops. Writing back to the accumulator allows the coalescer
21269 // to remove extra copies in the loop.
21270 MachineBasicBlock *
21271 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21272 MachineBasicBlock *MBB) const {
21273 MachineOperand &AddendOp = MI->getOperand(3);
21275 // Bail out early if the addend isn't a register - we can't switch these.
21276 if (!AddendOp.isReg())
21279 MachineFunction &MF = *MBB->getParent();
21280 MachineRegisterInfo &MRI = MF.getRegInfo();
21282 // Check whether the addend is defined by a PHI:
21283 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21284 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21285 if (!AddendDef.isPHI())
21288 // Look for the following pattern:
21290 // %addend = phi [%entry, 0], [%loop, %result]
21292 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21296 // %addend = phi [%entry, 0], [%loop, %result]
21298 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21300 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21301 assert(AddendDef.getOperand(i).isReg());
21302 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21303 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21304 if (&PHISrcInst == MI) {
21305 // Found a matching instruction.
21306 unsigned NewFMAOpc = 0;
21307 switch (MI->getOpcode()) {
21308 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21309 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21310 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21311 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21312 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21313 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21314 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21315 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21316 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21317 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21318 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21319 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21320 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21321 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21322 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21323 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21324 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21325 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21326 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21327 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21329 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21330 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21331 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21332 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21333 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21334 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21335 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21336 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21337 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21338 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21339 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21340 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21341 default: llvm_unreachable("Unrecognized FMA variant.");
21344 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21345 MachineInstrBuilder MIB =
21346 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21347 .addOperand(MI->getOperand(0))
21348 .addOperand(MI->getOperand(3))
21349 .addOperand(MI->getOperand(2))
21350 .addOperand(MI->getOperand(1));
21351 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21352 MI->eraseFromParent();
21359 MachineBasicBlock *
21360 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21361 MachineBasicBlock *BB) const {
21362 switch (MI->getOpcode()) {
21363 default: llvm_unreachable("Unexpected instr type to insert");
21364 case X86::TAILJMPd64:
21365 case X86::TAILJMPr64:
21366 case X86::TAILJMPm64:
21367 llvm_unreachable("TAILJMP64 would not be touched here.");
21368 case X86::TCRETURNdi64:
21369 case X86::TCRETURNri64:
21370 case X86::TCRETURNmi64:
21372 case X86::WIN_ALLOCA:
21373 return EmitLoweredWinAlloca(MI, BB);
21374 case X86::SEG_ALLOCA_32:
21375 case X86::SEG_ALLOCA_64:
21376 return EmitLoweredSegAlloca(MI, BB);
21377 case X86::TLSCall_32:
21378 case X86::TLSCall_64:
21379 return EmitLoweredTLSCall(MI, BB);
21380 case X86::CMOV_GR8:
21381 case X86::CMOV_FR32:
21382 case X86::CMOV_FR64:
21383 case X86::CMOV_V4F32:
21384 case X86::CMOV_V2F64:
21385 case X86::CMOV_V2I64:
21386 case X86::CMOV_V8F32:
21387 case X86::CMOV_V4F64:
21388 case X86::CMOV_V4I64:
21389 case X86::CMOV_V16F32:
21390 case X86::CMOV_V8F64:
21391 case X86::CMOV_V8I64:
21392 case X86::CMOV_GR16:
21393 case X86::CMOV_GR32:
21394 case X86::CMOV_RFP32:
21395 case X86::CMOV_RFP64:
21396 case X86::CMOV_RFP80:
21397 return EmitLoweredSelect(MI, BB);
21399 case X86::FP32_TO_INT16_IN_MEM:
21400 case X86::FP32_TO_INT32_IN_MEM:
21401 case X86::FP32_TO_INT64_IN_MEM:
21402 case X86::FP64_TO_INT16_IN_MEM:
21403 case X86::FP64_TO_INT32_IN_MEM:
21404 case X86::FP64_TO_INT64_IN_MEM:
21405 case X86::FP80_TO_INT16_IN_MEM:
21406 case X86::FP80_TO_INT32_IN_MEM:
21407 case X86::FP80_TO_INT64_IN_MEM: {
21408 MachineFunction *F = BB->getParent();
21409 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21410 DebugLoc DL = MI->getDebugLoc();
21412 // Change the floating point control register to use "round towards zero"
21413 // mode when truncating to an integer value.
21414 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21415 addFrameReference(BuildMI(*BB, MI, DL,
21416 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21418 // Load the old value of the high byte of the control word...
21420 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21421 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21424 // Set the high part to be round to zero...
21425 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21428 // Reload the modified control word now...
21429 addFrameReference(BuildMI(*BB, MI, DL,
21430 TII->get(X86::FLDCW16m)), CWFrameIdx);
21432 // Restore the memory image of control word to original value
21433 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21436 // Get the X86 opcode to use.
21438 switch (MI->getOpcode()) {
21439 default: llvm_unreachable("illegal opcode!");
21440 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21441 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21442 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21443 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21444 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21445 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21446 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21447 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21448 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21452 MachineOperand &Op = MI->getOperand(0);
21454 AM.BaseType = X86AddressMode::RegBase;
21455 AM.Base.Reg = Op.getReg();
21457 AM.BaseType = X86AddressMode::FrameIndexBase;
21458 AM.Base.FrameIndex = Op.getIndex();
21460 Op = MI->getOperand(1);
21462 AM.Scale = Op.getImm();
21463 Op = MI->getOperand(2);
21465 AM.IndexReg = Op.getImm();
21466 Op = MI->getOperand(3);
21467 if (Op.isGlobal()) {
21468 AM.GV = Op.getGlobal();
21470 AM.Disp = Op.getImm();
21472 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21473 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21475 // Reload the original control word now.
21476 addFrameReference(BuildMI(*BB, MI, DL,
21477 TII->get(X86::FLDCW16m)), CWFrameIdx);
21479 MI->eraseFromParent(); // The pseudo instruction is gone now.
21482 // String/text processing lowering.
21483 case X86::PCMPISTRM128REG:
21484 case X86::VPCMPISTRM128REG:
21485 case X86::PCMPISTRM128MEM:
21486 case X86::VPCMPISTRM128MEM:
21487 case X86::PCMPESTRM128REG:
21488 case X86::VPCMPESTRM128REG:
21489 case X86::PCMPESTRM128MEM:
21490 case X86::VPCMPESTRM128MEM:
21491 assert(Subtarget->hasSSE42() &&
21492 "Target must have SSE4.2 or AVX features enabled");
21493 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21495 // String/text processing lowering.
21496 case X86::PCMPISTRIREG:
21497 case X86::VPCMPISTRIREG:
21498 case X86::PCMPISTRIMEM:
21499 case X86::VPCMPISTRIMEM:
21500 case X86::PCMPESTRIREG:
21501 case X86::VPCMPESTRIREG:
21502 case X86::PCMPESTRIMEM:
21503 case X86::VPCMPESTRIMEM:
21504 assert(Subtarget->hasSSE42() &&
21505 "Target must have SSE4.2 or AVX features enabled");
21506 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21508 // Thread synchronization.
21510 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21515 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21517 case X86::VASTART_SAVE_XMM_REGS:
21518 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21520 case X86::VAARG_64:
21521 return EmitVAARG64WithCustomInserter(MI, BB);
21523 case X86::EH_SjLj_SetJmp32:
21524 case X86::EH_SjLj_SetJmp64:
21525 return emitEHSjLjSetJmp(MI, BB);
21527 case X86::EH_SjLj_LongJmp32:
21528 case X86::EH_SjLj_LongJmp64:
21529 return emitEHSjLjLongJmp(MI, BB);
21531 case TargetOpcode::STATEPOINT:
21532 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21533 // this point in the process. We diverge later.
21534 return emitPatchPoint(MI, BB);
21536 case TargetOpcode::STACKMAP:
21537 case TargetOpcode::PATCHPOINT:
21538 return emitPatchPoint(MI, BB);
21540 case X86::VFMADDPDr213r:
21541 case X86::VFMADDPSr213r:
21542 case X86::VFMADDSDr213r:
21543 case X86::VFMADDSSr213r:
21544 case X86::VFMSUBPDr213r:
21545 case X86::VFMSUBPSr213r:
21546 case X86::VFMSUBSDr213r:
21547 case X86::VFMSUBSSr213r:
21548 case X86::VFNMADDPDr213r:
21549 case X86::VFNMADDPSr213r:
21550 case X86::VFNMADDSDr213r:
21551 case X86::VFNMADDSSr213r:
21552 case X86::VFNMSUBPDr213r:
21553 case X86::VFNMSUBPSr213r:
21554 case X86::VFNMSUBSDr213r:
21555 case X86::VFNMSUBSSr213r:
21556 case X86::VFMADDSUBPDr213r:
21557 case X86::VFMADDSUBPSr213r:
21558 case X86::VFMSUBADDPDr213r:
21559 case X86::VFMSUBADDPSr213r:
21560 case X86::VFMADDPDr213rY:
21561 case X86::VFMADDPSr213rY:
21562 case X86::VFMSUBPDr213rY:
21563 case X86::VFMSUBPSr213rY:
21564 case X86::VFNMADDPDr213rY:
21565 case X86::VFNMADDPSr213rY:
21566 case X86::VFNMSUBPDr213rY:
21567 case X86::VFNMSUBPSr213rY:
21568 case X86::VFMADDSUBPDr213rY:
21569 case X86::VFMADDSUBPSr213rY:
21570 case X86::VFMSUBADDPDr213rY:
21571 case X86::VFMSUBADDPSr213rY:
21572 return emitFMA3Instr(MI, BB);
21576 //===----------------------------------------------------------------------===//
21577 // X86 Optimization Hooks
21578 //===----------------------------------------------------------------------===//
21580 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21583 const SelectionDAG &DAG,
21584 unsigned Depth) const {
21585 unsigned BitWidth = KnownZero.getBitWidth();
21586 unsigned Opc = Op.getOpcode();
21587 assert((Opc >= ISD::BUILTIN_OP_END ||
21588 Opc == ISD::INTRINSIC_WO_CHAIN ||
21589 Opc == ISD::INTRINSIC_W_CHAIN ||
21590 Opc == ISD::INTRINSIC_VOID) &&
21591 "Should use MaskedValueIsZero if you don't know whether Op"
21592 " is a target node!");
21594 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21608 // These nodes' second result is a boolean.
21609 if (Op.getResNo() == 0)
21612 case X86ISD::SETCC:
21613 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21615 case ISD::INTRINSIC_WO_CHAIN: {
21616 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21617 unsigned NumLoBits = 0;
21620 case Intrinsic::x86_sse_movmsk_ps:
21621 case Intrinsic::x86_avx_movmsk_ps_256:
21622 case Intrinsic::x86_sse2_movmsk_pd:
21623 case Intrinsic::x86_avx_movmsk_pd_256:
21624 case Intrinsic::x86_mmx_pmovmskb:
21625 case Intrinsic::x86_sse2_pmovmskb_128:
21626 case Intrinsic::x86_avx2_pmovmskb: {
21627 // High bits of movmskp{s|d}, pmovmskb are known zero.
21629 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21630 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21631 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21632 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21633 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21634 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21635 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21636 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21638 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21647 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21649 const SelectionDAG &,
21650 unsigned Depth) const {
21651 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21652 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21653 return Op.getValueType().getScalarType().getSizeInBits();
21659 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21660 /// node is a GlobalAddress + offset.
21661 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21662 const GlobalValue* &GA,
21663 int64_t &Offset) const {
21664 if (N->getOpcode() == X86ISD::Wrapper) {
21665 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21666 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21667 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21671 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21674 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21675 /// same as extracting the high 128-bit part of 256-bit vector and then
21676 /// inserting the result into the low part of a new 256-bit vector
21677 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21678 EVT VT = SVOp->getValueType(0);
21679 unsigned NumElems = VT.getVectorNumElements();
21681 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21682 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21683 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21684 SVOp->getMaskElt(j) >= 0)
21690 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21691 /// same as extracting the low 128-bit part of 256-bit vector and then
21692 /// inserting the result into the high part of a new 256-bit vector
21693 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21694 EVT VT = SVOp->getValueType(0);
21695 unsigned NumElems = VT.getVectorNumElements();
21697 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21698 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21699 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21700 SVOp->getMaskElt(j) >= 0)
21706 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21707 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21708 TargetLowering::DAGCombinerInfo &DCI,
21709 const X86Subtarget* Subtarget) {
21711 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21712 SDValue V1 = SVOp->getOperand(0);
21713 SDValue V2 = SVOp->getOperand(1);
21714 EVT VT = SVOp->getValueType(0);
21715 unsigned NumElems = VT.getVectorNumElements();
21717 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21718 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21722 // V UNDEF BUILD_VECTOR UNDEF
21724 // CONCAT_VECTOR CONCAT_VECTOR
21727 // RESULT: V + zero extended
21729 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21730 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21731 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21734 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21737 // To match the shuffle mask, the first half of the mask should
21738 // be exactly the first vector, and all the rest a splat with the
21739 // first element of the second one.
21740 for (unsigned i = 0; i != NumElems/2; ++i)
21741 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21742 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21745 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21746 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21747 if (Ld->hasNUsesOfValue(1, 0)) {
21748 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21749 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21751 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21753 Ld->getPointerInfo(),
21754 Ld->getAlignment(),
21755 false/*isVolatile*/, true/*ReadMem*/,
21756 false/*WriteMem*/);
21758 // Make sure the newly-created LOAD is in the same position as Ld in
21759 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21760 // and update uses of Ld's output chain to use the TokenFactor.
21761 if (Ld->hasAnyUseOfValue(1)) {
21762 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21763 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21764 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21765 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21766 SDValue(ResNode.getNode(), 1));
21769 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21773 // Emit a zeroed vector and insert the desired subvector on its
21775 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21776 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21777 return DCI.CombineTo(N, InsV);
21780 //===--------------------------------------------------------------------===//
21781 // Combine some shuffles into subvector extracts and inserts:
21784 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21785 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21786 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21787 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21788 return DCI.CombineTo(N, InsV);
21791 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21792 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21793 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21794 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21795 return DCI.CombineTo(N, InsV);
21801 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21804 /// This is the leaf of the recursive combinine below. When we have found some
21805 /// chain of single-use x86 shuffle instructions and accumulated the combined
21806 /// shuffle mask represented by them, this will try to pattern match that mask
21807 /// into either a single instruction if there is a special purpose instruction
21808 /// for this operation, or into a PSHUFB instruction which is a fully general
21809 /// instruction but should only be used to replace chains over a certain depth.
21810 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21811 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21812 TargetLowering::DAGCombinerInfo &DCI,
21813 const X86Subtarget *Subtarget) {
21814 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21816 // Find the operand that enters the chain. Note that multiple uses are OK
21817 // here, we're not going to remove the operand we find.
21818 SDValue Input = Op.getOperand(0);
21819 while (Input.getOpcode() == ISD::BITCAST)
21820 Input = Input.getOperand(0);
21822 MVT VT = Input.getSimpleValueType();
21823 MVT RootVT = Root.getSimpleValueType();
21826 // Just remove no-op shuffle masks.
21827 if (Mask.size() == 1) {
21828 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21833 // Use the float domain if the operand type is a floating point type.
21834 bool FloatDomain = VT.isFloatingPoint();
21836 // For floating point shuffles, we don't have free copies in the shuffle
21837 // instructions or the ability to load as part of the instruction, so
21838 // canonicalize their shuffles to UNPCK or MOV variants.
21840 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21841 // vectors because it can have a load folded into it that UNPCK cannot. This
21842 // doesn't preclude something switching to the shorter encoding post-RA.
21844 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21845 bool Lo = Mask.equals(0, 0);
21848 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21849 // is no slower than UNPCKLPD but has the option to fold the input operand
21850 // into even an unaligned memory load.
21851 if (Lo && Subtarget->hasSSE3()) {
21852 Shuffle = X86ISD::MOVDDUP;
21853 ShuffleVT = MVT::v2f64;
21855 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21856 // than the UNPCK variants.
21857 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21858 ShuffleVT = MVT::v4f32;
21860 if (Depth == 1 && Root->getOpcode() == Shuffle)
21861 return false; // Nothing to do!
21862 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21863 DCI.AddToWorklist(Op.getNode());
21864 if (Shuffle == X86ISD::MOVDDUP)
21865 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21867 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21868 DCI.AddToWorklist(Op.getNode());
21869 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21873 if (Subtarget->hasSSE3() &&
21874 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21875 bool Lo = Mask.equals(0, 0, 2, 2);
21876 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21877 MVT ShuffleVT = MVT::v4f32;
21878 if (Depth == 1 && Root->getOpcode() == Shuffle)
21879 return false; // Nothing to do!
21880 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21881 DCI.AddToWorklist(Op.getNode());
21882 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21883 DCI.AddToWorklist(Op.getNode());
21884 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21888 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21889 bool Lo = Mask.equals(0, 0, 1, 1);
21890 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21891 MVT ShuffleVT = MVT::v4f32;
21892 if (Depth == 1 && Root->getOpcode() == Shuffle)
21893 return false; // Nothing to do!
21894 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21895 DCI.AddToWorklist(Op.getNode());
21896 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21897 DCI.AddToWorklist(Op.getNode());
21898 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21904 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21905 // variants as none of these have single-instruction variants that are
21906 // superior to the UNPCK formulation.
21907 if (!FloatDomain &&
21908 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21909 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21910 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21911 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21913 bool Lo = Mask[0] == 0;
21914 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21915 if (Depth == 1 && Root->getOpcode() == Shuffle)
21916 return false; // Nothing to do!
21918 switch (Mask.size()) {
21920 ShuffleVT = MVT::v8i16;
21923 ShuffleVT = MVT::v16i8;
21926 llvm_unreachable("Impossible mask size!");
21928 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21929 DCI.AddToWorklist(Op.getNode());
21930 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21931 DCI.AddToWorklist(Op.getNode());
21932 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21937 // Don't try to re-form single instruction chains under any circumstances now
21938 // that we've done encoding canonicalization for them.
21942 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21943 // can replace them with a single PSHUFB instruction profitably. Intel's
21944 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21945 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21946 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21947 SmallVector<SDValue, 16> PSHUFBMask;
21948 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21949 int Ratio = 16 / Mask.size();
21950 for (unsigned i = 0; i < 16; ++i) {
21951 if (Mask[i / Ratio] == SM_SentinelUndef) {
21952 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21955 int M = Mask[i / Ratio] != SM_SentinelZero
21956 ? Ratio * Mask[i / Ratio] + i % Ratio
21958 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21960 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21961 DCI.AddToWorklist(Op.getNode());
21962 SDValue PSHUFBMaskOp =
21963 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21964 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21965 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21966 DCI.AddToWorklist(Op.getNode());
21967 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21972 // Failed to find any combines.
21976 /// \brief Fully generic combining of x86 shuffle instructions.
21978 /// This should be the last combine run over the x86 shuffle instructions. Once
21979 /// they have been fully optimized, this will recursively consider all chains
21980 /// of single-use shuffle instructions, build a generic model of the cumulative
21981 /// shuffle operation, and check for simpler instructions which implement this
21982 /// operation. We use this primarily for two purposes:
21984 /// 1) Collapse generic shuffles to specialized single instructions when
21985 /// equivalent. In most cases, this is just an encoding size win, but
21986 /// sometimes we will collapse multiple generic shuffles into a single
21987 /// special-purpose shuffle.
21988 /// 2) Look for sequences of shuffle instructions with 3 or more total
21989 /// instructions, and replace them with the slightly more expensive SSSE3
21990 /// PSHUFB instruction if available. We do this as the last combining step
21991 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21992 /// a suitable short sequence of other instructions. The PHUFB will either
21993 /// use a register or have to read from memory and so is slightly (but only
21994 /// slightly) more expensive than the other shuffle instructions.
21996 /// Because this is inherently a quadratic operation (for each shuffle in
21997 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21998 /// This should never be an issue in practice as the shuffle lowering doesn't
21999 /// produce sequences of more than 8 instructions.
22001 /// FIXME: We will currently miss some cases where the redundant shuffling
22002 /// would simplify under the threshold for PSHUFB formation because of
22003 /// combine-ordering. To fix this, we should do the redundant instruction
22004 /// combining in this recursive walk.
22005 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22006 ArrayRef<int> RootMask,
22007 int Depth, bool HasPSHUFB,
22009 TargetLowering::DAGCombinerInfo &DCI,
22010 const X86Subtarget *Subtarget) {
22011 // Bound the depth of our recursive combine because this is ultimately
22012 // quadratic in nature.
22016 // Directly rip through bitcasts to find the underlying operand.
22017 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22018 Op = Op.getOperand(0);
22020 MVT VT = Op.getSimpleValueType();
22021 if (!VT.isVector())
22022 return false; // Bail if we hit a non-vector.
22023 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
22024 // version should be added.
22025 if (VT.getSizeInBits() != 128)
22028 assert(Root.getSimpleValueType().isVector() &&
22029 "Shuffles operate on vector types!");
22030 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22031 "Can only combine shuffles of the same vector register size.");
22033 if (!isTargetShuffle(Op.getOpcode()))
22035 SmallVector<int, 16> OpMask;
22037 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22038 // We only can combine unary shuffles which we can decode the mask for.
22039 if (!HaveMask || !IsUnary)
22042 assert(VT.getVectorNumElements() == OpMask.size() &&
22043 "Different mask size from vector size!");
22044 assert(((RootMask.size() > OpMask.size() &&
22045 RootMask.size() % OpMask.size() == 0) ||
22046 (OpMask.size() > RootMask.size() &&
22047 OpMask.size() % RootMask.size() == 0) ||
22048 OpMask.size() == RootMask.size()) &&
22049 "The smaller number of elements must divide the larger.");
22050 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22051 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22052 assert(((RootRatio == 1 && OpRatio == 1) ||
22053 (RootRatio == 1) != (OpRatio == 1)) &&
22054 "Must not have a ratio for both incoming and op masks!");
22056 SmallVector<int, 16> Mask;
22057 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22059 // Merge this shuffle operation's mask into our accumulated mask. Note that
22060 // this shuffle's mask will be the first applied to the input, followed by the
22061 // root mask to get us all the way to the root value arrangement. The reason
22062 // for this order is that we are recursing up the operation chain.
22063 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22064 int RootIdx = i / RootRatio;
22065 if (RootMask[RootIdx] < 0) {
22066 // This is a zero or undef lane, we're done.
22067 Mask.push_back(RootMask[RootIdx]);
22071 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22072 int OpIdx = RootMaskedIdx / OpRatio;
22073 if (OpMask[OpIdx] < 0) {
22074 // The incoming lanes are zero or undef, it doesn't matter which ones we
22076 Mask.push_back(OpMask[OpIdx]);
22080 // Ok, we have non-zero lanes, map them through.
22081 Mask.push_back(OpMask[OpIdx] * OpRatio +
22082 RootMaskedIdx % OpRatio);
22085 // See if we can recurse into the operand to combine more things.
22086 switch (Op.getOpcode()) {
22087 case X86ISD::PSHUFB:
22089 case X86ISD::PSHUFD:
22090 case X86ISD::PSHUFHW:
22091 case X86ISD::PSHUFLW:
22092 if (Op.getOperand(0).hasOneUse() &&
22093 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22094 HasPSHUFB, DAG, DCI, Subtarget))
22098 case X86ISD::UNPCKL:
22099 case X86ISD::UNPCKH:
22100 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22101 // We can't check for single use, we have to check that this shuffle is the only user.
22102 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22103 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22104 HasPSHUFB, DAG, DCI, Subtarget))
22109 // Minor canonicalization of the accumulated shuffle mask to make it easier
22110 // to match below. All this does is detect masks with squential pairs of
22111 // elements, and shrink them to the half-width mask. It does this in a loop
22112 // so it will reduce the size of the mask to the minimal width mask which
22113 // performs an equivalent shuffle.
22114 SmallVector<int, 16> WidenedMask;
22115 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22116 Mask = std::move(WidenedMask);
22117 WidenedMask.clear();
22120 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22124 /// \brief Get the PSHUF-style mask from PSHUF node.
22126 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22127 /// PSHUF-style masks that can be reused with such instructions.
22128 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22129 SmallVector<int, 4> Mask;
22131 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22135 switch (N.getOpcode()) {
22136 case X86ISD::PSHUFD:
22138 case X86ISD::PSHUFLW:
22141 case X86ISD::PSHUFHW:
22142 Mask.erase(Mask.begin(), Mask.begin() + 4);
22143 for (int &M : Mask)
22147 llvm_unreachable("No valid shuffle instruction found!");
22151 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22153 /// We walk up the chain and look for a combinable shuffle, skipping over
22154 /// shuffles that we could hoist this shuffle's transformation past without
22155 /// altering anything.
22157 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22159 TargetLowering::DAGCombinerInfo &DCI) {
22160 assert(N.getOpcode() == X86ISD::PSHUFD &&
22161 "Called with something other than an x86 128-bit half shuffle!");
22164 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22165 // of the shuffles in the chain so that we can form a fresh chain to replace
22167 SmallVector<SDValue, 8> Chain;
22168 SDValue V = N.getOperand(0);
22169 for (; V.hasOneUse(); V = V.getOperand(0)) {
22170 switch (V.getOpcode()) {
22172 return SDValue(); // Nothing combined!
22175 // Skip bitcasts as we always know the type for the target specific
22179 case X86ISD::PSHUFD:
22180 // Found another dword shuffle.
22183 case X86ISD::PSHUFLW:
22184 // Check that the low words (being shuffled) are the identity in the
22185 // dword shuffle, and the high words are self-contained.
22186 if (Mask[0] != 0 || Mask[1] != 1 ||
22187 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22190 Chain.push_back(V);
22193 case X86ISD::PSHUFHW:
22194 // Check that the high words (being shuffled) are the identity in the
22195 // dword shuffle, and the low words are self-contained.
22196 if (Mask[2] != 2 || Mask[3] != 3 ||
22197 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22200 Chain.push_back(V);
22203 case X86ISD::UNPCKL:
22204 case X86ISD::UNPCKH:
22205 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22206 // shuffle into a preceding word shuffle.
22207 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22210 // Search for a half-shuffle which we can combine with.
22211 unsigned CombineOp =
22212 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22213 if (V.getOperand(0) != V.getOperand(1) ||
22214 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22216 Chain.push_back(V);
22217 V = V.getOperand(0);
22219 switch (V.getOpcode()) {
22221 return SDValue(); // Nothing to combine.
22223 case X86ISD::PSHUFLW:
22224 case X86ISD::PSHUFHW:
22225 if (V.getOpcode() == CombineOp)
22228 Chain.push_back(V);
22232 V = V.getOperand(0);
22236 } while (V.hasOneUse());
22239 // Break out of the loop if we break out of the switch.
22243 if (!V.hasOneUse())
22244 // We fell out of the loop without finding a viable combining instruction.
22247 // Merge this node's mask and our incoming mask.
22248 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22249 for (int &M : Mask)
22251 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22252 getV4X86ShuffleImm8ForMask(Mask, DAG));
22254 // Rebuild the chain around this new shuffle.
22255 while (!Chain.empty()) {
22256 SDValue W = Chain.pop_back_val();
22258 if (V.getValueType() != W.getOperand(0).getValueType())
22259 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22261 switch (W.getOpcode()) {
22263 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22265 case X86ISD::UNPCKL:
22266 case X86ISD::UNPCKH:
22267 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22270 case X86ISD::PSHUFD:
22271 case X86ISD::PSHUFLW:
22272 case X86ISD::PSHUFHW:
22273 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22277 if (V.getValueType() != N.getValueType())
22278 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22280 // Return the new chain to replace N.
22284 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22286 /// We walk up the chain, skipping shuffles of the other half and looking
22287 /// through shuffles which switch halves trying to find a shuffle of the same
22288 /// pair of dwords.
22289 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22291 TargetLowering::DAGCombinerInfo &DCI) {
22293 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22294 "Called with something other than an x86 128-bit half shuffle!");
22296 unsigned CombineOpcode = N.getOpcode();
22298 // Walk up a single-use chain looking for a combinable shuffle.
22299 SDValue V = N.getOperand(0);
22300 for (; V.hasOneUse(); V = V.getOperand(0)) {
22301 switch (V.getOpcode()) {
22303 return false; // Nothing combined!
22306 // Skip bitcasts as we always know the type for the target specific
22310 case X86ISD::PSHUFLW:
22311 case X86ISD::PSHUFHW:
22312 if (V.getOpcode() == CombineOpcode)
22315 // Other-half shuffles are no-ops.
22318 // Break out of the loop if we break out of the switch.
22322 if (!V.hasOneUse())
22323 // We fell out of the loop without finding a viable combining instruction.
22326 // Combine away the bottom node as its shuffle will be accumulated into
22327 // a preceding shuffle.
22328 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22330 // Record the old value.
22333 // Merge this node's mask and our incoming mask (adjusted to account for all
22334 // the pshufd instructions encountered).
22335 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22336 for (int &M : Mask)
22338 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22339 getV4X86ShuffleImm8ForMask(Mask, DAG));
22341 // Check that the shuffles didn't cancel each other out. If not, we need to
22342 // combine to the new one.
22344 // Replace the combinable shuffle with the combined one, updating all users
22345 // so that we re-evaluate the chain here.
22346 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22351 /// \brief Try to combine x86 target specific shuffles.
22352 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22353 TargetLowering::DAGCombinerInfo &DCI,
22354 const X86Subtarget *Subtarget) {
22356 MVT VT = N.getSimpleValueType();
22357 SmallVector<int, 4> Mask;
22359 switch (N.getOpcode()) {
22360 case X86ISD::PSHUFD:
22361 case X86ISD::PSHUFLW:
22362 case X86ISD::PSHUFHW:
22363 Mask = getPSHUFShuffleMask(N);
22364 assert(Mask.size() == 4);
22370 // Nuke no-op shuffles that show up after combining.
22371 if (isNoopShuffleMask(Mask))
22372 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22374 // Look for simplifications involving one or two shuffle instructions.
22375 SDValue V = N.getOperand(0);
22376 switch (N.getOpcode()) {
22379 case X86ISD::PSHUFLW:
22380 case X86ISD::PSHUFHW:
22381 assert(VT == MVT::v8i16);
22384 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22385 return SDValue(); // We combined away this shuffle, so we're done.
22387 // See if this reduces to a PSHUFD which is no more expensive and can
22388 // combine with more operations. Note that it has to at least flip the
22389 // dwords as otherwise it would have been removed as a no-op.
22390 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22391 int DMask[] = {0, 1, 2, 3};
22392 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22393 DMask[DOffset + 0] = DOffset + 1;
22394 DMask[DOffset + 1] = DOffset + 0;
22395 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22396 DCI.AddToWorklist(V.getNode());
22397 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22398 getV4X86ShuffleImm8ForMask(DMask, DAG));
22399 DCI.AddToWorklist(V.getNode());
22400 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22403 // Look for shuffle patterns which can be implemented as a single unpack.
22404 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22405 // only works when we have a PSHUFD followed by two half-shuffles.
22406 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22407 (V.getOpcode() == X86ISD::PSHUFLW ||
22408 V.getOpcode() == X86ISD::PSHUFHW) &&
22409 V.getOpcode() != N.getOpcode() &&
22411 SDValue D = V.getOperand(0);
22412 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22413 D = D.getOperand(0);
22414 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22415 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22416 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22417 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22418 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22420 for (int i = 0; i < 4; ++i) {
22421 WordMask[i + NOffset] = Mask[i] + NOffset;
22422 WordMask[i + VOffset] = VMask[i] + VOffset;
22424 // Map the word mask through the DWord mask.
22426 for (int i = 0; i < 8; ++i)
22427 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22428 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22429 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22430 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22431 std::begin(UnpackLoMask)) ||
22432 std::equal(std::begin(MappedMask), std::end(MappedMask),
22433 std::begin(UnpackHiMask))) {
22434 // We can replace all three shuffles with an unpack.
22435 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22436 DCI.AddToWorklist(V.getNode());
22437 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22439 DL, MVT::v8i16, V, V);
22446 case X86ISD::PSHUFD:
22447 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22456 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22458 /// We combine this directly on the abstract vector shuffle nodes so it is
22459 /// easier to generically match. We also insert dummy vector shuffle nodes for
22460 /// the operands which explicitly discard the lanes which are unused by this
22461 /// operation to try to flow through the rest of the combiner the fact that
22462 /// they're unused.
22463 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22465 EVT VT = N->getValueType(0);
22467 // We only handle target-independent shuffles.
22468 // FIXME: It would be easy and harmless to use the target shuffle mask
22469 // extraction tool to support more.
22470 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22473 auto *SVN = cast<ShuffleVectorSDNode>(N);
22474 ArrayRef<int> Mask = SVN->getMask();
22475 SDValue V1 = N->getOperand(0);
22476 SDValue V2 = N->getOperand(1);
22478 // We require the first shuffle operand to be the SUB node, and the second to
22479 // be the ADD node.
22480 // FIXME: We should support the commuted patterns.
22481 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22484 // If there are other uses of these operations we can't fold them.
22485 if (!V1->hasOneUse() || !V2->hasOneUse())
22488 // Ensure that both operations have the same operands. Note that we can
22489 // commute the FADD operands.
22490 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22491 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22492 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22495 // We're looking for blends between FADD and FSUB nodes. We insist on these
22496 // nodes being lined up in a specific expected pattern.
22497 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22498 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22499 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22502 // Only specific types are legal at this point, assert so we notice if and
22503 // when these change.
22504 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22505 VT == MVT::v4f64) &&
22506 "Unknown vector type encountered!");
22508 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22511 /// PerformShuffleCombine - Performs several different shuffle combines.
22512 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22513 TargetLowering::DAGCombinerInfo &DCI,
22514 const X86Subtarget *Subtarget) {
22516 SDValue N0 = N->getOperand(0);
22517 SDValue N1 = N->getOperand(1);
22518 EVT VT = N->getValueType(0);
22520 // Don't create instructions with illegal types after legalize types has run.
22521 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22522 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22525 // If we have legalized the vector types, look for blends of FADD and FSUB
22526 // nodes that we can fuse into an ADDSUB node.
22527 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22528 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22531 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22532 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22533 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22534 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22536 // During Type Legalization, when promoting illegal vector types,
22537 // the backend might introduce new shuffle dag nodes and bitcasts.
22539 // This code performs the following transformation:
22540 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22541 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22543 // We do this only if both the bitcast and the BINOP dag nodes have
22544 // one use. Also, perform this transformation only if the new binary
22545 // operation is legal. This is to avoid introducing dag nodes that
22546 // potentially need to be further expanded (or custom lowered) into a
22547 // less optimal sequence of dag nodes.
22548 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22549 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22550 N0.getOpcode() == ISD::BITCAST) {
22551 SDValue BC0 = N0.getOperand(0);
22552 EVT SVT = BC0.getValueType();
22553 unsigned Opcode = BC0.getOpcode();
22554 unsigned NumElts = VT.getVectorNumElements();
22556 if (BC0.hasOneUse() && SVT.isVector() &&
22557 SVT.getVectorNumElements() * 2 == NumElts &&
22558 TLI.isOperationLegal(Opcode, VT)) {
22559 bool CanFold = false;
22571 unsigned SVTNumElts = SVT.getVectorNumElements();
22572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22573 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22574 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22575 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22576 CanFold = SVOp->getMaskElt(i) < 0;
22579 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22580 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22581 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22582 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22587 // Only handle 128 wide vector from here on.
22588 if (!VT.is128BitVector())
22591 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22592 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22593 // consecutive, non-overlapping, and in the right order.
22594 SmallVector<SDValue, 16> Elts;
22595 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22596 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22598 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22602 if (isTargetShuffle(N->getOpcode())) {
22604 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22605 if (Shuffle.getNode())
22608 // Try recursively combining arbitrary sequences of x86 shuffle
22609 // instructions into higher-order shuffles. We do this after combining
22610 // specific PSHUF instruction sequences into their minimal form so that we
22611 // can evaluate how many specialized shuffle instructions are involved in
22612 // a particular chain.
22613 SmallVector<int, 1> NonceMask; // Just a placeholder.
22614 NonceMask.push_back(0);
22615 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22616 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22618 return SDValue(); // This routine will use CombineTo to replace N.
22624 /// PerformTruncateCombine - Converts truncate operation to
22625 /// a sequence of vector shuffle operations.
22626 /// It is possible when we truncate 256-bit vector to 128-bit vector
22627 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22628 TargetLowering::DAGCombinerInfo &DCI,
22629 const X86Subtarget *Subtarget) {
22633 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22634 /// specific shuffle of a load can be folded into a single element load.
22635 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22636 /// shuffles have been custom lowered so we need to handle those here.
22637 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22638 TargetLowering::DAGCombinerInfo &DCI) {
22639 if (DCI.isBeforeLegalizeOps())
22642 SDValue InVec = N->getOperand(0);
22643 SDValue EltNo = N->getOperand(1);
22645 if (!isa<ConstantSDNode>(EltNo))
22648 EVT OriginalVT = InVec.getValueType();
22650 if (InVec.getOpcode() == ISD::BITCAST) {
22651 // Don't duplicate a load with other uses.
22652 if (!InVec.hasOneUse())
22654 EVT BCVT = InVec.getOperand(0).getValueType();
22655 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22657 InVec = InVec.getOperand(0);
22660 EVT CurrentVT = InVec.getValueType();
22662 if (!isTargetShuffle(InVec.getOpcode()))
22665 // Don't duplicate a load with other uses.
22666 if (!InVec.hasOneUse())
22669 SmallVector<int, 16> ShuffleMask;
22671 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22672 ShuffleMask, UnaryShuffle))
22675 // Select the input vector, guarding against out of range extract vector.
22676 unsigned NumElems = CurrentVT.getVectorNumElements();
22677 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22678 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22679 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22680 : InVec.getOperand(1);
22682 // If inputs to shuffle are the same for both ops, then allow 2 uses
22683 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22685 if (LdNode.getOpcode() == ISD::BITCAST) {
22686 // Don't duplicate a load with other uses.
22687 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22690 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22691 LdNode = LdNode.getOperand(0);
22694 if (!ISD::isNormalLoad(LdNode.getNode()))
22697 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22699 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22702 EVT EltVT = N->getValueType(0);
22703 // If there's a bitcast before the shuffle, check if the load type and
22704 // alignment is valid.
22705 unsigned Align = LN0->getAlignment();
22706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22707 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22708 EltVT.getTypeForEVT(*DAG.getContext()));
22710 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22713 // All checks match so transform back to vector_shuffle so that DAG combiner
22714 // can finish the job
22717 // Create shuffle node taking into account the case that its a unary shuffle
22718 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22719 : InVec.getOperand(1);
22720 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22721 InVec.getOperand(0), Shuffle,
22723 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22724 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22728 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22729 /// generation and convert it from being a bunch of shuffles and extracts
22730 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22731 /// storing the value and loading scalars back, while for x64 we should
22732 /// use 64-bit extracts and shifts.
22733 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22734 TargetLowering::DAGCombinerInfo &DCI) {
22735 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22736 if (NewOp.getNode())
22739 SDValue InputVector = N->getOperand(0);
22741 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22742 // from mmx to v2i32 has a single usage.
22743 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22744 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22745 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22746 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22747 N->getValueType(0),
22748 InputVector.getNode()->getOperand(0));
22750 // Only operate on vectors of 4 elements, where the alternative shuffling
22751 // gets to be more expensive.
22752 if (InputVector.getValueType() != MVT::v4i32)
22755 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22756 // single use which is a sign-extend or zero-extend, and all elements are
22758 SmallVector<SDNode *, 4> Uses;
22759 unsigned ExtractedElements = 0;
22760 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22761 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22762 if (UI.getUse().getResNo() != InputVector.getResNo())
22765 SDNode *Extract = *UI;
22766 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22769 if (Extract->getValueType(0) != MVT::i32)
22771 if (!Extract->hasOneUse())
22773 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22774 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22776 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22779 // Record which element was extracted.
22780 ExtractedElements |=
22781 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22783 Uses.push_back(Extract);
22786 // If not all the elements were used, this may not be worthwhile.
22787 if (ExtractedElements != 15)
22790 // Ok, we've now decided to do the transformation.
22791 // If 64-bit shifts are legal, use the extract-shift sequence,
22792 // otherwise bounce the vector off the cache.
22793 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22795 SDLoc dl(InputVector);
22797 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22798 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22799 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22800 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22801 DAG.getConstant(0, VecIdxTy));
22802 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22803 DAG.getConstant(1, VecIdxTy));
22805 SDValue ShAmt = DAG.getConstant(32,
22806 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22807 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22808 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22809 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22810 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22811 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22812 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22814 // Store the value to a temporary stack slot.
22815 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22816 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22817 MachinePointerInfo(), false, false, 0);
22819 EVT ElementType = InputVector.getValueType().getVectorElementType();
22820 unsigned EltSize = ElementType.getSizeInBits() / 8;
22822 // Replace each use (extract) with a load of the appropriate element.
22823 for (unsigned i = 0; i < 4; ++i) {
22824 uint64_t Offset = EltSize * i;
22825 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22827 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22828 StackPtr, OffsetVal);
22830 // Load the scalar.
22831 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22832 ScalarAddr, MachinePointerInfo(),
22833 false, false, false, 0);
22838 // Replace the extracts
22839 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22840 UE = Uses.end(); UI != UE; ++UI) {
22841 SDNode *Extract = *UI;
22843 SDValue Idx = Extract->getOperand(1);
22844 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22845 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22848 // The replacement was made in place; don't return anything.
22852 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22853 static std::pair<unsigned, bool>
22854 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22855 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22856 if (!VT.isVector())
22857 return std::make_pair(0, false);
22859 bool NeedSplit = false;
22860 switch (VT.getSimpleVT().SimpleTy) {
22861 default: return std::make_pair(0, false);
22864 if (!Subtarget->hasVLX())
22865 return std::make_pair(0, false);
22869 if (!Subtarget->hasBWI())
22870 return std::make_pair(0, false);
22874 if (!Subtarget->hasAVX512())
22875 return std::make_pair(0, false);
22880 if (!Subtarget->hasAVX2())
22882 if (!Subtarget->hasAVX())
22883 return std::make_pair(0, false);
22888 if (!Subtarget->hasSSE2())
22889 return std::make_pair(0, false);
22892 // SSE2 has only a small subset of the operations.
22893 bool hasUnsigned = Subtarget->hasSSE41() ||
22894 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22895 bool hasSigned = Subtarget->hasSSE41() ||
22896 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22898 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22901 // Check for x CC y ? x : y.
22902 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22903 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22908 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22911 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22914 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22917 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22919 // Check for x CC y ? y : x -- a min/max with reversed arms.
22920 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22921 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22926 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22929 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22932 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22935 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22939 return std::make_pair(Opc, NeedSplit);
22943 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22944 const X86Subtarget *Subtarget) {
22946 SDValue Cond = N->getOperand(0);
22947 SDValue LHS = N->getOperand(1);
22948 SDValue RHS = N->getOperand(2);
22950 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22951 SDValue CondSrc = Cond->getOperand(0);
22952 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22953 Cond = CondSrc->getOperand(0);
22956 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22959 // A vselect where all conditions and data are constants can be optimized into
22960 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22961 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22962 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22965 unsigned MaskValue = 0;
22966 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22969 MVT VT = N->getSimpleValueType(0);
22970 unsigned NumElems = VT.getVectorNumElements();
22971 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22972 for (unsigned i = 0; i < NumElems; ++i) {
22973 // Be sure we emit undef where we can.
22974 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22975 ShuffleMask[i] = -1;
22977 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22980 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22981 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22983 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22986 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22988 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22989 TargetLowering::DAGCombinerInfo &DCI,
22990 const X86Subtarget *Subtarget) {
22992 SDValue Cond = N->getOperand(0);
22993 // Get the LHS/RHS of the select.
22994 SDValue LHS = N->getOperand(1);
22995 SDValue RHS = N->getOperand(2);
22996 EVT VT = LHS.getValueType();
22997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22999 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23000 // instructions match the semantics of the common C idiom x<y?x:y but not
23001 // x<=y?x:y, because of how they handle negative zero (which can be
23002 // ignored in unsafe-math mode).
23003 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23004 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
23005 (Subtarget->hasSSE2() ||
23006 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23007 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23009 unsigned Opcode = 0;
23010 // Check for x CC y ? x : y.
23011 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23012 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23016 // Converting this to a min would handle NaNs incorrectly, and swapping
23017 // the operands would cause it to handle comparisons between positive
23018 // and negative zero incorrectly.
23019 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23020 if (!DAG.getTarget().Options.UnsafeFPMath &&
23021 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23023 std::swap(LHS, RHS);
23025 Opcode = X86ISD::FMIN;
23028 // Converting this to a min would handle comparisons between positive
23029 // and negative zero incorrectly.
23030 if (!DAG.getTarget().Options.UnsafeFPMath &&
23031 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23033 Opcode = X86ISD::FMIN;
23036 // Converting this to a min would handle both negative zeros and NaNs
23037 // incorrectly, but we can swap the operands to fix both.
23038 std::swap(LHS, RHS);
23042 Opcode = X86ISD::FMIN;
23046 // Converting this to a max would handle comparisons between positive
23047 // and negative zero incorrectly.
23048 if (!DAG.getTarget().Options.UnsafeFPMath &&
23049 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23051 Opcode = X86ISD::FMAX;
23054 // Converting this to a max would handle NaNs incorrectly, and swapping
23055 // the operands would cause it to handle comparisons between positive
23056 // and negative zero incorrectly.
23057 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23058 if (!DAG.getTarget().Options.UnsafeFPMath &&
23059 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23061 std::swap(LHS, RHS);
23063 Opcode = X86ISD::FMAX;
23066 // Converting this to a max would handle both negative zeros and NaNs
23067 // incorrectly, but we can swap the operands to fix both.
23068 std::swap(LHS, RHS);
23072 Opcode = X86ISD::FMAX;
23075 // Check for x CC y ? y : x -- a min/max with reversed arms.
23076 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23077 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23081 // Converting this to a min would handle comparisons between positive
23082 // and negative zero incorrectly, and swapping the operands would
23083 // cause it to handle NaNs incorrectly.
23084 if (!DAG.getTarget().Options.UnsafeFPMath &&
23085 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23086 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23088 std::swap(LHS, RHS);
23090 Opcode = X86ISD::FMIN;
23093 // Converting this to a min would handle NaNs incorrectly.
23094 if (!DAG.getTarget().Options.UnsafeFPMath &&
23095 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23097 Opcode = X86ISD::FMIN;
23100 // Converting this to a min would handle both negative zeros and NaNs
23101 // incorrectly, but we can swap the operands to fix both.
23102 std::swap(LHS, RHS);
23106 Opcode = X86ISD::FMIN;
23110 // Converting this to a max would handle NaNs incorrectly.
23111 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23113 Opcode = X86ISD::FMAX;
23116 // Converting this to a max would handle comparisons between positive
23117 // and negative zero incorrectly, and swapping the operands would
23118 // cause it to handle NaNs incorrectly.
23119 if (!DAG.getTarget().Options.UnsafeFPMath &&
23120 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23121 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23123 std::swap(LHS, RHS);
23125 Opcode = X86ISD::FMAX;
23128 // Converting this to a max would handle both negative zeros and NaNs
23129 // incorrectly, but we can swap the operands to fix both.
23130 std::swap(LHS, RHS);
23134 Opcode = X86ISD::FMAX;
23140 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23143 EVT CondVT = Cond.getValueType();
23144 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23145 CondVT.getVectorElementType() == MVT::i1) {
23146 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23147 // lowering on KNL. In this case we convert it to
23148 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23149 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23150 // Since SKX these selects have a proper lowering.
23151 EVT OpVT = LHS.getValueType();
23152 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23153 (OpVT.getVectorElementType() == MVT::i8 ||
23154 OpVT.getVectorElementType() == MVT::i16) &&
23155 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23156 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23157 DCI.AddToWorklist(Cond.getNode());
23158 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23161 // If this is a select between two integer constants, try to do some
23163 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23164 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23165 // Don't do this for crazy integer types.
23166 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23167 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23168 // so that TrueC (the true value) is larger than FalseC.
23169 bool NeedsCondInvert = false;
23171 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23172 // Efficiently invertible.
23173 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23174 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23175 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23176 NeedsCondInvert = true;
23177 std::swap(TrueC, FalseC);
23180 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23181 if (FalseC->getAPIntValue() == 0 &&
23182 TrueC->getAPIntValue().isPowerOf2()) {
23183 if (NeedsCondInvert) // Invert the condition if needed.
23184 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23185 DAG.getConstant(1, Cond.getValueType()));
23187 // Zero extend the condition if needed.
23188 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23190 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23191 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23192 DAG.getConstant(ShAmt, MVT::i8));
23195 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23196 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23197 if (NeedsCondInvert) // Invert the condition if needed.
23198 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23199 DAG.getConstant(1, Cond.getValueType()));
23201 // Zero extend the condition if needed.
23202 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23203 FalseC->getValueType(0), Cond);
23204 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23205 SDValue(FalseC, 0));
23208 // Optimize cases that will turn into an LEA instruction. This requires
23209 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23210 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23211 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23212 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23214 bool isFastMultiplier = false;
23216 switch ((unsigned char)Diff) {
23218 case 1: // result = add base, cond
23219 case 2: // result = lea base( , cond*2)
23220 case 3: // result = lea base(cond, cond*2)
23221 case 4: // result = lea base( , cond*4)
23222 case 5: // result = lea base(cond, cond*4)
23223 case 8: // result = lea base( , cond*8)
23224 case 9: // result = lea base(cond, cond*8)
23225 isFastMultiplier = true;
23230 if (isFastMultiplier) {
23231 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23232 if (NeedsCondInvert) // Invert the condition if needed.
23233 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23234 DAG.getConstant(1, Cond.getValueType()));
23236 // Zero extend the condition if needed.
23237 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23239 // Scale the condition by the difference.
23241 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23242 DAG.getConstant(Diff, Cond.getValueType()));
23244 // Add the base if non-zero.
23245 if (FalseC->getAPIntValue() != 0)
23246 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23247 SDValue(FalseC, 0));
23254 // Canonicalize max and min:
23255 // (x > y) ? x : y -> (x >= y) ? x : y
23256 // (x < y) ? x : y -> (x <= y) ? x : y
23257 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23258 // the need for an extra compare
23259 // against zero. e.g.
23260 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23262 // testl %edi, %edi
23264 // cmovgl %edi, %eax
23268 // cmovsl %eax, %edi
23269 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23270 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23271 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23272 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23277 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23278 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23279 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23280 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23285 // Early exit check
23286 if (!TLI.isTypeLegal(VT))
23289 // Match VSELECTs into subs with unsigned saturation.
23290 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23291 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23292 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23293 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23294 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23296 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23297 // left side invert the predicate to simplify logic below.
23299 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23301 CC = ISD::getSetCCInverse(CC, true);
23302 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23306 if (Other.getNode() && Other->getNumOperands() == 2 &&
23307 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23308 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23309 SDValue CondRHS = Cond->getOperand(1);
23311 // Look for a general sub with unsigned saturation first.
23312 // x >= y ? x-y : 0 --> subus x, y
23313 // x > y ? x-y : 0 --> subus x, y
23314 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23315 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23316 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23318 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23319 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23320 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23321 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23322 // If the RHS is a constant we have to reverse the const
23323 // canonicalization.
23324 // x > C-1 ? x+-C : 0 --> subus x, C
23325 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23326 CondRHSConst->getAPIntValue() ==
23327 (-OpRHSConst->getAPIntValue() - 1))
23328 return DAG.getNode(
23329 X86ISD::SUBUS, DL, VT, OpLHS,
23330 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23332 // Another special case: If C was a sign bit, the sub has been
23333 // canonicalized into a xor.
23334 // FIXME: Would it be better to use computeKnownBits to determine
23335 // whether it's safe to decanonicalize the xor?
23336 // x s< 0 ? x^C : 0 --> subus x, C
23337 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23338 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23339 OpRHSConst->getAPIntValue().isSignBit())
23340 // Note that we have to rebuild the RHS constant here to ensure we
23341 // don't rely on particular values of undef lanes.
23342 return DAG.getNode(
23343 X86ISD::SUBUS, DL, VT, OpLHS,
23344 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23349 // Try to match a min/max vector operation.
23350 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23351 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23352 unsigned Opc = ret.first;
23353 bool NeedSplit = ret.second;
23355 if (Opc && NeedSplit) {
23356 unsigned NumElems = VT.getVectorNumElements();
23357 // Extract the LHS vectors
23358 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23359 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23361 // Extract the RHS vectors
23362 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23363 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23365 // Create min/max for each subvector
23366 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23367 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23369 // Merge the result
23370 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23372 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23375 // Simplify vector selection if condition value type matches vselect
23377 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23378 assert(Cond.getValueType().isVector() &&
23379 "vector select expects a vector selector!");
23381 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23382 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23384 // Try invert the condition if true value is not all 1s and false value
23386 if (!TValIsAllOnes && !FValIsAllZeros &&
23387 // Check if the selector will be produced by CMPP*/PCMP*
23388 Cond.getOpcode() == ISD::SETCC &&
23389 // Check if SETCC has already been promoted
23390 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23391 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23392 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23394 if (TValIsAllZeros || FValIsAllOnes) {
23395 SDValue CC = Cond.getOperand(2);
23396 ISD::CondCode NewCC =
23397 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23398 Cond.getOperand(0).getValueType().isInteger());
23399 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23400 std::swap(LHS, RHS);
23401 TValIsAllOnes = FValIsAllOnes;
23402 FValIsAllZeros = TValIsAllZeros;
23406 if (TValIsAllOnes || FValIsAllZeros) {
23409 if (TValIsAllOnes && FValIsAllZeros)
23411 else if (TValIsAllOnes)
23412 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23413 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23414 else if (FValIsAllZeros)
23415 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23416 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23418 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23422 // If we know that this node is legal then we know that it is going to be
23423 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23424 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23425 // to simplify previous instructions.
23426 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23427 !DCI.isBeforeLegalize() &&
23428 // We explicitly check against v8i16 and v16i16 because, although
23429 // they're marked as Custom, they might only be legal when Cond is a
23430 // build_vector of constants. This will be taken care in a later
23432 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23433 VT != MVT::v8i16) &&
23434 // Don't optimize vector of constants. Those are handled by
23435 // the generic code and all the bits must be properly set for
23436 // the generic optimizer.
23437 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23438 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23440 // Don't optimize vector selects that map to mask-registers.
23444 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23445 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23447 APInt KnownZero, KnownOne;
23448 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23449 DCI.isBeforeLegalizeOps());
23450 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23451 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23453 // If we changed the computation somewhere in the DAG, this change
23454 // will affect all users of Cond.
23455 // Make sure it is fine and update all the nodes so that we do not
23456 // use the generic VSELECT anymore. Otherwise, we may perform
23457 // wrong optimizations as we messed up with the actual expectation
23458 // for the vector boolean values.
23459 if (Cond != TLO.Old) {
23460 // Check all uses of that condition operand to check whether it will be
23461 // consumed by non-BLEND instructions, which may depend on all bits are
23463 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23465 if (I->getOpcode() != ISD::VSELECT)
23466 // TODO: Add other opcodes eventually lowered into BLEND.
23469 // Update all the users of the condition, before committing the change,
23470 // so that the VSELECT optimizations that expect the correct vector
23471 // boolean value will not be triggered.
23472 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23474 DAG.ReplaceAllUsesOfValueWith(
23476 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23477 Cond, I->getOperand(1), I->getOperand(2)));
23478 DCI.CommitTargetLoweringOpt(TLO);
23481 // At this point, only Cond is changed. Change the condition
23482 // just for N to keep the opportunity to optimize all other
23483 // users their own way.
23484 DAG.ReplaceAllUsesOfValueWith(
23486 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23487 TLO.New, N->getOperand(1), N->getOperand(2)));
23492 // We should generate an X86ISD::BLENDI from a vselect if its argument
23493 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23494 // constants. This specific pattern gets generated when we split a
23495 // selector for a 512 bit vector in a machine without AVX512 (but with
23496 // 256-bit vectors), during legalization:
23498 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23500 // Iff we find this pattern and the build_vectors are built from
23501 // constants, we translate the vselect into a shuffle_vector that we
23502 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23503 if ((N->getOpcode() == ISD::VSELECT ||
23504 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23505 !DCI.isBeforeLegalize()) {
23506 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23507 if (Shuffle.getNode())
23514 // Check whether a boolean test is testing a boolean value generated by
23515 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23518 // Simplify the following patterns:
23519 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23520 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23521 // to (Op EFLAGS Cond)
23523 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23524 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23525 // to (Op EFLAGS !Cond)
23527 // where Op could be BRCOND or CMOV.
23529 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23530 // Quit if not CMP and SUB with its value result used.
23531 if (Cmp.getOpcode() != X86ISD::CMP &&
23532 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23535 // Quit if not used as a boolean value.
23536 if (CC != X86::COND_E && CC != X86::COND_NE)
23539 // Check CMP operands. One of them should be 0 or 1 and the other should be
23540 // an SetCC or extended from it.
23541 SDValue Op1 = Cmp.getOperand(0);
23542 SDValue Op2 = Cmp.getOperand(1);
23545 const ConstantSDNode* C = nullptr;
23546 bool needOppositeCond = (CC == X86::COND_E);
23547 bool checkAgainstTrue = false; // Is it a comparison against 1?
23549 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23551 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23553 else // Quit if all operands are not constants.
23556 if (C->getZExtValue() == 1) {
23557 needOppositeCond = !needOppositeCond;
23558 checkAgainstTrue = true;
23559 } else if (C->getZExtValue() != 0)
23560 // Quit if the constant is neither 0 or 1.
23563 bool truncatedToBoolWithAnd = false;
23564 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23565 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23566 SetCC.getOpcode() == ISD::TRUNCATE ||
23567 SetCC.getOpcode() == ISD::AND) {
23568 if (SetCC.getOpcode() == ISD::AND) {
23570 ConstantSDNode *CS;
23571 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23572 CS->getZExtValue() == 1)
23574 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23575 CS->getZExtValue() == 1)
23579 SetCC = SetCC.getOperand(OpIdx);
23580 truncatedToBoolWithAnd = true;
23582 SetCC = SetCC.getOperand(0);
23585 switch (SetCC.getOpcode()) {
23586 case X86ISD::SETCC_CARRY:
23587 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23588 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23589 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23590 // truncated to i1 using 'and'.
23591 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23593 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23594 "Invalid use of SETCC_CARRY!");
23596 case X86ISD::SETCC:
23597 // Set the condition code or opposite one if necessary.
23598 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23599 if (needOppositeCond)
23600 CC = X86::GetOppositeBranchCondition(CC);
23601 return SetCC.getOperand(1);
23602 case X86ISD::CMOV: {
23603 // Check whether false/true value has canonical one, i.e. 0 or 1.
23604 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23605 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23606 // Quit if true value is not a constant.
23609 // Quit if false value is not a constant.
23611 SDValue Op = SetCC.getOperand(0);
23612 // Skip 'zext' or 'trunc' node.
23613 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23614 Op.getOpcode() == ISD::TRUNCATE)
23615 Op = Op.getOperand(0);
23616 // A special case for rdrand/rdseed, where 0 is set if false cond is
23618 if ((Op.getOpcode() != X86ISD::RDRAND &&
23619 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23622 // Quit if false value is not the constant 0 or 1.
23623 bool FValIsFalse = true;
23624 if (FVal && FVal->getZExtValue() != 0) {
23625 if (FVal->getZExtValue() != 1)
23627 // If FVal is 1, opposite cond is needed.
23628 needOppositeCond = !needOppositeCond;
23629 FValIsFalse = false;
23631 // Quit if TVal is not the constant opposite of FVal.
23632 if (FValIsFalse && TVal->getZExtValue() != 1)
23634 if (!FValIsFalse && TVal->getZExtValue() != 0)
23636 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23637 if (needOppositeCond)
23638 CC = X86::GetOppositeBranchCondition(CC);
23639 return SetCC.getOperand(3);
23646 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23647 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23648 TargetLowering::DAGCombinerInfo &DCI,
23649 const X86Subtarget *Subtarget) {
23652 // If the flag operand isn't dead, don't touch this CMOV.
23653 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23656 SDValue FalseOp = N->getOperand(0);
23657 SDValue TrueOp = N->getOperand(1);
23658 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23659 SDValue Cond = N->getOperand(3);
23661 if (CC == X86::COND_E || CC == X86::COND_NE) {
23662 switch (Cond.getOpcode()) {
23666 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23667 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23668 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23674 Flags = checkBoolTestSetCCCombine(Cond, CC);
23675 if (Flags.getNode() &&
23676 // Extra check as FCMOV only supports a subset of X86 cond.
23677 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23678 SDValue Ops[] = { FalseOp, TrueOp,
23679 DAG.getConstant(CC, MVT::i8), Flags };
23680 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23683 // If this is a select between two integer constants, try to do some
23684 // optimizations. Note that the operands are ordered the opposite of SELECT
23686 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23687 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23688 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23689 // larger than FalseC (the false value).
23690 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23691 CC = X86::GetOppositeBranchCondition(CC);
23692 std::swap(TrueC, FalseC);
23693 std::swap(TrueOp, FalseOp);
23696 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23697 // This is efficient for any integer data type (including i8/i16) and
23699 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23700 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23701 DAG.getConstant(CC, MVT::i8), Cond);
23703 // Zero extend the condition if needed.
23704 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23706 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23707 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23708 DAG.getConstant(ShAmt, MVT::i8));
23709 if (N->getNumValues() == 2) // Dead flag value?
23710 return DCI.CombineTo(N, Cond, SDValue());
23714 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23715 // for any integer data type, including i8/i16.
23716 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23717 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23718 DAG.getConstant(CC, MVT::i8), Cond);
23720 // Zero extend the condition if needed.
23721 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23722 FalseC->getValueType(0), Cond);
23723 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23724 SDValue(FalseC, 0));
23726 if (N->getNumValues() == 2) // Dead flag value?
23727 return DCI.CombineTo(N, Cond, SDValue());
23731 // Optimize cases that will turn into an LEA instruction. This requires
23732 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23733 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23734 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23735 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23737 bool isFastMultiplier = false;
23739 switch ((unsigned char)Diff) {
23741 case 1: // result = add base, cond
23742 case 2: // result = lea base( , cond*2)
23743 case 3: // result = lea base(cond, cond*2)
23744 case 4: // result = lea base( , cond*4)
23745 case 5: // result = lea base(cond, cond*4)
23746 case 8: // result = lea base( , cond*8)
23747 case 9: // result = lea base(cond, cond*8)
23748 isFastMultiplier = true;
23753 if (isFastMultiplier) {
23754 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23755 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23756 DAG.getConstant(CC, MVT::i8), Cond);
23757 // Zero extend the condition if needed.
23758 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23760 // Scale the condition by the difference.
23762 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23763 DAG.getConstant(Diff, Cond.getValueType()));
23765 // Add the base if non-zero.
23766 if (FalseC->getAPIntValue() != 0)
23767 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23768 SDValue(FalseC, 0));
23769 if (N->getNumValues() == 2) // Dead flag value?
23770 return DCI.CombineTo(N, Cond, SDValue());
23777 // Handle these cases:
23778 // (select (x != c), e, c) -> select (x != c), e, x),
23779 // (select (x == c), c, e) -> select (x == c), x, e)
23780 // where the c is an integer constant, and the "select" is the combination
23781 // of CMOV and CMP.
23783 // The rationale for this change is that the conditional-move from a constant
23784 // needs two instructions, however, conditional-move from a register needs
23785 // only one instruction.
23787 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23788 // some instruction-combining opportunities. This opt needs to be
23789 // postponed as late as possible.
23791 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23792 // the DCI.xxxx conditions are provided to postpone the optimization as
23793 // late as possible.
23795 ConstantSDNode *CmpAgainst = nullptr;
23796 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23797 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23798 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23800 if (CC == X86::COND_NE &&
23801 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23802 CC = X86::GetOppositeBranchCondition(CC);
23803 std::swap(TrueOp, FalseOp);
23806 if (CC == X86::COND_E &&
23807 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23808 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23809 DAG.getConstant(CC, MVT::i8), Cond };
23810 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23818 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23819 const X86Subtarget *Subtarget) {
23820 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23822 default: return SDValue();
23823 // SSE/AVX/AVX2 blend intrinsics.
23824 case Intrinsic::x86_avx2_pblendvb:
23825 case Intrinsic::x86_avx2_pblendw:
23826 case Intrinsic::x86_avx2_pblendd_128:
23827 case Intrinsic::x86_avx2_pblendd_256:
23828 // Don't try to simplify this intrinsic if we don't have AVX2.
23829 if (!Subtarget->hasAVX2())
23832 case Intrinsic::x86_avx_blend_pd_256:
23833 case Intrinsic::x86_avx_blend_ps_256:
23834 case Intrinsic::x86_avx_blendv_pd_256:
23835 case Intrinsic::x86_avx_blendv_ps_256:
23836 // Don't try to simplify this intrinsic if we don't have AVX.
23837 if (!Subtarget->hasAVX())
23840 case Intrinsic::x86_sse41_pblendw:
23841 case Intrinsic::x86_sse41_blendpd:
23842 case Intrinsic::x86_sse41_blendps:
23843 case Intrinsic::x86_sse41_blendvps:
23844 case Intrinsic::x86_sse41_blendvpd:
23845 case Intrinsic::x86_sse41_pblendvb: {
23846 SDValue Op0 = N->getOperand(1);
23847 SDValue Op1 = N->getOperand(2);
23848 SDValue Mask = N->getOperand(3);
23850 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23851 if (!Subtarget->hasSSE41())
23854 // fold (blend A, A, Mask) -> A
23857 // fold (blend A, B, allZeros) -> A
23858 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23860 // fold (blend A, B, allOnes) -> B
23861 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23864 // Simplify the case where the mask is a constant i32 value.
23865 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23866 if (C->isNullValue())
23868 if (C->isAllOnesValue())
23875 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23876 case Intrinsic::x86_sse2_psrai_w:
23877 case Intrinsic::x86_sse2_psrai_d:
23878 case Intrinsic::x86_avx2_psrai_w:
23879 case Intrinsic::x86_avx2_psrai_d:
23880 case Intrinsic::x86_sse2_psra_w:
23881 case Intrinsic::x86_sse2_psra_d:
23882 case Intrinsic::x86_avx2_psra_w:
23883 case Intrinsic::x86_avx2_psra_d: {
23884 SDValue Op0 = N->getOperand(1);
23885 SDValue Op1 = N->getOperand(2);
23886 EVT VT = Op0.getValueType();
23887 assert(VT.isVector() && "Expected a vector type!");
23889 if (isa<BuildVectorSDNode>(Op1))
23890 Op1 = Op1.getOperand(0);
23892 if (!isa<ConstantSDNode>(Op1))
23895 EVT SVT = VT.getVectorElementType();
23896 unsigned SVTBits = SVT.getSizeInBits();
23898 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23899 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23900 uint64_t ShAmt = C.getZExtValue();
23902 // Don't try to convert this shift into a ISD::SRA if the shift
23903 // count is bigger than or equal to the element size.
23904 if (ShAmt >= SVTBits)
23907 // Trivial case: if the shift count is zero, then fold this
23908 // into the first operand.
23912 // Replace this packed shift intrinsic with a target independent
23914 SDValue Splat = DAG.getConstant(C, VT);
23915 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23920 /// PerformMulCombine - Optimize a single multiply with constant into two
23921 /// in order to implement it with two cheaper instructions, e.g.
23922 /// LEA + SHL, LEA + LEA.
23923 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23924 TargetLowering::DAGCombinerInfo &DCI) {
23925 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23928 EVT VT = N->getValueType(0);
23929 if (VT != MVT::i64)
23932 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23935 uint64_t MulAmt = C->getZExtValue();
23936 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23939 uint64_t MulAmt1 = 0;
23940 uint64_t MulAmt2 = 0;
23941 if ((MulAmt % 9) == 0) {
23943 MulAmt2 = MulAmt / 9;
23944 } else if ((MulAmt % 5) == 0) {
23946 MulAmt2 = MulAmt / 5;
23947 } else if ((MulAmt % 3) == 0) {
23949 MulAmt2 = MulAmt / 3;
23952 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23955 if (isPowerOf2_64(MulAmt2) &&
23956 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23957 // If second multiplifer is pow2, issue it first. We want the multiply by
23958 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23960 std::swap(MulAmt1, MulAmt2);
23963 if (isPowerOf2_64(MulAmt1))
23964 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23965 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23967 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23968 DAG.getConstant(MulAmt1, VT));
23970 if (isPowerOf2_64(MulAmt2))
23971 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23972 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23974 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23975 DAG.getConstant(MulAmt2, VT));
23977 // Do not add new nodes to DAG combiner worklist.
23978 DCI.CombineTo(N, NewMul, false);
23983 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23984 SDValue N0 = N->getOperand(0);
23985 SDValue N1 = N->getOperand(1);
23986 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23987 EVT VT = N0.getValueType();
23989 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23990 // since the result of setcc_c is all zero's or all ones.
23991 if (VT.isInteger() && !VT.isVector() &&
23992 N1C && N0.getOpcode() == ISD::AND &&
23993 N0.getOperand(1).getOpcode() == ISD::Constant) {
23994 SDValue N00 = N0.getOperand(0);
23995 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23996 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23997 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23998 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23999 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24000 APInt ShAmt = N1C->getAPIntValue();
24001 Mask = Mask.shl(ShAmt);
24003 return DAG.getNode(ISD::AND, SDLoc(N), VT,
24004 N00, DAG.getConstant(Mask, VT));
24008 // Hardware support for vector shifts is sparse which makes us scalarize the
24009 // vector operations in many cases. Also, on sandybridge ADD is faster than
24011 // (shl V, 1) -> add V,V
24012 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24013 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24014 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24015 // We shift all of the values by one. In many cases we do not have
24016 // hardware support for this operation. This is better expressed as an ADD
24018 if (N1SplatC->getZExtValue() == 1)
24019 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24025 /// \brief Returns a vector of 0s if the node in input is a vector logical
24026 /// shift by a constant amount which is known to be bigger than or equal
24027 /// to the vector element size in bits.
24028 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24029 const X86Subtarget *Subtarget) {
24030 EVT VT = N->getValueType(0);
24032 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24033 (!Subtarget->hasInt256() ||
24034 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24037 SDValue Amt = N->getOperand(1);
24039 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24040 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24041 APInt ShiftAmt = AmtSplat->getAPIntValue();
24042 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24044 // SSE2/AVX2 logical shifts always return a vector of 0s
24045 // if the shift amount is bigger than or equal to
24046 // the element size. The constant shift amount will be
24047 // encoded as a 8-bit immediate.
24048 if (ShiftAmt.trunc(8).uge(MaxAmount))
24049 return getZeroVector(VT, Subtarget, DAG, DL);
24055 /// PerformShiftCombine - Combine shifts.
24056 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24057 TargetLowering::DAGCombinerInfo &DCI,
24058 const X86Subtarget *Subtarget) {
24059 if (N->getOpcode() == ISD::SHL) {
24060 SDValue V = PerformSHLCombine(N, DAG);
24061 if (V.getNode()) return V;
24064 if (N->getOpcode() != ISD::SRA) {
24065 // Try to fold this logical shift into a zero vector.
24066 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24067 if (V.getNode()) return V;
24073 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24074 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24075 // and friends. Likewise for OR -> CMPNEQSS.
24076 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24077 TargetLowering::DAGCombinerInfo &DCI,
24078 const X86Subtarget *Subtarget) {
24081 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24082 // we're requiring SSE2 for both.
24083 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24084 SDValue N0 = N->getOperand(0);
24085 SDValue N1 = N->getOperand(1);
24086 SDValue CMP0 = N0->getOperand(1);
24087 SDValue CMP1 = N1->getOperand(1);
24090 // The SETCCs should both refer to the same CMP.
24091 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24094 SDValue CMP00 = CMP0->getOperand(0);
24095 SDValue CMP01 = CMP0->getOperand(1);
24096 EVT VT = CMP00.getValueType();
24098 if (VT == MVT::f32 || VT == MVT::f64) {
24099 bool ExpectingFlags = false;
24100 // Check for any users that want flags:
24101 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24102 !ExpectingFlags && UI != UE; ++UI)
24103 switch (UI->getOpcode()) {
24108 ExpectingFlags = true;
24110 case ISD::CopyToReg:
24111 case ISD::SIGN_EXTEND:
24112 case ISD::ZERO_EXTEND:
24113 case ISD::ANY_EXTEND:
24117 if (!ExpectingFlags) {
24118 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24119 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24121 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24122 X86::CondCode tmp = cc0;
24127 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24128 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24129 // FIXME: need symbolic constants for these magic numbers.
24130 // See X86ATTInstPrinter.cpp:printSSECC().
24131 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24132 if (Subtarget->hasAVX512()) {
24133 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24134 CMP01, DAG.getConstant(x86cc, MVT::i8));
24135 if (N->getValueType(0) != MVT::i1)
24136 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24140 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24141 CMP00.getValueType(), CMP00, CMP01,
24142 DAG.getConstant(x86cc, MVT::i8));
24144 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24145 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24147 if (is64BitFP && !Subtarget->is64Bit()) {
24148 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24149 // 64-bit integer, since that's not a legal type. Since
24150 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24151 // bits, but can do this little dance to extract the lowest 32 bits
24152 // and work with those going forward.
24153 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24155 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24157 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24158 Vector32, DAG.getIntPtrConstant(0));
24162 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24163 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24164 DAG.getConstant(1, IntVT));
24165 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24166 return OneBitOfTruth;
24174 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24175 /// so it can be folded inside ANDNP.
24176 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24177 EVT VT = N->getValueType(0);
24179 // Match direct AllOnes for 128 and 256-bit vectors
24180 if (ISD::isBuildVectorAllOnes(N))
24183 // Look through a bit convert.
24184 if (N->getOpcode() == ISD::BITCAST)
24185 N = N->getOperand(0).getNode();
24187 // Sometimes the operand may come from a insert_subvector building a 256-bit
24189 if (VT.is256BitVector() &&
24190 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24191 SDValue V1 = N->getOperand(0);
24192 SDValue V2 = N->getOperand(1);
24194 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24195 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24196 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24197 ISD::isBuildVectorAllOnes(V2.getNode()))
24204 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24205 // register. In most cases we actually compare or select YMM-sized registers
24206 // and mixing the two types creates horrible code. This method optimizes
24207 // some of the transition sequences.
24208 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24209 TargetLowering::DAGCombinerInfo &DCI,
24210 const X86Subtarget *Subtarget) {
24211 EVT VT = N->getValueType(0);
24212 if (!VT.is256BitVector())
24215 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24216 N->getOpcode() == ISD::ZERO_EXTEND ||
24217 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24219 SDValue Narrow = N->getOperand(0);
24220 EVT NarrowVT = Narrow->getValueType(0);
24221 if (!NarrowVT.is128BitVector())
24224 if (Narrow->getOpcode() != ISD::XOR &&
24225 Narrow->getOpcode() != ISD::AND &&
24226 Narrow->getOpcode() != ISD::OR)
24229 SDValue N0 = Narrow->getOperand(0);
24230 SDValue N1 = Narrow->getOperand(1);
24233 // The Left side has to be a trunc.
24234 if (N0.getOpcode() != ISD::TRUNCATE)
24237 // The type of the truncated inputs.
24238 EVT WideVT = N0->getOperand(0)->getValueType(0);
24242 // The right side has to be a 'trunc' or a constant vector.
24243 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24244 ConstantSDNode *RHSConstSplat = nullptr;
24245 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24246 RHSConstSplat = RHSBV->getConstantSplatNode();
24247 if (!RHSTrunc && !RHSConstSplat)
24250 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24252 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24255 // Set N0 and N1 to hold the inputs to the new wide operation.
24256 N0 = N0->getOperand(0);
24257 if (RHSConstSplat) {
24258 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24259 SDValue(RHSConstSplat, 0));
24260 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24261 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24262 } else if (RHSTrunc) {
24263 N1 = N1->getOperand(0);
24266 // Generate the wide operation.
24267 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24268 unsigned Opcode = N->getOpcode();
24270 case ISD::ANY_EXTEND:
24272 case ISD::ZERO_EXTEND: {
24273 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24274 APInt Mask = APInt::getAllOnesValue(InBits);
24275 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24276 return DAG.getNode(ISD::AND, DL, VT,
24277 Op, DAG.getConstant(Mask, VT));
24279 case ISD::SIGN_EXTEND:
24280 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24281 Op, DAG.getValueType(NarrowVT));
24283 llvm_unreachable("Unexpected opcode");
24287 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24288 TargetLowering::DAGCombinerInfo &DCI,
24289 const X86Subtarget *Subtarget) {
24290 EVT VT = N->getValueType(0);
24291 if (DCI.isBeforeLegalizeOps())
24294 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24298 // Create BEXTR instructions
24299 // BEXTR is ((X >> imm) & (2**size-1))
24300 if (VT == MVT::i32 || VT == MVT::i64) {
24301 SDValue N0 = N->getOperand(0);
24302 SDValue N1 = N->getOperand(1);
24305 // Check for BEXTR.
24306 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24307 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24308 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24309 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24310 if (MaskNode && ShiftNode) {
24311 uint64_t Mask = MaskNode->getZExtValue();
24312 uint64_t Shift = ShiftNode->getZExtValue();
24313 if (isMask_64(Mask)) {
24314 uint64_t MaskSize = CountPopulation_64(Mask);
24315 if (Shift + MaskSize <= VT.getSizeInBits())
24316 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24317 DAG.getConstant(Shift | (MaskSize << 8), VT));
24325 // Want to form ANDNP nodes:
24326 // 1) In the hopes of then easily combining them with OR and AND nodes
24327 // to form PBLEND/PSIGN.
24328 // 2) To match ANDN packed intrinsics
24329 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24332 SDValue N0 = N->getOperand(0);
24333 SDValue N1 = N->getOperand(1);
24336 // Check LHS for vnot
24337 if (N0.getOpcode() == ISD::XOR &&
24338 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24339 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24340 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24342 // Check RHS for vnot
24343 if (N1.getOpcode() == ISD::XOR &&
24344 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24345 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24346 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24351 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24352 TargetLowering::DAGCombinerInfo &DCI,
24353 const X86Subtarget *Subtarget) {
24354 if (DCI.isBeforeLegalizeOps())
24357 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24361 SDValue N0 = N->getOperand(0);
24362 SDValue N1 = N->getOperand(1);
24363 EVT VT = N->getValueType(0);
24365 // look for psign/blend
24366 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24367 if (!Subtarget->hasSSSE3() ||
24368 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24371 // Canonicalize pandn to RHS
24372 if (N0.getOpcode() == X86ISD::ANDNP)
24374 // or (and (m, y), (pandn m, x))
24375 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24376 SDValue Mask = N1.getOperand(0);
24377 SDValue X = N1.getOperand(1);
24379 if (N0.getOperand(0) == Mask)
24380 Y = N0.getOperand(1);
24381 if (N0.getOperand(1) == Mask)
24382 Y = N0.getOperand(0);
24384 // Check to see if the mask appeared in both the AND and ANDNP and
24388 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24389 // Look through mask bitcast.
24390 if (Mask.getOpcode() == ISD::BITCAST)
24391 Mask = Mask.getOperand(0);
24392 if (X.getOpcode() == ISD::BITCAST)
24393 X = X.getOperand(0);
24394 if (Y.getOpcode() == ISD::BITCAST)
24395 Y = Y.getOperand(0);
24397 EVT MaskVT = Mask.getValueType();
24399 // Validate that the Mask operand is a vector sra node.
24400 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24401 // there is no psrai.b
24402 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24403 unsigned SraAmt = ~0;
24404 if (Mask.getOpcode() == ISD::SRA) {
24405 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24406 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24407 SraAmt = AmtConst->getZExtValue();
24408 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24409 SDValue SraC = Mask.getOperand(1);
24410 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24412 if ((SraAmt + 1) != EltBits)
24417 // Now we know we at least have a plendvb with the mask val. See if
24418 // we can form a psignb/w/d.
24419 // psign = x.type == y.type == mask.type && y = sub(0, x);
24420 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24421 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24422 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24423 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24424 "Unsupported VT for PSIGN");
24425 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24426 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24428 // PBLENDVB only available on SSE 4.1
24429 if (!Subtarget->hasSSE41())
24432 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24434 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24435 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24436 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24437 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24438 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24442 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24445 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24446 MachineFunction &MF = DAG.getMachineFunction();
24447 bool OptForSize = MF.getFunction()->getAttributes().
24448 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24450 // SHLD/SHRD instructions have lower register pressure, but on some
24451 // platforms they have higher latency than the equivalent
24452 // series of shifts/or that would otherwise be generated.
24453 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24454 // have higher latencies and we are not optimizing for size.
24455 if (!OptForSize && Subtarget->isSHLDSlow())
24458 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24460 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24462 if (!N0.hasOneUse() || !N1.hasOneUse())
24465 SDValue ShAmt0 = N0.getOperand(1);
24466 if (ShAmt0.getValueType() != MVT::i8)
24468 SDValue ShAmt1 = N1.getOperand(1);
24469 if (ShAmt1.getValueType() != MVT::i8)
24471 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24472 ShAmt0 = ShAmt0.getOperand(0);
24473 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24474 ShAmt1 = ShAmt1.getOperand(0);
24477 unsigned Opc = X86ISD::SHLD;
24478 SDValue Op0 = N0.getOperand(0);
24479 SDValue Op1 = N1.getOperand(0);
24480 if (ShAmt0.getOpcode() == ISD::SUB) {
24481 Opc = X86ISD::SHRD;
24482 std::swap(Op0, Op1);
24483 std::swap(ShAmt0, ShAmt1);
24486 unsigned Bits = VT.getSizeInBits();
24487 if (ShAmt1.getOpcode() == ISD::SUB) {
24488 SDValue Sum = ShAmt1.getOperand(0);
24489 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24490 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24491 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24492 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24493 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24494 return DAG.getNode(Opc, DL, VT,
24496 DAG.getNode(ISD::TRUNCATE, DL,
24499 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24500 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24502 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24503 return DAG.getNode(Opc, DL, VT,
24504 N0.getOperand(0), N1.getOperand(0),
24505 DAG.getNode(ISD::TRUNCATE, DL,
24512 // Generate NEG and CMOV for integer abs.
24513 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24514 EVT VT = N->getValueType(0);
24516 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24517 // 8-bit integer abs to NEG and CMOV.
24518 if (VT.isInteger() && VT.getSizeInBits() == 8)
24521 SDValue N0 = N->getOperand(0);
24522 SDValue N1 = N->getOperand(1);
24525 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24526 // and change it to SUB and CMOV.
24527 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24528 N0.getOpcode() == ISD::ADD &&
24529 N0.getOperand(1) == N1 &&
24530 N1.getOpcode() == ISD::SRA &&
24531 N1.getOperand(0) == N0.getOperand(0))
24532 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24533 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24534 // Generate SUB & CMOV.
24535 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24536 DAG.getConstant(0, VT), N0.getOperand(0));
24538 SDValue Ops[] = { N0.getOperand(0), Neg,
24539 DAG.getConstant(X86::COND_GE, MVT::i8),
24540 SDValue(Neg.getNode(), 1) };
24541 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24546 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24547 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24548 TargetLowering::DAGCombinerInfo &DCI,
24549 const X86Subtarget *Subtarget) {
24550 if (DCI.isBeforeLegalizeOps())
24553 if (Subtarget->hasCMov()) {
24554 SDValue RV = performIntegerAbsCombine(N, DAG);
24562 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24563 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24564 TargetLowering::DAGCombinerInfo &DCI,
24565 const X86Subtarget *Subtarget) {
24566 LoadSDNode *Ld = cast<LoadSDNode>(N);
24567 EVT RegVT = Ld->getValueType(0);
24568 EVT MemVT = Ld->getMemoryVT();
24570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24572 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24573 // into two 16-byte operations.
24574 ISD::LoadExtType Ext = Ld->getExtensionType();
24575 unsigned Alignment = Ld->getAlignment();
24576 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24577 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24578 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24579 unsigned NumElems = RegVT.getVectorNumElements();
24583 SDValue Ptr = Ld->getBasePtr();
24584 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24586 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24588 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24589 Ld->getPointerInfo(), Ld->isVolatile(),
24590 Ld->isNonTemporal(), Ld->isInvariant(),
24592 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24593 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24594 Ld->getPointerInfo(), Ld->isVolatile(),
24595 Ld->isNonTemporal(), Ld->isInvariant(),
24596 std::min(16U, Alignment));
24597 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24599 Load2.getValue(1));
24601 SDValue NewVec = DAG.getUNDEF(RegVT);
24602 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24603 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24604 return DCI.CombineTo(N, NewVec, TF, true);
24610 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24611 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24612 const X86Subtarget *Subtarget) {
24613 StoreSDNode *St = cast<StoreSDNode>(N);
24614 EVT VT = St->getValue().getValueType();
24615 EVT StVT = St->getMemoryVT();
24617 SDValue StoredVal = St->getOperand(1);
24618 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24620 // If we are saving a concatenation of two XMM registers and 32-byte stores
24621 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24622 unsigned Alignment = St->getAlignment();
24623 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24624 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24625 StVT == VT && !IsAligned) {
24626 unsigned NumElems = VT.getVectorNumElements();
24630 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24631 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24633 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24634 SDValue Ptr0 = St->getBasePtr();
24635 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24637 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24638 St->getPointerInfo(), St->isVolatile(),
24639 St->isNonTemporal(), Alignment);
24640 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24641 St->getPointerInfo(), St->isVolatile(),
24642 St->isNonTemporal(),
24643 std::min(16U, Alignment));
24644 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24647 // Optimize trunc store (of multiple scalars) to shuffle and store.
24648 // First, pack all of the elements in one place. Next, store to memory
24649 // in fewer chunks.
24650 if (St->isTruncatingStore() && VT.isVector()) {
24651 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24652 unsigned NumElems = VT.getVectorNumElements();
24653 assert(StVT != VT && "Cannot truncate to the same type");
24654 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24655 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24657 // From, To sizes and ElemCount must be pow of two
24658 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24659 // We are going to use the original vector elt for storing.
24660 // Accumulated smaller vector elements must be a multiple of the store size.
24661 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24663 unsigned SizeRatio = FromSz / ToSz;
24665 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24667 // Create a type on which we perform the shuffle
24668 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24669 StVT.getScalarType(), NumElems*SizeRatio);
24671 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24673 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24674 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24675 for (unsigned i = 0; i != NumElems; ++i)
24676 ShuffleVec[i] = i * SizeRatio;
24678 // Can't shuffle using an illegal type.
24679 if (!TLI.isTypeLegal(WideVecVT))
24682 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24683 DAG.getUNDEF(WideVecVT),
24685 // At this point all of the data is stored at the bottom of the
24686 // register. We now need to save it to mem.
24688 // Find the largest store unit
24689 MVT StoreType = MVT::i8;
24690 for (MVT Tp : MVT::integer_valuetypes()) {
24691 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24695 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24696 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24697 (64 <= NumElems * ToSz))
24698 StoreType = MVT::f64;
24700 // Bitcast the original vector into a vector of store-size units
24701 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24702 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24703 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24704 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24705 SmallVector<SDValue, 8> Chains;
24706 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24707 TLI.getPointerTy());
24708 SDValue Ptr = St->getBasePtr();
24710 // Perform one or more big stores into memory.
24711 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24712 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24713 StoreType, ShuffWide,
24714 DAG.getIntPtrConstant(i));
24715 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24716 St->getPointerInfo(), St->isVolatile(),
24717 St->isNonTemporal(), St->getAlignment());
24718 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24719 Chains.push_back(Ch);
24722 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24725 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24726 // the FP state in cases where an emms may be missing.
24727 // A preferable solution to the general problem is to figure out the right
24728 // places to insert EMMS. This qualifies as a quick hack.
24730 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24731 if (VT.getSizeInBits() != 64)
24734 const Function *F = DAG.getMachineFunction().getFunction();
24735 bool NoImplicitFloatOps = F->getAttributes().
24736 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24737 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24738 && Subtarget->hasSSE2();
24739 if ((VT.isVector() ||
24740 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24741 isa<LoadSDNode>(St->getValue()) &&
24742 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24743 St->getChain().hasOneUse() && !St->isVolatile()) {
24744 SDNode* LdVal = St->getValue().getNode();
24745 LoadSDNode *Ld = nullptr;
24746 int TokenFactorIndex = -1;
24747 SmallVector<SDValue, 8> Ops;
24748 SDNode* ChainVal = St->getChain().getNode();
24749 // Must be a store of a load. We currently handle two cases: the load
24750 // is a direct child, and it's under an intervening TokenFactor. It is
24751 // possible to dig deeper under nested TokenFactors.
24752 if (ChainVal == LdVal)
24753 Ld = cast<LoadSDNode>(St->getChain());
24754 else if (St->getValue().hasOneUse() &&
24755 ChainVal->getOpcode() == ISD::TokenFactor) {
24756 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24757 if (ChainVal->getOperand(i).getNode() == LdVal) {
24758 TokenFactorIndex = i;
24759 Ld = cast<LoadSDNode>(St->getValue());
24761 Ops.push_back(ChainVal->getOperand(i));
24765 if (!Ld || !ISD::isNormalLoad(Ld))
24768 // If this is not the MMX case, i.e. we are just turning i64 load/store
24769 // into f64 load/store, avoid the transformation if there are multiple
24770 // uses of the loaded value.
24771 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24776 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24777 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24779 if (Subtarget->is64Bit() || F64IsLegal) {
24780 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24781 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24782 Ld->getPointerInfo(), Ld->isVolatile(),
24783 Ld->isNonTemporal(), Ld->isInvariant(),
24784 Ld->getAlignment());
24785 SDValue NewChain = NewLd.getValue(1);
24786 if (TokenFactorIndex != -1) {
24787 Ops.push_back(NewChain);
24788 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24790 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24791 St->getPointerInfo(),
24792 St->isVolatile(), St->isNonTemporal(),
24793 St->getAlignment());
24796 // Otherwise, lower to two pairs of 32-bit loads / stores.
24797 SDValue LoAddr = Ld->getBasePtr();
24798 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24799 DAG.getConstant(4, MVT::i32));
24801 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24802 Ld->getPointerInfo(),
24803 Ld->isVolatile(), Ld->isNonTemporal(),
24804 Ld->isInvariant(), Ld->getAlignment());
24805 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24806 Ld->getPointerInfo().getWithOffset(4),
24807 Ld->isVolatile(), Ld->isNonTemporal(),
24809 MinAlign(Ld->getAlignment(), 4));
24811 SDValue NewChain = LoLd.getValue(1);
24812 if (TokenFactorIndex != -1) {
24813 Ops.push_back(LoLd);
24814 Ops.push_back(HiLd);
24815 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24818 LoAddr = St->getBasePtr();
24819 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24820 DAG.getConstant(4, MVT::i32));
24822 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24823 St->getPointerInfo(),
24824 St->isVolatile(), St->isNonTemporal(),
24825 St->getAlignment());
24826 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24827 St->getPointerInfo().getWithOffset(4),
24829 St->isNonTemporal(),
24830 MinAlign(St->getAlignment(), 4));
24831 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24836 /// Return 'true' if this vector operation is "horizontal"
24837 /// and return the operands for the horizontal operation in LHS and RHS. A
24838 /// horizontal operation performs the binary operation on successive elements
24839 /// of its first operand, then on successive elements of its second operand,
24840 /// returning the resulting values in a vector. For example, if
24841 /// A = < float a0, float a1, float a2, float a3 >
24843 /// B = < float b0, float b1, float b2, float b3 >
24844 /// then the result of doing a horizontal operation on A and B is
24845 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24846 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24847 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24848 /// set to A, RHS to B, and the routine returns 'true'.
24849 /// Note that the binary operation should have the property that if one of the
24850 /// operands is UNDEF then the result is UNDEF.
24851 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24852 // Look for the following pattern: if
24853 // A = < float a0, float a1, float a2, float a3 >
24854 // B = < float b0, float b1, float b2, float b3 >
24856 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24857 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24858 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24859 // which is A horizontal-op B.
24861 // At least one of the operands should be a vector shuffle.
24862 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24863 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24866 MVT VT = LHS.getSimpleValueType();
24868 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24869 "Unsupported vector type for horizontal add/sub");
24871 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24872 // operate independently on 128-bit lanes.
24873 unsigned NumElts = VT.getVectorNumElements();
24874 unsigned NumLanes = VT.getSizeInBits()/128;
24875 unsigned NumLaneElts = NumElts / NumLanes;
24876 assert((NumLaneElts % 2 == 0) &&
24877 "Vector type should have an even number of elements in each lane");
24878 unsigned HalfLaneElts = NumLaneElts/2;
24880 // View LHS in the form
24881 // LHS = VECTOR_SHUFFLE A, B, LMask
24882 // If LHS is not a shuffle then pretend it is the shuffle
24883 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24884 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24887 SmallVector<int, 16> LMask(NumElts);
24888 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24889 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24890 A = LHS.getOperand(0);
24891 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24892 B = LHS.getOperand(1);
24893 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24894 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24896 if (LHS.getOpcode() != ISD::UNDEF)
24898 for (unsigned i = 0; i != NumElts; ++i)
24902 // Likewise, view RHS in the form
24903 // RHS = VECTOR_SHUFFLE C, D, RMask
24905 SmallVector<int, 16> RMask(NumElts);
24906 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24907 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24908 C = RHS.getOperand(0);
24909 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24910 D = RHS.getOperand(1);
24911 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24912 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24914 if (RHS.getOpcode() != ISD::UNDEF)
24916 for (unsigned i = 0; i != NumElts; ++i)
24920 // Check that the shuffles are both shuffling the same vectors.
24921 if (!(A == C && B == D) && !(A == D && B == C))
24924 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24925 if (!A.getNode() && !B.getNode())
24928 // If A and B occur in reverse order in RHS, then "swap" them (which means
24929 // rewriting the mask).
24931 CommuteVectorShuffleMask(RMask, NumElts);
24933 // At this point LHS and RHS are equivalent to
24934 // LHS = VECTOR_SHUFFLE A, B, LMask
24935 // RHS = VECTOR_SHUFFLE A, B, RMask
24936 // Check that the masks correspond to performing a horizontal operation.
24937 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24938 for (unsigned i = 0; i != NumLaneElts; ++i) {
24939 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24941 // Ignore any UNDEF components.
24942 if (LIdx < 0 || RIdx < 0 ||
24943 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24944 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24947 // Check that successive elements are being operated on. If not, this is
24948 // not a horizontal operation.
24949 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24950 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24951 if (!(LIdx == Index && RIdx == Index + 1) &&
24952 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24957 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24958 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24962 /// Do target-specific dag combines on floating point adds.
24963 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24964 const X86Subtarget *Subtarget) {
24965 EVT VT = N->getValueType(0);
24966 SDValue LHS = N->getOperand(0);
24967 SDValue RHS = N->getOperand(1);
24969 // Try to synthesize horizontal adds from adds of shuffles.
24970 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24971 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24972 isHorizontalBinOp(LHS, RHS, true))
24973 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24977 /// Do target-specific dag combines on floating point subs.
24978 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24979 const X86Subtarget *Subtarget) {
24980 EVT VT = N->getValueType(0);
24981 SDValue LHS = N->getOperand(0);
24982 SDValue RHS = N->getOperand(1);
24984 // Try to synthesize horizontal subs from subs of shuffles.
24985 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24986 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24987 isHorizontalBinOp(LHS, RHS, false))
24988 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24992 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24993 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24994 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24995 // F[X]OR(0.0, x) -> x
24996 // F[X]OR(x, 0.0) -> x
24997 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24998 if (C->getValueAPF().isPosZero())
24999 return N->getOperand(1);
25000 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25001 if (C->getValueAPF().isPosZero())
25002 return N->getOperand(0);
25006 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25007 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25008 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25010 // Only perform optimizations if UnsafeMath is used.
25011 if (!DAG.getTarget().Options.UnsafeFPMath)
25014 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25015 // into FMINC and FMAXC, which are Commutative operations.
25016 unsigned NewOp = 0;
25017 switch (N->getOpcode()) {
25018 default: llvm_unreachable("unknown opcode");
25019 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25020 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25023 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25024 N->getOperand(0), N->getOperand(1));
25027 /// Do target-specific dag combines on X86ISD::FAND nodes.
25028 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25029 // FAND(0.0, x) -> 0.0
25030 // FAND(x, 0.0) -> 0.0
25031 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25032 if (C->getValueAPF().isPosZero())
25033 return N->getOperand(0);
25034 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25035 if (C->getValueAPF().isPosZero())
25036 return N->getOperand(1);
25040 /// Do target-specific dag combines on X86ISD::FANDN nodes
25041 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25042 // FANDN(x, 0.0) -> 0.0
25043 // FANDN(0.0, x) -> x
25044 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25045 if (C->getValueAPF().isPosZero())
25046 return N->getOperand(1);
25047 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25048 if (C->getValueAPF().isPosZero())
25049 return N->getOperand(1);
25053 static SDValue PerformBTCombine(SDNode *N,
25055 TargetLowering::DAGCombinerInfo &DCI) {
25056 // BT ignores high bits in the bit index operand.
25057 SDValue Op1 = N->getOperand(1);
25058 if (Op1.hasOneUse()) {
25059 unsigned BitWidth = Op1.getValueSizeInBits();
25060 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25061 APInt KnownZero, KnownOne;
25062 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25063 !DCI.isBeforeLegalizeOps());
25064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25065 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25066 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25067 DCI.CommitTargetLoweringOpt(TLO);
25072 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25073 SDValue Op = N->getOperand(0);
25074 if (Op.getOpcode() == ISD::BITCAST)
25075 Op = Op.getOperand(0);
25076 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25077 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25078 VT.getVectorElementType().getSizeInBits() ==
25079 OpVT.getVectorElementType().getSizeInBits()) {
25080 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25085 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25086 const X86Subtarget *Subtarget) {
25087 EVT VT = N->getValueType(0);
25088 if (!VT.isVector())
25091 SDValue N0 = N->getOperand(0);
25092 SDValue N1 = N->getOperand(1);
25093 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25096 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25097 // both SSE and AVX2 since there is no sign-extended shift right
25098 // operation on a vector with 64-bit elements.
25099 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25100 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25101 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25102 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25103 SDValue N00 = N0.getOperand(0);
25105 // EXTLOAD has a better solution on AVX2,
25106 // it may be replaced with X86ISD::VSEXT node.
25107 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25108 if (!ISD::isNormalLoad(N00.getNode()))
25111 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25112 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25114 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25120 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25121 TargetLowering::DAGCombinerInfo &DCI,
25122 const X86Subtarget *Subtarget) {
25123 SDValue N0 = N->getOperand(0);
25124 EVT VT = N->getValueType(0);
25126 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25127 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25128 // This exposes the sext to the sdivrem lowering, so that it directly extends
25129 // from AH (which we otherwise need to do contortions to access).
25130 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25131 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25133 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25134 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25135 N0.getOperand(0), N0.getOperand(1));
25136 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25137 return R.getValue(1);
25140 if (!DCI.isBeforeLegalizeOps())
25143 if (!Subtarget->hasFp256())
25146 if (VT.isVector() && VT.getSizeInBits() == 256) {
25147 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25155 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25156 const X86Subtarget* Subtarget) {
25158 EVT VT = N->getValueType(0);
25160 // Let legalize expand this if it isn't a legal type yet.
25161 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25164 EVT ScalarVT = VT.getScalarType();
25165 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25166 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25169 SDValue A = N->getOperand(0);
25170 SDValue B = N->getOperand(1);
25171 SDValue C = N->getOperand(2);
25173 bool NegA = (A.getOpcode() == ISD::FNEG);
25174 bool NegB = (B.getOpcode() == ISD::FNEG);
25175 bool NegC = (C.getOpcode() == ISD::FNEG);
25177 // Negative multiplication when NegA xor NegB
25178 bool NegMul = (NegA != NegB);
25180 A = A.getOperand(0);
25182 B = B.getOperand(0);
25184 C = C.getOperand(0);
25188 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25190 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25192 return DAG.getNode(Opcode, dl, VT, A, B, C);
25195 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25196 TargetLowering::DAGCombinerInfo &DCI,
25197 const X86Subtarget *Subtarget) {
25198 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25199 // (and (i32 x86isd::setcc_carry), 1)
25200 // This eliminates the zext. This transformation is necessary because
25201 // ISD::SETCC is always legalized to i8.
25203 SDValue N0 = N->getOperand(0);
25204 EVT VT = N->getValueType(0);
25206 if (N0.getOpcode() == ISD::AND &&
25208 N0.getOperand(0).hasOneUse()) {
25209 SDValue N00 = N0.getOperand(0);
25210 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25211 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25212 if (!C || C->getZExtValue() != 1)
25214 return DAG.getNode(ISD::AND, dl, VT,
25215 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25216 N00.getOperand(0), N00.getOperand(1)),
25217 DAG.getConstant(1, VT));
25221 if (N0.getOpcode() == ISD::TRUNCATE &&
25223 N0.getOperand(0).hasOneUse()) {
25224 SDValue N00 = N0.getOperand(0);
25225 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25226 return DAG.getNode(ISD::AND, dl, VT,
25227 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25228 N00.getOperand(0), N00.getOperand(1)),
25229 DAG.getConstant(1, VT));
25232 if (VT.is256BitVector()) {
25233 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25238 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25239 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25240 // This exposes the zext to the udivrem lowering, so that it directly extends
25241 // from AH (which we otherwise need to do contortions to access).
25242 if (N0.getOpcode() == ISD::UDIVREM &&
25243 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25244 (VT == MVT::i32 || VT == MVT::i64)) {
25245 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25246 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25247 N0.getOperand(0), N0.getOperand(1));
25248 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25249 return R.getValue(1);
25255 // Optimize x == -y --> x+y == 0
25256 // x != -y --> x+y != 0
25257 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25258 const X86Subtarget* Subtarget) {
25259 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25260 SDValue LHS = N->getOperand(0);
25261 SDValue RHS = N->getOperand(1);
25262 EVT VT = N->getValueType(0);
25265 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25267 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25268 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25269 LHS.getValueType(), RHS, LHS.getOperand(1));
25270 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25271 addV, DAG.getConstant(0, addV.getValueType()), CC);
25273 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25275 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25276 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25277 RHS.getValueType(), LHS, RHS.getOperand(1));
25278 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25279 addV, DAG.getConstant(0, addV.getValueType()), CC);
25282 if (VT.getScalarType() == MVT::i1) {
25283 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25284 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25285 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25286 if (!IsSEXT0 && !IsVZero0)
25288 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25289 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25290 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25292 if (!IsSEXT1 && !IsVZero1)
25295 if (IsSEXT0 && IsVZero1) {
25296 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25297 if (CC == ISD::SETEQ)
25298 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25299 return LHS.getOperand(0);
25301 if (IsSEXT1 && IsVZero0) {
25302 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25303 if (CC == ISD::SETEQ)
25304 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25305 return RHS.getOperand(0);
25312 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25313 const X86Subtarget *Subtarget) {
25315 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25316 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25317 "X86insertps is only defined for v4x32");
25319 SDValue Ld = N->getOperand(1);
25320 if (MayFoldLoad(Ld)) {
25321 // Extract the countS bits from the immediate so we can get the proper
25322 // address when narrowing the vector load to a specific element.
25323 // When the second source op is a memory address, interps doesn't use
25324 // countS and just gets an f32 from that address.
25325 unsigned DestIndex =
25326 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25327 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25331 // Create this as a scalar to vector to match the instruction pattern.
25332 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25333 // countS bits are ignored when loading from memory on insertps, which
25334 // means we don't need to explicitly set them to 0.
25335 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25336 LoadScalarToVector, N->getOperand(2));
25339 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25340 // as "sbb reg,reg", since it can be extended without zext and produces
25341 // an all-ones bit which is more useful than 0/1 in some cases.
25342 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25345 return DAG.getNode(ISD::AND, DL, VT,
25346 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25347 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25348 DAG.getConstant(1, VT));
25349 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25350 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25351 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25352 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25355 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25356 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25357 TargetLowering::DAGCombinerInfo &DCI,
25358 const X86Subtarget *Subtarget) {
25360 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25361 SDValue EFLAGS = N->getOperand(1);
25363 if (CC == X86::COND_A) {
25364 // Try to convert COND_A into COND_B in an attempt to facilitate
25365 // materializing "setb reg".
25367 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25368 // cannot take an immediate as its first operand.
25370 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25371 EFLAGS.getValueType().isInteger() &&
25372 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25373 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25374 EFLAGS.getNode()->getVTList(),
25375 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25376 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25377 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25381 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25382 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25384 if (CC == X86::COND_B)
25385 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25389 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25390 if (Flags.getNode()) {
25391 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25392 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25398 // Optimize branch condition evaluation.
25400 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25401 TargetLowering::DAGCombinerInfo &DCI,
25402 const X86Subtarget *Subtarget) {
25404 SDValue Chain = N->getOperand(0);
25405 SDValue Dest = N->getOperand(1);
25406 SDValue EFLAGS = N->getOperand(3);
25407 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25411 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25412 if (Flags.getNode()) {
25413 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25414 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25421 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25422 SelectionDAG &DAG) {
25423 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25424 // optimize away operation when it's from a constant.
25426 // The general transformation is:
25427 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25428 // AND(VECTOR_CMP(x,y), constant2)
25429 // constant2 = UNARYOP(constant)
25431 // Early exit if this isn't a vector operation, the operand of the
25432 // unary operation isn't a bitwise AND, or if the sizes of the operations
25433 // aren't the same.
25434 EVT VT = N->getValueType(0);
25435 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25436 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25437 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25440 // Now check that the other operand of the AND is a constant. We could
25441 // make the transformation for non-constant splats as well, but it's unclear
25442 // that would be a benefit as it would not eliminate any operations, just
25443 // perform one more step in scalar code before moving to the vector unit.
25444 if (BuildVectorSDNode *BV =
25445 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25446 // Bail out if the vector isn't a constant.
25447 if (!BV->isConstant())
25450 // Everything checks out. Build up the new and improved node.
25452 EVT IntVT = BV->getValueType(0);
25453 // Create a new constant of the appropriate type for the transformed
25455 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25456 // The AND node needs bitcasts to/from an integer vector type around it.
25457 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25458 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25459 N->getOperand(0)->getOperand(0), MaskConst);
25460 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25467 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25468 const X86TargetLowering *XTLI) {
25469 // First try to optimize away the conversion entirely when it's
25470 // conditionally from a constant. Vectors only.
25471 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25472 if (Res != SDValue())
25475 // Now move on to more general possibilities.
25476 SDValue Op0 = N->getOperand(0);
25477 EVT InVT = Op0->getValueType(0);
25479 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25480 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25482 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25483 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25484 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25487 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25488 // a 32-bit target where SSE doesn't support i64->FP operations.
25489 if (Op0.getOpcode() == ISD::LOAD) {
25490 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25491 EVT VT = Ld->getValueType(0);
25492 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25493 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25494 !XTLI->getSubtarget()->is64Bit() &&
25496 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25497 Ld->getChain(), Op0, DAG);
25498 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25505 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25506 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25507 X86TargetLowering::DAGCombinerInfo &DCI) {
25508 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25509 // the result is either zero or one (depending on the input carry bit).
25510 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25511 if (X86::isZeroNode(N->getOperand(0)) &&
25512 X86::isZeroNode(N->getOperand(1)) &&
25513 // We don't have a good way to replace an EFLAGS use, so only do this when
25515 SDValue(N, 1).use_empty()) {
25517 EVT VT = N->getValueType(0);
25518 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25519 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25520 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25521 DAG.getConstant(X86::COND_B,MVT::i8),
25523 DAG.getConstant(1, VT));
25524 return DCI.CombineTo(N, Res1, CarryOut);
25530 // fold (add Y, (sete X, 0)) -> adc 0, Y
25531 // (add Y, (setne X, 0)) -> sbb -1, Y
25532 // (sub (sete X, 0), Y) -> sbb 0, Y
25533 // (sub (setne X, 0), Y) -> adc -1, Y
25534 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25537 // Look through ZExts.
25538 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25539 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25542 SDValue SetCC = Ext.getOperand(0);
25543 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25546 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25547 if (CC != X86::COND_E && CC != X86::COND_NE)
25550 SDValue Cmp = SetCC.getOperand(1);
25551 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25552 !X86::isZeroNode(Cmp.getOperand(1)) ||
25553 !Cmp.getOperand(0).getValueType().isInteger())
25556 SDValue CmpOp0 = Cmp.getOperand(0);
25557 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25558 DAG.getConstant(1, CmpOp0.getValueType()));
25560 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25561 if (CC == X86::COND_NE)
25562 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25563 DL, OtherVal.getValueType(), OtherVal,
25564 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25565 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25566 DL, OtherVal.getValueType(), OtherVal,
25567 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25570 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25571 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25572 const X86Subtarget *Subtarget) {
25573 EVT VT = N->getValueType(0);
25574 SDValue Op0 = N->getOperand(0);
25575 SDValue Op1 = N->getOperand(1);
25577 // Try to synthesize horizontal adds from adds of shuffles.
25578 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25579 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25580 isHorizontalBinOp(Op0, Op1, true))
25581 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25583 return OptimizeConditionalInDecrement(N, DAG);
25586 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25587 const X86Subtarget *Subtarget) {
25588 SDValue Op0 = N->getOperand(0);
25589 SDValue Op1 = N->getOperand(1);
25591 // X86 can't encode an immediate LHS of a sub. See if we can push the
25592 // negation into a preceding instruction.
25593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25594 // If the RHS of the sub is a XOR with one use and a constant, invert the
25595 // immediate. Then add one to the LHS of the sub so we can turn
25596 // X-Y -> X+~Y+1, saving one register.
25597 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25598 isa<ConstantSDNode>(Op1.getOperand(1))) {
25599 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25600 EVT VT = Op0.getValueType();
25601 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25603 DAG.getConstant(~XorC, VT));
25604 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25605 DAG.getConstant(C->getAPIntValue()+1, VT));
25609 // Try to synthesize horizontal adds from adds of shuffles.
25610 EVT VT = N->getValueType(0);
25611 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25612 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25613 isHorizontalBinOp(Op0, Op1, true))
25614 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25616 return OptimizeConditionalInDecrement(N, DAG);
25619 /// performVZEXTCombine - Performs build vector combines
25620 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25621 TargetLowering::DAGCombinerInfo &DCI,
25622 const X86Subtarget *Subtarget) {
25624 MVT VT = N->getSimpleValueType(0);
25625 SDValue Op = N->getOperand(0);
25626 MVT OpVT = Op.getSimpleValueType();
25627 MVT OpEltVT = OpVT.getVectorElementType();
25628 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25630 // (vzext (bitcast (vzext (x)) -> (vzext x)
25632 while (V.getOpcode() == ISD::BITCAST)
25633 V = V.getOperand(0);
25635 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25636 MVT InnerVT = V.getSimpleValueType();
25637 MVT InnerEltVT = InnerVT.getVectorElementType();
25639 // If the element sizes match exactly, we can just do one larger vzext. This
25640 // is always an exact type match as vzext operates on integer types.
25641 if (OpEltVT == InnerEltVT) {
25642 assert(OpVT == InnerVT && "Types must match for vzext!");
25643 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25646 // The only other way we can combine them is if only a single element of the
25647 // inner vzext is used in the input to the outer vzext.
25648 if (InnerEltVT.getSizeInBits() < InputBits)
25651 // In this case, the inner vzext is completely dead because we're going to
25652 // only look at bits inside of the low element. Just do the outer vzext on
25653 // a bitcast of the input to the inner.
25654 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25655 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25658 // Check if we can bypass extracting and re-inserting an element of an input
25659 // vector. Essentialy:
25660 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25661 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25662 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25663 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25664 SDValue ExtractedV = V.getOperand(0);
25665 SDValue OrigV = ExtractedV.getOperand(0);
25666 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25667 if (ExtractIdx->getZExtValue() == 0) {
25668 MVT OrigVT = OrigV.getSimpleValueType();
25669 // Extract a subvector if necessary...
25670 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25671 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25672 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25673 OrigVT.getVectorNumElements() / Ratio);
25674 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25675 DAG.getIntPtrConstant(0));
25677 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25678 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25685 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25686 DAGCombinerInfo &DCI) const {
25687 SelectionDAG &DAG = DCI.DAG;
25688 switch (N->getOpcode()) {
25690 case ISD::EXTRACT_VECTOR_ELT:
25691 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25694 case X86ISD::SHRUNKBLEND:
25695 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25696 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25697 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25698 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25699 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25700 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25703 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25704 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25705 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25706 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25707 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25708 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25709 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25710 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25711 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25713 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25715 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25716 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25717 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25718 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25719 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25720 case ISD::ANY_EXTEND:
25721 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25722 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25723 case ISD::SIGN_EXTEND_INREG:
25724 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25725 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25726 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25727 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25728 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25729 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25730 case X86ISD::SHUFP: // Handle all target specific shuffles
25731 case X86ISD::PALIGNR:
25732 case X86ISD::UNPCKH:
25733 case X86ISD::UNPCKL:
25734 case X86ISD::MOVHLPS:
25735 case X86ISD::MOVLHPS:
25736 case X86ISD::PSHUFB:
25737 case X86ISD::PSHUFD:
25738 case X86ISD::PSHUFHW:
25739 case X86ISD::PSHUFLW:
25740 case X86ISD::MOVSS:
25741 case X86ISD::MOVSD:
25742 case X86ISD::VPERMILPI:
25743 case X86ISD::VPERM2X128:
25744 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25745 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25746 case ISD::INTRINSIC_WO_CHAIN:
25747 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25748 case X86ISD::INSERTPS:
25749 return PerformINSERTPSCombine(N, DAG, Subtarget);
25750 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25756 /// isTypeDesirableForOp - Return true if the target has native support for
25757 /// the specified value type and it is 'desirable' to use the type for the
25758 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25759 /// instruction encodings are longer and some i16 instructions are slow.
25760 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25761 if (!isTypeLegal(VT))
25763 if (VT != MVT::i16)
25770 case ISD::SIGN_EXTEND:
25771 case ISD::ZERO_EXTEND:
25772 case ISD::ANY_EXTEND:
25785 /// IsDesirableToPromoteOp - This method query the target whether it is
25786 /// beneficial for dag combiner to promote the specified node. If true, it
25787 /// should return the desired promotion type by reference.
25788 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25789 EVT VT = Op.getValueType();
25790 if (VT != MVT::i16)
25793 bool Promote = false;
25794 bool Commute = false;
25795 switch (Op.getOpcode()) {
25798 LoadSDNode *LD = cast<LoadSDNode>(Op);
25799 // If the non-extending load has a single use and it's not live out, then it
25800 // might be folded.
25801 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25802 Op.hasOneUse()*/) {
25803 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25804 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25805 // The only case where we'd want to promote LOAD (rather then it being
25806 // promoted as an operand is when it's only use is liveout.
25807 if (UI->getOpcode() != ISD::CopyToReg)
25814 case ISD::SIGN_EXTEND:
25815 case ISD::ZERO_EXTEND:
25816 case ISD::ANY_EXTEND:
25821 SDValue N0 = Op.getOperand(0);
25822 // Look out for (store (shl (load), x)).
25823 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25836 SDValue N0 = Op.getOperand(0);
25837 SDValue N1 = Op.getOperand(1);
25838 if (!Commute && MayFoldLoad(N1))
25840 // Avoid disabling potential load folding opportunities.
25841 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25843 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25853 //===----------------------------------------------------------------------===//
25854 // X86 Inline Assembly Support
25855 //===----------------------------------------------------------------------===//
25858 // Helper to match a string separated by whitespace.
25859 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25860 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25862 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25863 StringRef piece(*args[i]);
25864 if (!s.startswith(piece)) // Check if the piece matches.
25867 s = s.substr(piece.size());
25868 StringRef::size_type pos = s.find_first_not_of(" \t");
25869 if (pos == 0) // We matched a prefix.
25877 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25880 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25882 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25883 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25884 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25885 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25887 if (AsmPieces.size() == 3)
25889 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25896 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25897 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25899 std::string AsmStr = IA->getAsmString();
25901 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25902 if (!Ty || Ty->getBitWidth() % 16 != 0)
25905 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25906 SmallVector<StringRef, 4> AsmPieces;
25907 SplitString(AsmStr, AsmPieces, ";\n");
25909 switch (AsmPieces.size()) {
25910 default: return false;
25912 // FIXME: this should verify that we are targeting a 486 or better. If not,
25913 // we will turn this bswap into something that will be lowered to logical
25914 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25915 // lower so don't worry about this.
25917 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25918 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25919 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25920 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25921 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25922 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25923 // No need to check constraints, nothing other than the equivalent of
25924 // "=r,0" would be valid here.
25925 return IntrinsicLowering::LowerToByteSwap(CI);
25928 // rorw $$8, ${0:w} --> llvm.bswap.i16
25929 if (CI->getType()->isIntegerTy(16) &&
25930 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25931 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25932 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25934 const std::string &ConstraintsStr = IA->getConstraintString();
25935 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25936 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25937 if (clobbersFlagRegisters(AsmPieces))
25938 return IntrinsicLowering::LowerToByteSwap(CI);
25942 if (CI->getType()->isIntegerTy(32) &&
25943 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25944 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25945 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25946 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25948 const std::string &ConstraintsStr = IA->getConstraintString();
25949 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25950 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25951 if (clobbersFlagRegisters(AsmPieces))
25952 return IntrinsicLowering::LowerToByteSwap(CI);
25955 if (CI->getType()->isIntegerTy(64)) {
25956 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25957 if (Constraints.size() >= 2 &&
25958 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25959 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25960 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25961 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25962 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25963 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25964 return IntrinsicLowering::LowerToByteSwap(CI);
25972 /// getConstraintType - Given a constraint letter, return the type of
25973 /// constraint it is for this target.
25974 X86TargetLowering::ConstraintType
25975 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25976 if (Constraint.size() == 1) {
25977 switch (Constraint[0]) {
25988 return C_RegisterClass;
26012 return TargetLowering::getConstraintType(Constraint);
26015 /// Examine constraint type and operand type and determine a weight value.
26016 /// This object must already have been set up with the operand type
26017 /// and the current alternative constraint selected.
26018 TargetLowering::ConstraintWeight
26019 X86TargetLowering::getSingleConstraintMatchWeight(
26020 AsmOperandInfo &info, const char *constraint) const {
26021 ConstraintWeight weight = CW_Invalid;
26022 Value *CallOperandVal = info.CallOperandVal;
26023 // If we don't have a value, we can't do a match,
26024 // but allow it at the lowest weight.
26025 if (!CallOperandVal)
26027 Type *type = CallOperandVal->getType();
26028 // Look at the constraint type.
26029 switch (*constraint) {
26031 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26042 if (CallOperandVal->getType()->isIntegerTy())
26043 weight = CW_SpecificReg;
26048 if (type->isFloatingPointTy())
26049 weight = CW_SpecificReg;
26052 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26053 weight = CW_SpecificReg;
26057 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26058 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26059 weight = CW_Register;
26062 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26063 if (C->getZExtValue() <= 31)
26064 weight = CW_Constant;
26068 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26069 if (C->getZExtValue() <= 63)
26070 weight = CW_Constant;
26074 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26075 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26076 weight = CW_Constant;
26080 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26081 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26082 weight = CW_Constant;
26086 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26087 if (C->getZExtValue() <= 3)
26088 weight = CW_Constant;
26092 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26093 if (C->getZExtValue() <= 0xff)
26094 weight = CW_Constant;
26099 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26100 weight = CW_Constant;
26104 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26105 if ((C->getSExtValue() >= -0x80000000LL) &&
26106 (C->getSExtValue() <= 0x7fffffffLL))
26107 weight = CW_Constant;
26111 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26112 if (C->getZExtValue() <= 0xffffffff)
26113 weight = CW_Constant;
26120 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26121 /// with another that has more specific requirements based on the type of the
26122 /// corresponding operand.
26123 const char *X86TargetLowering::
26124 LowerXConstraint(EVT ConstraintVT) const {
26125 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26126 // 'f' like normal targets.
26127 if (ConstraintVT.isFloatingPoint()) {
26128 if (Subtarget->hasSSE2())
26130 if (Subtarget->hasSSE1())
26134 return TargetLowering::LowerXConstraint(ConstraintVT);
26137 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26138 /// vector. If it is invalid, don't add anything to Ops.
26139 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26140 std::string &Constraint,
26141 std::vector<SDValue>&Ops,
26142 SelectionDAG &DAG) const {
26145 // Only support length 1 constraints for now.
26146 if (Constraint.length() > 1) return;
26148 char ConstraintLetter = Constraint[0];
26149 switch (ConstraintLetter) {
26152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26153 if (C->getZExtValue() <= 31) {
26154 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26160 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26161 if (C->getZExtValue() <= 63) {
26162 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26169 if (isInt<8>(C->getSExtValue())) {
26170 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26177 if (C->getZExtValue() <= 255) {
26178 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26184 // 32-bit signed value
26185 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26186 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26187 C->getSExtValue())) {
26188 // Widen to 64 bits here to get it sign extended.
26189 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26192 // FIXME gcc accepts some relocatable values here too, but only in certain
26193 // memory models; it's complicated.
26198 // 32-bit unsigned value
26199 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26200 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26201 C->getZExtValue())) {
26202 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26206 // FIXME gcc accepts some relocatable values here too, but only in certain
26207 // memory models; it's complicated.
26211 // Literal immediates are always ok.
26212 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26213 // Widen to 64 bits here to get it sign extended.
26214 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26218 // In any sort of PIC mode addresses need to be computed at runtime by
26219 // adding in a register or some sort of table lookup. These can't
26220 // be used as immediates.
26221 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26224 // If we are in non-pic codegen mode, we allow the address of a global (with
26225 // an optional displacement) to be used with 'i'.
26226 GlobalAddressSDNode *GA = nullptr;
26227 int64_t Offset = 0;
26229 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26231 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26232 Offset += GA->getOffset();
26234 } else if (Op.getOpcode() == ISD::ADD) {
26235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26236 Offset += C->getZExtValue();
26237 Op = Op.getOperand(0);
26240 } else if (Op.getOpcode() == ISD::SUB) {
26241 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26242 Offset += -C->getZExtValue();
26243 Op = Op.getOperand(0);
26248 // Otherwise, this isn't something we can handle, reject it.
26252 const GlobalValue *GV = GA->getGlobal();
26253 // If we require an extra load to get this address, as in PIC mode, we
26254 // can't accept it.
26255 if (isGlobalStubReference(
26256 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26259 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26260 GA->getValueType(0), Offset);
26265 if (Result.getNode()) {
26266 Ops.push_back(Result);
26269 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26272 std::pair<unsigned, const TargetRegisterClass*>
26273 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26275 // First, see if this is a constraint that directly corresponds to an LLVM
26277 if (Constraint.size() == 1) {
26278 // GCC Constraint Letters
26279 switch (Constraint[0]) {
26281 // TODO: Slight differences here in allocation order and leaving
26282 // RIP in the class. Do they matter any more here than they do
26283 // in the normal allocation?
26284 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26285 if (Subtarget->is64Bit()) {
26286 if (VT == MVT::i32 || VT == MVT::f32)
26287 return std::make_pair(0U, &X86::GR32RegClass);
26288 if (VT == MVT::i16)
26289 return std::make_pair(0U, &X86::GR16RegClass);
26290 if (VT == MVT::i8 || VT == MVT::i1)
26291 return std::make_pair(0U, &X86::GR8RegClass);
26292 if (VT == MVT::i64 || VT == MVT::f64)
26293 return std::make_pair(0U, &X86::GR64RegClass);
26296 // 32-bit fallthrough
26297 case 'Q': // Q_REGS
26298 if (VT == MVT::i32 || VT == MVT::f32)
26299 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26300 if (VT == MVT::i16)
26301 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26302 if (VT == MVT::i8 || VT == MVT::i1)
26303 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26304 if (VT == MVT::i64)
26305 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26307 case 'r': // GENERAL_REGS
26308 case 'l': // INDEX_REGS
26309 if (VT == MVT::i8 || VT == MVT::i1)
26310 return std::make_pair(0U, &X86::GR8RegClass);
26311 if (VT == MVT::i16)
26312 return std::make_pair(0U, &X86::GR16RegClass);
26313 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26314 return std::make_pair(0U, &X86::GR32RegClass);
26315 return std::make_pair(0U, &X86::GR64RegClass);
26316 case 'R': // LEGACY_REGS
26317 if (VT == MVT::i8 || VT == MVT::i1)
26318 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26319 if (VT == MVT::i16)
26320 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26321 if (VT == MVT::i32 || !Subtarget->is64Bit())
26322 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26323 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26324 case 'f': // FP Stack registers.
26325 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26326 // value to the correct fpstack register class.
26327 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26328 return std::make_pair(0U, &X86::RFP32RegClass);
26329 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26330 return std::make_pair(0U, &X86::RFP64RegClass);
26331 return std::make_pair(0U, &X86::RFP80RegClass);
26332 case 'y': // MMX_REGS if MMX allowed.
26333 if (!Subtarget->hasMMX()) break;
26334 return std::make_pair(0U, &X86::VR64RegClass);
26335 case 'Y': // SSE_REGS if SSE2 allowed
26336 if (!Subtarget->hasSSE2()) break;
26338 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26339 if (!Subtarget->hasSSE1()) break;
26341 switch (VT.SimpleTy) {
26343 // Scalar SSE types.
26346 return std::make_pair(0U, &X86::FR32RegClass);
26349 return std::make_pair(0U, &X86::FR64RegClass);
26357 return std::make_pair(0U, &X86::VR128RegClass);
26365 return std::make_pair(0U, &X86::VR256RegClass);
26370 return std::make_pair(0U, &X86::VR512RegClass);
26376 // Use the default implementation in TargetLowering to convert the register
26377 // constraint into a member of a register class.
26378 std::pair<unsigned, const TargetRegisterClass*> Res;
26379 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26381 // Not found as a standard register?
26383 // Map st(0) -> st(7) -> ST0
26384 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26385 tolower(Constraint[1]) == 's' &&
26386 tolower(Constraint[2]) == 't' &&
26387 Constraint[3] == '(' &&
26388 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26389 Constraint[5] == ')' &&
26390 Constraint[6] == '}') {
26392 Res.first = X86::FP0+Constraint[4]-'0';
26393 Res.second = &X86::RFP80RegClass;
26397 // GCC allows "st(0)" to be called just plain "st".
26398 if (StringRef("{st}").equals_lower(Constraint)) {
26399 Res.first = X86::FP0;
26400 Res.second = &X86::RFP80RegClass;
26405 if (StringRef("{flags}").equals_lower(Constraint)) {
26406 Res.first = X86::EFLAGS;
26407 Res.second = &X86::CCRRegClass;
26411 // 'A' means EAX + EDX.
26412 if (Constraint == "A") {
26413 Res.first = X86::EAX;
26414 Res.second = &X86::GR32_ADRegClass;
26420 // Otherwise, check to see if this is a register class of the wrong value
26421 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26422 // turn into {ax},{dx}.
26423 if (Res.second->hasType(VT))
26424 return Res; // Correct type already, nothing to do.
26426 // All of the single-register GCC register classes map their values onto
26427 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26428 // really want an 8-bit or 32-bit register, map to the appropriate register
26429 // class and return the appropriate register.
26430 if (Res.second == &X86::GR16RegClass) {
26431 if (VT == MVT::i8 || VT == MVT::i1) {
26432 unsigned DestReg = 0;
26433 switch (Res.first) {
26435 case X86::AX: DestReg = X86::AL; break;
26436 case X86::DX: DestReg = X86::DL; break;
26437 case X86::CX: DestReg = X86::CL; break;
26438 case X86::BX: DestReg = X86::BL; break;
26441 Res.first = DestReg;
26442 Res.second = &X86::GR8RegClass;
26444 } else if (VT == MVT::i32 || VT == MVT::f32) {
26445 unsigned DestReg = 0;
26446 switch (Res.first) {
26448 case X86::AX: DestReg = X86::EAX; break;
26449 case X86::DX: DestReg = X86::EDX; break;
26450 case X86::CX: DestReg = X86::ECX; break;
26451 case X86::BX: DestReg = X86::EBX; break;
26452 case X86::SI: DestReg = X86::ESI; break;
26453 case X86::DI: DestReg = X86::EDI; break;
26454 case X86::BP: DestReg = X86::EBP; break;
26455 case X86::SP: DestReg = X86::ESP; break;
26458 Res.first = DestReg;
26459 Res.second = &X86::GR32RegClass;
26461 } else if (VT == MVT::i64 || VT == MVT::f64) {
26462 unsigned DestReg = 0;
26463 switch (Res.first) {
26465 case X86::AX: DestReg = X86::RAX; break;
26466 case X86::DX: DestReg = X86::RDX; break;
26467 case X86::CX: DestReg = X86::RCX; break;
26468 case X86::BX: DestReg = X86::RBX; break;
26469 case X86::SI: DestReg = X86::RSI; break;
26470 case X86::DI: DestReg = X86::RDI; break;
26471 case X86::BP: DestReg = X86::RBP; break;
26472 case X86::SP: DestReg = X86::RSP; break;
26475 Res.first = DestReg;
26476 Res.second = &X86::GR64RegClass;
26479 } else if (Res.second == &X86::FR32RegClass ||
26480 Res.second == &X86::FR64RegClass ||
26481 Res.second == &X86::VR128RegClass ||
26482 Res.second == &X86::VR256RegClass ||
26483 Res.second == &X86::FR32XRegClass ||
26484 Res.second == &X86::FR64XRegClass ||
26485 Res.second == &X86::VR128XRegClass ||
26486 Res.second == &X86::VR256XRegClass ||
26487 Res.second == &X86::VR512RegClass) {
26488 // Handle references to XMM physical registers that got mapped into the
26489 // wrong class. This can happen with constraints like {xmm0} where the
26490 // target independent register mapper will just pick the first match it can
26491 // find, ignoring the required type.
26493 if (VT == MVT::f32 || VT == MVT::i32)
26494 Res.second = &X86::FR32RegClass;
26495 else if (VT == MVT::f64 || VT == MVT::i64)
26496 Res.second = &X86::FR64RegClass;
26497 else if (X86::VR128RegClass.hasType(VT))
26498 Res.second = &X86::VR128RegClass;
26499 else if (X86::VR256RegClass.hasType(VT))
26500 Res.second = &X86::VR256RegClass;
26501 else if (X86::VR512RegClass.hasType(VT))
26502 Res.second = &X86::VR512RegClass;
26508 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26510 // Scaling factors are not free at all.
26511 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26512 // will take 2 allocations in the out of order engine instead of 1
26513 // for plain addressing mode, i.e. inst (reg1).
26515 // vaddps (%rsi,%drx), %ymm0, %ymm1
26516 // Requires two allocations (one for the load, one for the computation)
26518 // vaddps (%rsi), %ymm0, %ymm1
26519 // Requires just 1 allocation, i.e., freeing allocations for other operations
26520 // and having less micro operations to execute.
26522 // For some X86 architectures, this is even worse because for instance for
26523 // stores, the complex addressing mode forces the instruction to use the
26524 // "load" ports instead of the dedicated "store" port.
26525 // E.g., on Haswell:
26526 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26527 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26528 if (isLegalAddressingMode(AM, Ty))
26529 // Scale represents reg2 * scale, thus account for 1
26530 // as soon as we use a second register.
26531 return AM.Scale != 0;
26535 bool X86TargetLowering::isTargetFTOL() const {
26536 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();