1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 // Inserting UNDEF is Result
103 if (Vec.getOpcode() == ISD::UNDEF)
106 EVT VT = Vec.getValueType();
107 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
109 EVT ElVT = VT.getVectorElementType();
110 EVT ResultVT = Result.getValueType();
112 // Insert the relevant 128 bits.
113 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
115 // This is the index of the first element of the 128-bit chunk
117 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
120 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
121 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
125 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
126 /// instructions. This is used because creating CONCAT_VECTOR nodes of
127 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
128 /// large BUILD_VECTORS.
129 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
130 unsigned NumElems, SelectionDAG &DAG,
132 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
133 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
136 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
137 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
138 bool is64Bit = Subtarget->is64Bit();
140 if (Subtarget->isTargetEnvMacho()) {
142 return new X86_64MachoTargetObjectFile();
143 return new TargetLoweringObjectFileMachO();
146 if (Subtarget->isTargetLinux())
147 return new X86LinuxTargetObjectFile();
148 if (Subtarget->isTargetELF())
149 return new TargetLoweringObjectFileELF();
150 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
151 return new TargetLoweringObjectFileCOFF();
152 llvm_unreachable("unknown subtarget type");
155 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
156 : TargetLowering(TM, createTLOF(TM)) {
157 Subtarget = &TM.getSubtarget<X86Subtarget>();
158 X86ScalarSSEf64 = Subtarget->hasSSE2();
159 X86ScalarSSEf32 = Subtarget->hasSSE1();
160 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
162 RegInfo = TM.getRegisterInfo();
163 TD = getTargetData();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(X86StackPtr);
184 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
185 // Setup Windows compiler runtime calls.
186 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
187 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
188 setLibcallName(RTLIB::SREM_I64, "_allrem");
189 setLibcallName(RTLIB::UREM_I64, "_aullrem");
190 setLibcallName(RTLIB::MUL_I64, "_allmul");
191 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
197 // The _ftol2 runtime function has an unusual calling conv, which
198 // is modeled by a special pseudo-instruction.
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
201 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
202 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
205 if (Subtarget->isTargetDarwin()) {
206 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
207 setUseUnderscoreSetJmp(false);
208 setUseUnderscoreLongJmp(false);
209 } else if (Subtarget->isTargetMingw()) {
210 // MS runtime is weird: it exports _setjmp, but longjmp!
211 setUseUnderscoreSetJmp(true);
212 setUseUnderscoreLongJmp(false);
214 setUseUnderscoreSetJmp(true);
215 setUseUnderscoreLongJmp(true);
218 // Set up the register classes.
219 addRegisterClass(MVT::i8, &X86::GR8RegClass);
220 addRegisterClass(MVT::i16, &X86::GR16RegClass);
221 addRegisterClass(MVT::i32, &X86::GR32RegClass);
222 if (Subtarget->is64Bit())
223 addRegisterClass(MVT::i64, &X86::GR64RegClass);
225 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
227 // We don't accept any truncstore of integer registers.
228 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
231 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
232 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
233 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
235 // SETOEQ and SETUNE require checking two conditions.
236 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
243 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
245 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
249 if (Subtarget->is64Bit()) {
250 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
252 } else if (!TM.Options.UseSoftFloat) {
253 // We have an algorithm for SSE2->double, and we turn this into a
254 // 64-bit FILD followed by conditional FADD for other targets.
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 // We have an algorithm for SSE2, and we turn this into a 64-bit
257 // FILD for other targets.
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
261 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
266 if (!TM.Options.UseSoftFloat) {
267 // SSE has no i16 to fp conversion, only i32
268 if (X86ScalarSSEf32) {
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
270 // f32 and f64 cases are Legal, f80 case is not
271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
281 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
282 // are Legal, f80 is custom lowered.
283 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
286 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
288 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
289 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
291 if (X86ScalarSSEf32) {
292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
293 // f32 and f64 cases are Legal, f80 case is not
294 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 // Handle FP_TO_UINT by promoting the destination to a larger signed
302 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
306 if (Subtarget->is64Bit()) {
307 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
309 } else if (!TM.Options.UseSoftFloat) {
310 // Since AVX is a superset of SSE3, only check for SSE here.
311 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
312 // Expand FP_TO_UINT into a select.
313 // FIXME: We would like to use a Custom expander here eventually to do
314 // the optimal thing for SSE vs. the default expansion in the legalizer.
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
317 // With SSE3 we can use fisttpll to convert to a signed i64; without
318 // SSE, we're stuck with a fistpll.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
322 if (isTargetFTOL()) {
323 // Use the _ftol2 runtime function, which has a pseudo-instruction
324 // to handle its weird calling convention.
325 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
328 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
329 if (!X86ScalarSSEf64) {
330 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
331 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
334 // Without SSE, i64->f64 goes through memory.
335 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
339 // Scalar integer divide and remainder are lowered to use operations that
340 // produce two results, to match the available instructions. This exposes
341 // the two-result form to trivial CSE, which is able to combine x/y and x%y
342 // into a single instruction.
344 // Scalar integer multiply-high is also lowered to use two-result
345 // operations, to match the available instructions. However, plain multiply
346 // (low) operations are left as Legal, as there are single-result
347 // instructions for this in x86. Using the two-result multiply instructions
348 // when both high and low results are needed must be arranged by dagcombine.
349 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
351 setOperationAction(ISD::MULHS, VT, Expand);
352 setOperationAction(ISD::MULHU, VT, Expand);
353 setOperationAction(ISD::SDIV, VT, Expand);
354 setOperationAction(ISD::UDIV, VT, Expand);
355 setOperationAction(ISD::SREM, VT, Expand);
356 setOperationAction(ISD::UREM, VT, Expand);
358 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
359 setOperationAction(ISD::ADDC, VT, Custom);
360 setOperationAction(ISD::ADDE, VT, Custom);
361 setOperationAction(ISD::SUBC, VT, Custom);
362 setOperationAction(ISD::SUBE, VT, Custom);
365 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
366 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
367 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
368 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
369 if (Subtarget->is64Bit())
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
374 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f64 , Expand);
377 setOperationAction(ISD::FREM , MVT::f80 , Expand);
378 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
380 // Promote the i8 variants and force them on up to i32 which has a shorter
382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
383 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
384 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
385 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
386 if (Subtarget->hasBMI()) {
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
392 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
393 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
394 if (Subtarget->is64Bit())
395 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
398 if (Subtarget->hasLZCNT()) {
399 // When promoting the i8 variants, force them to i32 for a shorter
401 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
402 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
404 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
407 if (Subtarget->is64Bit())
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
410 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
422 if (Subtarget->hasPOPCNT()) {
423 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
425 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
432 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
433 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
435 // These should be promoted to a larger select which is supported.
436 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
437 // X86 wants to expand cmov itself.
438 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
450 if (Subtarget->is64Bit()) {
451 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
452 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
454 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
457 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
458 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
461 if (Subtarget->is64Bit())
462 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
463 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
464 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
465 if (Subtarget->is64Bit()) {
466 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
467 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
468 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
469 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
470 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
473 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
476 if (Subtarget->is64Bit()) {
477 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
482 if (Subtarget->hasSSE1())
483 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
485 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
486 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
488 // On X86 and X86-64, atomic operations are lowered to locked instructions.
489 // Locked instructions, in turn, have implicit fence semantics (all memory
490 // operations are flushed before issuing the locked instruction, and they
491 // are not buffered), so we can fold away the common pattern of
492 // fence-atomic-fence.
493 setShouldFoldAtomicFences(true);
495 // Expand certain atomics
496 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
498 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
499 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
500 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
503 if (!Subtarget->is64Bit()) {
504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
514 if (Subtarget->hasCmpxchg16b()) {
515 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
518 // FIXME - use subtarget debug flags
519 if (!Subtarget->isTargetDarwin() &&
520 !Subtarget->isTargetELF() &&
521 !Subtarget->isTargetCygMing()) {
522 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
526 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
527 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
528 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
529 if (Subtarget->is64Bit()) {
530 setExceptionPointerRegister(X86::RAX);
531 setExceptionSelectorRegister(X86::RDX);
533 setExceptionPointerRegister(X86::EAX);
534 setExceptionSelectorRegister(X86::EDX);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
539 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
540 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
542 setOperationAction(ISD::TRAP, MVT::Other, Legal);
544 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
545 setOperationAction(ISD::VASTART , MVT::Other, Custom);
546 setOperationAction(ISD::VAEND , MVT::Other, Expand);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::VAARG , MVT::Other, Custom);
549 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
551 setOperationAction(ISD::VAARG , MVT::Other, Expand);
552 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
555 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
556 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
558 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
559 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
560 MVT::i64 : MVT::i32, Custom);
561 else if (TM.Options.EnableSegmentedStacks)
562 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
563 MVT::i64 : MVT::i32, Custom);
565 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
566 MVT::i64 : MVT::i32, Expand);
568 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
569 // f32 and f64 use SSE.
570 // Set up the FP register classes.
571 addRegisterClass(MVT::f32, &X86::FR32RegClass);
572 addRegisterClass(MVT::f64, &X86::FR64RegClass);
574 // Use ANDPD to simulate FABS.
575 setOperationAction(ISD::FABS , MVT::f64, Custom);
576 setOperationAction(ISD::FABS , MVT::f32, Custom);
578 // Use XORP to simulate FNEG.
579 setOperationAction(ISD::FNEG , MVT::f64, Custom);
580 setOperationAction(ISD::FNEG , MVT::f32, Custom);
582 // Use ANDPD and ORPD to simulate FCOPYSIGN.
583 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
584 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
586 // Lower this to FGETSIGNx86 plus an AND.
587 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
588 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
590 // We don't support sin/cos/fmod
591 setOperationAction(ISD::FSIN , MVT::f64, Expand);
592 setOperationAction(ISD::FCOS , MVT::f64, Expand);
593 setOperationAction(ISD::FSIN , MVT::f32, Expand);
594 setOperationAction(ISD::FCOS , MVT::f32, Expand);
596 // Expand FP immediates into loads from the stack, except for the special
598 addLegalFPImmediate(APFloat(+0.0)); // xorpd
599 addLegalFPImmediate(APFloat(+0.0f)); // xorps
600 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
601 // Use SSE for f32, x87 for f64.
602 // Set up the FP register classes.
603 addRegisterClass(MVT::f32, &X86::FR32RegClass);
604 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
606 // Use ANDPS to simulate FABS.
607 setOperationAction(ISD::FABS , MVT::f32, Custom);
609 // Use XORP to simulate FNEG.
610 setOperationAction(ISD::FNEG , MVT::f32, Custom);
612 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
614 // Use ANDPS and ORPS to simulate FCOPYSIGN.
615 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
616 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
618 // We don't support sin/cos/fmod
619 setOperationAction(ISD::FSIN , MVT::f32, Expand);
620 setOperationAction(ISD::FCOS , MVT::f32, Expand);
622 // Special cases we handle for FP constants.
623 addLegalFPImmediate(APFloat(+0.0f)); // xorps
624 addLegalFPImmediate(APFloat(+0.0)); // FLD0
625 addLegalFPImmediate(APFloat(+1.0)); // FLD1
626 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
627 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
629 if (!TM.Options.UnsafeFPMath) {
630 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
631 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
633 } else if (!TM.Options.UseSoftFloat) {
634 // f32 and f64 in x87.
635 // Set up the FP register classes.
636 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
637 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
639 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
640 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
644 if (!TM.Options.UnsafeFPMath) {
645 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
646 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
648 addLegalFPImmediate(APFloat(+0.0)); // FLD0
649 addLegalFPImmediate(APFloat(+1.0)); // FLD1
650 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
651 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
652 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
653 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
654 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
655 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
658 // We don't support FMA.
659 setOperationAction(ISD::FMA, MVT::f64, Expand);
660 setOperationAction(ISD::FMA, MVT::f32, Expand);
662 // Long double always uses X87.
663 if (!TM.Options.UseSoftFloat) {
664 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
665 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
666 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
668 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
669 addLegalFPImmediate(TmpFlt); // FLD0
671 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
674 APFloat TmpFlt2(+1.0);
675 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
677 addLegalFPImmediate(TmpFlt2); // FLD1
678 TmpFlt2.changeSign();
679 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
682 if (!TM.Options.UnsafeFPMath) {
683 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
684 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
687 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
688 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
689 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
690 setOperationAction(ISD::FRINT, MVT::f80, Expand);
691 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
692 setOperationAction(ISD::FMA, MVT::f80, Expand);
695 // Always use a library call for pow.
696 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
700 setOperationAction(ISD::FLOG, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
706 // First set operation action for all vector types to either promote
707 // (for widening) or expand (for scalarization). Then we will selectively
708 // turn on ones that can be effectively codegen'd.
709 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
710 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
711 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
763 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
768 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
769 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
770 setTruncStoreAction((MVT::SimpleValueType)VT,
771 (MVT::SimpleValueType)InnerVT, Expand);
772 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
774 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
777 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
778 // with -msoft-float, disable use of MMX as well.
779 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
780 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
781 // No operations on x86mmx supported, everything uses intrinsics.
784 // MMX-sized vectors (other than x86mmx) are expected to be expanded
785 // into smaller operations.
786 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
787 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
788 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
789 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
790 setOperationAction(ISD::AND, MVT::v8i8, Expand);
791 setOperationAction(ISD::AND, MVT::v4i16, Expand);
792 setOperationAction(ISD::AND, MVT::v2i32, Expand);
793 setOperationAction(ISD::AND, MVT::v1i64, Expand);
794 setOperationAction(ISD::OR, MVT::v8i8, Expand);
795 setOperationAction(ISD::OR, MVT::v4i16, Expand);
796 setOperationAction(ISD::OR, MVT::v2i32, Expand);
797 setOperationAction(ISD::OR, MVT::v1i64, Expand);
798 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
799 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
800 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
801 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
806 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
807 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
808 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
809 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
810 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
816 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
817 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
819 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
820 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
821 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
822 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
823 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
824 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
825 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
826 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
827 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
828 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
830 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
833 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
834 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
836 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
837 // registers cannot be used even for integer operations.
838 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
839 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
840 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
841 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
843 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
844 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
845 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
846 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
848 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
849 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
850 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
851 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
852 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
853 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
854 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
855 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
856 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
857 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
858 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
862 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
863 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
877 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
878 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
879 EVT VT = (MVT::SimpleValueType)i;
880 // Do not attempt to custom lower non-power-of-2 vectors
881 if (!isPowerOf2_32(VT.getVectorNumElements()))
883 // Do not attempt to custom lower non-128-bit vectors
884 if (!VT.is128BitVector())
886 setOperationAction(ISD::BUILD_VECTOR,
887 VT.getSimpleVT().SimpleTy, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE,
889 VT.getSimpleVT().SimpleTy, Custom);
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
891 VT.getSimpleVT().SimpleTy, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
901 if (Subtarget->is64Bit()) {
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
903 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
906 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
907 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
908 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
911 // Do not attempt to promote non-128-bit vectors
912 if (!VT.is128BitVector())
915 setOperationAction(ISD::AND, SVT, Promote);
916 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
917 setOperationAction(ISD::OR, SVT, Promote);
918 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
919 setOperationAction(ISD::XOR, SVT, Promote);
920 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
921 setOperationAction(ISD::LOAD, SVT, Promote);
922 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
923 setOperationAction(ISD::SELECT, SVT, Promote);
924 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
927 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
929 // Custom lower v2i64 and v2f64 selects.
930 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
931 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
932 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
933 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
939 if (Subtarget->hasSSE41()) {
940 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
943 setOperationAction(ISD::FRINT, MVT::f32, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
945 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
946 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
947 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
948 setOperationAction(ISD::FRINT, MVT::f64, Legal);
949 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
951 // FIXME: Do we need to handle scalar-to-vector here?
952 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
958 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
960 // i8 and i16 vectors are custom , because the source register and source
961 // source memory operand types are not the same width. f32 vectors are
962 // custom since the immediate controlling the insert encodes additional
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
974 // FIXME: these should be Legal but thats only for the case where
975 // the index is constant. For now custom expand to deal with that.
976 if (Subtarget->is64Bit()) {
977 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
982 if (Subtarget->hasSSE2()) {
983 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
984 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
986 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
987 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
989 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
990 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
992 if (Subtarget->hasAVX2()) {
993 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
994 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
996 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
997 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1002 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1004 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1005 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1007 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1011 if (Subtarget->hasSSE42())
1012 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1014 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1015 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1016 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1017 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1018 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1019 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1020 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1022 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1024 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1026 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1033 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1038 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1040 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1041 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1042 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1054 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1055 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1057 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1058 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1063 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1069 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1072 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1074 if (Subtarget->hasAVX2()) {
1075 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1077 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1078 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1080 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1081 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1083 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1085 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1086 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1087 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1088 // Don't lower v32i8 because there is no 128-bit byte mul
1090 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1092 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1093 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1095 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1096 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1098 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1100 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1101 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1102 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1103 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1110 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1112 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1113 // Don't lower v32i8 because there is no 128-bit byte mul
1115 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1121 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1124 // Custom lower several nodes for 256-bit types.
1125 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1126 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1127 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1130 // Extract subvector is special because the value type
1131 // (result) is 128-bit but the source is 256-bit wide.
1132 if (VT.is128BitVector())
1133 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1135 // Do not attempt to custom lower other non-256-bit vectors
1136 if (!VT.is256BitVector())
1139 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1140 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1141 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1143 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1144 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1147 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1148 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1149 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1152 // Do not attempt to promote non-256-bit vectors
1153 if (!VT.is256BitVector())
1156 setOperationAction(ISD::AND, SVT, Promote);
1157 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1158 setOperationAction(ISD::OR, SVT, Promote);
1159 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1160 setOperationAction(ISD::XOR, SVT, Promote);
1161 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1162 setOperationAction(ISD::LOAD, SVT, Promote);
1163 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1164 setOperationAction(ISD::SELECT, SVT, Promote);
1165 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1169 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1170 // of this type with custom code.
1171 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1172 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1173 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1177 // We want to custom lower some of our intrinsics.
1178 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1179 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1182 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1183 // handle type legalization for these operations here.
1185 // FIXME: We really should do custom legalization for addition and
1186 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1187 // than generic legalization for 64-bit multiplication-with-overflow, though.
1188 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1189 // Add/Sub/Mul with overflow operations are custom lowered.
1191 setOperationAction(ISD::SADDO, VT, Custom);
1192 setOperationAction(ISD::UADDO, VT, Custom);
1193 setOperationAction(ISD::SSUBO, VT, Custom);
1194 setOperationAction(ISD::USUBO, VT, Custom);
1195 setOperationAction(ISD::SMULO, VT, Custom);
1196 setOperationAction(ISD::UMULO, VT, Custom);
1199 // There are no 8-bit 3-address imul/mul instructions
1200 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1201 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1203 if (!Subtarget->is64Bit()) {
1204 // These libcalls are not available in 32-bit.
1205 setLibcallName(RTLIB::SHL_I128, 0);
1206 setLibcallName(RTLIB::SRL_I128, 0);
1207 setLibcallName(RTLIB::SRA_I128, 0);
1210 // We have target-specific dag combine patterns for the following nodes:
1211 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1212 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1213 setTargetDAGCombine(ISD::VSELECT);
1214 setTargetDAGCombine(ISD::SELECT);
1215 setTargetDAGCombine(ISD::SHL);
1216 setTargetDAGCombine(ISD::SRA);
1217 setTargetDAGCombine(ISD::SRL);
1218 setTargetDAGCombine(ISD::OR);
1219 setTargetDAGCombine(ISD::AND);
1220 setTargetDAGCombine(ISD::ADD);
1221 setTargetDAGCombine(ISD::FADD);
1222 setTargetDAGCombine(ISD::FSUB);
1223 setTargetDAGCombine(ISD::SUB);
1224 setTargetDAGCombine(ISD::LOAD);
1225 setTargetDAGCombine(ISD::STORE);
1226 setTargetDAGCombine(ISD::ZERO_EXTEND);
1227 setTargetDAGCombine(ISD::ANY_EXTEND);
1228 setTargetDAGCombine(ISD::SIGN_EXTEND);
1229 setTargetDAGCombine(ISD::TRUNCATE);
1230 setTargetDAGCombine(ISD::UINT_TO_FP);
1231 setTargetDAGCombine(ISD::SINT_TO_FP);
1232 setTargetDAGCombine(ISD::SETCC);
1233 setTargetDAGCombine(ISD::FP_TO_SINT);
1234 if (Subtarget->is64Bit())
1235 setTargetDAGCombine(ISD::MUL);
1236 setTargetDAGCombine(ISD::XOR);
1238 computeRegisterProperties();
1240 // On Darwin, -Os means optimize for size without hurting performance,
1241 // do not reduce the limit.
1242 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1243 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1244 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1245 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1246 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1247 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1248 setPrefLoopAlignment(4); // 2^4 bytes.
1249 benefitFromCodePlacementOpt = true;
1251 // Predictable cmov don't hurt on atom because it's in-order.
1252 predictableSelectIsExpensive = !Subtarget->isAtom();
1254 setPrefFunctionAlignment(4); // 2^4 bytes.
1258 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1259 if (!VT.isVector()) return MVT::i8;
1260 return VT.changeVectorElementTypeToInteger();
1264 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1265 /// the desired ByVal argument alignment.
1266 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1269 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1270 if (VTy->getBitWidth() == 128)
1272 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1273 unsigned EltAlign = 0;
1274 getMaxByValAlign(ATy->getElementType(), EltAlign);
1275 if (EltAlign > MaxAlign)
1276 MaxAlign = EltAlign;
1277 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1278 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1279 unsigned EltAlign = 0;
1280 getMaxByValAlign(STy->getElementType(i), EltAlign);
1281 if (EltAlign > MaxAlign)
1282 MaxAlign = EltAlign;
1289 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1290 /// function arguments in the caller parameter area. For X86, aggregates
1291 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1292 /// are at 4-byte boundaries.
1293 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1294 if (Subtarget->is64Bit()) {
1295 // Max of 8 and alignment of type.
1296 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1303 if (Subtarget->hasSSE1())
1304 getMaxByValAlign(Ty, Align);
1308 /// getOptimalMemOpType - Returns the target specific optimal type for load
1309 /// and store operations as a result of memset, memcpy, and memmove
1310 /// lowering. If DstAlign is zero that means it's safe to destination
1311 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1312 /// means there isn't a need to check it against alignment requirement,
1313 /// probably because the source does not need to be loaded. If
1314 /// 'IsZeroVal' is true, that means it's safe to return a
1315 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1316 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1317 /// constant so it does not need to be loaded.
1318 /// It returns EVT::Other if the type should be determined using generic
1319 /// target-independent logic.
1321 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1322 unsigned DstAlign, unsigned SrcAlign,
1325 MachineFunction &MF) const {
1326 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1327 // linux. This is because the stack realignment code can't handle certain
1328 // cases like PR2962. This should be removed when PR2962 is fixed.
1329 const Function *F = MF.getFunction();
1331 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1333 (Subtarget->isUnalignedMemAccessFast() ||
1334 ((DstAlign == 0 || DstAlign >= 16) &&
1335 (SrcAlign == 0 || SrcAlign >= 16))) &&
1336 Subtarget->getStackAlignment() >= 16) {
1337 if (Subtarget->getStackAlignment() >= 32) {
1338 if (Subtarget->hasAVX2())
1340 if (Subtarget->hasAVX())
1343 if (Subtarget->hasSSE2())
1345 if (Subtarget->hasSSE1())
1347 } else if (!MemcpyStrSrc && Size >= 8 &&
1348 !Subtarget->is64Bit() &&
1349 Subtarget->getStackAlignment() >= 8 &&
1350 Subtarget->hasSSE2()) {
1351 // Do not use f64 to lower memcpy if source is string constant. It's
1352 // better to use i32 to avoid the loads.
1356 if (Subtarget->is64Bit() && Size >= 8)
1361 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1362 /// current function. The returned value is a member of the
1363 /// MachineJumpTableInfo::JTEntryKind enum.
1364 unsigned X86TargetLowering::getJumpTableEncoding() const {
1365 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1367 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1368 Subtarget->isPICStyleGOT())
1369 return MachineJumpTableInfo::EK_Custom32;
1371 // Otherwise, use the normal jump table encoding heuristics.
1372 return TargetLowering::getJumpTableEncoding();
1376 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1377 const MachineBasicBlock *MBB,
1378 unsigned uid,MCContext &Ctx) const{
1379 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1380 Subtarget->isPICStyleGOT());
1381 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1383 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1384 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1387 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1389 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1390 SelectionDAG &DAG) const {
1391 if (!Subtarget->is64Bit())
1392 // This doesn't have DebugLoc associated with it, but is not really the
1393 // same as a Register.
1394 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1398 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1399 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1401 const MCExpr *X86TargetLowering::
1402 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1403 MCContext &Ctx) const {
1404 // X86-64 uses RIP relative addressing based on the jump table label.
1405 if (Subtarget->isPICStyleRIPRel())
1406 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1408 // Otherwise, the reference is relative to the PIC base.
1409 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1412 // FIXME: Why this routine is here? Move to RegInfo!
1413 std::pair<const TargetRegisterClass*, uint8_t>
1414 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1415 const TargetRegisterClass *RRC = 0;
1417 switch (VT.getSimpleVT().SimpleTy) {
1419 return TargetLowering::findRepresentativeClass(VT);
1420 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1421 RRC = Subtarget->is64Bit() ?
1422 (const TargetRegisterClass*)&X86::GR64RegClass :
1423 (const TargetRegisterClass*)&X86::GR32RegClass;
1426 RRC = &X86::VR64RegClass;
1428 case MVT::f32: case MVT::f64:
1429 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1430 case MVT::v4f32: case MVT::v2f64:
1431 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1433 RRC = &X86::VR128RegClass;
1436 return std::make_pair(RRC, Cost);
1439 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1440 unsigned &Offset) const {
1441 if (!Subtarget->isTargetLinux())
1444 if (Subtarget->is64Bit()) {
1445 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1447 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1460 //===----------------------------------------------------------------------===//
1461 // Return Value Calling Convention Implementation
1462 //===----------------------------------------------------------------------===//
1464 #include "X86GenCallingConv.inc"
1467 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1468 MachineFunction &MF, bool isVarArg,
1469 const SmallVectorImpl<ISD::OutputArg> &Outs,
1470 LLVMContext &Context) const {
1471 SmallVector<CCValAssign, 16> RVLocs;
1472 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1474 return CCInfo.CheckReturn(Outs, RetCC_X86);
1478 X86TargetLowering::LowerReturn(SDValue Chain,
1479 CallingConv::ID CallConv, bool isVarArg,
1480 const SmallVectorImpl<ISD::OutputArg> &Outs,
1481 const SmallVectorImpl<SDValue> &OutVals,
1482 DebugLoc dl, SelectionDAG &DAG) const {
1483 MachineFunction &MF = DAG.getMachineFunction();
1484 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1486 SmallVector<CCValAssign, 16> RVLocs;
1487 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1488 RVLocs, *DAG.getContext());
1489 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1491 // Add the regs to the liveout set for the function.
1492 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1493 for (unsigned i = 0; i != RVLocs.size(); ++i)
1494 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1495 MRI.addLiveOut(RVLocs[i].getLocReg());
1499 SmallVector<SDValue, 6> RetOps;
1500 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1501 // Operand #1 = Bytes To Pop
1502 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1505 // Copy the result values into the output registers.
1506 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1507 CCValAssign &VA = RVLocs[i];
1508 assert(VA.isRegLoc() && "Can only return in registers!");
1509 SDValue ValToCopy = OutVals[i];
1510 EVT ValVT = ValToCopy.getValueType();
1512 // Promote values to the appropriate types
1513 if (VA.getLocInfo() == CCValAssign::SExt)
1514 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1515 else if (VA.getLocInfo() == CCValAssign::ZExt)
1516 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1517 else if (VA.getLocInfo() == CCValAssign::AExt)
1518 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1519 else if (VA.getLocInfo() == CCValAssign::BCvt)
1520 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1522 // If this is x86-64, and we disabled SSE, we can't return FP values,
1523 // or SSE or MMX vectors.
1524 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1525 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1526 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1527 report_fatal_error("SSE register return with SSE disabled");
1529 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1530 // llvm-gcc has never done it right and no one has noticed, so this
1531 // should be OK for now.
1532 if (ValVT == MVT::f64 &&
1533 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1534 report_fatal_error("SSE2 register return with SSE2 disabled");
1536 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1537 // the RET instruction and handled by the FP Stackifier.
1538 if (VA.getLocReg() == X86::ST0 ||
1539 VA.getLocReg() == X86::ST1) {
1540 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1541 // change the value to the FP stack register class.
1542 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1543 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1544 RetOps.push_back(ValToCopy);
1545 // Don't emit a copytoreg.
1549 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1550 // which is returned in RAX / RDX.
1551 if (Subtarget->is64Bit()) {
1552 if (ValVT == MVT::x86mmx) {
1553 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1554 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1555 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1557 // If we don't have SSE2 available, convert to v4f32 so the generated
1558 // register is legal.
1559 if (!Subtarget->hasSSE2())
1560 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1565 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1566 Flag = Chain.getValue(1);
1569 // The x86-64 ABI for returning structs by value requires that we copy
1570 // the sret argument into %rax for the return. We saved the argument into
1571 // a virtual register in the entry block, so now we copy the value out
1573 if (Subtarget->is64Bit() &&
1574 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1575 MachineFunction &MF = DAG.getMachineFunction();
1576 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1577 unsigned Reg = FuncInfo->getSRetReturnReg();
1579 "SRetReturnReg should have been set in LowerFormalArguments().");
1580 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1582 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1583 Flag = Chain.getValue(1);
1585 // RAX now acts like a return value.
1586 MRI.addLiveOut(X86::RAX);
1589 RetOps[0] = Chain; // Update chain.
1591 // Add the flag if we have it.
1593 RetOps.push_back(Flag);
1595 return DAG.getNode(X86ISD::RET_FLAG, dl,
1596 MVT::Other, &RetOps[0], RetOps.size());
1599 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1600 if (N->getNumValues() != 1)
1602 if (!N->hasNUsesOfValue(1, 0))
1605 SDValue TCChain = Chain;
1606 SDNode *Copy = *N->use_begin();
1607 if (Copy->getOpcode() == ISD::CopyToReg) {
1608 // If the copy has a glue operand, we conservatively assume it isn't safe to
1609 // perform a tail call.
1610 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1612 TCChain = Copy->getOperand(0);
1613 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1616 bool HasRet = false;
1617 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1619 if (UI->getOpcode() != X86ISD::RET_FLAG)
1632 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1633 ISD::NodeType ExtendKind) const {
1635 // TODO: Is this also valid on 32-bit?
1636 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1637 ReturnMVT = MVT::i8;
1639 ReturnMVT = MVT::i32;
1641 EVT MinVT = getRegisterType(Context, ReturnMVT);
1642 return VT.bitsLT(MinVT) ? MinVT : VT;
1645 /// LowerCallResult - Lower the result values of a call into the
1646 /// appropriate copies out of appropriate physical registers.
1649 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1650 CallingConv::ID CallConv, bool isVarArg,
1651 const SmallVectorImpl<ISD::InputArg> &Ins,
1652 DebugLoc dl, SelectionDAG &DAG,
1653 SmallVectorImpl<SDValue> &InVals) const {
1655 // Assign locations to each value returned by this call.
1656 SmallVector<CCValAssign, 16> RVLocs;
1657 bool Is64Bit = Subtarget->is64Bit();
1658 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1659 getTargetMachine(), RVLocs, *DAG.getContext());
1660 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1662 // Copy all of the result registers out of their specified physreg.
1663 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1664 CCValAssign &VA = RVLocs[i];
1665 EVT CopyVT = VA.getValVT();
1667 // If this is x86-64, and we disabled SSE, we can't return FP values
1668 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1669 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1670 report_fatal_error("SSE register return with SSE disabled");
1675 // If this is a call to a function that returns an fp value on the floating
1676 // point stack, we must guarantee the the value is popped from the stack, so
1677 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1678 // if the return value is not used. We use the FpPOP_RETVAL instruction
1680 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1681 // If we prefer to use the value in xmm registers, copy it out as f80 and
1682 // use a truncate to move it from fp stack reg to xmm reg.
1683 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1684 SDValue Ops[] = { Chain, InFlag };
1685 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1686 MVT::Other, MVT::Glue, Ops, 2), 1);
1687 Val = Chain.getValue(0);
1689 // Round the f80 to the right size, which also moves it to the appropriate
1691 if (CopyVT != VA.getValVT())
1692 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1693 // This truncation won't change the value.
1694 DAG.getIntPtrConstant(1));
1696 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1697 CopyVT, InFlag).getValue(1);
1698 Val = Chain.getValue(0);
1700 InFlag = Chain.getValue(2);
1701 InVals.push_back(Val);
1708 //===----------------------------------------------------------------------===//
1709 // C & StdCall & Fast Calling Convention implementation
1710 //===----------------------------------------------------------------------===//
1711 // StdCall calling convention seems to be standard for many Windows' API
1712 // routines and around. It differs from C calling convention just a little:
1713 // callee should clean up the stack, not caller. Symbols should be also
1714 // decorated in some fancy way :) It doesn't support any vector arguments.
1715 // For info on fast calling convention see Fast Calling Convention (tail call)
1716 // implementation LowerX86_32FastCCCallTo.
1718 /// CallIsStructReturn - Determines whether a call uses struct return
1720 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1724 return Outs[0].Flags.isSRet();
1727 /// ArgsAreStructReturn - Determines whether a function uses struct
1728 /// return semantics.
1730 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1734 return Ins[0].Flags.isSRet();
1737 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1738 /// by "Src" to address "Dst" with size and alignment information specified by
1739 /// the specific parameter attribute. The copy will be passed as a byval
1740 /// function parameter.
1742 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1743 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1745 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1747 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1748 /*isVolatile*/false, /*AlwaysInline=*/true,
1749 MachinePointerInfo(), MachinePointerInfo());
1752 /// IsTailCallConvention - Return true if the calling convention is one that
1753 /// supports tail call optimization.
1754 static bool IsTailCallConvention(CallingConv::ID CC) {
1755 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1758 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1759 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1763 CallingConv::ID CalleeCC = CS.getCallingConv();
1764 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1770 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1771 /// a tailcall target by changing its ABI.
1772 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1773 bool GuaranteedTailCallOpt) {
1774 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1778 X86TargetLowering::LowerMemArgument(SDValue Chain,
1779 CallingConv::ID CallConv,
1780 const SmallVectorImpl<ISD::InputArg> &Ins,
1781 DebugLoc dl, SelectionDAG &DAG,
1782 const CCValAssign &VA,
1783 MachineFrameInfo *MFI,
1785 // Create the nodes corresponding to a load from this parameter slot.
1786 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1787 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1788 getTargetMachine().Options.GuaranteedTailCallOpt);
1789 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1792 // If value is passed by pointer we have address passed instead of the value
1794 if (VA.getLocInfo() == CCValAssign::Indirect)
1795 ValVT = VA.getLocVT();
1797 ValVT = VA.getValVT();
1799 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1800 // changed with more analysis.
1801 // In case of tail call optimization mark all arguments mutable. Since they
1802 // could be overwritten by lowering of arguments in case of a tail call.
1803 if (Flags.isByVal()) {
1804 unsigned Bytes = Flags.getByValSize();
1805 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1806 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1807 return DAG.getFrameIndex(FI, getPointerTy());
1809 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1810 VA.getLocMemOffset(), isImmutable);
1811 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1812 return DAG.getLoad(ValVT, dl, Chain, FIN,
1813 MachinePointerInfo::getFixedStack(FI),
1814 false, false, false, 0);
1819 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1820 CallingConv::ID CallConv,
1822 const SmallVectorImpl<ISD::InputArg> &Ins,
1825 SmallVectorImpl<SDValue> &InVals)
1827 MachineFunction &MF = DAG.getMachineFunction();
1828 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1830 const Function* Fn = MF.getFunction();
1831 if (Fn->hasExternalLinkage() &&
1832 Subtarget->isTargetCygMing() &&
1833 Fn->getName() == "main")
1834 FuncInfo->setForceFramePointer(true);
1836 MachineFrameInfo *MFI = MF.getFrameInfo();
1837 bool Is64Bit = Subtarget->is64Bit();
1838 bool IsWindows = Subtarget->isTargetWindows();
1839 bool IsWin64 = Subtarget->isTargetWin64();
1841 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1842 "Var args not supported with calling convention fastcc or ghc");
1844 // Assign locations to all of the incoming arguments.
1845 SmallVector<CCValAssign, 16> ArgLocs;
1846 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1847 ArgLocs, *DAG.getContext());
1849 // Allocate shadow area for Win64
1851 CCInfo.AllocateStack(32, 8);
1854 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1856 unsigned LastVal = ~0U;
1858 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1859 CCValAssign &VA = ArgLocs[i];
1860 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1862 assert(VA.getValNo() != LastVal &&
1863 "Don't support value assigned to multiple locs yet");
1865 LastVal = VA.getValNo();
1867 if (VA.isRegLoc()) {
1868 EVT RegVT = VA.getLocVT();
1869 const TargetRegisterClass *RC;
1870 if (RegVT == MVT::i32)
1871 RC = &X86::GR32RegClass;
1872 else if (Is64Bit && RegVT == MVT::i64)
1873 RC = &X86::GR64RegClass;
1874 else if (RegVT == MVT::f32)
1875 RC = &X86::FR32RegClass;
1876 else if (RegVT == MVT::f64)
1877 RC = &X86::FR64RegClass;
1878 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1879 RC = &X86::VR256RegClass;
1880 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1881 RC = &X86::VR128RegClass;
1882 else if (RegVT == MVT::x86mmx)
1883 RC = &X86::VR64RegClass;
1885 llvm_unreachable("Unknown argument type!");
1887 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1888 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1890 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1891 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1893 if (VA.getLocInfo() == CCValAssign::SExt)
1894 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1895 DAG.getValueType(VA.getValVT()));
1896 else if (VA.getLocInfo() == CCValAssign::ZExt)
1897 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1898 DAG.getValueType(VA.getValVT()));
1899 else if (VA.getLocInfo() == CCValAssign::BCvt)
1900 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1902 if (VA.isExtInLoc()) {
1903 // Handle MMX values passed in XMM regs.
1904 if (RegVT.isVector()) {
1905 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1908 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1911 assert(VA.isMemLoc());
1912 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1915 // If value is passed via pointer - do a load.
1916 if (VA.getLocInfo() == CCValAssign::Indirect)
1917 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1918 MachinePointerInfo(), false, false, false, 0);
1920 InVals.push_back(ArgValue);
1923 // The x86-64 ABI for returning structs by value requires that we copy
1924 // the sret argument into %rax for the return. Save the argument into
1925 // a virtual register so that we can access it from the return points.
1926 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1927 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1928 unsigned Reg = FuncInfo->getSRetReturnReg();
1930 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1931 FuncInfo->setSRetReturnReg(Reg);
1933 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1934 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1937 unsigned StackSize = CCInfo.getNextStackOffset();
1938 // Align stack specially for tail calls.
1939 if (FuncIsMadeTailCallSafe(CallConv,
1940 MF.getTarget().Options.GuaranteedTailCallOpt))
1941 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1943 // If the function takes variable number of arguments, make a frame index for
1944 // the start of the first vararg value... for expansion of llvm.va_start.
1946 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1947 CallConv != CallingConv::X86_ThisCall)) {
1948 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1951 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1953 // FIXME: We should really autogenerate these arrays
1954 static const uint16_t GPR64ArgRegsWin64[] = {
1955 X86::RCX, X86::RDX, X86::R8, X86::R9
1957 static const uint16_t GPR64ArgRegs64Bit[] = {
1958 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1960 static const uint16_t XMMArgRegs64Bit[] = {
1961 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1962 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1964 const uint16_t *GPR64ArgRegs;
1965 unsigned NumXMMRegs = 0;
1968 // The XMM registers which might contain var arg parameters are shadowed
1969 // in their paired GPR. So we only need to save the GPR to their home
1971 TotalNumIntRegs = 4;
1972 GPR64ArgRegs = GPR64ArgRegsWin64;
1974 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1975 GPR64ArgRegs = GPR64ArgRegs64Bit;
1977 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1980 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1983 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1984 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1985 "SSE register cannot be used when SSE is disabled!");
1986 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1987 NoImplicitFloatOps) &&
1988 "SSE register cannot be used when SSE is disabled!");
1989 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1990 !Subtarget->hasSSE1())
1991 // Kernel mode asks for SSE to be disabled, so don't push them
1993 TotalNumXMMRegs = 0;
1996 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1997 // Get to the caller-allocated home save location. Add 8 to account
1998 // for the return address.
1999 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2000 FuncInfo->setRegSaveFrameIndex(
2001 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2002 // Fixup to set vararg frame on shadow area (4 x i64).
2004 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2006 // For X86-64, if there are vararg parameters that are passed via
2007 // registers, then we must store them to their spots on the stack so
2008 // they may be loaded by deferencing the result of va_next.
2009 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2010 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2011 FuncInfo->setRegSaveFrameIndex(
2012 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2016 // Store the integer parameter registers.
2017 SmallVector<SDValue, 8> MemOps;
2018 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2020 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2021 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2022 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2023 DAG.getIntPtrConstant(Offset));
2024 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2025 &X86::GR64RegClass);
2026 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2028 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2029 MachinePointerInfo::getFixedStack(
2030 FuncInfo->getRegSaveFrameIndex(), Offset),
2032 MemOps.push_back(Store);
2036 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2037 // Now store the XMM (fp + vector) parameter registers.
2038 SmallVector<SDValue, 11> SaveXMMOps;
2039 SaveXMMOps.push_back(Chain);
2041 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2042 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2043 SaveXMMOps.push_back(ALVal);
2045 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2046 FuncInfo->getRegSaveFrameIndex()));
2047 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2048 FuncInfo->getVarArgsFPOffset()));
2050 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2051 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2052 &X86::VR128RegClass);
2053 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2054 SaveXMMOps.push_back(Val);
2056 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2058 &SaveXMMOps[0], SaveXMMOps.size()));
2061 if (!MemOps.empty())
2062 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2063 &MemOps[0], MemOps.size());
2067 // Some CCs need callee pop.
2068 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2069 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2070 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2072 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2073 // If this is an sret function, the return should pop the hidden pointer.
2074 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2075 ArgsAreStructReturn(Ins))
2076 FuncInfo->setBytesToPopOnReturn(4);
2080 // RegSaveFrameIndex is X86-64 only.
2081 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2082 if (CallConv == CallingConv::X86_FastCall ||
2083 CallConv == CallingConv::X86_ThisCall)
2084 // fastcc functions can't have varargs.
2085 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2088 FuncInfo->setArgumentStackSize(StackSize);
2094 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2095 SDValue StackPtr, SDValue Arg,
2096 DebugLoc dl, SelectionDAG &DAG,
2097 const CCValAssign &VA,
2098 ISD::ArgFlagsTy Flags) const {
2099 unsigned LocMemOffset = VA.getLocMemOffset();
2100 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2101 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2102 if (Flags.isByVal())
2103 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2105 return DAG.getStore(Chain, dl, Arg, PtrOff,
2106 MachinePointerInfo::getStack(LocMemOffset),
2110 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2111 /// optimization is performed and it is required.
2113 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2114 SDValue &OutRetAddr, SDValue Chain,
2115 bool IsTailCall, bool Is64Bit,
2116 int FPDiff, DebugLoc dl) const {
2117 // Adjust the Return address stack slot.
2118 EVT VT = getPointerTy();
2119 OutRetAddr = getReturnAddressFrameIndex(DAG);
2121 // Load the "old" Return address.
2122 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2123 false, false, false, 0);
2124 return SDValue(OutRetAddr.getNode(), 1);
2127 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2128 /// optimization is performed and it is required (FPDiff!=0).
2130 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2131 SDValue Chain, SDValue RetAddrFrIdx,
2132 bool Is64Bit, int FPDiff, DebugLoc dl) {
2133 // Store the return address to the appropriate stack slot.
2134 if (!FPDiff) return Chain;
2135 // Calculate the new stack slot for the return address.
2136 int SlotSize = Is64Bit ? 8 : 4;
2137 int NewReturnAddrFI =
2138 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2139 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2140 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2141 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2142 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2148 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2149 SmallVectorImpl<SDValue> &InVals) const {
2150 SelectionDAG &DAG = CLI.DAG;
2151 DebugLoc &dl = CLI.DL;
2152 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2153 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2154 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2155 SDValue Chain = CLI.Chain;
2156 SDValue Callee = CLI.Callee;
2157 CallingConv::ID CallConv = CLI.CallConv;
2158 bool &isTailCall = CLI.IsTailCall;
2159 bool isVarArg = CLI.IsVarArg;
2161 MachineFunction &MF = DAG.getMachineFunction();
2162 bool Is64Bit = Subtarget->is64Bit();
2163 bool IsWin64 = Subtarget->isTargetWin64();
2164 bool IsWindows = Subtarget->isTargetWindows();
2165 bool IsStructRet = CallIsStructReturn(Outs);
2166 bool IsSibcall = false;
2168 if (MF.getTarget().Options.DisableTailCalls)
2172 // Check if it's really possible to do a tail call.
2173 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2174 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2175 Outs, OutVals, Ins, DAG);
2177 // Sibcalls are automatically detected tailcalls which do not require
2179 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2186 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2187 "Var args not supported with calling convention fastcc or ghc");
2189 // Analyze operands of the call, assigning locations to each operand.
2190 SmallVector<CCValAssign, 16> ArgLocs;
2191 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2192 ArgLocs, *DAG.getContext());
2194 // Allocate shadow area for Win64
2196 CCInfo.AllocateStack(32, 8);
2199 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2201 // Get a count of how many bytes are to be pushed on the stack.
2202 unsigned NumBytes = CCInfo.getNextStackOffset();
2204 // This is a sibcall. The memory operands are available in caller's
2205 // own caller's stack.
2207 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2208 IsTailCallConvention(CallConv))
2209 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2212 if (isTailCall && !IsSibcall) {
2213 // Lower arguments at fp - stackoffset + fpdiff.
2214 unsigned NumBytesCallerPushed =
2215 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2216 FPDiff = NumBytesCallerPushed - NumBytes;
2218 // Set the delta of movement of the returnaddr stackslot.
2219 // But only set if delta is greater than previous delta.
2220 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2221 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2225 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2227 SDValue RetAddrFrIdx;
2228 // Load return address for tail calls.
2229 if (isTailCall && FPDiff)
2230 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2231 Is64Bit, FPDiff, dl);
2233 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2234 SmallVector<SDValue, 8> MemOpChains;
2237 // Walk the register/memloc assignments, inserting copies/loads. In the case
2238 // of tail call optimization arguments are handle later.
2239 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2240 CCValAssign &VA = ArgLocs[i];
2241 EVT RegVT = VA.getLocVT();
2242 SDValue Arg = OutVals[i];
2243 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2244 bool isByVal = Flags.isByVal();
2246 // Promote the value if needed.
2247 switch (VA.getLocInfo()) {
2248 default: llvm_unreachable("Unknown loc info!");
2249 case CCValAssign::Full: break;
2250 case CCValAssign::SExt:
2251 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2253 case CCValAssign::ZExt:
2254 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2256 case CCValAssign::AExt:
2257 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2258 // Special case: passing MMX values in XMM registers.
2259 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2260 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2261 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2263 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2265 case CCValAssign::BCvt:
2266 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2268 case CCValAssign::Indirect: {
2269 // Store the argument.
2270 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2271 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2272 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2273 MachinePointerInfo::getFixedStack(FI),
2280 if (VA.isRegLoc()) {
2281 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2282 if (isVarArg && IsWin64) {
2283 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2284 // shadow reg if callee is a varargs function.
2285 unsigned ShadowReg = 0;
2286 switch (VA.getLocReg()) {
2287 case X86::XMM0: ShadowReg = X86::RCX; break;
2288 case X86::XMM1: ShadowReg = X86::RDX; break;
2289 case X86::XMM2: ShadowReg = X86::R8; break;
2290 case X86::XMM3: ShadowReg = X86::R9; break;
2293 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2295 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2296 assert(VA.isMemLoc());
2297 if (StackPtr.getNode() == 0)
2298 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2299 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2300 dl, DAG, VA, Flags));
2304 if (!MemOpChains.empty())
2305 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2306 &MemOpChains[0], MemOpChains.size());
2308 if (Subtarget->isPICStyleGOT()) {
2309 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2312 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2313 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2315 // If we are tail calling and generating PIC/GOT style code load the
2316 // address of the callee into ECX. The value in ecx is used as target of
2317 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2318 // for tail calls on PIC/GOT architectures. Normally we would just put the
2319 // address of GOT into ebx and then call target@PLT. But for tail calls
2320 // ebx would be restored (since ebx is callee saved) before jumping to the
2323 // Note: The actual moving to ECX is done further down.
2324 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2325 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2326 !G->getGlobal()->hasProtectedVisibility())
2327 Callee = LowerGlobalAddress(Callee, DAG);
2328 else if (isa<ExternalSymbolSDNode>(Callee))
2329 Callee = LowerExternalSymbol(Callee, DAG);
2333 if (Is64Bit && isVarArg && !IsWin64) {
2334 // From AMD64 ABI document:
2335 // For calls that may call functions that use varargs or stdargs
2336 // (prototype-less calls or calls to functions containing ellipsis (...) in
2337 // the declaration) %al is used as hidden argument to specify the number
2338 // of SSE registers used. The contents of %al do not need to match exactly
2339 // the number of registers, but must be an ubound on the number of SSE
2340 // registers used and is in the range 0 - 8 inclusive.
2342 // Count the number of XMM registers allocated.
2343 static const uint16_t XMMArgRegs[] = {
2344 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2345 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2347 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2348 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2349 && "SSE registers cannot be used when SSE is disabled");
2351 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2352 DAG.getConstant(NumXMMRegs, MVT::i8)));
2355 // For tail calls lower the arguments to the 'real' stack slot.
2357 // Force all the incoming stack arguments to be loaded from the stack
2358 // before any new outgoing arguments are stored to the stack, because the
2359 // outgoing stack slots may alias the incoming argument stack slots, and
2360 // the alias isn't otherwise explicit. This is slightly more conservative
2361 // than necessary, because it means that each store effectively depends
2362 // on every argument instead of just those arguments it would clobber.
2363 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2365 SmallVector<SDValue, 8> MemOpChains2;
2368 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2369 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2370 CCValAssign &VA = ArgLocs[i];
2373 assert(VA.isMemLoc());
2374 SDValue Arg = OutVals[i];
2375 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2376 // Create frame index.
2377 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2378 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2379 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2380 FIN = DAG.getFrameIndex(FI, getPointerTy());
2382 if (Flags.isByVal()) {
2383 // Copy relative to framepointer.
2384 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2385 if (StackPtr.getNode() == 0)
2386 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2388 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2390 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2394 // Store relative to framepointer.
2395 MemOpChains2.push_back(
2396 DAG.getStore(ArgChain, dl, Arg, FIN,
2397 MachinePointerInfo::getFixedStack(FI),
2403 if (!MemOpChains2.empty())
2404 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2405 &MemOpChains2[0], MemOpChains2.size());
2407 // Store the return address to the appropriate stack slot.
2408 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2412 // Build a sequence of copy-to-reg nodes chained together with token chain
2413 // and flag operands which copy the outgoing args into registers.
2415 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2416 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2417 RegsToPass[i].second, InFlag);
2418 InFlag = Chain.getValue(1);
2421 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2422 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2423 // In the 64-bit large code model, we have to make all calls
2424 // through a register, since the call instruction's 32-bit
2425 // pc-relative offset may not be large enough to hold the whole
2427 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2428 // If the callee is a GlobalAddress node (quite common, every direct call
2429 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2432 // We should use extra load for direct calls to dllimported functions in
2434 const GlobalValue *GV = G->getGlobal();
2435 if (!GV->hasDLLImportLinkage()) {
2436 unsigned char OpFlags = 0;
2437 bool ExtraLoad = false;
2438 unsigned WrapperKind = ISD::DELETED_NODE;
2440 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2441 // external symbols most go through the PLT in PIC mode. If the symbol
2442 // has hidden or protected visibility, or if it is static or local, then
2443 // we don't need to use the PLT - we can directly call it.
2444 if (Subtarget->isTargetELF() &&
2445 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2446 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2447 OpFlags = X86II::MO_PLT;
2448 } else if (Subtarget->isPICStyleStubAny() &&
2449 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2450 (!Subtarget->getTargetTriple().isMacOSX() ||
2451 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2452 // PC-relative references to external symbols should go through $stub,
2453 // unless we're building with the leopard linker or later, which
2454 // automatically synthesizes these stubs.
2455 OpFlags = X86II::MO_DARWIN_STUB;
2456 } else if (Subtarget->isPICStyleRIPRel() &&
2457 isa<Function>(GV) &&
2458 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2459 // If the function is marked as non-lazy, generate an indirect call
2460 // which loads from the GOT directly. This avoids runtime overhead
2461 // at the cost of eager binding (and one extra byte of encoding).
2462 OpFlags = X86II::MO_GOTPCREL;
2463 WrapperKind = X86ISD::WrapperRIP;
2467 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2468 G->getOffset(), OpFlags);
2470 // Add a wrapper if needed.
2471 if (WrapperKind != ISD::DELETED_NODE)
2472 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2473 // Add extra indirection if needed.
2475 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2476 MachinePointerInfo::getGOT(),
2477 false, false, false, 0);
2479 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2480 unsigned char OpFlags = 0;
2482 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2483 // external symbols should go through the PLT.
2484 if (Subtarget->isTargetELF() &&
2485 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2486 OpFlags = X86II::MO_PLT;
2487 } else if (Subtarget->isPICStyleStubAny() &&
2488 (!Subtarget->getTargetTriple().isMacOSX() ||
2489 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2490 // PC-relative references to external symbols should go through $stub,
2491 // unless we're building with the leopard linker or later, which
2492 // automatically synthesizes these stubs.
2493 OpFlags = X86II::MO_DARWIN_STUB;
2496 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2500 // Returns a chain & a flag for retval copy to use.
2501 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2502 SmallVector<SDValue, 8> Ops;
2504 if (!IsSibcall && isTailCall) {
2505 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2506 DAG.getIntPtrConstant(0, true), InFlag);
2507 InFlag = Chain.getValue(1);
2510 Ops.push_back(Chain);
2511 Ops.push_back(Callee);
2514 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2516 // Add argument registers to the end of the list so that they are known live
2518 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2519 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2520 RegsToPass[i].second.getValueType()));
2522 // Add a register mask operand representing the call-preserved registers.
2523 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2524 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2525 assert(Mask && "Missing call preserved mask for calling convention");
2526 Ops.push_back(DAG.getRegisterMask(Mask));
2528 if (InFlag.getNode())
2529 Ops.push_back(InFlag);
2533 //// If this is the first return lowered for this function, add the regs
2534 //// to the liveout set for the function.
2535 // This isn't right, although it's probably harmless on x86; liveouts
2536 // should be computed from returns not tail calls. Consider a void
2537 // function making a tail call to a function returning int.
2538 return DAG.getNode(X86ISD::TC_RETURN, dl,
2539 NodeTys, &Ops[0], Ops.size());
2542 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2543 InFlag = Chain.getValue(1);
2545 // Create the CALLSEQ_END node.
2546 unsigned NumBytesForCalleeToPush;
2547 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2548 getTargetMachine().Options.GuaranteedTailCallOpt))
2549 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2550 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2552 // If this is a call to a struct-return function, the callee
2553 // pops the hidden struct pointer, so we have to push it back.
2554 // This is common for Darwin/X86, Linux & Mingw32 targets.
2555 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2556 NumBytesForCalleeToPush = 4;
2558 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2560 // Returns a flag for retval copy to use.
2562 Chain = DAG.getCALLSEQ_END(Chain,
2563 DAG.getIntPtrConstant(NumBytes, true),
2564 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2567 InFlag = Chain.getValue(1);
2570 // Handle result values, copying them out of physregs into vregs that we
2572 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2573 Ins, dl, DAG, InVals);
2577 //===----------------------------------------------------------------------===//
2578 // Fast Calling Convention (tail call) implementation
2579 //===----------------------------------------------------------------------===//
2581 // Like std call, callee cleans arguments, convention except that ECX is
2582 // reserved for storing the tail called function address. Only 2 registers are
2583 // free for argument passing (inreg). Tail call optimization is performed
2585 // * tailcallopt is enabled
2586 // * caller/callee are fastcc
2587 // On X86_64 architecture with GOT-style position independent code only local
2588 // (within module) calls are supported at the moment.
2589 // To keep the stack aligned according to platform abi the function
2590 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2591 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2592 // If a tail called function callee has more arguments than the caller the
2593 // caller needs to make sure that there is room to move the RETADDR to. This is
2594 // achieved by reserving an area the size of the argument delta right after the
2595 // original REtADDR, but before the saved framepointer or the spilled registers
2596 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2608 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2609 /// for a 16 byte align requirement.
2611 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2612 SelectionDAG& DAG) const {
2613 MachineFunction &MF = DAG.getMachineFunction();
2614 const TargetMachine &TM = MF.getTarget();
2615 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2616 unsigned StackAlignment = TFI.getStackAlignment();
2617 uint64_t AlignMask = StackAlignment - 1;
2618 int64_t Offset = StackSize;
2619 uint64_t SlotSize = TD->getPointerSize();
2620 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2621 // Number smaller than 12 so just add the difference.
2622 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2624 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2625 Offset = ((~AlignMask) & Offset) + StackAlignment +
2626 (StackAlignment-SlotSize);
2631 /// MatchingStackOffset - Return true if the given stack call argument is
2632 /// already available in the same position (relatively) of the caller's
2633 /// incoming argument stack.
2635 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2636 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2637 const X86InstrInfo *TII) {
2638 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2640 if (Arg.getOpcode() == ISD::CopyFromReg) {
2641 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2642 if (!TargetRegisterInfo::isVirtualRegister(VR))
2644 MachineInstr *Def = MRI->getVRegDef(VR);
2647 if (!Flags.isByVal()) {
2648 if (!TII->isLoadFromStackSlot(Def, FI))
2651 unsigned Opcode = Def->getOpcode();
2652 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2653 Def->getOperand(1).isFI()) {
2654 FI = Def->getOperand(1).getIndex();
2655 Bytes = Flags.getByValSize();
2659 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2660 if (Flags.isByVal())
2661 // ByVal argument is passed in as a pointer but it's now being
2662 // dereferenced. e.g.
2663 // define @foo(%struct.X* %A) {
2664 // tail call @bar(%struct.X* byval %A)
2667 SDValue Ptr = Ld->getBasePtr();
2668 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2671 FI = FINode->getIndex();
2672 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2673 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2674 FI = FINode->getIndex();
2675 Bytes = Flags.getByValSize();
2679 assert(FI != INT_MAX);
2680 if (!MFI->isFixedObjectIndex(FI))
2682 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2685 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2686 /// for tail call optimization. Targets which want to do tail call
2687 /// optimization should implement this function.
2689 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2690 CallingConv::ID CalleeCC,
2692 bool isCalleeStructRet,
2693 bool isCallerStructRet,
2694 const SmallVectorImpl<ISD::OutputArg> &Outs,
2695 const SmallVectorImpl<SDValue> &OutVals,
2696 const SmallVectorImpl<ISD::InputArg> &Ins,
2697 SelectionDAG& DAG) const {
2698 if (!IsTailCallConvention(CalleeCC) &&
2699 CalleeCC != CallingConv::C)
2702 // If -tailcallopt is specified, make fastcc functions tail-callable.
2703 const MachineFunction &MF = DAG.getMachineFunction();
2704 const Function *CallerF = DAG.getMachineFunction().getFunction();
2705 CallingConv::ID CallerCC = CallerF->getCallingConv();
2706 bool CCMatch = CallerCC == CalleeCC;
2708 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2709 if (IsTailCallConvention(CalleeCC) && CCMatch)
2714 // Look for obvious safe cases to perform tail call optimization that do not
2715 // require ABI changes. This is what gcc calls sibcall.
2717 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2718 // emit a special epilogue.
2719 if (RegInfo->needsStackRealignment(MF))
2722 // Also avoid sibcall optimization if either caller or callee uses struct
2723 // return semantics.
2724 if (isCalleeStructRet || isCallerStructRet)
2727 // An stdcall caller is expected to clean up its arguments; the callee
2728 // isn't going to do that.
2729 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2732 // Do not sibcall optimize vararg calls unless all arguments are passed via
2734 if (isVarArg && !Outs.empty()) {
2736 // Optimizing for varargs on Win64 is unlikely to be safe without
2737 // additional testing.
2738 if (Subtarget->isTargetWin64())
2741 SmallVector<CCValAssign, 16> ArgLocs;
2742 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2743 getTargetMachine(), ArgLocs, *DAG.getContext());
2745 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2746 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2747 if (!ArgLocs[i].isRegLoc())
2751 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2752 // stack. Therefore, if it's not used by the call it is not safe to optimize
2753 // this into a sibcall.
2754 bool Unused = false;
2755 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2762 SmallVector<CCValAssign, 16> RVLocs;
2763 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2764 getTargetMachine(), RVLocs, *DAG.getContext());
2765 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2766 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2767 CCValAssign &VA = RVLocs[i];
2768 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2773 // If the calling conventions do not match, then we'd better make sure the
2774 // results are returned in the same way as what the caller expects.
2776 SmallVector<CCValAssign, 16> RVLocs1;
2777 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2778 getTargetMachine(), RVLocs1, *DAG.getContext());
2779 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2781 SmallVector<CCValAssign, 16> RVLocs2;
2782 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2783 getTargetMachine(), RVLocs2, *DAG.getContext());
2784 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2786 if (RVLocs1.size() != RVLocs2.size())
2788 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2789 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2791 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2793 if (RVLocs1[i].isRegLoc()) {
2794 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2797 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2803 // If the callee takes no arguments then go on to check the results of the
2805 if (!Outs.empty()) {
2806 // Check if stack adjustment is needed. For now, do not do this if any
2807 // argument is passed on the stack.
2808 SmallVector<CCValAssign, 16> ArgLocs;
2809 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2810 getTargetMachine(), ArgLocs, *DAG.getContext());
2812 // Allocate shadow area for Win64
2813 if (Subtarget->isTargetWin64()) {
2814 CCInfo.AllocateStack(32, 8);
2817 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2818 if (CCInfo.getNextStackOffset()) {
2819 MachineFunction &MF = DAG.getMachineFunction();
2820 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2823 // Check if the arguments are already laid out in the right way as
2824 // the caller's fixed stack objects.
2825 MachineFrameInfo *MFI = MF.getFrameInfo();
2826 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2827 const X86InstrInfo *TII =
2828 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2830 CCValAssign &VA = ArgLocs[i];
2831 SDValue Arg = OutVals[i];
2832 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2833 if (VA.getLocInfo() == CCValAssign::Indirect)
2835 if (!VA.isRegLoc()) {
2836 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2843 // If the tailcall address may be in a register, then make sure it's
2844 // possible to register allocate for it. In 32-bit, the call address can
2845 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2846 // callee-saved registers are restored. These happen to be the same
2847 // registers used to pass 'inreg' arguments so watch out for those.
2848 if (!Subtarget->is64Bit() &&
2849 !isa<GlobalAddressSDNode>(Callee) &&
2850 !isa<ExternalSymbolSDNode>(Callee)) {
2851 unsigned NumInRegs = 0;
2852 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2853 CCValAssign &VA = ArgLocs[i];
2856 unsigned Reg = VA.getLocReg();
2859 case X86::EAX: case X86::EDX: case X86::ECX:
2860 if (++NumInRegs == 3)
2872 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2873 return X86::createFastISel(funcInfo);
2877 //===----------------------------------------------------------------------===//
2878 // Other Lowering Hooks
2879 //===----------------------------------------------------------------------===//
2881 static bool MayFoldLoad(SDValue Op) {
2882 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2885 static bool MayFoldIntoStore(SDValue Op) {
2886 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2889 static bool isTargetShuffle(unsigned Opcode) {
2891 default: return false;
2892 case X86ISD::PSHUFD:
2893 case X86ISD::PSHUFHW:
2894 case X86ISD::PSHUFLW:
2896 case X86ISD::PALIGN:
2897 case X86ISD::MOVLHPS:
2898 case X86ISD::MOVLHPD:
2899 case X86ISD::MOVHLPS:
2900 case X86ISD::MOVLPS:
2901 case X86ISD::MOVLPD:
2902 case X86ISD::MOVSHDUP:
2903 case X86ISD::MOVSLDUP:
2904 case X86ISD::MOVDDUP:
2907 case X86ISD::UNPCKL:
2908 case X86ISD::UNPCKH:
2909 case X86ISD::VPERMILP:
2910 case X86ISD::VPERM2X128:
2911 case X86ISD::VPERMI:
2916 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2917 SDValue V1, SelectionDAG &DAG) {
2919 default: llvm_unreachable("Unknown x86 shuffle node");
2920 case X86ISD::MOVSHDUP:
2921 case X86ISD::MOVSLDUP:
2922 case X86ISD::MOVDDUP:
2923 return DAG.getNode(Opc, dl, VT, V1);
2927 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2928 SDValue V1, unsigned TargetMask,
2929 SelectionDAG &DAG) {
2931 default: llvm_unreachable("Unknown x86 shuffle node");
2932 case X86ISD::PSHUFD:
2933 case X86ISD::PSHUFHW:
2934 case X86ISD::PSHUFLW:
2935 case X86ISD::VPERMILP:
2936 case X86ISD::VPERMI:
2937 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2941 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2942 SDValue V1, SDValue V2, unsigned TargetMask,
2943 SelectionDAG &DAG) {
2945 default: llvm_unreachable("Unknown x86 shuffle node");
2946 case X86ISD::PALIGN:
2948 case X86ISD::VPERM2X128:
2949 return DAG.getNode(Opc, dl, VT, V1, V2,
2950 DAG.getConstant(TargetMask, MVT::i8));
2954 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2955 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2957 default: llvm_unreachable("Unknown x86 shuffle node");
2958 case X86ISD::MOVLHPS:
2959 case X86ISD::MOVLHPD:
2960 case X86ISD::MOVHLPS:
2961 case X86ISD::MOVLPS:
2962 case X86ISD::MOVLPD:
2965 case X86ISD::UNPCKL:
2966 case X86ISD::UNPCKH:
2967 return DAG.getNode(Opc, dl, VT, V1, V2);
2971 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2972 MachineFunction &MF = DAG.getMachineFunction();
2973 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2974 int ReturnAddrIndex = FuncInfo->getRAIndex();
2976 if (ReturnAddrIndex == 0) {
2977 // Set up a frame object for the return address.
2978 uint64_t SlotSize = TD->getPointerSize();
2979 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2981 FuncInfo->setRAIndex(ReturnAddrIndex);
2984 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2988 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2989 bool hasSymbolicDisplacement) {
2990 // Offset should fit into 32 bit immediate field.
2991 if (!isInt<32>(Offset))
2994 // If we don't have a symbolic displacement - we don't have any extra
2996 if (!hasSymbolicDisplacement)
2999 // FIXME: Some tweaks might be needed for medium code model.
3000 if (M != CodeModel::Small && M != CodeModel::Kernel)
3003 // For small code model we assume that latest object is 16MB before end of 31
3004 // bits boundary. We may also accept pretty large negative constants knowing
3005 // that all objects are in the positive half of address space.
3006 if (M == CodeModel::Small && Offset < 16*1024*1024)
3009 // For kernel code model we know that all object resist in the negative half
3010 // of 32bits address space. We may not accept negative offsets, since they may
3011 // be just off and we may accept pretty large positive ones.
3012 if (M == CodeModel::Kernel && Offset > 0)
3018 /// isCalleePop - Determines whether the callee is required to pop its
3019 /// own arguments. Callee pop is necessary to support tail calls.
3020 bool X86::isCalleePop(CallingConv::ID CallingConv,
3021 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3025 switch (CallingConv) {
3028 case CallingConv::X86_StdCall:
3030 case CallingConv::X86_FastCall:
3032 case CallingConv::X86_ThisCall:
3034 case CallingConv::Fast:
3036 case CallingConv::GHC:
3041 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3042 /// specific condition code, returning the condition code and the LHS/RHS of the
3043 /// comparison to make.
3044 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3045 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3047 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3048 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3049 // X > -1 -> X == 0, jump !sign.
3050 RHS = DAG.getConstant(0, RHS.getValueType());
3051 return X86::COND_NS;
3053 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3054 // X < 0 -> X == 0, jump on sign.
3057 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3059 RHS = DAG.getConstant(0, RHS.getValueType());
3060 return X86::COND_LE;
3062 if (SetCCOpcode == ISD::SETULT || SetCCOpcode == ISD::SETUGE) {
3063 unsigned TrailZeros = RHSC->getAPIntValue().countTrailingZeros();
3064 if (TrailZeros >= 32) {
3065 // The constant doesn't fit in cmp immediate field. Right shift LHS by
3066 // the # of trailing zeros and truncate it to 32-bit. Then compare
3067 // against shifted RHS.
3068 assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!");
3069 DebugLoc dl = LHS.getDebugLoc();
3070 LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
3071 DAG.getNode(ISD::SRL, dl, MVT::i64, LHS,
3072 DAG.getConstant(TrailZeros, MVT::i8)));
3073 uint64_t C = RHSC->getZExtValue() >> TrailZeros;
3075 if (SetCCOpcode == ISD::SETULT) {
3076 // X < 0x300000000 -> (X >> 32) < 3
3077 // X < 0x100000000 -> (X >> 32) == 0
3078 // X < 0x200000000 -> (X >> 33) == 0
3080 RHS = DAG.getConstant(0, MVT::i32);
3083 RHS = DAG.getConstant(C, MVT::i32);
3085 } else /* SetCCOpcode == ISD::SETUGE */ {
3086 // X >= 0x100000000 -> (X >> 32) >= 1
3087 RHS = DAG.getConstant(C, MVT::i32);
3088 return X86::COND_AE;
3092 if (SetCCOpcode == ISD::SETUGT) {
3093 unsigned TrailOnes = RHSC->getAPIntValue().countTrailingOnes();
3094 if (TrailOnes >= 32 && !RHSC->isAllOnesValue()) {
3095 assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!");
3096 DebugLoc dl = LHS.getDebugLoc();
3097 LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
3098 DAG.getNode(ISD::SRL, dl, MVT::i64, LHS,
3099 DAG.getConstant(TrailOnes, MVT::i8)));
3100 uint64_t C = (RHSC->getZExtValue()+1) >> TrailOnes;
3101 // X > 0x0ffffffff -> (X >> 32) >= 1
3102 RHS = DAG.getConstant(C, MVT::i32);
3103 return X86::COND_AE;
3108 switch (SetCCOpcode) {
3109 default: llvm_unreachable("Invalid integer condition!");
3110 case ISD::SETEQ: return X86::COND_E;
3111 case ISD::SETGT: return X86::COND_G;
3112 case ISD::SETGE: return X86::COND_GE;
3113 case ISD::SETLT: return X86::COND_L;
3114 case ISD::SETLE: return X86::COND_LE;
3115 case ISD::SETNE: return X86::COND_NE;
3116 case ISD::SETULT: return X86::COND_B;
3117 case ISD::SETUGT: return X86::COND_A;
3118 case ISD::SETULE: return X86::COND_BE;
3119 case ISD::SETUGE: return X86::COND_AE;
3123 // First determine if it is required or is profitable to flip the operands.
3125 // If LHS is a foldable load, but RHS is not, flip the condition.
3126 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3127 !ISD::isNON_EXTLoad(RHS.getNode())) {
3128 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3129 std::swap(LHS, RHS);
3132 switch (SetCCOpcode) {
3138 std::swap(LHS, RHS);
3142 // On a floating point condition, the flags are set as follows:
3144 // 0 | 0 | 0 | X > Y
3145 // 0 | 0 | 1 | X < Y
3146 // 1 | 0 | 0 | X == Y
3147 // 1 | 1 | 1 | unordered
3148 switch (SetCCOpcode) {
3149 default: llvm_unreachable("Condcode should be pre-legalized away");
3151 case ISD::SETEQ: return X86::COND_E;
3152 case ISD::SETOLT: // flipped
3154 case ISD::SETGT: return X86::COND_A;
3155 case ISD::SETOLE: // flipped
3157 case ISD::SETGE: return X86::COND_AE;
3158 case ISD::SETUGT: // flipped
3160 case ISD::SETLT: return X86::COND_B;
3161 case ISD::SETUGE: // flipped
3163 case ISD::SETLE: return X86::COND_BE;
3165 case ISD::SETNE: return X86::COND_NE;
3166 case ISD::SETUO: return X86::COND_P;
3167 case ISD::SETO: return X86::COND_NP;
3169 case ISD::SETUNE: return X86::COND_INVALID;
3173 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3174 /// code. Current x86 isa includes the following FP cmov instructions:
3175 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3176 static bool hasFPCMov(unsigned X86CC) {
3192 /// isFPImmLegal - Returns true if the target can instruction select the
3193 /// specified FP immediate natively. If false, the legalizer will
3194 /// materialize the FP immediate as a load from a constant pool.
3195 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3196 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3197 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3203 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3204 /// the specified range (L, H].
3205 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3206 return (Val < 0) || (Val >= Low && Val < Hi);
3209 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3210 /// specified value.
3211 static bool isUndefOrEqual(int Val, int CmpVal) {
3212 if (Val < 0 || Val == CmpVal)
3217 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3218 /// from position Pos and ending in Pos+Size, falls within the specified
3219 /// sequential range (L, L+Pos]. or is undef.
3220 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3221 unsigned Pos, unsigned Size, int Low) {
3222 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3223 if (!isUndefOrEqual(Mask[i], Low))
3228 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3229 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3230 /// the second operand.
3231 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3232 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3233 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3234 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3235 return (Mask[0] < 2 && Mask[1] < 2);
3239 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3240 /// is suitable for input to PSHUFHW.
3241 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3242 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3245 // Lower quadword copied in order or undef.
3246 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3249 // Upper quadword shuffled.
3250 for (unsigned i = 4; i != 8; ++i)
3251 if (!isUndefOrInRange(Mask[i], 4, 8))
3254 if (VT == MVT::v16i16) {
3255 // Lower quadword copied in order or undef.
3256 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3259 // Upper quadword shuffled.
3260 for (unsigned i = 12; i != 16; ++i)
3261 if (!isUndefOrInRange(Mask[i], 12, 16))
3268 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3269 /// is suitable for input to PSHUFLW.
3270 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3271 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3274 // Upper quadword copied in order.
3275 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3278 // Lower quadword shuffled.
3279 for (unsigned i = 0; i != 4; ++i)
3280 if (!isUndefOrInRange(Mask[i], 0, 4))
3283 if (VT == MVT::v16i16) {
3284 // Upper quadword copied in order.
3285 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3288 // Lower quadword shuffled.
3289 for (unsigned i = 8; i != 12; ++i)
3290 if (!isUndefOrInRange(Mask[i], 8, 12))
3297 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3298 /// is suitable for input to PALIGNR.
3299 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3300 const X86Subtarget *Subtarget) {
3301 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3302 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3305 unsigned NumElts = VT.getVectorNumElements();
3306 unsigned NumLanes = VT.getSizeInBits()/128;
3307 unsigned NumLaneElts = NumElts/NumLanes;
3309 // Do not handle 64-bit element shuffles with palignr.
3310 if (NumLaneElts == 2)
3313 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3315 for (i = 0; i != NumLaneElts; ++i) {
3320 // Lane is all undef, go to next lane
3321 if (i == NumLaneElts)
3324 int Start = Mask[i+l];
3326 // Make sure its in this lane in one of the sources
3327 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3328 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3331 // If not lane 0, then we must match lane 0
3332 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3335 // Correct second source to be contiguous with first source
3336 if (Start >= (int)NumElts)
3337 Start -= NumElts - NumLaneElts;
3339 // Make sure we're shifting in the right direction.
3340 if (Start <= (int)(i+l))
3345 // Check the rest of the elements to see if they are consecutive.
3346 for (++i; i != NumLaneElts; ++i) {
3347 int Idx = Mask[i+l];
3349 // Make sure its in this lane
3350 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3351 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3354 // If not lane 0, then we must match lane 0
3355 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3358 if (Idx >= (int)NumElts)
3359 Idx -= NumElts - NumLaneElts;
3361 if (!isUndefOrEqual(Idx, Start+i))
3370 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3371 /// the two vector operands have swapped position.
3372 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3373 unsigned NumElems) {
3374 for (unsigned i = 0; i != NumElems; ++i) {
3378 else if (idx < (int)NumElems)
3379 Mask[i] = idx + NumElems;
3381 Mask[i] = idx - NumElems;
3385 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3386 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3387 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3388 /// reverse of what x86 shuffles want.
3389 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3390 bool Commuted = false) {
3391 if (!HasAVX && VT.getSizeInBits() == 256)
3394 unsigned NumElems = VT.getVectorNumElements();
3395 unsigned NumLanes = VT.getSizeInBits()/128;
3396 unsigned NumLaneElems = NumElems/NumLanes;
3398 if (NumLaneElems != 2 && NumLaneElems != 4)
3401 // VSHUFPSY divides the resulting vector into 4 chunks.
3402 // The sources are also splitted into 4 chunks, and each destination
3403 // chunk must come from a different source chunk.
3405 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3406 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3408 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3409 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3411 // VSHUFPDY divides the resulting vector into 4 chunks.
3412 // The sources are also splitted into 4 chunks, and each destination
3413 // chunk must come from a different source chunk.
3415 // SRC1 => X3 X2 X1 X0
3416 // SRC2 => Y3 Y2 Y1 Y0
3418 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3420 unsigned HalfLaneElems = NumLaneElems/2;
3421 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3422 for (unsigned i = 0; i != NumLaneElems; ++i) {
3423 int Idx = Mask[i+l];
3424 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3425 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3427 // For VSHUFPSY, the mask of the second half must be the same as the
3428 // first but with the appropriate offsets. This works in the same way as
3429 // VPERMILPS works with masks.
3430 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3432 if (!isUndefOrEqual(Idx, Mask[i]+l))
3440 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3441 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3442 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3443 unsigned NumElems = VT.getVectorNumElements();
3445 if (VT.getSizeInBits() != 128)
3451 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3452 return isUndefOrEqual(Mask[0], 6) &&
3453 isUndefOrEqual(Mask[1], 7) &&
3454 isUndefOrEqual(Mask[2], 2) &&
3455 isUndefOrEqual(Mask[3], 3);
3458 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3459 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3461 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3462 unsigned NumElems = VT.getVectorNumElements();
3464 if (VT.getSizeInBits() != 128)
3470 return isUndefOrEqual(Mask[0], 2) &&
3471 isUndefOrEqual(Mask[1], 3) &&
3472 isUndefOrEqual(Mask[2], 2) &&
3473 isUndefOrEqual(Mask[3], 3);
3476 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3477 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3478 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3479 if (VT.getSizeInBits() != 128)
3482 unsigned NumElems = VT.getVectorNumElements();
3484 if (NumElems != 2 && NumElems != 4)
3487 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3488 if (!isUndefOrEqual(Mask[i], i + NumElems))
3491 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3492 if (!isUndefOrEqual(Mask[i], i))
3498 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3499 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3500 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3501 unsigned NumElems = VT.getVectorNumElements();
3503 if ((NumElems != 2 && NumElems != 4)
3504 || VT.getSizeInBits() > 128)
3507 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3508 if (!isUndefOrEqual(Mask[i], i))
3511 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3512 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3519 // Some special combinations that can be optimized.
3522 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3523 SelectionDAG &DAG) {
3524 EVT VT = SVOp->getValueType(0);
3525 DebugLoc dl = SVOp->getDebugLoc();
3527 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3530 ArrayRef<int> Mask = SVOp->getMask();
3532 // These are the special masks that may be optimized.
3533 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3534 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3535 bool MatchEvenMask = true;
3536 bool MatchOddMask = true;
3537 for (int i=0; i<8; ++i) {
3538 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3539 MatchEvenMask = false;
3540 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3541 MatchOddMask = false;
3543 static const int CompactionMaskEven[] = {0, 2, -1, -1, 4, 6, -1, -1};
3544 static const int CompactionMaskOdd [] = {1, 3, -1, -1, 5, 7, -1, -1};
3546 const int *CompactionMask;
3548 CompactionMask = CompactionMaskEven;
3549 else if (MatchOddMask)
3550 CompactionMask = CompactionMaskOdd;
3554 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3556 SDValue Op0 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(0),
3557 UndefNode, CompactionMask);
3558 SDValue Op1 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(1),
3559 UndefNode, CompactionMask);
3560 static const int UnpackMask[] = {0, 8, 1, 9, 4, 12, 5, 13};
3561 return DAG.getVectorShuffle(VT, dl, Op0, Op1, UnpackMask);
3564 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3565 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3566 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3567 bool HasAVX2, bool V2IsSplat = false) {
3568 unsigned NumElts = VT.getVectorNumElements();
3570 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3571 "Unsupported vector type for unpckh");
3573 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3574 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3577 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3578 // independently on 128-bit lanes.
3579 unsigned NumLanes = VT.getSizeInBits()/128;
3580 unsigned NumLaneElts = NumElts/NumLanes;
3582 for (unsigned l = 0; l != NumLanes; ++l) {
3583 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3584 i != (l+1)*NumLaneElts;
3587 int BitI1 = Mask[i+1];
3588 if (!isUndefOrEqual(BitI, j))
3591 if (!isUndefOrEqual(BitI1, NumElts))
3594 if (!isUndefOrEqual(BitI1, j + NumElts))
3603 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3604 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3605 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3606 bool HasAVX2, bool V2IsSplat = false) {
3607 unsigned NumElts = VT.getVectorNumElements();
3609 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3610 "Unsupported vector type for unpckh");
3612 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3613 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3616 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3617 // independently on 128-bit lanes.
3618 unsigned NumLanes = VT.getSizeInBits()/128;
3619 unsigned NumLaneElts = NumElts/NumLanes;
3621 for (unsigned l = 0; l != NumLanes; ++l) {
3622 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3623 i != (l+1)*NumLaneElts; i += 2, ++j) {
3625 int BitI1 = Mask[i+1];
3626 if (!isUndefOrEqual(BitI, j))
3629 if (isUndefOrEqual(BitI1, NumElts))
3632 if (!isUndefOrEqual(BitI1, j+NumElts))
3640 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3641 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3643 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3645 unsigned NumElts = VT.getVectorNumElements();
3647 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3648 "Unsupported vector type for unpckh");
3650 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3651 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3654 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3655 // FIXME: Need a better way to get rid of this, there's no latency difference
3656 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3657 // the former later. We should also remove the "_undef" special mask.
3658 if (NumElts == 4 && VT.getSizeInBits() == 256)
3661 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3662 // independently on 128-bit lanes.
3663 unsigned NumLanes = VT.getSizeInBits()/128;
3664 unsigned NumLaneElts = NumElts/NumLanes;
3666 for (unsigned l = 0; l != NumLanes; ++l) {
3667 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3668 i != (l+1)*NumLaneElts;
3671 int BitI1 = Mask[i+1];
3673 if (!isUndefOrEqual(BitI, j))
3675 if (!isUndefOrEqual(BitI1, j))
3683 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3684 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3686 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3687 unsigned NumElts = VT.getVectorNumElements();
3689 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3690 "Unsupported vector type for unpckh");
3692 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3693 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3696 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3697 // independently on 128-bit lanes.
3698 unsigned NumLanes = VT.getSizeInBits()/128;
3699 unsigned NumLaneElts = NumElts/NumLanes;
3701 for (unsigned l = 0; l != NumLanes; ++l) {
3702 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3703 i != (l+1)*NumLaneElts; i += 2, ++j) {
3705 int BitI1 = Mask[i+1];
3706 if (!isUndefOrEqual(BitI, j))
3708 if (!isUndefOrEqual(BitI1, j))
3715 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3716 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3717 /// MOVSD, and MOVD, i.e. setting the lowest element.
3718 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3719 if (VT.getVectorElementType().getSizeInBits() < 32)
3721 if (VT.getSizeInBits() == 256)
3724 unsigned NumElts = VT.getVectorNumElements();
3726 if (!isUndefOrEqual(Mask[0], NumElts))
3729 for (unsigned i = 1; i != NumElts; ++i)
3730 if (!isUndefOrEqual(Mask[i], i))
3736 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3737 /// as permutations between 128-bit chunks or halves. As an example: this
3739 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3740 /// The first half comes from the second half of V1 and the second half from the
3741 /// the second half of V2.
3742 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3743 if (!HasAVX || VT.getSizeInBits() != 256)
3746 // The shuffle result is divided into half A and half B. In total the two
3747 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3748 // B must come from C, D, E or F.
3749 unsigned HalfSize = VT.getVectorNumElements()/2;
3750 bool MatchA = false, MatchB = false;
3752 // Check if A comes from one of C, D, E, F.
3753 for (unsigned Half = 0; Half != 4; ++Half) {
3754 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3760 // Check if B comes from one of C, D, E, F.
3761 for (unsigned Half = 0; Half != 4; ++Half) {
3762 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3768 return MatchA && MatchB;
3771 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3772 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3773 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3774 EVT VT = SVOp->getValueType(0);
3776 unsigned HalfSize = VT.getVectorNumElements()/2;
3778 unsigned FstHalf = 0, SndHalf = 0;
3779 for (unsigned i = 0; i < HalfSize; ++i) {
3780 if (SVOp->getMaskElt(i) > 0) {
3781 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3785 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3786 if (SVOp->getMaskElt(i) > 0) {
3787 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3792 return (FstHalf | (SndHalf << 4));
3795 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3796 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3797 /// Note that VPERMIL mask matching is different depending whether theunderlying
3798 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3799 /// to the same elements of the low, but to the higher half of the source.
3800 /// In VPERMILPD the two lanes could be shuffled independently of each other
3801 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3802 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3806 unsigned NumElts = VT.getVectorNumElements();
3807 // Only match 256-bit with 32/64-bit types
3808 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3811 unsigned NumLanes = VT.getSizeInBits()/128;
3812 unsigned LaneSize = NumElts/NumLanes;
3813 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3814 for (unsigned i = 0; i != LaneSize; ++i) {
3815 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3817 if (NumElts != 8 || l == 0)
3819 // VPERMILPS handling
3822 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3830 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3831 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3832 /// element of vector 2 and the other elements to come from vector 1 in order.
3833 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3834 bool V2IsSplat = false, bool V2IsUndef = false) {
3835 unsigned NumOps = VT.getVectorNumElements();
3836 if (VT.getSizeInBits() == 256)
3838 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3841 if (!isUndefOrEqual(Mask[0], 0))
3844 for (unsigned i = 1; i != NumOps; ++i)
3845 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3846 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3847 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3853 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3854 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3855 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3856 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3857 const X86Subtarget *Subtarget) {
3858 if (!Subtarget->hasSSE3())
3861 unsigned NumElems = VT.getVectorNumElements();
3863 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3864 (VT.getSizeInBits() == 256 && NumElems != 8))
3867 // "i+1" is the value the indexed mask element must have
3868 for (unsigned i = 0; i != NumElems; i += 2)
3869 if (!isUndefOrEqual(Mask[i], i+1) ||
3870 !isUndefOrEqual(Mask[i+1], i+1))
3876 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3877 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3878 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3879 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3880 const X86Subtarget *Subtarget) {
3881 if (!Subtarget->hasSSE3())
3884 unsigned NumElems = VT.getVectorNumElements();
3886 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3887 (VT.getSizeInBits() == 256 && NumElems != 8))
3890 // "i" is the value the indexed mask element must have
3891 for (unsigned i = 0; i != NumElems; i += 2)
3892 if (!isUndefOrEqual(Mask[i], i) ||
3893 !isUndefOrEqual(Mask[i+1], i))
3899 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3900 /// specifies a shuffle of elements that is suitable for input to 256-bit
3901 /// version of MOVDDUP.
3902 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3903 unsigned NumElts = VT.getVectorNumElements();
3905 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3908 for (unsigned i = 0; i != NumElts/2; ++i)
3909 if (!isUndefOrEqual(Mask[i], 0))
3911 for (unsigned i = NumElts/2; i != NumElts; ++i)
3912 if (!isUndefOrEqual(Mask[i], NumElts/2))
3917 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3918 /// specifies a shuffle of elements that is suitable for input to 128-bit
3919 /// version of MOVDDUP.
3920 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3921 if (VT.getSizeInBits() != 128)
3924 unsigned e = VT.getVectorNumElements() / 2;
3925 for (unsigned i = 0; i != e; ++i)
3926 if (!isUndefOrEqual(Mask[i], i))
3928 for (unsigned i = 0; i != e; ++i)
3929 if (!isUndefOrEqual(Mask[e+i], i))
3934 /// isVEXTRACTF128Index - Return true if the specified
3935 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3936 /// suitable for input to VEXTRACTF128.
3937 bool X86::isVEXTRACTF128Index(SDNode *N) {
3938 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3941 // The index should be aligned on a 128-bit boundary.
3943 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3945 unsigned VL = N->getValueType(0).getVectorNumElements();
3946 unsigned VBits = N->getValueType(0).getSizeInBits();
3947 unsigned ElSize = VBits / VL;
3948 bool Result = (Index * ElSize) % 128 == 0;
3953 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3954 /// operand specifies a subvector insert that is suitable for input to
3956 bool X86::isVINSERTF128Index(SDNode *N) {
3957 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3960 // The index should be aligned on a 128-bit boundary.
3962 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3964 unsigned VL = N->getValueType(0).getVectorNumElements();
3965 unsigned VBits = N->getValueType(0).getSizeInBits();
3966 unsigned ElSize = VBits / VL;
3967 bool Result = (Index * ElSize) % 128 == 0;
3972 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3973 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3974 /// Handles 128-bit and 256-bit.
3975 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3976 EVT VT = N->getValueType(0);
3978 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3979 "Unsupported vector type for PSHUF/SHUFP");
3981 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3982 // independently on 128-bit lanes.
3983 unsigned NumElts = VT.getVectorNumElements();
3984 unsigned NumLanes = VT.getSizeInBits()/128;
3985 unsigned NumLaneElts = NumElts/NumLanes;
3987 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3988 "Only supports 2 or 4 elements per lane");
3990 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3992 for (unsigned i = 0; i != NumElts; ++i) {
3993 int Elt = N->getMaskElt(i);
3994 if (Elt < 0) continue;
3995 Elt &= NumLaneElts - 1;
3996 unsigned ShAmt = (i << Shift) % 8;
3997 Mask |= Elt << ShAmt;
4003 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4004 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4005 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4006 EVT VT = N->getValueType(0);
4008 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4009 "Unsupported vector type for PSHUFHW");
4011 unsigned NumElts = VT.getVectorNumElements();
4014 for (unsigned l = 0; l != NumElts; l += 8) {
4015 // 8 nodes per lane, but we only care about the last 4.
4016 for (unsigned i = 0; i < 4; ++i) {
4017 int Elt = N->getMaskElt(l+i+4);
4018 if (Elt < 0) continue;
4019 Elt &= 0x3; // only 2-bits.
4020 Mask |= Elt << (i * 2);
4027 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4028 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4029 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4030 EVT VT = N->getValueType(0);
4032 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4033 "Unsupported vector type for PSHUFHW");
4035 unsigned NumElts = VT.getVectorNumElements();
4038 for (unsigned l = 0; l != NumElts; l += 8) {
4039 // 8 nodes per lane, but we only care about the first 4.
4040 for (unsigned i = 0; i < 4; ++i) {
4041 int Elt = N->getMaskElt(l+i);
4042 if (Elt < 0) continue;
4043 Elt &= 0x3; // only 2-bits
4044 Mask |= Elt << (i * 2);
4051 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4052 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4053 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4054 EVT VT = SVOp->getValueType(0);
4055 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4057 unsigned NumElts = VT.getVectorNumElements();
4058 unsigned NumLanes = VT.getSizeInBits()/128;
4059 unsigned NumLaneElts = NumElts/NumLanes;
4063 for (i = 0; i != NumElts; ++i) {
4064 Val = SVOp->getMaskElt(i);
4068 if (Val >= (int)NumElts)
4069 Val -= NumElts - NumLaneElts;
4071 assert(Val - i > 0 && "PALIGNR imm should be positive");
4072 return (Val - i) * EltSize;
4075 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4076 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4078 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4079 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4080 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4083 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4085 EVT VecVT = N->getOperand(0).getValueType();
4086 EVT ElVT = VecVT.getVectorElementType();
4088 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4089 return Index / NumElemsPerChunk;
4092 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4093 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4095 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4096 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4097 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4100 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4102 EVT VecVT = N->getValueType(0);
4103 EVT ElVT = VecVT.getVectorElementType();
4105 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4106 return Index / NumElemsPerChunk;
4109 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4110 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4111 /// Handles 256-bit.
4112 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4113 EVT VT = N->getValueType(0);
4115 unsigned NumElts = VT.getVectorNumElements();
4117 assert((VT.is256BitVector() && NumElts == 4) &&
4118 "Unsupported vector type for VPERMQ/VPERMPD");
4121 for (unsigned i = 0; i != NumElts; ++i) {
4122 int Elt = N->getMaskElt(i);
4125 Mask |= Elt << (i*2);
4130 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4132 bool X86::isZeroNode(SDValue Elt) {
4133 return ((isa<ConstantSDNode>(Elt) &&
4134 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4135 (isa<ConstantFPSDNode>(Elt) &&
4136 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4139 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4140 /// their permute mask.
4141 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4142 SelectionDAG &DAG) {
4143 EVT VT = SVOp->getValueType(0);
4144 unsigned NumElems = VT.getVectorNumElements();
4145 SmallVector<int, 8> MaskVec;
4147 for (unsigned i = 0; i != NumElems; ++i) {
4148 int Idx = SVOp->getMaskElt(i);
4150 if (Idx < (int)NumElems)
4155 MaskVec.push_back(Idx);
4157 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4158 SVOp->getOperand(0), &MaskVec[0]);
4161 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4162 /// match movhlps. The lower half elements should come from upper half of
4163 /// V1 (and in order), and the upper half elements should come from the upper
4164 /// half of V2 (and in order).
4165 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4166 if (VT.getSizeInBits() != 128)
4168 if (VT.getVectorNumElements() != 4)
4170 for (unsigned i = 0, e = 2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i+2))
4173 for (unsigned i = 2; i != 4; ++i)
4174 if (!isUndefOrEqual(Mask[i], i+4))
4179 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4180 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4182 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4183 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4185 N = N->getOperand(0).getNode();
4186 if (!ISD::isNON_EXTLoad(N))
4189 *LD = cast<LoadSDNode>(N);
4193 // Test whether the given value is a vector value which will be legalized
4195 static bool WillBeConstantPoolLoad(SDNode *N) {
4196 if (N->getOpcode() != ISD::BUILD_VECTOR)
4199 // Check for any non-constant elements.
4200 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4201 switch (N->getOperand(i).getNode()->getOpcode()) {
4203 case ISD::ConstantFP:
4210 // Vectors of all-zeros and all-ones are materialized with special
4211 // instructions rather than being loaded.
4212 return !ISD::isBuildVectorAllZeros(N) &&
4213 !ISD::isBuildVectorAllOnes(N);
4216 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4217 /// match movlp{s|d}. The lower half elements should come from lower half of
4218 /// V1 (and in order), and the upper half elements should come from the upper
4219 /// half of V2 (and in order). And since V1 will become the source of the
4220 /// MOVLP, it must be either a vector load or a scalar load to vector.
4221 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4222 ArrayRef<int> Mask, EVT VT) {
4223 if (VT.getSizeInBits() != 128)
4226 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4228 // Is V2 is a vector load, don't do this transformation. We will try to use
4229 // load folding shufps op.
4230 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4233 unsigned NumElems = VT.getVectorNumElements();
4235 if (NumElems != 2 && NumElems != 4)
4237 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4238 if (!isUndefOrEqual(Mask[i], i))
4240 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4241 if (!isUndefOrEqual(Mask[i], i+NumElems))
4246 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4248 static bool isSplatVector(SDNode *N) {
4249 if (N->getOpcode() != ISD::BUILD_VECTOR)
4252 SDValue SplatValue = N->getOperand(0);
4253 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4254 if (N->getOperand(i) != SplatValue)
4259 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4260 /// to an zero vector.
4261 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4262 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4263 SDValue V1 = N->getOperand(0);
4264 SDValue V2 = N->getOperand(1);
4265 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4266 for (unsigned i = 0; i != NumElems; ++i) {
4267 int Idx = N->getMaskElt(i);
4268 if (Idx >= (int)NumElems) {
4269 unsigned Opc = V2.getOpcode();
4270 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4272 if (Opc != ISD::BUILD_VECTOR ||
4273 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4275 } else if (Idx >= 0) {
4276 unsigned Opc = V1.getOpcode();
4277 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4279 if (Opc != ISD::BUILD_VECTOR ||
4280 !X86::isZeroNode(V1.getOperand(Idx)))
4287 /// getZeroVector - Returns a vector of specified type with all zero elements.
4289 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4290 SelectionDAG &DAG, DebugLoc dl) {
4291 assert(VT.isVector() && "Expected a vector type");
4292 unsigned Size = VT.getSizeInBits();
4294 // Always build SSE zero vectors as <4 x i32> bitcasted
4295 // to their dest type. This ensures they get CSE'd.
4297 if (Size == 128) { // SSE
4298 if (Subtarget->hasSSE2()) { // SSE2
4299 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4300 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4302 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4303 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4305 } else if (Size == 256) { // AVX
4306 if (Subtarget->hasAVX2()) { // AVX2
4307 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4308 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4309 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4311 // 256-bit logic and arithmetic instructions in AVX are all
4312 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4313 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4314 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4315 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4318 llvm_unreachable("Unexpected vector type");
4320 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4323 /// getOnesVector - Returns a vector of specified type with all bits set.
4324 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4325 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4326 /// Then bitcast to their original type, ensuring they get CSE'd.
4327 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4329 assert(VT.isVector() && "Expected a vector type");
4330 unsigned Size = VT.getSizeInBits();
4332 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4335 if (HasAVX2) { // AVX2
4336 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4337 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4339 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4340 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4342 } else if (Size == 128) {
4343 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4345 llvm_unreachable("Unexpected vector type");
4347 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4350 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4351 /// that point to V2 points to its first element.
4352 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4353 for (unsigned i = 0; i != NumElems; ++i) {
4354 if (Mask[i] > (int)NumElems) {
4360 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4361 /// operation of specified width.
4362 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4364 unsigned NumElems = VT.getVectorNumElements();
4365 SmallVector<int, 8> Mask;
4366 Mask.push_back(NumElems);
4367 for (unsigned i = 1; i != NumElems; ++i)
4369 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4372 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4373 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4375 unsigned NumElems = VT.getVectorNumElements();
4376 SmallVector<int, 8> Mask;
4377 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4379 Mask.push_back(i + NumElems);
4381 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4384 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4385 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4387 unsigned NumElems = VT.getVectorNumElements();
4388 SmallVector<int, 8> Mask;
4389 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4390 Mask.push_back(i + Half);
4391 Mask.push_back(i + NumElems + Half);
4393 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4396 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4397 // a generic shuffle instruction because the target has no such instructions.
4398 // Generate shuffles which repeat i16 and i8 several times until they can be
4399 // represented by v4f32 and then be manipulated by target suported shuffles.
4400 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4401 EVT VT = V.getValueType();
4402 int NumElems = VT.getVectorNumElements();
4403 DebugLoc dl = V.getDebugLoc();
4405 while (NumElems > 4) {
4406 if (EltNo < NumElems/2) {
4407 V = getUnpackl(DAG, dl, VT, V, V);
4409 V = getUnpackh(DAG, dl, VT, V, V);
4410 EltNo -= NumElems/2;
4417 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4418 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4419 EVT VT = V.getValueType();
4420 DebugLoc dl = V.getDebugLoc();
4421 unsigned Size = VT.getSizeInBits();
4424 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4425 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4426 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4428 } else if (Size == 256) {
4429 // To use VPERMILPS to splat scalars, the second half of indicies must
4430 // refer to the higher part, which is a duplication of the lower one,
4431 // because VPERMILPS can only handle in-lane permutations.
4432 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4433 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4435 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4436 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4439 llvm_unreachable("Vector size not supported");
4441 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4444 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4445 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4446 EVT SrcVT = SV->getValueType(0);
4447 SDValue V1 = SV->getOperand(0);
4448 DebugLoc dl = SV->getDebugLoc();
4450 int EltNo = SV->getSplatIndex();
4451 int NumElems = SrcVT.getVectorNumElements();
4452 unsigned Size = SrcVT.getSizeInBits();
4454 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4455 "Unknown how to promote splat for type");
4457 // Extract the 128-bit part containing the splat element and update
4458 // the splat element index when it refers to the higher register.
4460 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4461 if (EltNo >= NumElems/2)
4462 EltNo -= NumElems/2;
4465 // All i16 and i8 vector types can't be used directly by a generic shuffle
4466 // instruction because the target has no such instruction. Generate shuffles
4467 // which repeat i16 and i8 several times until they fit in i32, and then can
4468 // be manipulated by target suported shuffles.
4469 EVT EltVT = SrcVT.getVectorElementType();
4470 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4471 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4473 // Recreate the 256-bit vector and place the same 128-bit vector
4474 // into the low and high part. This is necessary because we want
4475 // to use VPERM* to shuffle the vectors
4477 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4480 return getLegalSplat(DAG, V1, EltNo);
4483 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4484 /// vector of zero or undef vector. This produces a shuffle where the low
4485 /// element of V2 is swizzled into the zero/undef vector, landing at element
4486 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4487 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4489 const X86Subtarget *Subtarget,
4490 SelectionDAG &DAG) {
4491 EVT VT = V2.getValueType();
4493 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4494 unsigned NumElems = VT.getVectorNumElements();
4495 SmallVector<int, 16> MaskVec;
4496 for (unsigned i = 0; i != NumElems; ++i)
4497 // If this is the insertion idx, put the low elt of V2 here.
4498 MaskVec.push_back(i == Idx ? NumElems : i);
4499 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4502 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4503 /// target specific opcode. Returns true if the Mask could be calculated.
4504 /// Sets IsUnary to true if only uses one source.
4505 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4506 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4507 unsigned NumElems = VT.getVectorNumElements();
4511 switch(N->getOpcode()) {
4513 ImmN = N->getOperand(N->getNumOperands()-1);
4514 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4516 case X86ISD::UNPCKH:
4517 DecodeUNPCKHMask(VT, Mask);
4519 case X86ISD::UNPCKL:
4520 DecodeUNPCKLMask(VT, Mask);
4522 case X86ISD::MOVHLPS:
4523 DecodeMOVHLPSMask(NumElems, Mask);
4525 case X86ISD::MOVLHPS:
4526 DecodeMOVLHPSMask(NumElems, Mask);
4528 case X86ISD::PSHUFD:
4529 case X86ISD::VPERMILP:
4530 ImmN = N->getOperand(N->getNumOperands()-1);
4531 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4534 case X86ISD::PSHUFHW:
4535 ImmN = N->getOperand(N->getNumOperands()-1);
4536 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4539 case X86ISD::PSHUFLW:
4540 ImmN = N->getOperand(N->getNumOperands()-1);
4541 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4544 case X86ISD::VPERMI:
4545 ImmN = N->getOperand(N->getNumOperands()-1);
4546 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4550 case X86ISD::MOVSD: {
4551 // The index 0 always comes from the first element of the second source,
4552 // this is why MOVSS and MOVSD are used in the first place. The other
4553 // elements come from the other positions of the first source vector
4554 Mask.push_back(NumElems);
4555 for (unsigned i = 1; i != NumElems; ++i) {
4560 case X86ISD::VPERM2X128:
4561 ImmN = N->getOperand(N->getNumOperands()-1);
4562 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4563 if (Mask.empty()) return false;
4565 case X86ISD::MOVDDUP:
4566 case X86ISD::MOVLHPD:
4567 case X86ISD::MOVLPD:
4568 case X86ISD::MOVLPS:
4569 case X86ISD::MOVSHDUP:
4570 case X86ISD::MOVSLDUP:
4571 case X86ISD::PALIGN:
4572 // Not yet implemented
4574 default: llvm_unreachable("unknown target shuffle node");
4580 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4581 /// element of the result of the vector shuffle.
4582 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4585 return SDValue(); // Limit search depth.
4587 SDValue V = SDValue(N, 0);
4588 EVT VT = V.getValueType();
4589 unsigned Opcode = V.getOpcode();
4591 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4592 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4593 int Elt = SV->getMaskElt(Index);
4596 return DAG.getUNDEF(VT.getVectorElementType());
4598 unsigned NumElems = VT.getVectorNumElements();
4599 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4600 : SV->getOperand(1);
4601 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4604 // Recurse into target specific vector shuffles to find scalars.
4605 if (isTargetShuffle(Opcode)) {
4606 MVT ShufVT = V.getValueType().getSimpleVT();
4607 unsigned NumElems = ShufVT.getVectorNumElements();
4608 SmallVector<int, 16> ShuffleMask;
4612 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4615 int Elt = ShuffleMask[Index];
4617 return DAG.getUNDEF(ShufVT.getVectorElementType());
4619 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4621 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4625 // Actual nodes that may contain scalar elements
4626 if (Opcode == ISD::BITCAST) {
4627 V = V.getOperand(0);
4628 EVT SrcVT = V.getValueType();
4629 unsigned NumElems = VT.getVectorNumElements();
4631 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4635 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4636 return (Index == 0) ? V.getOperand(0)
4637 : DAG.getUNDEF(VT.getVectorElementType());
4639 if (V.getOpcode() == ISD::BUILD_VECTOR)
4640 return V.getOperand(Index);
4645 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4646 /// shuffle operation which come from a consecutively from a zero. The
4647 /// search can start in two different directions, from left or right.
4649 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4650 bool ZerosFromLeft, SelectionDAG &DAG) {
4652 for (i = 0; i != NumElems; ++i) {
4653 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4654 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4655 if (!(Elt.getNode() &&
4656 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4663 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4664 /// correspond consecutively to elements from one of the vector operands,
4665 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4667 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4668 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4669 unsigned NumElems, unsigned &OpNum) {
4670 bool SeenV1 = false;
4671 bool SeenV2 = false;
4673 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4674 int Idx = SVOp->getMaskElt(i);
4675 // Ignore undef indicies
4679 if (Idx < (int)NumElems)
4684 // Only accept consecutive elements from the same vector
4685 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4689 OpNum = SeenV1 ? 0 : 1;
4693 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4694 /// logical left shift of a vector.
4695 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4696 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4697 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4698 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4699 false /* check zeros from right */, DAG);
4705 // Considering the elements in the mask that are not consecutive zeros,
4706 // check if they consecutively come from only one of the source vectors.
4708 // V1 = {X, A, B, C} 0
4710 // vector_shuffle V1, V2 <1, 2, 3, X>
4712 if (!isShuffleMaskConsecutive(SVOp,
4713 0, // Mask Start Index
4714 NumElems-NumZeros, // Mask End Index(exclusive)
4715 NumZeros, // Where to start looking in the src vector
4716 NumElems, // Number of elements in vector
4717 OpSrc)) // Which source operand ?
4722 ShVal = SVOp->getOperand(OpSrc);
4726 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4727 /// logical left shift of a vector.
4728 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4729 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4730 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4731 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4732 true /* check zeros from left */, DAG);
4738 // Considering the elements in the mask that are not consecutive zeros,
4739 // check if they consecutively come from only one of the source vectors.
4741 // 0 { A, B, X, X } = V2
4743 // vector_shuffle V1, V2 <X, X, 4, 5>
4745 if (!isShuffleMaskConsecutive(SVOp,
4746 NumZeros, // Mask Start Index
4747 NumElems, // Mask End Index(exclusive)
4748 0, // Where to start looking in the src vector
4749 NumElems, // Number of elements in vector
4750 OpSrc)) // Which source operand ?
4755 ShVal = SVOp->getOperand(OpSrc);
4759 /// isVectorShift - Returns true if the shuffle can be implemented as a
4760 /// logical left or right shift of a vector.
4761 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4762 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4763 // Although the logic below support any bitwidth size, there are no
4764 // shift instructions which handle more than 128-bit vectors.
4765 if (SVOp->getValueType(0).getSizeInBits() > 128)
4768 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4769 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4775 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4777 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4778 unsigned NumNonZero, unsigned NumZero,
4780 const X86Subtarget* Subtarget,
4781 const TargetLowering &TLI) {
4785 DebugLoc dl = Op.getDebugLoc();
4788 for (unsigned i = 0; i < 16; ++i) {
4789 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4790 if (ThisIsNonZero && First) {
4792 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4794 V = DAG.getUNDEF(MVT::v8i16);
4799 SDValue ThisElt(0, 0), LastElt(0, 0);
4800 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4801 if (LastIsNonZero) {
4802 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4803 MVT::i16, Op.getOperand(i-1));
4805 if (ThisIsNonZero) {
4806 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4807 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4808 ThisElt, DAG.getConstant(8, MVT::i8));
4810 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4814 if (ThisElt.getNode())
4815 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4816 DAG.getIntPtrConstant(i/2));
4820 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4823 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4825 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4826 unsigned NumNonZero, unsigned NumZero,
4828 const X86Subtarget* Subtarget,
4829 const TargetLowering &TLI) {
4833 DebugLoc dl = Op.getDebugLoc();
4836 for (unsigned i = 0; i < 8; ++i) {
4837 bool isNonZero = (NonZeros & (1 << i)) != 0;
4841 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4843 V = DAG.getUNDEF(MVT::v8i16);
4846 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4847 MVT::v8i16, V, Op.getOperand(i),
4848 DAG.getIntPtrConstant(i));
4855 /// getVShift - Return a vector logical shift node.
4857 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4858 unsigned NumBits, SelectionDAG &DAG,
4859 const TargetLowering &TLI, DebugLoc dl) {
4860 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4861 EVT ShVT = MVT::v2i64;
4862 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4863 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4864 return DAG.getNode(ISD::BITCAST, dl, VT,
4865 DAG.getNode(Opc, dl, ShVT, SrcOp,
4866 DAG.getConstant(NumBits,
4867 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4871 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4872 SelectionDAG &DAG) const {
4874 // Check if the scalar load can be widened into a vector load. And if
4875 // the address is "base + cst" see if the cst can be "absorbed" into
4876 // the shuffle mask.
4877 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4878 SDValue Ptr = LD->getBasePtr();
4879 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4881 EVT PVT = LD->getValueType(0);
4882 if (PVT != MVT::i32 && PVT != MVT::f32)
4887 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4888 FI = FINode->getIndex();
4890 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4891 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4892 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4893 Offset = Ptr.getConstantOperandVal(1);
4894 Ptr = Ptr.getOperand(0);
4899 // FIXME: 256-bit vector instructions don't require a strict alignment,
4900 // improve this code to support it better.
4901 unsigned RequiredAlign = VT.getSizeInBits()/8;
4902 SDValue Chain = LD->getChain();
4903 // Make sure the stack object alignment is at least 16 or 32.
4904 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4905 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4906 if (MFI->isFixedObjectIndex(FI)) {
4907 // Can't change the alignment. FIXME: It's possible to compute
4908 // the exact stack offset and reference FI + adjust offset instead.
4909 // If someone *really* cares about this. That's the way to implement it.
4912 MFI->setObjectAlignment(FI, RequiredAlign);
4916 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4917 // Ptr + (Offset & ~15).
4920 if ((Offset % RequiredAlign) & 3)
4922 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4924 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4925 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4927 int EltNo = (Offset - StartOffset) >> 2;
4928 unsigned NumElems = VT.getVectorNumElements();
4930 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4931 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4932 LD->getPointerInfo().getWithOffset(StartOffset),
4933 false, false, false, 0);
4935 SmallVector<int, 8> Mask;
4936 for (unsigned i = 0; i != NumElems; ++i)
4937 Mask.push_back(EltNo);
4939 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4945 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4946 /// vector of type 'VT', see if the elements can be replaced by a single large
4947 /// load which has the same value as a build_vector whose operands are 'elts'.
4949 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4951 /// FIXME: we'd also like to handle the case where the last elements are zero
4952 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4953 /// There's even a handy isZeroNode for that purpose.
4954 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4955 DebugLoc &DL, SelectionDAG &DAG) {
4956 EVT EltVT = VT.getVectorElementType();
4957 unsigned NumElems = Elts.size();
4959 LoadSDNode *LDBase = NULL;
4960 unsigned LastLoadedElt = -1U;
4962 // For each element in the initializer, see if we've found a load or an undef.
4963 // If we don't find an initial load element, or later load elements are
4964 // non-consecutive, bail out.
4965 for (unsigned i = 0; i < NumElems; ++i) {
4966 SDValue Elt = Elts[i];
4968 if (!Elt.getNode() ||
4969 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4972 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4974 LDBase = cast<LoadSDNode>(Elt.getNode());
4978 if (Elt.getOpcode() == ISD::UNDEF)
4981 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4982 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4987 // If we have found an entire vector of loads and undefs, then return a large
4988 // load of the entire vector width starting at the base pointer. If we found
4989 // consecutive loads for the low half, generate a vzext_load node.
4990 if (LastLoadedElt == NumElems - 1) {
4991 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4992 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4993 LDBase->getPointerInfo(),
4994 LDBase->isVolatile(), LDBase->isNonTemporal(),
4995 LDBase->isInvariant(), 0);
4996 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4997 LDBase->getPointerInfo(),
4998 LDBase->isVolatile(), LDBase->isNonTemporal(),
4999 LDBase->isInvariant(), LDBase->getAlignment());
5001 if (NumElems == 4 && LastLoadedElt == 1 &&
5002 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5003 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5004 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5006 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5007 LDBase->getPointerInfo(),
5008 LDBase->getAlignment(),
5009 false/*isVolatile*/, true/*ReadMem*/,
5011 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5016 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5017 /// to generate a splat value for the following cases:
5018 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5019 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5020 /// a scalar load, or a constant.
5021 /// The VBROADCAST node is returned when a pattern is found,
5022 /// or SDValue() otherwise.
5024 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
5025 if (!Subtarget->hasAVX())
5028 EVT VT = Op.getValueType();
5029 DebugLoc dl = Op.getDebugLoc();
5031 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5032 "Unsupported vector type for broadcast.");
5037 switch (Op.getOpcode()) {
5039 // Unknown pattern found.
5042 case ISD::BUILD_VECTOR: {
5043 // The BUILD_VECTOR node must be a splat.
5044 if (!isSplatVector(Op.getNode()))
5047 Ld = Op.getOperand(0);
5048 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5049 Ld.getOpcode() == ISD::ConstantFP);
5051 // The suspected load node has several users. Make sure that all
5052 // of its users are from the BUILD_VECTOR node.
5053 // Constants may have multiple users.
5054 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5059 case ISD::VECTOR_SHUFFLE: {
5060 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5062 // Shuffles must have a splat mask where the first element is
5064 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5067 SDValue Sc = Op.getOperand(0);
5068 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5069 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5071 if (!Subtarget->hasAVX2())
5074 // Use the register form of the broadcast instruction available on AVX2.
5075 if (VT.is256BitVector())
5076 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5077 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5080 Ld = Sc.getOperand(0);
5081 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5082 Ld.getOpcode() == ISD::ConstantFP);
5084 // The scalar_to_vector node and the suspected
5085 // load node must have exactly one user.
5086 // Constants may have multiple users.
5087 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5093 bool Is256 = VT.getSizeInBits() == 256;
5095 // Handle the broadcasting a single constant scalar from the constant pool
5096 // into a vector. On Sandybridge it is still better to load a constant vector
5097 // from the constant pool and not to broadcast it from a scalar.
5098 if (ConstSplatVal && Subtarget->hasAVX2()) {
5099 EVT CVT = Ld.getValueType();
5100 assert(!CVT.isVector() && "Must not broadcast a vector type");
5101 unsigned ScalarSize = CVT.getSizeInBits();
5103 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5104 const Constant *C = 0;
5105 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5106 C = CI->getConstantIntValue();
5107 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5108 C = CF->getConstantFPValue();
5110 assert(C && "Invalid constant type");
5112 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5113 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5114 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5115 MachinePointerInfo::getConstantPool(),
5116 false, false, false, Alignment);
5118 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5122 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5123 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5125 // Handle AVX2 in-register broadcasts.
5126 if (!IsLoad && Subtarget->hasAVX2() &&
5127 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5128 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5130 // The scalar source must be a normal load.
5134 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5135 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5137 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5138 // double since there is no vbroadcastsd xmm
5139 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5140 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5144 // Unsupported broadcast.
5149 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5150 DebugLoc dl = Op.getDebugLoc();
5152 EVT VT = Op.getValueType();
5153 EVT ExtVT = VT.getVectorElementType();
5154 unsigned NumElems = Op.getNumOperands();
5156 // Vectors containing all zeros can be matched by pxor and xorps later
5157 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5158 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5159 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5160 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5163 return getZeroVector(VT, Subtarget, DAG, dl);
5166 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5167 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5168 // vpcmpeqd on 256-bit vectors.
5169 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5170 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5173 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5176 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5177 if (Broadcast.getNode())
5180 unsigned EVTBits = ExtVT.getSizeInBits();
5182 unsigned NumZero = 0;
5183 unsigned NumNonZero = 0;
5184 unsigned NonZeros = 0;
5185 bool IsAllConstants = true;
5186 SmallSet<SDValue, 8> Values;
5187 for (unsigned i = 0; i < NumElems; ++i) {
5188 SDValue Elt = Op.getOperand(i);
5189 if (Elt.getOpcode() == ISD::UNDEF)
5192 if (Elt.getOpcode() != ISD::Constant &&
5193 Elt.getOpcode() != ISD::ConstantFP)
5194 IsAllConstants = false;
5195 if (X86::isZeroNode(Elt))
5198 NonZeros |= (1 << i);
5203 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5204 if (NumNonZero == 0)
5205 return DAG.getUNDEF(VT);
5207 // Special case for single non-zero, non-undef, element.
5208 if (NumNonZero == 1) {
5209 unsigned Idx = CountTrailingZeros_32(NonZeros);
5210 SDValue Item = Op.getOperand(Idx);
5212 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5213 // the value are obviously zero, truncate the value to i32 and do the
5214 // insertion that way. Only do this if the value is non-constant or if the
5215 // value is a constant being inserted into element 0. It is cheaper to do
5216 // a constant pool load than it is to do a movd + shuffle.
5217 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5218 (!IsAllConstants || Idx == 0)) {
5219 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5221 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5222 EVT VecVT = MVT::v4i32;
5223 unsigned VecElts = 4;
5225 // Truncate the value (which may itself be a constant) to i32, and
5226 // convert it to a vector with movd (S2V+shuffle to zero extend).
5227 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5228 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5229 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5231 // Now we have our 32-bit value zero extended in the low element of
5232 // a vector. If Idx != 0, swizzle it into place.
5234 SmallVector<int, 4> Mask;
5235 Mask.push_back(Idx);
5236 for (unsigned i = 1; i != VecElts; ++i)
5238 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5241 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5245 // If we have a constant or non-constant insertion into the low element of
5246 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5247 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5248 // depending on what the source datatype is.
5251 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5253 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5254 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5255 if (VT.getSizeInBits() == 256) {
5256 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5257 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5258 Item, DAG.getIntPtrConstant(0));
5260 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5261 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5262 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5263 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5266 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5267 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5268 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5269 if (VT.getSizeInBits() == 256) {
5270 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5271 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5273 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5274 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5276 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5280 // Is it a vector logical left shift?
5281 if (NumElems == 2 && Idx == 1 &&
5282 X86::isZeroNode(Op.getOperand(0)) &&
5283 !X86::isZeroNode(Op.getOperand(1))) {
5284 unsigned NumBits = VT.getSizeInBits();
5285 return getVShift(true, VT,
5286 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5287 VT, Op.getOperand(1)),
5288 NumBits/2, DAG, *this, dl);
5291 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5294 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5295 // is a non-constant being inserted into an element other than the low one,
5296 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5297 // movd/movss) to move this into the low element, then shuffle it into
5299 if (EVTBits == 32) {
5300 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5302 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5303 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5304 SmallVector<int, 8> MaskVec;
5305 for (unsigned i = 0; i != NumElems; ++i)
5306 MaskVec.push_back(i == Idx ? 0 : 1);
5307 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5311 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5312 if (Values.size() == 1) {
5313 if (EVTBits == 32) {
5314 // Instead of a shuffle like this:
5315 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5316 // Check if it's possible to issue this instead.
5317 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5318 unsigned Idx = CountTrailingZeros_32(NonZeros);
5319 SDValue Item = Op.getOperand(Idx);
5320 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5321 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5326 // A vector full of immediates; various special cases are already
5327 // handled, so this is best done with a single constant-pool load.
5331 // For AVX-length vectors, build the individual 128-bit pieces and use
5332 // shuffles to put them in place.
5333 if (VT.getSizeInBits() == 256) {
5334 SmallVector<SDValue, 32> V;
5335 for (unsigned i = 0; i != NumElems; ++i)
5336 V.push_back(Op.getOperand(i));
5338 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5340 // Build both the lower and upper subvector.
5341 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5342 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5345 // Recreate the wider vector with the lower and upper part.
5346 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5349 // Let legalizer expand 2-wide build_vectors.
5350 if (EVTBits == 64) {
5351 if (NumNonZero == 1) {
5352 // One half is zero or undef.
5353 unsigned Idx = CountTrailingZeros_32(NonZeros);
5354 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5355 Op.getOperand(Idx));
5356 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5361 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5362 if (EVTBits == 8 && NumElems == 16) {
5363 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5365 if (V.getNode()) return V;
5368 if (EVTBits == 16 && NumElems == 8) {
5369 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5371 if (V.getNode()) return V;
5374 // If element VT is == 32 bits, turn it into a number of shuffles.
5375 SmallVector<SDValue, 8> V(NumElems);
5376 if (NumElems == 4 && NumZero > 0) {
5377 for (unsigned i = 0; i < 4; ++i) {
5378 bool isZero = !(NonZeros & (1 << i));
5380 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5382 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5385 for (unsigned i = 0; i < 2; ++i) {
5386 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5389 V[i] = V[i*2]; // Must be a zero vector.
5392 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5395 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5398 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5403 bool Reverse1 = (NonZeros & 0x3) == 2;
5404 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5408 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5409 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5411 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5414 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5415 // Check for a build vector of consecutive loads.
5416 for (unsigned i = 0; i < NumElems; ++i)
5417 V[i] = Op.getOperand(i);
5419 // Check for elements which are consecutive loads.
5420 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5424 // For SSE 4.1, use insertps to put the high elements into the low element.
5425 if (getSubtarget()->hasSSE41()) {
5427 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5428 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5430 Result = DAG.getUNDEF(VT);
5432 for (unsigned i = 1; i < NumElems; ++i) {
5433 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5434 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5435 Op.getOperand(i), DAG.getIntPtrConstant(i));
5440 // Otherwise, expand into a number of unpckl*, start by extending each of
5441 // our (non-undef) elements to the full vector width with the element in the
5442 // bottom slot of the vector (which generates no code for SSE).
5443 for (unsigned i = 0; i < NumElems; ++i) {
5444 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5445 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5447 V[i] = DAG.getUNDEF(VT);
5450 // Next, we iteratively mix elements, e.g. for v4f32:
5451 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5452 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5453 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5454 unsigned EltStride = NumElems >> 1;
5455 while (EltStride != 0) {
5456 for (unsigned i = 0; i < EltStride; ++i) {
5457 // If V[i+EltStride] is undef and this is the first round of mixing,
5458 // then it is safe to just drop this shuffle: V[i] is already in the
5459 // right place, the one element (since it's the first round) being
5460 // inserted as undef can be dropped. This isn't safe for successive
5461 // rounds because they will permute elements within both vectors.
5462 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5463 EltStride == NumElems/2)
5466 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5475 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5476 // them in a MMX register. This is better than doing a stack convert.
5477 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5478 DebugLoc dl = Op.getDebugLoc();
5479 EVT ResVT = Op.getValueType();
5481 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5482 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5484 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5485 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5486 InVec = Op.getOperand(1);
5487 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5488 unsigned NumElts = ResVT.getVectorNumElements();
5489 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5490 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5491 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5493 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5494 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5495 Mask[0] = 0; Mask[1] = 2;
5496 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5498 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5501 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5502 // to create 256-bit vectors from two other 128-bit ones.
5503 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5504 DebugLoc dl = Op.getDebugLoc();
5505 EVT ResVT = Op.getValueType();
5507 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5509 SDValue V1 = Op.getOperand(0);
5510 SDValue V2 = Op.getOperand(1);
5511 unsigned NumElems = ResVT.getVectorNumElements();
5513 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5517 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5518 EVT ResVT = Op.getValueType();
5520 assert(Op.getNumOperands() == 2);
5521 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5522 "Unsupported CONCAT_VECTORS for value type");
5524 // We support concatenate two MMX registers and place them in a MMX register.
5525 // This is better than doing a stack convert.
5526 if (ResVT.is128BitVector())
5527 return LowerMMXCONCAT_VECTORS(Op, DAG);
5529 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5530 // from two other 128-bit ones.
5531 return LowerAVXCONCAT_VECTORS(Op, DAG);
5534 // Try to lower a shuffle node into a simple blend instruction.
5535 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5536 const X86Subtarget *Subtarget,
5537 SelectionDAG &DAG) {
5538 SDValue V1 = SVOp->getOperand(0);
5539 SDValue V2 = SVOp->getOperand(1);
5540 DebugLoc dl = SVOp->getDebugLoc();
5541 MVT VT = SVOp->getValueType(0).getSimpleVT();
5542 unsigned NumElems = VT.getVectorNumElements();
5544 if (!Subtarget->hasSSE41())
5550 switch (VT.SimpleTy) {
5551 default: return SDValue();
5553 ISDNo = X86ISD::BLENDPW;
5558 ISDNo = X86ISD::BLENDPS;
5563 ISDNo = X86ISD::BLENDPD;
5568 if (!Subtarget->hasAVX())
5570 ISDNo = X86ISD::BLENDPS;
5575 if (!Subtarget->hasAVX())
5577 ISDNo = X86ISD::BLENDPD;
5581 assert(ISDNo && "Invalid Op Number");
5583 unsigned MaskVals = 0;
5585 for (unsigned i = 0; i != NumElems; ++i) {
5586 int EltIdx = SVOp->getMaskElt(i);
5587 if (EltIdx == (int)i || EltIdx < 0)
5589 else if (EltIdx == (int)(i + NumElems))
5590 continue; // Bit is set to zero;
5595 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5596 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5597 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5598 DAG.getConstant(MaskVals, MVT::i32));
5599 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5602 // v8i16 shuffles - Prefer shuffles in the following order:
5603 // 1. [all] pshuflw, pshufhw, optional move
5604 // 2. [ssse3] 1 x pshufb
5605 // 3. [ssse3] 2 x pshufb + 1 x por
5606 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5608 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5609 SelectionDAG &DAG) const {
5610 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5611 SDValue V1 = SVOp->getOperand(0);
5612 SDValue V2 = SVOp->getOperand(1);
5613 DebugLoc dl = SVOp->getDebugLoc();
5614 SmallVector<int, 8> MaskVals;
5616 // Determine if more than 1 of the words in each of the low and high quadwords
5617 // of the result come from the same quadword of one of the two inputs. Undef
5618 // mask values count as coming from any quadword, for better codegen.
5619 unsigned LoQuad[] = { 0, 0, 0, 0 };
5620 unsigned HiQuad[] = { 0, 0, 0, 0 };
5621 std::bitset<4> InputQuads;
5622 for (unsigned i = 0; i < 8; ++i) {
5623 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5624 int EltIdx = SVOp->getMaskElt(i);
5625 MaskVals.push_back(EltIdx);
5634 InputQuads.set(EltIdx / 4);
5637 int BestLoQuad = -1;
5638 unsigned MaxQuad = 1;
5639 for (unsigned i = 0; i < 4; ++i) {
5640 if (LoQuad[i] > MaxQuad) {
5642 MaxQuad = LoQuad[i];
5646 int BestHiQuad = -1;
5648 for (unsigned i = 0; i < 4; ++i) {
5649 if (HiQuad[i] > MaxQuad) {
5651 MaxQuad = HiQuad[i];
5655 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5656 // of the two input vectors, shuffle them into one input vector so only a
5657 // single pshufb instruction is necessary. If There are more than 2 input
5658 // quads, disable the next transformation since it does not help SSSE3.
5659 bool V1Used = InputQuads[0] || InputQuads[1];
5660 bool V2Used = InputQuads[2] || InputQuads[3];
5661 if (Subtarget->hasSSSE3()) {
5662 if (InputQuads.count() == 2 && V1Used && V2Used) {
5663 BestLoQuad = InputQuads[0] ? 0 : 1;
5664 BestHiQuad = InputQuads[2] ? 2 : 3;
5666 if (InputQuads.count() > 2) {
5672 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5673 // the shuffle mask. If a quad is scored as -1, that means that it contains
5674 // words from all 4 input quadwords.
5676 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5678 BestLoQuad < 0 ? 0 : BestLoQuad,
5679 BestHiQuad < 0 ? 1 : BestHiQuad
5681 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5682 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5683 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5684 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5686 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5687 // source words for the shuffle, to aid later transformations.
5688 bool AllWordsInNewV = true;
5689 bool InOrder[2] = { true, true };
5690 for (unsigned i = 0; i != 8; ++i) {
5691 int idx = MaskVals[i];
5693 InOrder[i/4] = false;
5694 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5696 AllWordsInNewV = false;
5700 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5701 if (AllWordsInNewV) {
5702 for (int i = 0; i != 8; ++i) {
5703 int idx = MaskVals[i];
5706 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5707 if ((idx != i) && idx < 4)
5709 if ((idx != i) && idx > 3)
5718 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5719 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5720 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5721 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5722 unsigned TargetMask = 0;
5723 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5724 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5726 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5727 getShufflePSHUFLWImmediate(SVOp);
5728 V1 = NewV.getOperand(0);
5729 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5733 // If we have SSSE3, and all words of the result are from 1 input vector,
5734 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5735 // is present, fall back to case 4.
5736 if (Subtarget->hasSSSE3()) {
5737 SmallVector<SDValue,16> pshufbMask;
5739 // If we have elements from both input vectors, set the high bit of the
5740 // shuffle mask element to zero out elements that come from V2 in the V1
5741 // mask, and elements that come from V1 in the V2 mask, so that the two
5742 // results can be OR'd together.
5743 bool TwoInputs = V1Used && V2Used;
5744 for (unsigned i = 0; i != 8; ++i) {
5745 int EltIdx = MaskVals[i] * 2;
5746 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5747 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5748 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5749 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5751 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5752 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5753 DAG.getNode(ISD::BUILD_VECTOR, dl,
5754 MVT::v16i8, &pshufbMask[0], 16));
5756 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5758 // Calculate the shuffle mask for the second input, shuffle it, and
5759 // OR it with the first shuffled input.
5761 for (unsigned i = 0; i != 8; ++i) {
5762 int EltIdx = MaskVals[i] * 2;
5763 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5764 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5765 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5766 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5768 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5769 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5770 DAG.getNode(ISD::BUILD_VECTOR, dl,
5771 MVT::v16i8, &pshufbMask[0], 16));
5772 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5773 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5776 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5777 // and update MaskVals with new element order.
5778 std::bitset<8> InOrder;
5779 if (BestLoQuad >= 0) {
5780 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5781 for (int i = 0; i != 4; ++i) {
5782 int idx = MaskVals[i];
5785 } else if ((idx / 4) == BestLoQuad) {
5790 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5793 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5794 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5795 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5797 getShufflePSHUFLWImmediate(SVOp), DAG);
5801 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5802 // and update MaskVals with the new element order.
5803 if (BestHiQuad >= 0) {
5804 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5805 for (unsigned i = 4; i != 8; ++i) {
5806 int idx = MaskVals[i];
5809 } else if ((idx / 4) == BestHiQuad) {
5810 MaskV[i] = (idx & 3) + 4;
5814 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5817 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5818 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5819 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5821 getShufflePSHUFHWImmediate(SVOp), DAG);
5825 // In case BestHi & BestLo were both -1, which means each quadword has a word
5826 // from each of the four input quadwords, calculate the InOrder bitvector now
5827 // before falling through to the insert/extract cleanup.
5828 if (BestLoQuad == -1 && BestHiQuad == -1) {
5830 for (int i = 0; i != 8; ++i)
5831 if (MaskVals[i] < 0 || MaskVals[i] == i)
5835 // The other elements are put in the right place using pextrw and pinsrw.
5836 for (unsigned i = 0; i != 8; ++i) {
5839 int EltIdx = MaskVals[i];
5842 SDValue ExtOp = (EltIdx < 8) ?
5843 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5844 DAG.getIntPtrConstant(EltIdx)) :
5845 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5846 DAG.getIntPtrConstant(EltIdx - 8));
5847 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5848 DAG.getIntPtrConstant(i));
5853 // v16i8 shuffles - Prefer shuffles in the following order:
5854 // 1. [ssse3] 1 x pshufb
5855 // 2. [ssse3] 2 x pshufb + 1 x por
5856 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5858 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5860 const X86TargetLowering &TLI) {
5861 SDValue V1 = SVOp->getOperand(0);
5862 SDValue V2 = SVOp->getOperand(1);
5863 DebugLoc dl = SVOp->getDebugLoc();
5864 ArrayRef<int> MaskVals = SVOp->getMask();
5866 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5868 // If we have SSSE3, case 1 is generated when all result bytes come from
5869 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5870 // present, fall back to case 3.
5872 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5873 if (TLI.getSubtarget()->hasSSSE3()) {
5874 SmallVector<SDValue,16> pshufbMask;
5876 // If all result elements are from one input vector, then only translate
5877 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5879 // Otherwise, we have elements from both input vectors, and must zero out
5880 // elements that come from V2 in the first mask, and V1 in the second mask
5881 // so that we can OR them together.
5882 for (unsigned i = 0; i != 16; ++i) {
5883 int EltIdx = MaskVals[i];
5884 if (EltIdx < 0 || EltIdx >= 16)
5886 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5888 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5889 DAG.getNode(ISD::BUILD_VECTOR, dl,
5890 MVT::v16i8, &pshufbMask[0], 16));
5894 // Calculate the shuffle mask for the second input, shuffle it, and
5895 // OR it with the first shuffled input.
5897 for (unsigned i = 0; i != 16; ++i) {
5898 int EltIdx = MaskVals[i];
5899 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5900 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5902 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5903 DAG.getNode(ISD::BUILD_VECTOR, dl,
5904 MVT::v16i8, &pshufbMask[0], 16));
5905 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5908 // No SSSE3 - Calculate in place words and then fix all out of place words
5909 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5910 // the 16 different words that comprise the two doublequadword input vectors.
5911 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5912 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5914 for (int i = 0; i != 8; ++i) {
5915 int Elt0 = MaskVals[i*2];
5916 int Elt1 = MaskVals[i*2+1];
5918 // This word of the result is all undef, skip it.
5919 if (Elt0 < 0 && Elt1 < 0)
5922 // This word of the result is already in the correct place, skip it.
5923 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5926 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5927 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5930 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5931 // using a single extract together, load it and store it.
5932 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5933 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5934 DAG.getIntPtrConstant(Elt1 / 2));
5935 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5936 DAG.getIntPtrConstant(i));
5940 // If Elt1 is defined, extract it from the appropriate source. If the
5941 // source byte is not also odd, shift the extracted word left 8 bits
5942 // otherwise clear the bottom 8 bits if we need to do an or.
5944 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5945 DAG.getIntPtrConstant(Elt1 / 2));
5946 if ((Elt1 & 1) == 0)
5947 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5949 TLI.getShiftAmountTy(InsElt.getValueType())));
5951 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5952 DAG.getConstant(0xFF00, MVT::i16));
5954 // If Elt0 is defined, extract it from the appropriate source. If the
5955 // source byte is not also even, shift the extracted word right 8 bits. If
5956 // Elt1 was also defined, OR the extracted values together before
5957 // inserting them in the result.
5959 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5960 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5961 if ((Elt0 & 1) != 0)
5962 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5964 TLI.getShiftAmountTy(InsElt0.getValueType())));
5966 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5967 DAG.getConstant(0x00FF, MVT::i16));
5968 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5971 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5972 DAG.getIntPtrConstant(i));
5974 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5977 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5978 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5979 /// done when every pair / quad of shuffle mask elements point to elements in
5980 /// the right sequence. e.g.
5981 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5983 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5984 SelectionDAG &DAG, DebugLoc dl) {
5985 MVT VT = SVOp->getValueType(0).getSimpleVT();
5986 unsigned NumElems = VT.getVectorNumElements();
5989 switch (VT.SimpleTy) {
5990 default: llvm_unreachable("Unexpected!");
5991 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
5992 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
5993 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
5994 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
5995 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
5996 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
5999 SmallVector<int, 8> MaskVec;
6000 for (unsigned i = 0; i != NumElems; i += Scale) {
6002 for (unsigned j = 0; j != Scale; ++j) {
6003 int EltIdx = SVOp->getMaskElt(i+j);
6007 StartIdx = (EltIdx / Scale);
6008 if (EltIdx != (int)(StartIdx*Scale + j))
6011 MaskVec.push_back(StartIdx);
6014 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6015 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6016 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6019 /// getVZextMovL - Return a zero-extending vector move low node.
6021 static SDValue getVZextMovL(EVT VT, EVT OpVT,
6022 SDValue SrcOp, SelectionDAG &DAG,
6023 const X86Subtarget *Subtarget, DebugLoc dl) {
6024 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6025 LoadSDNode *LD = NULL;
6026 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6027 LD = dyn_cast<LoadSDNode>(SrcOp);
6029 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6031 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6032 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6033 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6034 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6035 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6037 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6038 return DAG.getNode(ISD::BITCAST, dl, VT,
6039 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6040 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6048 return DAG.getNode(ISD::BITCAST, dl, VT,
6049 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6050 DAG.getNode(ISD::BITCAST, dl,
6054 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6055 /// which could not be matched by any known target speficic shuffle
6057 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6059 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6060 if (NewOp.getNode())
6063 EVT VT = SVOp->getValueType(0);
6065 unsigned NumElems = VT.getVectorNumElements();
6066 unsigned NumLaneElems = NumElems / 2;
6068 DebugLoc dl = SVOp->getDebugLoc();
6069 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6070 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6073 SmallVector<int, 16> Mask;
6074 for (unsigned l = 0; l < 2; ++l) {
6075 // Build a shuffle mask for the output, discovering on the fly which
6076 // input vectors to use as shuffle operands (recorded in InputUsed).
6077 // If building a suitable shuffle vector proves too hard, then bail
6078 // out with UseBuildVector set.
6079 bool UseBuildVector = false;
6080 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6081 unsigned LaneStart = l * NumLaneElems;
6082 for (unsigned i = 0; i != NumLaneElems; ++i) {
6083 // The mask element. This indexes into the input.
6084 int Idx = SVOp->getMaskElt(i+LaneStart);
6086 // the mask element does not index into any input vector.
6091 // The input vector this mask element indexes into.
6092 int Input = Idx / NumLaneElems;
6094 // Turn the index into an offset from the start of the input vector.
6095 Idx -= Input * NumLaneElems;
6097 // Find or create a shuffle vector operand to hold this input.
6099 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6100 if (InputUsed[OpNo] == Input)
6101 // This input vector is already an operand.
6103 if (InputUsed[OpNo] < 0) {
6104 // Create a new operand for this input vector.
6105 InputUsed[OpNo] = Input;
6110 if (OpNo >= array_lengthof(InputUsed)) {
6111 // More than two input vectors used! Give up on trying to create a
6112 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6113 UseBuildVector = true;
6117 // Add the mask index for the new shuffle vector.
6118 Mask.push_back(Idx + OpNo * NumLaneElems);
6121 if (UseBuildVector) {
6122 SmallVector<SDValue, 16> SVOps;
6123 for (unsigned i = 0; i != NumLaneElems; ++i) {
6124 // The mask element. This indexes into the input.
6125 int Idx = SVOp->getMaskElt(i+LaneStart);
6127 SVOps.push_back(DAG.getUNDEF(EltVT));
6131 // The input vector this mask element indexes into.
6132 int Input = Idx / NumElems;
6134 // Turn the index into an offset from the start of the input vector.
6135 Idx -= Input * NumElems;
6137 // Extract the vector element by hand.
6138 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6139 SVOp->getOperand(Input),
6140 DAG.getIntPtrConstant(Idx)));
6143 // Construct the output using a BUILD_VECTOR.
6144 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6146 } else if (InputUsed[0] < 0) {
6147 // No input vectors were used! The result is undefined.
6148 Output[l] = DAG.getUNDEF(NVT);
6150 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6151 (InputUsed[0] % 2) * NumLaneElems,
6153 // If only one input was used, use an undefined vector for the other.
6154 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6155 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6156 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6157 // At least one input vector was used. Create a new shuffle vector.
6158 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6164 // Concatenate the result back
6165 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6168 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6169 /// 4 elements, and match them with several different shuffle types.
6171 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6172 SDValue V1 = SVOp->getOperand(0);
6173 SDValue V2 = SVOp->getOperand(1);
6174 DebugLoc dl = SVOp->getDebugLoc();
6175 EVT VT = SVOp->getValueType(0);
6177 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6179 std::pair<int, int> Locs[4];
6180 int Mask1[] = { -1, -1, -1, -1 };
6181 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6185 for (unsigned i = 0; i != 4; ++i) {
6186 int Idx = PermMask[i];
6188 Locs[i] = std::make_pair(-1, -1);
6190 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6192 Locs[i] = std::make_pair(0, NumLo);
6196 Locs[i] = std::make_pair(1, NumHi);
6198 Mask1[2+NumHi] = Idx;
6204 if (NumLo <= 2 && NumHi <= 2) {
6205 // If no more than two elements come from either vector. This can be
6206 // implemented with two shuffles. First shuffle gather the elements.
6207 // The second shuffle, which takes the first shuffle as both of its
6208 // vector operands, put the elements into the right order.
6209 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6211 int Mask2[] = { -1, -1, -1, -1 };
6213 for (unsigned i = 0; i != 4; ++i)
6214 if (Locs[i].first != -1) {
6215 unsigned Idx = (i < 2) ? 0 : 4;
6216 Idx += Locs[i].first * 2 + Locs[i].second;
6220 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6223 if (NumLo == 3 || NumHi == 3) {
6224 // Otherwise, we must have three elements from one vector, call it X, and
6225 // one element from the other, call it Y. First, use a shufps to build an
6226 // intermediate vector with the one element from Y and the element from X
6227 // that will be in the same half in the final destination (the indexes don't
6228 // matter). Then, use a shufps to build the final vector, taking the half
6229 // containing the element from Y from the intermediate, and the other half
6232 // Normalize it so the 3 elements come from V1.
6233 CommuteVectorShuffleMask(PermMask, 4);
6237 // Find the element from V2.
6239 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6240 int Val = PermMask[HiIndex];
6247 Mask1[0] = PermMask[HiIndex];
6249 Mask1[2] = PermMask[HiIndex^1];
6251 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6254 Mask1[0] = PermMask[0];
6255 Mask1[1] = PermMask[1];
6256 Mask1[2] = HiIndex & 1 ? 6 : 4;
6257 Mask1[3] = HiIndex & 1 ? 4 : 6;
6258 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6261 Mask1[0] = HiIndex & 1 ? 2 : 0;
6262 Mask1[1] = HiIndex & 1 ? 0 : 2;
6263 Mask1[2] = PermMask[2];
6264 Mask1[3] = PermMask[3];
6269 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6272 // Break it into (shuffle shuffle_hi, shuffle_lo).
6273 int LoMask[] = { -1, -1, -1, -1 };
6274 int HiMask[] = { -1, -1, -1, -1 };
6276 int *MaskPtr = LoMask;
6277 unsigned MaskIdx = 0;
6280 for (unsigned i = 0; i != 4; ++i) {
6287 int Idx = PermMask[i];
6289 Locs[i] = std::make_pair(-1, -1);
6290 } else if (Idx < 4) {
6291 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6292 MaskPtr[LoIdx] = Idx;
6295 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6296 MaskPtr[HiIdx] = Idx;
6301 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6302 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6303 int MaskOps[] = { -1, -1, -1, -1 };
6304 for (unsigned i = 0; i != 4; ++i)
6305 if (Locs[i].first != -1)
6306 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6307 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6310 static bool MayFoldVectorLoad(SDValue V) {
6311 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6312 V = V.getOperand(0);
6313 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6314 V = V.getOperand(0);
6315 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6316 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6317 // BUILD_VECTOR (load), undef
6318 V = V.getOperand(0);
6324 // FIXME: the version above should always be used. Since there's
6325 // a bug where several vector shuffles can't be folded because the
6326 // DAG is not updated during lowering and a node claims to have two
6327 // uses while it only has one, use this version, and let isel match
6328 // another instruction if the load really happens to have more than
6329 // one use. Remove this version after this bug get fixed.
6330 // rdar://8434668, PR8156
6331 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6332 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6333 V = V.getOperand(0);
6334 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6335 V = V.getOperand(0);
6336 if (ISD::isNormalLoad(V.getNode()))
6342 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6343 EVT VT = Op.getValueType();
6345 // Canonizalize to v2f64.
6346 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6347 return DAG.getNode(ISD::BITCAST, dl, VT,
6348 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6353 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6355 SDValue V1 = Op.getOperand(0);
6356 SDValue V2 = Op.getOperand(1);
6357 EVT VT = Op.getValueType();
6359 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6361 if (HasSSE2 && VT == MVT::v2f64)
6362 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6364 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6365 return DAG.getNode(ISD::BITCAST, dl, VT,
6366 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6367 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6368 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6372 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6373 SDValue V1 = Op.getOperand(0);
6374 SDValue V2 = Op.getOperand(1);
6375 EVT VT = Op.getValueType();
6377 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6378 "unsupported shuffle type");
6380 if (V2.getOpcode() == ISD::UNDEF)
6384 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6388 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6389 SDValue V1 = Op.getOperand(0);
6390 SDValue V2 = Op.getOperand(1);
6391 EVT VT = Op.getValueType();
6392 unsigned NumElems = VT.getVectorNumElements();
6394 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6395 // operand of these instructions is only memory, so check if there's a
6396 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6398 bool CanFoldLoad = false;
6400 // Trivial case, when V2 comes from a load.
6401 if (MayFoldVectorLoad(V2))
6404 // When V1 is a load, it can be folded later into a store in isel, example:
6405 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6407 // (MOVLPSmr addr:$src1, VR128:$src2)
6408 // So, recognize this potential and also use MOVLPS or MOVLPD
6409 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6414 if (HasSSE2 && NumElems == 2)
6415 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6418 // If we don't care about the second element, proceed to use movss.
6419 if (SVOp->getMaskElt(1) != -1)
6420 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6423 // movl and movlp will both match v2i64, but v2i64 is never matched by
6424 // movl earlier because we make it strict to avoid messing with the movlp load
6425 // folding logic (see the code above getMOVLP call). Match it here then,
6426 // this is horrible, but will stay like this until we move all shuffle
6427 // matching to x86 specific nodes. Note that for the 1st condition all
6428 // types are matched with movsd.
6430 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6431 // as to remove this logic from here, as much as possible
6432 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6433 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6434 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6437 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6439 // Invert the operand order and use SHUFPS to match it.
6440 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6441 getShuffleSHUFImmediate(SVOp), DAG);
6445 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6446 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6447 EVT VT = Op.getValueType();
6448 DebugLoc dl = Op.getDebugLoc();
6449 SDValue V1 = Op.getOperand(0);
6450 SDValue V2 = Op.getOperand(1);
6452 if (isZeroShuffle(SVOp))
6453 return getZeroVector(VT, Subtarget, DAG, dl);
6455 // Handle splat operations
6456 if (SVOp->isSplat()) {
6457 unsigned NumElem = VT.getVectorNumElements();
6458 int Size = VT.getSizeInBits();
6460 // Use vbroadcast whenever the splat comes from a foldable load
6461 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6462 if (Broadcast.getNode())
6465 // Handle splats by matching through known shuffle masks
6466 if ((Size == 128 && NumElem <= 4) ||
6467 (Size == 256 && NumElem < 8))
6470 // All remaning splats are promoted to target supported vector shuffles.
6471 return PromoteSplat(SVOp, DAG);
6474 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6476 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6477 VT == MVT::v16i16 || VT == MVT::v32i8) {
6478 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6479 if (NewOp.getNode())
6480 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6481 } else if ((VT == MVT::v4i32 ||
6482 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6483 // FIXME: Figure out a cleaner way to do this.
6484 // Try to make use of movq to zero out the top part.
6485 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6486 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6487 if (NewOp.getNode()) {
6488 EVT NewVT = NewOp.getValueType();
6489 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6490 NewVT, true, false))
6491 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6492 DAG, Subtarget, dl);
6494 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6495 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6496 if (NewOp.getNode()) {
6497 EVT NewVT = NewOp.getValueType();
6498 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6499 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6500 DAG, Subtarget, dl);
6508 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6509 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6510 SDValue V1 = Op.getOperand(0);
6511 SDValue V2 = Op.getOperand(1);
6512 EVT VT = Op.getValueType();
6513 DebugLoc dl = Op.getDebugLoc();
6514 unsigned NumElems = VT.getVectorNumElements();
6515 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6516 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6517 bool V1IsSplat = false;
6518 bool V2IsSplat = false;
6519 bool HasSSE2 = Subtarget->hasSSE2();
6520 bool HasAVX = Subtarget->hasAVX();
6521 bool HasAVX2 = Subtarget->hasAVX2();
6522 MachineFunction &MF = DAG.getMachineFunction();
6523 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6525 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6527 if (V1IsUndef && V2IsUndef)
6528 return DAG.getUNDEF(VT);
6530 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6532 // Vector shuffle lowering takes 3 steps:
6534 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6535 // narrowing and commutation of operands should be handled.
6536 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6538 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6539 // so the shuffle can be broken into other shuffles and the legalizer can
6540 // try the lowering again.
6542 // The general idea is that no vector_shuffle operation should be left to
6543 // be matched during isel, all of them must be converted to a target specific
6546 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6547 // narrowing and commutation of operands should be handled. The actual code
6548 // doesn't include all of those, work in progress...
6549 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6550 if (NewOp.getNode())
6553 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6555 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6556 // unpckh_undef). Only use pshufd if speed is more important than size.
6557 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6558 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6559 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6560 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6562 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6563 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6564 return getMOVDDup(Op, dl, V1, DAG);
6566 if (isMOVHLPS_v_undef_Mask(M, VT))
6567 return getMOVHighToLow(Op, dl, DAG);
6569 // Use to match splats
6570 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6571 (VT == MVT::v2f64 || VT == MVT::v2i64))
6572 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6574 if (isPSHUFDMask(M, VT)) {
6575 // The actual implementation will match the mask in the if above and then
6576 // during isel it can match several different instructions, not only pshufd
6577 // as its name says, sad but true, emulate the behavior for now...
6578 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6579 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6581 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6583 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6584 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6586 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6587 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6589 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6593 // Check if this can be converted into a logical shift.
6594 bool isLeft = false;
6597 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6598 if (isShift && ShVal.hasOneUse()) {
6599 // If the shifted value has multiple uses, it may be cheaper to use
6600 // v_set0 + movlhps or movhlps, etc.
6601 EVT EltVT = VT.getVectorElementType();
6602 ShAmt *= EltVT.getSizeInBits();
6603 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6606 if (isMOVLMask(M, VT)) {
6607 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6608 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6609 if (!isMOVLPMask(M, VT)) {
6610 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6611 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6613 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6614 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6618 // FIXME: fold these into legal mask.
6619 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6620 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6622 if (isMOVHLPSMask(M, VT))
6623 return getMOVHighToLow(Op, dl, DAG);
6625 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6626 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6628 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6629 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6631 if (isMOVLPMask(M, VT))
6632 return getMOVLP(Op, dl, DAG, HasSSE2);
6634 if (ShouldXformToMOVHLPS(M, VT) ||
6635 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6636 return CommuteVectorShuffle(SVOp, DAG);
6639 // No better options. Use a vshldq / vsrldq.
6640 EVT EltVT = VT.getVectorElementType();
6641 ShAmt *= EltVT.getSizeInBits();
6642 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6645 bool Commuted = false;
6646 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6647 // 1,1,1,1 -> v8i16 though.
6648 V1IsSplat = isSplatVector(V1.getNode());
6649 V2IsSplat = isSplatVector(V2.getNode());
6651 // Canonicalize the splat or undef, if present, to be on the RHS.
6652 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6653 CommuteVectorShuffleMask(M, NumElems);
6655 std::swap(V1IsSplat, V2IsSplat);
6659 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6660 // Shuffling low element of v1 into undef, just return v1.
6663 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6664 // the instruction selector will not match, so get a canonical MOVL with
6665 // swapped operands to undo the commute.
6666 return getMOVL(DAG, dl, VT, V2, V1);
6669 if (isUNPCKLMask(M, VT, HasAVX2))
6670 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6672 if (isUNPCKHMask(M, VT, HasAVX2))
6673 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6676 // Normalize mask so all entries that point to V2 points to its first
6677 // element then try to match unpck{h|l} again. If match, return a
6678 // new vector_shuffle with the corrected mask.p
6679 SmallVector<int, 8> NewMask(M.begin(), M.end());
6680 NormalizeMask(NewMask, NumElems);
6681 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6682 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6683 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6684 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6688 // Commute is back and try unpck* again.
6689 // FIXME: this seems wrong.
6690 CommuteVectorShuffleMask(M, NumElems);
6692 std::swap(V1IsSplat, V2IsSplat);
6695 if (isUNPCKLMask(M, VT, HasAVX2))
6696 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6698 if (isUNPCKHMask(M, VT, HasAVX2))
6699 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6702 // Normalize the node to match x86 shuffle ops if needed
6703 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6704 return CommuteVectorShuffle(SVOp, DAG);
6706 // The checks below are all present in isShuffleMaskLegal, but they are
6707 // inlined here right now to enable us to directly emit target specific
6708 // nodes, and remove one by one until they don't return Op anymore.
6710 if (isPALIGNRMask(M, VT, Subtarget))
6711 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6712 getShufflePALIGNRImmediate(SVOp),
6715 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6716 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6717 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6718 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6721 if (isPSHUFHWMask(M, VT, HasAVX2))
6722 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6723 getShufflePSHUFHWImmediate(SVOp),
6726 if (isPSHUFLWMask(M, VT, HasAVX2))
6727 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6728 getShufflePSHUFLWImmediate(SVOp),
6731 if (isSHUFPMask(M, VT, HasAVX))
6732 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6733 getShuffleSHUFImmediate(SVOp), DAG);
6735 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6736 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6737 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6738 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6740 //===--------------------------------------------------------------------===//
6741 // Generate target specific nodes for 128 or 256-bit shuffles only
6742 // supported in the AVX instruction set.
6745 // Handle VMOVDDUPY permutations
6746 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6747 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6749 // Handle VPERMILPS/D* permutations
6750 if (isVPERMILPMask(M, VT, HasAVX)) {
6751 if (HasAVX2 && VT == MVT::v8i32)
6752 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6753 getShuffleSHUFImmediate(SVOp), DAG);
6754 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6755 getShuffleSHUFImmediate(SVOp), DAG);
6758 // Handle VPERM2F128/VPERM2I128 permutations
6759 if (isVPERM2X128Mask(M, VT, HasAVX))
6760 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6761 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6763 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6764 if (BlendOp.getNode())
6767 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6768 SmallVector<SDValue, 8> permclMask;
6769 for (unsigned i = 0; i != 8; ++i) {
6770 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6772 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6774 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6775 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6776 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6779 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6780 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6781 getShuffleCLImmediate(SVOp), DAG);
6784 //===--------------------------------------------------------------------===//
6785 // Since no target specific shuffle was selected for this generic one,
6786 // lower it into other known shuffles. FIXME: this isn't true yet, but
6787 // this is the plan.
6790 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6791 if (VT == MVT::v8i16) {
6792 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6793 if (NewOp.getNode())
6797 if (VT == MVT::v16i8) {
6798 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6799 if (NewOp.getNode())
6803 // Handle all 128-bit wide vectors with 4 elements, and match them with
6804 // several different shuffle types.
6805 if (NumElems == 4 && VT.getSizeInBits() == 128)
6806 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6808 // Handle general 256-bit shuffles
6809 if (VT.is256BitVector())
6810 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6816 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6817 SelectionDAG &DAG) const {
6818 EVT VT = Op.getValueType();
6819 DebugLoc dl = Op.getDebugLoc();
6821 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6824 if (VT.getSizeInBits() == 8) {
6825 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6826 Op.getOperand(0), Op.getOperand(1));
6827 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6828 DAG.getValueType(VT));
6829 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6832 if (VT.getSizeInBits() == 16) {
6833 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6834 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6836 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6837 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6838 DAG.getNode(ISD::BITCAST, dl,
6842 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6843 Op.getOperand(0), Op.getOperand(1));
6844 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6845 DAG.getValueType(VT));
6846 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6849 if (VT == MVT::f32) {
6850 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6851 // the result back to FR32 register. It's only worth matching if the
6852 // result has a single use which is a store or a bitcast to i32. And in
6853 // the case of a store, it's not worth it if the index is a constant 0,
6854 // because a MOVSSmr can be used instead, which is smaller and faster.
6855 if (!Op.hasOneUse())
6857 SDNode *User = *Op.getNode()->use_begin();
6858 if ((User->getOpcode() != ISD::STORE ||
6859 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6860 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6861 (User->getOpcode() != ISD::BITCAST ||
6862 User->getValueType(0) != MVT::i32))
6864 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6865 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6868 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6871 if (VT == MVT::i32 || VT == MVT::i64) {
6872 // ExtractPS/pextrq works with constant index.
6873 if (isa<ConstantSDNode>(Op.getOperand(1)))
6881 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6882 SelectionDAG &DAG) const {
6883 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6886 SDValue Vec = Op.getOperand(0);
6887 EVT VecVT = Vec.getValueType();
6889 // If this is a 256-bit vector result, first extract the 128-bit vector and
6890 // then extract the element from the 128-bit vector.
6891 if (VecVT.getSizeInBits() == 256) {
6892 DebugLoc dl = Op.getNode()->getDebugLoc();
6893 unsigned NumElems = VecVT.getVectorNumElements();
6894 SDValue Idx = Op.getOperand(1);
6895 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6897 // Get the 128-bit vector.
6898 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6900 if (IdxVal >= NumElems/2)
6901 IdxVal -= NumElems/2;
6902 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6903 DAG.getConstant(IdxVal, MVT::i32));
6906 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6908 if (Subtarget->hasSSE41()) {
6909 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6914 EVT VT = Op.getValueType();
6915 DebugLoc dl = Op.getDebugLoc();
6916 // TODO: handle v16i8.
6917 if (VT.getSizeInBits() == 16) {
6918 SDValue Vec = Op.getOperand(0);
6919 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6921 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6922 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6923 DAG.getNode(ISD::BITCAST, dl,
6926 // Transform it so it match pextrw which produces a 32-bit result.
6927 EVT EltVT = MVT::i32;
6928 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6929 Op.getOperand(0), Op.getOperand(1));
6930 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6931 DAG.getValueType(VT));
6932 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6935 if (VT.getSizeInBits() == 32) {
6936 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6940 // SHUFPS the element to the lowest double word, then movss.
6941 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6942 EVT VVT = Op.getOperand(0).getValueType();
6943 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6944 DAG.getUNDEF(VVT), Mask);
6945 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6946 DAG.getIntPtrConstant(0));
6949 if (VT.getSizeInBits() == 64) {
6950 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6951 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6952 // to match extract_elt for f64.
6953 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6957 // UNPCKHPD the element to the lowest double word, then movsd.
6958 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6959 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6960 int Mask[2] = { 1, -1 };
6961 EVT VVT = Op.getOperand(0).getValueType();
6962 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6963 DAG.getUNDEF(VVT), Mask);
6964 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6965 DAG.getIntPtrConstant(0));
6972 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6973 SelectionDAG &DAG) const {
6974 EVT VT = Op.getValueType();
6975 EVT EltVT = VT.getVectorElementType();
6976 DebugLoc dl = Op.getDebugLoc();
6978 SDValue N0 = Op.getOperand(0);
6979 SDValue N1 = Op.getOperand(1);
6980 SDValue N2 = Op.getOperand(2);
6982 if (VT.getSizeInBits() == 256)
6985 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6986 isa<ConstantSDNode>(N2)) {
6988 if (VT == MVT::v8i16)
6989 Opc = X86ISD::PINSRW;
6990 else if (VT == MVT::v16i8)
6991 Opc = X86ISD::PINSRB;
6993 Opc = X86ISD::PINSRB;
6995 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6997 if (N1.getValueType() != MVT::i32)
6998 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6999 if (N2.getValueType() != MVT::i32)
7000 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7001 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7004 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7005 // Bits [7:6] of the constant are the source select. This will always be
7006 // zero here. The DAG Combiner may combine an extract_elt index into these
7007 // bits. For example (insert (extract, 3), 2) could be matched by putting
7008 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7009 // Bits [5:4] of the constant are the destination select. This is the
7010 // value of the incoming immediate.
7011 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7012 // combine either bitwise AND or insert of float 0.0 to set these bits.
7013 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7014 // Create this as a scalar to vector..
7015 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7016 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7019 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7020 // PINSR* works with constant index.
7027 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7028 EVT VT = Op.getValueType();
7029 EVT EltVT = VT.getVectorElementType();
7031 DebugLoc dl = Op.getDebugLoc();
7032 SDValue N0 = Op.getOperand(0);
7033 SDValue N1 = Op.getOperand(1);
7034 SDValue N2 = Op.getOperand(2);
7036 // If this is a 256-bit vector result, first extract the 128-bit vector,
7037 // insert the element into the extracted half and then place it back.
7038 if (VT.getSizeInBits() == 256) {
7039 if (!isa<ConstantSDNode>(N2))
7042 // Get the desired 128-bit vector half.
7043 unsigned NumElems = VT.getVectorNumElements();
7044 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7045 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7047 // Insert the element into the desired half.
7048 bool Upper = IdxVal >= NumElems/2;
7049 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7050 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7052 // Insert the changed part back to the 256-bit vector
7053 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7056 if (Subtarget->hasSSE41())
7057 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7059 if (EltVT == MVT::i8)
7062 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7063 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7064 // as its second argument.
7065 if (N1.getValueType() != MVT::i32)
7066 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7067 if (N2.getValueType() != MVT::i32)
7068 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7069 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7075 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7076 LLVMContext *Context = DAG.getContext();
7077 DebugLoc dl = Op.getDebugLoc();
7078 EVT OpVT = Op.getValueType();
7080 // If this is a 256-bit vector result, first insert into a 128-bit
7081 // vector and then insert into the 256-bit vector.
7082 if (OpVT.getSizeInBits() > 128) {
7083 // Insert into a 128-bit vector.
7084 EVT VT128 = EVT::getVectorVT(*Context,
7085 OpVT.getVectorElementType(),
7086 OpVT.getVectorNumElements() / 2);
7088 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7090 // Insert the 128-bit vector.
7091 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7094 if (OpVT == MVT::v1i64 &&
7095 Op.getOperand(0).getValueType() == MVT::i64)
7096 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7098 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7099 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
7100 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7101 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7104 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7105 // a simple subregister reference or explicit instructions to grab
7106 // upper bits of a vector.
7108 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7109 if (Subtarget->hasAVX()) {
7110 DebugLoc dl = Op.getNode()->getDebugLoc();
7111 SDValue Vec = Op.getNode()->getOperand(0);
7112 SDValue Idx = Op.getNode()->getOperand(1);
7114 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
7115 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
7116 isa<ConstantSDNode>(Idx)) {
7117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7118 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7124 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7125 // simple superregister reference or explicit instructions to insert
7126 // the upper bits of a vector.
7128 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7129 if (Subtarget->hasAVX()) {
7130 DebugLoc dl = Op.getNode()->getDebugLoc();
7131 SDValue Vec = Op.getNode()->getOperand(0);
7132 SDValue SubVec = Op.getNode()->getOperand(1);
7133 SDValue Idx = Op.getNode()->getOperand(2);
7135 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7136 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7137 isa<ConstantSDNode>(Idx)) {
7138 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7139 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7145 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7146 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7147 // one of the above mentioned nodes. It has to be wrapped because otherwise
7148 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7149 // be used to form addressing mode. These wrapped nodes will be selected
7152 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7153 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7155 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7157 unsigned char OpFlag = 0;
7158 unsigned WrapperKind = X86ISD::Wrapper;
7159 CodeModel::Model M = getTargetMachine().getCodeModel();
7161 if (Subtarget->isPICStyleRIPRel() &&
7162 (M == CodeModel::Small || M == CodeModel::Kernel))
7163 WrapperKind = X86ISD::WrapperRIP;
7164 else if (Subtarget->isPICStyleGOT())
7165 OpFlag = X86II::MO_GOTOFF;
7166 else if (Subtarget->isPICStyleStubPIC())
7167 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7169 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7171 CP->getOffset(), OpFlag);
7172 DebugLoc DL = CP->getDebugLoc();
7173 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7174 // With PIC, the address is actually $g + Offset.
7176 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7177 DAG.getNode(X86ISD::GlobalBaseReg,
7178 DebugLoc(), getPointerTy()),
7185 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7186 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7188 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7190 unsigned char OpFlag = 0;
7191 unsigned WrapperKind = X86ISD::Wrapper;
7192 CodeModel::Model M = getTargetMachine().getCodeModel();
7194 if (Subtarget->isPICStyleRIPRel() &&
7195 (M == CodeModel::Small || M == CodeModel::Kernel))
7196 WrapperKind = X86ISD::WrapperRIP;
7197 else if (Subtarget->isPICStyleGOT())
7198 OpFlag = X86II::MO_GOTOFF;
7199 else if (Subtarget->isPICStyleStubPIC())
7200 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7202 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7204 DebugLoc DL = JT->getDebugLoc();
7205 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7207 // With PIC, the address is actually $g + Offset.
7209 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7210 DAG.getNode(X86ISD::GlobalBaseReg,
7211 DebugLoc(), getPointerTy()),
7218 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7219 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7221 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7223 unsigned char OpFlag = 0;
7224 unsigned WrapperKind = X86ISD::Wrapper;
7225 CodeModel::Model M = getTargetMachine().getCodeModel();
7227 if (Subtarget->isPICStyleRIPRel() &&
7228 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7229 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7230 OpFlag = X86II::MO_GOTPCREL;
7231 WrapperKind = X86ISD::WrapperRIP;
7232 } else if (Subtarget->isPICStyleGOT()) {
7233 OpFlag = X86II::MO_GOT;
7234 } else if (Subtarget->isPICStyleStubPIC()) {
7235 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7236 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7237 OpFlag = X86II::MO_DARWIN_NONLAZY;
7240 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7242 DebugLoc DL = Op.getDebugLoc();
7243 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7246 // With PIC, the address is actually $g + Offset.
7247 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7248 !Subtarget->is64Bit()) {
7249 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7250 DAG.getNode(X86ISD::GlobalBaseReg,
7251 DebugLoc(), getPointerTy()),
7255 // For symbols that require a load from a stub to get the address, emit the
7257 if (isGlobalStubReference(OpFlag))
7258 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7259 MachinePointerInfo::getGOT(), false, false, false, 0);
7265 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7266 // Create the TargetBlockAddressAddress node.
7267 unsigned char OpFlags =
7268 Subtarget->ClassifyBlockAddressReference();
7269 CodeModel::Model M = getTargetMachine().getCodeModel();
7270 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7271 DebugLoc dl = Op.getDebugLoc();
7272 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7273 /*isTarget=*/true, OpFlags);
7275 if (Subtarget->isPICStyleRIPRel() &&
7276 (M == CodeModel::Small || M == CodeModel::Kernel))
7277 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7279 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7281 // With PIC, the address is actually $g + Offset.
7282 if (isGlobalRelativeToPICBase(OpFlags)) {
7283 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7284 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7292 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7294 SelectionDAG &DAG) const {
7295 // Create the TargetGlobalAddress node, folding in the constant
7296 // offset if it is legal.
7297 unsigned char OpFlags =
7298 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7299 CodeModel::Model M = getTargetMachine().getCodeModel();
7301 if (OpFlags == X86II::MO_NO_FLAG &&
7302 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7303 // A direct static reference to a global.
7304 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7307 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7310 if (Subtarget->isPICStyleRIPRel() &&
7311 (M == CodeModel::Small || M == CodeModel::Kernel))
7312 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7314 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7316 // With PIC, the address is actually $g + Offset.
7317 if (isGlobalRelativeToPICBase(OpFlags)) {
7318 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7319 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7323 // For globals that require a load from a stub to get the address, emit the
7325 if (isGlobalStubReference(OpFlags))
7326 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7327 MachinePointerInfo::getGOT(), false, false, false, 0);
7329 // If there was a non-zero offset that we didn't fold, create an explicit
7332 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7333 DAG.getConstant(Offset, getPointerTy()));
7339 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7340 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7341 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7342 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7346 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7347 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7348 unsigned char OperandFlags, bool LocalDynamic = false) {
7349 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7350 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7351 DebugLoc dl = GA->getDebugLoc();
7352 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7353 GA->getValueType(0),
7357 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7361 SDValue Ops[] = { Chain, TGA, *InFlag };
7362 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7364 SDValue Ops[] = { Chain, TGA };
7365 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7368 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7369 MFI->setAdjustsStack(true);
7371 SDValue Flag = Chain.getValue(1);
7372 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7375 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7377 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7380 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7381 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7382 DAG.getNode(X86ISD::GlobalBaseReg,
7383 DebugLoc(), PtrVT), InFlag);
7384 InFlag = Chain.getValue(1);
7386 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7389 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7391 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7393 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7394 X86::RAX, X86II::MO_TLSGD);
7397 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7401 DebugLoc dl = GA->getDebugLoc();
7403 // Get the start address of the TLS block for this module.
7404 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7405 .getInfo<X86MachineFunctionInfo>();
7406 MFI->incNumLocalDynamicTLSAccesses();
7410 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7411 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7414 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7415 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7416 InFlag = Chain.getValue(1);
7417 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7418 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7421 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7425 unsigned char OperandFlags = X86II::MO_DTPOFF;
7426 unsigned WrapperKind = X86ISD::Wrapper;
7427 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7428 GA->getValueType(0),
7429 GA->getOffset(), OperandFlags);
7430 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7432 // Add x@dtpoff with the base.
7433 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7436 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7437 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7438 const EVT PtrVT, TLSModel::Model model,
7439 bool is64Bit, bool isPIC) {
7440 DebugLoc dl = GA->getDebugLoc();
7442 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7443 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7444 is64Bit ? 257 : 256));
7446 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7447 DAG.getIntPtrConstant(0),
7448 MachinePointerInfo(Ptr),
7449 false, false, false, 0);
7451 unsigned char OperandFlags = 0;
7452 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7454 unsigned WrapperKind = X86ISD::Wrapper;
7455 if (model == TLSModel::LocalExec) {
7456 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7457 } else if (model == TLSModel::InitialExec) {
7459 OperandFlags = X86II::MO_GOTTPOFF;
7460 WrapperKind = X86ISD::WrapperRIP;
7462 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7465 llvm_unreachable("Unexpected model");
7468 // emit "addl x@ntpoff,%eax" (local exec)
7469 // or "addl x@indntpoff,%eax" (initial exec)
7470 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7471 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7472 GA->getValueType(0),
7473 GA->getOffset(), OperandFlags);
7474 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7476 if (model == TLSModel::InitialExec) {
7477 if (isPIC && !is64Bit) {
7478 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7479 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7483 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7484 MachinePointerInfo::getGOT(), false, false, false,
7488 // The address of the thread local variable is the add of the thread
7489 // pointer with the offset of the variable.
7490 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7494 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7496 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7497 const GlobalValue *GV = GA->getGlobal();
7499 if (Subtarget->isTargetELF()) {
7500 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7503 case TLSModel::GeneralDynamic:
7504 if (Subtarget->is64Bit())
7505 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7506 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7507 case TLSModel::LocalDynamic:
7508 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7509 Subtarget->is64Bit());
7510 case TLSModel::InitialExec:
7511 case TLSModel::LocalExec:
7512 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7513 Subtarget->is64Bit(),
7514 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7516 llvm_unreachable("Unknown TLS model.");
7519 if (Subtarget->isTargetDarwin()) {
7520 // Darwin only has one model of TLS. Lower to that.
7521 unsigned char OpFlag = 0;
7522 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7523 X86ISD::WrapperRIP : X86ISD::Wrapper;
7525 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7527 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7528 !Subtarget->is64Bit();
7530 OpFlag = X86II::MO_TLVP_PIC_BASE;
7532 OpFlag = X86II::MO_TLVP;
7533 DebugLoc DL = Op.getDebugLoc();
7534 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7535 GA->getValueType(0),
7536 GA->getOffset(), OpFlag);
7537 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7539 // With PIC32, the address is actually $g + Offset.
7541 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7542 DAG.getNode(X86ISD::GlobalBaseReg,
7543 DebugLoc(), getPointerTy()),
7546 // Lowering the machine isd will make sure everything is in the right
7548 SDValue Chain = DAG.getEntryNode();
7549 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7550 SDValue Args[] = { Chain, Offset };
7551 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7553 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7554 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7555 MFI->setAdjustsStack(true);
7557 // And our return value (tls address) is in the standard call return value
7559 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7560 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7564 if (Subtarget->isTargetWindows()) {
7565 // Just use the implicit TLS architecture
7566 // Need to generate someting similar to:
7567 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7569 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7570 // mov rcx, qword [rdx+rcx*8]
7571 // mov eax, .tls$:tlsvar
7572 // [rax+rcx] contains the address
7573 // Windows 64bit: gs:0x58
7574 // Windows 32bit: fs:__tls_array
7576 // If GV is an alias then use the aliasee for determining
7577 // thread-localness.
7578 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7579 GV = GA->resolveAliasedGlobal(false);
7580 DebugLoc dl = GA->getDebugLoc();
7581 SDValue Chain = DAG.getEntryNode();
7583 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7584 // %gs:0x58 (64-bit).
7585 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7586 ? Type::getInt8PtrTy(*DAG.getContext(),
7588 : Type::getInt32PtrTy(*DAG.getContext(),
7591 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7592 Subtarget->is64Bit()
7593 ? DAG.getIntPtrConstant(0x58)
7594 : DAG.getExternalSymbol("_tls_array",
7596 MachinePointerInfo(Ptr),
7597 false, false, false, 0);
7599 // Load the _tls_index variable
7600 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7601 if (Subtarget->is64Bit())
7602 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7603 IDX, MachinePointerInfo(), MVT::i32,
7606 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7607 false, false, false, 0);
7609 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7611 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7613 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7614 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7615 false, false, false, 0);
7617 // Get the offset of start of .tls section
7618 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7619 GA->getValueType(0),
7620 GA->getOffset(), X86II::MO_SECREL);
7621 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7623 // The address of the thread local variable is the add of the thread
7624 // pointer with the offset of the variable.
7625 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7628 llvm_unreachable("TLS not implemented for this target.");
7632 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7633 /// and take a 2 x i32 value to shift plus a shift amount.
7634 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7635 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7636 EVT VT = Op.getValueType();
7637 unsigned VTBits = VT.getSizeInBits();
7638 DebugLoc dl = Op.getDebugLoc();
7639 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7640 SDValue ShOpLo = Op.getOperand(0);
7641 SDValue ShOpHi = Op.getOperand(1);
7642 SDValue ShAmt = Op.getOperand(2);
7643 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7644 DAG.getConstant(VTBits - 1, MVT::i8))
7645 : DAG.getConstant(0, VT);
7648 if (Op.getOpcode() == ISD::SHL_PARTS) {
7649 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7650 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7652 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7653 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7656 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7657 DAG.getConstant(VTBits, MVT::i8));
7658 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7659 AndNode, DAG.getConstant(0, MVT::i8));
7662 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7663 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7664 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7666 if (Op.getOpcode() == ISD::SHL_PARTS) {
7667 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7668 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7670 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7671 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7674 SDValue Ops[2] = { Lo, Hi };
7675 return DAG.getMergeValues(Ops, 2, dl);
7678 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7679 SelectionDAG &DAG) const {
7680 EVT SrcVT = Op.getOperand(0).getValueType();
7682 if (SrcVT.isVector())
7685 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7686 "Unknown SINT_TO_FP to lower!");
7688 // These are really Legal; return the operand so the caller accepts it as
7690 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7692 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7693 Subtarget->is64Bit()) {
7697 DebugLoc dl = Op.getDebugLoc();
7698 unsigned Size = SrcVT.getSizeInBits()/8;
7699 MachineFunction &MF = DAG.getMachineFunction();
7700 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7701 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7702 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7704 MachinePointerInfo::getFixedStack(SSFI),
7706 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7709 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7711 SelectionDAG &DAG) const {
7713 DebugLoc DL = Op.getDebugLoc();
7715 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7717 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7719 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7721 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7723 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7724 MachineMemOperand *MMO;
7726 int SSFI = FI->getIndex();
7728 DAG.getMachineFunction()
7729 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7730 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7732 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7733 StackSlot = StackSlot.getOperand(1);
7735 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7736 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7738 Tys, Ops, array_lengthof(Ops),
7742 Chain = Result.getValue(1);
7743 SDValue InFlag = Result.getValue(2);
7745 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7746 // shouldn't be necessary except that RFP cannot be live across
7747 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7748 MachineFunction &MF = DAG.getMachineFunction();
7749 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7750 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7751 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7752 Tys = DAG.getVTList(MVT::Other);
7754 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7756 MachineMemOperand *MMO =
7757 DAG.getMachineFunction()
7758 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7759 MachineMemOperand::MOStore, SSFISize, SSFISize);
7761 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7762 Ops, array_lengthof(Ops),
7763 Op.getValueType(), MMO);
7764 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7765 MachinePointerInfo::getFixedStack(SSFI),
7766 false, false, false, 0);
7772 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7773 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7774 SelectionDAG &DAG) const {
7775 // This algorithm is not obvious. Here it is what we're trying to output:
7778 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7779 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7783 pshufd $0x4e, %xmm0, %xmm1
7788 DebugLoc dl = Op.getDebugLoc();
7789 LLVMContext *Context = DAG.getContext();
7791 // Build some magic constants.
7792 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7793 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7794 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7796 SmallVector<Constant*,2> CV1;
7798 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7800 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7801 Constant *C1 = ConstantVector::get(CV1);
7802 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7804 // Load the 64-bit value into an XMM register.
7805 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7807 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7808 MachinePointerInfo::getConstantPool(),
7809 false, false, false, 16);
7810 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7811 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7814 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7815 MachinePointerInfo::getConstantPool(),
7816 false, false, false, 16);
7817 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7818 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7821 if (Subtarget->hasSSE3()) {
7822 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7823 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7825 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7826 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7828 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7829 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7833 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7834 DAG.getIntPtrConstant(0));
7837 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7838 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7839 SelectionDAG &DAG) const {
7840 DebugLoc dl = Op.getDebugLoc();
7841 // FP constant to bias correct the final result.
7842 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7845 // Load the 32-bit value into an XMM register.
7846 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7849 // Zero out the upper parts of the register.
7850 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7852 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7853 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7854 DAG.getIntPtrConstant(0));
7856 // Or the load with the bias.
7857 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7858 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7859 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7861 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7862 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7863 MVT::v2f64, Bias)));
7864 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7865 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7866 DAG.getIntPtrConstant(0));
7868 // Subtract the bias.
7869 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7871 // Handle final rounding.
7872 EVT DestVT = Op.getValueType();
7874 if (DestVT.bitsLT(MVT::f64))
7875 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7876 DAG.getIntPtrConstant(0));
7877 if (DestVT.bitsGT(MVT::f64))
7878 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7880 // Handle final rounding.
7884 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7885 SelectionDAG &DAG) const {
7886 SDValue N0 = Op.getOperand(0);
7887 DebugLoc dl = Op.getDebugLoc();
7889 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7890 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7891 // the optimization here.
7892 if (DAG.SignBitIsZero(N0))
7893 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7895 EVT SrcVT = N0.getValueType();
7896 EVT DstVT = Op.getValueType();
7897 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7898 return LowerUINT_TO_FP_i64(Op, DAG);
7899 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7900 return LowerUINT_TO_FP_i32(Op, DAG);
7901 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7904 // Make a 64-bit buffer, and use it to build an FILD.
7905 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7906 if (SrcVT == MVT::i32) {
7907 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7908 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7909 getPointerTy(), StackSlot, WordOff);
7910 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7911 StackSlot, MachinePointerInfo(),
7913 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7914 OffsetSlot, MachinePointerInfo(),
7916 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7920 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7921 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7922 StackSlot, MachinePointerInfo(),
7924 // For i64 source, we need to add the appropriate power of 2 if the input
7925 // was negative. This is the same as the optimization in
7926 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7927 // we must be careful to do the computation in x87 extended precision, not
7928 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7929 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7930 MachineMemOperand *MMO =
7931 DAG.getMachineFunction()
7932 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7933 MachineMemOperand::MOLoad, 8, 8);
7935 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7936 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7937 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7940 APInt FF(32, 0x5F800000ULL);
7942 // Check whether the sign bit is set.
7943 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7944 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7947 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7948 SDValue FudgePtr = DAG.getConstantPool(
7949 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7952 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7953 SDValue Zero = DAG.getIntPtrConstant(0);
7954 SDValue Four = DAG.getIntPtrConstant(4);
7955 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7957 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7959 // Load the value out, extending it from f32 to f80.
7960 // FIXME: Avoid the extend by constructing the right constant pool?
7961 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7962 FudgePtr, MachinePointerInfo::getConstantPool(),
7963 MVT::f32, false, false, 4);
7964 // Extend everything to 80 bits to force it to be done on x87.
7965 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7966 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7969 std::pair<SDValue,SDValue> X86TargetLowering::
7970 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7971 DebugLoc DL = Op.getDebugLoc();
7973 EVT DstTy = Op.getValueType();
7975 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7976 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7980 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7981 DstTy.getSimpleVT() >= MVT::i16 &&
7982 "Unknown FP_TO_INT to lower!");
7984 // These are really Legal.
7985 if (DstTy == MVT::i32 &&
7986 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7987 return std::make_pair(SDValue(), SDValue());
7988 if (Subtarget->is64Bit() &&
7989 DstTy == MVT::i64 &&
7990 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7991 return std::make_pair(SDValue(), SDValue());
7993 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7994 // stack slot, or into the FTOL runtime function.
7995 MachineFunction &MF = DAG.getMachineFunction();
7996 unsigned MemSize = DstTy.getSizeInBits()/8;
7997 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7998 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8001 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8002 Opc = X86ISD::WIN_FTOL;
8004 switch (DstTy.getSimpleVT().SimpleTy) {
8005 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8006 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8007 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8008 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8011 SDValue Chain = DAG.getEntryNode();
8012 SDValue Value = Op.getOperand(0);
8013 EVT TheVT = Op.getOperand(0).getValueType();
8014 // FIXME This causes a redundant load/store if the SSE-class value is already
8015 // in memory, such as if it is on the callstack.
8016 if (isScalarFPTypeInSSEReg(TheVT)) {
8017 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8018 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8019 MachinePointerInfo::getFixedStack(SSFI),
8021 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8023 Chain, StackSlot, DAG.getValueType(TheVT)
8026 MachineMemOperand *MMO =
8027 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8028 MachineMemOperand::MOLoad, MemSize, MemSize);
8029 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8031 Chain = Value.getValue(1);
8032 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8033 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8036 MachineMemOperand *MMO =
8037 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8038 MachineMemOperand::MOStore, MemSize, MemSize);
8040 if (Opc != X86ISD::WIN_FTOL) {
8041 // Build the FP_TO_INT*_IN_MEM
8042 SDValue Ops[] = { Chain, Value, StackSlot };
8043 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8044 Ops, 3, DstTy, MMO);
8045 return std::make_pair(FIST, StackSlot);
8047 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8048 DAG.getVTList(MVT::Other, MVT::Glue),
8050 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8051 MVT::i32, ftol.getValue(1));
8052 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8053 MVT::i32, eax.getValue(2));
8054 SDValue Ops[] = { eax, edx };
8055 SDValue pair = IsReplace
8056 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8057 : DAG.getMergeValues(Ops, 2, DL);
8058 return std::make_pair(pair, SDValue());
8062 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8063 SelectionDAG &DAG) const {
8064 if (Op.getValueType().isVector())
8067 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8068 /*IsSigned=*/ true, /*IsReplace=*/ false);
8069 SDValue FIST = Vals.first, StackSlot = Vals.second;
8070 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8071 if (FIST.getNode() == 0) return Op;
8073 if (StackSlot.getNode())
8075 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8076 FIST, StackSlot, MachinePointerInfo(),
8077 false, false, false, 0);
8079 // The node is the result.
8083 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8084 SelectionDAG &DAG) const {
8085 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8086 /*IsSigned=*/ false, /*IsReplace=*/ false);
8087 SDValue FIST = Vals.first, StackSlot = Vals.second;
8088 assert(FIST.getNode() && "Unexpected failure");
8090 if (StackSlot.getNode())
8092 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8093 FIST, StackSlot, MachinePointerInfo(),
8094 false, false, false, 0);
8096 // The node is the result.
8100 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8101 SelectionDAG &DAG) const {
8102 LLVMContext *Context = DAG.getContext();
8103 DebugLoc dl = Op.getDebugLoc();
8104 EVT VT = Op.getValueType();
8107 EltVT = VT.getVectorElementType();
8109 if (EltVT == MVT::f64) {
8110 C = ConstantVector::getSplat(2,
8111 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8113 C = ConstantVector::getSplat(4,
8114 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8116 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8117 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8118 MachinePointerInfo::getConstantPool(),
8119 false, false, false, 16);
8120 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8123 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8124 LLVMContext *Context = DAG.getContext();
8125 DebugLoc dl = Op.getDebugLoc();
8126 EVT VT = Op.getValueType();
8128 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8129 if (VT.isVector()) {
8130 EltVT = VT.getVectorElementType();
8131 NumElts = VT.getVectorNumElements();
8134 if (EltVT == MVT::f64)
8135 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8137 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8138 C = ConstantVector::getSplat(NumElts, C);
8139 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8140 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8141 MachinePointerInfo::getConstantPool(),
8142 false, false, false, 16);
8143 if (VT.isVector()) {
8144 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
8145 return DAG.getNode(ISD::BITCAST, dl, VT,
8146 DAG.getNode(ISD::XOR, dl, XORVT,
8147 DAG.getNode(ISD::BITCAST, dl, XORVT,
8149 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8152 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8155 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8156 LLVMContext *Context = DAG.getContext();
8157 SDValue Op0 = Op.getOperand(0);
8158 SDValue Op1 = Op.getOperand(1);
8159 DebugLoc dl = Op.getDebugLoc();
8160 EVT VT = Op.getValueType();
8161 EVT SrcVT = Op1.getValueType();
8163 // If second operand is smaller, extend it first.
8164 if (SrcVT.bitsLT(VT)) {
8165 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8168 // And if it is bigger, shrink it first.
8169 if (SrcVT.bitsGT(VT)) {
8170 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8174 // At this point the operands and the result should have the same
8175 // type, and that won't be f80 since that is not custom lowered.
8177 // First get the sign bit of second operand.
8178 SmallVector<Constant*,4> CV;
8179 if (SrcVT == MVT::f64) {
8180 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8181 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8183 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8184 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8185 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8186 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8188 Constant *C = ConstantVector::get(CV);
8189 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8190 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8191 MachinePointerInfo::getConstantPool(),
8192 false, false, false, 16);
8193 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8195 // Shift sign bit right or left if the two operands have different types.
8196 if (SrcVT.bitsGT(VT)) {
8197 // Op0 is MVT::f32, Op1 is MVT::f64.
8198 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8199 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8200 DAG.getConstant(32, MVT::i32));
8201 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8202 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8203 DAG.getIntPtrConstant(0));
8206 // Clear first operand sign bit.
8208 if (VT == MVT::f64) {
8209 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8210 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8212 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8213 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8214 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8215 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8217 C = ConstantVector::get(CV);
8218 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8219 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8220 MachinePointerInfo::getConstantPool(),
8221 false, false, false, 16);
8222 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8224 // Or the value with the sign bit.
8225 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8228 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8229 SDValue N0 = Op.getOperand(0);
8230 DebugLoc dl = Op.getDebugLoc();
8231 EVT VT = Op.getValueType();
8233 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8234 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8235 DAG.getConstant(1, VT));
8236 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8239 /// Emit nodes that will be selected as "test Op0,Op0", or something
8241 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8242 SelectionDAG &DAG) const {
8243 DebugLoc dl = Op.getDebugLoc();
8245 // CF and OF aren't always set the way we want. Determine which
8246 // of these we need.
8247 bool NeedCF = false;
8248 bool NeedOF = false;
8251 case X86::COND_A: case X86::COND_AE:
8252 case X86::COND_B: case X86::COND_BE:
8255 case X86::COND_G: case X86::COND_GE:
8256 case X86::COND_L: case X86::COND_LE:
8257 case X86::COND_O: case X86::COND_NO:
8262 // See if we can use the EFLAGS value from the operand instead of
8263 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8264 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8265 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8266 // Emit a CMP with 0, which is the TEST pattern.
8267 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8268 DAG.getConstant(0, Op.getValueType()));
8270 unsigned Opcode = 0;
8271 unsigned NumOperands = 0;
8272 switch (Op.getNode()->getOpcode()) {
8274 // Due to an isel shortcoming, be conservative if this add is likely to be
8275 // selected as part of a load-modify-store instruction. When the root node
8276 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8277 // uses of other nodes in the match, such as the ADD in this case. This
8278 // leads to the ADD being left around and reselected, with the result being
8279 // two adds in the output. Alas, even if none our users are stores, that
8280 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8281 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8282 // climbing the DAG back to the root, and it doesn't seem to be worth the
8284 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8285 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8286 if (UI->getOpcode() != ISD::CopyToReg &&
8287 UI->getOpcode() != ISD::SETCC &&
8288 UI->getOpcode() != ISD::STORE)
8291 if (ConstantSDNode *C =
8292 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8293 // An add of one will be selected as an INC.
8294 if (C->getAPIntValue() == 1) {
8295 Opcode = X86ISD::INC;
8300 // An add of negative one (subtract of one) will be selected as a DEC.
8301 if (C->getAPIntValue().isAllOnesValue()) {
8302 Opcode = X86ISD::DEC;
8308 // Otherwise use a regular EFLAGS-setting add.
8309 Opcode = X86ISD::ADD;
8313 // If the primary and result isn't used, don't bother using X86ISD::AND,
8314 // because a TEST instruction will be better.
8315 bool NonFlagUse = false;
8316 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8317 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8319 unsigned UOpNo = UI.getOperandNo();
8320 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8321 // Look pass truncate.
8322 UOpNo = User->use_begin().getOperandNo();
8323 User = *User->use_begin();
8326 if (User->getOpcode() != ISD::BRCOND &&
8327 User->getOpcode() != ISD::SETCC &&
8328 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8341 // Due to the ISEL shortcoming noted above, be conservative if this op is
8342 // likely to be selected as part of a load-modify-store instruction.
8343 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8344 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8345 if (UI->getOpcode() == ISD::STORE)
8348 // Otherwise use a regular EFLAGS-setting instruction.
8349 switch (Op.getNode()->getOpcode()) {
8350 default: llvm_unreachable("unexpected operator!");
8352 // If the only use of SUB is EFLAGS, use CMP instead.
8354 Opcode = X86ISD::CMP;
8356 Opcode = X86ISD::SUB;
8358 case ISD::OR: Opcode = X86ISD::OR; break;
8359 case ISD::XOR: Opcode = X86ISD::XOR; break;
8360 case ISD::AND: Opcode = X86ISD::AND; break;
8372 return SDValue(Op.getNode(), 1);
8379 // Emit a CMP with 0, which is the TEST pattern.
8380 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8381 DAG.getConstant(0, Op.getValueType()));
8383 if (Opcode == X86ISD::CMP) {
8384 SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0),
8386 // We can't replace usage of SUB with CMP.
8387 // The SUB node will be removed later because there is no use of it.
8388 return SDValue(New.getNode(), 0);
8391 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8392 SmallVector<SDValue, 4> Ops;
8393 for (unsigned i = 0; i != NumOperands; ++i)
8394 Ops.push_back(Op.getOperand(i));
8396 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8397 DAG.ReplaceAllUsesWith(Op, New);
8398 return SDValue(New.getNode(), 1);
8401 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8403 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8404 SelectionDAG &DAG) const {
8405 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8406 if (C->getAPIntValue() == 0)
8407 return EmitTest(Op0, X86CC, DAG);
8409 DebugLoc dl = Op0.getDebugLoc();
8410 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8413 /// Convert a comparison if required by the subtarget.
8414 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8415 SelectionDAG &DAG) const {
8416 // If the subtarget does not support the FUCOMI instruction, floating-point
8417 // comparisons have to be converted.
8418 if (Subtarget->hasCMov() ||
8419 Cmp.getOpcode() != X86ISD::CMP ||
8420 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8421 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8424 // The instruction selector will select an FUCOM instruction instead of
8425 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8426 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8427 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8428 DebugLoc dl = Cmp.getDebugLoc();
8429 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8430 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8431 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8432 DAG.getConstant(8, MVT::i8));
8433 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8434 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8437 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8438 /// if it's possible.
8439 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8440 DebugLoc dl, SelectionDAG &DAG) const {
8441 SDValue Op0 = And.getOperand(0);
8442 SDValue Op1 = And.getOperand(1);
8443 if (Op0.getOpcode() == ISD::TRUNCATE)
8444 Op0 = Op0.getOperand(0);
8445 if (Op1.getOpcode() == ISD::TRUNCATE)
8446 Op1 = Op1.getOperand(0);
8449 if (Op1.getOpcode() == ISD::SHL)
8450 std::swap(Op0, Op1);
8451 if (Op0.getOpcode() == ISD::SHL) {
8452 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8453 if (And00C->getZExtValue() == 1) {
8454 // If we looked past a truncate, check that it's only truncating away
8456 unsigned BitWidth = Op0.getValueSizeInBits();
8457 unsigned AndBitWidth = And.getValueSizeInBits();
8458 if (BitWidth > AndBitWidth) {
8460 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8461 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8465 RHS = Op0.getOperand(1);
8467 } else if (Op1.getOpcode() == ISD::Constant) {
8468 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8469 uint64_t AndRHSVal = AndRHS->getZExtValue();
8470 SDValue AndLHS = Op0;
8472 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8473 LHS = AndLHS.getOperand(0);
8474 RHS = AndLHS.getOperand(1);
8477 // Use BT if the immediate can't be encoded in a TEST instruction.
8478 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8480 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8484 if (LHS.getNode()) {
8485 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8486 // instruction. Since the shift amount is in-range-or-undefined, we know
8487 // that doing a bittest on the i32 value is ok. We extend to i32 because
8488 // the encoding for the i16 version is larger than the i32 version.
8489 // Also promote i16 to i32 for performance / code size reason.
8490 if (LHS.getValueType() == MVT::i8 ||
8491 LHS.getValueType() == MVT::i16)
8492 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8494 // If the operand types disagree, extend the shift amount to match. Since
8495 // BT ignores high bits (like shifts) we can use anyextend.
8496 if (LHS.getValueType() != RHS.getValueType())
8497 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8499 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8500 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8501 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8502 DAG.getConstant(Cond, MVT::i8), BT);
8508 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8510 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8512 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8513 SDValue Op0 = Op.getOperand(0);
8514 SDValue Op1 = Op.getOperand(1);
8515 DebugLoc dl = Op.getDebugLoc();
8516 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8518 // Optimize to BT if possible.
8519 // Lower (X & (1 << N)) == 0 to BT(X, N).
8520 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8521 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8522 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8523 Op1.getOpcode() == ISD::Constant &&
8524 cast<ConstantSDNode>(Op1)->isNullValue() &&
8525 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8526 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8527 if (NewSetCC.getNode())
8531 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8533 if (Op1.getOpcode() == ISD::Constant &&
8534 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8535 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8536 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8538 // If the input is a setcc, then reuse the input setcc or use a new one with
8539 // the inverted condition.
8540 if (Op0.getOpcode() == X86ISD::SETCC) {
8541 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8542 bool Invert = (CC == ISD::SETNE) ^
8543 cast<ConstantSDNode>(Op1)->isNullValue();
8544 if (!Invert) return Op0;
8546 CCode = X86::GetOppositeBranchCondition(CCode);
8547 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8548 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8552 bool isFP = Op1.getValueType().isFloatingPoint();
8553 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8554 if (X86CC == X86::COND_INVALID)
8557 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8558 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8559 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8560 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8563 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8564 // ones, and then concatenate the result back.
8565 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8566 EVT VT = Op.getValueType();
8568 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8569 "Unsupported value type for operation");
8571 unsigned NumElems = VT.getVectorNumElements();
8572 DebugLoc dl = Op.getDebugLoc();
8573 SDValue CC = Op.getOperand(2);
8575 // Extract the LHS vectors
8576 SDValue LHS = Op.getOperand(0);
8577 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8578 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8580 // Extract the RHS vectors
8581 SDValue RHS = Op.getOperand(1);
8582 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8583 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8585 // Issue the operation on the smaller types and concatenate the result back
8586 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8587 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8588 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8589 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8590 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8594 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8596 SDValue Op0 = Op.getOperand(0);
8597 SDValue Op1 = Op.getOperand(1);
8598 SDValue CC = Op.getOperand(2);
8599 EVT VT = Op.getValueType();
8600 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8601 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8602 DebugLoc dl = Op.getDebugLoc();
8606 EVT EltVT = Op0.getValueType().getVectorElementType();
8607 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8611 // SSE Condition code mapping:
8620 switch (SetCCOpcode) {
8623 case ISD::SETEQ: SSECC = 0; break;
8625 case ISD::SETGT: Swap = true; // Fallthrough
8627 case ISD::SETOLT: SSECC = 1; break;
8629 case ISD::SETGE: Swap = true; // Fallthrough
8631 case ISD::SETOLE: SSECC = 2; break;
8632 case ISD::SETUO: SSECC = 3; break;
8634 case ISD::SETNE: SSECC = 4; break;
8635 case ISD::SETULE: Swap = true;
8636 case ISD::SETUGE: SSECC = 5; break;
8637 case ISD::SETULT: Swap = true;
8638 case ISD::SETUGT: SSECC = 6; break;
8639 case ISD::SETO: SSECC = 7; break;
8642 std::swap(Op0, Op1);
8644 // In the two special cases we can't handle, emit two comparisons.
8646 if (SetCCOpcode == ISD::SETUEQ) {
8648 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8649 DAG.getConstant(3, MVT::i8));
8650 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8651 DAG.getConstant(0, MVT::i8));
8652 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8654 if (SetCCOpcode == ISD::SETONE) {
8656 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8657 DAG.getConstant(7, MVT::i8));
8658 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8659 DAG.getConstant(4, MVT::i8));
8660 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8662 llvm_unreachable("Illegal FP comparison");
8664 // Handle all other FP comparisons here.
8665 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8666 DAG.getConstant(SSECC, MVT::i8));
8669 // Break 256-bit integer vector compare into smaller ones.
8670 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8671 return Lower256IntVSETCC(Op, DAG);
8673 // We are handling one of the integer comparisons here. Since SSE only has
8674 // GT and EQ comparisons for integer, swapping operands and multiple
8675 // operations may be required for some comparisons.
8677 bool Swap = false, Invert = false, FlipSigns = false;
8679 switch (SetCCOpcode) {
8681 case ISD::SETNE: Invert = true;
8682 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8683 case ISD::SETLT: Swap = true;
8684 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8685 case ISD::SETGE: Swap = true;
8686 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8687 case ISD::SETULT: Swap = true;
8688 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8689 case ISD::SETUGE: Swap = true;
8690 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8693 std::swap(Op0, Op1);
8695 // Check that the operation in question is available (most are plain SSE2,
8696 // but PCMPGTQ and PCMPEQQ have different requirements).
8697 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8699 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8702 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8703 // bits of the inputs before performing those operations.
8705 EVT EltVT = VT.getVectorElementType();
8706 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8708 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8709 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8711 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8712 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8715 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8717 // If the logical-not of the result is required, perform that now.
8719 Result = DAG.getNOT(dl, Result, VT);
8724 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8725 static bool isX86LogicalCmp(SDValue Op) {
8726 unsigned Opc = Op.getNode()->getOpcode();
8727 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8728 Opc == X86ISD::SAHF)
8730 if (Op.getResNo() == 1 &&
8731 (Opc == X86ISD::ADD ||
8732 Opc == X86ISD::SUB ||
8733 Opc == X86ISD::ADC ||
8734 Opc == X86ISD::SBB ||
8735 Opc == X86ISD::SMUL ||
8736 Opc == X86ISD::UMUL ||
8737 Opc == X86ISD::INC ||
8738 Opc == X86ISD::DEC ||
8739 Opc == X86ISD::OR ||
8740 Opc == X86ISD::XOR ||
8741 Opc == X86ISD::AND))
8744 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8750 static bool isZero(SDValue V) {
8751 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8752 return C && C->isNullValue();
8755 static bool isAllOnes(SDValue V) {
8756 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8757 return C && C->isAllOnesValue();
8760 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8761 bool addTest = true;
8762 SDValue Cond = Op.getOperand(0);
8763 SDValue Op1 = Op.getOperand(1);
8764 SDValue Op2 = Op.getOperand(2);
8765 DebugLoc DL = Op.getDebugLoc();
8768 if (Cond.getOpcode() == ISD::SETCC) {
8769 SDValue NewCond = LowerSETCC(Cond, DAG);
8770 if (NewCond.getNode())
8774 // Handle the following cases related to max and min:
8775 // (a > b) ? (a-b) : 0
8776 // (a >= b) ? (a-b) : 0
8777 // (b < a) ? (a-b) : 0
8778 // (b <= a) ? (a-b) : 0
8779 // Comparison is removed to use EFLAGS from SUB.
8780 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2))
8781 if (Cond.getOpcode() == X86ISD::SETCC &&
8782 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8783 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) &&
8784 C->getAPIntValue() == 0) {
8785 SDValue Cmp = Cond.getOperand(1);
8786 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8787 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) &&
8788 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) &&
8789 (CC == X86::COND_G || CC == X86::COND_GE ||
8790 CC == X86::COND_A || CC == X86::COND_AE)) ||
8791 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) &&
8792 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) &&
8793 (CC == X86::COND_L || CC == X86::COND_LE ||
8794 CC == X86::COND_B || CC == X86::COND_BE))) {
8796 if (Op1.getOpcode() == ISD::SUB) {
8797 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32);
8798 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs,
8799 Op1.getOperand(0), Op1.getOperand(1));
8800 DAG.ReplaceAllUsesWith(Op1, New);
8804 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8805 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE ||
8806 CC == X86::COND_L ||
8807 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE;
8808 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8),
8809 SDValue(Op1.getNode(), 1) };
8810 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8814 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8815 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8816 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8817 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8818 if (Cond.getOpcode() == X86ISD::SETCC &&
8819 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8820 isZero(Cond.getOperand(1).getOperand(1))) {
8821 SDValue Cmp = Cond.getOperand(1);
8823 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8825 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8826 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8827 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8829 SDValue CmpOp0 = Cmp.getOperand(0);
8830 // Apply further optimizations for special cases
8831 // (select (x != 0), -1, 0) -> neg & sbb
8832 // (select (x == 0), 0, -1) -> neg & sbb
8833 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8834 if (YC->isNullValue() &&
8835 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8836 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8837 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8838 DAG.getConstant(0, CmpOp0.getValueType()),
8840 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8841 DAG.getConstant(X86::COND_B, MVT::i8),
8842 SDValue(Neg.getNode(), 1));
8846 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8847 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8848 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8850 SDValue Res = // Res = 0 or -1.
8851 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8852 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8854 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8855 Res = DAG.getNOT(DL, Res, Res.getValueType());
8857 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8858 if (N2C == 0 || !N2C->isNullValue())
8859 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8864 // Look past (and (setcc_carry (cmp ...)), 1).
8865 if (Cond.getOpcode() == ISD::AND &&
8866 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8867 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8868 if (C && C->getAPIntValue() == 1)
8869 Cond = Cond.getOperand(0);
8872 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8873 // setting operand in place of the X86ISD::SETCC.
8874 unsigned CondOpcode = Cond.getOpcode();
8875 if (CondOpcode == X86ISD::SETCC ||
8876 CondOpcode == X86ISD::SETCC_CARRY) {
8877 CC = Cond.getOperand(0);
8879 SDValue Cmp = Cond.getOperand(1);
8880 unsigned Opc = Cmp.getOpcode();
8881 EVT VT = Op.getValueType();
8883 bool IllegalFPCMov = false;
8884 if (VT.isFloatingPoint() && !VT.isVector() &&
8885 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8886 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8888 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8889 Opc == X86ISD::BT) { // FIXME
8893 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8894 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8895 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8896 Cond.getOperand(0).getValueType() != MVT::i8)) {
8897 SDValue LHS = Cond.getOperand(0);
8898 SDValue RHS = Cond.getOperand(1);
8902 switch (CondOpcode) {
8903 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8904 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8905 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8906 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8907 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8908 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8909 default: llvm_unreachable("unexpected overflowing operator");
8911 if (CondOpcode == ISD::UMULO)
8912 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8915 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8917 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8919 if (CondOpcode == ISD::UMULO)
8920 Cond = X86Op.getValue(2);
8922 Cond = X86Op.getValue(1);
8924 CC = DAG.getConstant(X86Cond, MVT::i8);
8929 // Look pass the truncate.
8930 if (Cond.getOpcode() == ISD::TRUNCATE)
8931 Cond = Cond.getOperand(0);
8933 // We know the result of AND is compared against zero. Try to match
8935 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8936 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8937 if (NewSetCC.getNode()) {
8938 CC = NewSetCC.getOperand(0);
8939 Cond = NewSetCC.getOperand(1);
8946 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8947 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8950 // a < b ? -1 : 0 -> RES = ~setcc_carry
8951 // a < b ? 0 : -1 -> RES = setcc_carry
8952 // a >= b ? -1 : 0 -> RES = setcc_carry
8953 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8954 if (Cond.getOpcode() == X86ISD::CMP) {
8955 Cond = ConvertCmpIfNecessary(Cond, DAG);
8956 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8958 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8959 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8960 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8961 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8962 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8963 return DAG.getNOT(DL, Res, Res.getValueType());
8968 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8969 // condition is true.
8970 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8971 SDValue Ops[] = { Op2, Op1, CC, Cond };
8972 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8975 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8976 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8977 // from the AND / OR.
8978 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8979 Opc = Op.getOpcode();
8980 if (Opc != ISD::OR && Opc != ISD::AND)
8982 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8983 Op.getOperand(0).hasOneUse() &&
8984 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8985 Op.getOperand(1).hasOneUse());
8988 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8989 // 1 and that the SETCC node has a single use.
8990 static bool isXor1OfSetCC(SDValue Op) {
8991 if (Op.getOpcode() != ISD::XOR)
8993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8994 if (N1C && N1C->getAPIntValue() == 1) {
8995 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8996 Op.getOperand(0).hasOneUse();
9001 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9002 bool addTest = true;
9003 SDValue Chain = Op.getOperand(0);
9004 SDValue Cond = Op.getOperand(1);
9005 SDValue Dest = Op.getOperand(2);
9006 DebugLoc dl = Op.getDebugLoc();
9008 bool Inverted = false;
9010 if (Cond.getOpcode() == ISD::SETCC) {
9011 // Check for setcc([su]{add,sub,mul}o == 0).
9012 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9013 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9014 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9015 Cond.getOperand(0).getResNo() == 1 &&
9016 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9017 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9018 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9019 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9020 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9021 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9023 Cond = Cond.getOperand(0);
9025 SDValue NewCond = LowerSETCC(Cond, DAG);
9026 if (NewCond.getNode())
9031 // FIXME: LowerXALUO doesn't handle these!!
9032 else if (Cond.getOpcode() == X86ISD::ADD ||
9033 Cond.getOpcode() == X86ISD::SUB ||
9034 Cond.getOpcode() == X86ISD::SMUL ||
9035 Cond.getOpcode() == X86ISD::UMUL)
9036 Cond = LowerXALUO(Cond, DAG);
9039 // Look pass (and (setcc_carry (cmp ...)), 1).
9040 if (Cond.getOpcode() == ISD::AND &&
9041 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9042 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9043 if (C && C->getAPIntValue() == 1)
9044 Cond = Cond.getOperand(0);
9047 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9048 // setting operand in place of the X86ISD::SETCC.
9049 unsigned CondOpcode = Cond.getOpcode();
9050 if (CondOpcode == X86ISD::SETCC ||
9051 CondOpcode == X86ISD::SETCC_CARRY) {
9052 CC = Cond.getOperand(0);
9054 SDValue Cmp = Cond.getOperand(1);
9055 unsigned Opc = Cmp.getOpcode();
9056 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9057 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9061 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9065 // These can only come from an arithmetic instruction with overflow,
9066 // e.g. SADDO, UADDO.
9067 Cond = Cond.getNode()->getOperand(1);
9073 CondOpcode = Cond.getOpcode();
9074 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9075 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9076 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9077 Cond.getOperand(0).getValueType() != MVT::i8)) {
9078 SDValue LHS = Cond.getOperand(0);
9079 SDValue RHS = Cond.getOperand(1);
9083 switch (CondOpcode) {
9084 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9085 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9086 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9087 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9088 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9089 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9090 default: llvm_unreachable("unexpected overflowing operator");
9093 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9094 if (CondOpcode == ISD::UMULO)
9095 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9098 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9100 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9102 if (CondOpcode == ISD::UMULO)
9103 Cond = X86Op.getValue(2);
9105 Cond = X86Op.getValue(1);
9107 CC = DAG.getConstant(X86Cond, MVT::i8);
9111 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9112 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9113 if (CondOpc == ISD::OR) {
9114 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9115 // two branches instead of an explicit OR instruction with a
9117 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9118 isX86LogicalCmp(Cmp)) {
9119 CC = Cond.getOperand(0).getOperand(0);
9120 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9121 Chain, Dest, CC, Cmp);
9122 CC = Cond.getOperand(1).getOperand(0);
9126 } else { // ISD::AND
9127 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9128 // two branches instead of an explicit AND instruction with a
9129 // separate test. However, we only do this if this block doesn't
9130 // have a fall-through edge, because this requires an explicit
9131 // jmp when the condition is false.
9132 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9133 isX86LogicalCmp(Cmp) &&
9134 Op.getNode()->hasOneUse()) {
9135 X86::CondCode CCode =
9136 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9137 CCode = X86::GetOppositeBranchCondition(CCode);
9138 CC = DAG.getConstant(CCode, MVT::i8);
9139 SDNode *User = *Op.getNode()->use_begin();
9140 // Look for an unconditional branch following this conditional branch.
9141 // We need this because we need to reverse the successors in order
9142 // to implement FCMP_OEQ.
9143 if (User->getOpcode() == ISD::BR) {
9144 SDValue FalseBB = User->getOperand(1);
9146 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9147 assert(NewBR == User);
9151 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9152 Chain, Dest, CC, Cmp);
9153 X86::CondCode CCode =
9154 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9155 CCode = X86::GetOppositeBranchCondition(CCode);
9156 CC = DAG.getConstant(CCode, MVT::i8);
9162 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9163 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9164 // It should be transformed during dag combiner except when the condition
9165 // is set by a arithmetics with overflow node.
9166 X86::CondCode CCode =
9167 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9168 CCode = X86::GetOppositeBranchCondition(CCode);
9169 CC = DAG.getConstant(CCode, MVT::i8);
9170 Cond = Cond.getOperand(0).getOperand(1);
9172 } else if (Cond.getOpcode() == ISD::SETCC &&
9173 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9174 // For FCMP_OEQ, we can emit
9175 // two branches instead of an explicit AND instruction with a
9176 // separate test. However, we only do this if this block doesn't
9177 // have a fall-through edge, because this requires an explicit
9178 // jmp when the condition is false.
9179 if (Op.getNode()->hasOneUse()) {
9180 SDNode *User = *Op.getNode()->use_begin();
9181 // Look for an unconditional branch following this conditional branch.
9182 // We need this because we need to reverse the successors in order
9183 // to implement FCMP_OEQ.
9184 if (User->getOpcode() == ISD::BR) {
9185 SDValue FalseBB = User->getOperand(1);
9187 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9188 assert(NewBR == User);
9192 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9193 Cond.getOperand(0), Cond.getOperand(1));
9194 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9195 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9196 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9197 Chain, Dest, CC, Cmp);
9198 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9203 } else if (Cond.getOpcode() == ISD::SETCC &&
9204 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9205 // For FCMP_UNE, we can emit
9206 // two branches instead of an explicit AND instruction with a
9207 // separate test. However, we only do this if this block doesn't
9208 // have a fall-through edge, because this requires an explicit
9209 // jmp when the condition is false.
9210 if (Op.getNode()->hasOneUse()) {
9211 SDNode *User = *Op.getNode()->use_begin();
9212 // Look for an unconditional branch following this conditional branch.
9213 // We need this because we need to reverse the successors in order
9214 // to implement FCMP_UNE.
9215 if (User->getOpcode() == ISD::BR) {
9216 SDValue FalseBB = User->getOperand(1);
9218 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9219 assert(NewBR == User);
9222 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9223 Cond.getOperand(0), Cond.getOperand(1));
9224 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9225 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9226 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9227 Chain, Dest, CC, Cmp);
9228 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9238 // Look pass the truncate.
9239 if (Cond.getOpcode() == ISD::TRUNCATE)
9240 Cond = Cond.getOperand(0);
9242 // We know the result of AND is compared against zero. Try to match
9244 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9245 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9246 if (NewSetCC.getNode()) {
9247 CC = NewSetCC.getOperand(0);
9248 Cond = NewSetCC.getOperand(1);
9255 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9256 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9258 Cond = ConvertCmpIfNecessary(Cond, DAG);
9259 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9260 Chain, Dest, CC, Cond);
9264 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9265 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9266 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9267 // that the guard pages used by the OS virtual memory manager are allocated in
9268 // correct sequence.
9270 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9271 SelectionDAG &DAG) const {
9272 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9273 getTargetMachine().Options.EnableSegmentedStacks) &&
9274 "This should be used only on Windows targets or when segmented stacks "
9276 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9277 DebugLoc dl = Op.getDebugLoc();
9280 SDValue Chain = Op.getOperand(0);
9281 SDValue Size = Op.getOperand(1);
9282 // FIXME: Ensure alignment here
9284 bool Is64Bit = Subtarget->is64Bit();
9285 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9287 if (getTargetMachine().Options.EnableSegmentedStacks) {
9288 MachineFunction &MF = DAG.getMachineFunction();
9289 MachineRegisterInfo &MRI = MF.getRegInfo();
9292 // The 64 bit implementation of segmented stacks needs to clobber both r10
9293 // r11. This makes it impossible to use it along with nested parameters.
9294 const Function *F = MF.getFunction();
9296 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9298 if (I->hasNestAttr())
9299 report_fatal_error("Cannot use segmented stacks with functions that "
9300 "have nested arguments.");
9303 const TargetRegisterClass *AddrRegClass =
9304 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9305 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9306 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9307 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9308 DAG.getRegister(Vreg, SPTy));
9309 SDValue Ops1[2] = { Value, Chain };
9310 return DAG.getMergeValues(Ops1, 2, dl);
9313 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9315 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9316 Flag = Chain.getValue(1);
9317 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9319 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9320 Flag = Chain.getValue(1);
9322 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9324 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9325 return DAG.getMergeValues(Ops1, 2, dl);
9329 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9330 MachineFunction &MF = DAG.getMachineFunction();
9331 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9333 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9334 DebugLoc DL = Op.getDebugLoc();
9336 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9337 // vastart just stores the address of the VarArgsFrameIndex slot into the
9338 // memory location argument.
9339 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9341 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9342 MachinePointerInfo(SV), false, false, 0);
9346 // gp_offset (0 - 6 * 8)
9347 // fp_offset (48 - 48 + 8 * 16)
9348 // overflow_arg_area (point to parameters coming in memory).
9350 SmallVector<SDValue, 8> MemOps;
9351 SDValue FIN = Op.getOperand(1);
9353 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9354 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9356 FIN, MachinePointerInfo(SV), false, false, 0);
9357 MemOps.push_back(Store);
9360 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9361 FIN, DAG.getIntPtrConstant(4));
9362 Store = DAG.getStore(Op.getOperand(0), DL,
9363 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9365 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9366 MemOps.push_back(Store);
9368 // Store ptr to overflow_arg_area
9369 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9370 FIN, DAG.getIntPtrConstant(4));
9371 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9373 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9374 MachinePointerInfo(SV, 8),
9376 MemOps.push_back(Store);
9378 // Store ptr to reg_save_area.
9379 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9380 FIN, DAG.getIntPtrConstant(8));
9381 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9383 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9384 MachinePointerInfo(SV, 16), false, false, 0);
9385 MemOps.push_back(Store);
9386 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9387 &MemOps[0], MemOps.size());
9390 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9391 assert(Subtarget->is64Bit() &&
9392 "LowerVAARG only handles 64-bit va_arg!");
9393 assert((Subtarget->isTargetLinux() ||
9394 Subtarget->isTargetDarwin()) &&
9395 "Unhandled target in LowerVAARG");
9396 assert(Op.getNode()->getNumOperands() == 4);
9397 SDValue Chain = Op.getOperand(0);
9398 SDValue SrcPtr = Op.getOperand(1);
9399 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9400 unsigned Align = Op.getConstantOperandVal(3);
9401 DebugLoc dl = Op.getDebugLoc();
9403 EVT ArgVT = Op.getNode()->getValueType(0);
9404 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9405 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9408 // Decide which area this value should be read from.
9409 // TODO: Implement the AMD64 ABI in its entirety. This simple
9410 // selection mechanism works only for the basic types.
9411 if (ArgVT == MVT::f80) {
9412 llvm_unreachable("va_arg for f80 not yet implemented");
9413 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9414 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9415 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9416 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9418 llvm_unreachable("Unhandled argument type in LowerVAARG");
9422 // Sanity Check: Make sure using fp_offset makes sense.
9423 assert(!getTargetMachine().Options.UseSoftFloat &&
9424 !(DAG.getMachineFunction()
9425 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9426 Subtarget->hasSSE1());
9429 // Insert VAARG_64 node into the DAG
9430 // VAARG_64 returns two values: Variable Argument Address, Chain
9431 SmallVector<SDValue, 11> InstOps;
9432 InstOps.push_back(Chain);
9433 InstOps.push_back(SrcPtr);
9434 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9435 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9436 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9437 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9438 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9439 VTs, &InstOps[0], InstOps.size(),
9441 MachinePointerInfo(SV),
9446 Chain = VAARG.getValue(1);
9448 // Load the next argument and return it
9449 return DAG.getLoad(ArgVT, dl,
9452 MachinePointerInfo(),
9453 false, false, false, 0);
9456 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9457 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9458 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9459 SDValue Chain = Op.getOperand(0);
9460 SDValue DstPtr = Op.getOperand(1);
9461 SDValue SrcPtr = Op.getOperand(2);
9462 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9463 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9464 DebugLoc DL = Op.getDebugLoc();
9466 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9467 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9469 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9472 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9473 // may or may not be a constant. Takes immediate version of shift as input.
9474 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9475 SDValue SrcOp, SDValue ShAmt,
9476 SelectionDAG &DAG) {
9477 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9479 if (isa<ConstantSDNode>(ShAmt)) {
9480 // Constant may be a TargetConstant. Use a regular constant.
9481 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
9483 default: llvm_unreachable("Unknown target vector shift node");
9487 return DAG.getNode(Opc, dl, VT, SrcOp,
9488 DAG.getConstant(ShiftAmt, MVT::i32));
9492 // Change opcode to non-immediate version
9494 default: llvm_unreachable("Unknown target vector shift node");
9495 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9496 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9497 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9500 // Need to build a vector containing shift amount
9501 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9504 ShOps[1] = DAG.getConstant(0, MVT::i32);
9505 ShOps[2] = DAG.getUNDEF(MVT::i32);
9506 ShOps[3] = DAG.getUNDEF(MVT::i32);
9507 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9509 // The return type has to be a 128-bit type with the same element
9510 // type as the input type.
9511 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9512 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
9514 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
9515 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9519 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9520 DebugLoc dl = Op.getDebugLoc();
9521 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9523 default: return SDValue(); // Don't custom lower most intrinsics.
9524 // Comparison intrinsics.
9525 case Intrinsic::x86_sse_comieq_ss:
9526 case Intrinsic::x86_sse_comilt_ss:
9527 case Intrinsic::x86_sse_comile_ss:
9528 case Intrinsic::x86_sse_comigt_ss:
9529 case Intrinsic::x86_sse_comige_ss:
9530 case Intrinsic::x86_sse_comineq_ss:
9531 case Intrinsic::x86_sse_ucomieq_ss:
9532 case Intrinsic::x86_sse_ucomilt_ss:
9533 case Intrinsic::x86_sse_ucomile_ss:
9534 case Intrinsic::x86_sse_ucomigt_ss:
9535 case Intrinsic::x86_sse_ucomige_ss:
9536 case Intrinsic::x86_sse_ucomineq_ss:
9537 case Intrinsic::x86_sse2_comieq_sd:
9538 case Intrinsic::x86_sse2_comilt_sd:
9539 case Intrinsic::x86_sse2_comile_sd:
9540 case Intrinsic::x86_sse2_comigt_sd:
9541 case Intrinsic::x86_sse2_comige_sd:
9542 case Intrinsic::x86_sse2_comineq_sd:
9543 case Intrinsic::x86_sse2_ucomieq_sd:
9544 case Intrinsic::x86_sse2_ucomilt_sd:
9545 case Intrinsic::x86_sse2_ucomile_sd:
9546 case Intrinsic::x86_sse2_ucomigt_sd:
9547 case Intrinsic::x86_sse2_ucomige_sd:
9548 case Intrinsic::x86_sse2_ucomineq_sd: {
9550 ISD::CondCode CC = ISD::SETCC_INVALID;
9552 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9553 case Intrinsic::x86_sse_comieq_ss:
9554 case Intrinsic::x86_sse2_comieq_sd:
9558 case Intrinsic::x86_sse_comilt_ss:
9559 case Intrinsic::x86_sse2_comilt_sd:
9563 case Intrinsic::x86_sse_comile_ss:
9564 case Intrinsic::x86_sse2_comile_sd:
9568 case Intrinsic::x86_sse_comigt_ss:
9569 case Intrinsic::x86_sse2_comigt_sd:
9573 case Intrinsic::x86_sse_comige_ss:
9574 case Intrinsic::x86_sse2_comige_sd:
9578 case Intrinsic::x86_sse_comineq_ss:
9579 case Intrinsic::x86_sse2_comineq_sd:
9583 case Intrinsic::x86_sse_ucomieq_ss:
9584 case Intrinsic::x86_sse2_ucomieq_sd:
9585 Opc = X86ISD::UCOMI;
9588 case Intrinsic::x86_sse_ucomilt_ss:
9589 case Intrinsic::x86_sse2_ucomilt_sd:
9590 Opc = X86ISD::UCOMI;
9593 case Intrinsic::x86_sse_ucomile_ss:
9594 case Intrinsic::x86_sse2_ucomile_sd:
9595 Opc = X86ISD::UCOMI;
9598 case Intrinsic::x86_sse_ucomigt_ss:
9599 case Intrinsic::x86_sse2_ucomigt_sd:
9600 Opc = X86ISD::UCOMI;
9603 case Intrinsic::x86_sse_ucomige_ss:
9604 case Intrinsic::x86_sse2_ucomige_sd:
9605 Opc = X86ISD::UCOMI;
9608 case Intrinsic::x86_sse_ucomineq_ss:
9609 case Intrinsic::x86_sse2_ucomineq_sd:
9610 Opc = X86ISD::UCOMI;
9615 SDValue LHS = Op.getOperand(1);
9616 SDValue RHS = Op.getOperand(2);
9617 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9618 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9619 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9620 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9621 DAG.getConstant(X86CC, MVT::i8), Cond);
9622 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9624 // Arithmetic intrinsics.
9625 case Intrinsic::x86_sse2_pmulu_dq:
9626 case Intrinsic::x86_avx2_pmulu_dq:
9627 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9628 Op.getOperand(1), Op.getOperand(2));
9629 case Intrinsic::x86_sse3_hadd_ps:
9630 case Intrinsic::x86_sse3_hadd_pd:
9631 case Intrinsic::x86_avx_hadd_ps_256:
9632 case Intrinsic::x86_avx_hadd_pd_256:
9633 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9634 Op.getOperand(1), Op.getOperand(2));
9635 case Intrinsic::x86_sse3_hsub_ps:
9636 case Intrinsic::x86_sse3_hsub_pd:
9637 case Intrinsic::x86_avx_hsub_ps_256:
9638 case Intrinsic::x86_avx_hsub_pd_256:
9639 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9640 Op.getOperand(1), Op.getOperand(2));
9641 case Intrinsic::x86_ssse3_phadd_w_128:
9642 case Intrinsic::x86_ssse3_phadd_d_128:
9643 case Intrinsic::x86_avx2_phadd_w:
9644 case Intrinsic::x86_avx2_phadd_d:
9645 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9646 Op.getOperand(1), Op.getOperand(2));
9647 case Intrinsic::x86_ssse3_phsub_w_128:
9648 case Intrinsic::x86_ssse3_phsub_d_128:
9649 case Intrinsic::x86_avx2_phsub_w:
9650 case Intrinsic::x86_avx2_phsub_d:
9651 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9652 Op.getOperand(1), Op.getOperand(2));
9653 case Intrinsic::x86_avx2_psllv_d:
9654 case Intrinsic::x86_avx2_psllv_q:
9655 case Intrinsic::x86_avx2_psllv_d_256:
9656 case Intrinsic::x86_avx2_psllv_q_256:
9657 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9658 Op.getOperand(1), Op.getOperand(2));
9659 case Intrinsic::x86_avx2_psrlv_d:
9660 case Intrinsic::x86_avx2_psrlv_q:
9661 case Intrinsic::x86_avx2_psrlv_d_256:
9662 case Intrinsic::x86_avx2_psrlv_q_256:
9663 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9664 Op.getOperand(1), Op.getOperand(2));
9665 case Intrinsic::x86_avx2_psrav_d:
9666 case Intrinsic::x86_avx2_psrav_d_256:
9667 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9668 Op.getOperand(1), Op.getOperand(2));
9669 case Intrinsic::x86_ssse3_pshuf_b_128:
9670 case Intrinsic::x86_avx2_pshuf_b:
9671 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9672 Op.getOperand(1), Op.getOperand(2));
9673 case Intrinsic::x86_ssse3_psign_b_128:
9674 case Intrinsic::x86_ssse3_psign_w_128:
9675 case Intrinsic::x86_ssse3_psign_d_128:
9676 case Intrinsic::x86_avx2_psign_b:
9677 case Intrinsic::x86_avx2_psign_w:
9678 case Intrinsic::x86_avx2_psign_d:
9679 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9680 Op.getOperand(1), Op.getOperand(2));
9681 case Intrinsic::x86_sse41_insertps:
9682 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9683 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9684 case Intrinsic::x86_avx_vperm2f128_ps_256:
9685 case Intrinsic::x86_avx_vperm2f128_pd_256:
9686 case Intrinsic::x86_avx_vperm2f128_si_256:
9687 case Intrinsic::x86_avx2_vperm2i128:
9688 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9689 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9690 case Intrinsic::x86_avx2_permd:
9691 case Intrinsic::x86_avx2_permps:
9692 // Operands intentionally swapped. Mask is last operand to intrinsic,
9693 // but second operand for node/intruction.
9694 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9695 Op.getOperand(2), Op.getOperand(1));
9697 // ptest and testp intrinsics. The intrinsic these come from are designed to
9698 // return an integer value, not just an instruction so lower it to the ptest
9699 // or testp pattern and a setcc for the result.
9700 case Intrinsic::x86_sse41_ptestz:
9701 case Intrinsic::x86_sse41_ptestc:
9702 case Intrinsic::x86_sse41_ptestnzc:
9703 case Intrinsic::x86_avx_ptestz_256:
9704 case Intrinsic::x86_avx_ptestc_256:
9705 case Intrinsic::x86_avx_ptestnzc_256:
9706 case Intrinsic::x86_avx_vtestz_ps:
9707 case Intrinsic::x86_avx_vtestc_ps:
9708 case Intrinsic::x86_avx_vtestnzc_ps:
9709 case Intrinsic::x86_avx_vtestz_pd:
9710 case Intrinsic::x86_avx_vtestc_pd:
9711 case Intrinsic::x86_avx_vtestnzc_pd:
9712 case Intrinsic::x86_avx_vtestz_ps_256:
9713 case Intrinsic::x86_avx_vtestc_ps_256:
9714 case Intrinsic::x86_avx_vtestnzc_ps_256:
9715 case Intrinsic::x86_avx_vtestz_pd_256:
9716 case Intrinsic::x86_avx_vtestc_pd_256:
9717 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9718 bool IsTestPacked = false;
9721 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9722 case Intrinsic::x86_avx_vtestz_ps:
9723 case Intrinsic::x86_avx_vtestz_pd:
9724 case Intrinsic::x86_avx_vtestz_ps_256:
9725 case Intrinsic::x86_avx_vtestz_pd_256:
9726 IsTestPacked = true; // Fallthrough
9727 case Intrinsic::x86_sse41_ptestz:
9728 case Intrinsic::x86_avx_ptestz_256:
9730 X86CC = X86::COND_E;
9732 case Intrinsic::x86_avx_vtestc_ps:
9733 case Intrinsic::x86_avx_vtestc_pd:
9734 case Intrinsic::x86_avx_vtestc_ps_256:
9735 case Intrinsic::x86_avx_vtestc_pd_256:
9736 IsTestPacked = true; // Fallthrough
9737 case Intrinsic::x86_sse41_ptestc:
9738 case Intrinsic::x86_avx_ptestc_256:
9740 X86CC = X86::COND_B;
9742 case Intrinsic::x86_avx_vtestnzc_ps:
9743 case Intrinsic::x86_avx_vtestnzc_pd:
9744 case Intrinsic::x86_avx_vtestnzc_ps_256:
9745 case Intrinsic::x86_avx_vtestnzc_pd_256:
9746 IsTestPacked = true; // Fallthrough
9747 case Intrinsic::x86_sse41_ptestnzc:
9748 case Intrinsic::x86_avx_ptestnzc_256:
9750 X86CC = X86::COND_A;
9754 SDValue LHS = Op.getOperand(1);
9755 SDValue RHS = Op.getOperand(2);
9756 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9757 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9758 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9759 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9760 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9763 // SSE/AVX shift intrinsics
9764 case Intrinsic::x86_sse2_psll_w:
9765 case Intrinsic::x86_sse2_psll_d:
9766 case Intrinsic::x86_sse2_psll_q:
9767 case Intrinsic::x86_avx2_psll_w:
9768 case Intrinsic::x86_avx2_psll_d:
9769 case Intrinsic::x86_avx2_psll_q:
9770 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9771 Op.getOperand(1), Op.getOperand(2));
9772 case Intrinsic::x86_sse2_psrl_w:
9773 case Intrinsic::x86_sse2_psrl_d:
9774 case Intrinsic::x86_sse2_psrl_q:
9775 case Intrinsic::x86_avx2_psrl_w:
9776 case Intrinsic::x86_avx2_psrl_d:
9777 case Intrinsic::x86_avx2_psrl_q:
9778 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9779 Op.getOperand(1), Op.getOperand(2));
9780 case Intrinsic::x86_sse2_psra_w:
9781 case Intrinsic::x86_sse2_psra_d:
9782 case Intrinsic::x86_avx2_psra_w:
9783 case Intrinsic::x86_avx2_psra_d:
9784 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9785 Op.getOperand(1), Op.getOperand(2));
9786 case Intrinsic::x86_sse2_pslli_w:
9787 case Intrinsic::x86_sse2_pslli_d:
9788 case Intrinsic::x86_sse2_pslli_q:
9789 case Intrinsic::x86_avx2_pslli_w:
9790 case Intrinsic::x86_avx2_pslli_d:
9791 case Intrinsic::x86_avx2_pslli_q:
9792 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9793 Op.getOperand(1), Op.getOperand(2), DAG);
9794 case Intrinsic::x86_sse2_psrli_w:
9795 case Intrinsic::x86_sse2_psrli_d:
9796 case Intrinsic::x86_sse2_psrli_q:
9797 case Intrinsic::x86_avx2_psrli_w:
9798 case Intrinsic::x86_avx2_psrli_d:
9799 case Intrinsic::x86_avx2_psrli_q:
9800 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9801 Op.getOperand(1), Op.getOperand(2), DAG);
9802 case Intrinsic::x86_sse2_psrai_w:
9803 case Intrinsic::x86_sse2_psrai_d:
9804 case Intrinsic::x86_avx2_psrai_w:
9805 case Intrinsic::x86_avx2_psrai_d:
9806 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9807 Op.getOperand(1), Op.getOperand(2), DAG);
9808 // Fix vector shift instructions where the last operand is a non-immediate
9810 case Intrinsic::x86_mmx_pslli_w:
9811 case Intrinsic::x86_mmx_pslli_d:
9812 case Intrinsic::x86_mmx_pslli_q:
9813 case Intrinsic::x86_mmx_psrli_w:
9814 case Intrinsic::x86_mmx_psrli_d:
9815 case Intrinsic::x86_mmx_psrli_q:
9816 case Intrinsic::x86_mmx_psrai_w:
9817 case Intrinsic::x86_mmx_psrai_d: {
9818 SDValue ShAmt = Op.getOperand(2);
9819 if (isa<ConstantSDNode>(ShAmt))
9822 unsigned NewIntNo = 0;
9824 case Intrinsic::x86_mmx_pslli_w:
9825 NewIntNo = Intrinsic::x86_mmx_psll_w;
9827 case Intrinsic::x86_mmx_pslli_d:
9828 NewIntNo = Intrinsic::x86_mmx_psll_d;
9830 case Intrinsic::x86_mmx_pslli_q:
9831 NewIntNo = Intrinsic::x86_mmx_psll_q;
9833 case Intrinsic::x86_mmx_psrli_w:
9834 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9836 case Intrinsic::x86_mmx_psrli_d:
9837 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9839 case Intrinsic::x86_mmx_psrli_q:
9840 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9842 case Intrinsic::x86_mmx_psrai_w:
9843 NewIntNo = Intrinsic::x86_mmx_psra_w;
9845 case Intrinsic::x86_mmx_psrai_d:
9846 NewIntNo = Intrinsic::x86_mmx_psra_d;
9848 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9851 // The vector shift intrinsics with scalars uses 32b shift amounts but
9852 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9854 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9855 DAG.getConstant(0, MVT::i32));
9856 // FIXME this must be lowered to get rid of the invalid type.
9858 EVT VT = Op.getValueType();
9859 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9860 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9861 DAG.getConstant(NewIntNo, MVT::i32),
9862 Op.getOperand(1), ShAmt);
9868 X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9869 DebugLoc dl = Op.getDebugLoc();
9870 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9872 default: return SDValue(); // Don't custom lower most intrinsics.
9874 // RDRAND intrinsics.
9875 case Intrinsic::x86_rdrand_16:
9876 case Intrinsic::x86_rdrand_32:
9877 case Intrinsic::x86_rdrand_64: {
9878 // Emit the node with the right value type.
9879 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
9880 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
9882 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
9883 // return the value from Rand, which is always 0, casted to i32.
9884 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
9885 DAG.getConstant(1, Op->getValueType(1)),
9886 DAG.getConstant(X86::COND_B, MVT::i32),
9887 SDValue(Result.getNode(), 1) };
9888 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
9889 DAG.getVTList(Op->getValueType(1), MVT::Glue),
9892 // Return { result, isValid, chain }.
9893 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
9894 SDValue(Result.getNode(), 2));
9899 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9900 SelectionDAG &DAG) const {
9901 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9902 MFI->setReturnAddressIsTaken(true);
9904 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9905 DebugLoc dl = Op.getDebugLoc();
9908 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9910 DAG.getConstant(TD->getPointerSize(),
9911 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9912 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9913 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9915 MachinePointerInfo(), false, false, false, 0);
9918 // Just load the return address.
9919 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9920 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9921 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9924 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9925 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9926 MFI->setFrameAddressIsTaken(true);
9928 EVT VT = Op.getValueType();
9929 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9930 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9931 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9932 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9934 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9935 MachinePointerInfo(),
9936 false, false, false, 0);
9940 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9941 SelectionDAG &DAG) const {
9942 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9945 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9946 SDValue Chain = Op.getOperand(0);
9947 SDValue Offset = Op.getOperand(1);
9948 SDValue Handler = Op.getOperand(2);
9949 DebugLoc dl = Op.getDebugLoc();
9951 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9952 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9954 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9956 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9957 DAG.getIntPtrConstant(TD->getPointerSize()));
9958 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9959 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9961 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9963 return DAG.getNode(X86ISD::EH_RETURN, dl,
9965 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9968 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9969 SelectionDAG &DAG) const {
9970 return Op.getOperand(0);
9973 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9974 SelectionDAG &DAG) const {
9975 SDValue Root = Op.getOperand(0);
9976 SDValue Trmp = Op.getOperand(1); // trampoline
9977 SDValue FPtr = Op.getOperand(2); // nested function
9978 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9979 DebugLoc dl = Op.getDebugLoc();
9981 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9983 if (Subtarget->is64Bit()) {
9984 SDValue OutChains[6];
9986 // Large code-model.
9987 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9988 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9990 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9991 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9993 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9995 // Load the pointer to the nested function into R11.
9996 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9997 SDValue Addr = Trmp;
9998 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9999 Addr, MachinePointerInfo(TrmpAddr),
10002 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10003 DAG.getConstant(2, MVT::i64));
10004 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
10005 MachinePointerInfo(TrmpAddr, 2),
10008 // Load the 'nest' parameter value into R10.
10009 // R10 is specified in X86CallingConv.td
10010 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
10011 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10012 DAG.getConstant(10, MVT::i64));
10013 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10014 Addr, MachinePointerInfo(TrmpAddr, 10),
10017 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10018 DAG.getConstant(12, MVT::i64));
10019 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
10020 MachinePointerInfo(TrmpAddr, 12),
10023 // Jump to the nested function.
10024 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
10025 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10026 DAG.getConstant(20, MVT::i64));
10027 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10028 Addr, MachinePointerInfo(TrmpAddr, 20),
10031 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
10032 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10033 DAG.getConstant(22, MVT::i64));
10034 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
10035 MachinePointerInfo(TrmpAddr, 22),
10038 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
10040 const Function *Func =
10041 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
10042 CallingConv::ID CC = Func->getCallingConv();
10047 llvm_unreachable("Unsupported calling convention");
10048 case CallingConv::C:
10049 case CallingConv::X86_StdCall: {
10050 // Pass 'nest' parameter in ECX.
10051 // Must be kept in sync with X86CallingConv.td
10052 NestReg = X86::ECX;
10054 // Check that ECX wasn't needed by an 'inreg' parameter.
10055 FunctionType *FTy = Func->getFunctionType();
10056 const AttrListPtr &Attrs = Func->getAttributes();
10058 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10059 unsigned InRegCount = 0;
10062 for (FunctionType::param_iterator I = FTy->param_begin(),
10063 E = FTy->param_end(); I != E; ++I, ++Idx)
10064 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10065 // FIXME: should only count parameters that are lowered to integers.
10066 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10068 if (InRegCount > 2) {
10069 report_fatal_error("Nest register in use - reduce number of inreg"
10075 case CallingConv::X86_FastCall:
10076 case CallingConv::X86_ThisCall:
10077 case CallingConv::Fast:
10078 // Pass 'nest' parameter in EAX.
10079 // Must be kept in sync with X86CallingConv.td
10080 NestReg = X86::EAX;
10084 SDValue OutChains[4];
10085 SDValue Addr, Disp;
10087 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10088 DAG.getConstant(10, MVT::i32));
10089 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10091 // This is storing the opcode for MOV32ri.
10092 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10093 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10094 OutChains[0] = DAG.getStore(Root, dl,
10095 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10096 Trmp, MachinePointerInfo(TrmpAddr),
10099 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10100 DAG.getConstant(1, MVT::i32));
10101 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10102 MachinePointerInfo(TrmpAddr, 1),
10105 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10106 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10107 DAG.getConstant(5, MVT::i32));
10108 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10109 MachinePointerInfo(TrmpAddr, 5),
10112 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10113 DAG.getConstant(6, MVT::i32));
10114 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10115 MachinePointerInfo(TrmpAddr, 6),
10118 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10122 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10123 SelectionDAG &DAG) const {
10125 The rounding mode is in bits 11:10 of FPSR, and has the following
10127 00 Round to nearest
10132 FLT_ROUNDS, on the other hand, expects the following:
10139 To perform the conversion, we do:
10140 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10143 MachineFunction &MF = DAG.getMachineFunction();
10144 const TargetMachine &TM = MF.getTarget();
10145 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10146 unsigned StackAlignment = TFI.getStackAlignment();
10147 EVT VT = Op.getValueType();
10148 DebugLoc DL = Op.getDebugLoc();
10150 // Save FP Control Word to stack slot
10151 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10152 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10155 MachineMemOperand *MMO =
10156 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10157 MachineMemOperand::MOStore, 2, 2);
10159 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10160 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10161 DAG.getVTList(MVT::Other),
10162 Ops, 2, MVT::i16, MMO);
10164 // Load FP Control Word from stack slot
10165 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10166 MachinePointerInfo(), false, false, false, 0);
10168 // Transform as necessary
10170 DAG.getNode(ISD::SRL, DL, MVT::i16,
10171 DAG.getNode(ISD::AND, DL, MVT::i16,
10172 CWD, DAG.getConstant(0x800, MVT::i16)),
10173 DAG.getConstant(11, MVT::i8));
10175 DAG.getNode(ISD::SRL, DL, MVT::i16,
10176 DAG.getNode(ISD::AND, DL, MVT::i16,
10177 CWD, DAG.getConstant(0x400, MVT::i16)),
10178 DAG.getConstant(9, MVT::i8));
10181 DAG.getNode(ISD::AND, DL, MVT::i16,
10182 DAG.getNode(ISD::ADD, DL, MVT::i16,
10183 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10184 DAG.getConstant(1, MVT::i16)),
10185 DAG.getConstant(3, MVT::i16));
10188 return DAG.getNode((VT.getSizeInBits() < 16 ?
10189 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10192 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10193 EVT VT = Op.getValueType();
10195 unsigned NumBits = VT.getSizeInBits();
10196 DebugLoc dl = Op.getDebugLoc();
10198 Op = Op.getOperand(0);
10199 if (VT == MVT::i8) {
10200 // Zero extend to i32 since there is not an i8 bsr.
10202 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10205 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10206 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10207 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10209 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10212 DAG.getConstant(NumBits+NumBits-1, OpVT),
10213 DAG.getConstant(X86::COND_E, MVT::i8),
10216 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10218 // Finally xor with NumBits-1.
10219 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10222 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10226 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10227 SelectionDAG &DAG) const {
10228 EVT VT = Op.getValueType();
10230 unsigned NumBits = VT.getSizeInBits();
10231 DebugLoc dl = Op.getDebugLoc();
10233 Op = Op.getOperand(0);
10234 if (VT == MVT::i8) {
10235 // Zero extend to i32 since there is not an i8 bsr.
10237 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10240 // Issue a bsr (scan bits in reverse).
10241 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10242 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10244 // And xor with NumBits-1.
10245 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10248 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10252 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10253 EVT VT = Op.getValueType();
10254 unsigned NumBits = VT.getSizeInBits();
10255 DebugLoc dl = Op.getDebugLoc();
10256 Op = Op.getOperand(0);
10258 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10259 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10260 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10262 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10265 DAG.getConstant(NumBits, VT),
10266 DAG.getConstant(X86::COND_E, MVT::i8),
10269 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10272 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10273 // ones, and then concatenate the result back.
10274 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10275 EVT VT = Op.getValueType();
10277 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10278 "Unsupported value type for operation");
10280 unsigned NumElems = VT.getVectorNumElements();
10281 DebugLoc dl = Op.getDebugLoc();
10283 // Extract the LHS vectors
10284 SDValue LHS = Op.getOperand(0);
10285 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10286 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10288 // Extract the RHS vectors
10289 SDValue RHS = Op.getOperand(1);
10290 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10291 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10293 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10294 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10296 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10297 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10298 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10301 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10302 assert(Op.getValueType().getSizeInBits() == 256 &&
10303 Op.getValueType().isInteger() &&
10304 "Only handle AVX 256-bit vector integer operation");
10305 return Lower256IntArith(Op, DAG);
10308 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10309 assert(Op.getValueType().getSizeInBits() == 256 &&
10310 Op.getValueType().isInteger() &&
10311 "Only handle AVX 256-bit vector integer operation");
10312 return Lower256IntArith(Op, DAG);
10315 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10316 EVT VT = Op.getValueType();
10318 // Decompose 256-bit ops into smaller 128-bit ops.
10319 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10320 return Lower256IntArith(Op, DAG);
10322 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10323 "Only know how to lower V2I64/V4I64 multiply");
10325 DebugLoc dl = Op.getDebugLoc();
10327 // Ahi = psrlqi(a, 32);
10328 // Bhi = psrlqi(b, 32);
10330 // AloBlo = pmuludq(a, b);
10331 // AloBhi = pmuludq(a, Bhi);
10332 // AhiBlo = pmuludq(Ahi, b);
10334 // AloBhi = psllqi(AloBhi, 32);
10335 // AhiBlo = psllqi(AhiBlo, 32);
10336 // return AloBlo + AloBhi + AhiBlo;
10338 SDValue A = Op.getOperand(0);
10339 SDValue B = Op.getOperand(1);
10341 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10343 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10344 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10346 // Bit cast to 32-bit vectors for MULUDQ
10347 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10348 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10349 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10350 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10351 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10353 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10354 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10355 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10357 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10358 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10360 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10361 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10364 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10366 EVT VT = Op.getValueType();
10367 DebugLoc dl = Op.getDebugLoc();
10368 SDValue R = Op.getOperand(0);
10369 SDValue Amt = Op.getOperand(1);
10370 LLVMContext *Context = DAG.getContext();
10372 if (!Subtarget->hasSSE2())
10375 // Optimize shl/srl/sra with constant shift amount.
10376 if (isSplatVector(Amt.getNode())) {
10377 SDValue SclrAmt = Amt->getOperand(0);
10378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10379 uint64_t ShiftAmt = C->getZExtValue();
10381 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10382 (Subtarget->hasAVX2() &&
10383 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10384 if (Op.getOpcode() == ISD::SHL)
10385 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10386 DAG.getConstant(ShiftAmt, MVT::i32));
10387 if (Op.getOpcode() == ISD::SRL)
10388 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10389 DAG.getConstant(ShiftAmt, MVT::i32));
10390 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10391 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10392 DAG.getConstant(ShiftAmt, MVT::i32));
10395 if (VT == MVT::v16i8) {
10396 if (Op.getOpcode() == ISD::SHL) {
10397 // Make a large shift.
10398 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10399 DAG.getConstant(ShiftAmt, MVT::i32));
10400 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10401 // Zero out the rightmost bits.
10402 SmallVector<SDValue, 16> V(16,
10403 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10405 return DAG.getNode(ISD::AND, dl, VT, SHL,
10406 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10408 if (Op.getOpcode() == ISD::SRL) {
10409 // Make a large shift.
10410 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10411 DAG.getConstant(ShiftAmt, MVT::i32));
10412 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10413 // Zero out the leftmost bits.
10414 SmallVector<SDValue, 16> V(16,
10415 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10417 return DAG.getNode(ISD::AND, dl, VT, SRL,
10418 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10420 if (Op.getOpcode() == ISD::SRA) {
10421 if (ShiftAmt == 7) {
10422 // R s>> 7 === R s< 0
10423 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10424 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10427 // R s>> a === ((R u>> a) ^ m) - m
10428 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10429 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10431 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10432 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10433 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10436 llvm_unreachable("Unknown shift opcode.");
10439 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10440 if (Op.getOpcode() == ISD::SHL) {
10441 // Make a large shift.
10442 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10443 DAG.getConstant(ShiftAmt, MVT::i32));
10444 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10445 // Zero out the rightmost bits.
10446 SmallVector<SDValue, 32> V(32,
10447 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10449 return DAG.getNode(ISD::AND, dl, VT, SHL,
10450 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10452 if (Op.getOpcode() == ISD::SRL) {
10453 // Make a large shift.
10454 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10455 DAG.getConstant(ShiftAmt, MVT::i32));
10456 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10457 // Zero out the leftmost bits.
10458 SmallVector<SDValue, 32> V(32,
10459 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10461 return DAG.getNode(ISD::AND, dl, VT, SRL,
10462 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10464 if (Op.getOpcode() == ISD::SRA) {
10465 if (ShiftAmt == 7) {
10466 // R s>> 7 === R s< 0
10467 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10468 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10471 // R s>> a === ((R u>> a) ^ m) - m
10472 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10473 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10475 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10476 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10477 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10480 llvm_unreachable("Unknown shift opcode.");
10485 // Lower SHL with variable shift amount.
10486 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10487 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10488 DAG.getConstant(23, MVT::i32));
10490 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10491 Constant *C = ConstantDataVector::get(*Context, CV);
10492 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10493 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10494 MachinePointerInfo::getConstantPool(),
10495 false, false, false, 16);
10497 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10498 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10499 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10500 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10502 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10503 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10506 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10507 DAG.getConstant(5, MVT::i32));
10508 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10510 // Turn 'a' into a mask suitable for VSELECT
10511 SDValue VSelM = DAG.getConstant(0x80, VT);
10512 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10513 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10515 SDValue CM1 = DAG.getConstant(0x0f, VT);
10516 SDValue CM2 = DAG.getConstant(0x3f, VT);
10518 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10519 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10520 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10521 DAG.getConstant(4, MVT::i32), DAG);
10522 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10523 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10526 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10527 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10528 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10530 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10531 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10532 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10533 DAG.getConstant(2, MVT::i32), DAG);
10534 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10535 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10538 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10539 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10540 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10542 // return VSELECT(r, r+r, a);
10543 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10544 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10548 // Decompose 256-bit shifts into smaller 128-bit shifts.
10549 if (VT.getSizeInBits() == 256) {
10550 unsigned NumElems = VT.getVectorNumElements();
10551 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10552 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10554 // Extract the two vectors
10555 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10556 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10558 // Recreate the shift amount vectors
10559 SDValue Amt1, Amt2;
10560 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10561 // Constant shift amount
10562 SmallVector<SDValue, 4> Amt1Csts;
10563 SmallVector<SDValue, 4> Amt2Csts;
10564 for (unsigned i = 0; i != NumElems/2; ++i)
10565 Amt1Csts.push_back(Amt->getOperand(i));
10566 for (unsigned i = NumElems/2; i != NumElems; ++i)
10567 Amt2Csts.push_back(Amt->getOperand(i));
10569 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10570 &Amt1Csts[0], NumElems/2);
10571 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10572 &Amt2Csts[0], NumElems/2);
10574 // Variable shift amount
10575 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10576 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10579 // Issue new vector shifts for the smaller types
10580 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10581 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10583 // Concatenate the result back
10584 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10590 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10591 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10592 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10593 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10594 // has only one use.
10595 SDNode *N = Op.getNode();
10596 SDValue LHS = N->getOperand(0);
10597 SDValue RHS = N->getOperand(1);
10598 unsigned BaseOp = 0;
10600 DebugLoc DL = Op.getDebugLoc();
10601 switch (Op.getOpcode()) {
10602 default: llvm_unreachable("Unknown ovf instruction!");
10604 // A subtract of one will be selected as a INC. Note that INC doesn't
10605 // set CF, so we can't do this for UADDO.
10606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10608 BaseOp = X86ISD::INC;
10609 Cond = X86::COND_O;
10612 BaseOp = X86ISD::ADD;
10613 Cond = X86::COND_O;
10616 BaseOp = X86ISD::ADD;
10617 Cond = X86::COND_B;
10620 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10621 // set CF, so we can't do this for USUBO.
10622 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10624 BaseOp = X86ISD::DEC;
10625 Cond = X86::COND_O;
10628 BaseOp = X86ISD::SUB;
10629 Cond = X86::COND_O;
10632 BaseOp = X86ISD::SUB;
10633 Cond = X86::COND_B;
10636 BaseOp = X86ISD::SMUL;
10637 Cond = X86::COND_O;
10639 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10640 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10642 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10645 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10646 DAG.getConstant(X86::COND_O, MVT::i32),
10647 SDValue(Sum.getNode(), 2));
10649 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10653 // Also sets EFLAGS.
10654 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10655 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10658 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10659 DAG.getConstant(Cond, MVT::i32),
10660 SDValue(Sum.getNode(), 1));
10662 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10665 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10666 SelectionDAG &DAG) const {
10667 DebugLoc dl = Op.getDebugLoc();
10668 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10669 EVT VT = Op.getValueType();
10671 if (!Subtarget->hasSSE2() || !VT.isVector())
10674 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10675 ExtraVT.getScalarType().getSizeInBits();
10676 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10678 switch (VT.getSimpleVT().SimpleTy) {
10679 default: return SDValue();
10682 if (!Subtarget->hasAVX())
10684 if (!Subtarget->hasAVX2()) {
10685 // needs to be split
10686 unsigned NumElems = VT.getVectorNumElements();
10688 // Extract the LHS vectors
10689 SDValue LHS = Op.getOperand(0);
10690 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10691 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10693 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10694 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10696 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10697 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10698 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10700 SDValue Extra = DAG.getValueType(ExtraVT);
10702 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10703 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10705 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10710 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10711 Op.getOperand(0), ShAmt, DAG);
10712 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10718 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10719 DebugLoc dl = Op.getDebugLoc();
10721 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10722 // There isn't any reason to disable it if the target processor supports it.
10723 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10724 SDValue Chain = Op.getOperand(0);
10725 SDValue Zero = DAG.getConstant(0, MVT::i32);
10727 DAG.getRegister(X86::ESP, MVT::i32), // Base
10728 DAG.getTargetConstant(1, MVT::i8), // Scale
10729 DAG.getRegister(0, MVT::i32), // Index
10730 DAG.getTargetConstant(0, MVT::i32), // Disp
10731 DAG.getRegister(0, MVT::i32), // Segment.
10736 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10737 array_lengthof(Ops));
10738 return SDValue(Res, 0);
10741 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10743 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10745 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10746 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10747 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10748 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10750 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10751 if (!Op1 && !Op2 && !Op3 && Op4)
10752 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10754 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10755 if (Op1 && !Op2 && !Op3 && !Op4)
10756 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10758 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10760 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10763 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10764 SelectionDAG &DAG) const {
10765 DebugLoc dl = Op.getDebugLoc();
10766 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10767 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10768 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10769 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10771 // The only fence that needs an instruction is a sequentially-consistent
10772 // cross-thread fence.
10773 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10774 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10775 // no-sse2). There isn't any reason to disable it if the target processor
10777 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10778 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10780 SDValue Chain = Op.getOperand(0);
10781 SDValue Zero = DAG.getConstant(0, MVT::i32);
10783 DAG.getRegister(X86::ESP, MVT::i32), // Base
10784 DAG.getTargetConstant(1, MVT::i8), // Scale
10785 DAG.getRegister(0, MVT::i32), // Index
10786 DAG.getTargetConstant(0, MVT::i32), // Disp
10787 DAG.getRegister(0, MVT::i32), // Segment.
10792 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10793 array_lengthof(Ops));
10794 return SDValue(Res, 0);
10797 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10798 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10802 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10803 EVT T = Op.getValueType();
10804 DebugLoc DL = Op.getDebugLoc();
10807 switch(T.getSimpleVT().SimpleTy) {
10808 default: llvm_unreachable("Invalid value type!");
10809 case MVT::i8: Reg = X86::AL; size = 1; break;
10810 case MVT::i16: Reg = X86::AX; size = 2; break;
10811 case MVT::i32: Reg = X86::EAX; size = 4; break;
10813 assert(Subtarget->is64Bit() && "Node not type legal!");
10814 Reg = X86::RAX; size = 8;
10817 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10818 Op.getOperand(2), SDValue());
10819 SDValue Ops[] = { cpIn.getValue(0),
10822 DAG.getTargetConstant(size, MVT::i8),
10823 cpIn.getValue(1) };
10824 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10825 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10826 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10829 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10833 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10834 SelectionDAG &DAG) const {
10835 assert(Subtarget->is64Bit() && "Result not type legalized?");
10836 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10837 SDValue TheChain = Op.getOperand(0);
10838 DebugLoc dl = Op.getDebugLoc();
10839 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10840 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10841 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10843 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10844 DAG.getConstant(32, MVT::i8));
10846 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10849 return DAG.getMergeValues(Ops, 2, dl);
10852 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10853 SelectionDAG &DAG) const {
10854 EVT SrcVT = Op.getOperand(0).getValueType();
10855 EVT DstVT = Op.getValueType();
10856 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10857 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10858 assert((DstVT == MVT::i64 ||
10859 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10860 "Unexpected custom BITCAST");
10861 // i64 <=> MMX conversions are Legal.
10862 if (SrcVT==MVT::i64 && DstVT.isVector())
10864 if (DstVT==MVT::i64 && SrcVT.isVector())
10866 // MMX <=> MMX conversions are Legal.
10867 if (SrcVT.isVector() && DstVT.isVector())
10869 // All other conversions need to be expanded.
10873 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10874 SDNode *Node = Op.getNode();
10875 DebugLoc dl = Node->getDebugLoc();
10876 EVT T = Node->getValueType(0);
10877 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10878 DAG.getConstant(0, T), Node->getOperand(2));
10879 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10880 cast<AtomicSDNode>(Node)->getMemoryVT(),
10881 Node->getOperand(0),
10882 Node->getOperand(1), negOp,
10883 cast<AtomicSDNode>(Node)->getSrcValue(),
10884 cast<AtomicSDNode>(Node)->getAlignment(),
10885 cast<AtomicSDNode>(Node)->getOrdering(),
10886 cast<AtomicSDNode>(Node)->getSynchScope());
10889 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10890 SDNode *Node = Op.getNode();
10891 DebugLoc dl = Node->getDebugLoc();
10892 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10894 // Convert seq_cst store -> xchg
10895 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10896 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10897 // (The only way to get a 16-byte store is cmpxchg16b)
10898 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10899 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10900 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10901 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10902 cast<AtomicSDNode>(Node)->getMemoryVT(),
10903 Node->getOperand(0),
10904 Node->getOperand(1), Node->getOperand(2),
10905 cast<AtomicSDNode>(Node)->getMemOperand(),
10906 cast<AtomicSDNode>(Node)->getOrdering(),
10907 cast<AtomicSDNode>(Node)->getSynchScope());
10908 return Swap.getValue(1);
10910 // Other atomic stores have a simple pattern.
10914 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10915 EVT VT = Op.getNode()->getValueType(0);
10917 // Let legalize expand this if it isn't a legal type yet.
10918 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10921 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10924 bool ExtraOp = false;
10925 switch (Op.getOpcode()) {
10926 default: llvm_unreachable("Invalid code");
10927 case ISD::ADDC: Opc = X86ISD::ADD; break;
10928 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10929 case ISD::SUBC: Opc = X86ISD::SUB; break;
10930 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10934 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10936 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10937 Op.getOperand(1), Op.getOperand(2));
10940 /// LowerOperation - Provide custom lowering hooks for some operations.
10942 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10943 switch (Op.getOpcode()) {
10944 default: llvm_unreachable("Should not custom lower this!");
10945 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10946 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10947 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10948 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10949 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10950 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10951 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10952 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10953 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10954 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10955 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10956 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10957 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10958 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10959 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10960 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10961 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10962 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10963 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10964 case ISD::SHL_PARTS:
10965 case ISD::SRA_PARTS:
10966 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10967 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10968 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10969 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10970 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10971 case ISD::FABS: return LowerFABS(Op, DAG);
10972 case ISD::FNEG: return LowerFNEG(Op, DAG);
10973 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10974 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10975 case ISD::SETCC: return LowerSETCC(Op, DAG);
10976 case ISD::SELECT: return LowerSELECT(Op, DAG);
10977 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10978 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10979 case ISD::VASTART: return LowerVASTART(Op, DAG);
10980 case ISD::VAARG: return LowerVAARG(Op, DAG);
10981 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10982 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10983 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
10984 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10985 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10986 case ISD::FRAME_TO_ARGS_OFFSET:
10987 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10988 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10989 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10990 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10991 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10992 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10993 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10994 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10995 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10996 case ISD::MUL: return LowerMUL(Op, DAG);
10999 case ISD::SHL: return LowerShift(Op, DAG);
11005 case ISD::UMULO: return LowerXALUO(Op, DAG);
11006 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
11007 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
11011 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
11012 case ISD::ADD: return LowerADD(Op, DAG);
11013 case ISD::SUB: return LowerSUB(Op, DAG);
11017 static void ReplaceATOMIC_LOAD(SDNode *Node,
11018 SmallVectorImpl<SDValue> &Results,
11019 SelectionDAG &DAG) {
11020 DebugLoc dl = Node->getDebugLoc();
11021 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11023 // Convert wide load -> cmpxchg8b/cmpxchg16b
11024 // FIXME: On 32-bit, load -> fild or movq would be more efficient
11025 // (The only way to get a 16-byte load is cmpxchg16b)
11026 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
11027 SDValue Zero = DAG.getConstant(0, VT);
11028 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
11029 Node->getOperand(0),
11030 Node->getOperand(1), Zero, Zero,
11031 cast<AtomicSDNode>(Node)->getMemOperand(),
11032 cast<AtomicSDNode>(Node)->getOrdering(),
11033 cast<AtomicSDNode>(Node)->getSynchScope());
11034 Results.push_back(Swap.getValue(0));
11035 Results.push_back(Swap.getValue(1));
11038 void X86TargetLowering::
11039 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
11040 SelectionDAG &DAG, unsigned NewOp) const {
11041 DebugLoc dl = Node->getDebugLoc();
11042 assert (Node->getValueType(0) == MVT::i64 &&
11043 "Only know how to expand i64 atomics");
11045 SDValue Chain = Node->getOperand(0);
11046 SDValue In1 = Node->getOperand(1);
11047 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11048 Node->getOperand(2), DAG.getIntPtrConstant(0));
11049 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11050 Node->getOperand(2), DAG.getIntPtrConstant(1));
11051 SDValue Ops[] = { Chain, In1, In2L, In2H };
11052 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11054 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11055 cast<MemSDNode>(Node)->getMemOperand());
11056 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11057 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11058 Results.push_back(Result.getValue(2));
11061 /// ReplaceNodeResults - Replace a node with an illegal result type
11062 /// with a new node built out of custom code.
11063 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11064 SmallVectorImpl<SDValue>&Results,
11065 SelectionDAG &DAG) const {
11066 DebugLoc dl = N->getDebugLoc();
11067 switch (N->getOpcode()) {
11069 llvm_unreachable("Do not know how to custom type legalize this operation!");
11070 case ISD::SIGN_EXTEND_INREG:
11075 // We don't want to expand or promote these.
11077 case ISD::FP_TO_SINT:
11078 case ISD::FP_TO_UINT: {
11079 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11081 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11084 std::pair<SDValue,SDValue> Vals =
11085 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11086 SDValue FIST = Vals.first, StackSlot = Vals.second;
11087 if (FIST.getNode() != 0) {
11088 EVT VT = N->getValueType(0);
11089 // Return a load from the stack slot.
11090 if (StackSlot.getNode() != 0)
11091 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11092 MachinePointerInfo(),
11093 false, false, false, 0));
11095 Results.push_back(FIST);
11099 case ISD::READCYCLECOUNTER: {
11100 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11101 SDValue TheChain = N->getOperand(0);
11102 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11103 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11105 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11107 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11108 SDValue Ops[] = { eax, edx };
11109 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11110 Results.push_back(edx.getValue(1));
11113 case ISD::ATOMIC_CMP_SWAP: {
11114 EVT T = N->getValueType(0);
11115 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11116 bool Regs64bit = T == MVT::i128;
11117 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11118 SDValue cpInL, cpInH;
11119 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11120 DAG.getConstant(0, HalfT));
11121 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11122 DAG.getConstant(1, HalfT));
11123 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11124 Regs64bit ? X86::RAX : X86::EAX,
11126 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11127 Regs64bit ? X86::RDX : X86::EDX,
11128 cpInH, cpInL.getValue(1));
11129 SDValue swapInL, swapInH;
11130 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11131 DAG.getConstant(0, HalfT));
11132 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11133 DAG.getConstant(1, HalfT));
11134 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11135 Regs64bit ? X86::RBX : X86::EBX,
11136 swapInL, cpInH.getValue(1));
11137 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11138 Regs64bit ? X86::RCX : X86::ECX,
11139 swapInH, swapInL.getValue(1));
11140 SDValue Ops[] = { swapInH.getValue(0),
11142 swapInH.getValue(1) };
11143 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11144 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11145 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11146 X86ISD::LCMPXCHG8_DAG;
11147 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11149 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11150 Regs64bit ? X86::RAX : X86::EAX,
11151 HalfT, Result.getValue(1));
11152 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11153 Regs64bit ? X86::RDX : X86::EDX,
11154 HalfT, cpOutL.getValue(2));
11155 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11156 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11157 Results.push_back(cpOutH.getValue(1));
11160 case ISD::ATOMIC_LOAD_ADD:
11161 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11163 case ISD::ATOMIC_LOAD_AND:
11164 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11166 case ISD::ATOMIC_LOAD_NAND:
11167 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11169 case ISD::ATOMIC_LOAD_OR:
11170 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11172 case ISD::ATOMIC_LOAD_SUB:
11173 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11175 case ISD::ATOMIC_LOAD_XOR:
11176 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11178 case ISD::ATOMIC_SWAP:
11179 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11181 case ISD::ATOMIC_LOAD:
11182 ReplaceATOMIC_LOAD(N, Results, DAG);
11186 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11188 default: return NULL;
11189 case X86ISD::BSF: return "X86ISD::BSF";
11190 case X86ISD::BSR: return "X86ISD::BSR";
11191 case X86ISD::SHLD: return "X86ISD::SHLD";
11192 case X86ISD::SHRD: return "X86ISD::SHRD";
11193 case X86ISD::FAND: return "X86ISD::FAND";
11194 case X86ISD::FOR: return "X86ISD::FOR";
11195 case X86ISD::FXOR: return "X86ISD::FXOR";
11196 case X86ISD::FSRL: return "X86ISD::FSRL";
11197 case X86ISD::FILD: return "X86ISD::FILD";
11198 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11199 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11200 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11201 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11202 case X86ISD::FLD: return "X86ISD::FLD";
11203 case X86ISD::FST: return "X86ISD::FST";
11204 case X86ISD::CALL: return "X86ISD::CALL";
11205 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11206 case X86ISD::BT: return "X86ISD::BT";
11207 case X86ISD::CMP: return "X86ISD::CMP";
11208 case X86ISD::COMI: return "X86ISD::COMI";
11209 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11210 case X86ISD::SETCC: return "X86ISD::SETCC";
11211 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11212 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11213 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11214 case X86ISD::CMOV: return "X86ISD::CMOV";
11215 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11216 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11217 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11218 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11219 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11220 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11221 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11222 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11223 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11224 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11225 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11226 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11227 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11228 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11229 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11230 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11231 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11232 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11233 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11234 case X86ISD::HADD: return "X86ISD::HADD";
11235 case X86ISD::HSUB: return "X86ISD::HSUB";
11236 case X86ISD::FHADD: return "X86ISD::FHADD";
11237 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11238 case X86ISD::FMAX: return "X86ISD::FMAX";
11239 case X86ISD::FMIN: return "X86ISD::FMIN";
11240 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11241 case X86ISD::FRCP: return "X86ISD::FRCP";
11242 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11243 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11244 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11245 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11246 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11247 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11248 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11249 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11250 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11251 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11252 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11253 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11254 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11255 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11256 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11257 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11258 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11259 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11260 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11261 case X86ISD::VSHL: return "X86ISD::VSHL";
11262 case X86ISD::VSRL: return "X86ISD::VSRL";
11263 case X86ISD::VSRA: return "X86ISD::VSRA";
11264 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11265 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11266 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11267 case X86ISD::CMPP: return "X86ISD::CMPP";
11268 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11269 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11270 case X86ISD::ADD: return "X86ISD::ADD";
11271 case X86ISD::SUB: return "X86ISD::SUB";
11272 case X86ISD::ADC: return "X86ISD::ADC";
11273 case X86ISD::SBB: return "X86ISD::SBB";
11274 case X86ISD::SMUL: return "X86ISD::SMUL";
11275 case X86ISD::UMUL: return "X86ISD::UMUL";
11276 case X86ISD::INC: return "X86ISD::INC";
11277 case X86ISD::DEC: return "X86ISD::DEC";
11278 case X86ISD::OR: return "X86ISD::OR";
11279 case X86ISD::XOR: return "X86ISD::XOR";
11280 case X86ISD::AND: return "X86ISD::AND";
11281 case X86ISD::ANDN: return "X86ISD::ANDN";
11282 case X86ISD::BLSI: return "X86ISD::BLSI";
11283 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11284 case X86ISD::BLSR: return "X86ISD::BLSR";
11285 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11286 case X86ISD::PTEST: return "X86ISD::PTEST";
11287 case X86ISD::TESTP: return "X86ISD::TESTP";
11288 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11289 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11290 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11291 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11292 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11293 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11294 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11295 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11296 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11297 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11298 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11299 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11300 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11301 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11302 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11303 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11304 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11305 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11306 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11307 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11308 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11309 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11310 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11311 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11312 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11313 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11314 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11315 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11316 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11317 case X86ISD::SAHF: return "X86ISD::SAHF";
11318 case X86ISD::RDRAND: return "X86ISD::RDRAND";
11322 // isLegalAddressingMode - Return true if the addressing mode represented
11323 // by AM is legal for this target, for a load/store of the specified type.
11324 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11326 // X86 supports extremely general addressing modes.
11327 CodeModel::Model M = getTargetMachine().getCodeModel();
11328 Reloc::Model R = getTargetMachine().getRelocationModel();
11330 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11331 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11336 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11338 // If a reference to this global requires an extra load, we can't fold it.
11339 if (isGlobalStubReference(GVFlags))
11342 // If BaseGV requires a register for the PIC base, we cannot also have a
11343 // BaseReg specified.
11344 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11347 // If lower 4G is not available, then we must use rip-relative addressing.
11348 if ((M != CodeModel::Small || R != Reloc::Static) &&
11349 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11353 switch (AM.Scale) {
11359 // These scales always work.
11364 // These scales are formed with basereg+scalereg. Only accept if there is
11369 default: // Other stuff never works.
11377 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11378 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11380 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11381 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11382 if (NumBits1 <= NumBits2)
11387 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11388 if (!VT1.isInteger() || !VT2.isInteger())
11390 unsigned NumBits1 = VT1.getSizeInBits();
11391 unsigned NumBits2 = VT2.getSizeInBits();
11392 if (NumBits1 <= NumBits2)
11397 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11398 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11399 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11402 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11403 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11404 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11407 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11408 // i16 instructions are longer (0x66 prefix) and potentially slower.
11409 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11412 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11413 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11414 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11415 /// are assumed to be legal.
11417 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11419 // Very little shuffling can be done for 64-bit vectors right now.
11420 if (VT.getSizeInBits() == 64)
11423 // FIXME: pshufb, blends, shifts.
11424 return (VT.getVectorNumElements() == 2 ||
11425 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11426 isMOVLMask(M, VT) ||
11427 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11428 isPSHUFDMask(M, VT) ||
11429 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11430 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11431 isPALIGNRMask(M, VT, Subtarget) ||
11432 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11433 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11434 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11435 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11439 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11441 unsigned NumElts = VT.getVectorNumElements();
11442 // FIXME: This collection of masks seems suspect.
11445 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11446 return (isMOVLMask(Mask, VT) ||
11447 isCommutedMOVLMask(Mask, VT, true) ||
11448 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11449 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11454 //===----------------------------------------------------------------------===//
11455 // X86 Scheduler Hooks
11456 //===----------------------------------------------------------------------===//
11458 // private utility function
11459 MachineBasicBlock *
11460 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11461 MachineBasicBlock *MBB,
11468 const TargetRegisterClass *RC,
11469 bool Invert) const {
11470 // For the atomic bitwise operator, we generate
11473 // ld t1 = [bitinstr.addr]
11474 // op t2 = t1, [bitinstr.val]
11475 // not t3 = t2 (if Invert)
11477 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11479 // fallthrough -->nextMBB
11480 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11481 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11482 MachineFunction::iterator MBBIter = MBB;
11485 /// First build the CFG
11486 MachineFunction *F = MBB->getParent();
11487 MachineBasicBlock *thisMBB = MBB;
11488 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11489 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11490 F->insert(MBBIter, newMBB);
11491 F->insert(MBBIter, nextMBB);
11493 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11494 nextMBB->splice(nextMBB->begin(), thisMBB,
11495 llvm::next(MachineBasicBlock::iterator(bInstr)),
11497 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11499 // Update thisMBB to fall through to newMBB
11500 thisMBB->addSuccessor(newMBB);
11502 // newMBB jumps to itself and fall through to nextMBB
11503 newMBB->addSuccessor(nextMBB);
11504 newMBB->addSuccessor(newMBB);
11506 // Insert instructions into newMBB based on incoming instruction
11507 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11508 "unexpected number of operands");
11509 DebugLoc dl = bInstr->getDebugLoc();
11510 MachineOperand& destOper = bInstr->getOperand(0);
11511 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11512 int numArgs = bInstr->getNumOperands() - 1;
11513 for (int i=0; i < numArgs; ++i)
11514 argOpers[i] = &bInstr->getOperand(i+1);
11516 // x86 address has 4 operands: base, index, scale, and displacement
11517 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11518 int valArgIndx = lastAddrIndx + 1;
11520 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11521 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11522 for (int i=0; i <= lastAddrIndx; ++i)
11523 (*MIB).addOperand(*argOpers[i]);
11525 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11526 assert((argOpers[valArgIndx]->isReg() ||
11527 argOpers[valArgIndx]->isImm()) &&
11528 "invalid operand");
11529 if (argOpers[valArgIndx]->isReg())
11530 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11532 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11534 (*MIB).addOperand(*argOpers[valArgIndx]);
11536 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11538 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11543 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11546 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11547 for (int i=0; i <= lastAddrIndx; ++i)
11548 (*MIB).addOperand(*argOpers[i]);
11550 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11551 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11552 bInstr->memoperands_end());
11554 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11555 MIB.addReg(EAXreg);
11558 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11560 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11564 // private utility function: 64 bit atomics on 32 bit host.
11565 MachineBasicBlock *
11566 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11567 MachineBasicBlock *MBB,
11572 bool Invert) const {
11573 // For the atomic bitwise operator, we generate
11574 // thisMBB (instructions are in pairs, except cmpxchg8b)
11575 // ld t1,t2 = [bitinstr.addr]
11577 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11578 // op t5, t6 <- out1, out2, [bitinstr.val]
11579 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11580 // neg t7, t8 < t5, t6 (if Invert)
11581 // mov ECX, EBX <- t5, t6
11582 // mov EAX, EDX <- t1, t2
11583 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11584 // mov t3, t4 <- EAX, EDX
11586 // result in out1, out2
11587 // fallthrough -->nextMBB
11589 const TargetRegisterClass *RC = &X86::GR32RegClass;
11590 const unsigned LoadOpc = X86::MOV32rm;
11591 const unsigned NotOpc = X86::NOT32r;
11592 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11593 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11594 MachineFunction::iterator MBBIter = MBB;
11597 /// First build the CFG
11598 MachineFunction *F = MBB->getParent();
11599 MachineBasicBlock *thisMBB = MBB;
11600 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11601 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11602 F->insert(MBBIter, newMBB);
11603 F->insert(MBBIter, nextMBB);
11605 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11606 nextMBB->splice(nextMBB->begin(), thisMBB,
11607 llvm::next(MachineBasicBlock::iterator(bInstr)),
11609 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11611 // Update thisMBB to fall through to newMBB
11612 thisMBB->addSuccessor(newMBB);
11614 // newMBB jumps to itself and fall through to nextMBB
11615 newMBB->addSuccessor(nextMBB);
11616 newMBB->addSuccessor(newMBB);
11618 DebugLoc dl = bInstr->getDebugLoc();
11619 // Insert instructions into newMBB based on incoming instruction
11620 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11621 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11622 "unexpected number of operands");
11623 MachineOperand& dest1Oper = bInstr->getOperand(0);
11624 MachineOperand& dest2Oper = bInstr->getOperand(1);
11625 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11626 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11627 argOpers[i] = &bInstr->getOperand(i+2);
11629 // We use some of the operands multiple times, so conservatively just
11630 // clear any kill flags that might be present.
11631 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11632 argOpers[i]->setIsKill(false);
11635 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11636 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11638 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11639 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11640 for (int i=0; i <= lastAddrIndx; ++i)
11641 (*MIB).addOperand(*argOpers[i]);
11642 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11643 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11644 // add 4 to displacement.
11645 for (int i=0; i <= lastAddrIndx-2; ++i)
11646 (*MIB).addOperand(*argOpers[i]);
11647 MachineOperand newOp3 = *(argOpers[3]);
11648 if (newOp3.isImm())
11649 newOp3.setImm(newOp3.getImm()+4);
11651 newOp3.setOffset(newOp3.getOffset()+4);
11652 (*MIB).addOperand(newOp3);
11653 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11655 // t3/4 are defined later, at the bottom of the loop
11656 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11657 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11658 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11659 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11660 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11661 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11663 // The subsequent operations should be using the destination registers of
11664 // the PHI instructions.
11665 t1 = dest1Oper.getReg();
11666 t2 = dest2Oper.getReg();
11668 int valArgIndx = lastAddrIndx + 1;
11669 assert((argOpers[valArgIndx]->isReg() ||
11670 argOpers[valArgIndx]->isImm()) &&
11671 "invalid operand");
11672 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11673 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11674 if (argOpers[valArgIndx]->isReg())
11675 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11677 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11678 if (regOpcL != X86::MOV32rr)
11680 (*MIB).addOperand(*argOpers[valArgIndx]);
11681 assert(argOpers[valArgIndx + 1]->isReg() ==
11682 argOpers[valArgIndx]->isReg());
11683 assert(argOpers[valArgIndx + 1]->isImm() ==
11684 argOpers[valArgIndx]->isImm());
11685 if (argOpers[valArgIndx + 1]->isReg())
11686 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11688 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11689 if (regOpcH != X86::MOV32rr)
11691 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11695 t7 = F->getRegInfo().createVirtualRegister(RC);
11696 t8 = F->getRegInfo().createVirtualRegister(RC);
11697 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11698 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11704 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11706 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11709 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11711 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11714 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11715 for (int i=0; i <= lastAddrIndx; ++i)
11716 (*MIB).addOperand(*argOpers[i]);
11718 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11719 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11720 bInstr->memoperands_end());
11722 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11723 MIB.addReg(X86::EAX);
11724 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11725 MIB.addReg(X86::EDX);
11728 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11730 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11734 // private utility function
11735 MachineBasicBlock *
11736 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11737 MachineBasicBlock *MBB,
11738 unsigned cmovOpc) const {
11739 // For the atomic min/max operator, we generate
11742 // ld t1 = [min/max.addr]
11743 // mov t2 = [min/max.val]
11745 // cmov[cond] t2 = t1
11747 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11749 // fallthrough -->nextMBB
11751 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11752 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11753 MachineFunction::iterator MBBIter = MBB;
11756 /// First build the CFG
11757 MachineFunction *F = MBB->getParent();
11758 MachineBasicBlock *thisMBB = MBB;
11759 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11760 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11761 F->insert(MBBIter, newMBB);
11762 F->insert(MBBIter, nextMBB);
11764 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11765 nextMBB->splice(nextMBB->begin(), thisMBB,
11766 llvm::next(MachineBasicBlock::iterator(mInstr)),
11768 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11770 // Update thisMBB to fall through to newMBB
11771 thisMBB->addSuccessor(newMBB);
11773 // newMBB jumps to newMBB and fall through to nextMBB
11774 newMBB->addSuccessor(nextMBB);
11775 newMBB->addSuccessor(newMBB);
11777 DebugLoc dl = mInstr->getDebugLoc();
11778 // Insert instructions into newMBB based on incoming instruction
11779 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11780 "unexpected number of operands");
11781 MachineOperand& destOper = mInstr->getOperand(0);
11782 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11783 int numArgs = mInstr->getNumOperands() - 1;
11784 for (int i=0; i < numArgs; ++i)
11785 argOpers[i] = &mInstr->getOperand(i+1);
11787 // x86 address has 4 operands: base, index, scale, and displacement
11788 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11789 int valArgIndx = lastAddrIndx + 1;
11791 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11792 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11793 for (int i=0; i <= lastAddrIndx; ++i)
11794 (*MIB).addOperand(*argOpers[i]);
11796 // We only support register and immediate values
11797 assert((argOpers[valArgIndx]->isReg() ||
11798 argOpers[valArgIndx]->isImm()) &&
11799 "invalid operand");
11801 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11802 if (argOpers[valArgIndx]->isReg())
11803 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11805 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11806 (*MIB).addOperand(*argOpers[valArgIndx]);
11808 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11811 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11816 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11817 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11821 // Cmp and exchange if none has modified the memory location
11822 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11823 for (int i=0; i <= lastAddrIndx; ++i)
11824 (*MIB).addOperand(*argOpers[i]);
11826 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11827 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11828 mInstr->memoperands_end());
11830 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11831 MIB.addReg(X86::EAX);
11834 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11836 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11840 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11841 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11842 // in the .td file.
11843 MachineBasicBlock *
11844 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11845 unsigned numArgs, bool memArg) const {
11846 assert(Subtarget->hasSSE42() &&
11847 "Target must have SSE4.2 or AVX features enabled");
11849 DebugLoc dl = MI->getDebugLoc();
11850 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11852 if (!Subtarget->hasAVX()) {
11854 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11856 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11859 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11861 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11864 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11865 for (unsigned i = 0; i < numArgs; ++i) {
11866 MachineOperand &Op = MI->getOperand(i+1);
11867 if (!(Op.isReg() && Op.isImplicit()))
11868 MIB.addOperand(Op);
11870 BuildMI(*BB, MI, dl,
11871 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11872 MI->getOperand(0).getReg())
11873 .addReg(X86::XMM0);
11875 MI->eraseFromParent();
11879 MachineBasicBlock *
11880 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11881 DebugLoc dl = MI->getDebugLoc();
11882 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11884 // Address into RAX/EAX, other two args into ECX, EDX.
11885 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11886 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11887 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11888 for (int i = 0; i < X86::AddrNumOperands; ++i)
11889 MIB.addOperand(MI->getOperand(i));
11891 unsigned ValOps = X86::AddrNumOperands;
11892 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11893 .addReg(MI->getOperand(ValOps).getReg());
11894 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11895 .addReg(MI->getOperand(ValOps+1).getReg());
11897 // The instruction doesn't actually take any operands though.
11898 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11900 MI->eraseFromParent(); // The pseudo is gone now.
11904 MachineBasicBlock *
11905 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11906 DebugLoc dl = MI->getDebugLoc();
11907 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11909 // First arg in ECX, the second in EAX.
11910 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11911 .addReg(MI->getOperand(0).getReg());
11912 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11913 .addReg(MI->getOperand(1).getReg());
11915 // The instruction doesn't actually take any operands though.
11916 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11918 MI->eraseFromParent(); // The pseudo is gone now.
11922 MachineBasicBlock *
11923 X86TargetLowering::EmitVAARG64WithCustomInserter(
11925 MachineBasicBlock *MBB) const {
11926 // Emit va_arg instruction on X86-64.
11928 // Operands to this pseudo-instruction:
11929 // 0 ) Output : destination address (reg)
11930 // 1-5) Input : va_list address (addr, i64mem)
11931 // 6 ) ArgSize : Size (in bytes) of vararg type
11932 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11933 // 8 ) Align : Alignment of type
11934 // 9 ) EFLAGS (implicit-def)
11936 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11937 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11939 unsigned DestReg = MI->getOperand(0).getReg();
11940 MachineOperand &Base = MI->getOperand(1);
11941 MachineOperand &Scale = MI->getOperand(2);
11942 MachineOperand &Index = MI->getOperand(3);
11943 MachineOperand &Disp = MI->getOperand(4);
11944 MachineOperand &Segment = MI->getOperand(5);
11945 unsigned ArgSize = MI->getOperand(6).getImm();
11946 unsigned ArgMode = MI->getOperand(7).getImm();
11947 unsigned Align = MI->getOperand(8).getImm();
11949 // Memory Reference
11950 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11951 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11952 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11954 // Machine Information
11955 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11956 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11957 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11958 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11959 DebugLoc DL = MI->getDebugLoc();
11961 // struct va_list {
11964 // i64 overflow_area (address)
11965 // i64 reg_save_area (address)
11967 // sizeof(va_list) = 24
11968 // alignment(va_list) = 8
11970 unsigned TotalNumIntRegs = 6;
11971 unsigned TotalNumXMMRegs = 8;
11972 bool UseGPOffset = (ArgMode == 1);
11973 bool UseFPOffset = (ArgMode == 2);
11974 unsigned MaxOffset = TotalNumIntRegs * 8 +
11975 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11977 /* Align ArgSize to a multiple of 8 */
11978 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11979 bool NeedsAlign = (Align > 8);
11981 MachineBasicBlock *thisMBB = MBB;
11982 MachineBasicBlock *overflowMBB;
11983 MachineBasicBlock *offsetMBB;
11984 MachineBasicBlock *endMBB;
11986 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11987 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11988 unsigned OffsetReg = 0;
11990 if (!UseGPOffset && !UseFPOffset) {
11991 // If we only pull from the overflow region, we don't create a branch.
11992 // We don't need to alter control flow.
11993 OffsetDestReg = 0; // unused
11994 OverflowDestReg = DestReg;
11997 overflowMBB = thisMBB;
12000 // First emit code to check if gp_offset (or fp_offset) is below the bound.
12001 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
12002 // If not, pull from overflow_area. (branch to overflowMBB)
12007 // offsetMBB overflowMBB
12012 // Registers for the PHI in endMBB
12013 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
12014 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
12016 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12017 MachineFunction *MF = MBB->getParent();
12018 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12019 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12020 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12022 MachineFunction::iterator MBBIter = MBB;
12025 // Insert the new basic blocks
12026 MF->insert(MBBIter, offsetMBB);
12027 MF->insert(MBBIter, overflowMBB);
12028 MF->insert(MBBIter, endMBB);
12030 // Transfer the remainder of MBB and its successor edges to endMBB.
12031 endMBB->splice(endMBB->begin(), thisMBB,
12032 llvm::next(MachineBasicBlock::iterator(MI)),
12034 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
12036 // Make offsetMBB and overflowMBB successors of thisMBB
12037 thisMBB->addSuccessor(offsetMBB);
12038 thisMBB->addSuccessor(overflowMBB);
12040 // endMBB is a successor of both offsetMBB and overflowMBB
12041 offsetMBB->addSuccessor(endMBB);
12042 overflowMBB->addSuccessor(endMBB);
12044 // Load the offset value into a register
12045 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12046 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12050 .addDisp(Disp, UseFPOffset ? 4 : 0)
12051 .addOperand(Segment)
12052 .setMemRefs(MMOBegin, MMOEnd);
12054 // Check if there is enough room left to pull this argument.
12055 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12057 .addImm(MaxOffset + 8 - ArgSizeA8);
12059 // Branch to "overflowMBB" if offset >= max
12060 // Fall through to "offsetMBB" otherwise
12061 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12062 .addMBB(overflowMBB);
12065 // In offsetMBB, emit code to use the reg_save_area.
12067 assert(OffsetReg != 0);
12069 // Read the reg_save_area address.
12070 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12071 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12076 .addOperand(Segment)
12077 .setMemRefs(MMOBegin, MMOEnd);
12079 // Zero-extend the offset
12080 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12081 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12084 .addImm(X86::sub_32bit);
12086 // Add the offset to the reg_save_area to get the final address.
12087 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12088 .addReg(OffsetReg64)
12089 .addReg(RegSaveReg);
12091 // Compute the offset for the next argument
12092 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12093 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12095 .addImm(UseFPOffset ? 16 : 8);
12097 // Store it back into the va_list.
12098 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12102 .addDisp(Disp, UseFPOffset ? 4 : 0)
12103 .addOperand(Segment)
12104 .addReg(NextOffsetReg)
12105 .setMemRefs(MMOBegin, MMOEnd);
12108 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12113 // Emit code to use overflow area
12116 // Load the overflow_area address into a register.
12117 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12118 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12123 .addOperand(Segment)
12124 .setMemRefs(MMOBegin, MMOEnd);
12126 // If we need to align it, do so. Otherwise, just copy the address
12127 // to OverflowDestReg.
12129 // Align the overflow address
12130 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12131 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12133 // aligned_addr = (addr + (align-1)) & ~(align-1)
12134 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12135 .addReg(OverflowAddrReg)
12138 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12140 .addImm(~(uint64_t)(Align-1));
12142 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12143 .addReg(OverflowAddrReg);
12146 // Compute the next overflow address after this argument.
12147 // (the overflow address should be kept 8-byte aligned)
12148 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12149 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12150 .addReg(OverflowDestReg)
12151 .addImm(ArgSizeA8);
12153 // Store the new overflow address.
12154 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12159 .addOperand(Segment)
12160 .addReg(NextAddrReg)
12161 .setMemRefs(MMOBegin, MMOEnd);
12163 // If we branched, emit the PHI to the front of endMBB.
12165 BuildMI(*endMBB, endMBB->begin(), DL,
12166 TII->get(X86::PHI), DestReg)
12167 .addReg(OffsetDestReg).addMBB(offsetMBB)
12168 .addReg(OverflowDestReg).addMBB(overflowMBB);
12171 // Erase the pseudo instruction
12172 MI->eraseFromParent();
12177 MachineBasicBlock *
12178 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12180 MachineBasicBlock *MBB) const {
12181 // Emit code to save XMM registers to the stack. The ABI says that the
12182 // number of registers to save is given in %al, so it's theoretically
12183 // possible to do an indirect jump trick to avoid saving all of them,
12184 // however this code takes a simpler approach and just executes all
12185 // of the stores if %al is non-zero. It's less code, and it's probably
12186 // easier on the hardware branch predictor, and stores aren't all that
12187 // expensive anyway.
12189 // Create the new basic blocks. One block contains all the XMM stores,
12190 // and one block is the final destination regardless of whether any
12191 // stores were performed.
12192 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12193 MachineFunction *F = MBB->getParent();
12194 MachineFunction::iterator MBBIter = MBB;
12196 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12197 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12198 F->insert(MBBIter, XMMSaveMBB);
12199 F->insert(MBBIter, EndMBB);
12201 // Transfer the remainder of MBB and its successor edges to EndMBB.
12202 EndMBB->splice(EndMBB->begin(), MBB,
12203 llvm::next(MachineBasicBlock::iterator(MI)),
12205 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12207 // The original block will now fall through to the XMM save block.
12208 MBB->addSuccessor(XMMSaveMBB);
12209 // The XMMSaveMBB will fall through to the end block.
12210 XMMSaveMBB->addSuccessor(EndMBB);
12212 // Now add the instructions.
12213 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12214 DebugLoc DL = MI->getDebugLoc();
12216 unsigned CountReg = MI->getOperand(0).getReg();
12217 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12218 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12220 if (!Subtarget->isTargetWin64()) {
12221 // If %al is 0, branch around the XMM save block.
12222 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12223 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12224 MBB->addSuccessor(EndMBB);
12227 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12228 // In the XMM save block, save all the XMM argument registers.
12229 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12230 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12231 MachineMemOperand *MMO =
12232 F->getMachineMemOperand(
12233 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12234 MachineMemOperand::MOStore,
12235 /*Size=*/16, /*Align=*/16);
12236 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12237 .addFrameIndex(RegSaveFrameIndex)
12238 .addImm(/*Scale=*/1)
12239 .addReg(/*IndexReg=*/0)
12240 .addImm(/*Disp=*/Offset)
12241 .addReg(/*Segment=*/0)
12242 .addReg(MI->getOperand(i).getReg())
12243 .addMemOperand(MMO);
12246 MI->eraseFromParent(); // The pseudo instruction is gone now.
12251 // The EFLAGS operand of SelectItr might be missing a kill marker
12252 // because there were multiple uses of EFLAGS, and ISel didn't know
12253 // which to mark. Figure out whether SelectItr should have had a
12254 // kill marker, and set it if it should. Returns the correct kill
12256 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12257 MachineBasicBlock* BB,
12258 const TargetRegisterInfo* TRI) {
12259 // Scan forward through BB for a use/def of EFLAGS.
12260 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12261 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12262 const MachineInstr& mi = *miI;
12263 if (mi.readsRegister(X86::EFLAGS))
12265 if (mi.definesRegister(X86::EFLAGS))
12266 break; // Should have kill-flag - update below.
12269 // If we hit the end of the block, check whether EFLAGS is live into a
12271 if (miI == BB->end()) {
12272 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12273 sEnd = BB->succ_end();
12274 sItr != sEnd; ++sItr) {
12275 MachineBasicBlock* succ = *sItr;
12276 if (succ->isLiveIn(X86::EFLAGS))
12281 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12282 // out. SelectMI should have a kill flag on EFLAGS.
12283 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12287 MachineBasicBlock *
12288 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12289 MachineBasicBlock *BB) const {
12290 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12291 DebugLoc DL = MI->getDebugLoc();
12293 // To "insert" a SELECT_CC instruction, we actually have to insert the
12294 // diamond control-flow pattern. The incoming instruction knows the
12295 // destination vreg to set, the condition code register to branch on, the
12296 // true/false values to select between, and a branch opcode to use.
12297 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12298 MachineFunction::iterator It = BB;
12304 // cmpTY ccX, r1, r2
12306 // fallthrough --> copy0MBB
12307 MachineBasicBlock *thisMBB = BB;
12308 MachineFunction *F = BB->getParent();
12309 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12310 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12311 F->insert(It, copy0MBB);
12312 F->insert(It, sinkMBB);
12314 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12315 // live into the sink and copy blocks.
12316 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12317 if (!MI->killsRegister(X86::EFLAGS) &&
12318 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12319 copy0MBB->addLiveIn(X86::EFLAGS);
12320 sinkMBB->addLiveIn(X86::EFLAGS);
12323 // Transfer the remainder of BB and its successor edges to sinkMBB.
12324 sinkMBB->splice(sinkMBB->begin(), BB,
12325 llvm::next(MachineBasicBlock::iterator(MI)),
12327 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12329 // Add the true and fallthrough blocks as its successors.
12330 BB->addSuccessor(copy0MBB);
12331 BB->addSuccessor(sinkMBB);
12333 // Create the conditional branch instruction.
12335 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12336 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12339 // %FalseValue = ...
12340 // # fallthrough to sinkMBB
12341 copy0MBB->addSuccessor(sinkMBB);
12344 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12346 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12347 TII->get(X86::PHI), MI->getOperand(0).getReg())
12348 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12349 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12351 MI->eraseFromParent(); // The pseudo instruction is gone now.
12355 MachineBasicBlock *
12356 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12357 bool Is64Bit) const {
12358 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12359 DebugLoc DL = MI->getDebugLoc();
12360 MachineFunction *MF = BB->getParent();
12361 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12363 assert(getTargetMachine().Options.EnableSegmentedStacks);
12365 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12366 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12369 // ... [Till the alloca]
12370 // If stacklet is not large enough, jump to mallocMBB
12373 // Allocate by subtracting from RSP
12374 // Jump to continueMBB
12377 // Allocate by call to runtime
12381 // [rest of original BB]
12384 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12385 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12386 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12388 MachineRegisterInfo &MRI = MF->getRegInfo();
12389 const TargetRegisterClass *AddrRegClass =
12390 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12392 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12393 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12394 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12395 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12396 sizeVReg = MI->getOperand(1).getReg(),
12397 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12399 MachineFunction::iterator MBBIter = BB;
12402 MF->insert(MBBIter, bumpMBB);
12403 MF->insert(MBBIter, mallocMBB);
12404 MF->insert(MBBIter, continueMBB);
12406 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12407 (MachineBasicBlock::iterator(MI)), BB->end());
12408 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12410 // Add code to the main basic block to check if the stack limit has been hit,
12411 // and if so, jump to mallocMBB otherwise to bumpMBB.
12412 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12413 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12414 .addReg(tmpSPVReg).addReg(sizeVReg);
12415 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12416 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12417 .addReg(SPLimitVReg);
12418 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12420 // bumpMBB simply decreases the stack pointer, since we know the current
12421 // stacklet has enough space.
12422 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12423 .addReg(SPLimitVReg);
12424 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12425 .addReg(SPLimitVReg);
12426 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12428 // Calls into a routine in libgcc to allocate more space from the heap.
12429 const uint32_t *RegMask =
12430 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12432 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12434 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12435 .addExternalSymbol("__morestack_allocate_stack_space")
12436 .addRegMask(RegMask)
12437 .addReg(X86::RDI, RegState::Implicit)
12438 .addReg(X86::RAX, RegState::ImplicitDefine);
12440 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12442 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12443 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12444 .addExternalSymbol("__morestack_allocate_stack_space")
12445 .addRegMask(RegMask)
12446 .addReg(X86::EAX, RegState::ImplicitDefine);
12450 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12453 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12454 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12455 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12457 // Set up the CFG correctly.
12458 BB->addSuccessor(bumpMBB);
12459 BB->addSuccessor(mallocMBB);
12460 mallocMBB->addSuccessor(continueMBB);
12461 bumpMBB->addSuccessor(continueMBB);
12463 // Take care of the PHI nodes.
12464 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12465 MI->getOperand(0).getReg())
12466 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12467 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12469 // Delete the original pseudo instruction.
12470 MI->eraseFromParent();
12473 return continueMBB;
12476 MachineBasicBlock *
12477 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12478 MachineBasicBlock *BB) const {
12479 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12480 DebugLoc DL = MI->getDebugLoc();
12482 assert(!Subtarget->isTargetEnvMacho());
12484 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12485 // non-trivial part is impdef of ESP.
12487 if (Subtarget->isTargetWin64()) {
12488 if (Subtarget->isTargetCygMing()) {
12489 // ___chkstk(Mingw64):
12490 // Clobbers R10, R11, RAX and EFLAGS.
12492 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12493 .addExternalSymbol("___chkstk")
12494 .addReg(X86::RAX, RegState::Implicit)
12495 .addReg(X86::RSP, RegState::Implicit)
12496 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12497 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12498 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12500 // __chkstk(MSVCRT): does not update stack pointer.
12501 // Clobbers R10, R11 and EFLAGS.
12502 // FIXME: RAX(allocated size) might be reused and not killed.
12503 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12504 .addExternalSymbol("__chkstk")
12505 .addReg(X86::RAX, RegState::Implicit)
12506 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12507 // RAX has the offset to subtracted from RSP.
12508 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12513 const char *StackProbeSymbol =
12514 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12516 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12517 .addExternalSymbol(StackProbeSymbol)
12518 .addReg(X86::EAX, RegState::Implicit)
12519 .addReg(X86::ESP, RegState::Implicit)
12520 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12521 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12522 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12525 MI->eraseFromParent(); // The pseudo instruction is gone now.
12529 MachineBasicBlock *
12530 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12531 MachineBasicBlock *BB) const {
12532 // This is pretty easy. We're taking the value that we received from
12533 // our load from the relocation, sticking it in either RDI (x86-64)
12534 // or EAX and doing an indirect call. The return value will then
12535 // be in the normal return register.
12536 const X86InstrInfo *TII
12537 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12538 DebugLoc DL = MI->getDebugLoc();
12539 MachineFunction *F = BB->getParent();
12541 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12542 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12544 // Get a register mask for the lowered call.
12545 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12546 // proper register mask.
12547 const uint32_t *RegMask =
12548 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12549 if (Subtarget->is64Bit()) {
12550 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12551 TII->get(X86::MOV64rm), X86::RDI)
12553 .addImm(0).addReg(0)
12554 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12555 MI->getOperand(3).getTargetFlags())
12557 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12558 addDirectMem(MIB, X86::RDI);
12559 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12560 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12561 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12562 TII->get(X86::MOV32rm), X86::EAX)
12564 .addImm(0).addReg(0)
12565 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12566 MI->getOperand(3).getTargetFlags())
12568 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12569 addDirectMem(MIB, X86::EAX);
12570 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12572 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12573 TII->get(X86::MOV32rm), X86::EAX)
12574 .addReg(TII->getGlobalBaseReg(F))
12575 .addImm(0).addReg(0)
12576 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12577 MI->getOperand(3).getTargetFlags())
12579 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12580 addDirectMem(MIB, X86::EAX);
12581 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12584 MI->eraseFromParent(); // The pseudo instruction is gone now.
12588 MachineBasicBlock *
12589 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12590 MachineBasicBlock *BB) const {
12591 switch (MI->getOpcode()) {
12592 default: llvm_unreachable("Unexpected instr type to insert");
12593 case X86::TAILJMPd64:
12594 case X86::TAILJMPr64:
12595 case X86::TAILJMPm64:
12596 llvm_unreachable("TAILJMP64 would not be touched here.");
12597 case X86::TCRETURNdi64:
12598 case X86::TCRETURNri64:
12599 case X86::TCRETURNmi64:
12601 case X86::WIN_ALLOCA:
12602 return EmitLoweredWinAlloca(MI, BB);
12603 case X86::SEG_ALLOCA_32:
12604 return EmitLoweredSegAlloca(MI, BB, false);
12605 case X86::SEG_ALLOCA_64:
12606 return EmitLoweredSegAlloca(MI, BB, true);
12607 case X86::TLSCall_32:
12608 case X86::TLSCall_64:
12609 return EmitLoweredTLSCall(MI, BB);
12610 case X86::CMOV_GR8:
12611 case X86::CMOV_FR32:
12612 case X86::CMOV_FR64:
12613 case X86::CMOV_V4F32:
12614 case X86::CMOV_V2F64:
12615 case X86::CMOV_V2I64:
12616 case X86::CMOV_V8F32:
12617 case X86::CMOV_V4F64:
12618 case X86::CMOV_V4I64:
12619 case X86::CMOV_GR16:
12620 case X86::CMOV_GR32:
12621 case X86::CMOV_RFP32:
12622 case X86::CMOV_RFP64:
12623 case X86::CMOV_RFP80:
12624 return EmitLoweredSelect(MI, BB);
12626 case X86::FP32_TO_INT16_IN_MEM:
12627 case X86::FP32_TO_INT32_IN_MEM:
12628 case X86::FP32_TO_INT64_IN_MEM:
12629 case X86::FP64_TO_INT16_IN_MEM:
12630 case X86::FP64_TO_INT32_IN_MEM:
12631 case X86::FP64_TO_INT64_IN_MEM:
12632 case X86::FP80_TO_INT16_IN_MEM:
12633 case X86::FP80_TO_INT32_IN_MEM:
12634 case X86::FP80_TO_INT64_IN_MEM: {
12635 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12636 DebugLoc DL = MI->getDebugLoc();
12638 // Change the floating point control register to use "round towards zero"
12639 // mode when truncating to an integer value.
12640 MachineFunction *F = BB->getParent();
12641 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12642 addFrameReference(BuildMI(*BB, MI, DL,
12643 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12645 // Load the old value of the high byte of the control word...
12647 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12648 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12651 // Set the high part to be round to zero...
12652 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12655 // Reload the modified control word now...
12656 addFrameReference(BuildMI(*BB, MI, DL,
12657 TII->get(X86::FLDCW16m)), CWFrameIdx);
12659 // Restore the memory image of control word to original value
12660 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12663 // Get the X86 opcode to use.
12665 switch (MI->getOpcode()) {
12666 default: llvm_unreachable("illegal opcode!");
12667 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12668 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12669 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12670 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12671 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12672 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12673 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12674 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12675 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12679 MachineOperand &Op = MI->getOperand(0);
12681 AM.BaseType = X86AddressMode::RegBase;
12682 AM.Base.Reg = Op.getReg();
12684 AM.BaseType = X86AddressMode::FrameIndexBase;
12685 AM.Base.FrameIndex = Op.getIndex();
12687 Op = MI->getOperand(1);
12689 AM.Scale = Op.getImm();
12690 Op = MI->getOperand(2);
12692 AM.IndexReg = Op.getImm();
12693 Op = MI->getOperand(3);
12694 if (Op.isGlobal()) {
12695 AM.GV = Op.getGlobal();
12697 AM.Disp = Op.getImm();
12699 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12700 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12702 // Reload the original control word now.
12703 addFrameReference(BuildMI(*BB, MI, DL,
12704 TII->get(X86::FLDCW16m)), CWFrameIdx);
12706 MI->eraseFromParent(); // The pseudo instruction is gone now.
12709 // String/text processing lowering.
12710 case X86::PCMPISTRM128REG:
12711 case X86::VPCMPISTRM128REG:
12712 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12713 case X86::PCMPISTRM128MEM:
12714 case X86::VPCMPISTRM128MEM:
12715 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12716 case X86::PCMPESTRM128REG:
12717 case X86::VPCMPESTRM128REG:
12718 return EmitPCMP(MI, BB, 5, false /* in mem */);
12719 case X86::PCMPESTRM128MEM:
12720 case X86::VPCMPESTRM128MEM:
12721 return EmitPCMP(MI, BB, 5, true /* in mem */);
12723 // Thread synchronization.
12725 return EmitMonitor(MI, BB);
12727 return EmitMwait(MI, BB);
12729 // Atomic Lowering.
12730 case X86::ATOMAND32:
12731 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12732 X86::AND32ri, X86::MOV32rm,
12734 X86::NOT32r, X86::EAX,
12735 &X86::GR32RegClass);
12736 case X86::ATOMOR32:
12737 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12738 X86::OR32ri, X86::MOV32rm,
12740 X86::NOT32r, X86::EAX,
12741 &X86::GR32RegClass);
12742 case X86::ATOMXOR32:
12743 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12744 X86::XOR32ri, X86::MOV32rm,
12746 X86::NOT32r, X86::EAX,
12747 &X86::GR32RegClass);
12748 case X86::ATOMNAND32:
12749 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12750 X86::AND32ri, X86::MOV32rm,
12752 X86::NOT32r, X86::EAX,
12753 &X86::GR32RegClass, true);
12754 case X86::ATOMMIN32:
12755 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12756 case X86::ATOMMAX32:
12757 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12758 case X86::ATOMUMIN32:
12759 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12760 case X86::ATOMUMAX32:
12761 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12763 case X86::ATOMAND16:
12764 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12765 X86::AND16ri, X86::MOV16rm,
12767 X86::NOT16r, X86::AX,
12768 &X86::GR16RegClass);
12769 case X86::ATOMOR16:
12770 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12771 X86::OR16ri, X86::MOV16rm,
12773 X86::NOT16r, X86::AX,
12774 &X86::GR16RegClass);
12775 case X86::ATOMXOR16:
12776 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12777 X86::XOR16ri, X86::MOV16rm,
12779 X86::NOT16r, X86::AX,
12780 &X86::GR16RegClass);
12781 case X86::ATOMNAND16:
12782 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12783 X86::AND16ri, X86::MOV16rm,
12785 X86::NOT16r, X86::AX,
12786 &X86::GR16RegClass, true);
12787 case X86::ATOMMIN16:
12788 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12789 case X86::ATOMMAX16:
12790 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12791 case X86::ATOMUMIN16:
12792 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12793 case X86::ATOMUMAX16:
12794 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12796 case X86::ATOMAND8:
12797 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12798 X86::AND8ri, X86::MOV8rm,
12800 X86::NOT8r, X86::AL,
12801 &X86::GR8RegClass);
12803 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12804 X86::OR8ri, X86::MOV8rm,
12806 X86::NOT8r, X86::AL,
12807 &X86::GR8RegClass);
12808 case X86::ATOMXOR8:
12809 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12810 X86::XOR8ri, X86::MOV8rm,
12812 X86::NOT8r, X86::AL,
12813 &X86::GR8RegClass);
12814 case X86::ATOMNAND8:
12815 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12816 X86::AND8ri, X86::MOV8rm,
12818 X86::NOT8r, X86::AL,
12819 &X86::GR8RegClass, true);
12820 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12821 // This group is for 64-bit host.
12822 case X86::ATOMAND64:
12823 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12824 X86::AND64ri32, X86::MOV64rm,
12826 X86::NOT64r, X86::RAX,
12827 &X86::GR64RegClass);
12828 case X86::ATOMOR64:
12829 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12830 X86::OR64ri32, X86::MOV64rm,
12832 X86::NOT64r, X86::RAX,
12833 &X86::GR64RegClass);
12834 case X86::ATOMXOR64:
12835 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12836 X86::XOR64ri32, X86::MOV64rm,
12838 X86::NOT64r, X86::RAX,
12839 &X86::GR64RegClass);
12840 case X86::ATOMNAND64:
12841 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12842 X86::AND64ri32, X86::MOV64rm,
12844 X86::NOT64r, X86::RAX,
12845 &X86::GR64RegClass, true);
12846 case X86::ATOMMIN64:
12847 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12848 case X86::ATOMMAX64:
12849 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12850 case X86::ATOMUMIN64:
12851 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12852 case X86::ATOMUMAX64:
12853 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12855 // This group does 64-bit operations on a 32-bit host.
12856 case X86::ATOMAND6432:
12857 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12858 X86::AND32rr, X86::AND32rr,
12859 X86::AND32ri, X86::AND32ri,
12861 case X86::ATOMOR6432:
12862 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12863 X86::OR32rr, X86::OR32rr,
12864 X86::OR32ri, X86::OR32ri,
12866 case X86::ATOMXOR6432:
12867 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12868 X86::XOR32rr, X86::XOR32rr,
12869 X86::XOR32ri, X86::XOR32ri,
12871 case X86::ATOMNAND6432:
12872 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12873 X86::AND32rr, X86::AND32rr,
12874 X86::AND32ri, X86::AND32ri,
12876 case X86::ATOMADD6432:
12877 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12878 X86::ADD32rr, X86::ADC32rr,
12879 X86::ADD32ri, X86::ADC32ri,
12881 case X86::ATOMSUB6432:
12882 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12883 X86::SUB32rr, X86::SBB32rr,
12884 X86::SUB32ri, X86::SBB32ri,
12886 case X86::ATOMSWAP6432:
12887 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12888 X86::MOV32rr, X86::MOV32rr,
12889 X86::MOV32ri, X86::MOV32ri,
12891 case X86::VASTART_SAVE_XMM_REGS:
12892 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12894 case X86::VAARG_64:
12895 return EmitVAARG64WithCustomInserter(MI, BB);
12899 //===----------------------------------------------------------------------===//
12900 // X86 Optimization Hooks
12901 //===----------------------------------------------------------------------===//
12903 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12906 const SelectionDAG &DAG,
12907 unsigned Depth) const {
12908 unsigned BitWidth = KnownZero.getBitWidth();
12909 unsigned Opc = Op.getOpcode();
12910 assert((Opc >= ISD::BUILTIN_OP_END ||
12911 Opc == ISD::INTRINSIC_WO_CHAIN ||
12912 Opc == ISD::INTRINSIC_W_CHAIN ||
12913 Opc == ISD::INTRINSIC_VOID) &&
12914 "Should use MaskedValueIsZero if you don't know whether Op"
12915 " is a target node!");
12917 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12931 // These nodes' second result is a boolean.
12932 if (Op.getResNo() == 0)
12935 case X86ISD::SETCC:
12936 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12938 case ISD::INTRINSIC_WO_CHAIN: {
12939 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12940 unsigned NumLoBits = 0;
12943 case Intrinsic::x86_sse_movmsk_ps:
12944 case Intrinsic::x86_avx_movmsk_ps_256:
12945 case Intrinsic::x86_sse2_movmsk_pd:
12946 case Intrinsic::x86_avx_movmsk_pd_256:
12947 case Intrinsic::x86_mmx_pmovmskb:
12948 case Intrinsic::x86_sse2_pmovmskb_128:
12949 case Intrinsic::x86_avx2_pmovmskb: {
12950 // High bits of movmskp{s|d}, pmovmskb are known zero.
12952 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12953 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12954 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12955 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12956 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12957 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12958 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12959 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12961 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12970 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12971 unsigned Depth) const {
12972 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12973 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12974 return Op.getValueType().getScalarType().getSizeInBits();
12980 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12981 /// node is a GlobalAddress + offset.
12982 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12983 const GlobalValue* &GA,
12984 int64_t &Offset) const {
12985 if (N->getOpcode() == X86ISD::Wrapper) {
12986 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12987 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12988 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12992 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12995 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12996 /// same as extracting the high 128-bit part of 256-bit vector and then
12997 /// inserting the result into the low part of a new 256-bit vector
12998 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12999 EVT VT = SVOp->getValueType(0);
13000 unsigned NumElems = VT.getVectorNumElements();
13002 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13003 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
13004 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13005 SVOp->getMaskElt(j) >= 0)
13011 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
13012 /// same as extracting the low 128-bit part of 256-bit vector and then
13013 /// inserting the result into the high part of a new 256-bit vector
13014 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
13015 EVT VT = SVOp->getValueType(0);
13016 unsigned NumElems = VT.getVectorNumElements();
13018 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13019 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
13020 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
13021 SVOp->getMaskElt(j) >= 0)
13027 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
13028 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
13029 TargetLowering::DAGCombinerInfo &DCI,
13030 const X86Subtarget* Subtarget) {
13031 DebugLoc dl = N->getDebugLoc();
13032 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
13033 SDValue V1 = SVOp->getOperand(0);
13034 SDValue V2 = SVOp->getOperand(1);
13035 EVT VT = SVOp->getValueType(0);
13036 unsigned NumElems = VT.getVectorNumElements();
13038 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
13039 V2.getOpcode() == ISD::CONCAT_VECTORS) {
13043 // V UNDEF BUILD_VECTOR UNDEF
13045 // CONCAT_VECTOR CONCAT_VECTOR
13048 // RESULT: V + zero extended
13050 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13051 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13052 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13055 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13058 // To match the shuffle mask, the first half of the mask should
13059 // be exactly the first vector, and all the rest a splat with the
13060 // first element of the second one.
13061 for (unsigned i = 0; i != NumElems/2; ++i)
13062 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13063 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13066 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13067 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13068 if (Ld->hasNUsesOfValue(1, 0)) {
13069 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13070 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13072 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13074 Ld->getPointerInfo(),
13075 Ld->getAlignment(),
13076 false/*isVolatile*/, true/*ReadMem*/,
13077 false/*WriteMem*/);
13078 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13082 // Emit a zeroed vector and insert the desired subvector on its
13084 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13085 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13086 return DCI.CombineTo(N, InsV);
13089 //===--------------------------------------------------------------------===//
13090 // Combine some shuffles into subvector extracts and inserts:
13093 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13094 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13095 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13096 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13097 return DCI.CombineTo(N, InsV);
13100 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13101 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13102 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13103 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13104 return DCI.CombineTo(N, InsV);
13110 /// PerformShuffleCombine - Performs several different shuffle combines.
13111 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13112 TargetLowering::DAGCombinerInfo &DCI,
13113 const X86Subtarget *Subtarget) {
13114 DebugLoc dl = N->getDebugLoc();
13115 EVT VT = N->getValueType(0);
13117 // Don't create instructions with illegal types after legalize types has run.
13118 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13119 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13122 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13123 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13124 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13125 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13127 // Only handle 128 wide vector from here on.
13128 if (VT.getSizeInBits() != 128)
13131 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13132 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13133 // consecutive, non-overlapping, and in the right order.
13134 SmallVector<SDValue, 16> Elts;
13135 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13136 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13138 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13142 /// DCI, PerformTruncateCombine - Converts truncate operation to
13143 /// a sequence of vector shuffle operations.
13144 /// It is possible when we truncate 256-bit vector to 128-bit vector
13146 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13147 DAGCombinerInfo &DCI) const {
13148 if (!DCI.isBeforeLegalizeOps())
13151 if (!Subtarget->hasAVX())
13154 EVT VT = N->getValueType(0);
13155 SDValue Op = N->getOperand(0);
13156 EVT OpVT = Op.getValueType();
13157 DebugLoc dl = N->getDebugLoc();
13159 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13161 if (Subtarget->hasAVX2()) {
13162 // AVX2: v4i64 -> v4i32
13165 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13167 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13168 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13171 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13172 DAG.getIntPtrConstant(0));
13175 // AVX: v4i64 -> v4i32
13176 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13177 DAG.getIntPtrConstant(0));
13179 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13180 DAG.getIntPtrConstant(2));
13182 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13183 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13186 static const int ShufMask1[] = {0, 2, 0, 0};
13188 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13189 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13192 static const int ShufMask2[] = {0, 1, 4, 5};
13194 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13197 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13199 if (Subtarget->hasAVX2()) {
13200 // AVX2: v8i32 -> v8i16
13202 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13205 SmallVector<SDValue,32> pshufbMask;
13206 for (unsigned i = 0; i < 2; ++i) {
13207 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13208 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13209 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13210 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13211 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13212 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13213 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13214 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13215 for (unsigned j = 0; j < 8; ++j)
13216 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13218 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13219 &pshufbMask[0], 32);
13220 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13222 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13224 static const int ShufMask[] = {0, 2, -1, -1};
13225 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13228 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13229 DAG.getIntPtrConstant(0));
13231 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13234 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13235 DAG.getIntPtrConstant(0));
13237 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13238 DAG.getIntPtrConstant(4));
13240 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13241 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13244 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13245 -1, -1, -1, -1, -1, -1, -1, -1};
13247 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13249 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13252 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13253 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13256 static const int ShufMask2[] = {0, 1, 4, 5};
13258 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13259 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13265 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13266 /// specific shuffle of a load can be folded into a single element load.
13267 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13268 /// shuffles have been customed lowered so we need to handle those here.
13269 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13270 TargetLowering::DAGCombinerInfo &DCI) {
13271 if (DCI.isBeforeLegalizeOps())
13274 SDValue InVec = N->getOperand(0);
13275 SDValue EltNo = N->getOperand(1);
13277 if (!isa<ConstantSDNode>(EltNo))
13280 EVT VT = InVec.getValueType();
13282 bool HasShuffleIntoBitcast = false;
13283 if (InVec.getOpcode() == ISD::BITCAST) {
13284 // Don't duplicate a load with other uses.
13285 if (!InVec.hasOneUse())
13287 EVT BCVT = InVec.getOperand(0).getValueType();
13288 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13290 InVec = InVec.getOperand(0);
13291 HasShuffleIntoBitcast = true;
13294 if (!isTargetShuffle(InVec.getOpcode()))
13297 // Don't duplicate a load with other uses.
13298 if (!InVec.hasOneUse())
13301 SmallVector<int, 16> ShuffleMask;
13303 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13307 // Select the input vector, guarding against out of range extract vector.
13308 unsigned NumElems = VT.getVectorNumElements();
13309 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13310 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13311 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13312 : InVec.getOperand(1);
13314 // If inputs to shuffle are the same for both ops, then allow 2 uses
13315 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13317 if (LdNode.getOpcode() == ISD::BITCAST) {
13318 // Don't duplicate a load with other uses.
13319 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13322 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13323 LdNode = LdNode.getOperand(0);
13326 if (!ISD::isNormalLoad(LdNode.getNode()))
13329 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13331 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13334 if (HasShuffleIntoBitcast) {
13335 // If there's a bitcast before the shuffle, check if the load type and
13336 // alignment is valid.
13337 unsigned Align = LN0->getAlignment();
13338 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13339 unsigned NewAlign = TLI.getTargetData()->
13340 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13342 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13346 // All checks match so transform back to vector_shuffle so that DAG combiner
13347 // can finish the job
13348 DebugLoc dl = N->getDebugLoc();
13350 // Create shuffle node taking into account the case that its a unary shuffle
13351 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13352 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13353 InVec.getOperand(0), Shuffle,
13355 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13356 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13360 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13361 /// generation and convert it from being a bunch of shuffles and extracts
13362 /// to a simple store and scalar loads to extract the elements.
13363 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13364 TargetLowering::DAGCombinerInfo &DCI) {
13365 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13366 if (NewOp.getNode())
13369 SDValue InputVector = N->getOperand(0);
13371 // Only operate on vectors of 4 elements, where the alternative shuffling
13372 // gets to be more expensive.
13373 if (InputVector.getValueType() != MVT::v4i32)
13376 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13377 // single use which is a sign-extend or zero-extend, and all elements are
13379 SmallVector<SDNode *, 4> Uses;
13380 unsigned ExtractedElements = 0;
13381 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13382 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13383 if (UI.getUse().getResNo() != InputVector.getResNo())
13386 SDNode *Extract = *UI;
13387 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13390 if (Extract->getValueType(0) != MVT::i32)
13392 if (!Extract->hasOneUse())
13394 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13395 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13397 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13400 // Record which element was extracted.
13401 ExtractedElements |=
13402 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13404 Uses.push_back(Extract);
13407 // If not all the elements were used, this may not be worthwhile.
13408 if (ExtractedElements != 15)
13411 // Ok, we've now decided to do the transformation.
13412 DebugLoc dl = InputVector.getDebugLoc();
13414 // Store the value to a temporary stack slot.
13415 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13416 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13417 MachinePointerInfo(), false, false, 0);
13419 // Replace each use (extract) with a load of the appropriate element.
13420 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13421 UE = Uses.end(); UI != UE; ++UI) {
13422 SDNode *Extract = *UI;
13424 // cOMpute the element's address.
13425 SDValue Idx = Extract->getOperand(1);
13427 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13428 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13430 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13432 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13433 StackPtr, OffsetVal);
13435 // Load the scalar.
13436 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13437 ScalarAddr, MachinePointerInfo(),
13438 false, false, false, 0);
13440 // Replace the exact with the load.
13441 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13444 // The replacement was made in place; don't return anything.
13448 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13450 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13451 TargetLowering::DAGCombinerInfo &DCI,
13452 const X86Subtarget *Subtarget) {
13453 DebugLoc DL = N->getDebugLoc();
13454 SDValue Cond = N->getOperand(0);
13455 // Get the LHS/RHS of the select.
13456 SDValue LHS = N->getOperand(1);
13457 SDValue RHS = N->getOperand(2);
13458 EVT VT = LHS.getValueType();
13460 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13461 // instructions match the semantics of the common C idiom x<y?x:y but not
13462 // x<=y?x:y, because of how they handle negative zero (which can be
13463 // ignored in unsafe-math mode).
13464 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13465 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13466 (Subtarget->hasSSE2() ||
13467 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13468 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13470 unsigned Opcode = 0;
13471 // Check for x CC y ? x : y.
13472 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13473 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13477 // Converting this to a min would handle NaNs incorrectly, and swapping
13478 // the operands would cause it to handle comparisons between positive
13479 // and negative zero incorrectly.
13480 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13481 if (!DAG.getTarget().Options.UnsafeFPMath &&
13482 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13484 std::swap(LHS, RHS);
13486 Opcode = X86ISD::FMIN;
13489 // Converting this to a min would handle comparisons between positive
13490 // and negative zero incorrectly.
13491 if (!DAG.getTarget().Options.UnsafeFPMath &&
13492 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13494 Opcode = X86ISD::FMIN;
13497 // Converting this to a min would handle both negative zeros and NaNs
13498 // incorrectly, but we can swap the operands to fix both.
13499 std::swap(LHS, RHS);
13503 Opcode = X86ISD::FMIN;
13507 // Converting this to a max would handle comparisons between positive
13508 // and negative zero incorrectly.
13509 if (!DAG.getTarget().Options.UnsafeFPMath &&
13510 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13512 Opcode = X86ISD::FMAX;
13515 // Converting this to a max would handle NaNs incorrectly, and swapping
13516 // the operands would cause it to handle comparisons between positive
13517 // and negative zero incorrectly.
13518 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13519 if (!DAG.getTarget().Options.UnsafeFPMath &&
13520 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13522 std::swap(LHS, RHS);
13524 Opcode = X86ISD::FMAX;
13527 // Converting this to a max would handle both negative zeros and NaNs
13528 // incorrectly, but we can swap the operands to fix both.
13529 std::swap(LHS, RHS);
13533 Opcode = X86ISD::FMAX;
13536 // Check for x CC y ? y : x -- a min/max with reversed arms.
13537 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13538 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13542 // Converting this to a min would handle comparisons between positive
13543 // and negative zero incorrectly, and swapping the operands would
13544 // cause it to handle NaNs incorrectly.
13545 if (!DAG.getTarget().Options.UnsafeFPMath &&
13546 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13547 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13549 std::swap(LHS, RHS);
13551 Opcode = X86ISD::FMIN;
13554 // Converting this to a min would handle NaNs incorrectly.
13555 if (!DAG.getTarget().Options.UnsafeFPMath &&
13556 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13558 Opcode = X86ISD::FMIN;
13561 // Converting this to a min would handle both negative zeros and NaNs
13562 // incorrectly, but we can swap the operands to fix both.
13563 std::swap(LHS, RHS);
13567 Opcode = X86ISD::FMIN;
13571 // Converting this to a max would handle NaNs incorrectly.
13572 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13574 Opcode = X86ISD::FMAX;
13577 // Converting this to a max would handle comparisons between positive
13578 // and negative zero incorrectly, and swapping the operands would
13579 // cause it to handle NaNs incorrectly.
13580 if (!DAG.getTarget().Options.UnsafeFPMath &&
13581 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13582 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13584 std::swap(LHS, RHS);
13586 Opcode = X86ISD::FMAX;
13589 // Converting this to a max would handle both negative zeros and NaNs
13590 // incorrectly, but we can swap the operands to fix both.
13591 std::swap(LHS, RHS);
13595 Opcode = X86ISD::FMAX;
13601 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13604 // If this is a select between two integer constants, try to do some
13606 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13607 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13608 // Don't do this for crazy integer types.
13609 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13610 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13611 // so that TrueC (the true value) is larger than FalseC.
13612 bool NeedsCondInvert = false;
13614 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13615 // Efficiently invertible.
13616 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13617 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13618 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13619 NeedsCondInvert = true;
13620 std::swap(TrueC, FalseC);
13623 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13624 if (FalseC->getAPIntValue() == 0 &&
13625 TrueC->getAPIntValue().isPowerOf2()) {
13626 if (NeedsCondInvert) // Invert the condition if needed.
13627 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13628 DAG.getConstant(1, Cond.getValueType()));
13630 // Zero extend the condition if needed.
13631 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13633 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13634 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13635 DAG.getConstant(ShAmt, MVT::i8));
13638 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13639 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13640 if (NeedsCondInvert) // Invert the condition if needed.
13641 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13642 DAG.getConstant(1, Cond.getValueType()));
13644 // Zero extend the condition if needed.
13645 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13646 FalseC->getValueType(0), Cond);
13647 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13648 SDValue(FalseC, 0));
13651 // Optimize cases that will turn into an LEA instruction. This requires
13652 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13653 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13654 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13655 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13657 bool isFastMultiplier = false;
13659 switch ((unsigned char)Diff) {
13661 case 1: // result = add base, cond
13662 case 2: // result = lea base( , cond*2)
13663 case 3: // result = lea base(cond, cond*2)
13664 case 4: // result = lea base( , cond*4)
13665 case 5: // result = lea base(cond, cond*4)
13666 case 8: // result = lea base( , cond*8)
13667 case 9: // result = lea base(cond, cond*8)
13668 isFastMultiplier = true;
13673 if (isFastMultiplier) {
13674 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13675 if (NeedsCondInvert) // Invert the condition if needed.
13676 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13677 DAG.getConstant(1, Cond.getValueType()));
13679 // Zero extend the condition if needed.
13680 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13682 // Scale the condition by the difference.
13684 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13685 DAG.getConstant(Diff, Cond.getValueType()));
13687 // Add the base if non-zero.
13688 if (FalseC->getAPIntValue() != 0)
13689 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13690 SDValue(FalseC, 0));
13697 // Canonicalize max and min:
13698 // (x > y) ? x : y -> (x >= y) ? x : y
13699 // (x < y) ? x : y -> (x <= y) ? x : y
13700 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13701 // the need for an extra compare
13702 // against zero. e.g.
13703 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13705 // testl %edi, %edi
13707 // cmovgl %edi, %eax
13711 // cmovsl %eax, %edi
13712 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13713 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13714 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13715 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13720 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13721 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13722 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13723 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13728 // If we know that this node is legal then we know that it is going to be
13729 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13730 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13731 // to simplify previous instructions.
13732 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13733 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13734 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
13735 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13737 // Don't optimize vector selects that map to mask-registers.
13741 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13742 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13744 APInt KnownZero, KnownOne;
13745 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13746 DCI.isBeforeLegalizeOps());
13747 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13748 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13749 DCI.CommitTargetLoweringOpt(TLO);
13755 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13756 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13757 TargetLowering::DAGCombinerInfo &DCI) {
13758 DebugLoc DL = N->getDebugLoc();
13760 // If the flag operand isn't dead, don't touch this CMOV.
13761 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13764 SDValue FalseOp = N->getOperand(0);
13765 SDValue TrueOp = N->getOperand(1);
13766 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13767 SDValue Cond = N->getOperand(3);
13768 if (CC == X86::COND_E || CC == X86::COND_NE) {
13769 switch (Cond.getOpcode()) {
13773 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13774 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13775 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13779 // If this is a select between two integer constants, try to do some
13780 // optimizations. Note that the operands are ordered the opposite of SELECT
13782 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13783 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13784 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13785 // larger than FalseC (the false value).
13786 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13787 CC = X86::GetOppositeBranchCondition(CC);
13788 std::swap(TrueC, FalseC);
13791 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13792 // This is efficient for any integer data type (including i8/i16) and
13794 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13795 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13796 DAG.getConstant(CC, MVT::i8), Cond);
13798 // Zero extend the condition if needed.
13799 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13801 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13802 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13803 DAG.getConstant(ShAmt, MVT::i8));
13804 if (N->getNumValues() == 2) // Dead flag value?
13805 return DCI.CombineTo(N, Cond, SDValue());
13809 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13810 // for any integer data type, including i8/i16.
13811 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13812 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13813 DAG.getConstant(CC, MVT::i8), Cond);
13815 // Zero extend the condition if needed.
13816 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13817 FalseC->getValueType(0), Cond);
13818 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13819 SDValue(FalseC, 0));
13821 if (N->getNumValues() == 2) // Dead flag value?
13822 return DCI.CombineTo(N, Cond, SDValue());
13826 // Optimize cases that will turn into an LEA instruction. This requires
13827 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13828 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13829 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13830 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13832 bool isFastMultiplier = false;
13834 switch ((unsigned char)Diff) {
13836 case 1: // result = add base, cond
13837 case 2: // result = lea base( , cond*2)
13838 case 3: // result = lea base(cond, cond*2)
13839 case 4: // result = lea base( , cond*4)
13840 case 5: // result = lea base(cond, cond*4)
13841 case 8: // result = lea base( , cond*8)
13842 case 9: // result = lea base(cond, cond*8)
13843 isFastMultiplier = true;
13848 if (isFastMultiplier) {
13849 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13850 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13851 DAG.getConstant(CC, MVT::i8), Cond);
13852 // Zero extend the condition if needed.
13853 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13855 // Scale the condition by the difference.
13857 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13858 DAG.getConstant(Diff, Cond.getValueType()));
13860 // Add the base if non-zero.
13861 if (FalseC->getAPIntValue() != 0)
13862 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13863 SDValue(FalseC, 0));
13864 if (N->getNumValues() == 2) // Dead flag value?
13865 return DCI.CombineTo(N, Cond, SDValue());
13875 /// PerformMulCombine - Optimize a single multiply with constant into two
13876 /// in order to implement it with two cheaper instructions, e.g.
13877 /// LEA + SHL, LEA + LEA.
13878 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13879 TargetLowering::DAGCombinerInfo &DCI) {
13880 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13883 EVT VT = N->getValueType(0);
13884 if (VT != MVT::i64)
13887 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13890 uint64_t MulAmt = C->getZExtValue();
13891 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13894 uint64_t MulAmt1 = 0;
13895 uint64_t MulAmt2 = 0;
13896 if ((MulAmt % 9) == 0) {
13898 MulAmt2 = MulAmt / 9;
13899 } else if ((MulAmt % 5) == 0) {
13901 MulAmt2 = MulAmt / 5;
13902 } else if ((MulAmt % 3) == 0) {
13904 MulAmt2 = MulAmt / 3;
13907 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13908 DebugLoc DL = N->getDebugLoc();
13910 if (isPowerOf2_64(MulAmt2) &&
13911 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13912 // If second multiplifer is pow2, issue it first. We want the multiply by
13913 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13915 std::swap(MulAmt1, MulAmt2);
13918 if (isPowerOf2_64(MulAmt1))
13919 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13920 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13922 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13923 DAG.getConstant(MulAmt1, VT));
13925 if (isPowerOf2_64(MulAmt2))
13926 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13927 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13929 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13930 DAG.getConstant(MulAmt2, VT));
13932 // Do not add new nodes to DAG combiner worklist.
13933 DCI.CombineTo(N, NewMul, false);
13938 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13939 SDValue N0 = N->getOperand(0);
13940 SDValue N1 = N->getOperand(1);
13941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13942 EVT VT = N0.getValueType();
13944 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13945 // since the result of setcc_c is all zero's or all ones.
13946 if (VT.isInteger() && !VT.isVector() &&
13947 N1C && N0.getOpcode() == ISD::AND &&
13948 N0.getOperand(1).getOpcode() == ISD::Constant) {
13949 SDValue N00 = N0.getOperand(0);
13950 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13951 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13952 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13953 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13954 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13955 APInt ShAmt = N1C->getAPIntValue();
13956 Mask = Mask.shl(ShAmt);
13958 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13959 N00, DAG.getConstant(Mask, VT));
13964 // Hardware support for vector shifts is sparse which makes us scalarize the
13965 // vector operations in many cases. Also, on sandybridge ADD is faster than
13967 // (shl V, 1) -> add V,V
13968 if (isSplatVector(N1.getNode())) {
13969 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13970 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13971 // We shift all of the values by one. In many cases we do not have
13972 // hardware support for this operation. This is better expressed as an ADD
13974 if (N1C && (1 == N1C->getZExtValue())) {
13975 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13982 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13984 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13985 TargetLowering::DAGCombinerInfo &DCI,
13986 const X86Subtarget *Subtarget) {
13987 EVT VT = N->getValueType(0);
13988 if (N->getOpcode() == ISD::SHL) {
13989 SDValue V = PerformSHLCombine(N, DAG);
13990 if (V.getNode()) return V;
13993 // On X86 with SSE2 support, we can transform this to a vector shift if
13994 // all elements are shifted by the same amount. We can't do this in legalize
13995 // because the a constant vector is typically transformed to a constant pool
13996 // so we have no knowledge of the shift amount.
13997 if (!Subtarget->hasSSE2())
14000 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
14001 (!Subtarget->hasAVX2() ||
14002 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
14005 SDValue ShAmtOp = N->getOperand(1);
14006 EVT EltVT = VT.getVectorElementType();
14007 DebugLoc DL = N->getDebugLoc();
14008 SDValue BaseShAmt = SDValue();
14009 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
14010 unsigned NumElts = VT.getVectorNumElements();
14012 for (; i != NumElts; ++i) {
14013 SDValue Arg = ShAmtOp.getOperand(i);
14014 if (Arg.getOpcode() == ISD::UNDEF) continue;
14018 // Handle the case where the build_vector is all undef
14019 // FIXME: Should DAG allow this?
14023 for (; i != NumElts; ++i) {
14024 SDValue Arg = ShAmtOp.getOperand(i);
14025 if (Arg.getOpcode() == ISD::UNDEF) continue;
14026 if (Arg != BaseShAmt) {
14030 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
14031 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
14032 SDValue InVec = ShAmtOp.getOperand(0);
14033 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
14034 unsigned NumElts = InVec.getValueType().getVectorNumElements();
14036 for (; i != NumElts; ++i) {
14037 SDValue Arg = InVec.getOperand(i);
14038 if (Arg.getOpcode() == ISD::UNDEF) continue;
14042 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
14043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
14044 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
14045 if (C->getZExtValue() == SplatIdx)
14046 BaseShAmt = InVec.getOperand(1);
14049 if (BaseShAmt.getNode() == 0) {
14050 // Don't create instructions with illegal types after legalize
14052 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
14053 !DCI.isBeforeLegalize())
14056 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14057 DAG.getIntPtrConstant(0));
14062 // The shift amount is an i32.
14063 if (EltVT.bitsGT(MVT::i32))
14064 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14065 else if (EltVT.bitsLT(MVT::i32))
14066 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14068 // The shift amount is identical so we can do a vector shift.
14069 SDValue ValOp = N->getOperand(0);
14070 switch (N->getOpcode()) {
14072 llvm_unreachable("Unknown shift opcode!");
14074 switch (VT.getSimpleVT().SimpleTy) {
14075 default: return SDValue();
14082 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14085 switch (VT.getSimpleVT().SimpleTy) {
14086 default: return SDValue();
14091 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14094 switch (VT.getSimpleVT().SimpleTy) {
14095 default: return SDValue();
14102 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14108 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14109 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14110 // and friends. Likewise for OR -> CMPNEQSS.
14111 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14112 TargetLowering::DAGCombinerInfo &DCI,
14113 const X86Subtarget *Subtarget) {
14116 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14117 // we're requiring SSE2 for both.
14118 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14119 SDValue N0 = N->getOperand(0);
14120 SDValue N1 = N->getOperand(1);
14121 SDValue CMP0 = N0->getOperand(1);
14122 SDValue CMP1 = N1->getOperand(1);
14123 DebugLoc DL = N->getDebugLoc();
14125 // The SETCCs should both refer to the same CMP.
14126 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14129 SDValue CMP00 = CMP0->getOperand(0);
14130 SDValue CMP01 = CMP0->getOperand(1);
14131 EVT VT = CMP00.getValueType();
14133 if (VT == MVT::f32 || VT == MVT::f64) {
14134 bool ExpectingFlags = false;
14135 // Check for any users that want flags:
14136 for (SDNode::use_iterator UI = N->use_begin(),
14138 !ExpectingFlags && UI != UE; ++UI)
14139 switch (UI->getOpcode()) {
14144 ExpectingFlags = true;
14146 case ISD::CopyToReg:
14147 case ISD::SIGN_EXTEND:
14148 case ISD::ZERO_EXTEND:
14149 case ISD::ANY_EXTEND:
14153 if (!ExpectingFlags) {
14154 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14155 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14157 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14158 X86::CondCode tmp = cc0;
14163 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14164 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14165 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14166 X86ISD::NodeType NTOperator = is64BitFP ?
14167 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14168 // FIXME: need symbolic constants for these magic numbers.
14169 // See X86ATTInstPrinter.cpp:printSSECC().
14170 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14171 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14172 DAG.getConstant(x86cc, MVT::i8));
14173 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14175 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14176 DAG.getConstant(1, MVT::i32));
14177 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14178 return OneBitOfTruth;
14186 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14187 /// so it can be folded inside ANDNP.
14188 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14189 EVT VT = N->getValueType(0);
14191 // Match direct AllOnes for 128 and 256-bit vectors
14192 if (ISD::isBuildVectorAllOnes(N))
14195 // Look through a bit convert.
14196 if (N->getOpcode() == ISD::BITCAST)
14197 N = N->getOperand(0).getNode();
14199 // Sometimes the operand may come from a insert_subvector building a 256-bit
14201 if (VT.getSizeInBits() == 256 &&
14202 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14203 SDValue V1 = N->getOperand(0);
14204 SDValue V2 = N->getOperand(1);
14206 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14207 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14208 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14209 ISD::isBuildVectorAllOnes(V2.getNode()))
14216 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14217 TargetLowering::DAGCombinerInfo &DCI,
14218 const X86Subtarget *Subtarget) {
14219 if (DCI.isBeforeLegalizeOps())
14222 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14226 EVT VT = N->getValueType(0);
14228 // Create ANDN, BLSI, and BLSR instructions
14229 // BLSI is X & (-X)
14230 // BLSR is X & (X-1)
14231 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14232 SDValue N0 = N->getOperand(0);
14233 SDValue N1 = N->getOperand(1);
14234 DebugLoc DL = N->getDebugLoc();
14236 // Check LHS for not
14237 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14238 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14239 // Check RHS for not
14240 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14241 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14243 // Check LHS for neg
14244 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14245 isZero(N0.getOperand(0)))
14246 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14248 // Check RHS for neg
14249 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14250 isZero(N1.getOperand(0)))
14251 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14253 // Check LHS for X-1
14254 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14255 isAllOnes(N0.getOperand(1)))
14256 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14258 // Check RHS for X-1
14259 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14260 isAllOnes(N1.getOperand(1)))
14261 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14266 // Want to form ANDNP nodes:
14267 // 1) In the hopes of then easily combining them with OR and AND nodes
14268 // to form PBLEND/PSIGN.
14269 // 2) To match ANDN packed intrinsics
14270 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14273 SDValue N0 = N->getOperand(0);
14274 SDValue N1 = N->getOperand(1);
14275 DebugLoc DL = N->getDebugLoc();
14277 // Check LHS for vnot
14278 if (N0.getOpcode() == ISD::XOR &&
14279 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14280 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14281 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14283 // Check RHS for vnot
14284 if (N1.getOpcode() == ISD::XOR &&
14285 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14286 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14287 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14292 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14293 TargetLowering::DAGCombinerInfo &DCI,
14294 const X86Subtarget *Subtarget) {
14295 if (DCI.isBeforeLegalizeOps())
14298 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14302 EVT VT = N->getValueType(0);
14304 SDValue N0 = N->getOperand(0);
14305 SDValue N1 = N->getOperand(1);
14307 // look for psign/blend
14308 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14309 if (!Subtarget->hasSSSE3() ||
14310 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14313 // Canonicalize pandn to RHS
14314 if (N0.getOpcode() == X86ISD::ANDNP)
14316 // or (and (m, y), (pandn m, x))
14317 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14318 SDValue Mask = N1.getOperand(0);
14319 SDValue X = N1.getOperand(1);
14321 if (N0.getOperand(0) == Mask)
14322 Y = N0.getOperand(1);
14323 if (N0.getOperand(1) == Mask)
14324 Y = N0.getOperand(0);
14326 // Check to see if the mask appeared in both the AND and ANDNP and
14330 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14331 // Look through mask bitcast.
14332 if (Mask.getOpcode() == ISD::BITCAST)
14333 Mask = Mask.getOperand(0);
14334 if (X.getOpcode() == ISD::BITCAST)
14335 X = X.getOperand(0);
14336 if (Y.getOpcode() == ISD::BITCAST)
14337 Y = Y.getOperand(0);
14339 EVT MaskVT = Mask.getValueType();
14341 // Validate that the Mask operand is a vector sra node.
14342 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14343 // there is no psrai.b
14344 if (Mask.getOpcode() != X86ISD::VSRAI)
14347 // Check that the SRA is all signbits.
14348 SDValue SraC = Mask.getOperand(1);
14349 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14350 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14351 if ((SraAmt + 1) != EltBits)
14354 DebugLoc DL = N->getDebugLoc();
14356 // Now we know we at least have a plendvb with the mask val. See if
14357 // we can form a psignb/w/d.
14358 // psign = x.type == y.type == mask.type && y = sub(0, x);
14359 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14360 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14361 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14362 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14363 "Unsupported VT for PSIGN");
14364 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14365 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14367 // PBLENDVB only available on SSE 4.1
14368 if (!Subtarget->hasSSE41())
14371 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14373 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14374 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14375 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14376 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14377 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14381 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14384 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14385 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14387 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14389 if (!N0.hasOneUse() || !N1.hasOneUse())
14392 SDValue ShAmt0 = N0.getOperand(1);
14393 if (ShAmt0.getValueType() != MVT::i8)
14395 SDValue ShAmt1 = N1.getOperand(1);
14396 if (ShAmt1.getValueType() != MVT::i8)
14398 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14399 ShAmt0 = ShAmt0.getOperand(0);
14400 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14401 ShAmt1 = ShAmt1.getOperand(0);
14403 DebugLoc DL = N->getDebugLoc();
14404 unsigned Opc = X86ISD::SHLD;
14405 SDValue Op0 = N0.getOperand(0);
14406 SDValue Op1 = N1.getOperand(0);
14407 if (ShAmt0.getOpcode() == ISD::SUB) {
14408 Opc = X86ISD::SHRD;
14409 std::swap(Op0, Op1);
14410 std::swap(ShAmt0, ShAmt1);
14413 unsigned Bits = VT.getSizeInBits();
14414 if (ShAmt1.getOpcode() == ISD::SUB) {
14415 SDValue Sum = ShAmt1.getOperand(0);
14416 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14417 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14418 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14419 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14420 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14421 return DAG.getNode(Opc, DL, VT,
14423 DAG.getNode(ISD::TRUNCATE, DL,
14426 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14427 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14429 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14430 return DAG.getNode(Opc, DL, VT,
14431 N0.getOperand(0), N1.getOperand(0),
14432 DAG.getNode(ISD::TRUNCATE, DL,
14439 // Generate NEG and CMOV for integer abs.
14440 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
14441 EVT VT = N->getValueType(0);
14443 // Since X86 does not have CMOV for 8-bit integer, we don't convert
14444 // 8-bit integer abs to NEG and CMOV.
14445 if (VT.isInteger() && VT.getSizeInBits() == 8)
14448 SDValue N0 = N->getOperand(0);
14449 SDValue N1 = N->getOperand(1);
14450 DebugLoc DL = N->getDebugLoc();
14452 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
14453 // and change it to SUB and CMOV.
14454 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
14455 N0.getOpcode() == ISD::ADD &&
14456 N0.getOperand(1) == N1 &&
14457 N1.getOpcode() == ISD::SRA &&
14458 N1.getOperand(0) == N0.getOperand(0))
14459 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
14460 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
14461 // Generate SUB & CMOV.
14462 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
14463 DAG.getConstant(0, VT), N0.getOperand(0));
14465 SDValue Ops[] = { N0.getOperand(0), Neg,
14466 DAG.getConstant(X86::COND_GE, MVT::i8),
14467 SDValue(Neg.getNode(), 1) };
14468 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
14469 Ops, array_lengthof(Ops));
14474 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14475 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14476 TargetLowering::DAGCombinerInfo &DCI,
14477 const X86Subtarget *Subtarget) {
14478 if (DCI.isBeforeLegalizeOps())
14481 if (Subtarget->hasCMov()) {
14482 SDValue RV = performIntegerAbsCombine(N, DAG);
14487 // Try forming BMI if it is available.
14488 if (!Subtarget->hasBMI())
14491 EVT VT = N->getValueType(0);
14493 if (VT != MVT::i32 && VT != MVT::i64)
14496 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14498 // Create BLSMSK instructions by finding X ^ (X-1)
14499 SDValue N0 = N->getOperand(0);
14500 SDValue N1 = N->getOperand(1);
14501 DebugLoc DL = N->getDebugLoc();
14503 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14504 isAllOnes(N0.getOperand(1)))
14505 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14507 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14508 isAllOnes(N1.getOperand(1)))
14509 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14514 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14515 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14516 TargetLowering::DAGCombinerInfo &DCI,
14517 const X86Subtarget *Subtarget) {
14518 LoadSDNode *Ld = cast<LoadSDNode>(N);
14519 EVT RegVT = Ld->getValueType(0);
14520 EVT MemVT = Ld->getMemoryVT();
14521 DebugLoc dl = Ld->getDebugLoc();
14522 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14524 ISD::LoadExtType Ext = Ld->getExtensionType();
14526 // If this is a vector EXT Load then attempt to optimize it using a
14527 // shuffle. We need SSE4 for the shuffles.
14528 // TODO: It is possible to support ZExt by zeroing the undef values
14529 // during the shuffle phase or after the shuffle.
14530 if (RegVT.isVector() && RegVT.isInteger() &&
14531 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14532 assert(MemVT != RegVT && "Cannot extend to the same type");
14533 assert(MemVT.isVector() && "Must load a vector from memory");
14535 unsigned NumElems = RegVT.getVectorNumElements();
14536 unsigned RegSz = RegVT.getSizeInBits();
14537 unsigned MemSz = MemVT.getSizeInBits();
14538 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14540 // All sizes must be a power of two.
14541 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
14544 // Attempt to load the original value using scalar loads.
14545 // Find the largest scalar type that divides the total loaded size.
14546 MVT SclrLoadTy = MVT::i8;
14547 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14548 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14549 MVT Tp = (MVT::SimpleValueType)tp;
14550 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14555 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14556 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14558 SclrLoadTy = MVT::f64;
14560 // Calculate the number of scalar loads that we need to perform
14561 // in order to load our vector from memory.
14562 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14564 // Represent our vector as a sequence of elements which are the
14565 // largest scalar that we can load.
14566 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14567 RegSz/SclrLoadTy.getSizeInBits());
14569 // Represent the data using the same element type that is stored in
14570 // memory. In practice, we ''widen'' MemVT.
14571 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14572 RegSz/MemVT.getScalarType().getSizeInBits());
14574 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14575 "Invalid vector type");
14577 // We can't shuffle using an illegal type.
14578 if (!TLI.isTypeLegal(WideVecVT))
14581 SmallVector<SDValue, 8> Chains;
14582 SDValue Ptr = Ld->getBasePtr();
14583 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
14584 TLI.getPointerTy());
14585 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14587 for (unsigned i = 0; i < NumLoads; ++i) {
14588 // Perform a single load.
14589 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14590 Ptr, Ld->getPointerInfo(),
14591 Ld->isVolatile(), Ld->isNonTemporal(),
14592 Ld->isInvariant(), Ld->getAlignment());
14593 Chains.push_back(ScalarLoad.getValue(1));
14594 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14595 // another round of DAGCombining.
14597 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14599 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14600 ScalarLoad, DAG.getIntPtrConstant(i));
14602 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14605 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14608 // Bitcast the loaded value to a vector of the original element type, in
14609 // the size of the target vector type.
14610 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14611 unsigned SizeRatio = RegSz/MemSz;
14613 // Redistribute the loaded elements into the different locations.
14614 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14615 for (unsigned i = 0; i != NumElems; ++i)
14616 ShuffleVec[i*SizeRatio] = i;
14618 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14619 DAG.getUNDEF(WideVecVT),
14622 // Bitcast to the requested type.
14623 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14624 // Replace the original load with the new sequence
14625 // and return the new chain.
14626 return DCI.CombineTo(N, Shuff, TF, true);
14632 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14633 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14634 const X86Subtarget *Subtarget) {
14635 StoreSDNode *St = cast<StoreSDNode>(N);
14636 EVT VT = St->getValue().getValueType();
14637 EVT StVT = St->getMemoryVT();
14638 DebugLoc dl = St->getDebugLoc();
14639 SDValue StoredVal = St->getOperand(1);
14640 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14642 // If we are saving a concatenation of two XMM registers, perform two stores.
14643 // On Sandy Bridge, 256-bit memory operations are executed by two
14644 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
14645 // memory operation.
14646 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2() &&
14647 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14648 StoredVal.getNumOperands() == 2) {
14649 SDValue Value0 = StoredVal.getOperand(0);
14650 SDValue Value1 = StoredVal.getOperand(1);
14652 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14653 SDValue Ptr0 = St->getBasePtr();
14654 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14656 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14657 St->getPointerInfo(), St->isVolatile(),
14658 St->isNonTemporal(), St->getAlignment());
14659 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14660 St->getPointerInfo(), St->isVolatile(),
14661 St->isNonTemporal(), St->getAlignment());
14662 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14665 // Optimize trunc store (of multiple scalars) to shuffle and store.
14666 // First, pack all of the elements in one place. Next, store to memory
14667 // in fewer chunks.
14668 if (St->isTruncatingStore() && VT.isVector()) {
14669 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14670 unsigned NumElems = VT.getVectorNumElements();
14671 assert(StVT != VT && "Cannot truncate to the same type");
14672 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14673 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14675 // From, To sizes and ElemCount must be pow of two
14676 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14677 // We are going to use the original vector elt for storing.
14678 // Accumulated smaller vector elements must be a multiple of the store size.
14679 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14681 unsigned SizeRatio = FromSz / ToSz;
14683 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14685 // Create a type on which we perform the shuffle
14686 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14687 StVT.getScalarType(), NumElems*SizeRatio);
14689 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14691 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14692 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14693 for (unsigned i = 0; i != NumElems; ++i)
14694 ShuffleVec[i] = i * SizeRatio;
14696 // Can't shuffle using an illegal type.
14697 if (!TLI.isTypeLegal(WideVecVT))
14700 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14701 DAG.getUNDEF(WideVecVT),
14703 // At this point all of the data is stored at the bottom of the
14704 // register. We now need to save it to mem.
14706 // Find the largest store unit
14707 MVT StoreType = MVT::i8;
14708 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14709 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14710 MVT Tp = (MVT::SimpleValueType)tp;
14711 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
14715 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14716 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
14717 (64 <= NumElems * ToSz))
14718 StoreType = MVT::f64;
14720 // Bitcast the original vector into a vector of store-size units
14721 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14722 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
14723 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14724 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14725 SmallVector<SDValue, 8> Chains;
14726 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14727 TLI.getPointerTy());
14728 SDValue Ptr = St->getBasePtr();
14730 // Perform one or more big stores into memory.
14731 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
14732 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14733 StoreType, ShuffWide,
14734 DAG.getIntPtrConstant(i));
14735 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14736 St->getPointerInfo(), St->isVolatile(),
14737 St->isNonTemporal(), St->getAlignment());
14738 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14739 Chains.push_back(Ch);
14742 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14747 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14748 // the FP state in cases where an emms may be missing.
14749 // A preferable solution to the general problem is to figure out the right
14750 // places to insert EMMS. This qualifies as a quick hack.
14752 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14753 if (VT.getSizeInBits() != 64)
14756 const Function *F = DAG.getMachineFunction().getFunction();
14757 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14758 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14759 && Subtarget->hasSSE2();
14760 if ((VT.isVector() ||
14761 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14762 isa<LoadSDNode>(St->getValue()) &&
14763 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14764 St->getChain().hasOneUse() && !St->isVolatile()) {
14765 SDNode* LdVal = St->getValue().getNode();
14766 LoadSDNode *Ld = 0;
14767 int TokenFactorIndex = -1;
14768 SmallVector<SDValue, 8> Ops;
14769 SDNode* ChainVal = St->getChain().getNode();
14770 // Must be a store of a load. We currently handle two cases: the load
14771 // is a direct child, and it's under an intervening TokenFactor. It is
14772 // possible to dig deeper under nested TokenFactors.
14773 if (ChainVal == LdVal)
14774 Ld = cast<LoadSDNode>(St->getChain());
14775 else if (St->getValue().hasOneUse() &&
14776 ChainVal->getOpcode() == ISD::TokenFactor) {
14777 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14778 if (ChainVal->getOperand(i).getNode() == LdVal) {
14779 TokenFactorIndex = i;
14780 Ld = cast<LoadSDNode>(St->getValue());
14782 Ops.push_back(ChainVal->getOperand(i));
14786 if (!Ld || !ISD::isNormalLoad(Ld))
14789 // If this is not the MMX case, i.e. we are just turning i64 load/store
14790 // into f64 load/store, avoid the transformation if there are multiple
14791 // uses of the loaded value.
14792 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14795 DebugLoc LdDL = Ld->getDebugLoc();
14796 DebugLoc StDL = N->getDebugLoc();
14797 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14798 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14800 if (Subtarget->is64Bit() || F64IsLegal) {
14801 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14802 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14803 Ld->getPointerInfo(), Ld->isVolatile(),
14804 Ld->isNonTemporal(), Ld->isInvariant(),
14805 Ld->getAlignment());
14806 SDValue NewChain = NewLd.getValue(1);
14807 if (TokenFactorIndex != -1) {
14808 Ops.push_back(NewChain);
14809 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14812 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14813 St->getPointerInfo(),
14814 St->isVolatile(), St->isNonTemporal(),
14815 St->getAlignment());
14818 // Otherwise, lower to two pairs of 32-bit loads / stores.
14819 SDValue LoAddr = Ld->getBasePtr();
14820 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14821 DAG.getConstant(4, MVT::i32));
14823 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14824 Ld->getPointerInfo(),
14825 Ld->isVolatile(), Ld->isNonTemporal(),
14826 Ld->isInvariant(), Ld->getAlignment());
14827 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14828 Ld->getPointerInfo().getWithOffset(4),
14829 Ld->isVolatile(), Ld->isNonTemporal(),
14831 MinAlign(Ld->getAlignment(), 4));
14833 SDValue NewChain = LoLd.getValue(1);
14834 if (TokenFactorIndex != -1) {
14835 Ops.push_back(LoLd);
14836 Ops.push_back(HiLd);
14837 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14841 LoAddr = St->getBasePtr();
14842 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14843 DAG.getConstant(4, MVT::i32));
14845 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14846 St->getPointerInfo(),
14847 St->isVolatile(), St->isNonTemporal(),
14848 St->getAlignment());
14849 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14850 St->getPointerInfo().getWithOffset(4),
14852 St->isNonTemporal(),
14853 MinAlign(St->getAlignment(), 4));
14854 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14859 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14860 /// and return the operands for the horizontal operation in LHS and RHS. A
14861 /// horizontal operation performs the binary operation on successive elements
14862 /// of its first operand, then on successive elements of its second operand,
14863 /// returning the resulting values in a vector. For example, if
14864 /// A = < float a0, float a1, float a2, float a3 >
14866 /// B = < float b0, float b1, float b2, float b3 >
14867 /// then the result of doing a horizontal operation on A and B is
14868 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14869 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14870 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14871 /// set to A, RHS to B, and the routine returns 'true'.
14872 /// Note that the binary operation should have the property that if one of the
14873 /// operands is UNDEF then the result is UNDEF.
14874 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14875 // Look for the following pattern: if
14876 // A = < float a0, float a1, float a2, float a3 >
14877 // B = < float b0, float b1, float b2, float b3 >
14879 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14880 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14881 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14882 // which is A horizontal-op B.
14884 // At least one of the operands should be a vector shuffle.
14885 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14886 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14889 EVT VT = LHS.getValueType();
14891 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14892 "Unsupported vector type for horizontal add/sub");
14894 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14895 // operate independently on 128-bit lanes.
14896 unsigned NumElts = VT.getVectorNumElements();
14897 unsigned NumLanes = VT.getSizeInBits()/128;
14898 unsigned NumLaneElts = NumElts / NumLanes;
14899 assert((NumLaneElts % 2 == 0) &&
14900 "Vector type should have an even number of elements in each lane");
14901 unsigned HalfLaneElts = NumLaneElts/2;
14903 // View LHS in the form
14904 // LHS = VECTOR_SHUFFLE A, B, LMask
14905 // If LHS is not a shuffle then pretend it is the shuffle
14906 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14907 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14910 SmallVector<int, 16> LMask(NumElts);
14911 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14912 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14913 A = LHS.getOperand(0);
14914 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14915 B = LHS.getOperand(1);
14916 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14917 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14919 if (LHS.getOpcode() != ISD::UNDEF)
14921 for (unsigned i = 0; i != NumElts; ++i)
14925 // Likewise, view RHS in the form
14926 // RHS = VECTOR_SHUFFLE C, D, RMask
14928 SmallVector<int, 16> RMask(NumElts);
14929 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14930 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14931 C = RHS.getOperand(0);
14932 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14933 D = RHS.getOperand(1);
14934 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14935 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14937 if (RHS.getOpcode() != ISD::UNDEF)
14939 for (unsigned i = 0; i != NumElts; ++i)
14943 // Check that the shuffles are both shuffling the same vectors.
14944 if (!(A == C && B == D) && !(A == D && B == C))
14947 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14948 if (!A.getNode() && !B.getNode())
14951 // If A and B occur in reverse order in RHS, then "swap" them (which means
14952 // rewriting the mask).
14954 CommuteVectorShuffleMask(RMask, NumElts);
14956 // At this point LHS and RHS are equivalent to
14957 // LHS = VECTOR_SHUFFLE A, B, LMask
14958 // RHS = VECTOR_SHUFFLE A, B, RMask
14959 // Check that the masks correspond to performing a horizontal operation.
14960 for (unsigned i = 0; i != NumElts; ++i) {
14961 int LIdx = LMask[i], RIdx = RMask[i];
14963 // Ignore any UNDEF components.
14964 if (LIdx < 0 || RIdx < 0 ||
14965 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14966 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14969 // Check that successive elements are being operated on. If not, this is
14970 // not a horizontal operation.
14971 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14972 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14973 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14974 if (!(LIdx == Index && RIdx == Index + 1) &&
14975 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14979 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14980 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14984 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14985 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14986 const X86Subtarget *Subtarget) {
14987 EVT VT = N->getValueType(0);
14988 SDValue LHS = N->getOperand(0);
14989 SDValue RHS = N->getOperand(1);
14991 // Try to synthesize horizontal adds from adds of shuffles.
14992 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14993 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14994 isHorizontalBinOp(LHS, RHS, true))
14995 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14999 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
15000 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
15001 const X86Subtarget *Subtarget) {
15002 EVT VT = N->getValueType(0);
15003 SDValue LHS = N->getOperand(0);
15004 SDValue RHS = N->getOperand(1);
15006 // Try to synthesize horizontal subs from subs of shuffles.
15007 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
15008 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
15009 isHorizontalBinOp(LHS, RHS, false))
15010 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
15014 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
15015 /// X86ISD::FXOR nodes.
15016 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
15017 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
15018 // F[X]OR(0.0, x) -> x
15019 // F[X]OR(x, 0.0) -> x
15020 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15021 if (C->getValueAPF().isPosZero())
15022 return N->getOperand(1);
15023 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15024 if (C->getValueAPF().isPosZero())
15025 return N->getOperand(0);
15029 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
15030 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
15031 // FAND(0.0, x) -> 0.0
15032 // FAND(x, 0.0) -> 0.0
15033 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
15034 if (C->getValueAPF().isPosZero())
15035 return N->getOperand(0);
15036 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
15037 if (C->getValueAPF().isPosZero())
15038 return N->getOperand(1);
15042 static SDValue PerformBTCombine(SDNode *N,
15044 TargetLowering::DAGCombinerInfo &DCI) {
15045 // BT ignores high bits in the bit index operand.
15046 SDValue Op1 = N->getOperand(1);
15047 if (Op1.hasOneUse()) {
15048 unsigned BitWidth = Op1.getValueSizeInBits();
15049 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
15050 APInt KnownZero, KnownOne;
15051 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
15052 !DCI.isBeforeLegalizeOps());
15053 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15054 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
15055 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
15056 DCI.CommitTargetLoweringOpt(TLO);
15061 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
15062 SDValue Op = N->getOperand(0);
15063 if (Op.getOpcode() == ISD::BITCAST)
15064 Op = Op.getOperand(0);
15065 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
15066 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
15067 VT.getVectorElementType().getSizeInBits() ==
15068 OpVT.getVectorElementType().getSizeInBits()) {
15069 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
15074 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
15075 TargetLowering::DAGCombinerInfo &DCI,
15076 const X86Subtarget *Subtarget) {
15077 if (!DCI.isBeforeLegalizeOps())
15080 if (!Subtarget->hasAVX())
15083 EVT VT = N->getValueType(0);
15084 SDValue Op = N->getOperand(0);
15085 EVT OpVT = Op.getValueType();
15086 DebugLoc dl = N->getDebugLoc();
15088 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
15089 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
15091 if (Subtarget->hasAVX2())
15092 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
15094 // Optimize vectors in AVX mode
15095 // Sign extend v8i16 to v8i32 and
15098 // Divide input vector into two parts
15099 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15100 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15101 // concat the vectors to original VT
15103 unsigned NumElems = OpVT.getVectorNumElements();
15104 SmallVector<int,8> ShufMask1(NumElems, -1);
15105 for (unsigned i = 0; i != NumElems/2; ++i)
15108 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15111 SmallVector<int,8> ShufMask2(NumElems, -1);
15112 for (unsigned i = 0; i != NumElems/2; ++i)
15113 ShufMask2[i] = i + NumElems/2;
15115 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15118 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
15119 VT.getVectorNumElements()/2);
15121 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
15122 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
15124 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15129 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
15130 TargetLowering::DAGCombinerInfo &DCI,
15131 const X86Subtarget *Subtarget) {
15132 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15133 // (and (i32 x86isd::setcc_carry), 1)
15134 // This eliminates the zext. This transformation is necessary because
15135 // ISD::SETCC is always legalized to i8.
15136 DebugLoc dl = N->getDebugLoc();
15137 SDValue N0 = N->getOperand(0);
15138 EVT VT = N->getValueType(0);
15139 EVT OpVT = N0.getValueType();
15141 if (N0.getOpcode() == ISD::AND &&
15143 N0.getOperand(0).hasOneUse()) {
15144 SDValue N00 = N0.getOperand(0);
15145 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15147 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15148 if (!C || C->getZExtValue() != 1)
15150 return DAG.getNode(ISD::AND, dl, VT,
15151 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15152 N00.getOperand(0), N00.getOperand(1)),
15153 DAG.getConstant(1, VT));
15156 // Optimize vectors in AVX mode:
15159 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15160 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15161 // Concat upper and lower parts.
15164 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15165 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15166 // Concat upper and lower parts.
15168 if (!DCI.isBeforeLegalizeOps())
15171 if (!Subtarget->hasAVX())
15174 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15175 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15177 if (Subtarget->hasAVX2())
15178 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15180 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15181 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15182 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15184 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15185 VT.getVectorNumElements()/2);
15187 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15188 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15190 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15196 // Optimize x == -y --> x+y == 0
15197 // x != -y --> x+y != 0
15198 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15199 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15200 SDValue LHS = N->getOperand(0);
15201 SDValue RHS = N->getOperand(1);
15203 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15204 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15205 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15206 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15207 LHS.getValueType(), RHS, LHS.getOperand(1));
15208 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15209 addV, DAG.getConstant(0, addV.getValueType()), CC);
15211 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15213 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15214 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15215 RHS.getValueType(), LHS, RHS.getOperand(1));
15216 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15217 addV, DAG.getConstant(0, addV.getValueType()), CC);
15222 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15223 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15224 unsigned X86CC = N->getConstantOperandVal(0);
15225 SDValue EFLAG = N->getOperand(1);
15226 DebugLoc DL = N->getDebugLoc();
15228 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15229 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15231 if (X86CC == X86::COND_B)
15232 return DAG.getNode(ISD::AND, DL, MVT::i8,
15233 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15234 DAG.getConstant(X86CC, MVT::i8), EFLAG),
15235 DAG.getConstant(1, MVT::i8));
15240 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15241 SDValue Op0 = N->getOperand(0);
15242 EVT InVT = Op0->getValueType(0);
15244 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15245 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15246 DebugLoc dl = N->getDebugLoc();
15247 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15248 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15249 // Notice that we use SINT_TO_FP because we know that the high bits
15250 // are zero and SINT_TO_FP is better supported by the hardware.
15251 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15257 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15258 const X86TargetLowering *XTLI) {
15259 SDValue Op0 = N->getOperand(0);
15260 EVT InVT = Op0->getValueType(0);
15262 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15263 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15264 DebugLoc dl = N->getDebugLoc();
15265 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15266 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15267 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15270 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15271 // a 32-bit target where SSE doesn't support i64->FP operations.
15272 if (Op0.getOpcode() == ISD::LOAD) {
15273 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15274 EVT VT = Ld->getValueType(0);
15275 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15276 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15277 !XTLI->getSubtarget()->is64Bit() &&
15278 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15279 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15280 Ld->getChain(), Op0, DAG);
15281 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15288 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15289 EVT VT = N->getValueType(0);
15291 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15292 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15293 DebugLoc dl = N->getDebugLoc();
15294 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15295 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15296 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15302 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15303 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15304 X86TargetLowering::DAGCombinerInfo &DCI) {
15305 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15306 // the result is either zero or one (depending on the input carry bit).
15307 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15308 if (X86::isZeroNode(N->getOperand(0)) &&
15309 X86::isZeroNode(N->getOperand(1)) &&
15310 // We don't have a good way to replace an EFLAGS use, so only do this when
15312 SDValue(N, 1).use_empty()) {
15313 DebugLoc DL = N->getDebugLoc();
15314 EVT VT = N->getValueType(0);
15315 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15316 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15317 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15318 DAG.getConstant(X86::COND_B,MVT::i8),
15320 DAG.getConstant(1, VT));
15321 return DCI.CombineTo(N, Res1, CarryOut);
15327 // fold (add Y, (sete X, 0)) -> adc 0, Y
15328 // (add Y, (setne X, 0)) -> sbb -1, Y
15329 // (sub (sete X, 0), Y) -> sbb 0, Y
15330 // (sub (setne X, 0), Y) -> adc -1, Y
15331 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15332 DebugLoc DL = N->getDebugLoc();
15334 // Look through ZExts.
15335 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15336 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15339 SDValue SetCC = Ext.getOperand(0);
15340 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15343 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15344 if (CC != X86::COND_E && CC != X86::COND_NE)
15347 SDValue Cmp = SetCC.getOperand(1);
15348 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15349 !X86::isZeroNode(Cmp.getOperand(1)) ||
15350 !Cmp.getOperand(0).getValueType().isInteger())
15353 SDValue CmpOp0 = Cmp.getOperand(0);
15354 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15355 DAG.getConstant(1, CmpOp0.getValueType()));
15357 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15358 if (CC == X86::COND_NE)
15359 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15360 DL, OtherVal.getValueType(), OtherVal,
15361 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15362 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15363 DL, OtherVal.getValueType(), OtherVal,
15364 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15367 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15368 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15369 const X86Subtarget *Subtarget) {
15370 EVT VT = N->getValueType(0);
15371 SDValue Op0 = N->getOperand(0);
15372 SDValue Op1 = N->getOperand(1);
15374 // Try to synthesize horizontal adds from adds of shuffles.
15375 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15376 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15377 isHorizontalBinOp(Op0, Op1, true))
15378 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15380 return OptimizeConditionalInDecrement(N, DAG);
15383 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15384 const X86Subtarget *Subtarget) {
15385 SDValue Op0 = N->getOperand(0);
15386 SDValue Op1 = N->getOperand(1);
15388 // X86 can't encode an immediate LHS of a sub. See if we can push the
15389 // negation into a preceding instruction.
15390 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15391 // If the RHS of the sub is a XOR with one use and a constant, invert the
15392 // immediate. Then add one to the LHS of the sub so we can turn
15393 // X-Y -> X+~Y+1, saving one register.
15394 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15395 isa<ConstantSDNode>(Op1.getOperand(1))) {
15396 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15397 EVT VT = Op0.getValueType();
15398 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15400 DAG.getConstant(~XorC, VT));
15401 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15402 DAG.getConstant(C->getAPIntValue()+1, VT));
15406 // Try to synthesize horizontal adds from adds of shuffles.
15407 EVT VT = N->getValueType(0);
15408 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15409 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15410 isHorizontalBinOp(Op0, Op1, true))
15411 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15413 return OptimizeConditionalInDecrement(N, DAG);
15416 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15417 DAGCombinerInfo &DCI) const {
15418 SelectionDAG &DAG = DCI.DAG;
15419 switch (N->getOpcode()) {
15421 case ISD::EXTRACT_VECTOR_ELT:
15422 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15424 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15425 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15426 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15427 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15428 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15429 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15432 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15433 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15434 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15435 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15436 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
15437 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15438 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15439 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15440 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15441 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15442 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15444 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15445 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15446 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15447 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15448 case ISD::ANY_EXTEND:
15449 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15450 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15451 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15452 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15453 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15454 case X86ISD::SHUFP: // Handle all target specific shuffles
15455 case X86ISD::PALIGN:
15456 case X86ISD::UNPCKH:
15457 case X86ISD::UNPCKL:
15458 case X86ISD::MOVHLPS:
15459 case X86ISD::MOVLHPS:
15460 case X86ISD::PSHUFD:
15461 case X86ISD::PSHUFHW:
15462 case X86ISD::PSHUFLW:
15463 case X86ISD::MOVSS:
15464 case X86ISD::MOVSD:
15465 case X86ISD::VPERMILP:
15466 case X86ISD::VPERM2X128:
15467 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15473 /// isTypeDesirableForOp - Return true if the target has native support for
15474 /// the specified value type and it is 'desirable' to use the type for the
15475 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15476 /// instruction encodings are longer and some i16 instructions are slow.
15477 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15478 if (!isTypeLegal(VT))
15480 if (VT != MVT::i16)
15487 case ISD::SIGN_EXTEND:
15488 case ISD::ZERO_EXTEND:
15489 case ISD::ANY_EXTEND:
15502 /// IsDesirableToPromoteOp - This method query the target whether it is
15503 /// beneficial for dag combiner to promote the specified node. If true, it
15504 /// should return the desired promotion type by reference.
15505 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15506 EVT VT = Op.getValueType();
15507 if (VT != MVT::i16)
15510 bool Promote = false;
15511 bool Commute = false;
15512 switch (Op.getOpcode()) {
15515 LoadSDNode *LD = cast<LoadSDNode>(Op);
15516 // If the non-extending load has a single use and it's not live out, then it
15517 // might be folded.
15518 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15519 Op.hasOneUse()*/) {
15520 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15521 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15522 // The only case where we'd want to promote LOAD (rather then it being
15523 // promoted as an operand is when it's only use is liveout.
15524 if (UI->getOpcode() != ISD::CopyToReg)
15531 case ISD::SIGN_EXTEND:
15532 case ISD::ZERO_EXTEND:
15533 case ISD::ANY_EXTEND:
15538 SDValue N0 = Op.getOperand(0);
15539 // Look out for (store (shl (load), x)).
15540 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15553 SDValue N0 = Op.getOperand(0);
15554 SDValue N1 = Op.getOperand(1);
15555 if (!Commute && MayFoldLoad(N1))
15557 // Avoid disabling potential load folding opportunities.
15558 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15560 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15570 //===----------------------------------------------------------------------===//
15571 // X86 Inline Assembly Support
15572 //===----------------------------------------------------------------------===//
15575 // Helper to match a string separated by whitespace.
15576 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15577 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15579 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15580 StringRef piece(*args[i]);
15581 if (!s.startswith(piece)) // Check if the piece matches.
15584 s = s.substr(piece.size());
15585 StringRef::size_type pos = s.find_first_not_of(" \t");
15586 if (pos == 0) // We matched a prefix.
15594 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15597 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15598 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15600 std::string AsmStr = IA->getAsmString();
15602 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15603 if (!Ty || Ty->getBitWidth() % 16 != 0)
15606 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15607 SmallVector<StringRef, 4> AsmPieces;
15608 SplitString(AsmStr, AsmPieces, ";\n");
15610 switch (AsmPieces.size()) {
15611 default: return false;
15613 // FIXME: this should verify that we are targeting a 486 or better. If not,
15614 // we will turn this bswap into something that will be lowered to logical
15615 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15616 // lower so don't worry about this.
15618 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15619 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15620 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15621 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15622 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15623 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15624 // No need to check constraints, nothing other than the equivalent of
15625 // "=r,0" would be valid here.
15626 return IntrinsicLowering::LowerToByteSwap(CI);
15629 // rorw $$8, ${0:w} --> llvm.bswap.i16
15630 if (CI->getType()->isIntegerTy(16) &&
15631 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15632 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15633 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15635 const std::string &ConstraintsStr = IA->getConstraintString();
15636 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15637 std::sort(AsmPieces.begin(), AsmPieces.end());
15638 if (AsmPieces.size() == 4 &&
15639 AsmPieces[0] == "~{cc}" &&
15640 AsmPieces[1] == "~{dirflag}" &&
15641 AsmPieces[2] == "~{flags}" &&
15642 AsmPieces[3] == "~{fpsr}")
15643 return IntrinsicLowering::LowerToByteSwap(CI);
15647 if (CI->getType()->isIntegerTy(32) &&
15648 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15649 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15650 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15651 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15653 const std::string &ConstraintsStr = IA->getConstraintString();
15654 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15655 std::sort(AsmPieces.begin(), AsmPieces.end());
15656 if (AsmPieces.size() == 4 &&
15657 AsmPieces[0] == "~{cc}" &&
15658 AsmPieces[1] == "~{dirflag}" &&
15659 AsmPieces[2] == "~{flags}" &&
15660 AsmPieces[3] == "~{fpsr}")
15661 return IntrinsicLowering::LowerToByteSwap(CI);
15664 if (CI->getType()->isIntegerTy(64)) {
15665 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15666 if (Constraints.size() >= 2 &&
15667 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15668 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15669 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15670 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15671 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15672 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15673 return IntrinsicLowering::LowerToByteSwap(CI);
15683 /// getConstraintType - Given a constraint letter, return the type of
15684 /// constraint it is for this target.
15685 X86TargetLowering::ConstraintType
15686 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15687 if (Constraint.size() == 1) {
15688 switch (Constraint[0]) {
15699 return C_RegisterClass;
15723 return TargetLowering::getConstraintType(Constraint);
15726 /// Examine constraint type and operand type and determine a weight value.
15727 /// This object must already have been set up with the operand type
15728 /// and the current alternative constraint selected.
15729 TargetLowering::ConstraintWeight
15730 X86TargetLowering::getSingleConstraintMatchWeight(
15731 AsmOperandInfo &info, const char *constraint) const {
15732 ConstraintWeight weight = CW_Invalid;
15733 Value *CallOperandVal = info.CallOperandVal;
15734 // If we don't have a value, we can't do a match,
15735 // but allow it at the lowest weight.
15736 if (CallOperandVal == NULL)
15738 Type *type = CallOperandVal->getType();
15739 // Look at the constraint type.
15740 switch (*constraint) {
15742 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15753 if (CallOperandVal->getType()->isIntegerTy())
15754 weight = CW_SpecificReg;
15759 if (type->isFloatingPointTy())
15760 weight = CW_SpecificReg;
15763 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15764 weight = CW_SpecificReg;
15768 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15769 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15770 weight = CW_Register;
15773 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15774 if (C->getZExtValue() <= 31)
15775 weight = CW_Constant;
15779 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15780 if (C->getZExtValue() <= 63)
15781 weight = CW_Constant;
15785 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15786 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15787 weight = CW_Constant;
15791 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15792 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15793 weight = CW_Constant;
15797 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15798 if (C->getZExtValue() <= 3)
15799 weight = CW_Constant;
15803 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15804 if (C->getZExtValue() <= 0xff)
15805 weight = CW_Constant;
15810 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15811 weight = CW_Constant;
15815 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15816 if ((C->getSExtValue() >= -0x80000000LL) &&
15817 (C->getSExtValue() <= 0x7fffffffLL))
15818 weight = CW_Constant;
15822 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15823 if (C->getZExtValue() <= 0xffffffff)
15824 weight = CW_Constant;
15831 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15832 /// with another that has more specific requirements based on the type of the
15833 /// corresponding operand.
15834 const char *X86TargetLowering::
15835 LowerXConstraint(EVT ConstraintVT) const {
15836 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15837 // 'f' like normal targets.
15838 if (ConstraintVT.isFloatingPoint()) {
15839 if (Subtarget->hasSSE2())
15841 if (Subtarget->hasSSE1())
15845 return TargetLowering::LowerXConstraint(ConstraintVT);
15848 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15849 /// vector. If it is invalid, don't add anything to Ops.
15850 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15851 std::string &Constraint,
15852 std::vector<SDValue>&Ops,
15853 SelectionDAG &DAG) const {
15854 SDValue Result(0, 0);
15856 // Only support length 1 constraints for now.
15857 if (Constraint.length() > 1) return;
15859 char ConstraintLetter = Constraint[0];
15860 switch (ConstraintLetter) {
15863 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15864 if (C->getZExtValue() <= 31) {
15865 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15871 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15872 if (C->getZExtValue() <= 63) {
15873 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15879 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15880 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15881 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15887 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15888 if (C->getZExtValue() <= 255) {
15889 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15895 // 32-bit signed value
15896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15897 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15898 C->getSExtValue())) {
15899 // Widen to 64 bits here to get it sign extended.
15900 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15903 // FIXME gcc accepts some relocatable values here too, but only in certain
15904 // memory models; it's complicated.
15909 // 32-bit unsigned value
15910 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15911 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15912 C->getZExtValue())) {
15913 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15917 // FIXME gcc accepts some relocatable values here too, but only in certain
15918 // memory models; it's complicated.
15922 // Literal immediates are always ok.
15923 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15924 // Widen to 64 bits here to get it sign extended.
15925 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15929 // In any sort of PIC mode addresses need to be computed at runtime by
15930 // adding in a register or some sort of table lookup. These can't
15931 // be used as immediates.
15932 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15935 // If we are in non-pic codegen mode, we allow the address of a global (with
15936 // an optional displacement) to be used with 'i'.
15937 GlobalAddressSDNode *GA = 0;
15938 int64_t Offset = 0;
15940 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15942 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15943 Offset += GA->getOffset();
15945 } else if (Op.getOpcode() == ISD::ADD) {
15946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15947 Offset += C->getZExtValue();
15948 Op = Op.getOperand(0);
15951 } else if (Op.getOpcode() == ISD::SUB) {
15952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15953 Offset += -C->getZExtValue();
15954 Op = Op.getOperand(0);
15959 // Otherwise, this isn't something we can handle, reject it.
15963 const GlobalValue *GV = GA->getGlobal();
15964 // If we require an extra load to get this address, as in PIC mode, we
15965 // can't accept it.
15966 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15967 getTargetMachine())))
15970 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15971 GA->getValueType(0), Offset);
15976 if (Result.getNode()) {
15977 Ops.push_back(Result);
15980 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15983 std::pair<unsigned, const TargetRegisterClass*>
15984 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15986 // First, see if this is a constraint that directly corresponds to an LLVM
15988 if (Constraint.size() == 1) {
15989 // GCC Constraint Letters
15990 switch (Constraint[0]) {
15992 // TODO: Slight differences here in allocation order and leaving
15993 // RIP in the class. Do they matter any more here than they do
15994 // in the normal allocation?
15995 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15996 if (Subtarget->is64Bit()) {
15997 if (VT == MVT::i32 || VT == MVT::f32)
15998 return std::make_pair(0U, &X86::GR32RegClass);
15999 if (VT == MVT::i16)
16000 return std::make_pair(0U, &X86::GR16RegClass);
16001 if (VT == MVT::i8 || VT == MVT::i1)
16002 return std::make_pair(0U, &X86::GR8RegClass);
16003 if (VT == MVT::i64 || VT == MVT::f64)
16004 return std::make_pair(0U, &X86::GR64RegClass);
16007 // 32-bit fallthrough
16008 case 'Q': // Q_REGS
16009 if (VT == MVT::i32 || VT == MVT::f32)
16010 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
16011 if (VT == MVT::i16)
16012 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
16013 if (VT == MVT::i8 || VT == MVT::i1)
16014 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
16015 if (VT == MVT::i64)
16016 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
16018 case 'r': // GENERAL_REGS
16019 case 'l': // INDEX_REGS
16020 if (VT == MVT::i8 || VT == MVT::i1)
16021 return std::make_pair(0U, &X86::GR8RegClass);
16022 if (VT == MVT::i16)
16023 return std::make_pair(0U, &X86::GR16RegClass);
16024 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
16025 return std::make_pair(0U, &X86::GR32RegClass);
16026 return std::make_pair(0U, &X86::GR64RegClass);
16027 case 'R': // LEGACY_REGS
16028 if (VT == MVT::i8 || VT == MVT::i1)
16029 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
16030 if (VT == MVT::i16)
16031 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
16032 if (VT == MVT::i32 || !Subtarget->is64Bit())
16033 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
16034 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
16035 case 'f': // FP Stack registers.
16036 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
16037 // value to the correct fpstack register class.
16038 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
16039 return std::make_pair(0U, &X86::RFP32RegClass);
16040 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
16041 return std::make_pair(0U, &X86::RFP64RegClass);
16042 return std::make_pair(0U, &X86::RFP80RegClass);
16043 case 'y': // MMX_REGS if MMX allowed.
16044 if (!Subtarget->hasMMX()) break;
16045 return std::make_pair(0U, &X86::VR64RegClass);
16046 case 'Y': // SSE_REGS if SSE2 allowed
16047 if (!Subtarget->hasSSE2()) break;
16049 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
16050 if (!Subtarget->hasSSE1()) break;
16052 switch (VT.getSimpleVT().SimpleTy) {
16054 // Scalar SSE types.
16057 return std::make_pair(0U, &X86::FR32RegClass);
16060 return std::make_pair(0U, &X86::FR64RegClass);
16068 return std::make_pair(0U, &X86::VR128RegClass);
16076 return std::make_pair(0U, &X86::VR256RegClass);
16082 // Use the default implementation in TargetLowering to convert the register
16083 // constraint into a member of a register class.
16084 std::pair<unsigned, const TargetRegisterClass*> Res;
16085 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
16087 // Not found as a standard register?
16088 if (Res.second == 0) {
16089 // Map st(0) -> st(7) -> ST0
16090 if (Constraint.size() == 7 && Constraint[0] == '{' &&
16091 tolower(Constraint[1]) == 's' &&
16092 tolower(Constraint[2]) == 't' &&
16093 Constraint[3] == '(' &&
16094 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
16095 Constraint[5] == ')' &&
16096 Constraint[6] == '}') {
16098 Res.first = X86::ST0+Constraint[4]-'0';
16099 Res.second = &X86::RFP80RegClass;
16103 // GCC allows "st(0)" to be called just plain "st".
16104 if (StringRef("{st}").equals_lower(Constraint)) {
16105 Res.first = X86::ST0;
16106 Res.second = &X86::RFP80RegClass;
16111 if (StringRef("{flags}").equals_lower(Constraint)) {
16112 Res.first = X86::EFLAGS;
16113 Res.second = &X86::CCRRegClass;
16117 // 'A' means EAX + EDX.
16118 if (Constraint == "A") {
16119 Res.first = X86::EAX;
16120 Res.second = &X86::GR32_ADRegClass;
16126 // Otherwise, check to see if this is a register class of the wrong value
16127 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
16128 // turn into {ax},{dx}.
16129 if (Res.second->hasType(VT))
16130 return Res; // Correct type already, nothing to do.
16132 // All of the single-register GCC register classes map their values onto
16133 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16134 // really want an 8-bit or 32-bit register, map to the appropriate register
16135 // class and return the appropriate register.
16136 if (Res.second == &X86::GR16RegClass) {
16137 if (VT == MVT::i8) {
16138 unsigned DestReg = 0;
16139 switch (Res.first) {
16141 case X86::AX: DestReg = X86::AL; break;
16142 case X86::DX: DestReg = X86::DL; break;
16143 case X86::CX: DestReg = X86::CL; break;
16144 case X86::BX: DestReg = X86::BL; break;
16147 Res.first = DestReg;
16148 Res.second = &X86::GR8RegClass;
16150 } else if (VT == MVT::i32) {
16151 unsigned DestReg = 0;
16152 switch (Res.first) {
16154 case X86::AX: DestReg = X86::EAX; break;
16155 case X86::DX: DestReg = X86::EDX; break;
16156 case X86::CX: DestReg = X86::ECX; break;
16157 case X86::BX: DestReg = X86::EBX; break;
16158 case X86::SI: DestReg = X86::ESI; break;
16159 case X86::DI: DestReg = X86::EDI; break;
16160 case X86::BP: DestReg = X86::EBP; break;
16161 case X86::SP: DestReg = X86::ESP; break;
16164 Res.first = DestReg;
16165 Res.second = &X86::GR32RegClass;
16167 } else if (VT == MVT::i64) {
16168 unsigned DestReg = 0;
16169 switch (Res.first) {
16171 case X86::AX: DestReg = X86::RAX; break;
16172 case X86::DX: DestReg = X86::RDX; break;
16173 case X86::CX: DestReg = X86::RCX; break;
16174 case X86::BX: DestReg = X86::RBX; break;
16175 case X86::SI: DestReg = X86::RSI; break;
16176 case X86::DI: DestReg = X86::RDI; break;
16177 case X86::BP: DestReg = X86::RBP; break;
16178 case X86::SP: DestReg = X86::RSP; break;
16181 Res.first = DestReg;
16182 Res.second = &X86::GR64RegClass;
16185 } else if (Res.second == &X86::FR32RegClass ||
16186 Res.second == &X86::FR64RegClass ||
16187 Res.second == &X86::VR128RegClass) {
16188 // Handle references to XMM physical registers that got mapped into the
16189 // wrong class. This can happen with constraints like {xmm0} where the
16190 // target independent register mapper will just pick the first match it can
16191 // find, ignoring the required type.
16193 if (VT == MVT::f32 || VT == MVT::i32)
16194 Res.second = &X86::FR32RegClass;
16195 else if (VT == MVT::f64 || VT == MVT::i64)
16196 Res.second = &X86::FR64RegClass;
16197 else if (X86::VR128RegClass.hasType(VT))
16198 Res.second = &X86::VR128RegClass;
16199 else if (X86::VR256RegClass.hasType(VT))
16200 Res.second = &X86::VR256RegClass;