1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static SDValue Insert128BitVector(SDValue Result,
70 static SDValue Extract128BitVector(SDValue Vec,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
76 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
77 /// simple subregister reference. Idx is an index in the 128 bits we
78 /// want. It need not be aligned to a 128-bit bounday. That makes
79 /// lowering EXTRACT_VECTOR_ELT operations easier.
80 static SDValue Extract128BitVector(SDValue Vec,
84 EVT VT = Vec.getValueType();
85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
86 EVT ElVT = VT.getVectorElementType();
87 int Factor = VT.getSizeInBits()/128;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
95 if (isa<ConstantSDNode>(Idx)) {
96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
99 // we can match to VEXTRACTF128.
100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
102 // This is the index of the first element of the 128-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
117 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
118 /// sets things up to match to an AVX VINSERTF128 instruction or a
119 /// simple superregister reference. Idx is an index in the 128 bits
120 /// we want. It need not be aligned to a 128-bit bounday. That makes
121 /// lowering INSERT_VECTOR_ELT operations easier.
122 static SDValue Insert128BitVector(SDValue Result,
127 if (isa<ConstantSDNode>(Idx)) {
128 EVT VT = Vec.getValueType();
129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
131 EVT ElVT = VT.getVectorElementType();
132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
133 EVT ResultVT = Result.getValueType();
135 // Insert the relevant 128 bits.
136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
138 // This is the index of the first element of the 128-bit chunk
140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
152 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
154 bool is64Bit = Subtarget->is64Bit();
156 if (Subtarget->isTargetEnvMacho()) {
158 return new X8664_MachoTargetObjectFile();
159 return new TargetLoweringObjectFileMachO();
162 if (Subtarget->isTargetELF())
163 return new TargetLoweringObjectFileELF();
164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
165 return new TargetLoweringObjectFileCOFF();
166 llvm_unreachable("unknown subtarget type");
169 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<X86Subtarget>();
172 X86ScalarSSEf64 = Subtarget->hasXMMInt();
173 X86ScalarSSEf32 = Subtarget->hasXMM();
174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
176 RegInfo = TM.getRegisterInfo();
177 TD = getTargetData();
179 // Set up the TargetLowering object.
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
183 setBooleanContents(ZeroOrOneBooleanContent);
184 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
187 // For 64-bit since we have so many registers use the ILP scheduler, for
188 // 32-bit code use the register pressure specific scheduling.
189 if (Subtarget->is64Bit())
190 setSchedulingPreference(Sched::ILP);
192 setSchedulingPreference(Sched::RegPressure);
193 setStackPointerRegisterToSaveRestore(X86StackPtr);
195 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
196 // Setup Windows compiler runtime calls.
197 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
198 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
199 setLibcallName(RTLIB::SREM_I64, "_allrem");
200 setLibcallName(RTLIB::UREM_I64, "_aullrem");
201 setLibcallName(RTLIB::MUL_I64, "_allmul");
202 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
203 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
204 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
210 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
213 if (Subtarget->isTargetDarwin()) {
214 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
215 setUseUnderscoreSetJmp(false);
216 setUseUnderscoreLongJmp(false);
217 } else if (Subtarget->isTargetMingw()) {
218 // MS runtime is weird: it exports _setjmp, but longjmp!
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(false);
222 setUseUnderscoreSetJmp(true);
223 setUseUnderscoreLongJmp(true);
226 // Set up the register classes.
227 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
228 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
229 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
230 if (Subtarget->is64Bit())
231 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
235 // We don't accept any truncstore of integer registers.
236 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
239 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
241 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
243 // SETOEQ and SETUNE require checking two conditions.
244 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
249 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
257 if (Subtarget->is64Bit()) {
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
260 } else if (!TM.Options.UseSoftFloat) {
261 // We have an algorithm for SSE2->double, and we turn this into a
262 // 64-bit FILD followed by conditional FADD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
264 // We have an algorithm for SSE2, and we turn this into a 64-bit
265 // FILD for other targets.
266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
274 if (!TM.Options.UseSoftFloat) {
275 // SSE has no i16 to fp conversion, only i32
276 if (X86ScalarSSEf32) {
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 // f32 and f64 cases are Legal, f80 case is not
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
289 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
290 // are Legal, f80 is custom lowered.
291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
296 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
299 if (X86ScalarSSEf32) {
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
301 // f32 and f64 cases are Legal, f80 case is not
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 // Handle FP_TO_UINT by promoting the destination to a larger signed
310 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
314 if (Subtarget->is64Bit()) {
315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
317 } else if (!TM.Options.UseSoftFloat) {
318 // Since AVX is a superset of SSE3, only check for SSE here.
319 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
320 // Expand FP_TO_UINT into a select.
321 // FIXME: We would like to use a Custom expander here eventually to do
322 // the optimal thing for SSE vs. the default expansion in the legalizer.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
325 // With SSE3 we can use fisttpll to convert to a signed i64; without
326 // SSE, we're stuck with a fistpll.
327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
330 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
331 if (!X86ScalarSSEf64) {
332 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
333 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
334 if (Subtarget->is64Bit()) {
335 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
336 // Without SSE, i64->f64 goes through memory.
337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
341 // Scalar integer divide and remainder are lowered to use operations that
342 // produce two results, to match the available instructions. This exposes
343 // the two-result form to trivial CSE, which is able to combine x/y and x%y
344 // into a single instruction.
346 // Scalar integer multiply-high is also lowered to use two-result
347 // operations, to match the available instructions. However, plain multiply
348 // (low) operations are left as Legal, as there are single-result
349 // instructions for this in x86. Using the two-result multiply instructions
350 // when both high and low results are needed must be arranged by dagcombine.
351 for (unsigned i = 0, e = 4; i != e; ++i) {
353 setOperationAction(ISD::MULHS, VT, Expand);
354 setOperationAction(ISD::MULHU, VT, Expand);
355 setOperationAction(ISD::SDIV, VT, Expand);
356 setOperationAction(ISD::UDIV, VT, Expand);
357 setOperationAction(ISD::SREM, VT, Expand);
358 setOperationAction(ISD::UREM, VT, Expand);
360 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
361 setOperationAction(ISD::ADDC, VT, Custom);
362 setOperationAction(ISD::ADDE, VT, Custom);
363 setOperationAction(ISD::SUBC, VT, Custom);
364 setOperationAction(ISD::SUBE, VT, Custom);
367 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
368 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
369 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
370 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
371 if (Subtarget->is64Bit())
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
376 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f32 , Expand);
378 setOperationAction(ISD::FREM , MVT::f64 , Expand);
379 setOperationAction(ISD::FREM , MVT::f80 , Expand);
380 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Expand);
383 if (Subtarget->hasBMI()) {
384 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
386 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i8 , Expand);
394 if (Subtarget->hasLZCNT()) {
395 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
398 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
399 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
404 if (Subtarget->hasPOPCNT()) {
405 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
407 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
408 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
409 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
410 if (Subtarget->is64Bit())
411 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
414 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
415 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
417 // These should be promoted to a larger select which is supported.
418 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
419 // X86 wants to expand cmov itself.
420 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
421 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
422 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
423 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
424 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
425 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
426 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
427 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
428 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
429 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
430 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
431 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
434 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
436 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
439 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
440 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
441 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
442 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
445 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
446 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
449 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
450 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
451 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
452 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
454 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
455 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
456 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
457 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
458 if (Subtarget->is64Bit()) {
459 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
464 if (Subtarget->hasXMM())
465 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
467 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
468 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
470 // On X86 and X86-64, atomic operations are lowered to locked instructions.
471 // Locked instructions, in turn, have implicit fence semantics (all memory
472 // operations are flushed before issuing the locked instruction, and they
473 // are not buffered), so we can fold away the common pattern of
474 // fence-atomic-fence.
475 setShouldFoldAtomicFences(true);
477 // Expand certain atomics
478 for (unsigned i = 0, e = 4; i != e; ++i) {
480 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
481 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
482 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
485 if (!Subtarget->is64Bit()) {
486 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
487 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
488 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
489 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
490 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
491 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
492 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
493 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
496 if (Subtarget->hasCmpxchg16b()) {
497 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
500 // FIXME - use subtarget debug flags
501 if (!Subtarget->isTargetDarwin() &&
502 !Subtarget->isTargetELF() &&
503 !Subtarget->isTargetCygMing()) {
504 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
507 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
508 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
509 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
510 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
511 if (Subtarget->is64Bit()) {
512 setExceptionPointerRegister(X86::RAX);
513 setExceptionSelectorRegister(X86::RDX);
515 setExceptionPointerRegister(X86::EAX);
516 setExceptionSelectorRegister(X86::EDX);
518 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
519 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
521 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
522 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
524 setOperationAction(ISD::TRAP, MVT::Other, Legal);
526 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
527 setOperationAction(ISD::VASTART , MVT::Other, Custom);
528 setOperationAction(ISD::VAEND , MVT::Other, Expand);
529 if (Subtarget->is64Bit()) {
530 setOperationAction(ISD::VAARG , MVT::Other, Custom);
531 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
533 setOperationAction(ISD::VAARG , MVT::Other, Expand);
534 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
537 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
538 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
540 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
541 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
542 MVT::i64 : MVT::i32, Custom);
543 else if (TM.Options.EnableSegmentedStacks)
544 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
545 MVT::i64 : MVT::i32, Custom);
547 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
548 MVT::i64 : MVT::i32, Expand);
550 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
551 // f32 and f64 use SSE.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
554 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
556 // Use ANDPD to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f64, Custom);
558 setOperationAction(ISD::FABS , MVT::f32, Custom);
560 // Use XORP to simulate FNEG.
561 setOperationAction(ISD::FNEG , MVT::f64, Custom);
562 setOperationAction(ISD::FNEG , MVT::f32, Custom);
564 // Use ANDPD and ORPD to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // Lower this to FGETSIGNx86 plus an AND.
569 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
570 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f64, Expand);
574 setOperationAction(ISD::FCOS , MVT::f64, Expand);
575 setOperationAction(ISD::FSIN , MVT::f32, Expand);
576 setOperationAction(ISD::FCOS , MVT::f32, Expand);
578 // Expand FP immediates into loads from the stack, except for the special
580 addLegalFPImmediate(APFloat(+0.0)); // xorpd
581 addLegalFPImmediate(APFloat(+0.0f)); // xorps
582 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
583 // Use SSE for f32, x87 for f64.
584 // Set up the FP register classes.
585 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
586 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
588 // Use ANDPS to simulate FABS.
589 setOperationAction(ISD::FABS , MVT::f32, Custom);
591 // Use XORP to simulate FNEG.
592 setOperationAction(ISD::FNEG , MVT::f32, Custom);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 // Use ANDPS and ORPS to simulate FCOPYSIGN.
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
600 // We don't support sin/cos/fmod
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 // Special cases we handle for FP constants.
605 addLegalFPImmediate(APFloat(+0.0f)); // xorps
606 addLegalFPImmediate(APFloat(+0.0)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 if (!TM.Options.UnsafeFPMath) {
612 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
613 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
615 } else if (!TM.Options.UseSoftFloat) {
616 // f32 and f64 in x87.
617 // Set up the FP register classes.
618 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
619 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
621 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
622 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
623 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
624 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
626 if (!TM.Options.UnsafeFPMath) {
627 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
628 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
630 addLegalFPImmediate(APFloat(+0.0)); // FLD0
631 addLegalFPImmediate(APFloat(+1.0)); // FLD1
632 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
633 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
634 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
635 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
636 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
637 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
640 // We don't support FMA.
641 setOperationAction(ISD::FMA, MVT::f64, Expand);
642 setOperationAction(ISD::FMA, MVT::f32, Expand);
644 // Long double always uses X87.
645 if (!TM.Options.UseSoftFloat) {
646 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
647 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
648 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
650 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
651 addLegalFPImmediate(TmpFlt); // FLD0
653 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
656 APFloat TmpFlt2(+1.0);
657 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
659 addLegalFPImmediate(TmpFlt2); // FLD1
660 TmpFlt2.changeSign();
661 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
664 if (!TM.Options.UnsafeFPMath) {
665 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
666 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
669 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
670 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
671 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
672 setOperationAction(ISD::FRINT, MVT::f80, Expand);
673 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
674 setOperationAction(ISD::FMA, MVT::f80, Expand);
677 // Always use a library call for pow.
678 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
679 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
680 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
682 setOperationAction(ISD::FLOG, MVT::f80, Expand);
683 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
684 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
685 setOperationAction(ISD::FEXP, MVT::f80, Expand);
686 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
688 // First set operation action for all vector types to either promote
689 // (for widening) or expand (for scalarization). Then we will selectively
690 // turn on ones that can be effectively codegen'd.
691 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
692 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
693 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
708 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
710 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
711 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
745 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
750 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
751 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
752 setTruncStoreAction((MVT::SimpleValueType)VT,
753 (MVT::SimpleValueType)InnerVT, Expand);
754 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
755 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
756 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
759 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
760 // with -msoft-float, disable use of MMX as well.
761 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
762 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
763 // No operations on x86mmx supported, everything uses intrinsics.
766 // MMX-sized vectors (other than x86mmx) are expected to be expanded
767 // into smaller operations.
768 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
769 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
770 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
771 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
772 setOperationAction(ISD::AND, MVT::v8i8, Expand);
773 setOperationAction(ISD::AND, MVT::v4i16, Expand);
774 setOperationAction(ISD::AND, MVT::v2i32, Expand);
775 setOperationAction(ISD::AND, MVT::v1i64, Expand);
776 setOperationAction(ISD::OR, MVT::v8i8, Expand);
777 setOperationAction(ISD::OR, MVT::v4i16, Expand);
778 setOperationAction(ISD::OR, MVT::v2i32, Expand);
779 setOperationAction(ISD::OR, MVT::v1i64, Expand);
780 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
781 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
782 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
783 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
784 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
785 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
786 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
787 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
788 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
789 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
790 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
791 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
792 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
793 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
794 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
795 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
796 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
798 if (!TM.Options.UseSoftFloat && Subtarget->hasXMM()) {
799 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
801 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
802 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
803 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
804 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
805 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
806 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
807 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
808 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
809 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
810 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
811 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
812 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
815 if (!TM.Options.UseSoftFloat && Subtarget->hasXMMInt()) {
816 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
818 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
819 // registers cannot be used even for integer operations.
820 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
821 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
822 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
823 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
825 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
826 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
827 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
828 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
829 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
830 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
831 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
832 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
833 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
834 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
835 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
836 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
837 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
838 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
839 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
840 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
842 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
843 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
844 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
845 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
847 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
848 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
850 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
851 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
853 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
854 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
855 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
856 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
857 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
859 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
860 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
861 EVT VT = (MVT::SimpleValueType)i;
862 // Do not attempt to custom lower non-power-of-2 vectors
863 if (!isPowerOf2_32(VT.getVectorNumElements()))
865 // Do not attempt to custom lower non-128-bit vectors
866 if (!VT.is128BitVector())
868 setOperationAction(ISD::BUILD_VECTOR,
869 VT.getSimpleVT().SimpleTy, Custom);
870 setOperationAction(ISD::VECTOR_SHUFFLE,
871 VT.getSimpleVT().SimpleTy, Custom);
872 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
873 VT.getSimpleVT().SimpleTy, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
877 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
879 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
881 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
883 if (Subtarget->is64Bit()) {
884 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
888 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
889 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
890 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
893 // Do not attempt to promote non-128-bit vectors
894 if (!VT.is128BitVector())
897 setOperationAction(ISD::AND, SVT, Promote);
898 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
899 setOperationAction(ISD::OR, SVT, Promote);
900 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
901 setOperationAction(ISD::XOR, SVT, Promote);
902 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
903 setOperationAction(ISD::LOAD, SVT, Promote);
904 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
905 setOperationAction(ISD::SELECT, SVT, Promote);
906 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
909 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
911 // Custom lower v2i64 and v2f64 selects.
912 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
913 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
914 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
915 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
917 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
918 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
921 if (Subtarget->hasSSE41orAVX()) {
922 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
923 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
924 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
925 setOperationAction(ISD::FRINT, MVT::f32, Legal);
926 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
927 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
928 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
929 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
930 setOperationAction(ISD::FRINT, MVT::f64, Legal);
931 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
933 // FIXME: Do we need to handle scalar-to-vector here?
934 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
936 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
937 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
938 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
939 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
940 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
942 // i8 and i16 vectors are custom , because the source register and source
943 // source memory operand types are not the same width. f32 vectors are
944 // custom since the immediate controlling the insert encodes additional
946 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
947 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
948 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
949 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
951 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
952 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
953 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
954 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 // FIXME: these should be Legal but thats only for the case where
957 // the index is constant. For now custom expand to deal with that.
958 if (Subtarget->is64Bit()) {
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
960 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
964 if (Subtarget->hasXMMInt()) {
965 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
966 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
968 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
969 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
971 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
972 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
974 if (Subtarget->hasAVX2()) {
975 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
976 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
978 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
979 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
981 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
983 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
984 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
986 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
987 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
989 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
993 if (Subtarget->hasSSE42orAVX())
994 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
996 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
997 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
998 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
999 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1000 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1001 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1002 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1004 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1005 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1006 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1008 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1009 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1010 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1011 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1012 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1013 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1015 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1016 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1017 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1018 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1019 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1020 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1022 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1024 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1026 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1027 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1028 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1029 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1030 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1031 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1034 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1037 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1040 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1042 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1043 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1044 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1045 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1047 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1048 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1049 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1051 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1052 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1053 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1054 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1056 if (Subtarget->hasAVX2()) {
1057 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1058 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1059 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1060 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1062 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1063 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1064 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1065 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1067 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1068 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1069 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1070 // Don't lower v32i8 because there is no 128-bit byte mul
1072 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1074 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1075 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1078 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1080 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1082 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1083 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1084 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1085 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1087 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1088 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1089 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1090 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1092 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1093 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1094 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1095 // Don't lower v32i8 because there is no 128-bit byte mul
1097 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1098 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1100 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1103 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1106 // Custom lower several nodes for 256-bit types.
1107 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1108 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1109 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1112 // Extract subvector is special because the value type
1113 // (result) is 128-bit but the source is 256-bit wide.
1114 if (VT.is128BitVector())
1115 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1117 // Do not attempt to custom lower other non-256-bit vectors
1118 if (!VT.is256BitVector())
1121 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1122 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1123 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1124 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1125 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1126 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1129 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1130 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1131 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1134 // Do not attempt to promote non-256-bit vectors
1135 if (!VT.is256BitVector())
1138 setOperationAction(ISD::AND, SVT, Promote);
1139 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1140 setOperationAction(ISD::OR, SVT, Promote);
1141 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1142 setOperationAction(ISD::XOR, SVT, Promote);
1143 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1144 setOperationAction(ISD::LOAD, SVT, Promote);
1145 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1146 setOperationAction(ISD::SELECT, SVT, Promote);
1147 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1151 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1152 // of this type with custom code.
1153 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1154 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1155 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1159 // We want to custom lower some of our intrinsics.
1160 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1163 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1164 // handle type legalization for these operations here.
1166 // FIXME: We really should do custom legalization for addition and
1167 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1168 // than generic legalization for 64-bit multiplication-with-overflow, though.
1169 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1170 // Add/Sub/Mul with overflow operations are custom lowered.
1172 setOperationAction(ISD::SADDO, VT, Custom);
1173 setOperationAction(ISD::UADDO, VT, Custom);
1174 setOperationAction(ISD::SSUBO, VT, Custom);
1175 setOperationAction(ISD::USUBO, VT, Custom);
1176 setOperationAction(ISD::SMULO, VT, Custom);
1177 setOperationAction(ISD::UMULO, VT, Custom);
1180 // There are no 8-bit 3-address imul/mul instructions
1181 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1182 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1184 if (!Subtarget->is64Bit()) {
1185 // These libcalls are not available in 32-bit.
1186 setLibcallName(RTLIB::SHL_I128, 0);
1187 setLibcallName(RTLIB::SRL_I128, 0);
1188 setLibcallName(RTLIB::SRA_I128, 0);
1191 // We have target-specific dag combine patterns for the following nodes:
1192 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1193 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1194 setTargetDAGCombine(ISD::VSELECT);
1195 setTargetDAGCombine(ISD::SELECT);
1196 setTargetDAGCombine(ISD::SHL);
1197 setTargetDAGCombine(ISD::SRA);
1198 setTargetDAGCombine(ISD::SRL);
1199 setTargetDAGCombine(ISD::OR);
1200 setTargetDAGCombine(ISD::AND);
1201 setTargetDAGCombine(ISD::ADD);
1202 setTargetDAGCombine(ISD::FADD);
1203 setTargetDAGCombine(ISD::FSUB);
1204 setTargetDAGCombine(ISD::SUB);
1205 setTargetDAGCombine(ISD::LOAD);
1206 setTargetDAGCombine(ISD::STORE);
1207 setTargetDAGCombine(ISD::ZERO_EXTEND);
1208 setTargetDAGCombine(ISD::SINT_TO_FP);
1209 if (Subtarget->is64Bit())
1210 setTargetDAGCombine(ISD::MUL);
1211 if (Subtarget->hasBMI())
1212 setTargetDAGCombine(ISD::XOR);
1214 computeRegisterProperties();
1216 // On Darwin, -Os means optimize for size without hurting performance,
1217 // do not reduce the limit.
1218 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1219 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1220 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1221 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1222 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1223 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1224 setPrefLoopAlignment(4); // 2^4 bytes.
1225 benefitFromCodePlacementOpt = true;
1227 setPrefFunctionAlignment(4); // 2^4 bytes.
1231 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1232 if (!VT.isVector()) return MVT::i8;
1233 return VT.changeVectorElementTypeToInteger();
1237 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1238 /// the desired ByVal argument alignment.
1239 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1242 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1243 if (VTy->getBitWidth() == 128)
1245 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1246 unsigned EltAlign = 0;
1247 getMaxByValAlign(ATy->getElementType(), EltAlign);
1248 if (EltAlign > MaxAlign)
1249 MaxAlign = EltAlign;
1250 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1251 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1252 unsigned EltAlign = 0;
1253 getMaxByValAlign(STy->getElementType(i), EltAlign);
1254 if (EltAlign > MaxAlign)
1255 MaxAlign = EltAlign;
1263 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1264 /// function arguments in the caller parameter area. For X86, aggregates
1265 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1266 /// are at 4-byte boundaries.
1267 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1268 if (Subtarget->is64Bit()) {
1269 // Max of 8 and alignment of type.
1270 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1277 if (Subtarget->hasXMM())
1278 getMaxByValAlign(Ty, Align);
1282 /// getOptimalMemOpType - Returns the target specific optimal type for load
1283 /// and store operations as a result of memset, memcpy, and memmove
1284 /// lowering. If DstAlign is zero that means it's safe to destination
1285 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1286 /// means there isn't a need to check it against alignment requirement,
1287 /// probably because the source does not need to be loaded. If
1288 /// 'IsZeroVal' is true, that means it's safe to return a
1289 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1290 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1291 /// constant so it does not need to be loaded.
1292 /// It returns EVT::Other if the type should be determined using generic
1293 /// target-independent logic.
1295 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1296 unsigned DstAlign, unsigned SrcAlign,
1299 MachineFunction &MF) const {
1300 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1301 // linux. This is because the stack realignment code can't handle certain
1302 // cases like PR2962. This should be removed when PR2962 is fixed.
1303 const Function *F = MF.getFunction();
1305 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1307 (Subtarget->isUnalignedMemAccessFast() ||
1308 ((DstAlign == 0 || DstAlign >= 16) &&
1309 (SrcAlign == 0 || SrcAlign >= 16))) &&
1310 Subtarget->getStackAlignment() >= 16) {
1311 if (Subtarget->hasAVX() &&
1312 Subtarget->getStackAlignment() >= 32)
1314 if (Subtarget->hasXMMInt())
1316 if (Subtarget->hasXMM())
1318 } else if (!MemcpyStrSrc && Size >= 8 &&
1319 !Subtarget->is64Bit() &&
1320 Subtarget->getStackAlignment() >= 8 &&
1321 Subtarget->hasXMMInt()) {
1322 // Do not use f64 to lower memcpy if source is string constant. It's
1323 // better to use i32 to avoid the loads.
1327 if (Subtarget->is64Bit() && Size >= 8)
1332 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1333 /// current function. The returned value is a member of the
1334 /// MachineJumpTableInfo::JTEntryKind enum.
1335 unsigned X86TargetLowering::getJumpTableEncoding() const {
1336 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1338 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1339 Subtarget->isPICStyleGOT())
1340 return MachineJumpTableInfo::EK_Custom32;
1342 // Otherwise, use the normal jump table encoding heuristics.
1343 return TargetLowering::getJumpTableEncoding();
1347 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1348 const MachineBasicBlock *MBB,
1349 unsigned uid,MCContext &Ctx) const{
1350 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1351 Subtarget->isPICStyleGOT());
1352 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1354 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1355 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1358 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1360 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1361 SelectionDAG &DAG) const {
1362 if (!Subtarget->is64Bit())
1363 // This doesn't have DebugLoc associated with it, but is not really the
1364 // same as a Register.
1365 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1369 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1370 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1372 const MCExpr *X86TargetLowering::
1373 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1374 MCContext &Ctx) const {
1375 // X86-64 uses RIP relative addressing based on the jump table label.
1376 if (Subtarget->isPICStyleRIPRel())
1377 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1379 // Otherwise, the reference is relative to the PIC base.
1380 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1383 // FIXME: Why this routine is here? Move to RegInfo!
1384 std::pair<const TargetRegisterClass*, uint8_t>
1385 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1386 const TargetRegisterClass *RRC = 0;
1388 switch (VT.getSimpleVT().SimpleTy) {
1390 return TargetLowering::findRepresentativeClass(VT);
1391 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1392 RRC = (Subtarget->is64Bit()
1393 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1396 RRC = X86::VR64RegisterClass;
1398 case MVT::f32: case MVT::f64:
1399 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1400 case MVT::v4f32: case MVT::v2f64:
1401 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1403 RRC = X86::VR128RegisterClass;
1406 return std::make_pair(RRC, Cost);
1409 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1410 unsigned &Offset) const {
1411 if (!Subtarget->isTargetLinux())
1414 if (Subtarget->is64Bit()) {
1415 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1417 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1430 //===----------------------------------------------------------------------===//
1431 // Return Value Calling Convention Implementation
1432 //===----------------------------------------------------------------------===//
1434 #include "X86GenCallingConv.inc"
1437 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1438 MachineFunction &MF, bool isVarArg,
1439 const SmallVectorImpl<ISD::OutputArg> &Outs,
1440 LLVMContext &Context) const {
1441 SmallVector<CCValAssign, 16> RVLocs;
1442 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1444 return CCInfo.CheckReturn(Outs, RetCC_X86);
1448 X86TargetLowering::LowerReturn(SDValue Chain,
1449 CallingConv::ID CallConv, bool isVarArg,
1450 const SmallVectorImpl<ISD::OutputArg> &Outs,
1451 const SmallVectorImpl<SDValue> &OutVals,
1452 DebugLoc dl, SelectionDAG &DAG) const {
1453 MachineFunction &MF = DAG.getMachineFunction();
1454 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1456 SmallVector<CCValAssign, 16> RVLocs;
1457 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1458 RVLocs, *DAG.getContext());
1459 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1461 // Add the regs to the liveout set for the function.
1462 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1463 for (unsigned i = 0; i != RVLocs.size(); ++i)
1464 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1465 MRI.addLiveOut(RVLocs[i].getLocReg());
1469 SmallVector<SDValue, 6> RetOps;
1470 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1471 // Operand #1 = Bytes To Pop
1472 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1475 // Copy the result values into the output registers.
1476 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1477 CCValAssign &VA = RVLocs[i];
1478 assert(VA.isRegLoc() && "Can only return in registers!");
1479 SDValue ValToCopy = OutVals[i];
1480 EVT ValVT = ValToCopy.getValueType();
1482 // If this is x86-64, and we disabled SSE, we can't return FP values,
1483 // or SSE or MMX vectors.
1484 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1485 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1486 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1487 report_fatal_error("SSE register return with SSE disabled");
1489 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1490 // llvm-gcc has never done it right and no one has noticed, so this
1491 // should be OK for now.
1492 if (ValVT == MVT::f64 &&
1493 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1494 report_fatal_error("SSE2 register return with SSE2 disabled");
1496 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1497 // the RET instruction and handled by the FP Stackifier.
1498 if (VA.getLocReg() == X86::ST0 ||
1499 VA.getLocReg() == X86::ST1) {
1500 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1501 // change the value to the FP stack register class.
1502 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1503 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1504 RetOps.push_back(ValToCopy);
1505 // Don't emit a copytoreg.
1509 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1510 // which is returned in RAX / RDX.
1511 if (Subtarget->is64Bit()) {
1512 if (ValVT == MVT::x86mmx) {
1513 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1514 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1515 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1517 // If we don't have SSE2 available, convert to v4f32 so the generated
1518 // register is legal.
1519 if (!Subtarget->hasXMMInt())
1520 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1525 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1526 Flag = Chain.getValue(1);
1529 // The x86-64 ABI for returning structs by value requires that we copy
1530 // the sret argument into %rax for the return. We saved the argument into
1531 // a virtual register in the entry block, so now we copy the value out
1533 if (Subtarget->is64Bit() &&
1534 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1535 MachineFunction &MF = DAG.getMachineFunction();
1536 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1537 unsigned Reg = FuncInfo->getSRetReturnReg();
1539 "SRetReturnReg should have been set in LowerFormalArguments().");
1540 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1542 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1543 Flag = Chain.getValue(1);
1545 // RAX now acts like a return value.
1546 MRI.addLiveOut(X86::RAX);
1549 RetOps[0] = Chain; // Update chain.
1551 // Add the flag if we have it.
1553 RetOps.push_back(Flag);
1555 return DAG.getNode(X86ISD::RET_FLAG, dl,
1556 MVT::Other, &RetOps[0], RetOps.size());
1559 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1560 if (N->getNumValues() != 1)
1562 if (!N->hasNUsesOfValue(1, 0))
1565 SDNode *Copy = *N->use_begin();
1566 if (Copy->getOpcode() != ISD::CopyToReg &&
1567 Copy->getOpcode() != ISD::FP_EXTEND)
1570 bool HasRet = false;
1571 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1573 if (UI->getOpcode() != X86ISD::RET_FLAG)
1582 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1583 ISD::NodeType ExtendKind) const {
1585 // TODO: Is this also valid on 32-bit?
1586 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1587 ReturnMVT = MVT::i8;
1589 ReturnMVT = MVT::i32;
1591 EVT MinVT = getRegisterType(Context, ReturnMVT);
1592 return VT.bitsLT(MinVT) ? MinVT : VT;
1595 /// LowerCallResult - Lower the result values of a call into the
1596 /// appropriate copies out of appropriate physical registers.
1599 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1600 CallingConv::ID CallConv, bool isVarArg,
1601 const SmallVectorImpl<ISD::InputArg> &Ins,
1602 DebugLoc dl, SelectionDAG &DAG,
1603 SmallVectorImpl<SDValue> &InVals) const {
1605 // Assign locations to each value returned by this call.
1606 SmallVector<CCValAssign, 16> RVLocs;
1607 bool Is64Bit = Subtarget->is64Bit();
1608 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1609 getTargetMachine(), RVLocs, *DAG.getContext());
1610 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1612 // Copy all of the result registers out of their specified physreg.
1613 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1614 CCValAssign &VA = RVLocs[i];
1615 EVT CopyVT = VA.getValVT();
1617 // If this is x86-64, and we disabled SSE, we can't return FP values
1618 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1619 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1620 report_fatal_error("SSE register return with SSE disabled");
1625 // If this is a call to a function that returns an fp value on the floating
1626 // point stack, we must guarantee the the value is popped from the stack, so
1627 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1628 // if the return value is not used. We use the FpPOP_RETVAL instruction
1630 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1631 // If we prefer to use the value in xmm registers, copy it out as f80 and
1632 // use a truncate to move it from fp stack reg to xmm reg.
1633 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1634 SDValue Ops[] = { Chain, InFlag };
1635 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1636 MVT::Other, MVT::Glue, Ops, 2), 1);
1637 Val = Chain.getValue(0);
1639 // Round the f80 to the right size, which also moves it to the appropriate
1641 if (CopyVT != VA.getValVT())
1642 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1643 // This truncation won't change the value.
1644 DAG.getIntPtrConstant(1));
1646 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1647 CopyVT, InFlag).getValue(1);
1648 Val = Chain.getValue(0);
1650 InFlag = Chain.getValue(2);
1651 InVals.push_back(Val);
1658 //===----------------------------------------------------------------------===//
1659 // C & StdCall & Fast Calling Convention implementation
1660 //===----------------------------------------------------------------------===//
1661 // StdCall calling convention seems to be standard for many Windows' API
1662 // routines and around. It differs from C calling convention just a little:
1663 // callee should clean up the stack, not caller. Symbols should be also
1664 // decorated in some fancy way :) It doesn't support any vector arguments.
1665 // For info on fast calling convention see Fast Calling Convention (tail call)
1666 // implementation LowerX86_32FastCCCallTo.
1668 /// CallIsStructReturn - Determines whether a call uses struct return
1670 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1674 return Outs[0].Flags.isSRet();
1677 /// ArgsAreStructReturn - Determines whether a function uses struct
1678 /// return semantics.
1680 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1684 return Ins[0].Flags.isSRet();
1687 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1688 /// by "Src" to address "Dst" with size and alignment information specified by
1689 /// the specific parameter attribute. The copy will be passed as a byval
1690 /// function parameter.
1692 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1693 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1695 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1697 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1698 /*isVolatile*/false, /*AlwaysInline=*/true,
1699 MachinePointerInfo(), MachinePointerInfo());
1702 /// IsTailCallConvention - Return true if the calling convention is one that
1703 /// supports tail call optimization.
1704 static bool IsTailCallConvention(CallingConv::ID CC) {
1705 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1708 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1709 if (!CI->isTailCall())
1713 CallingConv::ID CalleeCC = CS.getCallingConv();
1714 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1720 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1721 /// a tailcall target by changing its ABI.
1722 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1723 bool GuaranteedTailCallOpt) {
1724 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1728 X86TargetLowering::LowerMemArgument(SDValue Chain,
1729 CallingConv::ID CallConv,
1730 const SmallVectorImpl<ISD::InputArg> &Ins,
1731 DebugLoc dl, SelectionDAG &DAG,
1732 const CCValAssign &VA,
1733 MachineFrameInfo *MFI,
1735 // Create the nodes corresponding to a load from this parameter slot.
1736 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1737 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1738 getTargetMachine().Options.GuaranteedTailCallOpt);
1739 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1742 // If value is passed by pointer we have address passed instead of the value
1744 if (VA.getLocInfo() == CCValAssign::Indirect)
1745 ValVT = VA.getLocVT();
1747 ValVT = VA.getValVT();
1749 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1750 // changed with more analysis.
1751 // In case of tail call optimization mark all arguments mutable. Since they
1752 // could be overwritten by lowering of arguments in case of a tail call.
1753 if (Flags.isByVal()) {
1754 unsigned Bytes = Flags.getByValSize();
1755 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1756 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1757 return DAG.getFrameIndex(FI, getPointerTy());
1759 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1760 VA.getLocMemOffset(), isImmutable);
1761 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1762 return DAG.getLoad(ValVT, dl, Chain, FIN,
1763 MachinePointerInfo::getFixedStack(FI),
1764 false, false, false, 0);
1769 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1770 CallingConv::ID CallConv,
1772 const SmallVectorImpl<ISD::InputArg> &Ins,
1775 SmallVectorImpl<SDValue> &InVals)
1777 MachineFunction &MF = DAG.getMachineFunction();
1778 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1780 const Function* Fn = MF.getFunction();
1781 if (Fn->hasExternalLinkage() &&
1782 Subtarget->isTargetCygMing() &&
1783 Fn->getName() == "main")
1784 FuncInfo->setForceFramePointer(true);
1786 MachineFrameInfo *MFI = MF.getFrameInfo();
1787 bool Is64Bit = Subtarget->is64Bit();
1788 bool IsWin64 = Subtarget->isTargetWin64();
1790 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1791 "Var args not supported with calling convention fastcc or ghc");
1793 // Assign locations to all of the incoming arguments.
1794 SmallVector<CCValAssign, 16> ArgLocs;
1795 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1796 ArgLocs, *DAG.getContext());
1798 // Allocate shadow area for Win64
1800 CCInfo.AllocateStack(32, 8);
1803 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1805 unsigned LastVal = ~0U;
1807 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1808 CCValAssign &VA = ArgLocs[i];
1809 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1811 assert(VA.getValNo() != LastVal &&
1812 "Don't support value assigned to multiple locs yet");
1814 LastVal = VA.getValNo();
1816 if (VA.isRegLoc()) {
1817 EVT RegVT = VA.getLocVT();
1818 TargetRegisterClass *RC = NULL;
1819 if (RegVT == MVT::i32)
1820 RC = X86::GR32RegisterClass;
1821 else if (Is64Bit && RegVT == MVT::i64)
1822 RC = X86::GR64RegisterClass;
1823 else if (RegVT == MVT::f32)
1824 RC = X86::FR32RegisterClass;
1825 else if (RegVT == MVT::f64)
1826 RC = X86::FR64RegisterClass;
1827 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1828 RC = X86::VR256RegisterClass;
1829 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1830 RC = X86::VR128RegisterClass;
1831 else if (RegVT == MVT::x86mmx)
1832 RC = X86::VR64RegisterClass;
1834 llvm_unreachable("Unknown argument type!");
1836 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1837 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1839 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1840 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1842 if (VA.getLocInfo() == CCValAssign::SExt)
1843 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1844 DAG.getValueType(VA.getValVT()));
1845 else if (VA.getLocInfo() == CCValAssign::ZExt)
1846 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1847 DAG.getValueType(VA.getValVT()));
1848 else if (VA.getLocInfo() == CCValAssign::BCvt)
1849 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1851 if (VA.isExtInLoc()) {
1852 // Handle MMX values passed in XMM regs.
1853 if (RegVT.isVector()) {
1854 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1857 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1860 assert(VA.isMemLoc());
1861 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1864 // If value is passed via pointer - do a load.
1865 if (VA.getLocInfo() == CCValAssign::Indirect)
1866 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1867 MachinePointerInfo(), false, false, false, 0);
1869 InVals.push_back(ArgValue);
1872 // The x86-64 ABI for returning structs by value requires that we copy
1873 // the sret argument into %rax for the return. Save the argument into
1874 // a virtual register so that we can access it from the return points.
1875 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1876 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1877 unsigned Reg = FuncInfo->getSRetReturnReg();
1879 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1880 FuncInfo->setSRetReturnReg(Reg);
1882 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1883 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1886 unsigned StackSize = CCInfo.getNextStackOffset();
1887 // Align stack specially for tail calls.
1888 if (FuncIsMadeTailCallSafe(CallConv,
1889 MF.getTarget().Options.GuaranteedTailCallOpt))
1890 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1892 // If the function takes variable number of arguments, make a frame index for
1893 // the start of the first vararg value... for expansion of llvm.va_start.
1895 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1896 CallConv != CallingConv::X86_ThisCall)) {
1897 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1900 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1902 // FIXME: We should really autogenerate these arrays
1903 static const unsigned GPR64ArgRegsWin64[] = {
1904 X86::RCX, X86::RDX, X86::R8, X86::R9
1906 static const unsigned GPR64ArgRegs64Bit[] = {
1907 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1909 static const unsigned XMMArgRegs64Bit[] = {
1910 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1911 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1913 const unsigned *GPR64ArgRegs;
1914 unsigned NumXMMRegs = 0;
1917 // The XMM registers which might contain var arg parameters are shadowed
1918 // in their paired GPR. So we only need to save the GPR to their home
1920 TotalNumIntRegs = 4;
1921 GPR64ArgRegs = GPR64ArgRegsWin64;
1923 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1924 GPR64ArgRegs = GPR64ArgRegs64Bit;
1926 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1929 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1932 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1933 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1934 "SSE register cannot be used when SSE is disabled!");
1935 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1936 NoImplicitFloatOps) &&
1937 "SSE register cannot be used when SSE is disabled!");
1938 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1939 !Subtarget->hasXMM())
1940 // Kernel mode asks for SSE to be disabled, so don't push them
1942 TotalNumXMMRegs = 0;
1945 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1946 // Get to the caller-allocated home save location. Add 8 to account
1947 // for the return address.
1948 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1949 FuncInfo->setRegSaveFrameIndex(
1950 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1951 // Fixup to set vararg frame on shadow area (4 x i64).
1953 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1955 // For X86-64, if there are vararg parameters that are passed via
1956 // registers, then we must store them to their spots on the stack so
1957 // they may be loaded by deferencing the result of va_next.
1958 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1959 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1960 FuncInfo->setRegSaveFrameIndex(
1961 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1965 // Store the integer parameter registers.
1966 SmallVector<SDValue, 8> MemOps;
1967 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1969 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1970 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1971 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1972 DAG.getIntPtrConstant(Offset));
1973 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1974 X86::GR64RegisterClass);
1975 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1977 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1978 MachinePointerInfo::getFixedStack(
1979 FuncInfo->getRegSaveFrameIndex(), Offset),
1981 MemOps.push_back(Store);
1985 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1986 // Now store the XMM (fp + vector) parameter registers.
1987 SmallVector<SDValue, 11> SaveXMMOps;
1988 SaveXMMOps.push_back(Chain);
1990 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1991 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1992 SaveXMMOps.push_back(ALVal);
1994 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1995 FuncInfo->getRegSaveFrameIndex()));
1996 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1997 FuncInfo->getVarArgsFPOffset()));
1999 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2000 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2001 X86::VR128RegisterClass);
2002 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2003 SaveXMMOps.push_back(Val);
2005 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2007 &SaveXMMOps[0], SaveXMMOps.size()));
2010 if (!MemOps.empty())
2011 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2012 &MemOps[0], MemOps.size());
2016 // Some CCs need callee pop.
2017 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2018 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2019 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2021 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2022 // If this is an sret function, the return should pop the hidden pointer.
2023 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
2024 FuncInfo->setBytesToPopOnReturn(4);
2028 // RegSaveFrameIndex is X86-64 only.
2029 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2030 if (CallConv == CallingConv::X86_FastCall ||
2031 CallConv == CallingConv::X86_ThisCall)
2032 // fastcc functions can't have varargs.
2033 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2036 FuncInfo->setArgumentStackSize(StackSize);
2042 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2043 SDValue StackPtr, SDValue Arg,
2044 DebugLoc dl, SelectionDAG &DAG,
2045 const CCValAssign &VA,
2046 ISD::ArgFlagsTy Flags) const {
2047 unsigned LocMemOffset = VA.getLocMemOffset();
2048 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2049 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2050 if (Flags.isByVal())
2051 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2053 return DAG.getStore(Chain, dl, Arg, PtrOff,
2054 MachinePointerInfo::getStack(LocMemOffset),
2058 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2059 /// optimization is performed and it is required.
2061 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2062 SDValue &OutRetAddr, SDValue Chain,
2063 bool IsTailCall, bool Is64Bit,
2064 int FPDiff, DebugLoc dl) const {
2065 // Adjust the Return address stack slot.
2066 EVT VT = getPointerTy();
2067 OutRetAddr = getReturnAddressFrameIndex(DAG);
2069 // Load the "old" Return address.
2070 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2071 false, false, false, 0);
2072 return SDValue(OutRetAddr.getNode(), 1);
2075 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2076 /// optimization is performed and it is required (FPDiff!=0).
2078 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2079 SDValue Chain, SDValue RetAddrFrIdx,
2080 bool Is64Bit, int FPDiff, DebugLoc dl) {
2081 // Store the return address to the appropriate stack slot.
2082 if (!FPDiff) return Chain;
2083 // Calculate the new stack slot for the return address.
2084 int SlotSize = Is64Bit ? 8 : 4;
2085 int NewReturnAddrFI =
2086 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2087 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2088 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2089 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2090 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2096 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2097 CallingConv::ID CallConv, bool isVarArg,
2099 const SmallVectorImpl<ISD::OutputArg> &Outs,
2100 const SmallVectorImpl<SDValue> &OutVals,
2101 const SmallVectorImpl<ISD::InputArg> &Ins,
2102 DebugLoc dl, SelectionDAG &DAG,
2103 SmallVectorImpl<SDValue> &InVals) const {
2104 MachineFunction &MF = DAG.getMachineFunction();
2105 bool Is64Bit = Subtarget->is64Bit();
2106 bool IsWin64 = Subtarget->isTargetWin64();
2107 bool IsStructRet = CallIsStructReturn(Outs);
2108 bool IsSibcall = false;
2111 // Check if it's really possible to do a tail call.
2112 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2113 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2114 Outs, OutVals, Ins, DAG);
2116 // Sibcalls are automatically detected tailcalls which do not require
2118 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2125 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2126 "Var args not supported with calling convention fastcc or ghc");
2128 // Analyze operands of the call, assigning locations to each operand.
2129 SmallVector<CCValAssign, 16> ArgLocs;
2130 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2131 ArgLocs, *DAG.getContext());
2133 // Allocate shadow area for Win64
2135 CCInfo.AllocateStack(32, 8);
2138 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2140 // Get a count of how many bytes are to be pushed on the stack.
2141 unsigned NumBytes = CCInfo.getNextStackOffset();
2143 // This is a sibcall. The memory operands are available in caller's
2144 // own caller's stack.
2146 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2147 IsTailCallConvention(CallConv))
2148 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2151 if (isTailCall && !IsSibcall) {
2152 // Lower arguments at fp - stackoffset + fpdiff.
2153 unsigned NumBytesCallerPushed =
2154 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2155 FPDiff = NumBytesCallerPushed - NumBytes;
2157 // Set the delta of movement of the returnaddr stackslot.
2158 // But only set if delta is greater than previous delta.
2159 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2160 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2164 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2166 SDValue RetAddrFrIdx;
2167 // Load return address for tail calls.
2168 if (isTailCall && FPDiff)
2169 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2170 Is64Bit, FPDiff, dl);
2172 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2173 SmallVector<SDValue, 8> MemOpChains;
2176 // Walk the register/memloc assignments, inserting copies/loads. In the case
2177 // of tail call optimization arguments are handle later.
2178 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2179 CCValAssign &VA = ArgLocs[i];
2180 EVT RegVT = VA.getLocVT();
2181 SDValue Arg = OutVals[i];
2182 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2183 bool isByVal = Flags.isByVal();
2185 // Promote the value if needed.
2186 switch (VA.getLocInfo()) {
2187 default: llvm_unreachable("Unknown loc info!");
2188 case CCValAssign::Full: break;
2189 case CCValAssign::SExt:
2190 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2192 case CCValAssign::ZExt:
2193 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2195 case CCValAssign::AExt:
2196 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2197 // Special case: passing MMX values in XMM registers.
2198 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2199 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2200 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2202 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2204 case CCValAssign::BCvt:
2205 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2207 case CCValAssign::Indirect: {
2208 // Store the argument.
2209 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2210 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2211 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2212 MachinePointerInfo::getFixedStack(FI),
2219 if (VA.isRegLoc()) {
2220 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2221 if (isVarArg && IsWin64) {
2222 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2223 // shadow reg if callee is a varargs function.
2224 unsigned ShadowReg = 0;
2225 switch (VA.getLocReg()) {
2226 case X86::XMM0: ShadowReg = X86::RCX; break;
2227 case X86::XMM1: ShadowReg = X86::RDX; break;
2228 case X86::XMM2: ShadowReg = X86::R8; break;
2229 case X86::XMM3: ShadowReg = X86::R9; break;
2232 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2234 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2235 assert(VA.isMemLoc());
2236 if (StackPtr.getNode() == 0)
2237 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2238 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2239 dl, DAG, VA, Flags));
2243 if (!MemOpChains.empty())
2244 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2245 &MemOpChains[0], MemOpChains.size());
2247 // Build a sequence of copy-to-reg nodes chained together with token chain
2248 // and flag operands which copy the outgoing args into registers.
2250 // Tail call byval lowering might overwrite argument registers so in case of
2251 // tail call optimization the copies to registers are lowered later.
2253 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2254 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2255 RegsToPass[i].second, InFlag);
2256 InFlag = Chain.getValue(1);
2259 if (Subtarget->isPICStyleGOT()) {
2260 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2263 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2264 DAG.getNode(X86ISD::GlobalBaseReg,
2265 DebugLoc(), getPointerTy()),
2267 InFlag = Chain.getValue(1);
2269 // If we are tail calling and generating PIC/GOT style code load the
2270 // address of the callee into ECX. The value in ecx is used as target of
2271 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2272 // for tail calls on PIC/GOT architectures. Normally we would just put the
2273 // address of GOT into ebx and then call target@PLT. But for tail calls
2274 // ebx would be restored (since ebx is callee saved) before jumping to the
2277 // Note: The actual moving to ECX is done further down.
2278 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2279 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2280 !G->getGlobal()->hasProtectedVisibility())
2281 Callee = LowerGlobalAddress(Callee, DAG);
2282 else if (isa<ExternalSymbolSDNode>(Callee))
2283 Callee = LowerExternalSymbol(Callee, DAG);
2287 if (Is64Bit && isVarArg && !IsWin64) {
2288 // From AMD64 ABI document:
2289 // For calls that may call functions that use varargs or stdargs
2290 // (prototype-less calls or calls to functions containing ellipsis (...) in
2291 // the declaration) %al is used as hidden argument to specify the number
2292 // of SSE registers used. The contents of %al do not need to match exactly
2293 // the number of registers, but must be an ubound on the number of SSE
2294 // registers used and is in the range 0 - 8 inclusive.
2296 // Count the number of XMM registers allocated.
2297 static const unsigned XMMArgRegs[] = {
2298 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2299 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2301 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2302 assert((Subtarget->hasXMM() || !NumXMMRegs)
2303 && "SSE registers cannot be used when SSE is disabled");
2305 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2306 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2307 InFlag = Chain.getValue(1);
2311 // For tail calls lower the arguments to the 'real' stack slot.
2313 // Force all the incoming stack arguments to be loaded from the stack
2314 // before any new outgoing arguments are stored to the stack, because the
2315 // outgoing stack slots may alias the incoming argument stack slots, and
2316 // the alias isn't otherwise explicit. This is slightly more conservative
2317 // than necessary, because it means that each store effectively depends
2318 // on every argument instead of just those arguments it would clobber.
2319 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2321 SmallVector<SDValue, 8> MemOpChains2;
2324 // Do not flag preceding copytoreg stuff together with the following stuff.
2326 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2327 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2328 CCValAssign &VA = ArgLocs[i];
2331 assert(VA.isMemLoc());
2332 SDValue Arg = OutVals[i];
2333 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2334 // Create frame index.
2335 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2336 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2337 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2338 FIN = DAG.getFrameIndex(FI, getPointerTy());
2340 if (Flags.isByVal()) {
2341 // Copy relative to framepointer.
2342 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2343 if (StackPtr.getNode() == 0)
2344 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2346 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2348 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2352 // Store relative to framepointer.
2353 MemOpChains2.push_back(
2354 DAG.getStore(ArgChain, dl, Arg, FIN,
2355 MachinePointerInfo::getFixedStack(FI),
2361 if (!MemOpChains2.empty())
2362 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2363 &MemOpChains2[0], MemOpChains2.size());
2365 // Copy arguments to their registers.
2366 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2367 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2368 RegsToPass[i].second, InFlag);
2369 InFlag = Chain.getValue(1);
2373 // Store the return address to the appropriate stack slot.
2374 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2378 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2379 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2380 // In the 64-bit large code model, we have to make all calls
2381 // through a register, since the call instruction's 32-bit
2382 // pc-relative offset may not be large enough to hold the whole
2384 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2385 // If the callee is a GlobalAddress node (quite common, every direct call
2386 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2389 // We should use extra load for direct calls to dllimported functions in
2391 const GlobalValue *GV = G->getGlobal();
2392 if (!GV->hasDLLImportLinkage()) {
2393 unsigned char OpFlags = 0;
2394 bool ExtraLoad = false;
2395 unsigned WrapperKind = ISD::DELETED_NODE;
2397 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2398 // external symbols most go through the PLT in PIC mode. If the symbol
2399 // has hidden or protected visibility, or if it is static or local, then
2400 // we don't need to use the PLT - we can directly call it.
2401 if (Subtarget->isTargetELF() &&
2402 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2403 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2404 OpFlags = X86II::MO_PLT;
2405 } else if (Subtarget->isPICStyleStubAny() &&
2406 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2407 (!Subtarget->getTargetTriple().isMacOSX() ||
2408 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2409 // PC-relative references to external symbols should go through $stub,
2410 // unless we're building with the leopard linker or later, which
2411 // automatically synthesizes these stubs.
2412 OpFlags = X86II::MO_DARWIN_STUB;
2413 } else if (Subtarget->isPICStyleRIPRel() &&
2414 isa<Function>(GV) &&
2415 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2416 // If the function is marked as non-lazy, generate an indirect call
2417 // which loads from the GOT directly. This avoids runtime overhead
2418 // at the cost of eager binding (and one extra byte of encoding).
2419 OpFlags = X86II::MO_GOTPCREL;
2420 WrapperKind = X86ISD::WrapperRIP;
2424 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2425 G->getOffset(), OpFlags);
2427 // Add a wrapper if needed.
2428 if (WrapperKind != ISD::DELETED_NODE)
2429 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2430 // Add extra indirection if needed.
2432 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2433 MachinePointerInfo::getGOT(),
2434 false, false, false, 0);
2436 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2437 unsigned char OpFlags = 0;
2439 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2440 // external symbols should go through the PLT.
2441 if (Subtarget->isTargetELF() &&
2442 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2443 OpFlags = X86II::MO_PLT;
2444 } else if (Subtarget->isPICStyleStubAny() &&
2445 (!Subtarget->getTargetTriple().isMacOSX() ||
2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2447 // PC-relative references to external symbols should go through $stub,
2448 // unless we're building with the leopard linker or later, which
2449 // automatically synthesizes these stubs.
2450 OpFlags = X86II::MO_DARWIN_STUB;
2453 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2457 // Returns a chain & a flag for retval copy to use.
2458 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2459 SmallVector<SDValue, 8> Ops;
2461 if (!IsSibcall && isTailCall) {
2462 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2463 DAG.getIntPtrConstant(0, true), InFlag);
2464 InFlag = Chain.getValue(1);
2467 Ops.push_back(Chain);
2468 Ops.push_back(Callee);
2471 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2473 // Add argument registers to the end of the list so that they are known live
2475 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2476 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2477 RegsToPass[i].second.getValueType()));
2479 // Add an implicit use GOT pointer in EBX.
2480 if (!isTailCall && Subtarget->isPICStyleGOT())
2481 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2483 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2484 if (Is64Bit && isVarArg && !IsWin64)
2485 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2487 if (InFlag.getNode())
2488 Ops.push_back(InFlag);
2492 //// If this is the first return lowered for this function, add the regs
2493 //// to the liveout set for the function.
2494 // This isn't right, although it's probably harmless on x86; liveouts
2495 // should be computed from returns not tail calls. Consider a void
2496 // function making a tail call to a function returning int.
2497 return DAG.getNode(X86ISD::TC_RETURN, dl,
2498 NodeTys, &Ops[0], Ops.size());
2501 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2502 InFlag = Chain.getValue(1);
2504 // Create the CALLSEQ_END node.
2505 unsigned NumBytesForCalleeToPush;
2506 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2507 getTargetMachine().Options.GuaranteedTailCallOpt))
2508 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2509 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2510 // If this is a call to a struct-return function, the callee
2511 // pops the hidden struct pointer, so we have to push it back.
2512 // This is common for Darwin/X86, Linux & Mingw32 targets.
2513 NumBytesForCalleeToPush = 4;
2515 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2517 // Returns a flag for retval copy to use.
2519 Chain = DAG.getCALLSEQ_END(Chain,
2520 DAG.getIntPtrConstant(NumBytes, true),
2521 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2524 InFlag = Chain.getValue(1);
2527 // Handle result values, copying them out of physregs into vregs that we
2529 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2530 Ins, dl, DAG, InVals);
2534 //===----------------------------------------------------------------------===//
2535 // Fast Calling Convention (tail call) implementation
2536 //===----------------------------------------------------------------------===//
2538 // Like std call, callee cleans arguments, convention except that ECX is
2539 // reserved for storing the tail called function address. Only 2 registers are
2540 // free for argument passing (inreg). Tail call optimization is performed
2542 // * tailcallopt is enabled
2543 // * caller/callee are fastcc
2544 // On X86_64 architecture with GOT-style position independent code only local
2545 // (within module) calls are supported at the moment.
2546 // To keep the stack aligned according to platform abi the function
2547 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2548 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2549 // If a tail called function callee has more arguments than the caller the
2550 // caller needs to make sure that there is room to move the RETADDR to. This is
2551 // achieved by reserving an area the size of the argument delta right after the
2552 // original REtADDR, but before the saved framepointer or the spilled registers
2553 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2565 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2566 /// for a 16 byte align requirement.
2568 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2569 SelectionDAG& DAG) const {
2570 MachineFunction &MF = DAG.getMachineFunction();
2571 const TargetMachine &TM = MF.getTarget();
2572 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2573 unsigned StackAlignment = TFI.getStackAlignment();
2574 uint64_t AlignMask = StackAlignment - 1;
2575 int64_t Offset = StackSize;
2576 uint64_t SlotSize = TD->getPointerSize();
2577 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2578 // Number smaller than 12 so just add the difference.
2579 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2581 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2582 Offset = ((~AlignMask) & Offset) + StackAlignment +
2583 (StackAlignment-SlotSize);
2588 /// MatchingStackOffset - Return true if the given stack call argument is
2589 /// already available in the same position (relatively) of the caller's
2590 /// incoming argument stack.
2592 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2593 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2594 const X86InstrInfo *TII) {
2595 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2597 if (Arg.getOpcode() == ISD::CopyFromReg) {
2598 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2599 if (!TargetRegisterInfo::isVirtualRegister(VR))
2601 MachineInstr *Def = MRI->getVRegDef(VR);
2604 if (!Flags.isByVal()) {
2605 if (!TII->isLoadFromStackSlot(Def, FI))
2608 unsigned Opcode = Def->getOpcode();
2609 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2610 Def->getOperand(1).isFI()) {
2611 FI = Def->getOperand(1).getIndex();
2612 Bytes = Flags.getByValSize();
2616 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2617 if (Flags.isByVal())
2618 // ByVal argument is passed in as a pointer but it's now being
2619 // dereferenced. e.g.
2620 // define @foo(%struct.X* %A) {
2621 // tail call @bar(%struct.X* byval %A)
2624 SDValue Ptr = Ld->getBasePtr();
2625 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2628 FI = FINode->getIndex();
2629 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2630 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2631 FI = FINode->getIndex();
2632 Bytes = Flags.getByValSize();
2636 assert(FI != INT_MAX);
2637 if (!MFI->isFixedObjectIndex(FI))
2639 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2642 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2643 /// for tail call optimization. Targets which want to do tail call
2644 /// optimization should implement this function.
2646 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2647 CallingConv::ID CalleeCC,
2649 bool isCalleeStructRet,
2650 bool isCallerStructRet,
2651 const SmallVectorImpl<ISD::OutputArg> &Outs,
2652 const SmallVectorImpl<SDValue> &OutVals,
2653 const SmallVectorImpl<ISD::InputArg> &Ins,
2654 SelectionDAG& DAG) const {
2655 if (!IsTailCallConvention(CalleeCC) &&
2656 CalleeCC != CallingConv::C)
2659 // If -tailcallopt is specified, make fastcc functions tail-callable.
2660 const MachineFunction &MF = DAG.getMachineFunction();
2661 const Function *CallerF = DAG.getMachineFunction().getFunction();
2662 CallingConv::ID CallerCC = CallerF->getCallingConv();
2663 bool CCMatch = CallerCC == CalleeCC;
2665 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2666 if (IsTailCallConvention(CalleeCC) && CCMatch)
2671 // Look for obvious safe cases to perform tail call optimization that do not
2672 // require ABI changes. This is what gcc calls sibcall.
2674 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2675 // emit a special epilogue.
2676 if (RegInfo->needsStackRealignment(MF))
2679 // Also avoid sibcall optimization if either caller or callee uses struct
2680 // return semantics.
2681 if (isCalleeStructRet || isCallerStructRet)
2684 // An stdcall caller is expected to clean up its arguments; the callee
2685 // isn't going to do that.
2686 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2689 // Do not sibcall optimize vararg calls unless all arguments are passed via
2691 if (isVarArg && !Outs.empty()) {
2693 // Optimizing for varargs on Win64 is unlikely to be safe without
2694 // additional testing.
2695 if (Subtarget->isTargetWin64())
2698 SmallVector<CCValAssign, 16> ArgLocs;
2699 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2700 getTargetMachine(), ArgLocs, *DAG.getContext());
2702 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2703 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2704 if (!ArgLocs[i].isRegLoc())
2708 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2709 // stack. Therefore, if it's not used by the call it is not safe to optimize
2710 // this into a sibcall.
2711 bool Unused = false;
2712 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2719 SmallVector<CCValAssign, 16> RVLocs;
2720 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2721 getTargetMachine(), RVLocs, *DAG.getContext());
2722 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2723 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2724 CCValAssign &VA = RVLocs[i];
2725 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2730 // If the calling conventions do not match, then we'd better make sure the
2731 // results are returned in the same way as what the caller expects.
2733 SmallVector<CCValAssign, 16> RVLocs1;
2734 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2735 getTargetMachine(), RVLocs1, *DAG.getContext());
2736 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2738 SmallVector<CCValAssign, 16> RVLocs2;
2739 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2740 getTargetMachine(), RVLocs2, *DAG.getContext());
2741 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2743 if (RVLocs1.size() != RVLocs2.size())
2745 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2746 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2748 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2750 if (RVLocs1[i].isRegLoc()) {
2751 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2754 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2760 // If the callee takes no arguments then go on to check the results of the
2762 if (!Outs.empty()) {
2763 // Check if stack adjustment is needed. For now, do not do this if any
2764 // argument is passed on the stack.
2765 SmallVector<CCValAssign, 16> ArgLocs;
2766 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2767 getTargetMachine(), ArgLocs, *DAG.getContext());
2769 // Allocate shadow area for Win64
2770 if (Subtarget->isTargetWin64()) {
2771 CCInfo.AllocateStack(32, 8);
2774 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2775 if (CCInfo.getNextStackOffset()) {
2776 MachineFunction &MF = DAG.getMachineFunction();
2777 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2780 // Check if the arguments are already laid out in the right way as
2781 // the caller's fixed stack objects.
2782 MachineFrameInfo *MFI = MF.getFrameInfo();
2783 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2784 const X86InstrInfo *TII =
2785 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2786 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2787 CCValAssign &VA = ArgLocs[i];
2788 SDValue Arg = OutVals[i];
2789 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2790 if (VA.getLocInfo() == CCValAssign::Indirect)
2792 if (!VA.isRegLoc()) {
2793 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2800 // If the tailcall address may be in a register, then make sure it's
2801 // possible to register allocate for it. In 32-bit, the call address can
2802 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2803 // callee-saved registers are restored. These happen to be the same
2804 // registers used to pass 'inreg' arguments so watch out for those.
2805 if (!Subtarget->is64Bit() &&
2806 !isa<GlobalAddressSDNode>(Callee) &&
2807 !isa<ExternalSymbolSDNode>(Callee)) {
2808 unsigned NumInRegs = 0;
2809 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2810 CCValAssign &VA = ArgLocs[i];
2813 unsigned Reg = VA.getLocReg();
2816 case X86::EAX: case X86::EDX: case X86::ECX:
2817 if (++NumInRegs == 3)
2829 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2830 return X86::createFastISel(funcInfo);
2834 //===----------------------------------------------------------------------===//
2835 // Other Lowering Hooks
2836 //===----------------------------------------------------------------------===//
2838 static bool MayFoldLoad(SDValue Op) {
2839 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2842 static bool MayFoldIntoStore(SDValue Op) {
2843 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2846 static bool isTargetShuffle(unsigned Opcode) {
2848 default: return false;
2849 case X86ISD::PSHUFD:
2850 case X86ISD::PSHUFHW:
2851 case X86ISD::PSHUFLW:
2852 case X86ISD::SHUFPD:
2853 case X86ISD::PALIGN:
2854 case X86ISD::SHUFPS:
2855 case X86ISD::MOVLHPS:
2856 case X86ISD::MOVLHPD:
2857 case X86ISD::MOVHLPS:
2858 case X86ISD::MOVLPS:
2859 case X86ISD::MOVLPD:
2860 case X86ISD::MOVSHDUP:
2861 case X86ISD::MOVSLDUP:
2862 case X86ISD::MOVDDUP:
2865 case X86ISD::UNPCKL:
2866 case X86ISD::UNPCKH:
2867 case X86ISD::VPERMILP:
2868 case X86ISD::VPERM2X128:
2874 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2875 SDValue V1, SelectionDAG &DAG) {
2877 default: llvm_unreachable("Unknown x86 shuffle node");
2878 case X86ISD::MOVSHDUP:
2879 case X86ISD::MOVSLDUP:
2880 case X86ISD::MOVDDUP:
2881 return DAG.getNode(Opc, dl, VT, V1);
2887 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2888 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2890 default: llvm_unreachable("Unknown x86 shuffle node");
2891 case X86ISD::PSHUFD:
2892 case X86ISD::PSHUFHW:
2893 case X86ISD::PSHUFLW:
2894 case X86ISD::VPERMILP:
2895 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2901 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2902 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2904 default: llvm_unreachable("Unknown x86 shuffle node");
2905 case X86ISD::PALIGN:
2906 case X86ISD::SHUFPD:
2907 case X86ISD::SHUFPS:
2908 case X86ISD::VPERM2X128:
2909 return DAG.getNode(Opc, dl, VT, V1, V2,
2910 DAG.getConstant(TargetMask, MVT::i8));
2915 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2916 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2918 default: llvm_unreachable("Unknown x86 shuffle node");
2919 case X86ISD::MOVLHPS:
2920 case X86ISD::MOVLHPD:
2921 case X86ISD::MOVHLPS:
2922 case X86ISD::MOVLPS:
2923 case X86ISD::MOVLPD:
2926 case X86ISD::UNPCKL:
2927 case X86ISD::UNPCKH:
2928 return DAG.getNode(Opc, dl, VT, V1, V2);
2933 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2934 MachineFunction &MF = DAG.getMachineFunction();
2935 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2936 int ReturnAddrIndex = FuncInfo->getRAIndex();
2938 if (ReturnAddrIndex == 0) {
2939 // Set up a frame object for the return address.
2940 uint64_t SlotSize = TD->getPointerSize();
2941 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2943 FuncInfo->setRAIndex(ReturnAddrIndex);
2946 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2950 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2951 bool hasSymbolicDisplacement) {
2952 // Offset should fit into 32 bit immediate field.
2953 if (!isInt<32>(Offset))
2956 // If we don't have a symbolic displacement - we don't have any extra
2958 if (!hasSymbolicDisplacement)
2961 // FIXME: Some tweaks might be needed for medium code model.
2962 if (M != CodeModel::Small && M != CodeModel::Kernel)
2965 // For small code model we assume that latest object is 16MB before end of 31
2966 // bits boundary. We may also accept pretty large negative constants knowing
2967 // that all objects are in the positive half of address space.
2968 if (M == CodeModel::Small && Offset < 16*1024*1024)
2971 // For kernel code model we know that all object resist in the negative half
2972 // of 32bits address space. We may not accept negative offsets, since they may
2973 // be just off and we may accept pretty large positive ones.
2974 if (M == CodeModel::Kernel && Offset > 0)
2980 /// isCalleePop - Determines whether the callee is required to pop its
2981 /// own arguments. Callee pop is necessary to support tail calls.
2982 bool X86::isCalleePop(CallingConv::ID CallingConv,
2983 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2987 switch (CallingConv) {
2990 case CallingConv::X86_StdCall:
2992 case CallingConv::X86_FastCall:
2994 case CallingConv::X86_ThisCall:
2996 case CallingConv::Fast:
2998 case CallingConv::GHC:
3003 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3004 /// specific condition code, returning the condition code and the LHS/RHS of the
3005 /// comparison to make.
3006 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3007 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3009 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3010 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3011 // X > -1 -> X == 0, jump !sign.
3012 RHS = DAG.getConstant(0, RHS.getValueType());
3013 return X86::COND_NS;
3014 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3015 // X < 0 -> X == 0, jump on sign.
3017 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3019 RHS = DAG.getConstant(0, RHS.getValueType());
3020 return X86::COND_LE;
3024 switch (SetCCOpcode) {
3025 default: llvm_unreachable("Invalid integer condition!");
3026 case ISD::SETEQ: return X86::COND_E;
3027 case ISD::SETGT: return X86::COND_G;
3028 case ISD::SETGE: return X86::COND_GE;
3029 case ISD::SETLT: return X86::COND_L;
3030 case ISD::SETLE: return X86::COND_LE;
3031 case ISD::SETNE: return X86::COND_NE;
3032 case ISD::SETULT: return X86::COND_B;
3033 case ISD::SETUGT: return X86::COND_A;
3034 case ISD::SETULE: return X86::COND_BE;
3035 case ISD::SETUGE: return X86::COND_AE;
3039 // First determine if it is required or is profitable to flip the operands.
3041 // If LHS is a foldable load, but RHS is not, flip the condition.
3042 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3043 !ISD::isNON_EXTLoad(RHS.getNode())) {
3044 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3045 std::swap(LHS, RHS);
3048 switch (SetCCOpcode) {
3054 std::swap(LHS, RHS);
3058 // On a floating point condition, the flags are set as follows:
3060 // 0 | 0 | 0 | X > Y
3061 // 0 | 0 | 1 | X < Y
3062 // 1 | 0 | 0 | X == Y
3063 // 1 | 1 | 1 | unordered
3064 switch (SetCCOpcode) {
3065 default: llvm_unreachable("Condcode should be pre-legalized away");
3067 case ISD::SETEQ: return X86::COND_E;
3068 case ISD::SETOLT: // flipped
3070 case ISD::SETGT: return X86::COND_A;
3071 case ISD::SETOLE: // flipped
3073 case ISD::SETGE: return X86::COND_AE;
3074 case ISD::SETUGT: // flipped
3076 case ISD::SETLT: return X86::COND_B;
3077 case ISD::SETUGE: // flipped
3079 case ISD::SETLE: return X86::COND_BE;
3081 case ISD::SETNE: return X86::COND_NE;
3082 case ISD::SETUO: return X86::COND_P;
3083 case ISD::SETO: return X86::COND_NP;
3085 case ISD::SETUNE: return X86::COND_INVALID;
3089 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3090 /// code. Current x86 isa includes the following FP cmov instructions:
3091 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3092 static bool hasFPCMov(unsigned X86CC) {
3108 /// isFPImmLegal - Returns true if the target can instruction select the
3109 /// specified FP immediate natively. If false, the legalizer will
3110 /// materialize the FP immediate as a load from a constant pool.
3111 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3112 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3113 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3119 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3120 /// the specified range (L, H].
3121 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3122 return (Val < 0) || (Val >= Low && Val < Hi);
3125 /// isUndefOrInRange - Return true if every element in Mask, begining
3126 /// from position Pos and ending in Pos+Size, falls within the specified
3127 /// range (L, L+Pos]. or is undef.
3128 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3129 int Pos, int Size, int Low, int Hi) {
3130 for (int i = Pos, e = Pos+Size; i != e; ++i)
3131 if (!isUndefOrInRange(Mask[i], Low, Hi))
3136 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3137 /// specified value.
3138 static bool isUndefOrEqual(int Val, int CmpVal) {
3139 if (Val < 0 || Val == CmpVal)
3144 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3145 /// from position Pos and ending in Pos+Size, falls within the specified
3146 /// sequential range (L, L+Pos]. or is undef.
3147 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3148 int Pos, int Size, int Low) {
3149 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3150 if (!isUndefOrEqual(Mask[i], Low))
3155 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3156 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3157 /// the second operand.
3158 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3159 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3160 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3161 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3162 return (Mask[0] < 2 && Mask[1] < 2);
3166 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3167 SmallVector<int, 8> M;
3169 return ::isPSHUFDMask(M, N->getValueType(0));
3172 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3173 /// is suitable for input to PSHUFHW.
3174 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3175 if (VT != MVT::v8i16)
3178 // Lower quadword copied in order or undef.
3179 for (int i = 0; i != 4; ++i)
3180 if (Mask[i] >= 0 && Mask[i] != i)
3183 // Upper quadword shuffled.
3184 for (int i = 4; i != 8; ++i)
3185 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3191 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3192 SmallVector<int, 8> M;
3194 return ::isPSHUFHWMask(M, N->getValueType(0));
3197 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3198 /// is suitable for input to PSHUFLW.
3199 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3200 if (VT != MVT::v8i16)
3203 // Upper quadword copied in order.
3204 for (int i = 4; i != 8; ++i)
3205 if (Mask[i] >= 0 && Mask[i] != i)
3208 // Lower quadword shuffled.
3209 for (int i = 0; i != 4; ++i)
3216 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3217 SmallVector<int, 8> M;
3219 return ::isPSHUFLWMask(M, N->getValueType(0));
3222 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3223 /// is suitable for input to PALIGNR.
3224 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3225 bool hasSSSE3OrAVX) {
3226 int i, e = VT.getVectorNumElements();
3227 if (VT.getSizeInBits() != 128)
3230 // Do not handle v2i64 / v2f64 shuffles with palignr.
3231 if (e < 4 || !hasSSSE3OrAVX)
3234 for (i = 0; i != e; ++i)
3238 // All undef, not a palignr.
3242 // Make sure we're shifting in the right direction.
3246 int s = Mask[i] - i;
3248 // Check the rest of the elements to see if they are consecutive.
3249 for (++i; i != e; ++i) {
3251 if (m >= 0 && m != s+i)
3257 /// isVSHUFPYMask - Return true if the specified VECTOR_SHUFFLE operand
3258 /// specifies a shuffle of elements that is suitable for input to 256-bit
3260 static bool isVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3261 bool HasAVX, bool Commuted = false) {
3262 int NumElems = VT.getVectorNumElements();
3264 if (!HasAVX || VT.getSizeInBits() != 256)
3267 if (NumElems != 4 && NumElems != 8)
3270 // VSHUFPSY divides the resulting vector into 4 chunks.
3271 // The sources are also splitted into 4 chunks, and each destination
3272 // chunk must come from a different source chunk.
3274 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3275 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3277 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3278 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3280 // VSHUFPDY divides the resulting vector into 4 chunks.
3281 // The sources are also splitted into 4 chunks, and each destination
3282 // chunk must come from a different source chunk.
3284 // SRC1 => X3 X2 X1 X0
3285 // SRC2 => Y3 Y2 Y1 Y0
3287 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3289 unsigned QuarterSize = NumElems/4;
3290 unsigned HalfSize = QuarterSize*2;
3291 for (unsigned l = 0; l != 2; ++l) {
3292 unsigned LaneStart = l*HalfSize;
3293 for (unsigned s = 0; s != 2; ++s) {
3294 unsigned QuarterStart = s*QuarterSize;
3295 unsigned Src = (Commuted) ? (1-s) : s;
3296 unsigned SrcStart = Src*NumElems + LaneStart;
3297 for (unsigned i = 0; i != QuarterSize; ++i) {
3298 int Idx = Mask[i+QuarterStart+LaneStart];
3299 if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize))
3301 // For VSHUFPSY, the mask of the second half must be the same as the
3302 // first but with the appropriate offsets. This works in the same way as
3303 // VPERMILPS works with masks.
3304 if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0)
3306 if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+HalfSize))
3315 /// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle
3316 /// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions.
3317 static unsigned getShuffleVSHUFPYImmediate(SDNode *N) {
3318 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3319 EVT VT = SVOp->getValueType(0);
3320 int NumElems = VT.getVectorNumElements();
3322 assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types");
3323 assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types");
3325 int HalfSize = NumElems/2;
3326 unsigned Mul = (NumElems == 8) ? 2 : 1;
3328 for (int i = 0; i != NumElems; ++i) {
3329 int Elt = SVOp->getMaskElt(i);
3334 // For VSHUFPSY, the mask of the first half must be equal to the second one.
3335 if (NumElems == 8) Shamt %= HalfSize;
3336 Mask |= Elt << (Shamt*Mul);
3342 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3343 /// the two vector operands have swapped position.
3344 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3345 unsigned NumElems) {
3346 for (unsigned i = 0; i != NumElems; ++i) {
3350 else if (idx < (int)NumElems)
3351 Mask[i] = idx + NumElems;
3353 Mask[i] = idx - NumElems;
3357 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3358 /// specifies a shuffle of elements that is suitable for input to 128-bit
3359 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3360 /// reverse of what x86 shuffles want.
3361 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT,
3362 bool Commuted = false) {
3363 unsigned NumElems = VT.getVectorNumElements();
3365 if (VT.getSizeInBits() != 128)
3368 if (NumElems != 2 && NumElems != 4)
3371 unsigned Half = NumElems / 2;
3372 unsigned SrcStart = Commuted ? NumElems : 0;
3373 for (unsigned i = 0; i != Half; ++i)
3374 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3376 SrcStart = Commuted ? 0 : NumElems;
3377 for (unsigned i = Half; i != NumElems; ++i)
3378 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3384 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3385 SmallVector<int, 8> M;
3387 return ::isSHUFPMask(M, N->getValueType(0));
3390 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3391 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3392 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3393 EVT VT = N->getValueType(0);
3394 unsigned NumElems = VT.getVectorNumElements();
3396 if (VT.getSizeInBits() != 128)
3402 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3403 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3404 isUndefOrEqual(N->getMaskElt(1), 7) &&
3405 isUndefOrEqual(N->getMaskElt(2), 2) &&
3406 isUndefOrEqual(N->getMaskElt(3), 3);
3409 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3410 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3412 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3413 EVT VT = N->getValueType(0);
3414 unsigned NumElems = VT.getVectorNumElements();
3416 if (VT.getSizeInBits() != 128)
3422 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3423 isUndefOrEqual(N->getMaskElt(1), 3) &&
3424 isUndefOrEqual(N->getMaskElt(2), 2) &&
3425 isUndefOrEqual(N->getMaskElt(3), 3);
3428 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3429 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3430 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3431 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3433 if (NumElems != 2 && NumElems != 4)
3436 for (unsigned i = 0; i < NumElems/2; ++i)
3437 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3440 for (unsigned i = NumElems/2; i < NumElems; ++i)
3441 if (!isUndefOrEqual(N->getMaskElt(i), i))
3447 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3448 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3449 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3450 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3452 if ((NumElems != 2 && NumElems != 4)
3453 || N->getValueType(0).getSizeInBits() > 128)
3456 for (unsigned i = 0; i < NumElems/2; ++i)
3457 if (!isUndefOrEqual(N->getMaskElt(i), i))
3460 for (unsigned i = 0; i < NumElems/2; ++i)
3461 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3467 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3468 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3469 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3470 bool HasAVX2, bool V2IsSplat = false) {
3471 unsigned NumElts = VT.getVectorNumElements();
3473 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3474 "Unsupported vector type for unpckh");
3476 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3477 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3480 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3481 // independently on 128-bit lanes.
3482 unsigned NumLanes = VT.getSizeInBits()/128;
3483 unsigned NumLaneElts = NumElts/NumLanes;
3485 for (unsigned l = 0; l != NumLanes; ++l) {
3486 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3487 i != (l+1)*NumLaneElts;
3490 int BitI1 = Mask[i+1];
3491 if (!isUndefOrEqual(BitI, j))
3494 if (!isUndefOrEqual(BitI1, NumElts))
3497 if (!isUndefOrEqual(BitI1, j + NumElts))
3506 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3507 SmallVector<int, 8> M;
3509 return ::isUNPCKLMask(M, N->getValueType(0), HasAVX2, V2IsSplat);
3512 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3513 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3514 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3515 bool HasAVX2, bool V2IsSplat = false) {
3516 unsigned NumElts = VT.getVectorNumElements();
3518 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3519 "Unsupported vector type for unpckh");
3521 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3522 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3525 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3526 // independently on 128-bit lanes.
3527 unsigned NumLanes = VT.getSizeInBits()/128;
3528 unsigned NumLaneElts = NumElts/NumLanes;
3530 for (unsigned l = 0; l != NumLanes; ++l) {
3531 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3532 i != (l+1)*NumLaneElts; i += 2, ++j) {
3534 int BitI1 = Mask[i+1];
3535 if (!isUndefOrEqual(BitI, j))
3538 if (isUndefOrEqual(BitI1, NumElts))
3541 if (!isUndefOrEqual(BitI1, j+NumElts))
3549 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3550 SmallVector<int, 8> M;
3552 return ::isUNPCKHMask(M, N->getValueType(0), HasAVX2, V2IsSplat);
3555 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3556 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3558 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3560 unsigned NumElts = VT.getVectorNumElements();
3562 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3563 "Unsupported vector type for unpckh");
3565 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3566 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3569 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3570 // FIXME: Need a better way to get rid of this, there's no latency difference
3571 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3572 // the former later. We should also remove the "_undef" special mask.
3573 if (NumElts == 4 && VT.getSizeInBits() == 256)
3576 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3577 // independently on 128-bit lanes.
3578 unsigned NumLanes = VT.getSizeInBits()/128;
3579 unsigned NumLaneElts = NumElts/NumLanes;
3581 for (unsigned l = 0; l != NumLanes; ++l) {
3582 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3583 i != (l+1)*NumLaneElts;
3586 int BitI1 = Mask[i+1];
3588 if (!isUndefOrEqual(BitI, j))
3590 if (!isUndefOrEqual(BitI1, j))
3598 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3599 SmallVector<int, 8> M;
3601 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0), HasAVX2);
3604 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3605 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3607 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3609 unsigned NumElts = VT.getVectorNumElements();
3611 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3612 "Unsupported vector type for unpckh");
3614 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3615 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3618 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3619 // independently on 128-bit lanes.
3620 unsigned NumLanes = VT.getSizeInBits()/128;
3621 unsigned NumLaneElts = NumElts/NumLanes;
3623 for (unsigned l = 0; l != NumLanes; ++l) {
3624 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3625 i != (l+1)*NumLaneElts; i += 2, ++j) {
3627 int BitI1 = Mask[i+1];
3628 if (!isUndefOrEqual(BitI, j))
3630 if (!isUndefOrEqual(BitI1, j))
3637 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3638 SmallVector<int, 8> M;
3640 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0), HasAVX2);
3643 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3644 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3645 /// MOVSD, and MOVD, i.e. setting the lowest element.
3646 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3647 if (VT.getVectorElementType().getSizeInBits() < 32)
3650 int NumElts = VT.getVectorNumElements();
3652 if (!isUndefOrEqual(Mask[0], NumElts))
3655 for (int i = 1; i < NumElts; ++i)
3656 if (!isUndefOrEqual(Mask[i], i))
3662 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3663 SmallVector<int, 8> M;
3665 return ::isMOVLMask(M, N->getValueType(0));
3668 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3669 /// as permutations between 128-bit chunks or halves. As an example: this
3671 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3672 /// The first half comes from the second half of V1 and the second half from the
3673 /// the second half of V2.
3674 static bool isVPERM2X128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3676 if (!HasAVX || VT.getSizeInBits() != 256)
3679 // The shuffle result is divided into half A and half B. In total the two
3680 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3681 // B must come from C, D, E or F.
3682 int HalfSize = VT.getVectorNumElements()/2;
3683 bool MatchA = false, MatchB = false;
3685 // Check if A comes from one of C, D, E, F.
3686 for (int Half = 0; Half < 4; ++Half) {
3687 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3693 // Check if B comes from one of C, D, E, F.
3694 for (int Half = 0; Half < 4; ++Half) {
3695 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3701 return MatchA && MatchB;
3704 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3705 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3706 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3707 EVT VT = SVOp->getValueType(0);
3709 int HalfSize = VT.getVectorNumElements()/2;
3711 int FstHalf = 0, SndHalf = 0;
3712 for (int i = 0; i < HalfSize; ++i) {
3713 if (SVOp->getMaskElt(i) > 0) {
3714 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3718 for (int i = HalfSize; i < HalfSize*2; ++i) {
3719 if (SVOp->getMaskElt(i) > 0) {
3720 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3725 return (FstHalf | (SndHalf << 4));
3728 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3729 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3730 /// Note that VPERMIL mask matching is different depending whether theunderlying
3731 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3732 /// to the same elements of the low, but to the higher half of the source.
3733 /// In VPERMILPD the two lanes could be shuffled independently of each other
3734 /// with the same restriction that lanes can't be crossed.
3735 static bool isVPERMILPMask(const SmallVectorImpl<int> &Mask, EVT VT,
3737 int NumElts = VT.getVectorNumElements();
3738 int NumLanes = VT.getSizeInBits()/128;
3743 // Only match 256-bit with 32/64-bit types
3744 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3747 int LaneSize = NumElts/NumLanes;
3748 for (int l = 0; l != NumLanes; ++l) {
3749 int LaneStart = l*LaneSize;
3750 for (int i = 0; i != LaneSize; ++i) {
3751 if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize))
3753 if (NumElts == 4 || l == 0)
3755 // VPERMILPS handling
3758 if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneSize))
3766 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3767 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3768 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3769 EVT VT = SVOp->getValueType(0);
3771 int NumElts = VT.getVectorNumElements();
3772 int NumLanes = VT.getSizeInBits()/128;
3773 int LaneSize = NumElts/NumLanes;
3775 // Although the mask is equal for both lanes do it twice to get the cases
3776 // where a mask will match because the same mask element is undef on the
3777 // first half but valid on the second. This would get pathological cases
3778 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3779 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3781 for (int i = 0; i != NumElts; ++i) {
3782 int MaskElt = SVOp->getMaskElt(i);
3785 MaskElt %= LaneSize;
3787 // VPERMILPSY, the mask of the first half must be equal to the second one
3788 if (NumElts == 8) Shamt %= LaneSize;
3789 Mask |= MaskElt << (Shamt*Shift);
3795 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3796 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3797 /// element of vector 2 and the other elements to come from vector 1 in order.
3798 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3799 bool V2IsSplat = false, bool V2IsUndef = false) {
3800 int NumOps = VT.getVectorNumElements();
3801 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3804 if (!isUndefOrEqual(Mask[0], 0))
3807 for (int i = 1; i < NumOps; ++i)
3808 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3809 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3810 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3816 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3817 bool V2IsUndef = false) {
3818 SmallVector<int, 8> M;
3820 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3823 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3824 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3825 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3826 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3827 const X86Subtarget *Subtarget) {
3828 if (!Subtarget->hasSSE3orAVX())
3831 // The second vector must be undef
3832 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3835 EVT VT = N->getValueType(0);
3836 unsigned NumElems = VT.getVectorNumElements();
3838 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3839 (VT.getSizeInBits() == 256 && NumElems != 8))
3842 // "i+1" is the value the indexed mask element must have
3843 for (unsigned i = 0; i < NumElems; i += 2)
3844 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3845 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3851 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3852 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3853 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3854 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3855 const X86Subtarget *Subtarget) {
3856 if (!Subtarget->hasSSE3orAVX())
3859 // The second vector must be undef
3860 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3863 EVT VT = N->getValueType(0);
3864 unsigned NumElems = VT.getVectorNumElements();
3866 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3867 (VT.getSizeInBits() == 256 && NumElems != 8))
3870 // "i" is the value the indexed mask element must have
3871 for (unsigned i = 0; i < NumElems; i += 2)
3872 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3873 !isUndefOrEqual(N->getMaskElt(i+1), i))
3879 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3880 /// specifies a shuffle of elements that is suitable for input to 256-bit
3881 /// version of MOVDDUP.
3882 static bool isMOVDDUPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3884 int NumElts = VT.getVectorNumElements();
3886 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3889 for (int i = 0; i != NumElts/2; ++i)
3890 if (!isUndefOrEqual(Mask[i], 0))
3892 for (int i = NumElts/2; i != NumElts; ++i)
3893 if (!isUndefOrEqual(Mask[i], NumElts/2))
3898 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3899 /// specifies a shuffle of elements that is suitable for input to 128-bit
3900 /// version of MOVDDUP.
3901 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3902 EVT VT = N->getValueType(0);
3904 if (VT.getSizeInBits() != 128)
3907 int e = VT.getVectorNumElements() / 2;
3908 for (int i = 0; i < e; ++i)
3909 if (!isUndefOrEqual(N->getMaskElt(i), i))
3911 for (int i = 0; i < e; ++i)
3912 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3917 /// isVEXTRACTF128Index - Return true if the specified
3918 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3919 /// suitable for input to VEXTRACTF128.
3920 bool X86::isVEXTRACTF128Index(SDNode *N) {
3921 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3924 // The index should be aligned on a 128-bit boundary.
3926 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3928 unsigned VL = N->getValueType(0).getVectorNumElements();
3929 unsigned VBits = N->getValueType(0).getSizeInBits();
3930 unsigned ElSize = VBits / VL;
3931 bool Result = (Index * ElSize) % 128 == 0;
3936 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3937 /// operand specifies a subvector insert that is suitable for input to
3939 bool X86::isVINSERTF128Index(SDNode *N) {
3940 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3943 // The index should be aligned on a 128-bit boundary.
3945 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3947 unsigned VL = N->getValueType(0).getVectorNumElements();
3948 unsigned VBits = N->getValueType(0).getSizeInBits();
3949 unsigned ElSize = VBits / VL;
3950 bool Result = (Index * ElSize) % 128 == 0;
3955 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3956 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3957 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3958 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3959 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3961 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3963 for (int i = 0; i < NumOperands; ++i) {
3964 int Val = SVOp->getMaskElt(NumOperands-i-1);
3965 if (Val < 0) Val = 0;
3966 if (Val >= NumOperands) Val -= NumOperands;
3968 if (i != NumOperands - 1)
3974 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3975 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3976 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3977 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3979 // 8 nodes, but we only care about the last 4.
3980 for (unsigned i = 7; i >= 4; --i) {
3981 int Val = SVOp->getMaskElt(i);
3990 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3991 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3992 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3993 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3995 // 8 nodes, but we only care about the first 4.
3996 for (int i = 3; i >= 0; --i) {
3997 int Val = SVOp->getMaskElt(i);
4006 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4007 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4008 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4009 EVT VT = SVOp->getValueType(0);
4010 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4014 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4015 Val = SVOp->getMaskElt(i);
4019 assert(Val - i > 0 && "PALIGNR imm should be positive");
4020 return (Val - i) * EltSize;
4023 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4024 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4026 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4027 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4028 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4031 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4033 EVT VecVT = N->getOperand(0).getValueType();
4034 EVT ElVT = VecVT.getVectorElementType();
4036 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4037 return Index / NumElemsPerChunk;
4040 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4041 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4043 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4044 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4045 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4048 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4050 EVT VecVT = N->getValueType(0);
4051 EVT ElVT = VecVT.getVectorElementType();
4053 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4054 return Index / NumElemsPerChunk;
4057 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4059 bool X86::isZeroNode(SDValue Elt) {
4060 return ((isa<ConstantSDNode>(Elt) &&
4061 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4062 (isa<ConstantFPSDNode>(Elt) &&
4063 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4066 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4067 /// their permute mask.
4068 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4069 SelectionDAG &DAG) {
4070 EVT VT = SVOp->getValueType(0);
4071 unsigned NumElems = VT.getVectorNumElements();
4072 SmallVector<int, 8> MaskVec;
4074 for (unsigned i = 0; i != NumElems; ++i) {
4075 int idx = SVOp->getMaskElt(i);
4077 MaskVec.push_back(idx);
4078 else if (idx < (int)NumElems)
4079 MaskVec.push_back(idx + NumElems);
4081 MaskVec.push_back(idx - NumElems);
4083 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4084 SVOp->getOperand(0), &MaskVec[0]);
4087 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4088 /// match movhlps. The lower half elements should come from upper half of
4089 /// V1 (and in order), and the upper half elements should come from the upper
4090 /// half of V2 (and in order).
4091 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4092 EVT VT = Op->getValueType(0);
4093 if (VT.getSizeInBits() != 128)
4095 if (VT.getVectorNumElements() != 4)
4097 for (unsigned i = 0, e = 2; i != e; ++i)
4098 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4100 for (unsigned i = 2; i != 4; ++i)
4101 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4106 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4107 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4109 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4110 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4112 N = N->getOperand(0).getNode();
4113 if (!ISD::isNON_EXTLoad(N))
4116 *LD = cast<LoadSDNode>(N);
4120 // Test whether the given value is a vector value which will be legalized
4122 static bool WillBeConstantPoolLoad(SDNode *N) {
4123 if (N->getOpcode() != ISD::BUILD_VECTOR)
4126 // Check for any non-constant elements.
4127 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4128 switch (N->getOperand(i).getNode()->getOpcode()) {
4130 case ISD::ConstantFP:
4137 // Vectors of all-zeros and all-ones are materialized with special
4138 // instructions rather than being loaded.
4139 return !ISD::isBuildVectorAllZeros(N) &&
4140 !ISD::isBuildVectorAllOnes(N);
4143 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4144 /// match movlp{s|d}. The lower half elements should come from lower half of
4145 /// V1 (and in order), and the upper half elements should come from the upper
4146 /// half of V2 (and in order). And since V1 will become the source of the
4147 /// MOVLP, it must be either a vector load or a scalar load to vector.
4148 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4149 ShuffleVectorSDNode *Op) {
4150 EVT VT = Op->getValueType(0);
4151 if (VT.getSizeInBits() != 128)
4154 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4156 // Is V2 is a vector load, don't do this transformation. We will try to use
4157 // load folding shufps op.
4158 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4161 unsigned NumElems = VT.getVectorNumElements();
4163 if (NumElems != 2 && NumElems != 4)
4165 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4166 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4168 for (unsigned i = NumElems/2; i != NumElems; ++i)
4169 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4174 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4176 static bool isSplatVector(SDNode *N) {
4177 if (N->getOpcode() != ISD::BUILD_VECTOR)
4180 SDValue SplatValue = N->getOperand(0);
4181 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4182 if (N->getOperand(i) != SplatValue)
4187 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4188 /// to an zero vector.
4189 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4190 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4191 SDValue V1 = N->getOperand(0);
4192 SDValue V2 = N->getOperand(1);
4193 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4194 for (unsigned i = 0; i != NumElems; ++i) {
4195 int Idx = N->getMaskElt(i);
4196 if (Idx >= (int)NumElems) {
4197 unsigned Opc = V2.getOpcode();
4198 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4200 if (Opc != ISD::BUILD_VECTOR ||
4201 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4203 } else if (Idx >= 0) {
4204 unsigned Opc = V1.getOpcode();
4205 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4207 if (Opc != ISD::BUILD_VECTOR ||
4208 !X86::isZeroNode(V1.getOperand(Idx)))
4215 /// getZeroVector - Returns a vector of specified type with all zero elements.
4217 static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG,
4219 assert(VT.isVector() && "Expected a vector type");
4221 // Always build SSE zero vectors as <4 x i32> bitcasted
4222 // to their dest type. This ensures they get CSE'd.
4224 if (VT.getSizeInBits() == 128) { // SSE
4225 if (HasXMMInt) { // SSE2
4226 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4227 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4229 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4230 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4232 } else if (VT.getSizeInBits() == 256) { // AVX
4233 // 256-bit logic and arithmetic instructions in AVX are
4234 // all floating-point, no support for integer ops. Default
4235 // to emitting fp zeroed vectors then.
4236 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4237 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4238 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4240 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4243 /// getOnesVector - Returns a vector of specified type with all bits set.
4244 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4245 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4246 /// Then bitcast to their original type, ensuring they get CSE'd.
4247 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4249 assert(VT.isVector() && "Expected a vector type");
4250 assert((VT.is128BitVector() || VT.is256BitVector())
4251 && "Expected a 128-bit or 256-bit vector type");
4253 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4255 if (VT.getSizeInBits() == 256) {
4256 if (HasAVX2) { // AVX2
4257 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4260 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4261 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4262 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4263 Vec = Insert128BitVector(InsV, Vec,
4264 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4267 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4270 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4273 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4274 /// that point to V2 points to its first element.
4275 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4276 EVT VT = SVOp->getValueType(0);
4277 unsigned NumElems = VT.getVectorNumElements();
4279 bool Changed = false;
4280 SmallVector<int, 8> MaskVec;
4281 SVOp->getMask(MaskVec);
4283 for (unsigned i = 0; i != NumElems; ++i) {
4284 if (MaskVec[i] > (int)NumElems) {
4285 MaskVec[i] = NumElems;
4290 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4291 SVOp->getOperand(1), &MaskVec[0]);
4292 return SDValue(SVOp, 0);
4295 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4296 /// operation of specified width.
4297 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4299 unsigned NumElems = VT.getVectorNumElements();
4300 SmallVector<int, 8> Mask;
4301 Mask.push_back(NumElems);
4302 for (unsigned i = 1; i != NumElems; ++i)
4304 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4307 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4308 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4310 unsigned NumElems = VT.getVectorNumElements();
4311 SmallVector<int, 8> Mask;
4312 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4314 Mask.push_back(i + NumElems);
4316 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4319 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4320 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4322 unsigned NumElems = VT.getVectorNumElements();
4323 unsigned Half = NumElems/2;
4324 SmallVector<int, 8> Mask;
4325 for (unsigned i = 0; i != Half; ++i) {
4326 Mask.push_back(i + Half);
4327 Mask.push_back(i + NumElems + Half);
4329 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4332 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4333 // a generic shuffle instruction because the target has no such instructions.
4334 // Generate shuffles which repeat i16 and i8 several times until they can be
4335 // represented by v4f32 and then be manipulated by target suported shuffles.
4336 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4337 EVT VT = V.getValueType();
4338 int NumElems = VT.getVectorNumElements();
4339 DebugLoc dl = V.getDebugLoc();
4341 while (NumElems > 4) {
4342 if (EltNo < NumElems/2) {
4343 V = getUnpackl(DAG, dl, VT, V, V);
4345 V = getUnpackh(DAG, dl, VT, V, V);
4346 EltNo -= NumElems/2;
4353 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4354 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4355 EVT VT = V.getValueType();
4356 DebugLoc dl = V.getDebugLoc();
4357 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4358 && "Vector size not supported");
4360 if (VT.getSizeInBits() == 128) {
4361 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4362 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4363 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4366 // To use VPERMILPS to splat scalars, the second half of indicies must
4367 // refer to the higher part, which is a duplication of the lower one,
4368 // because VPERMILPS can only handle in-lane permutations.
4369 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4370 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4372 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4373 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4377 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4380 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4381 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4382 EVT SrcVT = SV->getValueType(0);
4383 SDValue V1 = SV->getOperand(0);
4384 DebugLoc dl = SV->getDebugLoc();
4386 int EltNo = SV->getSplatIndex();
4387 int NumElems = SrcVT.getVectorNumElements();
4388 unsigned Size = SrcVT.getSizeInBits();
4390 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4391 "Unknown how to promote splat for type");
4393 // Extract the 128-bit part containing the splat element and update
4394 // the splat element index when it refers to the higher register.
4396 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4397 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4399 EltNo -= NumElems/2;
4402 // All i16 and i8 vector types can't be used directly by a generic shuffle
4403 // instruction because the target has no such instruction. Generate shuffles
4404 // which repeat i16 and i8 several times until they fit in i32, and then can
4405 // be manipulated by target suported shuffles.
4406 EVT EltVT = SrcVT.getVectorElementType();
4407 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4408 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4410 // Recreate the 256-bit vector and place the same 128-bit vector
4411 // into the low and high part. This is necessary because we want
4412 // to use VPERM* to shuffle the vectors
4414 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4415 DAG.getConstant(0, MVT::i32), DAG, dl);
4416 V1 = Insert128BitVector(InsV, V1,
4417 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4420 return getLegalSplat(DAG, V1, EltNo);
4423 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4424 /// vector of zero or undef vector. This produces a shuffle where the low
4425 /// element of V2 is swizzled into the zero/undef vector, landing at element
4426 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4427 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4428 bool isZero, bool HasXMMInt,
4429 SelectionDAG &DAG) {
4430 EVT VT = V2.getValueType();
4432 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4433 unsigned NumElems = VT.getVectorNumElements();
4434 SmallVector<int, 16> MaskVec;
4435 for (unsigned i = 0; i != NumElems; ++i)
4436 // If this is the insertion idx, put the low elt of V2 here.
4437 MaskVec.push_back(i == Idx ? NumElems : i);
4438 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4441 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4442 /// element of the result of the vector shuffle.
4443 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4446 return SDValue(); // Limit search depth.
4448 SDValue V = SDValue(N, 0);
4449 EVT VT = V.getValueType();
4450 unsigned Opcode = V.getOpcode();
4452 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4453 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4454 Index = SV->getMaskElt(Index);
4457 return DAG.getUNDEF(VT.getVectorElementType());
4459 int NumElems = VT.getVectorNumElements();
4460 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4461 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4464 // Recurse into target specific vector shuffles to find scalars.
4465 if (isTargetShuffle(Opcode)) {
4466 int NumElems = VT.getVectorNumElements();
4467 SmallVector<unsigned, 16> ShuffleMask;
4471 case X86ISD::SHUFPS:
4472 case X86ISD::SHUFPD:
4473 ImmN = N->getOperand(N->getNumOperands()-1);
4474 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4477 case X86ISD::UNPCKH:
4478 DecodeUNPCKHMask(VT, ShuffleMask);
4480 case X86ISD::UNPCKL:
4481 DecodeUNPCKLMask(VT, ShuffleMask);
4483 case X86ISD::MOVHLPS:
4484 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4486 case X86ISD::MOVLHPS:
4487 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4489 case X86ISD::PSHUFD:
4490 ImmN = N->getOperand(N->getNumOperands()-1);
4491 DecodePSHUFMask(NumElems,
4492 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4495 case X86ISD::PSHUFHW:
4496 ImmN = N->getOperand(N->getNumOperands()-1);
4497 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4500 case X86ISD::PSHUFLW:
4501 ImmN = N->getOperand(N->getNumOperands()-1);
4502 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4506 case X86ISD::MOVSD: {
4507 // The index 0 always comes from the first element of the second source,
4508 // this is why MOVSS and MOVSD are used in the first place. The other
4509 // elements come from the other positions of the first source vector.
4510 unsigned OpNum = (Index == 0) ? 1 : 0;
4511 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4514 case X86ISD::VPERMILP:
4515 ImmN = N->getOperand(N->getNumOperands()-1);
4516 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4519 case X86ISD::VPERM2X128:
4520 ImmN = N->getOperand(N->getNumOperands()-1);
4521 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4524 case X86ISD::MOVDDUP:
4525 case X86ISD::MOVLHPD:
4526 case X86ISD::MOVLPD:
4527 case X86ISD::MOVLPS:
4528 case X86ISD::MOVSHDUP:
4529 case X86ISD::MOVSLDUP:
4530 case X86ISD::PALIGN:
4531 return SDValue(); // Not yet implemented.
4533 assert(0 && "unknown target shuffle node");
4537 Index = ShuffleMask[Index];
4539 return DAG.getUNDEF(VT.getVectorElementType());
4541 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4542 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4546 // Actual nodes that may contain scalar elements
4547 if (Opcode == ISD::BITCAST) {
4548 V = V.getOperand(0);
4549 EVT SrcVT = V.getValueType();
4550 unsigned NumElems = VT.getVectorNumElements();
4552 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4556 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4557 return (Index == 0) ? V.getOperand(0)
4558 : DAG.getUNDEF(VT.getVectorElementType());
4560 if (V.getOpcode() == ISD::BUILD_VECTOR)
4561 return V.getOperand(Index);
4566 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4567 /// shuffle operation which come from a consecutively from a zero. The
4568 /// search can start in two different directions, from left or right.
4570 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4571 bool ZerosFromLeft, SelectionDAG &DAG) {
4574 while (i < NumElems) {
4575 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4576 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4577 if (!(Elt.getNode() &&
4578 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4586 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4587 /// MaskE correspond consecutively to elements from one of the vector operands,
4588 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4590 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4591 int OpIdx, int NumElems, unsigned &OpNum) {
4592 bool SeenV1 = false;
4593 bool SeenV2 = false;
4595 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4596 int Idx = SVOp->getMaskElt(i);
4597 // Ignore undef indicies
4606 // Only accept consecutive elements from the same vector
4607 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4611 OpNum = SeenV1 ? 0 : 1;
4615 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4616 /// logical left shift of a vector.
4617 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4618 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4619 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4620 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4621 false /* check zeros from right */, DAG);
4627 // Considering the elements in the mask that are not consecutive zeros,
4628 // check if they consecutively come from only one of the source vectors.
4630 // V1 = {X, A, B, C} 0
4632 // vector_shuffle V1, V2 <1, 2, 3, X>
4634 if (!isShuffleMaskConsecutive(SVOp,
4635 0, // Mask Start Index
4636 NumElems-NumZeros-1, // Mask End Index
4637 NumZeros, // Where to start looking in the src vector
4638 NumElems, // Number of elements in vector
4639 OpSrc)) // Which source operand ?
4644 ShVal = SVOp->getOperand(OpSrc);
4648 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4649 /// logical left shift of a vector.
4650 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4651 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4652 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4653 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4654 true /* check zeros from left */, DAG);
4660 // Considering the elements in the mask that are not consecutive zeros,
4661 // check if they consecutively come from only one of the source vectors.
4663 // 0 { A, B, X, X } = V2
4665 // vector_shuffle V1, V2 <X, X, 4, 5>
4667 if (!isShuffleMaskConsecutive(SVOp,
4668 NumZeros, // Mask Start Index
4669 NumElems-1, // Mask End Index
4670 0, // Where to start looking in the src vector
4671 NumElems, // Number of elements in vector
4672 OpSrc)) // Which source operand ?
4677 ShVal = SVOp->getOperand(OpSrc);
4681 /// isVectorShift - Returns true if the shuffle can be implemented as a
4682 /// logical left or right shift of a vector.
4683 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4684 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4685 // Although the logic below support any bitwidth size, there are no
4686 // shift instructions which handle more than 128-bit vectors.
4687 if (SVOp->getValueType(0).getSizeInBits() > 128)
4690 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4691 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4697 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4699 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4700 unsigned NumNonZero, unsigned NumZero,
4702 const TargetLowering &TLI) {
4706 DebugLoc dl = Op.getDebugLoc();
4709 for (unsigned i = 0; i < 16; ++i) {
4710 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4711 if (ThisIsNonZero && First) {
4713 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4715 V = DAG.getUNDEF(MVT::v8i16);
4720 SDValue ThisElt(0, 0), LastElt(0, 0);
4721 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4722 if (LastIsNonZero) {
4723 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4724 MVT::i16, Op.getOperand(i-1));
4726 if (ThisIsNonZero) {
4727 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4728 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4729 ThisElt, DAG.getConstant(8, MVT::i8));
4731 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4735 if (ThisElt.getNode())
4736 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4737 DAG.getIntPtrConstant(i/2));
4741 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4744 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4746 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4747 unsigned NumNonZero, unsigned NumZero,
4749 const TargetLowering &TLI) {
4753 DebugLoc dl = Op.getDebugLoc();
4756 for (unsigned i = 0; i < 8; ++i) {
4757 bool isNonZero = (NonZeros & (1 << i)) != 0;
4761 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4763 V = DAG.getUNDEF(MVT::v8i16);
4766 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4767 MVT::v8i16, V, Op.getOperand(i),
4768 DAG.getIntPtrConstant(i));
4775 /// getVShift - Return a vector logical shift node.
4777 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4778 unsigned NumBits, SelectionDAG &DAG,
4779 const TargetLowering &TLI, DebugLoc dl) {
4780 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4781 EVT ShVT = MVT::v2i64;
4782 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4783 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4784 return DAG.getNode(ISD::BITCAST, dl, VT,
4785 DAG.getNode(Opc, dl, ShVT, SrcOp,
4786 DAG.getConstant(NumBits,
4787 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4791 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4792 SelectionDAG &DAG) const {
4794 // Check if the scalar load can be widened into a vector load. And if
4795 // the address is "base + cst" see if the cst can be "absorbed" into
4796 // the shuffle mask.
4797 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4798 SDValue Ptr = LD->getBasePtr();
4799 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4801 EVT PVT = LD->getValueType(0);
4802 if (PVT != MVT::i32 && PVT != MVT::f32)
4807 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4808 FI = FINode->getIndex();
4810 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4811 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4812 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4813 Offset = Ptr.getConstantOperandVal(1);
4814 Ptr = Ptr.getOperand(0);
4819 // FIXME: 256-bit vector instructions don't require a strict alignment,
4820 // improve this code to support it better.
4821 unsigned RequiredAlign = VT.getSizeInBits()/8;
4822 SDValue Chain = LD->getChain();
4823 // Make sure the stack object alignment is at least 16 or 32.
4824 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4825 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4826 if (MFI->isFixedObjectIndex(FI)) {
4827 // Can't change the alignment. FIXME: It's possible to compute
4828 // the exact stack offset and reference FI + adjust offset instead.
4829 // If someone *really* cares about this. That's the way to implement it.
4832 MFI->setObjectAlignment(FI, RequiredAlign);
4836 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4837 // Ptr + (Offset & ~15).
4840 if ((Offset % RequiredAlign) & 3)
4842 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4844 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4845 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4847 int EltNo = (Offset - StartOffset) >> 2;
4848 int NumElems = VT.getVectorNumElements();
4850 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4851 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4852 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4853 LD->getPointerInfo().getWithOffset(StartOffset),
4854 false, false, false, 0);
4856 // Canonicalize it to a v4i32 or v8i32 shuffle.
4857 SmallVector<int, 8> Mask;
4858 for (int i = 0; i < NumElems; ++i)
4859 Mask.push_back(EltNo);
4861 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4862 return DAG.getNode(ISD::BITCAST, dl, NVT,
4863 DAG.getVectorShuffle(CanonVT, dl, V1,
4864 DAG.getUNDEF(CanonVT),&Mask[0]));
4870 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4871 /// vector of type 'VT', see if the elements can be replaced by a single large
4872 /// load which has the same value as a build_vector whose operands are 'elts'.
4874 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4876 /// FIXME: we'd also like to handle the case where the last elements are zero
4877 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4878 /// There's even a handy isZeroNode for that purpose.
4879 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4880 DebugLoc &DL, SelectionDAG &DAG) {
4881 EVT EltVT = VT.getVectorElementType();
4882 unsigned NumElems = Elts.size();
4884 LoadSDNode *LDBase = NULL;
4885 unsigned LastLoadedElt = -1U;
4887 // For each element in the initializer, see if we've found a load or an undef.
4888 // If we don't find an initial load element, or later load elements are
4889 // non-consecutive, bail out.
4890 for (unsigned i = 0; i < NumElems; ++i) {
4891 SDValue Elt = Elts[i];
4893 if (!Elt.getNode() ||
4894 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4897 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4899 LDBase = cast<LoadSDNode>(Elt.getNode());
4903 if (Elt.getOpcode() == ISD::UNDEF)
4906 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4907 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4912 // If we have found an entire vector of loads and undefs, then return a large
4913 // load of the entire vector width starting at the base pointer. If we found
4914 // consecutive loads for the low half, generate a vzext_load node.
4915 if (LastLoadedElt == NumElems - 1) {
4916 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4917 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4918 LDBase->getPointerInfo(),
4919 LDBase->isVolatile(), LDBase->isNonTemporal(),
4920 LDBase->isInvariant(), 0);
4921 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4922 LDBase->getPointerInfo(),
4923 LDBase->isVolatile(), LDBase->isNonTemporal(),
4924 LDBase->isInvariant(), LDBase->getAlignment());
4925 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4926 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4927 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4928 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4930 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4931 LDBase->getPointerInfo(),
4932 LDBase->getAlignment(),
4933 false/*isVolatile*/, true/*ReadMem*/,
4935 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4940 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4941 /// a vbroadcast node. We support two patterns:
4942 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4943 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4945 /// The scalar load node is returned when a pattern is found,
4946 /// or SDValue() otherwise.
4947 static SDValue isVectorBroadcast(SDValue &Op, bool hasAVX2) {
4948 EVT VT = Op.getValueType();
4951 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4952 V = V.getOperand(0);
4954 //A suspected load to be broadcasted.
4957 switch (V.getOpcode()) {
4959 // Unknown pattern found.
4962 case ISD::BUILD_VECTOR: {
4963 // The BUILD_VECTOR node must be a splat.
4964 if (!isSplatVector(V.getNode()))
4967 Ld = V.getOperand(0);
4969 // The suspected load node has several users. Make sure that all
4970 // of its users are from the BUILD_VECTOR node.
4971 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4976 case ISD::VECTOR_SHUFFLE: {
4977 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4979 // Shuffles must have a splat mask where the first element is
4981 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4984 SDValue Sc = Op.getOperand(0);
4985 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4988 Ld = Sc.getOperand(0);
4990 // The scalar_to_vector node and the suspected
4991 // load node must have exactly one user.
4992 if (!Sc.hasOneUse() || !Ld.hasOneUse())
4998 // The scalar source must be a normal load.
4999 if (!ISD::isNormalLoad(Ld.getNode()))
5002 bool Is256 = VT.getSizeInBits() == 256;
5003 bool Is128 = VT.getSizeInBits() == 128;
5004 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5007 // VBroadcast to YMM
5008 if (Is256 && (ScalarSize == 8 || ScalarSize == 16 ||
5009 ScalarSize == 32 || ScalarSize == 64 ))
5012 // VBroadcast to XMM
5013 if (Is128 && (ScalarSize == 8 || ScalarSize == 32 ||
5014 ScalarSize == 16 || ScalarSize == 64 ))
5018 // VBroadcast to YMM
5019 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5022 // VBroadcast to XMM
5023 if (Is128 && (ScalarSize == 32))
5027 // Unsupported broadcast.
5032 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5033 DebugLoc dl = Op.getDebugLoc();
5035 EVT VT = Op.getValueType();
5036 EVT ExtVT = VT.getVectorElementType();
5037 unsigned NumElems = Op.getNumOperands();
5039 // Vectors containing all zeros can be matched by pxor and xorps later
5040 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5041 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5042 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5043 if (Op.getValueType() == MVT::v4i32 ||
5044 Op.getValueType() == MVT::v8i32)
5047 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl);
5050 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5051 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5052 // vpcmpeqd on 256-bit vectors.
5053 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5054 if (Op.getValueType() == MVT::v4i32 ||
5055 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
5058 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl);
5061 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
5062 if (Subtarget->hasAVX() && LD.getNode())
5063 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5065 unsigned EVTBits = ExtVT.getSizeInBits();
5067 unsigned NumZero = 0;
5068 unsigned NumNonZero = 0;
5069 unsigned NonZeros = 0;
5070 bool IsAllConstants = true;
5071 SmallSet<SDValue, 8> Values;
5072 for (unsigned i = 0; i < NumElems; ++i) {
5073 SDValue Elt = Op.getOperand(i);
5074 if (Elt.getOpcode() == ISD::UNDEF)
5077 if (Elt.getOpcode() != ISD::Constant &&
5078 Elt.getOpcode() != ISD::ConstantFP)
5079 IsAllConstants = false;
5080 if (X86::isZeroNode(Elt))
5083 NonZeros |= (1 << i);
5088 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5089 if (NumNonZero == 0)
5090 return DAG.getUNDEF(VT);
5092 // Special case for single non-zero, non-undef, element.
5093 if (NumNonZero == 1) {
5094 unsigned Idx = CountTrailingZeros_32(NonZeros);
5095 SDValue Item = Op.getOperand(Idx);
5097 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5098 // the value are obviously zero, truncate the value to i32 and do the
5099 // insertion that way. Only do this if the value is non-constant or if the
5100 // value is a constant being inserted into element 0. It is cheaper to do
5101 // a constant pool load than it is to do a movd + shuffle.
5102 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5103 (!IsAllConstants || Idx == 0)) {
5104 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5106 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5107 EVT VecVT = MVT::v4i32;
5108 unsigned VecElts = 4;
5110 // Truncate the value (which may itself be a constant) to i32, and
5111 // convert it to a vector with movd (S2V+shuffle to zero extend).
5112 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5113 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5114 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5115 Subtarget->hasXMMInt(), DAG);
5117 // Now we have our 32-bit value zero extended in the low element of
5118 // a vector. If Idx != 0, swizzle it into place.
5120 SmallVector<int, 4> Mask;
5121 Mask.push_back(Idx);
5122 for (unsigned i = 1; i != VecElts; ++i)
5124 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5125 DAG.getUNDEF(Item.getValueType()),
5128 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5132 // If we have a constant or non-constant insertion into the low element of
5133 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5134 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5135 // depending on what the source datatype is.
5138 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5139 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5140 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5141 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5142 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5143 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(),
5145 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5146 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5147 unsigned NumBits = VT.getSizeInBits();
5148 assert((NumBits == 128 || NumBits == 256) &&
5149 "Expected an SSE or AVX value type!");
5150 EVT MiddleVT = NumBits == 128 ? MVT::v4i32 : MVT::v8i32;
5151 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5152 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5153 Subtarget->hasXMMInt(), DAG);
5154 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5158 // Is it a vector logical left shift?
5159 if (NumElems == 2 && Idx == 1 &&
5160 X86::isZeroNode(Op.getOperand(0)) &&
5161 !X86::isZeroNode(Op.getOperand(1))) {
5162 unsigned NumBits = VT.getSizeInBits();
5163 return getVShift(true, VT,
5164 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5165 VT, Op.getOperand(1)),
5166 NumBits/2, DAG, *this, dl);
5169 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5172 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5173 // is a non-constant being inserted into an element other than the low one,
5174 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5175 // movd/movss) to move this into the low element, then shuffle it into
5177 if (EVTBits == 32) {
5178 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5180 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5181 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5182 Subtarget->hasXMMInt(), DAG);
5183 SmallVector<int, 8> MaskVec;
5184 for (unsigned i = 0; i < NumElems; i++)
5185 MaskVec.push_back(i == Idx ? 0 : 1);
5186 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5190 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5191 if (Values.size() == 1) {
5192 if (EVTBits == 32) {
5193 // Instead of a shuffle like this:
5194 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5195 // Check if it's possible to issue this instead.
5196 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5197 unsigned Idx = CountTrailingZeros_32(NonZeros);
5198 SDValue Item = Op.getOperand(Idx);
5199 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5200 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5205 // A vector full of immediates; various special cases are already
5206 // handled, so this is best done with a single constant-pool load.
5210 // For AVX-length vectors, build the individual 128-bit pieces and use
5211 // shuffles to put them in place.
5212 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5213 SmallVector<SDValue, 32> V;
5214 for (unsigned i = 0; i < NumElems; ++i)
5215 V.push_back(Op.getOperand(i));
5217 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5219 // Build both the lower and upper subvector.
5220 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5221 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5224 // Recreate the wider vector with the lower and upper part.
5225 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5226 DAG.getConstant(0, MVT::i32), DAG, dl);
5227 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5231 // Let legalizer expand 2-wide build_vectors.
5232 if (EVTBits == 64) {
5233 if (NumNonZero == 1) {
5234 // One half is zero or undef.
5235 unsigned Idx = CountTrailingZeros_32(NonZeros);
5236 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5237 Op.getOperand(Idx));
5238 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5239 Subtarget->hasXMMInt(), DAG);
5244 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5245 if (EVTBits == 8 && NumElems == 16) {
5246 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5248 if (V.getNode()) return V;
5251 if (EVTBits == 16 && NumElems == 8) {
5252 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5254 if (V.getNode()) return V;
5257 // If element VT is == 32 bits, turn it into a number of shuffles.
5258 SmallVector<SDValue, 8> V;
5260 if (NumElems == 4 && NumZero > 0) {
5261 for (unsigned i = 0; i < 4; ++i) {
5262 bool isZero = !(NonZeros & (1 << i));
5264 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
5266 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5269 for (unsigned i = 0; i < 2; ++i) {
5270 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5273 V[i] = V[i*2]; // Must be a zero vector.
5276 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5279 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5282 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5287 SmallVector<int, 8> MaskVec;
5288 bool Reverse = (NonZeros & 0x3) == 2;
5289 for (unsigned i = 0; i < 2; ++i)
5290 MaskVec.push_back(Reverse ? 1-i : i);
5291 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5292 for (unsigned i = 0; i < 2; ++i)
5293 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5294 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5297 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5298 // Check for a build vector of consecutive loads.
5299 for (unsigned i = 0; i < NumElems; ++i)
5300 V[i] = Op.getOperand(i);
5302 // Check for elements which are consecutive loads.
5303 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5307 // For SSE 4.1, use insertps to put the high elements into the low element.
5308 if (getSubtarget()->hasSSE41orAVX()) {
5310 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5311 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5313 Result = DAG.getUNDEF(VT);
5315 for (unsigned i = 1; i < NumElems; ++i) {
5316 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5317 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5318 Op.getOperand(i), DAG.getIntPtrConstant(i));
5323 // Otherwise, expand into a number of unpckl*, start by extending each of
5324 // our (non-undef) elements to the full vector width with the element in the
5325 // bottom slot of the vector (which generates no code for SSE).
5326 for (unsigned i = 0; i < NumElems; ++i) {
5327 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5328 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5330 V[i] = DAG.getUNDEF(VT);
5333 // Next, we iteratively mix elements, e.g. for v4f32:
5334 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5335 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5336 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5337 unsigned EltStride = NumElems >> 1;
5338 while (EltStride != 0) {
5339 for (unsigned i = 0; i < EltStride; ++i) {
5340 // If V[i+EltStride] is undef and this is the first round of mixing,
5341 // then it is safe to just drop this shuffle: V[i] is already in the
5342 // right place, the one element (since it's the first round) being
5343 // inserted as undef can be dropped. This isn't safe for successive
5344 // rounds because they will permute elements within both vectors.
5345 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5346 EltStride == NumElems/2)
5349 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5358 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5359 // them in a MMX register. This is better than doing a stack convert.
5360 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5361 DebugLoc dl = Op.getDebugLoc();
5362 EVT ResVT = Op.getValueType();
5364 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5365 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5367 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5368 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5369 InVec = Op.getOperand(1);
5370 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5371 unsigned NumElts = ResVT.getVectorNumElements();
5372 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5373 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5374 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5376 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5377 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5378 Mask[0] = 0; Mask[1] = 2;
5379 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5381 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5384 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5385 // to create 256-bit vectors from two other 128-bit ones.
5386 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5387 DebugLoc dl = Op.getDebugLoc();
5388 EVT ResVT = Op.getValueType();
5390 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5392 SDValue V1 = Op.getOperand(0);
5393 SDValue V2 = Op.getOperand(1);
5394 unsigned NumElems = ResVT.getVectorNumElements();
5396 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5397 DAG.getConstant(0, MVT::i32), DAG, dl);
5398 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5403 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5404 EVT ResVT = Op.getValueType();
5406 assert(Op.getNumOperands() == 2);
5407 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5408 "Unsupported CONCAT_VECTORS for value type");
5410 // We support concatenate two MMX registers and place them in a MMX register.
5411 // This is better than doing a stack convert.
5412 if (ResVT.is128BitVector())
5413 return LowerMMXCONCAT_VECTORS(Op, DAG);
5415 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5416 // from two other 128-bit ones.
5417 return LowerAVXCONCAT_VECTORS(Op, DAG);
5420 // v8i16 shuffles - Prefer shuffles in the following order:
5421 // 1. [all] pshuflw, pshufhw, optional move
5422 // 2. [ssse3] 1 x pshufb
5423 // 3. [ssse3] 2 x pshufb + 1 x por
5424 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5426 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5427 SelectionDAG &DAG) const {
5428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5429 SDValue V1 = SVOp->getOperand(0);
5430 SDValue V2 = SVOp->getOperand(1);
5431 DebugLoc dl = SVOp->getDebugLoc();
5432 SmallVector<int, 8> MaskVals;
5434 // Determine if more than 1 of the words in each of the low and high quadwords
5435 // of the result come from the same quadword of one of the two inputs. Undef
5436 // mask values count as coming from any quadword, for better codegen.
5437 unsigned LoQuad[] = { 0, 0, 0, 0 };
5438 unsigned HiQuad[] = { 0, 0, 0, 0 };
5439 BitVector InputQuads(4);
5440 for (unsigned i = 0; i < 8; ++i) {
5441 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5442 int EltIdx = SVOp->getMaskElt(i);
5443 MaskVals.push_back(EltIdx);
5452 InputQuads.set(EltIdx / 4);
5455 int BestLoQuad = -1;
5456 unsigned MaxQuad = 1;
5457 for (unsigned i = 0; i < 4; ++i) {
5458 if (LoQuad[i] > MaxQuad) {
5460 MaxQuad = LoQuad[i];
5464 int BestHiQuad = -1;
5466 for (unsigned i = 0; i < 4; ++i) {
5467 if (HiQuad[i] > MaxQuad) {
5469 MaxQuad = HiQuad[i];
5473 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5474 // of the two input vectors, shuffle them into one input vector so only a
5475 // single pshufb instruction is necessary. If There are more than 2 input
5476 // quads, disable the next transformation since it does not help SSSE3.
5477 bool V1Used = InputQuads[0] || InputQuads[1];
5478 bool V2Used = InputQuads[2] || InputQuads[3];
5479 if (Subtarget->hasSSSE3orAVX()) {
5480 if (InputQuads.count() == 2 && V1Used && V2Used) {
5481 BestLoQuad = InputQuads.find_first();
5482 BestHiQuad = InputQuads.find_next(BestLoQuad);
5484 if (InputQuads.count() > 2) {
5490 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5491 // the shuffle mask. If a quad is scored as -1, that means that it contains
5492 // words from all 4 input quadwords.
5494 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5495 SmallVector<int, 8> MaskV;
5496 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5497 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5498 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5499 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5500 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5501 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5503 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5504 // source words for the shuffle, to aid later transformations.
5505 bool AllWordsInNewV = true;
5506 bool InOrder[2] = { true, true };
5507 for (unsigned i = 0; i != 8; ++i) {
5508 int idx = MaskVals[i];
5510 InOrder[i/4] = false;
5511 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5513 AllWordsInNewV = false;
5517 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5518 if (AllWordsInNewV) {
5519 for (int i = 0; i != 8; ++i) {
5520 int idx = MaskVals[i];
5523 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5524 if ((idx != i) && idx < 4)
5526 if ((idx != i) && idx > 3)
5535 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5536 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5537 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5538 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5539 unsigned TargetMask = 0;
5540 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5541 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5542 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5543 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5544 V1 = NewV.getOperand(0);
5545 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5549 // If we have SSSE3, and all words of the result are from 1 input vector,
5550 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5551 // is present, fall back to case 4.
5552 if (Subtarget->hasSSSE3orAVX()) {
5553 SmallVector<SDValue,16> pshufbMask;
5555 // If we have elements from both input vectors, set the high bit of the
5556 // shuffle mask element to zero out elements that come from V2 in the V1
5557 // mask, and elements that come from V1 in the V2 mask, so that the two
5558 // results can be OR'd together.
5559 bool TwoInputs = V1Used && V2Used;
5560 for (unsigned i = 0; i != 8; ++i) {
5561 int EltIdx = MaskVals[i] * 2;
5562 if (TwoInputs && (EltIdx >= 16)) {
5563 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5564 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5567 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5568 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5570 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5571 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5572 DAG.getNode(ISD::BUILD_VECTOR, dl,
5573 MVT::v16i8, &pshufbMask[0], 16));
5575 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5577 // Calculate the shuffle mask for the second input, shuffle it, and
5578 // OR it with the first shuffled input.
5580 for (unsigned i = 0; i != 8; ++i) {
5581 int EltIdx = MaskVals[i] * 2;
5583 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5584 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5587 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5588 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5590 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5591 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5592 DAG.getNode(ISD::BUILD_VECTOR, dl,
5593 MVT::v16i8, &pshufbMask[0], 16));
5594 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5595 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5598 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5599 // and update MaskVals with new element order.
5600 BitVector InOrder(8);
5601 if (BestLoQuad >= 0) {
5602 SmallVector<int, 8> MaskV;
5603 for (int i = 0; i != 4; ++i) {
5604 int idx = MaskVals[i];
5606 MaskV.push_back(-1);
5608 } else if ((idx / 4) == BestLoQuad) {
5609 MaskV.push_back(idx & 3);
5612 MaskV.push_back(-1);
5615 for (unsigned i = 4; i != 8; ++i)
5617 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5620 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
5621 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5623 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5627 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5628 // and update MaskVals with the new element order.
5629 if (BestHiQuad >= 0) {
5630 SmallVector<int, 8> MaskV;
5631 for (unsigned i = 0; i != 4; ++i)
5633 for (unsigned i = 4; i != 8; ++i) {
5634 int idx = MaskVals[i];
5636 MaskV.push_back(-1);
5638 } else if ((idx / 4) == BestHiQuad) {
5639 MaskV.push_back((idx & 3) + 4);
5642 MaskV.push_back(-1);
5645 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5648 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
5649 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5651 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5655 // In case BestHi & BestLo were both -1, which means each quadword has a word
5656 // from each of the four input quadwords, calculate the InOrder bitvector now
5657 // before falling through to the insert/extract cleanup.
5658 if (BestLoQuad == -1 && BestHiQuad == -1) {
5660 for (int i = 0; i != 8; ++i)
5661 if (MaskVals[i] < 0 || MaskVals[i] == i)
5665 // The other elements are put in the right place using pextrw and pinsrw.
5666 for (unsigned i = 0; i != 8; ++i) {
5669 int EltIdx = MaskVals[i];
5672 SDValue ExtOp = (EltIdx < 8)
5673 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5674 DAG.getIntPtrConstant(EltIdx))
5675 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5676 DAG.getIntPtrConstant(EltIdx - 8));
5677 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5678 DAG.getIntPtrConstant(i));
5683 // v16i8 shuffles - Prefer shuffles in the following order:
5684 // 1. [ssse3] 1 x pshufb
5685 // 2. [ssse3] 2 x pshufb + 1 x por
5686 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5688 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5690 const X86TargetLowering &TLI) {
5691 SDValue V1 = SVOp->getOperand(0);
5692 SDValue V2 = SVOp->getOperand(1);
5693 DebugLoc dl = SVOp->getDebugLoc();
5694 SmallVector<int, 16> MaskVals;
5695 SVOp->getMask(MaskVals);
5697 // If we have SSSE3, case 1 is generated when all result bytes come from
5698 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5699 // present, fall back to case 3.
5700 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5703 for (unsigned i = 0; i < 16; ++i) {
5704 int EltIdx = MaskVals[i];
5713 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5714 if (TLI.getSubtarget()->hasSSSE3orAVX()) {
5715 SmallVector<SDValue,16> pshufbMask;
5717 // If all result elements are from one input vector, then only translate
5718 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5720 // Otherwise, we have elements from both input vectors, and must zero out
5721 // elements that come from V2 in the first mask, and V1 in the second mask
5722 // so that we can OR them together.
5723 bool TwoInputs = !(V1Only || V2Only);
5724 for (unsigned i = 0; i != 16; ++i) {
5725 int EltIdx = MaskVals[i];
5726 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5727 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5730 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5732 // If all the elements are from V2, assign it to V1 and return after
5733 // building the first pshufb.
5736 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5737 DAG.getNode(ISD::BUILD_VECTOR, dl,
5738 MVT::v16i8, &pshufbMask[0], 16));
5742 // Calculate the shuffle mask for the second input, shuffle it, and
5743 // OR it with the first shuffled input.
5745 for (unsigned i = 0; i != 16; ++i) {
5746 int EltIdx = MaskVals[i];
5748 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5751 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5753 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5754 DAG.getNode(ISD::BUILD_VECTOR, dl,
5755 MVT::v16i8, &pshufbMask[0], 16));
5756 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5759 // No SSSE3 - Calculate in place words and then fix all out of place words
5760 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5761 // the 16 different words that comprise the two doublequadword input vectors.
5762 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5763 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5764 SDValue NewV = V2Only ? V2 : V1;
5765 for (int i = 0; i != 8; ++i) {
5766 int Elt0 = MaskVals[i*2];
5767 int Elt1 = MaskVals[i*2+1];
5769 // This word of the result is all undef, skip it.
5770 if (Elt0 < 0 && Elt1 < 0)
5773 // This word of the result is already in the correct place, skip it.
5774 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5776 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5779 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5780 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5783 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5784 // using a single extract together, load it and store it.
5785 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5786 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5787 DAG.getIntPtrConstant(Elt1 / 2));
5788 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5789 DAG.getIntPtrConstant(i));
5793 // If Elt1 is defined, extract it from the appropriate source. If the
5794 // source byte is not also odd, shift the extracted word left 8 bits
5795 // otherwise clear the bottom 8 bits if we need to do an or.
5797 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5798 DAG.getIntPtrConstant(Elt1 / 2));
5799 if ((Elt1 & 1) == 0)
5800 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5802 TLI.getShiftAmountTy(InsElt.getValueType())));
5804 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5805 DAG.getConstant(0xFF00, MVT::i16));
5807 // If Elt0 is defined, extract it from the appropriate source. If the
5808 // source byte is not also even, shift the extracted word right 8 bits. If
5809 // Elt1 was also defined, OR the extracted values together before
5810 // inserting them in the result.
5812 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5813 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5814 if ((Elt0 & 1) != 0)
5815 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5817 TLI.getShiftAmountTy(InsElt0.getValueType())));
5819 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5820 DAG.getConstant(0x00FF, MVT::i16));
5821 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5824 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5825 DAG.getIntPtrConstant(i));
5827 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5830 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5831 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5832 /// done when every pair / quad of shuffle mask elements point to elements in
5833 /// the right sequence. e.g.
5834 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5836 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5837 SelectionDAG &DAG, DebugLoc dl) {
5838 EVT VT = SVOp->getValueType(0);
5839 SDValue V1 = SVOp->getOperand(0);
5840 SDValue V2 = SVOp->getOperand(1);
5841 unsigned NumElems = VT.getVectorNumElements();
5842 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5844 switch (VT.getSimpleVT().SimpleTy) {
5845 default: assert(false && "Unexpected!");
5846 case MVT::v4f32: NewVT = MVT::v2f64; break;
5847 case MVT::v4i32: NewVT = MVT::v2i64; break;
5848 case MVT::v8i16: NewVT = MVT::v4i32; break;
5849 case MVT::v16i8: NewVT = MVT::v4i32; break;
5852 int Scale = NumElems / NewWidth;
5853 SmallVector<int, 8> MaskVec;
5854 for (unsigned i = 0; i < NumElems; i += Scale) {
5856 for (int j = 0; j < Scale; ++j) {
5857 int EltIdx = SVOp->getMaskElt(i+j);
5861 StartIdx = EltIdx - (EltIdx % Scale);
5862 if (EltIdx != StartIdx + j)
5866 MaskVec.push_back(-1);
5868 MaskVec.push_back(StartIdx / Scale);
5871 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5872 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5873 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5876 /// getVZextMovL - Return a zero-extending vector move low node.
5878 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5879 SDValue SrcOp, SelectionDAG &DAG,
5880 const X86Subtarget *Subtarget, DebugLoc dl) {
5881 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5882 LoadSDNode *LD = NULL;
5883 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5884 LD = dyn_cast<LoadSDNode>(SrcOp);
5886 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5888 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5889 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5890 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5891 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5892 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5894 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5895 return DAG.getNode(ISD::BITCAST, dl, VT,
5896 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5905 return DAG.getNode(ISD::BITCAST, dl, VT,
5906 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5907 DAG.getNode(ISD::BITCAST, dl,
5911 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5912 /// shuffle node referes to only one lane in the sources.
5913 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5914 EVT VT = SVOp->getValueType(0);
5915 int NumElems = VT.getVectorNumElements();
5916 int HalfSize = NumElems/2;
5917 SmallVector<int, 16> M;
5919 bool MatchA = false, MatchB = false;
5921 for (int l = 0; l < NumElems*2; l += HalfSize) {
5922 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5928 for (int l = 0; l < NumElems*2; l += HalfSize) {
5929 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5935 return MatchA && MatchB;
5938 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5939 /// which could not be matched by any known target speficic shuffle
5941 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5942 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5943 // If each half of a vector shuffle node referes to only one lane in the
5944 // source vectors, extract each used 128-bit lane and shuffle them using
5945 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5946 // the work to the legalizer.
5947 DebugLoc dl = SVOp->getDebugLoc();
5948 EVT VT = SVOp->getValueType(0);
5949 int NumElems = VT.getVectorNumElements();
5950 int HalfSize = NumElems/2;
5952 // Extract the reference for each half
5953 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5954 int FstVecOpNum = 0, SndVecOpNum = 0;
5955 for (int i = 0; i < HalfSize; ++i) {
5956 int Elt = SVOp->getMaskElt(i);
5957 if (SVOp->getMaskElt(i) < 0)
5959 FstVecOpNum = Elt/NumElems;
5960 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5963 for (int i = HalfSize; i < NumElems; ++i) {
5964 int Elt = SVOp->getMaskElt(i);
5965 if (SVOp->getMaskElt(i) < 0)
5967 SndVecOpNum = Elt/NumElems;
5968 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5972 // Extract the subvectors
5973 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5974 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5975 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5976 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5978 // Generate 128-bit shuffles
5979 SmallVector<int, 16> MaskV1, MaskV2;
5980 for (int i = 0; i < HalfSize; ++i) {
5981 int Elt = SVOp->getMaskElt(i);
5982 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5984 for (int i = HalfSize; i < NumElems; ++i) {
5985 int Elt = SVOp->getMaskElt(i);
5986 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5989 EVT NVT = V1.getValueType();
5990 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5991 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5993 // Concatenate the result back
5994 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5995 DAG.getConstant(0, MVT::i32), DAG, dl);
5996 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
6003 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6004 /// 4 elements, and match them with several different shuffle types.
6006 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6007 SDValue V1 = SVOp->getOperand(0);
6008 SDValue V2 = SVOp->getOperand(1);
6009 DebugLoc dl = SVOp->getDebugLoc();
6010 EVT VT = SVOp->getValueType(0);
6012 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6014 SmallVector<std::pair<int, int>, 8> Locs;
6016 SmallVector<int, 8> Mask1(4U, -1);
6017 SmallVector<int, 8> PermMask;
6018 SVOp->getMask(PermMask);
6022 for (unsigned i = 0; i != 4; ++i) {
6023 int Idx = PermMask[i];
6025 Locs[i] = std::make_pair(-1, -1);
6027 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6029 Locs[i] = std::make_pair(0, NumLo);
6033 Locs[i] = std::make_pair(1, NumHi);
6035 Mask1[2+NumHi] = Idx;
6041 if (NumLo <= 2 && NumHi <= 2) {
6042 // If no more than two elements come from either vector. This can be
6043 // implemented with two shuffles. First shuffle gather the elements.
6044 // The second shuffle, which takes the first shuffle as both of its
6045 // vector operands, put the elements into the right order.
6046 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6048 SmallVector<int, 8> Mask2(4U, -1);
6050 for (unsigned i = 0; i != 4; ++i) {
6051 if (Locs[i].first == -1)
6054 unsigned Idx = (i < 2) ? 0 : 4;
6055 Idx += Locs[i].first * 2 + Locs[i].second;
6060 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6061 } else if (NumLo == 3 || NumHi == 3) {
6062 // Otherwise, we must have three elements from one vector, call it X, and
6063 // one element from the other, call it Y. First, use a shufps to build an
6064 // intermediate vector with the one element from Y and the element from X
6065 // that will be in the same half in the final destination (the indexes don't
6066 // matter). Then, use a shufps to build the final vector, taking the half
6067 // containing the element from Y from the intermediate, and the other half
6070 // Normalize it so the 3 elements come from V1.
6071 CommuteVectorShuffleMask(PermMask, 4);
6075 // Find the element from V2.
6077 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6078 int Val = PermMask[HiIndex];
6085 Mask1[0] = PermMask[HiIndex];
6087 Mask1[2] = PermMask[HiIndex^1];
6089 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6092 Mask1[0] = PermMask[0];
6093 Mask1[1] = PermMask[1];
6094 Mask1[2] = HiIndex & 1 ? 6 : 4;
6095 Mask1[3] = HiIndex & 1 ? 4 : 6;
6096 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6098 Mask1[0] = HiIndex & 1 ? 2 : 0;
6099 Mask1[1] = HiIndex & 1 ? 0 : 2;
6100 Mask1[2] = PermMask[2];
6101 Mask1[3] = PermMask[3];
6106 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6110 // Break it into (shuffle shuffle_hi, shuffle_lo).
6113 SmallVector<int,8> LoMask(4U, -1);
6114 SmallVector<int,8> HiMask(4U, -1);
6116 SmallVector<int,8> *MaskPtr = &LoMask;
6117 unsigned MaskIdx = 0;
6120 for (unsigned i = 0; i != 4; ++i) {
6127 int Idx = PermMask[i];
6129 Locs[i] = std::make_pair(-1, -1);
6130 } else if (Idx < 4) {
6131 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6132 (*MaskPtr)[LoIdx] = Idx;
6135 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6136 (*MaskPtr)[HiIdx] = Idx;
6141 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6142 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6143 SmallVector<int, 8> MaskOps;
6144 for (unsigned i = 0; i != 4; ++i) {
6145 if (Locs[i].first == -1) {
6146 MaskOps.push_back(-1);
6148 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6149 MaskOps.push_back(Idx);
6152 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6155 static bool MayFoldVectorLoad(SDValue V) {
6156 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6157 V = V.getOperand(0);
6158 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6159 V = V.getOperand(0);
6160 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6161 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6162 // BUILD_VECTOR (load), undef
6163 V = V.getOperand(0);
6169 // FIXME: the version above should always be used. Since there's
6170 // a bug where several vector shuffles can't be folded because the
6171 // DAG is not updated during lowering and a node claims to have two
6172 // uses while it only has one, use this version, and let isel match
6173 // another instruction if the load really happens to have more than
6174 // one use. Remove this version after this bug get fixed.
6175 // rdar://8434668, PR8156
6176 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6177 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6178 V = V.getOperand(0);
6179 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6180 V = V.getOperand(0);
6181 if (ISD::isNormalLoad(V.getNode()))
6186 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6187 /// a vector extract, and if both can be later optimized into a single load.
6188 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6189 /// here because otherwise a target specific shuffle node is going to be
6190 /// emitted for this shuffle, and the optimization not done.
6191 /// FIXME: This is probably not the best approach, but fix the problem
6192 /// until the right path is decided.
6194 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6195 const TargetLowering &TLI) {
6196 EVT VT = V.getValueType();
6197 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6199 // Be sure that the vector shuffle is present in a pattern like this:
6200 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6204 SDNode *N = *V.getNode()->use_begin();
6205 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6208 SDValue EltNo = N->getOperand(1);
6209 if (!isa<ConstantSDNode>(EltNo))
6212 // If the bit convert changed the number of elements, it is unsafe
6213 // to examine the mask.
6214 bool HasShuffleIntoBitcast = false;
6215 if (V.getOpcode() == ISD::BITCAST) {
6216 EVT SrcVT = V.getOperand(0).getValueType();
6217 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6219 V = V.getOperand(0);
6220 HasShuffleIntoBitcast = true;
6223 // Select the input vector, guarding against out of range extract vector.
6224 unsigned NumElems = VT.getVectorNumElements();
6225 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6226 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6227 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6229 // Skip one more bit_convert if necessary
6230 if (V.getOpcode() == ISD::BITCAST)
6231 V = V.getOperand(0);
6233 if (ISD::isNormalLoad(V.getNode())) {
6234 // Is the original load suitable?
6235 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6237 // FIXME: avoid the multi-use bug that is preventing lots of
6238 // of foldings to be detected, this is still wrong of course, but
6239 // give the temporary desired behavior, and if it happens that
6240 // the load has real more uses, during isel it will not fold, and
6241 // will generate poor code.
6242 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6245 if (!HasShuffleIntoBitcast)
6248 // If there's a bitcast before the shuffle, check if the load type and
6249 // alignment is valid.
6250 unsigned Align = LN0->getAlignment();
6252 TLI.getTargetData()->getABITypeAlignment(
6253 VT.getTypeForEVT(*DAG.getContext()));
6255 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6263 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6264 EVT VT = Op.getValueType();
6266 // Canonizalize to v2f64.
6267 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6268 return DAG.getNode(ISD::BITCAST, dl, VT,
6269 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6274 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6276 SDValue V1 = Op.getOperand(0);
6277 SDValue V2 = Op.getOperand(1);
6278 EVT VT = Op.getValueType();
6280 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6282 if (HasXMMInt && VT == MVT::v2f64)
6283 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6285 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6286 return DAG.getNode(ISD::BITCAST, dl, VT,
6287 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6288 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6289 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6293 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6294 SDValue V1 = Op.getOperand(0);
6295 SDValue V2 = Op.getOperand(1);
6296 EVT VT = Op.getValueType();
6298 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6299 "unsupported shuffle type");
6301 if (V2.getOpcode() == ISD::UNDEF)
6305 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6308 static inline unsigned getSHUFPOpcode(EVT VT) {
6309 switch(VT.getSimpleVT().SimpleTy) {
6310 case MVT::v8i32: // Use fp unit for int unpack.
6312 case MVT::v4i32: // Use fp unit for int unpack.
6313 case MVT::v4f32: return X86ISD::SHUFPS;
6314 case MVT::v4i64: // Use fp unit for int unpack.
6316 case MVT::v2i64: // Use fp unit for int unpack.
6317 case MVT::v2f64: return X86ISD::SHUFPD;
6319 llvm_unreachable("Unknown type for shufp*");
6325 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) {
6326 SDValue V1 = Op.getOperand(0);
6327 SDValue V2 = Op.getOperand(1);
6328 EVT VT = Op.getValueType();
6329 unsigned NumElems = VT.getVectorNumElements();
6331 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6332 // operand of these instructions is only memory, so check if there's a
6333 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6335 bool CanFoldLoad = false;
6337 // Trivial case, when V2 comes from a load.
6338 if (MayFoldVectorLoad(V2))
6341 // When V1 is a load, it can be folded later into a store in isel, example:
6342 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6344 // (MOVLPSmr addr:$src1, VR128:$src2)
6345 // So, recognize this potential and also use MOVLPS or MOVLPD
6346 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6349 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6351 if (HasXMMInt && NumElems == 2)
6352 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6355 // If we don't care about the second element, procede to use movss.
6356 if (SVOp->getMaskElt(1) != -1)
6357 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6360 // movl and movlp will both match v2i64, but v2i64 is never matched by
6361 // movl earlier because we make it strict to avoid messing with the movlp load
6362 // folding logic (see the code above getMOVLP call). Match it here then,
6363 // this is horrible, but will stay like this until we move all shuffle
6364 // matching to x86 specific nodes. Note that for the 1st condition all
6365 // types are matched with movsd.
6367 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6368 // as to remove this logic from here, as much as possible
6369 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6370 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6371 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6374 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6376 // Invert the operand order and use SHUFPS to match it.
6377 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6378 X86::getShuffleSHUFImmediate(SVOp), DAG);
6382 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6383 const TargetLowering &TLI,
6384 const X86Subtarget *Subtarget) {
6385 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6386 EVT VT = Op.getValueType();
6387 DebugLoc dl = Op.getDebugLoc();
6388 SDValue V1 = Op.getOperand(0);
6389 SDValue V2 = Op.getOperand(1);
6391 if (isZeroShuffle(SVOp))
6392 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
6394 // Handle splat operations
6395 if (SVOp->isSplat()) {
6396 unsigned NumElem = VT.getVectorNumElements();
6397 int Size = VT.getSizeInBits();
6398 // Special case, this is the only place now where it's allowed to return
6399 // a vector_shuffle operation without using a target specific node, because
6400 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6401 // this be moved to DAGCombine instead?
6402 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6405 // Use vbroadcast whenever the splat comes from a foldable load
6406 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
6407 if (Subtarget->hasAVX() && LD.getNode())
6408 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6410 // Handle splats by matching through known shuffle masks
6411 if ((Size == 128 && NumElem <= 4) ||
6412 (Size == 256 && NumElem < 8))
6415 // All remaning splats are promoted to target supported vector shuffles.
6416 return PromoteSplat(SVOp, DAG);
6419 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6421 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6422 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6423 if (NewOp.getNode())
6424 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6425 } else if ((VT == MVT::v4i32 ||
6426 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) {
6427 // FIXME: Figure out a cleaner way to do this.
6428 // Try to make use of movq to zero out the top part.
6429 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6430 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6431 if (NewOp.getNode()) {
6432 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6433 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6434 DAG, Subtarget, dl);
6436 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6437 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6438 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6439 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6440 DAG, Subtarget, dl);
6447 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6448 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6449 SDValue V1 = Op.getOperand(0);
6450 SDValue V2 = Op.getOperand(1);
6451 EVT VT = Op.getValueType();
6452 DebugLoc dl = Op.getDebugLoc();
6453 unsigned NumElems = VT.getVectorNumElements();
6454 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6455 bool V1IsSplat = false;
6456 bool V2IsSplat = false;
6457 bool HasXMMInt = Subtarget->hasXMMInt();
6458 bool HasAVX = Subtarget->hasAVX();
6459 bool HasAVX2 = Subtarget->hasAVX2();
6460 MachineFunction &MF = DAG.getMachineFunction();
6461 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6463 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6465 assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef");
6467 // Vector shuffle lowering takes 3 steps:
6469 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6470 // narrowing and commutation of operands should be handled.
6471 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6473 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6474 // so the shuffle can be broken into other shuffles and the legalizer can
6475 // try the lowering again.
6477 // The general idea is that no vector_shuffle operation should be left to
6478 // be matched during isel, all of them must be converted to a target specific
6481 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6482 // narrowing and commutation of operands should be handled. The actual code
6483 // doesn't include all of those, work in progress...
6484 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6485 if (NewOp.getNode())
6488 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6489 // unpckh_undef). Only use pshufd if speed is more important than size.
6490 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6491 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6492 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6493 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6495 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() &&
6496 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6497 return getMOVDDup(Op, dl, V1, DAG);
6499 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6500 return getMOVHighToLow(Op, dl, DAG);
6502 // Use to match splats
6503 if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6504 (VT == MVT::v2f64 || VT == MVT::v2i64))
6505 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6507 if (X86::isPSHUFDMask(SVOp)) {
6508 // The actual implementation will match the mask in the if above and then
6509 // during isel it can match several different instructions, not only pshufd
6510 // as its name says, sad but true, emulate the behavior for now...
6511 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6512 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6514 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6516 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32))
6517 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6519 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6523 // Check if this can be converted into a logical shift.
6524 bool isLeft = false;
6527 bool isShift = HasXMMInt && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6528 if (isShift && ShVal.hasOneUse()) {
6529 // If the shifted value has multiple uses, it may be cheaper to use
6530 // v_set0 + movlhps or movhlps, etc.
6531 EVT EltVT = VT.getVectorElementType();
6532 ShAmt *= EltVT.getSizeInBits();
6533 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6536 if (X86::isMOVLMask(SVOp)) {
6537 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6538 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6539 if (!X86::isMOVLPMask(SVOp)) {
6540 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64))
6541 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6543 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6544 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6548 // FIXME: fold these into legal mask.
6549 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6550 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt);
6552 if (X86::isMOVHLPSMask(SVOp))
6553 return getMOVHighToLow(Op, dl, DAG);
6555 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6556 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6558 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6559 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6561 if (X86::isMOVLPMask(SVOp))
6562 return getMOVLP(Op, dl, DAG, HasXMMInt);
6564 if (ShouldXformToMOVHLPS(SVOp) ||
6565 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6566 return CommuteVectorShuffle(SVOp, DAG);
6569 // No better options. Use a vshl / vsrl.
6570 EVT EltVT = VT.getVectorElementType();
6571 ShAmt *= EltVT.getSizeInBits();
6572 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6575 bool Commuted = false;
6576 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6577 // 1,1,1,1 -> v8i16 though.
6578 V1IsSplat = isSplatVector(V1.getNode());
6579 V2IsSplat = isSplatVector(V2.getNode());
6581 // Canonicalize the splat or undef, if present, to be on the RHS.
6582 if (V1IsSplat && !V2IsSplat) {
6583 Op = CommuteVectorShuffle(SVOp, DAG);
6584 SVOp = cast<ShuffleVectorSDNode>(Op);
6585 V1 = SVOp->getOperand(0);
6586 V2 = SVOp->getOperand(1);
6587 std::swap(V1IsSplat, V2IsSplat);
6591 SmallVector<int, 32> M;
6594 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6595 // Shuffling low element of v1 into undef, just return v1.
6598 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6599 // the instruction selector will not match, so get a canonical MOVL with
6600 // swapped operands to undo the commute.
6601 return getMOVL(DAG, dl, VT, V2, V1);
6604 if (isUNPCKLMask(M, VT, HasAVX2))
6605 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6607 if (isUNPCKHMask(M, VT, HasAVX2))
6608 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6611 // Normalize mask so all entries that point to V2 points to its first
6612 // element then try to match unpck{h|l} again. If match, return a
6613 // new vector_shuffle with the corrected mask.
6614 SDValue NewMask = NormalizeMask(SVOp, DAG);
6615 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6616 if (NSVOp != SVOp) {
6617 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6619 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6626 // Commute is back and try unpck* again.
6627 // FIXME: this seems wrong.
6628 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6629 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6631 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6632 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6634 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6635 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6638 // Normalize the node to match x86 shuffle ops if needed
6639 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) ||
6640 isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true)))
6641 return CommuteVectorShuffle(SVOp, DAG);
6643 // The checks below are all present in isShuffleMaskLegal, but they are
6644 // inlined here right now to enable us to directly emit target specific
6645 // nodes, and remove one by one until they don't return Op anymore.
6647 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()))
6648 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6649 getShufflePALIGNRImmediate(SVOp),
6652 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6653 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6654 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6655 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6658 if (isPSHUFHWMask(M, VT))
6659 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6660 X86::getShufflePSHUFHWImmediate(SVOp),
6663 if (isPSHUFLWMask(M, VT))
6664 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6665 X86::getShufflePSHUFLWImmediate(SVOp),
6668 if (isSHUFPMask(M, VT))
6669 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6670 X86::getShuffleSHUFImmediate(SVOp), DAG);
6672 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6673 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6674 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6675 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6677 //===--------------------------------------------------------------------===//
6678 // Generate target specific nodes for 128 or 256-bit shuffles only
6679 // supported in the AVX instruction set.
6682 // Handle VMOVDDUPY permutations
6683 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6684 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6686 // Handle VPERMILPS/D* permutations
6687 if (isVPERMILPMask(M, VT, HasAVX))
6688 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6689 getShuffleVPERMILPImmediate(SVOp), DAG);
6691 // Handle VPERM2F128/VPERM2I128 permutations
6692 if (isVPERM2X128Mask(M, VT, HasAVX))
6693 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6694 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6696 // Handle VSHUFPS/DY permutations
6697 if (isVSHUFPYMask(M, VT, HasAVX))
6698 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6699 getShuffleVSHUFPYImmediate(SVOp), DAG);
6701 //===--------------------------------------------------------------------===//
6702 // Since no target specific shuffle was selected for this generic one,
6703 // lower it into other known shuffles. FIXME: this isn't true yet, but
6704 // this is the plan.
6707 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6708 if (VT == MVT::v8i16) {
6709 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6710 if (NewOp.getNode())
6714 if (VT == MVT::v16i8) {
6715 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6716 if (NewOp.getNode())
6720 // Handle all 128-bit wide vectors with 4 elements, and match them with
6721 // several different shuffle types.
6722 if (NumElems == 4 && VT.getSizeInBits() == 128)
6723 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6725 // Handle general 256-bit shuffles
6726 if (VT.is256BitVector())
6727 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6733 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6734 SelectionDAG &DAG) const {
6735 EVT VT = Op.getValueType();
6736 DebugLoc dl = Op.getDebugLoc();
6738 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6741 if (VT.getSizeInBits() == 8) {
6742 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6743 Op.getOperand(0), Op.getOperand(1));
6744 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6745 DAG.getValueType(VT));
6746 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6747 } else if (VT.getSizeInBits() == 16) {
6748 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6749 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6751 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6752 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6753 DAG.getNode(ISD::BITCAST, dl,
6757 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6758 Op.getOperand(0), Op.getOperand(1));
6759 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6760 DAG.getValueType(VT));
6761 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6762 } else if (VT == MVT::f32) {
6763 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6764 // the result back to FR32 register. It's only worth matching if the
6765 // result has a single use which is a store or a bitcast to i32. And in
6766 // the case of a store, it's not worth it if the index is a constant 0,
6767 // because a MOVSSmr can be used instead, which is smaller and faster.
6768 if (!Op.hasOneUse())
6770 SDNode *User = *Op.getNode()->use_begin();
6771 if ((User->getOpcode() != ISD::STORE ||
6772 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6773 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6774 (User->getOpcode() != ISD::BITCAST ||
6775 User->getValueType(0) != MVT::i32))
6777 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6778 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6781 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6782 } else if (VT == MVT::i32 || VT == MVT::i64) {
6783 // ExtractPS/pextrq works with constant index.
6784 if (isa<ConstantSDNode>(Op.getOperand(1)))
6792 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6793 SelectionDAG &DAG) const {
6794 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6797 SDValue Vec = Op.getOperand(0);
6798 EVT VecVT = Vec.getValueType();
6800 // If this is a 256-bit vector result, first extract the 128-bit vector and
6801 // then extract the element from the 128-bit vector.
6802 if (VecVT.getSizeInBits() == 256) {
6803 DebugLoc dl = Op.getNode()->getDebugLoc();
6804 unsigned NumElems = VecVT.getVectorNumElements();
6805 SDValue Idx = Op.getOperand(1);
6806 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6808 // Get the 128-bit vector.
6809 bool Upper = IdxVal >= NumElems/2;
6810 Vec = Extract128BitVector(Vec,
6811 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6813 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6814 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6817 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6819 if (Subtarget->hasSSE41orAVX()) {
6820 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6825 EVT VT = Op.getValueType();
6826 DebugLoc dl = Op.getDebugLoc();
6827 // TODO: handle v16i8.
6828 if (VT.getSizeInBits() == 16) {
6829 SDValue Vec = Op.getOperand(0);
6830 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6832 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6833 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6834 DAG.getNode(ISD::BITCAST, dl,
6837 // Transform it so it match pextrw which produces a 32-bit result.
6838 EVT EltVT = MVT::i32;
6839 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6840 Op.getOperand(0), Op.getOperand(1));
6841 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6842 DAG.getValueType(VT));
6843 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6844 } else if (VT.getSizeInBits() == 32) {
6845 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6849 // SHUFPS the element to the lowest double word, then movss.
6850 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6851 EVT VVT = Op.getOperand(0).getValueType();
6852 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6853 DAG.getUNDEF(VVT), Mask);
6854 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6855 DAG.getIntPtrConstant(0));
6856 } else if (VT.getSizeInBits() == 64) {
6857 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6858 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6859 // to match extract_elt for f64.
6860 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6864 // UNPCKHPD the element to the lowest double word, then movsd.
6865 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6866 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6867 int Mask[2] = { 1, -1 };
6868 EVT VVT = Op.getOperand(0).getValueType();
6869 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6870 DAG.getUNDEF(VVT), Mask);
6871 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6872 DAG.getIntPtrConstant(0));
6879 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6880 SelectionDAG &DAG) const {
6881 EVT VT = Op.getValueType();
6882 EVT EltVT = VT.getVectorElementType();
6883 DebugLoc dl = Op.getDebugLoc();
6885 SDValue N0 = Op.getOperand(0);
6886 SDValue N1 = Op.getOperand(1);
6887 SDValue N2 = Op.getOperand(2);
6889 if (VT.getSizeInBits() == 256)
6892 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6893 isa<ConstantSDNode>(N2)) {
6895 if (VT == MVT::v8i16)
6896 Opc = X86ISD::PINSRW;
6897 else if (VT == MVT::v16i8)
6898 Opc = X86ISD::PINSRB;
6900 Opc = X86ISD::PINSRB;
6902 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6904 if (N1.getValueType() != MVT::i32)
6905 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6906 if (N2.getValueType() != MVT::i32)
6907 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6908 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6909 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6910 // Bits [7:6] of the constant are the source select. This will always be
6911 // zero here. The DAG Combiner may combine an extract_elt index into these
6912 // bits. For example (insert (extract, 3), 2) could be matched by putting
6913 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6914 // Bits [5:4] of the constant are the destination select. This is the
6915 // value of the incoming immediate.
6916 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6917 // combine either bitwise AND or insert of float 0.0 to set these bits.
6918 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6919 // Create this as a scalar to vector..
6920 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6921 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6922 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6923 isa<ConstantSDNode>(N2)) {
6924 // PINSR* works with constant index.
6931 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6932 EVT VT = Op.getValueType();
6933 EVT EltVT = VT.getVectorElementType();
6935 DebugLoc dl = Op.getDebugLoc();
6936 SDValue N0 = Op.getOperand(0);
6937 SDValue N1 = Op.getOperand(1);
6938 SDValue N2 = Op.getOperand(2);
6940 // If this is a 256-bit vector result, first extract the 128-bit vector,
6941 // insert the element into the extracted half and then place it back.
6942 if (VT.getSizeInBits() == 256) {
6943 if (!isa<ConstantSDNode>(N2))
6946 // Get the desired 128-bit vector half.
6947 unsigned NumElems = VT.getVectorNumElements();
6948 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6949 bool Upper = IdxVal >= NumElems/2;
6950 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6951 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6953 // Insert the element into the desired half.
6954 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6955 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6957 // Insert the changed part back to the 256-bit vector
6958 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6961 if (Subtarget->hasSSE41orAVX())
6962 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6964 if (EltVT == MVT::i8)
6967 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6968 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6969 // as its second argument.
6970 if (N1.getValueType() != MVT::i32)
6971 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6972 if (N2.getValueType() != MVT::i32)
6973 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6974 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6980 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6981 LLVMContext *Context = DAG.getContext();
6982 DebugLoc dl = Op.getDebugLoc();
6983 EVT OpVT = Op.getValueType();
6985 // If this is a 256-bit vector result, first insert into a 128-bit
6986 // vector and then insert into the 256-bit vector.
6987 if (OpVT.getSizeInBits() > 128) {
6988 // Insert into a 128-bit vector.
6989 EVT VT128 = EVT::getVectorVT(*Context,
6990 OpVT.getVectorElementType(),
6991 OpVT.getVectorNumElements() / 2);
6993 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6995 // Insert the 128-bit vector.
6996 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6997 DAG.getConstant(0, MVT::i32),
7001 if (Op.getValueType() == MVT::v1i64 &&
7002 Op.getOperand(0).getValueType() == MVT::i64)
7003 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7005 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7006 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7007 "Expected an SSE type!");
7008 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7009 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7012 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7013 // a simple subregister reference or explicit instructions to grab
7014 // upper bits of a vector.
7016 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7017 if (Subtarget->hasAVX()) {
7018 DebugLoc dl = Op.getNode()->getDebugLoc();
7019 SDValue Vec = Op.getNode()->getOperand(0);
7020 SDValue Idx = Op.getNode()->getOperand(1);
7022 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7023 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7024 return Extract128BitVector(Vec, Idx, DAG, dl);
7030 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7031 // simple superregister reference or explicit instructions to insert
7032 // the upper bits of a vector.
7034 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7035 if (Subtarget->hasAVX()) {
7036 DebugLoc dl = Op.getNode()->getDebugLoc();
7037 SDValue Vec = Op.getNode()->getOperand(0);
7038 SDValue SubVec = Op.getNode()->getOperand(1);
7039 SDValue Idx = Op.getNode()->getOperand(2);
7041 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7042 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7043 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7049 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7050 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7051 // one of the above mentioned nodes. It has to be wrapped because otherwise
7052 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7053 // be used to form addressing mode. These wrapped nodes will be selected
7056 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7057 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7059 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7061 unsigned char OpFlag = 0;
7062 unsigned WrapperKind = X86ISD::Wrapper;
7063 CodeModel::Model M = getTargetMachine().getCodeModel();
7065 if (Subtarget->isPICStyleRIPRel() &&
7066 (M == CodeModel::Small || M == CodeModel::Kernel))
7067 WrapperKind = X86ISD::WrapperRIP;
7068 else if (Subtarget->isPICStyleGOT())
7069 OpFlag = X86II::MO_GOTOFF;
7070 else if (Subtarget->isPICStyleStubPIC())
7071 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7073 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7075 CP->getOffset(), OpFlag);
7076 DebugLoc DL = CP->getDebugLoc();
7077 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7078 // With PIC, the address is actually $g + Offset.
7080 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7081 DAG.getNode(X86ISD::GlobalBaseReg,
7082 DebugLoc(), getPointerTy()),
7089 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7090 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7092 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7094 unsigned char OpFlag = 0;
7095 unsigned WrapperKind = X86ISD::Wrapper;
7096 CodeModel::Model M = getTargetMachine().getCodeModel();
7098 if (Subtarget->isPICStyleRIPRel() &&
7099 (M == CodeModel::Small || M == CodeModel::Kernel))
7100 WrapperKind = X86ISD::WrapperRIP;
7101 else if (Subtarget->isPICStyleGOT())
7102 OpFlag = X86II::MO_GOTOFF;
7103 else if (Subtarget->isPICStyleStubPIC())
7104 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7106 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7108 DebugLoc DL = JT->getDebugLoc();
7109 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7111 // With PIC, the address is actually $g + Offset.
7113 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7114 DAG.getNode(X86ISD::GlobalBaseReg,
7115 DebugLoc(), getPointerTy()),
7122 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7123 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7125 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7127 unsigned char OpFlag = 0;
7128 unsigned WrapperKind = X86ISD::Wrapper;
7129 CodeModel::Model M = getTargetMachine().getCodeModel();
7131 if (Subtarget->isPICStyleRIPRel() &&
7132 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7133 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7134 OpFlag = X86II::MO_GOTPCREL;
7135 WrapperKind = X86ISD::WrapperRIP;
7136 } else if (Subtarget->isPICStyleGOT()) {
7137 OpFlag = X86II::MO_GOT;
7138 } else if (Subtarget->isPICStyleStubPIC()) {
7139 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7140 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7141 OpFlag = X86II::MO_DARWIN_NONLAZY;
7144 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7146 DebugLoc DL = Op.getDebugLoc();
7147 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7150 // With PIC, the address is actually $g + Offset.
7151 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7152 !Subtarget->is64Bit()) {
7153 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7154 DAG.getNode(X86ISD::GlobalBaseReg,
7155 DebugLoc(), getPointerTy()),
7159 // For symbols that require a load from a stub to get the address, emit the
7161 if (isGlobalStubReference(OpFlag))
7162 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7163 MachinePointerInfo::getGOT(), false, false, false, 0);
7169 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7170 // Create the TargetBlockAddressAddress node.
7171 unsigned char OpFlags =
7172 Subtarget->ClassifyBlockAddressReference();
7173 CodeModel::Model M = getTargetMachine().getCodeModel();
7174 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7175 DebugLoc dl = Op.getDebugLoc();
7176 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7177 /*isTarget=*/true, OpFlags);
7179 if (Subtarget->isPICStyleRIPRel() &&
7180 (M == CodeModel::Small || M == CodeModel::Kernel))
7181 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7183 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7185 // With PIC, the address is actually $g + Offset.
7186 if (isGlobalRelativeToPICBase(OpFlags)) {
7187 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7188 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7196 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7198 SelectionDAG &DAG) const {
7199 // Create the TargetGlobalAddress node, folding in the constant
7200 // offset if it is legal.
7201 unsigned char OpFlags =
7202 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7203 CodeModel::Model M = getTargetMachine().getCodeModel();
7205 if (OpFlags == X86II::MO_NO_FLAG &&
7206 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7207 // A direct static reference to a global.
7208 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7211 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7214 if (Subtarget->isPICStyleRIPRel() &&
7215 (M == CodeModel::Small || M == CodeModel::Kernel))
7216 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7218 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7220 // With PIC, the address is actually $g + Offset.
7221 if (isGlobalRelativeToPICBase(OpFlags)) {
7222 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7223 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7227 // For globals that require a load from a stub to get the address, emit the
7229 if (isGlobalStubReference(OpFlags))
7230 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7231 MachinePointerInfo::getGOT(), false, false, false, 0);
7233 // If there was a non-zero offset that we didn't fold, create an explicit
7236 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7237 DAG.getConstant(Offset, getPointerTy()));
7243 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7244 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7245 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7246 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7250 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7251 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7252 unsigned char OperandFlags) {
7253 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7254 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7255 DebugLoc dl = GA->getDebugLoc();
7256 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7257 GA->getValueType(0),
7261 SDValue Ops[] = { Chain, TGA, *InFlag };
7262 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7264 SDValue Ops[] = { Chain, TGA };
7265 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7268 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7269 MFI->setAdjustsStack(true);
7271 SDValue Flag = Chain.getValue(1);
7272 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7275 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7277 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7280 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7281 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7282 DAG.getNode(X86ISD::GlobalBaseReg,
7283 DebugLoc(), PtrVT), InFlag);
7284 InFlag = Chain.getValue(1);
7286 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7289 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7291 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7293 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7294 X86::RAX, X86II::MO_TLSGD);
7297 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7298 // "local exec" model.
7299 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7300 const EVT PtrVT, TLSModel::Model model,
7302 DebugLoc dl = GA->getDebugLoc();
7304 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7305 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7306 is64Bit ? 257 : 256));
7308 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7309 DAG.getIntPtrConstant(0),
7310 MachinePointerInfo(Ptr),
7311 false, false, false, 0);
7313 unsigned char OperandFlags = 0;
7314 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7316 unsigned WrapperKind = X86ISD::Wrapper;
7317 if (model == TLSModel::LocalExec) {
7318 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7319 } else if (is64Bit) {
7320 assert(model == TLSModel::InitialExec);
7321 OperandFlags = X86II::MO_GOTTPOFF;
7322 WrapperKind = X86ISD::WrapperRIP;
7324 assert(model == TLSModel::InitialExec);
7325 OperandFlags = X86II::MO_INDNTPOFF;
7328 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7330 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7331 GA->getValueType(0),
7332 GA->getOffset(), OperandFlags);
7333 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7335 if (model == TLSModel::InitialExec)
7336 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7337 MachinePointerInfo::getGOT(), false, false, false, 0);
7339 // The address of the thread local variable is the add of the thread
7340 // pointer with the offset of the variable.
7341 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7345 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7347 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7348 const GlobalValue *GV = GA->getGlobal();
7350 if (Subtarget->isTargetELF()) {
7351 // TODO: implement the "local dynamic" model
7352 // TODO: implement the "initial exec"model for pic executables
7354 // If GV is an alias then use the aliasee for determining
7355 // thread-localness.
7356 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7357 GV = GA->resolveAliasedGlobal(false);
7359 TLSModel::Model model
7360 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7363 case TLSModel::GeneralDynamic:
7364 case TLSModel::LocalDynamic: // not implemented
7365 if (Subtarget->is64Bit())
7366 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7367 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7369 case TLSModel::InitialExec:
7370 case TLSModel::LocalExec:
7371 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7372 Subtarget->is64Bit());
7374 } else if (Subtarget->isTargetDarwin()) {
7375 // Darwin only has one model of TLS. Lower to that.
7376 unsigned char OpFlag = 0;
7377 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7378 X86ISD::WrapperRIP : X86ISD::Wrapper;
7380 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7382 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7383 !Subtarget->is64Bit();
7385 OpFlag = X86II::MO_TLVP_PIC_BASE;
7387 OpFlag = X86II::MO_TLVP;
7388 DebugLoc DL = Op.getDebugLoc();
7389 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7390 GA->getValueType(0),
7391 GA->getOffset(), OpFlag);
7392 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7394 // With PIC32, the address is actually $g + Offset.
7396 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7397 DAG.getNode(X86ISD::GlobalBaseReg,
7398 DebugLoc(), getPointerTy()),
7401 // Lowering the machine isd will make sure everything is in the right
7403 SDValue Chain = DAG.getEntryNode();
7404 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7405 SDValue Args[] = { Chain, Offset };
7406 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7408 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7409 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7410 MFI->setAdjustsStack(true);
7412 // And our return value (tls address) is in the standard call return value
7414 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7415 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7420 "TLS not implemented for this target.");
7422 llvm_unreachable("Unreachable");
7427 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7428 /// take a 2 x i32 value to shift plus a shift amount.
7429 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7430 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7431 EVT VT = Op.getValueType();
7432 unsigned VTBits = VT.getSizeInBits();
7433 DebugLoc dl = Op.getDebugLoc();
7434 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7435 SDValue ShOpLo = Op.getOperand(0);
7436 SDValue ShOpHi = Op.getOperand(1);
7437 SDValue ShAmt = Op.getOperand(2);
7438 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7439 DAG.getConstant(VTBits - 1, MVT::i8))
7440 : DAG.getConstant(0, VT);
7443 if (Op.getOpcode() == ISD::SHL_PARTS) {
7444 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7445 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7447 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7448 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7451 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7452 DAG.getConstant(VTBits, MVT::i8));
7453 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7454 AndNode, DAG.getConstant(0, MVT::i8));
7457 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7458 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7459 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7461 if (Op.getOpcode() == ISD::SHL_PARTS) {
7462 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7463 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7465 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7466 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7469 SDValue Ops[2] = { Lo, Hi };
7470 return DAG.getMergeValues(Ops, 2, dl);
7473 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7474 SelectionDAG &DAG) const {
7475 EVT SrcVT = Op.getOperand(0).getValueType();
7477 if (SrcVT.isVector())
7480 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7481 "Unknown SINT_TO_FP to lower!");
7483 // These are really Legal; return the operand so the caller accepts it as
7485 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7487 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7488 Subtarget->is64Bit()) {
7492 DebugLoc dl = Op.getDebugLoc();
7493 unsigned Size = SrcVT.getSizeInBits()/8;
7494 MachineFunction &MF = DAG.getMachineFunction();
7495 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7496 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7497 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7499 MachinePointerInfo::getFixedStack(SSFI),
7501 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7504 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7506 SelectionDAG &DAG) const {
7508 DebugLoc DL = Op.getDebugLoc();
7510 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7512 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7514 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7516 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7518 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7519 MachineMemOperand *MMO;
7521 int SSFI = FI->getIndex();
7523 DAG.getMachineFunction()
7524 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7525 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7527 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7528 StackSlot = StackSlot.getOperand(1);
7530 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7531 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7533 Tys, Ops, array_lengthof(Ops),
7537 Chain = Result.getValue(1);
7538 SDValue InFlag = Result.getValue(2);
7540 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7541 // shouldn't be necessary except that RFP cannot be live across
7542 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7543 MachineFunction &MF = DAG.getMachineFunction();
7544 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7545 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7546 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7547 Tys = DAG.getVTList(MVT::Other);
7549 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7551 MachineMemOperand *MMO =
7552 DAG.getMachineFunction()
7553 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7554 MachineMemOperand::MOStore, SSFISize, SSFISize);
7556 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7557 Ops, array_lengthof(Ops),
7558 Op.getValueType(), MMO);
7559 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7560 MachinePointerInfo::getFixedStack(SSFI),
7561 false, false, false, 0);
7567 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7568 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7569 SelectionDAG &DAG) const {
7570 // This algorithm is not obvious. Here it is in C code, more or less:
7572 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7573 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7574 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7576 // Copy ints to xmm registers.
7577 __m128i xh = _mm_cvtsi32_si128( hi );
7578 __m128i xl = _mm_cvtsi32_si128( lo );
7580 // Combine into low half of a single xmm register.
7581 __m128i x = _mm_unpacklo_epi32( xh, xl );
7585 // Merge in appropriate exponents to give the integer bits the right
7587 x = _mm_unpacklo_epi32( x, exp );
7589 // Subtract away the biases to deal with the IEEE-754 double precision
7591 d = _mm_sub_pd( (__m128d) x, bias );
7593 // All conversions up to here are exact. The correctly rounded result is
7594 // calculated using the current rounding mode using the following
7596 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7597 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7598 // store doesn't really need to be here (except
7599 // maybe to zero the other double)
7604 DebugLoc dl = Op.getDebugLoc();
7605 LLVMContext *Context = DAG.getContext();
7607 // Build some magic constants.
7608 SmallVector<Constant*,4> CV0;
7609 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7610 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7611 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7612 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7613 Constant *C0 = ConstantVector::get(CV0);
7614 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7616 SmallVector<Constant*,2> CV1;
7618 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7620 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7621 Constant *C1 = ConstantVector::get(CV1);
7622 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7624 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7625 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7627 DAG.getIntPtrConstant(1)));
7628 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7629 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7631 DAG.getIntPtrConstant(0)));
7632 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7633 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7634 MachinePointerInfo::getConstantPool(),
7635 false, false, false, 16);
7636 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7637 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7638 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7639 MachinePointerInfo::getConstantPool(),
7640 false, false, false, 16);
7641 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7643 // Add the halves; easiest way is to swap them into another reg first.
7644 int ShufMask[2] = { 1, -1 };
7645 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7646 DAG.getUNDEF(MVT::v2f64), ShufMask);
7647 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7648 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7649 DAG.getIntPtrConstant(0));
7652 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7653 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7654 SelectionDAG &DAG) const {
7655 DebugLoc dl = Op.getDebugLoc();
7656 // FP constant to bias correct the final result.
7657 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7660 // Load the 32-bit value into an XMM register.
7661 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7664 // Zero out the upper parts of the register.
7665 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(),
7668 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7669 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7670 DAG.getIntPtrConstant(0));
7672 // Or the load with the bias.
7673 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7674 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7675 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7677 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7678 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7679 MVT::v2f64, Bias)));
7680 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7681 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7682 DAG.getIntPtrConstant(0));
7684 // Subtract the bias.
7685 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7687 // Handle final rounding.
7688 EVT DestVT = Op.getValueType();
7690 if (DestVT.bitsLT(MVT::f64)) {
7691 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7692 DAG.getIntPtrConstant(0));
7693 } else if (DestVT.bitsGT(MVT::f64)) {
7694 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7697 // Handle final rounding.
7701 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7702 SelectionDAG &DAG) const {
7703 SDValue N0 = Op.getOperand(0);
7704 DebugLoc dl = Op.getDebugLoc();
7706 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7707 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7708 // the optimization here.
7709 if (DAG.SignBitIsZero(N0))
7710 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7712 EVT SrcVT = N0.getValueType();
7713 EVT DstVT = Op.getValueType();
7714 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7715 return LowerUINT_TO_FP_i64(Op, DAG);
7716 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7717 return LowerUINT_TO_FP_i32(Op, DAG);
7719 // Make a 64-bit buffer, and use it to build an FILD.
7720 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7721 if (SrcVT == MVT::i32) {
7722 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7723 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7724 getPointerTy(), StackSlot, WordOff);
7725 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7726 StackSlot, MachinePointerInfo(),
7728 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7729 OffsetSlot, MachinePointerInfo(),
7731 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7735 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7736 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7737 StackSlot, MachinePointerInfo(),
7739 // For i64 source, we need to add the appropriate power of 2 if the input
7740 // was negative. This is the same as the optimization in
7741 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7742 // we must be careful to do the computation in x87 extended precision, not
7743 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7744 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7745 MachineMemOperand *MMO =
7746 DAG.getMachineFunction()
7747 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7748 MachineMemOperand::MOLoad, 8, 8);
7750 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7751 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7752 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7755 APInt FF(32, 0x5F800000ULL);
7757 // Check whether the sign bit is set.
7758 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7759 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7762 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7763 SDValue FudgePtr = DAG.getConstantPool(
7764 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7767 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7768 SDValue Zero = DAG.getIntPtrConstant(0);
7769 SDValue Four = DAG.getIntPtrConstant(4);
7770 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7772 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7774 // Load the value out, extending it from f32 to f80.
7775 // FIXME: Avoid the extend by constructing the right constant pool?
7776 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7777 FudgePtr, MachinePointerInfo::getConstantPool(),
7778 MVT::f32, false, false, 4);
7779 // Extend everything to 80 bits to force it to be done on x87.
7780 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7781 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7784 std::pair<SDValue,SDValue> X86TargetLowering::
7785 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7786 DebugLoc DL = Op.getDebugLoc();
7788 EVT DstTy = Op.getValueType();
7791 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7795 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7796 DstTy.getSimpleVT() >= MVT::i16 &&
7797 "Unknown FP_TO_SINT to lower!");
7799 // These are really Legal.
7800 if (DstTy == MVT::i32 &&
7801 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7802 return std::make_pair(SDValue(), SDValue());
7803 if (Subtarget->is64Bit() &&
7804 DstTy == MVT::i64 &&
7805 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7806 return std::make_pair(SDValue(), SDValue());
7808 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7810 MachineFunction &MF = DAG.getMachineFunction();
7811 unsigned MemSize = DstTy.getSizeInBits()/8;
7812 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7813 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7818 switch (DstTy.getSimpleVT().SimpleTy) {
7819 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7820 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7821 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7822 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7825 SDValue Chain = DAG.getEntryNode();
7826 SDValue Value = Op.getOperand(0);
7827 EVT TheVT = Op.getOperand(0).getValueType();
7828 if (isScalarFPTypeInSSEReg(TheVT)) {
7829 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7830 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7831 MachinePointerInfo::getFixedStack(SSFI),
7833 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7835 Chain, StackSlot, DAG.getValueType(TheVT)
7838 MachineMemOperand *MMO =
7839 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7840 MachineMemOperand::MOLoad, MemSize, MemSize);
7841 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7843 Chain = Value.getValue(1);
7844 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7845 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7848 MachineMemOperand *MMO =
7849 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7850 MachineMemOperand::MOStore, MemSize, MemSize);
7852 // Build the FP_TO_INT*_IN_MEM
7853 SDValue Ops[] = { Chain, Value, StackSlot };
7854 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7855 Ops, 3, DstTy, MMO);
7857 return std::make_pair(FIST, StackSlot);
7860 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7861 SelectionDAG &DAG) const {
7862 if (Op.getValueType().isVector())
7865 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7866 SDValue FIST = Vals.first, StackSlot = Vals.second;
7867 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7868 if (FIST.getNode() == 0) return Op;
7871 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7872 FIST, StackSlot, MachinePointerInfo(),
7873 false, false, false, 0);
7876 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7877 SelectionDAG &DAG) const {
7878 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7879 SDValue FIST = Vals.first, StackSlot = Vals.second;
7880 assert(FIST.getNode() && "Unexpected failure");
7883 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7884 FIST, StackSlot, MachinePointerInfo(),
7885 false, false, false, 0);
7888 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7889 SelectionDAG &DAG) const {
7890 LLVMContext *Context = DAG.getContext();
7891 DebugLoc dl = Op.getDebugLoc();
7892 EVT VT = Op.getValueType();
7895 EltVT = VT.getVectorElementType();
7896 SmallVector<Constant*,4> CV;
7897 if (EltVT == MVT::f64) {
7898 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7901 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7904 Constant *C = ConstantVector::get(CV);
7905 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7906 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7907 MachinePointerInfo::getConstantPool(),
7908 false, false, false, 16);
7909 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7912 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7913 LLVMContext *Context = DAG.getContext();
7914 DebugLoc dl = Op.getDebugLoc();
7915 EVT VT = Op.getValueType();
7917 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7918 if (VT.isVector()) {
7919 EltVT = VT.getVectorElementType();
7920 NumElts = VT.getVectorNumElements();
7922 SmallVector<Constant*,8> CV;
7923 if (EltVT == MVT::f64) {
7924 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7925 CV.assign(NumElts, C);
7927 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7928 CV.assign(NumElts, C);
7930 Constant *C = ConstantVector::get(CV);
7931 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7932 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7933 MachinePointerInfo::getConstantPool(),
7934 false, false, false, 16);
7935 if (VT.isVector()) {
7936 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7937 return DAG.getNode(ISD::BITCAST, dl, VT,
7938 DAG.getNode(ISD::XOR, dl, XORVT,
7939 DAG.getNode(ISD::BITCAST, dl, XORVT,
7941 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7943 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7947 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7948 LLVMContext *Context = DAG.getContext();
7949 SDValue Op0 = Op.getOperand(0);
7950 SDValue Op1 = Op.getOperand(1);
7951 DebugLoc dl = Op.getDebugLoc();
7952 EVT VT = Op.getValueType();
7953 EVT SrcVT = Op1.getValueType();
7955 // If second operand is smaller, extend it first.
7956 if (SrcVT.bitsLT(VT)) {
7957 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7960 // And if it is bigger, shrink it first.
7961 if (SrcVT.bitsGT(VT)) {
7962 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7966 // At this point the operands and the result should have the same
7967 // type, and that won't be f80 since that is not custom lowered.
7969 // First get the sign bit of second operand.
7970 SmallVector<Constant*,4> CV;
7971 if (SrcVT == MVT::f64) {
7972 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7973 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7975 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7976 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7977 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7978 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7980 Constant *C = ConstantVector::get(CV);
7981 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7982 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7983 MachinePointerInfo::getConstantPool(),
7984 false, false, false, 16);
7985 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7987 // Shift sign bit right or left if the two operands have different types.
7988 if (SrcVT.bitsGT(VT)) {
7989 // Op0 is MVT::f32, Op1 is MVT::f64.
7990 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7991 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7992 DAG.getConstant(32, MVT::i32));
7993 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7994 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7995 DAG.getIntPtrConstant(0));
7998 // Clear first operand sign bit.
8000 if (VT == MVT::f64) {
8001 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8005 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8007 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8009 C = ConstantVector::get(CV);
8010 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8011 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8012 MachinePointerInfo::getConstantPool(),
8013 false, false, false, 16);
8014 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8016 // Or the value with the sign bit.
8017 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8020 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8021 SDValue N0 = Op.getOperand(0);
8022 DebugLoc dl = Op.getDebugLoc();
8023 EVT VT = Op.getValueType();
8025 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8026 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8027 DAG.getConstant(1, VT));
8028 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8031 /// Emit nodes that will be selected as "test Op0,Op0", or something
8033 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8034 SelectionDAG &DAG) const {
8035 DebugLoc dl = Op.getDebugLoc();
8037 // CF and OF aren't always set the way we want. Determine which
8038 // of these we need.
8039 bool NeedCF = false;
8040 bool NeedOF = false;
8043 case X86::COND_A: case X86::COND_AE:
8044 case X86::COND_B: case X86::COND_BE:
8047 case X86::COND_G: case X86::COND_GE:
8048 case X86::COND_L: case X86::COND_LE:
8049 case X86::COND_O: case X86::COND_NO:
8054 // See if we can use the EFLAGS value from the operand instead of
8055 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8056 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8057 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8058 // Emit a CMP with 0, which is the TEST pattern.
8059 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8060 DAG.getConstant(0, Op.getValueType()));
8062 unsigned Opcode = 0;
8063 unsigned NumOperands = 0;
8064 switch (Op.getNode()->getOpcode()) {
8066 // Due to an isel shortcoming, be conservative if this add is likely to be
8067 // selected as part of a load-modify-store instruction. When the root node
8068 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8069 // uses of other nodes in the match, such as the ADD in this case. This
8070 // leads to the ADD being left around and reselected, with the result being
8071 // two adds in the output. Alas, even if none our users are stores, that
8072 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8073 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8074 // climbing the DAG back to the root, and it doesn't seem to be worth the
8076 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8077 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8078 if (UI->getOpcode() != ISD::CopyToReg &&
8079 UI->getOpcode() != ISD::SETCC &&
8080 UI->getOpcode() != ISD::STORE)
8083 if (ConstantSDNode *C =
8084 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8085 // An add of one will be selected as an INC.
8086 if (C->getAPIntValue() == 1) {
8087 Opcode = X86ISD::INC;
8092 // An add of negative one (subtract of one) will be selected as a DEC.
8093 if (C->getAPIntValue().isAllOnesValue()) {
8094 Opcode = X86ISD::DEC;
8100 // Otherwise use a regular EFLAGS-setting add.
8101 Opcode = X86ISD::ADD;
8105 // If the primary and result isn't used, don't bother using X86ISD::AND,
8106 // because a TEST instruction will be better.
8107 bool NonFlagUse = false;
8108 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8109 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8111 unsigned UOpNo = UI.getOperandNo();
8112 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8113 // Look pass truncate.
8114 UOpNo = User->use_begin().getOperandNo();
8115 User = *User->use_begin();
8118 if (User->getOpcode() != ISD::BRCOND &&
8119 User->getOpcode() != ISD::SETCC &&
8120 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8133 // Due to the ISEL shortcoming noted above, be conservative if this op is
8134 // likely to be selected as part of a load-modify-store instruction.
8135 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8136 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8137 if (UI->getOpcode() == ISD::STORE)
8140 // Otherwise use a regular EFLAGS-setting instruction.
8141 switch (Op.getNode()->getOpcode()) {
8142 default: llvm_unreachable("unexpected operator!");
8143 case ISD::SUB: Opcode = X86ISD::SUB; break;
8144 case ISD::OR: Opcode = X86ISD::OR; break;
8145 case ISD::XOR: Opcode = X86ISD::XOR; break;
8146 case ISD::AND: Opcode = X86ISD::AND; break;
8158 return SDValue(Op.getNode(), 1);
8165 // Emit a CMP with 0, which is the TEST pattern.
8166 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8167 DAG.getConstant(0, Op.getValueType()));
8169 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8170 SmallVector<SDValue, 4> Ops;
8171 for (unsigned i = 0; i != NumOperands; ++i)
8172 Ops.push_back(Op.getOperand(i));
8174 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8175 DAG.ReplaceAllUsesWith(Op, New);
8176 return SDValue(New.getNode(), 1);
8179 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8181 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8182 SelectionDAG &DAG) const {
8183 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8184 if (C->getAPIntValue() == 0)
8185 return EmitTest(Op0, X86CC, DAG);
8187 DebugLoc dl = Op0.getDebugLoc();
8188 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8191 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8192 /// if it's possible.
8193 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8194 DebugLoc dl, SelectionDAG &DAG) const {
8195 SDValue Op0 = And.getOperand(0);
8196 SDValue Op1 = And.getOperand(1);
8197 if (Op0.getOpcode() == ISD::TRUNCATE)
8198 Op0 = Op0.getOperand(0);
8199 if (Op1.getOpcode() == ISD::TRUNCATE)
8200 Op1 = Op1.getOperand(0);
8203 if (Op1.getOpcode() == ISD::SHL)
8204 std::swap(Op0, Op1);
8205 if (Op0.getOpcode() == ISD::SHL) {
8206 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8207 if (And00C->getZExtValue() == 1) {
8208 // If we looked past a truncate, check that it's only truncating away
8210 unsigned BitWidth = Op0.getValueSizeInBits();
8211 unsigned AndBitWidth = And.getValueSizeInBits();
8212 if (BitWidth > AndBitWidth) {
8213 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8214 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8215 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8219 RHS = Op0.getOperand(1);
8221 } else if (Op1.getOpcode() == ISD::Constant) {
8222 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8223 uint64_t AndRHSVal = AndRHS->getZExtValue();
8224 SDValue AndLHS = Op0;
8226 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8227 LHS = AndLHS.getOperand(0);
8228 RHS = AndLHS.getOperand(1);
8231 // Use BT if the immediate can't be encoded in a TEST instruction.
8232 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8234 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8238 if (LHS.getNode()) {
8239 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8240 // instruction. Since the shift amount is in-range-or-undefined, we know
8241 // that doing a bittest on the i32 value is ok. We extend to i32 because
8242 // the encoding for the i16 version is larger than the i32 version.
8243 // Also promote i16 to i32 for performance / code size reason.
8244 if (LHS.getValueType() == MVT::i8 ||
8245 LHS.getValueType() == MVT::i16)
8246 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8248 // If the operand types disagree, extend the shift amount to match. Since
8249 // BT ignores high bits (like shifts) we can use anyextend.
8250 if (LHS.getValueType() != RHS.getValueType())
8251 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8253 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8254 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8255 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8256 DAG.getConstant(Cond, MVT::i8), BT);
8262 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8264 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8266 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8267 SDValue Op0 = Op.getOperand(0);
8268 SDValue Op1 = Op.getOperand(1);
8269 DebugLoc dl = Op.getDebugLoc();
8270 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8272 // Optimize to BT if possible.
8273 // Lower (X & (1 << N)) == 0 to BT(X, N).
8274 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8275 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8276 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8277 Op1.getOpcode() == ISD::Constant &&
8278 cast<ConstantSDNode>(Op1)->isNullValue() &&
8279 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8280 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8281 if (NewSetCC.getNode())
8285 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8287 if (Op1.getOpcode() == ISD::Constant &&
8288 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8289 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8290 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8292 // If the input is a setcc, then reuse the input setcc or use a new one with
8293 // the inverted condition.
8294 if (Op0.getOpcode() == X86ISD::SETCC) {
8295 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8296 bool Invert = (CC == ISD::SETNE) ^
8297 cast<ConstantSDNode>(Op1)->isNullValue();
8298 if (!Invert) return Op0;
8300 CCode = X86::GetOppositeBranchCondition(CCode);
8301 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8302 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8306 bool isFP = Op1.getValueType().isFloatingPoint();
8307 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8308 if (X86CC == X86::COND_INVALID)
8311 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8312 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8313 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8316 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8317 // ones, and then concatenate the result back.
8318 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8319 EVT VT = Op.getValueType();
8321 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8322 "Unsupported value type for operation");
8324 int NumElems = VT.getVectorNumElements();
8325 DebugLoc dl = Op.getDebugLoc();
8326 SDValue CC = Op.getOperand(2);
8327 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8328 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8330 // Extract the LHS vectors
8331 SDValue LHS = Op.getOperand(0);
8332 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8333 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8335 // Extract the RHS vectors
8336 SDValue RHS = Op.getOperand(1);
8337 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8338 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8340 // Issue the operation on the smaller types and concatenate the result back
8341 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8342 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8343 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8344 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8345 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8349 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8351 SDValue Op0 = Op.getOperand(0);
8352 SDValue Op1 = Op.getOperand(1);
8353 SDValue CC = Op.getOperand(2);
8354 EVT VT = Op.getValueType();
8355 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8356 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8357 DebugLoc dl = Op.getDebugLoc();
8361 EVT EltVT = Op0.getValueType().getVectorElementType();
8362 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8364 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8367 // SSE Condition code mapping:
8376 switch (SetCCOpcode) {
8379 case ISD::SETEQ: SSECC = 0; break;
8381 case ISD::SETGT: Swap = true; // Fallthrough
8383 case ISD::SETOLT: SSECC = 1; break;
8385 case ISD::SETGE: Swap = true; // Fallthrough
8387 case ISD::SETOLE: SSECC = 2; break;
8388 case ISD::SETUO: SSECC = 3; break;
8390 case ISD::SETNE: SSECC = 4; break;
8391 case ISD::SETULE: Swap = true;
8392 case ISD::SETUGE: SSECC = 5; break;
8393 case ISD::SETULT: Swap = true;
8394 case ISD::SETUGT: SSECC = 6; break;
8395 case ISD::SETO: SSECC = 7; break;
8398 std::swap(Op0, Op1);
8400 // In the two special cases we can't handle, emit two comparisons.
8402 if (SetCCOpcode == ISD::SETUEQ) {
8404 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8405 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8406 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8407 } else if (SetCCOpcode == ISD::SETONE) {
8409 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8410 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8411 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8413 llvm_unreachable("Illegal FP comparison");
8415 // Handle all other FP comparisons here.
8416 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8419 // Break 256-bit integer vector compare into smaller ones.
8420 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8421 return Lower256IntVSETCC(Op, DAG);
8423 // We are handling one of the integer comparisons here. Since SSE only has
8424 // GT and EQ comparisons for integer, swapping operands and multiple
8425 // operations may be required for some comparisons.
8426 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8427 bool Swap = false, Invert = false, FlipSigns = false;
8429 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8431 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8432 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8433 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8434 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8437 switch (SetCCOpcode) {
8439 case ISD::SETNE: Invert = true;
8440 case ISD::SETEQ: Opc = EQOpc; break;
8441 case ISD::SETLT: Swap = true;
8442 case ISD::SETGT: Opc = GTOpc; break;
8443 case ISD::SETGE: Swap = true;
8444 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8445 case ISD::SETULT: Swap = true;
8446 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8447 case ISD::SETUGE: Swap = true;
8448 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8451 std::swap(Op0, Op1);
8453 // Check that the operation in question is available (most are plain SSE2,
8454 // but PCMPGTQ and PCMPEQQ have different requirements).
8455 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42orAVX())
8457 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41orAVX())
8460 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8461 // bits of the inputs before performing those operations.
8463 EVT EltVT = VT.getVectorElementType();
8464 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8466 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8467 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8469 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8470 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8473 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8475 // If the logical-not of the result is required, perform that now.
8477 Result = DAG.getNOT(dl, Result, VT);
8482 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8483 static bool isX86LogicalCmp(SDValue Op) {
8484 unsigned Opc = Op.getNode()->getOpcode();
8485 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8487 if (Op.getResNo() == 1 &&
8488 (Opc == X86ISD::ADD ||
8489 Opc == X86ISD::SUB ||
8490 Opc == X86ISD::ADC ||
8491 Opc == X86ISD::SBB ||
8492 Opc == X86ISD::SMUL ||
8493 Opc == X86ISD::UMUL ||
8494 Opc == X86ISD::INC ||
8495 Opc == X86ISD::DEC ||
8496 Opc == X86ISD::OR ||
8497 Opc == X86ISD::XOR ||
8498 Opc == X86ISD::AND))
8501 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8507 static bool isZero(SDValue V) {
8508 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8509 return C && C->isNullValue();
8512 static bool isAllOnes(SDValue V) {
8513 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8514 return C && C->isAllOnesValue();
8517 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8518 bool addTest = true;
8519 SDValue Cond = Op.getOperand(0);
8520 SDValue Op1 = Op.getOperand(1);
8521 SDValue Op2 = Op.getOperand(2);
8522 DebugLoc DL = Op.getDebugLoc();
8525 if (Cond.getOpcode() == ISD::SETCC) {
8526 SDValue NewCond = LowerSETCC(Cond, DAG);
8527 if (NewCond.getNode())
8531 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8532 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8533 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8534 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8535 if (Cond.getOpcode() == X86ISD::SETCC &&
8536 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8537 isZero(Cond.getOperand(1).getOperand(1))) {
8538 SDValue Cmp = Cond.getOperand(1);
8540 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8542 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8543 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8544 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8546 SDValue CmpOp0 = Cmp.getOperand(0);
8547 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8548 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8550 SDValue Res = // Res = 0 or -1.
8551 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8552 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8554 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8555 Res = DAG.getNOT(DL, Res, Res.getValueType());
8557 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8558 if (N2C == 0 || !N2C->isNullValue())
8559 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8564 // Look past (and (setcc_carry (cmp ...)), 1).
8565 if (Cond.getOpcode() == ISD::AND &&
8566 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8567 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8568 if (C && C->getAPIntValue() == 1)
8569 Cond = Cond.getOperand(0);
8572 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8573 // setting operand in place of the X86ISD::SETCC.
8574 unsigned CondOpcode = Cond.getOpcode();
8575 if (CondOpcode == X86ISD::SETCC ||
8576 CondOpcode == X86ISD::SETCC_CARRY) {
8577 CC = Cond.getOperand(0);
8579 SDValue Cmp = Cond.getOperand(1);
8580 unsigned Opc = Cmp.getOpcode();
8581 EVT VT = Op.getValueType();
8583 bool IllegalFPCMov = false;
8584 if (VT.isFloatingPoint() && !VT.isVector() &&
8585 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8586 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8588 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8589 Opc == X86ISD::BT) { // FIXME
8593 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8594 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8595 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8596 Cond.getOperand(0).getValueType() != MVT::i8)) {
8597 SDValue LHS = Cond.getOperand(0);
8598 SDValue RHS = Cond.getOperand(1);
8602 switch (CondOpcode) {
8603 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8604 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8605 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8606 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8607 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8608 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8609 default: llvm_unreachable("unexpected overflowing operator");
8611 if (CondOpcode == ISD::UMULO)
8612 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8615 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8617 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8619 if (CondOpcode == ISD::UMULO)
8620 Cond = X86Op.getValue(2);
8622 Cond = X86Op.getValue(1);
8624 CC = DAG.getConstant(X86Cond, MVT::i8);
8629 // Look pass the truncate.
8630 if (Cond.getOpcode() == ISD::TRUNCATE)
8631 Cond = Cond.getOperand(0);
8633 // We know the result of AND is compared against zero. Try to match
8635 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8636 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8637 if (NewSetCC.getNode()) {
8638 CC = NewSetCC.getOperand(0);
8639 Cond = NewSetCC.getOperand(1);
8646 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8647 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8650 // a < b ? -1 : 0 -> RES = ~setcc_carry
8651 // a < b ? 0 : -1 -> RES = setcc_carry
8652 // a >= b ? -1 : 0 -> RES = setcc_carry
8653 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8654 if (Cond.getOpcode() == X86ISD::CMP) {
8655 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8657 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8658 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8659 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8660 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8661 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8662 return DAG.getNOT(DL, Res, Res.getValueType());
8667 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8668 // condition is true.
8669 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8670 SDValue Ops[] = { Op2, Op1, CC, Cond };
8671 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8674 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8675 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8676 // from the AND / OR.
8677 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8678 Opc = Op.getOpcode();
8679 if (Opc != ISD::OR && Opc != ISD::AND)
8681 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8682 Op.getOperand(0).hasOneUse() &&
8683 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8684 Op.getOperand(1).hasOneUse());
8687 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8688 // 1 and that the SETCC node has a single use.
8689 static bool isXor1OfSetCC(SDValue Op) {
8690 if (Op.getOpcode() != ISD::XOR)
8692 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8693 if (N1C && N1C->getAPIntValue() == 1) {
8694 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8695 Op.getOperand(0).hasOneUse();
8700 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8701 bool addTest = true;
8702 SDValue Chain = Op.getOperand(0);
8703 SDValue Cond = Op.getOperand(1);
8704 SDValue Dest = Op.getOperand(2);
8705 DebugLoc dl = Op.getDebugLoc();
8707 bool Inverted = false;
8709 if (Cond.getOpcode() == ISD::SETCC) {
8710 // Check for setcc([su]{add,sub,mul}o == 0).
8711 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8712 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8713 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8714 Cond.getOperand(0).getResNo() == 1 &&
8715 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8716 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8717 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8718 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8719 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8720 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8722 Cond = Cond.getOperand(0);
8724 SDValue NewCond = LowerSETCC(Cond, DAG);
8725 if (NewCond.getNode())
8730 // FIXME: LowerXALUO doesn't handle these!!
8731 else if (Cond.getOpcode() == X86ISD::ADD ||
8732 Cond.getOpcode() == X86ISD::SUB ||
8733 Cond.getOpcode() == X86ISD::SMUL ||
8734 Cond.getOpcode() == X86ISD::UMUL)
8735 Cond = LowerXALUO(Cond, DAG);
8738 // Look pass (and (setcc_carry (cmp ...)), 1).
8739 if (Cond.getOpcode() == ISD::AND &&
8740 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8741 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8742 if (C && C->getAPIntValue() == 1)
8743 Cond = Cond.getOperand(0);
8746 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8747 // setting operand in place of the X86ISD::SETCC.
8748 unsigned CondOpcode = Cond.getOpcode();
8749 if (CondOpcode == X86ISD::SETCC ||
8750 CondOpcode == X86ISD::SETCC_CARRY) {
8751 CC = Cond.getOperand(0);
8753 SDValue Cmp = Cond.getOperand(1);
8754 unsigned Opc = Cmp.getOpcode();
8755 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8756 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8760 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8764 // These can only come from an arithmetic instruction with overflow,
8765 // e.g. SADDO, UADDO.
8766 Cond = Cond.getNode()->getOperand(1);
8772 CondOpcode = Cond.getOpcode();
8773 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8774 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8775 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8776 Cond.getOperand(0).getValueType() != MVT::i8)) {
8777 SDValue LHS = Cond.getOperand(0);
8778 SDValue RHS = Cond.getOperand(1);
8782 switch (CondOpcode) {
8783 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8784 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8785 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8786 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8787 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8788 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8789 default: llvm_unreachable("unexpected overflowing operator");
8792 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8793 if (CondOpcode == ISD::UMULO)
8794 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8797 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8799 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8801 if (CondOpcode == ISD::UMULO)
8802 Cond = X86Op.getValue(2);
8804 Cond = X86Op.getValue(1);
8806 CC = DAG.getConstant(X86Cond, MVT::i8);
8810 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8811 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8812 if (CondOpc == ISD::OR) {
8813 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8814 // two branches instead of an explicit OR instruction with a
8816 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8817 isX86LogicalCmp(Cmp)) {
8818 CC = Cond.getOperand(0).getOperand(0);
8819 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8820 Chain, Dest, CC, Cmp);
8821 CC = Cond.getOperand(1).getOperand(0);
8825 } else { // ISD::AND
8826 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8827 // two branches instead of an explicit AND instruction with a
8828 // separate test. However, we only do this if this block doesn't
8829 // have a fall-through edge, because this requires an explicit
8830 // jmp when the condition is false.
8831 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8832 isX86LogicalCmp(Cmp) &&
8833 Op.getNode()->hasOneUse()) {
8834 X86::CondCode CCode =
8835 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8836 CCode = X86::GetOppositeBranchCondition(CCode);
8837 CC = DAG.getConstant(CCode, MVT::i8);
8838 SDNode *User = *Op.getNode()->use_begin();
8839 // Look for an unconditional branch following this conditional branch.
8840 // We need this because we need to reverse the successors in order
8841 // to implement FCMP_OEQ.
8842 if (User->getOpcode() == ISD::BR) {
8843 SDValue FalseBB = User->getOperand(1);
8845 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8846 assert(NewBR == User);
8850 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8851 Chain, Dest, CC, Cmp);
8852 X86::CondCode CCode =
8853 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8854 CCode = X86::GetOppositeBranchCondition(CCode);
8855 CC = DAG.getConstant(CCode, MVT::i8);
8861 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8862 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8863 // It should be transformed during dag combiner except when the condition
8864 // is set by a arithmetics with overflow node.
8865 X86::CondCode CCode =
8866 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8867 CCode = X86::GetOppositeBranchCondition(CCode);
8868 CC = DAG.getConstant(CCode, MVT::i8);
8869 Cond = Cond.getOperand(0).getOperand(1);
8871 } else if (Cond.getOpcode() == ISD::SETCC &&
8872 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8873 // For FCMP_OEQ, we can emit
8874 // two branches instead of an explicit AND instruction with a
8875 // separate test. However, we only do this if this block doesn't
8876 // have a fall-through edge, because this requires an explicit
8877 // jmp when the condition is false.
8878 if (Op.getNode()->hasOneUse()) {
8879 SDNode *User = *Op.getNode()->use_begin();
8880 // Look for an unconditional branch following this conditional branch.
8881 // We need this because we need to reverse the successors in order
8882 // to implement FCMP_OEQ.
8883 if (User->getOpcode() == ISD::BR) {
8884 SDValue FalseBB = User->getOperand(1);
8886 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8887 assert(NewBR == User);
8891 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8892 Cond.getOperand(0), Cond.getOperand(1));
8893 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8894 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8895 Chain, Dest, CC, Cmp);
8896 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8901 } else if (Cond.getOpcode() == ISD::SETCC &&
8902 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8903 // For FCMP_UNE, we can emit
8904 // two branches instead of an explicit AND instruction with a
8905 // separate test. However, we only do this if this block doesn't
8906 // have a fall-through edge, because this requires an explicit
8907 // jmp when the condition is false.
8908 if (Op.getNode()->hasOneUse()) {
8909 SDNode *User = *Op.getNode()->use_begin();
8910 // Look for an unconditional branch following this conditional branch.
8911 // We need this because we need to reverse the successors in order
8912 // to implement FCMP_UNE.
8913 if (User->getOpcode() == ISD::BR) {
8914 SDValue FalseBB = User->getOperand(1);
8916 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8917 assert(NewBR == User);
8920 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8921 Cond.getOperand(0), Cond.getOperand(1));
8922 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8923 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8924 Chain, Dest, CC, Cmp);
8925 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8935 // Look pass the truncate.
8936 if (Cond.getOpcode() == ISD::TRUNCATE)
8937 Cond = Cond.getOperand(0);
8939 // We know the result of AND is compared against zero. Try to match
8941 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8942 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8943 if (NewSetCC.getNode()) {
8944 CC = NewSetCC.getOperand(0);
8945 Cond = NewSetCC.getOperand(1);
8952 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8953 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8955 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8956 Chain, Dest, CC, Cond);
8960 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8961 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8962 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8963 // that the guard pages used by the OS virtual memory manager are allocated in
8964 // correct sequence.
8966 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8967 SelectionDAG &DAG) const {
8968 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8969 getTargetMachine().Options.EnableSegmentedStacks) &&
8970 "This should be used only on Windows targets or when segmented stacks "
8972 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8973 DebugLoc dl = Op.getDebugLoc();
8976 SDValue Chain = Op.getOperand(0);
8977 SDValue Size = Op.getOperand(1);
8978 // FIXME: Ensure alignment here
8980 bool Is64Bit = Subtarget->is64Bit();
8981 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8983 if (getTargetMachine().Options.EnableSegmentedStacks) {
8984 MachineFunction &MF = DAG.getMachineFunction();
8985 MachineRegisterInfo &MRI = MF.getRegInfo();
8988 // The 64 bit implementation of segmented stacks needs to clobber both r10
8989 // r11. This makes it impossible to use it along with nested parameters.
8990 const Function *F = MF.getFunction();
8992 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8994 if (I->hasNestAttr())
8995 report_fatal_error("Cannot use segmented stacks with functions that "
8996 "have nested arguments.");
8999 const TargetRegisterClass *AddrRegClass =
9000 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9001 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9002 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9003 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9004 DAG.getRegister(Vreg, SPTy));
9005 SDValue Ops1[2] = { Value, Chain };
9006 return DAG.getMergeValues(Ops1, 2, dl);
9009 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9011 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9012 Flag = Chain.getValue(1);
9013 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9015 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9016 Flag = Chain.getValue(1);
9018 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9020 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9021 return DAG.getMergeValues(Ops1, 2, dl);
9025 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9026 MachineFunction &MF = DAG.getMachineFunction();
9027 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9029 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9030 DebugLoc DL = Op.getDebugLoc();
9032 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9033 // vastart just stores the address of the VarArgsFrameIndex slot into the
9034 // memory location argument.
9035 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9037 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9038 MachinePointerInfo(SV), false, false, 0);
9042 // gp_offset (0 - 6 * 8)
9043 // fp_offset (48 - 48 + 8 * 16)
9044 // overflow_arg_area (point to parameters coming in memory).
9046 SmallVector<SDValue, 8> MemOps;
9047 SDValue FIN = Op.getOperand(1);
9049 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9050 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9052 FIN, MachinePointerInfo(SV), false, false, 0);
9053 MemOps.push_back(Store);
9056 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9057 FIN, DAG.getIntPtrConstant(4));
9058 Store = DAG.getStore(Op.getOperand(0), DL,
9059 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9061 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9062 MemOps.push_back(Store);
9064 // Store ptr to overflow_arg_area
9065 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9066 FIN, DAG.getIntPtrConstant(4));
9067 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9069 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9070 MachinePointerInfo(SV, 8),
9072 MemOps.push_back(Store);
9074 // Store ptr to reg_save_area.
9075 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9076 FIN, DAG.getIntPtrConstant(8));
9077 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9079 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9080 MachinePointerInfo(SV, 16), false, false, 0);
9081 MemOps.push_back(Store);
9082 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9083 &MemOps[0], MemOps.size());
9086 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9087 assert(Subtarget->is64Bit() &&
9088 "LowerVAARG only handles 64-bit va_arg!");
9089 assert((Subtarget->isTargetLinux() ||
9090 Subtarget->isTargetDarwin()) &&
9091 "Unhandled target in LowerVAARG");
9092 assert(Op.getNode()->getNumOperands() == 4);
9093 SDValue Chain = Op.getOperand(0);
9094 SDValue SrcPtr = Op.getOperand(1);
9095 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9096 unsigned Align = Op.getConstantOperandVal(3);
9097 DebugLoc dl = Op.getDebugLoc();
9099 EVT ArgVT = Op.getNode()->getValueType(0);
9100 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9101 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9104 // Decide which area this value should be read from.
9105 // TODO: Implement the AMD64 ABI in its entirety. This simple
9106 // selection mechanism works only for the basic types.
9107 if (ArgVT == MVT::f80) {
9108 llvm_unreachable("va_arg for f80 not yet implemented");
9109 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9110 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9111 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9112 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9114 llvm_unreachable("Unhandled argument type in LowerVAARG");
9118 // Sanity Check: Make sure using fp_offset makes sense.
9119 assert(!getTargetMachine().Options.UseSoftFloat &&
9120 !(DAG.getMachineFunction()
9121 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9122 Subtarget->hasXMM());
9125 // Insert VAARG_64 node into the DAG
9126 // VAARG_64 returns two values: Variable Argument Address, Chain
9127 SmallVector<SDValue, 11> InstOps;
9128 InstOps.push_back(Chain);
9129 InstOps.push_back(SrcPtr);
9130 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9131 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9132 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9133 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9134 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9135 VTs, &InstOps[0], InstOps.size(),
9137 MachinePointerInfo(SV),
9142 Chain = VAARG.getValue(1);
9144 // Load the next argument and return it
9145 return DAG.getLoad(ArgVT, dl,
9148 MachinePointerInfo(),
9149 false, false, false, 0);
9152 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9153 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9154 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9155 SDValue Chain = Op.getOperand(0);
9156 SDValue DstPtr = Op.getOperand(1);
9157 SDValue SrcPtr = Op.getOperand(2);
9158 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9159 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9160 DebugLoc DL = Op.getDebugLoc();
9162 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9163 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9165 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9169 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9170 DebugLoc dl = Op.getDebugLoc();
9171 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9173 default: return SDValue(); // Don't custom lower most intrinsics.
9174 // Comparison intrinsics.
9175 case Intrinsic::x86_sse_comieq_ss:
9176 case Intrinsic::x86_sse_comilt_ss:
9177 case Intrinsic::x86_sse_comile_ss:
9178 case Intrinsic::x86_sse_comigt_ss:
9179 case Intrinsic::x86_sse_comige_ss:
9180 case Intrinsic::x86_sse_comineq_ss:
9181 case Intrinsic::x86_sse_ucomieq_ss:
9182 case Intrinsic::x86_sse_ucomilt_ss:
9183 case Intrinsic::x86_sse_ucomile_ss:
9184 case Intrinsic::x86_sse_ucomigt_ss:
9185 case Intrinsic::x86_sse_ucomige_ss:
9186 case Intrinsic::x86_sse_ucomineq_ss:
9187 case Intrinsic::x86_sse2_comieq_sd:
9188 case Intrinsic::x86_sse2_comilt_sd:
9189 case Intrinsic::x86_sse2_comile_sd:
9190 case Intrinsic::x86_sse2_comigt_sd:
9191 case Intrinsic::x86_sse2_comige_sd:
9192 case Intrinsic::x86_sse2_comineq_sd:
9193 case Intrinsic::x86_sse2_ucomieq_sd:
9194 case Intrinsic::x86_sse2_ucomilt_sd:
9195 case Intrinsic::x86_sse2_ucomile_sd:
9196 case Intrinsic::x86_sse2_ucomigt_sd:
9197 case Intrinsic::x86_sse2_ucomige_sd:
9198 case Intrinsic::x86_sse2_ucomineq_sd: {
9200 ISD::CondCode CC = ISD::SETCC_INVALID;
9203 case Intrinsic::x86_sse_comieq_ss:
9204 case Intrinsic::x86_sse2_comieq_sd:
9208 case Intrinsic::x86_sse_comilt_ss:
9209 case Intrinsic::x86_sse2_comilt_sd:
9213 case Intrinsic::x86_sse_comile_ss:
9214 case Intrinsic::x86_sse2_comile_sd:
9218 case Intrinsic::x86_sse_comigt_ss:
9219 case Intrinsic::x86_sse2_comigt_sd:
9223 case Intrinsic::x86_sse_comige_ss:
9224 case Intrinsic::x86_sse2_comige_sd:
9228 case Intrinsic::x86_sse_comineq_ss:
9229 case Intrinsic::x86_sse2_comineq_sd:
9233 case Intrinsic::x86_sse_ucomieq_ss:
9234 case Intrinsic::x86_sse2_ucomieq_sd:
9235 Opc = X86ISD::UCOMI;
9238 case Intrinsic::x86_sse_ucomilt_ss:
9239 case Intrinsic::x86_sse2_ucomilt_sd:
9240 Opc = X86ISD::UCOMI;
9243 case Intrinsic::x86_sse_ucomile_ss:
9244 case Intrinsic::x86_sse2_ucomile_sd:
9245 Opc = X86ISD::UCOMI;
9248 case Intrinsic::x86_sse_ucomigt_ss:
9249 case Intrinsic::x86_sse2_ucomigt_sd:
9250 Opc = X86ISD::UCOMI;
9253 case Intrinsic::x86_sse_ucomige_ss:
9254 case Intrinsic::x86_sse2_ucomige_sd:
9255 Opc = X86ISD::UCOMI;
9258 case Intrinsic::x86_sse_ucomineq_ss:
9259 case Intrinsic::x86_sse2_ucomineq_sd:
9260 Opc = X86ISD::UCOMI;
9265 SDValue LHS = Op.getOperand(1);
9266 SDValue RHS = Op.getOperand(2);
9267 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9268 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9269 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9270 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9271 DAG.getConstant(X86CC, MVT::i8), Cond);
9272 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9274 // Arithmetic intrinsics.
9275 case Intrinsic::x86_sse3_hadd_ps:
9276 case Intrinsic::x86_sse3_hadd_pd:
9277 case Intrinsic::x86_avx_hadd_ps_256:
9278 case Intrinsic::x86_avx_hadd_pd_256:
9279 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9280 Op.getOperand(1), Op.getOperand(2));
9281 case Intrinsic::x86_sse3_hsub_ps:
9282 case Intrinsic::x86_sse3_hsub_pd:
9283 case Intrinsic::x86_avx_hsub_ps_256:
9284 case Intrinsic::x86_avx_hsub_pd_256:
9285 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9286 Op.getOperand(1), Op.getOperand(2));
9287 case Intrinsic::x86_avx2_psllv_d:
9288 case Intrinsic::x86_avx2_psllv_q:
9289 case Intrinsic::x86_avx2_psllv_d_256:
9290 case Intrinsic::x86_avx2_psllv_q_256:
9291 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9292 Op.getOperand(1), Op.getOperand(2));
9293 case Intrinsic::x86_avx2_psrlv_d:
9294 case Intrinsic::x86_avx2_psrlv_q:
9295 case Intrinsic::x86_avx2_psrlv_d_256:
9296 case Intrinsic::x86_avx2_psrlv_q_256:
9297 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9298 Op.getOperand(1), Op.getOperand(2));
9299 case Intrinsic::x86_avx2_psrav_d:
9300 case Intrinsic::x86_avx2_psrav_d_256:
9301 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9302 Op.getOperand(1), Op.getOperand(2));
9304 // ptest and testp intrinsics. The intrinsic these come from are designed to
9305 // return an integer value, not just an instruction so lower it to the ptest
9306 // or testp pattern and a setcc for the result.
9307 case Intrinsic::x86_sse41_ptestz:
9308 case Intrinsic::x86_sse41_ptestc:
9309 case Intrinsic::x86_sse41_ptestnzc:
9310 case Intrinsic::x86_avx_ptestz_256:
9311 case Intrinsic::x86_avx_ptestc_256:
9312 case Intrinsic::x86_avx_ptestnzc_256:
9313 case Intrinsic::x86_avx_vtestz_ps:
9314 case Intrinsic::x86_avx_vtestc_ps:
9315 case Intrinsic::x86_avx_vtestnzc_ps:
9316 case Intrinsic::x86_avx_vtestz_pd:
9317 case Intrinsic::x86_avx_vtestc_pd:
9318 case Intrinsic::x86_avx_vtestnzc_pd:
9319 case Intrinsic::x86_avx_vtestz_ps_256:
9320 case Intrinsic::x86_avx_vtestc_ps_256:
9321 case Intrinsic::x86_avx_vtestnzc_ps_256:
9322 case Intrinsic::x86_avx_vtestz_pd_256:
9323 case Intrinsic::x86_avx_vtestc_pd_256:
9324 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9325 bool IsTestPacked = false;
9328 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9329 case Intrinsic::x86_avx_vtestz_ps:
9330 case Intrinsic::x86_avx_vtestz_pd:
9331 case Intrinsic::x86_avx_vtestz_ps_256:
9332 case Intrinsic::x86_avx_vtestz_pd_256:
9333 IsTestPacked = true; // Fallthrough
9334 case Intrinsic::x86_sse41_ptestz:
9335 case Intrinsic::x86_avx_ptestz_256:
9337 X86CC = X86::COND_E;
9339 case Intrinsic::x86_avx_vtestc_ps:
9340 case Intrinsic::x86_avx_vtestc_pd:
9341 case Intrinsic::x86_avx_vtestc_ps_256:
9342 case Intrinsic::x86_avx_vtestc_pd_256:
9343 IsTestPacked = true; // Fallthrough
9344 case Intrinsic::x86_sse41_ptestc:
9345 case Intrinsic::x86_avx_ptestc_256:
9347 X86CC = X86::COND_B;
9349 case Intrinsic::x86_avx_vtestnzc_ps:
9350 case Intrinsic::x86_avx_vtestnzc_pd:
9351 case Intrinsic::x86_avx_vtestnzc_ps_256:
9352 case Intrinsic::x86_avx_vtestnzc_pd_256:
9353 IsTestPacked = true; // Fallthrough
9354 case Intrinsic::x86_sse41_ptestnzc:
9355 case Intrinsic::x86_avx_ptestnzc_256:
9357 X86CC = X86::COND_A;
9361 SDValue LHS = Op.getOperand(1);
9362 SDValue RHS = Op.getOperand(2);
9363 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9364 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9365 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9366 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9367 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9370 // Fix vector shift instructions where the last operand is a non-immediate
9372 case Intrinsic::x86_avx2_pslli_w:
9373 case Intrinsic::x86_avx2_pslli_d:
9374 case Intrinsic::x86_avx2_pslli_q:
9375 case Intrinsic::x86_avx2_psrli_w:
9376 case Intrinsic::x86_avx2_psrli_d:
9377 case Intrinsic::x86_avx2_psrli_q:
9378 case Intrinsic::x86_avx2_psrai_w:
9379 case Intrinsic::x86_avx2_psrai_d:
9380 case Intrinsic::x86_sse2_pslli_w:
9381 case Intrinsic::x86_sse2_pslli_d:
9382 case Intrinsic::x86_sse2_pslli_q:
9383 case Intrinsic::x86_sse2_psrli_w:
9384 case Intrinsic::x86_sse2_psrli_d:
9385 case Intrinsic::x86_sse2_psrli_q:
9386 case Intrinsic::x86_sse2_psrai_w:
9387 case Intrinsic::x86_sse2_psrai_d:
9388 case Intrinsic::x86_mmx_pslli_w:
9389 case Intrinsic::x86_mmx_pslli_d:
9390 case Intrinsic::x86_mmx_pslli_q:
9391 case Intrinsic::x86_mmx_psrli_w:
9392 case Intrinsic::x86_mmx_psrli_d:
9393 case Intrinsic::x86_mmx_psrli_q:
9394 case Intrinsic::x86_mmx_psrai_w:
9395 case Intrinsic::x86_mmx_psrai_d: {
9396 SDValue ShAmt = Op.getOperand(2);
9397 if (isa<ConstantSDNode>(ShAmt))
9400 unsigned NewIntNo = 0;
9401 EVT ShAmtVT = MVT::v4i32;
9403 case Intrinsic::x86_sse2_pslli_w:
9404 NewIntNo = Intrinsic::x86_sse2_psll_w;
9406 case Intrinsic::x86_sse2_pslli_d:
9407 NewIntNo = Intrinsic::x86_sse2_psll_d;
9409 case Intrinsic::x86_sse2_pslli_q:
9410 NewIntNo = Intrinsic::x86_sse2_psll_q;
9412 case Intrinsic::x86_sse2_psrli_w:
9413 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9415 case Intrinsic::x86_sse2_psrli_d:
9416 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9418 case Intrinsic::x86_sse2_psrli_q:
9419 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9421 case Intrinsic::x86_sse2_psrai_w:
9422 NewIntNo = Intrinsic::x86_sse2_psra_w;
9424 case Intrinsic::x86_sse2_psrai_d:
9425 NewIntNo = Intrinsic::x86_sse2_psra_d;
9427 case Intrinsic::x86_avx2_pslli_w:
9428 NewIntNo = Intrinsic::x86_avx2_psll_w;
9430 case Intrinsic::x86_avx2_pslli_d:
9431 NewIntNo = Intrinsic::x86_avx2_psll_d;
9433 case Intrinsic::x86_avx2_pslli_q:
9434 NewIntNo = Intrinsic::x86_avx2_psll_q;
9436 case Intrinsic::x86_avx2_psrli_w:
9437 NewIntNo = Intrinsic::x86_avx2_psrl_w;
9439 case Intrinsic::x86_avx2_psrli_d:
9440 NewIntNo = Intrinsic::x86_avx2_psrl_d;
9442 case Intrinsic::x86_avx2_psrli_q:
9443 NewIntNo = Intrinsic::x86_avx2_psrl_q;
9445 case Intrinsic::x86_avx2_psrai_w:
9446 NewIntNo = Intrinsic::x86_avx2_psra_w;
9448 case Intrinsic::x86_avx2_psrai_d:
9449 NewIntNo = Intrinsic::x86_avx2_psra_d;
9452 ShAmtVT = MVT::v2i32;
9454 case Intrinsic::x86_mmx_pslli_w:
9455 NewIntNo = Intrinsic::x86_mmx_psll_w;
9457 case Intrinsic::x86_mmx_pslli_d:
9458 NewIntNo = Intrinsic::x86_mmx_psll_d;
9460 case Intrinsic::x86_mmx_pslli_q:
9461 NewIntNo = Intrinsic::x86_mmx_psll_q;
9463 case Intrinsic::x86_mmx_psrli_w:
9464 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9466 case Intrinsic::x86_mmx_psrli_d:
9467 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9469 case Intrinsic::x86_mmx_psrli_q:
9470 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9472 case Intrinsic::x86_mmx_psrai_w:
9473 NewIntNo = Intrinsic::x86_mmx_psra_w;
9475 case Intrinsic::x86_mmx_psrai_d:
9476 NewIntNo = Intrinsic::x86_mmx_psra_d;
9478 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9484 // The vector shift intrinsics with scalars uses 32b shift amounts but
9485 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9489 ShOps[1] = DAG.getConstant(0, MVT::i32);
9490 if (ShAmtVT == MVT::v4i32) {
9491 ShOps[2] = DAG.getUNDEF(MVT::i32);
9492 ShOps[3] = DAG.getUNDEF(MVT::i32);
9493 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9495 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9496 // FIXME this must be lowered to get rid of the invalid type.
9499 EVT VT = Op.getValueType();
9500 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9501 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9502 DAG.getConstant(NewIntNo, MVT::i32),
9503 Op.getOperand(1), ShAmt);
9508 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9509 SelectionDAG &DAG) const {
9510 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9511 MFI->setReturnAddressIsTaken(true);
9513 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9514 DebugLoc dl = Op.getDebugLoc();
9517 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9519 DAG.getConstant(TD->getPointerSize(),
9520 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9521 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9522 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9524 MachinePointerInfo(), false, false, false, 0);
9527 // Just load the return address.
9528 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9529 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9530 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9533 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9534 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9535 MFI->setFrameAddressIsTaken(true);
9537 EVT VT = Op.getValueType();
9538 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9539 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9540 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9541 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9543 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9544 MachinePointerInfo(),
9545 false, false, false, 0);
9549 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9550 SelectionDAG &DAG) const {
9551 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9554 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9555 MachineFunction &MF = DAG.getMachineFunction();
9556 SDValue Chain = Op.getOperand(0);
9557 SDValue Offset = Op.getOperand(1);
9558 SDValue Handler = Op.getOperand(2);
9559 DebugLoc dl = Op.getDebugLoc();
9561 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9562 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9564 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9566 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9567 DAG.getIntPtrConstant(TD->getPointerSize()));
9568 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9569 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9571 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9572 MF.getRegInfo().addLiveOut(StoreAddrReg);
9574 return DAG.getNode(X86ISD::EH_RETURN, dl,
9576 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9579 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9580 SelectionDAG &DAG) const {
9581 return Op.getOperand(0);
9584 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9585 SelectionDAG &DAG) const {
9586 SDValue Root = Op.getOperand(0);
9587 SDValue Trmp = Op.getOperand(1); // trampoline
9588 SDValue FPtr = Op.getOperand(2); // nested function
9589 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9590 DebugLoc dl = Op.getDebugLoc();
9592 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9594 if (Subtarget->is64Bit()) {
9595 SDValue OutChains[6];
9597 // Large code-model.
9598 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9599 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9601 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9602 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9604 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9606 // Load the pointer to the nested function into R11.
9607 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9608 SDValue Addr = Trmp;
9609 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9610 Addr, MachinePointerInfo(TrmpAddr),
9613 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9614 DAG.getConstant(2, MVT::i64));
9615 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9616 MachinePointerInfo(TrmpAddr, 2),
9619 // Load the 'nest' parameter value into R10.
9620 // R10 is specified in X86CallingConv.td
9621 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9622 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9623 DAG.getConstant(10, MVT::i64));
9624 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9625 Addr, MachinePointerInfo(TrmpAddr, 10),
9628 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9629 DAG.getConstant(12, MVT::i64));
9630 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9631 MachinePointerInfo(TrmpAddr, 12),
9634 // Jump to the nested function.
9635 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9636 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9637 DAG.getConstant(20, MVT::i64));
9638 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9639 Addr, MachinePointerInfo(TrmpAddr, 20),
9642 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9643 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9644 DAG.getConstant(22, MVT::i64));
9645 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9646 MachinePointerInfo(TrmpAddr, 22),
9649 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9651 const Function *Func =
9652 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9653 CallingConv::ID CC = Func->getCallingConv();
9658 llvm_unreachable("Unsupported calling convention");
9659 case CallingConv::C:
9660 case CallingConv::X86_StdCall: {
9661 // Pass 'nest' parameter in ECX.
9662 // Must be kept in sync with X86CallingConv.td
9665 // Check that ECX wasn't needed by an 'inreg' parameter.
9666 FunctionType *FTy = Func->getFunctionType();
9667 const AttrListPtr &Attrs = Func->getAttributes();
9669 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9670 unsigned InRegCount = 0;
9673 for (FunctionType::param_iterator I = FTy->param_begin(),
9674 E = FTy->param_end(); I != E; ++I, ++Idx)
9675 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9676 // FIXME: should only count parameters that are lowered to integers.
9677 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9679 if (InRegCount > 2) {
9680 report_fatal_error("Nest register in use - reduce number of inreg"
9686 case CallingConv::X86_FastCall:
9687 case CallingConv::X86_ThisCall:
9688 case CallingConv::Fast:
9689 // Pass 'nest' parameter in EAX.
9690 // Must be kept in sync with X86CallingConv.td
9695 SDValue OutChains[4];
9698 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9699 DAG.getConstant(10, MVT::i32));
9700 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9702 // This is storing the opcode for MOV32ri.
9703 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9704 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9705 OutChains[0] = DAG.getStore(Root, dl,
9706 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9707 Trmp, MachinePointerInfo(TrmpAddr),
9710 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9711 DAG.getConstant(1, MVT::i32));
9712 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9713 MachinePointerInfo(TrmpAddr, 1),
9716 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9717 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9718 DAG.getConstant(5, MVT::i32));
9719 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9720 MachinePointerInfo(TrmpAddr, 5),
9723 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9724 DAG.getConstant(6, MVT::i32));
9725 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9726 MachinePointerInfo(TrmpAddr, 6),
9729 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9733 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9734 SelectionDAG &DAG) const {
9736 The rounding mode is in bits 11:10 of FPSR, and has the following
9743 FLT_ROUNDS, on the other hand, expects the following:
9750 To perform the conversion, we do:
9751 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9754 MachineFunction &MF = DAG.getMachineFunction();
9755 const TargetMachine &TM = MF.getTarget();
9756 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9757 unsigned StackAlignment = TFI.getStackAlignment();
9758 EVT VT = Op.getValueType();
9759 DebugLoc DL = Op.getDebugLoc();
9761 // Save FP Control Word to stack slot
9762 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9763 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9766 MachineMemOperand *MMO =
9767 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9768 MachineMemOperand::MOStore, 2, 2);
9770 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9771 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9772 DAG.getVTList(MVT::Other),
9773 Ops, 2, MVT::i16, MMO);
9775 // Load FP Control Word from stack slot
9776 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9777 MachinePointerInfo(), false, false, false, 0);
9779 // Transform as necessary
9781 DAG.getNode(ISD::SRL, DL, MVT::i16,
9782 DAG.getNode(ISD::AND, DL, MVT::i16,
9783 CWD, DAG.getConstant(0x800, MVT::i16)),
9784 DAG.getConstant(11, MVT::i8));
9786 DAG.getNode(ISD::SRL, DL, MVT::i16,
9787 DAG.getNode(ISD::AND, DL, MVT::i16,
9788 CWD, DAG.getConstant(0x400, MVT::i16)),
9789 DAG.getConstant(9, MVT::i8));
9792 DAG.getNode(ISD::AND, DL, MVT::i16,
9793 DAG.getNode(ISD::ADD, DL, MVT::i16,
9794 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9795 DAG.getConstant(1, MVT::i16)),
9796 DAG.getConstant(3, MVT::i16));
9799 return DAG.getNode((VT.getSizeInBits() < 16 ?
9800 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9803 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9804 EVT VT = Op.getValueType();
9806 unsigned NumBits = VT.getSizeInBits();
9807 DebugLoc dl = Op.getDebugLoc();
9809 Op = Op.getOperand(0);
9810 if (VT == MVT::i8) {
9811 // Zero extend to i32 since there is not an i8 bsr.
9813 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9816 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9817 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9818 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9820 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9823 DAG.getConstant(NumBits+NumBits-1, OpVT),
9824 DAG.getConstant(X86::COND_E, MVT::i8),
9827 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9829 // Finally xor with NumBits-1.
9830 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9833 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9837 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9838 EVT VT = Op.getValueType();
9840 unsigned NumBits = VT.getSizeInBits();
9841 DebugLoc dl = Op.getDebugLoc();
9843 Op = Op.getOperand(0);
9844 if (VT == MVT::i8) {
9846 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9849 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9850 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9851 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9853 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9856 DAG.getConstant(NumBits, OpVT),
9857 DAG.getConstant(X86::COND_E, MVT::i8),
9860 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9863 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9867 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9868 // ones, and then concatenate the result back.
9869 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9870 EVT VT = Op.getValueType();
9872 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9873 "Unsupported value type for operation");
9875 int NumElems = VT.getVectorNumElements();
9876 DebugLoc dl = Op.getDebugLoc();
9877 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9878 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9880 // Extract the LHS vectors
9881 SDValue LHS = Op.getOperand(0);
9882 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9883 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9885 // Extract the RHS vectors
9886 SDValue RHS = Op.getOperand(1);
9887 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9888 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9890 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9891 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9893 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9894 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9895 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9898 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9899 assert(Op.getValueType().getSizeInBits() == 256 &&
9900 Op.getValueType().isInteger() &&
9901 "Only handle AVX 256-bit vector integer operation");
9902 return Lower256IntArith(Op, DAG);
9905 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9906 assert(Op.getValueType().getSizeInBits() == 256 &&
9907 Op.getValueType().isInteger() &&
9908 "Only handle AVX 256-bit vector integer operation");
9909 return Lower256IntArith(Op, DAG);
9912 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9913 EVT VT = Op.getValueType();
9915 // Decompose 256-bit ops into smaller 128-bit ops.
9916 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
9917 return Lower256IntArith(Op, DAG);
9919 DebugLoc dl = Op.getDebugLoc();
9921 SDValue A = Op.getOperand(0);
9922 SDValue B = Op.getOperand(1);
9924 if (VT == MVT::v4i64) {
9925 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
9927 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
9928 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
9929 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
9930 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
9931 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
9933 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
9934 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
9935 // return AloBlo + AloBhi + AhiBlo;
9937 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9938 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9939 A, DAG.getConstant(32, MVT::i32));
9940 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9941 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9942 B, DAG.getConstant(32, MVT::i32));
9943 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9944 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9946 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9947 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9949 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9950 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9952 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9953 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9954 AloBhi, DAG.getConstant(32, MVT::i32));
9955 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9956 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9957 AhiBlo, DAG.getConstant(32, MVT::i32));
9958 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9959 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9963 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9965 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9966 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9967 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9968 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9969 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9971 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9972 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9973 // return AloBlo + AloBhi + AhiBlo;
9975 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9976 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9977 A, DAG.getConstant(32, MVT::i32));
9978 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9979 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9980 B, DAG.getConstant(32, MVT::i32));
9981 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9982 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9984 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9985 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9987 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9988 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9990 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9991 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9992 AloBhi, DAG.getConstant(32, MVT::i32));
9993 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9994 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9995 AhiBlo, DAG.getConstant(32, MVT::i32));
9996 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9997 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10001 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10003 EVT VT = Op.getValueType();
10004 DebugLoc dl = Op.getDebugLoc();
10005 SDValue R = Op.getOperand(0);
10006 SDValue Amt = Op.getOperand(1);
10007 LLVMContext *Context = DAG.getContext();
10009 if (!Subtarget->hasXMMInt())
10012 // Optimize shl/srl/sra with constant shift amount.
10013 if (isSplatVector(Amt.getNode())) {
10014 SDValue SclrAmt = Amt->getOperand(0);
10015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10016 uint64_t ShiftAmt = C->getZExtValue();
10018 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) {
10019 // Make a large shift.
10021 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10022 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10023 R, DAG.getConstant(ShiftAmt, MVT::i32));
10024 // Zero out the rightmost bits.
10025 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10027 return DAG.getNode(ISD::AND, dl, VT, SHL,
10028 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10031 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
10032 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10033 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10034 R, DAG.getConstant(ShiftAmt, MVT::i32));
10036 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
10037 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10038 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10039 R, DAG.getConstant(ShiftAmt, MVT::i32));
10041 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
10042 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10043 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10044 R, DAG.getConstant(ShiftAmt, MVT::i32));
10046 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) {
10047 // Make a large shift.
10049 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10050 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10051 R, DAG.getConstant(ShiftAmt, MVT::i32));
10052 // Zero out the leftmost bits.
10053 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10055 return DAG.getNode(ISD::AND, dl, VT, SRL,
10056 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10059 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
10060 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10061 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10062 R, DAG.getConstant(ShiftAmt, MVT::i32));
10064 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
10065 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10066 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10067 R, DAG.getConstant(ShiftAmt, MVT::i32));
10069 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
10070 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10071 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10072 R, DAG.getConstant(ShiftAmt, MVT::i32));
10074 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
10075 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10076 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10077 R, DAG.getConstant(ShiftAmt, MVT::i32));
10079 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
10080 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10081 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10082 R, DAG.getConstant(ShiftAmt, MVT::i32));
10084 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) {
10085 if (ShiftAmt == 7) {
10086 // R s>> 7 === R s< 0
10087 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
10088 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10091 // R s>> a === ((R u>> a) ^ m) - m
10092 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10093 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10095 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10096 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10097 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10101 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10102 if (Op.getOpcode() == ISD::SHL) {
10103 // Make a large shift.
10105 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10106 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
10107 R, DAG.getConstant(ShiftAmt, MVT::i32));
10108 // Zero out the rightmost bits.
10109 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10111 return DAG.getNode(ISD::AND, dl, VT, SHL,
10112 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10114 if (Op.getOpcode() == ISD::SRL) {
10115 // Make a large shift.
10117 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10118 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
10119 R, DAG.getConstant(ShiftAmt, MVT::i32));
10120 // Zero out the leftmost bits.
10121 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10123 return DAG.getNode(ISD::AND, dl, VT, SRL,
10124 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10126 if (Op.getOpcode() == ISD::SRA) {
10127 if (ShiftAmt == 7) {
10128 // R s>> 7 === R s< 0
10129 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
10130 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10133 // R s>> a === ((R u>> a) ^ m) - m
10134 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10135 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10137 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10138 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10139 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10146 // Lower SHL with variable shift amount.
10147 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10148 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10149 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10150 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
10152 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10154 std::vector<Constant*> CV(4, CI);
10155 Constant *C = ConstantVector::get(CV);
10156 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10157 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10158 MachinePointerInfo::getConstantPool(),
10159 false, false, false, 16);
10161 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10162 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10163 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10164 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10166 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10167 assert((Subtarget->hasSSE2() || Subtarget->hasAVX()) &&
10168 "Need SSE2 for pslli/pcmpeq.");
10171 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10172 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10173 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
10175 // Turn 'a' into a mask suitable for VSELECT
10176 SDValue VSelM = DAG.getConstant(0x80, VT);
10177 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10178 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10179 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10182 SDValue CM1 = DAG.getConstant(0x0f, VT);
10183 SDValue CM2 = DAG.getConstant(0x3f, VT);
10185 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10186 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10187 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10188 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10189 DAG.getConstant(4, MVT::i32));
10190 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10193 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10194 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10195 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10196 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10199 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10200 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10201 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10202 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10203 DAG.getConstant(2, MVT::i32));
10204 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10207 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10208 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10209 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10210 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10213 // return VSELECT(r, r+r, a);
10214 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10215 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10219 // Decompose 256-bit shifts into smaller 128-bit shifts.
10220 if (VT.getSizeInBits() == 256) {
10221 int NumElems = VT.getVectorNumElements();
10222 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10223 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10225 // Extract the two vectors
10226 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10227 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10230 // Recreate the shift amount vectors
10231 SDValue Amt1, Amt2;
10232 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10233 // Constant shift amount
10234 SmallVector<SDValue, 4> Amt1Csts;
10235 SmallVector<SDValue, 4> Amt2Csts;
10236 for (int i = 0; i < NumElems/2; ++i)
10237 Amt1Csts.push_back(Amt->getOperand(i));
10238 for (int i = NumElems/2; i < NumElems; ++i)
10239 Amt2Csts.push_back(Amt->getOperand(i));
10241 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10242 &Amt1Csts[0], NumElems/2);
10243 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10244 &Amt2Csts[0], NumElems/2);
10246 // Variable shift amount
10247 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10248 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10252 // Issue new vector shifts for the smaller types
10253 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10254 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10256 // Concatenate the result back
10257 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10263 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10264 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10265 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10266 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10267 // has only one use.
10268 SDNode *N = Op.getNode();
10269 SDValue LHS = N->getOperand(0);
10270 SDValue RHS = N->getOperand(1);
10271 unsigned BaseOp = 0;
10273 DebugLoc DL = Op.getDebugLoc();
10274 switch (Op.getOpcode()) {
10275 default: llvm_unreachable("Unknown ovf instruction!");
10277 // A subtract of one will be selected as a INC. Note that INC doesn't
10278 // set CF, so we can't do this for UADDO.
10279 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10281 BaseOp = X86ISD::INC;
10282 Cond = X86::COND_O;
10285 BaseOp = X86ISD::ADD;
10286 Cond = X86::COND_O;
10289 BaseOp = X86ISD::ADD;
10290 Cond = X86::COND_B;
10293 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10294 // set CF, so we can't do this for USUBO.
10295 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10297 BaseOp = X86ISD::DEC;
10298 Cond = X86::COND_O;
10301 BaseOp = X86ISD::SUB;
10302 Cond = X86::COND_O;
10305 BaseOp = X86ISD::SUB;
10306 Cond = X86::COND_B;
10309 BaseOp = X86ISD::SMUL;
10310 Cond = X86::COND_O;
10312 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10313 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10315 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10318 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10319 DAG.getConstant(X86::COND_O, MVT::i32),
10320 SDValue(Sum.getNode(), 2));
10322 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10326 // Also sets EFLAGS.
10327 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10328 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10331 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10332 DAG.getConstant(Cond, MVT::i32),
10333 SDValue(Sum.getNode(), 1));
10335 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10338 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10339 SelectionDAG &DAG) const {
10340 DebugLoc dl = Op.getDebugLoc();
10341 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10342 EVT VT = Op.getValueType();
10344 if (Subtarget->hasXMMInt() && VT.isVector()) {
10345 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10346 ExtraVT.getScalarType().getSizeInBits();
10347 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10349 unsigned SHLIntrinsicsID = 0;
10350 unsigned SRAIntrinsicsID = 0;
10351 switch (VT.getSimpleVT().SimpleTy) {
10355 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10356 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10359 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10360 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10364 if (!Subtarget->hasAVX())
10366 if (!Subtarget->hasAVX2()) {
10367 // needs to be split
10368 int NumElems = VT.getVectorNumElements();
10369 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10370 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10372 // Extract the LHS vectors
10373 SDValue LHS = Op.getOperand(0);
10374 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10375 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10377 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10378 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10380 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10381 int ExtraNumElems = ExtraVT.getVectorNumElements();
10382 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10384 SDValue Extra = DAG.getValueType(ExtraVT);
10386 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10387 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10389 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10391 if (VT == MVT::v8i32) {
10392 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d;
10393 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d;
10395 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w;
10396 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w;
10400 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10401 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10402 Op.getOperand(0), ShAmt);
10404 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10405 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10413 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10414 DebugLoc dl = Op.getDebugLoc();
10416 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10417 // There isn't any reason to disable it if the target processor supports it.
10418 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) {
10419 SDValue Chain = Op.getOperand(0);
10420 SDValue Zero = DAG.getConstant(0, MVT::i32);
10422 DAG.getRegister(X86::ESP, MVT::i32), // Base
10423 DAG.getTargetConstant(1, MVT::i8), // Scale
10424 DAG.getRegister(0, MVT::i32), // Index
10425 DAG.getTargetConstant(0, MVT::i32), // Disp
10426 DAG.getRegister(0, MVT::i32), // Segment.
10431 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10432 array_lengthof(Ops));
10433 return SDValue(Res, 0);
10436 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10438 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10440 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10441 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10442 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10443 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10445 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10446 if (!Op1 && !Op2 && !Op3 && Op4)
10447 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10449 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10450 if (Op1 && !Op2 && !Op3 && !Op4)
10451 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10453 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10455 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10458 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10459 SelectionDAG &DAG) const {
10460 DebugLoc dl = Op.getDebugLoc();
10461 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10462 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10463 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10464 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10466 // The only fence that needs an instruction is a sequentially-consistent
10467 // cross-thread fence.
10468 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10469 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10470 // no-sse2). There isn't any reason to disable it if the target processor
10472 if (Subtarget->hasXMMInt() || Subtarget->is64Bit())
10473 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10475 SDValue Chain = Op.getOperand(0);
10476 SDValue Zero = DAG.getConstant(0, MVT::i32);
10478 DAG.getRegister(X86::ESP, MVT::i32), // Base
10479 DAG.getTargetConstant(1, MVT::i8), // Scale
10480 DAG.getRegister(0, MVT::i32), // Index
10481 DAG.getTargetConstant(0, MVT::i32), // Disp
10482 DAG.getRegister(0, MVT::i32), // Segment.
10487 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10488 array_lengthof(Ops));
10489 return SDValue(Res, 0);
10492 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10493 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10497 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10498 EVT T = Op.getValueType();
10499 DebugLoc DL = Op.getDebugLoc();
10502 switch(T.getSimpleVT().SimpleTy) {
10504 assert(false && "Invalid value type!");
10505 case MVT::i8: Reg = X86::AL; size = 1; break;
10506 case MVT::i16: Reg = X86::AX; size = 2; break;
10507 case MVT::i32: Reg = X86::EAX; size = 4; break;
10509 assert(Subtarget->is64Bit() && "Node not type legal!");
10510 Reg = X86::RAX; size = 8;
10513 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10514 Op.getOperand(2), SDValue());
10515 SDValue Ops[] = { cpIn.getValue(0),
10518 DAG.getTargetConstant(size, MVT::i8),
10519 cpIn.getValue(1) };
10520 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10521 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10522 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10525 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10529 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10530 SelectionDAG &DAG) const {
10531 assert(Subtarget->is64Bit() && "Result not type legalized?");
10532 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10533 SDValue TheChain = Op.getOperand(0);
10534 DebugLoc dl = Op.getDebugLoc();
10535 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10536 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10537 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10539 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10540 DAG.getConstant(32, MVT::i8));
10542 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10545 return DAG.getMergeValues(Ops, 2, dl);
10548 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10549 SelectionDAG &DAG) const {
10550 EVT SrcVT = Op.getOperand(0).getValueType();
10551 EVT DstVT = Op.getValueType();
10552 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() &&
10553 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10554 assert((DstVT == MVT::i64 ||
10555 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10556 "Unexpected custom BITCAST");
10557 // i64 <=> MMX conversions are Legal.
10558 if (SrcVT==MVT::i64 && DstVT.isVector())
10560 if (DstVT==MVT::i64 && SrcVT.isVector())
10562 // MMX <=> MMX conversions are Legal.
10563 if (SrcVT.isVector() && DstVT.isVector())
10565 // All other conversions need to be expanded.
10569 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10570 SDNode *Node = Op.getNode();
10571 DebugLoc dl = Node->getDebugLoc();
10572 EVT T = Node->getValueType(0);
10573 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10574 DAG.getConstant(0, T), Node->getOperand(2));
10575 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10576 cast<AtomicSDNode>(Node)->getMemoryVT(),
10577 Node->getOperand(0),
10578 Node->getOperand(1), negOp,
10579 cast<AtomicSDNode>(Node)->getSrcValue(),
10580 cast<AtomicSDNode>(Node)->getAlignment(),
10581 cast<AtomicSDNode>(Node)->getOrdering(),
10582 cast<AtomicSDNode>(Node)->getSynchScope());
10585 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10586 SDNode *Node = Op.getNode();
10587 DebugLoc dl = Node->getDebugLoc();
10588 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10590 // Convert seq_cst store -> xchg
10591 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10592 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10593 // (The only way to get a 16-byte store is cmpxchg16b)
10594 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10595 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10596 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10597 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10598 cast<AtomicSDNode>(Node)->getMemoryVT(),
10599 Node->getOperand(0),
10600 Node->getOperand(1), Node->getOperand(2),
10601 cast<AtomicSDNode>(Node)->getMemOperand(),
10602 cast<AtomicSDNode>(Node)->getOrdering(),
10603 cast<AtomicSDNode>(Node)->getSynchScope());
10604 return Swap.getValue(1);
10606 // Other atomic stores have a simple pattern.
10610 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10611 EVT VT = Op.getNode()->getValueType(0);
10613 // Let legalize expand this if it isn't a legal type yet.
10614 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10617 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10620 bool ExtraOp = false;
10621 switch (Op.getOpcode()) {
10622 default: assert(0 && "Invalid code");
10623 case ISD::ADDC: Opc = X86ISD::ADD; break;
10624 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10625 case ISD::SUBC: Opc = X86ISD::SUB; break;
10626 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10630 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10632 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10633 Op.getOperand(1), Op.getOperand(2));
10636 /// LowerOperation - Provide custom lowering hooks for some operations.
10638 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10639 switch (Op.getOpcode()) {
10640 default: llvm_unreachable("Should not custom lower this!");
10641 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10642 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10643 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10644 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10645 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10646 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10647 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10648 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10649 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10650 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10651 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10652 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10653 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10654 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10655 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10656 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10657 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10658 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10659 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10660 case ISD::SHL_PARTS:
10661 case ISD::SRA_PARTS:
10662 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10663 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10664 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10665 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10666 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10667 case ISD::FABS: return LowerFABS(Op, DAG);
10668 case ISD::FNEG: return LowerFNEG(Op, DAG);
10669 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10670 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10671 case ISD::SETCC: return LowerSETCC(Op, DAG);
10672 case ISD::SELECT: return LowerSELECT(Op, DAG);
10673 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10674 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10675 case ISD::VASTART: return LowerVASTART(Op, DAG);
10676 case ISD::VAARG: return LowerVAARG(Op, DAG);
10677 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10678 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10679 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10680 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10681 case ISD::FRAME_TO_ARGS_OFFSET:
10682 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10683 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10684 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10685 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10686 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10687 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10688 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10689 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10690 case ISD::MUL: return LowerMUL(Op, DAG);
10693 case ISD::SHL: return LowerShift(Op, DAG);
10699 case ISD::UMULO: return LowerXALUO(Op, DAG);
10700 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10701 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10705 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10706 case ISD::ADD: return LowerADD(Op, DAG);
10707 case ISD::SUB: return LowerSUB(Op, DAG);
10711 static void ReplaceATOMIC_LOAD(SDNode *Node,
10712 SmallVectorImpl<SDValue> &Results,
10713 SelectionDAG &DAG) {
10714 DebugLoc dl = Node->getDebugLoc();
10715 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10717 // Convert wide load -> cmpxchg8b/cmpxchg16b
10718 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10719 // (The only way to get a 16-byte load is cmpxchg16b)
10720 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10721 SDValue Zero = DAG.getConstant(0, VT);
10722 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10723 Node->getOperand(0),
10724 Node->getOperand(1), Zero, Zero,
10725 cast<AtomicSDNode>(Node)->getMemOperand(),
10726 cast<AtomicSDNode>(Node)->getOrdering(),
10727 cast<AtomicSDNode>(Node)->getSynchScope());
10728 Results.push_back(Swap.getValue(0));
10729 Results.push_back(Swap.getValue(1));
10732 void X86TargetLowering::
10733 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10734 SelectionDAG &DAG, unsigned NewOp) const {
10735 DebugLoc dl = Node->getDebugLoc();
10736 assert (Node->getValueType(0) == MVT::i64 &&
10737 "Only know how to expand i64 atomics");
10739 SDValue Chain = Node->getOperand(0);
10740 SDValue In1 = Node->getOperand(1);
10741 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10742 Node->getOperand(2), DAG.getIntPtrConstant(0));
10743 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10744 Node->getOperand(2), DAG.getIntPtrConstant(1));
10745 SDValue Ops[] = { Chain, In1, In2L, In2H };
10746 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10748 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10749 cast<MemSDNode>(Node)->getMemOperand());
10750 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10751 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10752 Results.push_back(Result.getValue(2));
10755 /// ReplaceNodeResults - Replace a node with an illegal result type
10756 /// with a new node built out of custom code.
10757 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10758 SmallVectorImpl<SDValue>&Results,
10759 SelectionDAG &DAG) const {
10760 DebugLoc dl = N->getDebugLoc();
10761 switch (N->getOpcode()) {
10763 assert(false && "Do not know how to custom type legalize this operation!");
10765 case ISD::SIGN_EXTEND_INREG:
10770 // We don't want to expand or promote these.
10772 case ISD::FP_TO_SINT: {
10773 std::pair<SDValue,SDValue> Vals =
10774 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10775 SDValue FIST = Vals.first, StackSlot = Vals.second;
10776 if (FIST.getNode() != 0) {
10777 EVT VT = N->getValueType(0);
10778 // Return a load from the stack slot.
10779 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10780 MachinePointerInfo(),
10781 false, false, false, 0));
10785 case ISD::READCYCLECOUNTER: {
10786 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10787 SDValue TheChain = N->getOperand(0);
10788 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10789 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10791 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10793 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10794 SDValue Ops[] = { eax, edx };
10795 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10796 Results.push_back(edx.getValue(1));
10799 case ISD::ATOMIC_CMP_SWAP: {
10800 EVT T = N->getValueType(0);
10801 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10802 bool Regs64bit = T == MVT::i128;
10803 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10804 SDValue cpInL, cpInH;
10805 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10806 DAG.getConstant(0, HalfT));
10807 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10808 DAG.getConstant(1, HalfT));
10809 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10810 Regs64bit ? X86::RAX : X86::EAX,
10812 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10813 Regs64bit ? X86::RDX : X86::EDX,
10814 cpInH, cpInL.getValue(1));
10815 SDValue swapInL, swapInH;
10816 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10817 DAG.getConstant(0, HalfT));
10818 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10819 DAG.getConstant(1, HalfT));
10820 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10821 Regs64bit ? X86::RBX : X86::EBX,
10822 swapInL, cpInH.getValue(1));
10823 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10824 Regs64bit ? X86::RCX : X86::ECX,
10825 swapInH, swapInL.getValue(1));
10826 SDValue Ops[] = { swapInH.getValue(0),
10828 swapInH.getValue(1) };
10829 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10830 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10831 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10832 X86ISD::LCMPXCHG8_DAG;
10833 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10835 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10836 Regs64bit ? X86::RAX : X86::EAX,
10837 HalfT, Result.getValue(1));
10838 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10839 Regs64bit ? X86::RDX : X86::EDX,
10840 HalfT, cpOutL.getValue(2));
10841 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10842 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10843 Results.push_back(cpOutH.getValue(1));
10846 case ISD::ATOMIC_LOAD_ADD:
10847 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10849 case ISD::ATOMIC_LOAD_AND:
10850 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10852 case ISD::ATOMIC_LOAD_NAND:
10853 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10855 case ISD::ATOMIC_LOAD_OR:
10856 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10858 case ISD::ATOMIC_LOAD_SUB:
10859 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10861 case ISD::ATOMIC_LOAD_XOR:
10862 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10864 case ISD::ATOMIC_SWAP:
10865 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10867 case ISD::ATOMIC_LOAD:
10868 ReplaceATOMIC_LOAD(N, Results, DAG);
10872 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10874 default: return NULL;
10875 case X86ISD::BSF: return "X86ISD::BSF";
10876 case X86ISD::BSR: return "X86ISD::BSR";
10877 case X86ISD::SHLD: return "X86ISD::SHLD";
10878 case X86ISD::SHRD: return "X86ISD::SHRD";
10879 case X86ISD::FAND: return "X86ISD::FAND";
10880 case X86ISD::FOR: return "X86ISD::FOR";
10881 case X86ISD::FXOR: return "X86ISD::FXOR";
10882 case X86ISD::FSRL: return "X86ISD::FSRL";
10883 case X86ISD::FILD: return "X86ISD::FILD";
10884 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10885 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10886 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10887 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10888 case X86ISD::FLD: return "X86ISD::FLD";
10889 case X86ISD::FST: return "X86ISD::FST";
10890 case X86ISD::CALL: return "X86ISD::CALL";
10891 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10892 case X86ISD::BT: return "X86ISD::BT";
10893 case X86ISD::CMP: return "X86ISD::CMP";
10894 case X86ISD::COMI: return "X86ISD::COMI";
10895 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10896 case X86ISD::SETCC: return "X86ISD::SETCC";
10897 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10898 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10899 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10900 case X86ISD::CMOV: return "X86ISD::CMOV";
10901 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10902 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10903 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10904 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10905 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10906 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10907 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10908 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10909 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10910 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10911 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10912 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10913 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10914 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10915 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10916 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10917 case X86ISD::HADD: return "X86ISD::HADD";
10918 case X86ISD::HSUB: return "X86ISD::HSUB";
10919 case X86ISD::FHADD: return "X86ISD::FHADD";
10920 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10921 case X86ISD::FMAX: return "X86ISD::FMAX";
10922 case X86ISD::FMIN: return "X86ISD::FMIN";
10923 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10924 case X86ISD::FRCP: return "X86ISD::FRCP";
10925 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10926 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10927 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10928 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10929 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10930 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10931 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10932 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10933 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10934 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10935 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10936 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10937 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10938 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10939 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10940 case X86ISD::VSHL: return "X86ISD::VSHL";
10941 case X86ISD::VSRL: return "X86ISD::VSRL";
10942 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10943 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10944 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10945 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10946 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10947 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10948 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10949 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10950 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10951 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10952 case X86ISD::ADD: return "X86ISD::ADD";
10953 case X86ISD::SUB: return "X86ISD::SUB";
10954 case X86ISD::ADC: return "X86ISD::ADC";
10955 case X86ISD::SBB: return "X86ISD::SBB";
10956 case X86ISD::SMUL: return "X86ISD::SMUL";
10957 case X86ISD::UMUL: return "X86ISD::UMUL";
10958 case X86ISD::INC: return "X86ISD::INC";
10959 case X86ISD::DEC: return "X86ISD::DEC";
10960 case X86ISD::OR: return "X86ISD::OR";
10961 case X86ISD::XOR: return "X86ISD::XOR";
10962 case X86ISD::AND: return "X86ISD::AND";
10963 case X86ISD::ANDN: return "X86ISD::ANDN";
10964 case X86ISD::BLSI: return "X86ISD::BLSI";
10965 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
10966 case X86ISD::BLSR: return "X86ISD::BLSR";
10967 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10968 case X86ISD::PTEST: return "X86ISD::PTEST";
10969 case X86ISD::TESTP: return "X86ISD::TESTP";
10970 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10971 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10972 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10973 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10974 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10975 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10976 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10977 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10978 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10979 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10980 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10981 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10982 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10983 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10984 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10985 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10986 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10987 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10988 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10989 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10990 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
10991 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
10992 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10993 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
10994 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
10995 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10996 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10997 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10998 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10999 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11003 // isLegalAddressingMode - Return true if the addressing mode represented
11004 // by AM is legal for this target, for a load/store of the specified type.
11005 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11007 // X86 supports extremely general addressing modes.
11008 CodeModel::Model M = getTargetMachine().getCodeModel();
11009 Reloc::Model R = getTargetMachine().getRelocationModel();
11011 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11012 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11017 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11019 // If a reference to this global requires an extra load, we can't fold it.
11020 if (isGlobalStubReference(GVFlags))
11023 // If BaseGV requires a register for the PIC base, we cannot also have a
11024 // BaseReg specified.
11025 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11028 // If lower 4G is not available, then we must use rip-relative addressing.
11029 if ((M != CodeModel::Small || R != Reloc::Static) &&
11030 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11034 switch (AM.Scale) {
11040 // These scales always work.
11045 // These scales are formed with basereg+scalereg. Only accept if there is
11050 default: // Other stuff never works.
11058 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11059 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11061 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11062 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11063 if (NumBits1 <= NumBits2)
11068 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11069 if (!VT1.isInteger() || !VT2.isInteger())
11071 unsigned NumBits1 = VT1.getSizeInBits();
11072 unsigned NumBits2 = VT2.getSizeInBits();
11073 if (NumBits1 <= NumBits2)
11078 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11079 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11080 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11083 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11084 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11085 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11088 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11089 // i16 instructions are longer (0x66 prefix) and potentially slower.
11090 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11093 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11094 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11095 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11096 /// are assumed to be legal.
11098 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11100 // Very little shuffling can be done for 64-bit vectors right now.
11101 if (VT.getSizeInBits() == 64)
11104 // FIXME: pshufb, blends, shifts.
11105 return (VT.getVectorNumElements() == 2 ||
11106 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11107 isMOVLMask(M, VT) ||
11108 isSHUFPMask(M, VT) ||
11109 isPSHUFDMask(M, VT) ||
11110 isPSHUFHWMask(M, VT) ||
11111 isPSHUFLWMask(M, VT) ||
11112 isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()) ||
11113 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11114 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11115 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11116 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11120 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11122 unsigned NumElts = VT.getVectorNumElements();
11123 // FIXME: This collection of masks seems suspect.
11126 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11127 return (isMOVLMask(Mask, VT) ||
11128 isCommutedMOVLMask(Mask, VT, true) ||
11129 isSHUFPMask(Mask, VT) ||
11130 isSHUFPMask(Mask, VT, /* Commuted */ true));
11135 //===----------------------------------------------------------------------===//
11136 // X86 Scheduler Hooks
11137 //===----------------------------------------------------------------------===//
11139 // private utility function
11140 MachineBasicBlock *
11141 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11142 MachineBasicBlock *MBB,
11149 TargetRegisterClass *RC,
11150 bool invSrc) const {
11151 // For the atomic bitwise operator, we generate
11154 // ld t1 = [bitinstr.addr]
11155 // op t2 = t1, [bitinstr.val]
11157 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11159 // fallthrough -->nextMBB
11160 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11161 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11162 MachineFunction::iterator MBBIter = MBB;
11165 /// First build the CFG
11166 MachineFunction *F = MBB->getParent();
11167 MachineBasicBlock *thisMBB = MBB;
11168 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11169 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11170 F->insert(MBBIter, newMBB);
11171 F->insert(MBBIter, nextMBB);
11173 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11174 nextMBB->splice(nextMBB->begin(), thisMBB,
11175 llvm::next(MachineBasicBlock::iterator(bInstr)),
11177 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11179 // Update thisMBB to fall through to newMBB
11180 thisMBB->addSuccessor(newMBB);
11182 // newMBB jumps to itself and fall through to nextMBB
11183 newMBB->addSuccessor(nextMBB);
11184 newMBB->addSuccessor(newMBB);
11186 // Insert instructions into newMBB based on incoming instruction
11187 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11188 "unexpected number of operands");
11189 DebugLoc dl = bInstr->getDebugLoc();
11190 MachineOperand& destOper = bInstr->getOperand(0);
11191 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11192 int numArgs = bInstr->getNumOperands() - 1;
11193 for (int i=0; i < numArgs; ++i)
11194 argOpers[i] = &bInstr->getOperand(i+1);
11196 // x86 address has 4 operands: base, index, scale, and displacement
11197 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11198 int valArgIndx = lastAddrIndx + 1;
11200 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11201 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11202 for (int i=0; i <= lastAddrIndx; ++i)
11203 (*MIB).addOperand(*argOpers[i]);
11205 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11207 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11212 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11213 assert((argOpers[valArgIndx]->isReg() ||
11214 argOpers[valArgIndx]->isImm()) &&
11215 "invalid operand");
11216 if (argOpers[valArgIndx]->isReg())
11217 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11219 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11221 (*MIB).addOperand(*argOpers[valArgIndx]);
11223 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11226 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11227 for (int i=0; i <= lastAddrIndx; ++i)
11228 (*MIB).addOperand(*argOpers[i]);
11230 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11231 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11232 bInstr->memoperands_end());
11234 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11235 MIB.addReg(EAXreg);
11238 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11240 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11244 // private utility function: 64 bit atomics on 32 bit host.
11245 MachineBasicBlock *
11246 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11247 MachineBasicBlock *MBB,
11252 bool invSrc) const {
11253 // For the atomic bitwise operator, we generate
11254 // thisMBB (instructions are in pairs, except cmpxchg8b)
11255 // ld t1,t2 = [bitinstr.addr]
11257 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11258 // op t5, t6 <- out1, out2, [bitinstr.val]
11259 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11260 // mov ECX, EBX <- t5, t6
11261 // mov EAX, EDX <- t1, t2
11262 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11263 // mov t3, t4 <- EAX, EDX
11265 // result in out1, out2
11266 // fallthrough -->nextMBB
11268 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11269 const unsigned LoadOpc = X86::MOV32rm;
11270 const unsigned NotOpc = X86::NOT32r;
11271 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11272 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11273 MachineFunction::iterator MBBIter = MBB;
11276 /// First build the CFG
11277 MachineFunction *F = MBB->getParent();
11278 MachineBasicBlock *thisMBB = MBB;
11279 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11280 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11281 F->insert(MBBIter, newMBB);
11282 F->insert(MBBIter, nextMBB);
11284 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11285 nextMBB->splice(nextMBB->begin(), thisMBB,
11286 llvm::next(MachineBasicBlock::iterator(bInstr)),
11288 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11290 // Update thisMBB to fall through to newMBB
11291 thisMBB->addSuccessor(newMBB);
11293 // newMBB jumps to itself and fall through to nextMBB
11294 newMBB->addSuccessor(nextMBB);
11295 newMBB->addSuccessor(newMBB);
11297 DebugLoc dl = bInstr->getDebugLoc();
11298 // Insert instructions into newMBB based on incoming instruction
11299 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11300 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11301 "unexpected number of operands");
11302 MachineOperand& dest1Oper = bInstr->getOperand(0);
11303 MachineOperand& dest2Oper = bInstr->getOperand(1);
11304 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11305 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11306 argOpers[i] = &bInstr->getOperand(i+2);
11308 // We use some of the operands multiple times, so conservatively just
11309 // clear any kill flags that might be present.
11310 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11311 argOpers[i]->setIsKill(false);
11314 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11315 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11317 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11318 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11319 for (int i=0; i <= lastAddrIndx; ++i)
11320 (*MIB).addOperand(*argOpers[i]);
11321 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11322 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11323 // add 4 to displacement.
11324 for (int i=0; i <= lastAddrIndx-2; ++i)
11325 (*MIB).addOperand(*argOpers[i]);
11326 MachineOperand newOp3 = *(argOpers[3]);
11327 if (newOp3.isImm())
11328 newOp3.setImm(newOp3.getImm()+4);
11330 newOp3.setOffset(newOp3.getOffset()+4);
11331 (*MIB).addOperand(newOp3);
11332 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11334 // t3/4 are defined later, at the bottom of the loop
11335 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11336 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11337 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11338 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11339 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11340 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11342 // The subsequent operations should be using the destination registers of
11343 //the PHI instructions.
11345 t1 = F->getRegInfo().createVirtualRegister(RC);
11346 t2 = F->getRegInfo().createVirtualRegister(RC);
11347 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11348 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11350 t1 = dest1Oper.getReg();
11351 t2 = dest2Oper.getReg();
11354 int valArgIndx = lastAddrIndx + 1;
11355 assert((argOpers[valArgIndx]->isReg() ||
11356 argOpers[valArgIndx]->isImm()) &&
11357 "invalid operand");
11358 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11359 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11360 if (argOpers[valArgIndx]->isReg())
11361 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11363 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11364 if (regOpcL != X86::MOV32rr)
11366 (*MIB).addOperand(*argOpers[valArgIndx]);
11367 assert(argOpers[valArgIndx + 1]->isReg() ==
11368 argOpers[valArgIndx]->isReg());
11369 assert(argOpers[valArgIndx + 1]->isImm() ==
11370 argOpers[valArgIndx]->isImm());
11371 if (argOpers[valArgIndx + 1]->isReg())
11372 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11374 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11375 if (regOpcH != X86::MOV32rr)
11377 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11379 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11381 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11384 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11386 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11389 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11390 for (int i=0; i <= lastAddrIndx; ++i)
11391 (*MIB).addOperand(*argOpers[i]);
11393 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11394 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11395 bInstr->memoperands_end());
11397 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11398 MIB.addReg(X86::EAX);
11399 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11400 MIB.addReg(X86::EDX);
11403 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11405 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11409 // private utility function
11410 MachineBasicBlock *
11411 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11412 MachineBasicBlock *MBB,
11413 unsigned cmovOpc) const {
11414 // For the atomic min/max operator, we generate
11417 // ld t1 = [min/max.addr]
11418 // mov t2 = [min/max.val]
11420 // cmov[cond] t2 = t1
11422 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11424 // fallthrough -->nextMBB
11426 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11427 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11428 MachineFunction::iterator MBBIter = MBB;
11431 /// First build the CFG
11432 MachineFunction *F = MBB->getParent();
11433 MachineBasicBlock *thisMBB = MBB;
11434 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11435 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11436 F->insert(MBBIter, newMBB);
11437 F->insert(MBBIter, nextMBB);
11439 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11440 nextMBB->splice(nextMBB->begin(), thisMBB,
11441 llvm::next(MachineBasicBlock::iterator(mInstr)),
11443 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11445 // Update thisMBB to fall through to newMBB
11446 thisMBB->addSuccessor(newMBB);
11448 // newMBB jumps to newMBB and fall through to nextMBB
11449 newMBB->addSuccessor(nextMBB);
11450 newMBB->addSuccessor(newMBB);
11452 DebugLoc dl = mInstr->getDebugLoc();
11453 // Insert instructions into newMBB based on incoming instruction
11454 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11455 "unexpected number of operands");
11456 MachineOperand& destOper = mInstr->getOperand(0);
11457 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11458 int numArgs = mInstr->getNumOperands() - 1;
11459 for (int i=0; i < numArgs; ++i)
11460 argOpers[i] = &mInstr->getOperand(i+1);
11462 // x86 address has 4 operands: base, index, scale, and displacement
11463 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11464 int valArgIndx = lastAddrIndx + 1;
11466 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11467 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11468 for (int i=0; i <= lastAddrIndx; ++i)
11469 (*MIB).addOperand(*argOpers[i]);
11471 // We only support register and immediate values
11472 assert((argOpers[valArgIndx]->isReg() ||
11473 argOpers[valArgIndx]->isImm()) &&
11474 "invalid operand");
11476 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11477 if (argOpers[valArgIndx]->isReg())
11478 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11480 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11481 (*MIB).addOperand(*argOpers[valArgIndx]);
11483 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11486 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11491 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11492 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11496 // Cmp and exchange if none has modified the memory location
11497 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11498 for (int i=0; i <= lastAddrIndx; ++i)
11499 (*MIB).addOperand(*argOpers[i]);
11501 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11502 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11503 mInstr->memoperands_end());
11505 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11506 MIB.addReg(X86::EAX);
11509 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11511 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11515 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11516 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11517 // in the .td file.
11518 MachineBasicBlock *
11519 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11520 unsigned numArgs, bool memArg) const {
11521 assert(Subtarget->hasSSE42orAVX() &&
11522 "Target must have SSE4.2 or AVX features enabled");
11524 DebugLoc dl = MI->getDebugLoc();
11525 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11527 if (!Subtarget->hasAVX()) {
11529 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11531 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11534 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11536 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11539 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11540 for (unsigned i = 0; i < numArgs; ++i) {
11541 MachineOperand &Op = MI->getOperand(i+1);
11542 if (!(Op.isReg() && Op.isImplicit()))
11543 MIB.addOperand(Op);
11545 BuildMI(*BB, MI, dl,
11546 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11547 MI->getOperand(0).getReg())
11548 .addReg(X86::XMM0);
11550 MI->eraseFromParent();
11554 MachineBasicBlock *
11555 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11556 DebugLoc dl = MI->getDebugLoc();
11557 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11559 // Address into RAX/EAX, other two args into ECX, EDX.
11560 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11561 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11562 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11563 for (int i = 0; i < X86::AddrNumOperands; ++i)
11564 MIB.addOperand(MI->getOperand(i));
11566 unsigned ValOps = X86::AddrNumOperands;
11567 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11568 .addReg(MI->getOperand(ValOps).getReg());
11569 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11570 .addReg(MI->getOperand(ValOps+1).getReg());
11572 // The instruction doesn't actually take any operands though.
11573 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11575 MI->eraseFromParent(); // The pseudo is gone now.
11579 MachineBasicBlock *
11580 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11581 DebugLoc dl = MI->getDebugLoc();
11582 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11584 // First arg in ECX, the second in EAX.
11585 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11586 .addReg(MI->getOperand(0).getReg());
11587 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11588 .addReg(MI->getOperand(1).getReg());
11590 // The instruction doesn't actually take any operands though.
11591 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11593 MI->eraseFromParent(); // The pseudo is gone now.
11597 MachineBasicBlock *
11598 X86TargetLowering::EmitVAARG64WithCustomInserter(
11600 MachineBasicBlock *MBB) const {
11601 // Emit va_arg instruction on X86-64.
11603 // Operands to this pseudo-instruction:
11604 // 0 ) Output : destination address (reg)
11605 // 1-5) Input : va_list address (addr, i64mem)
11606 // 6 ) ArgSize : Size (in bytes) of vararg type
11607 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11608 // 8 ) Align : Alignment of type
11609 // 9 ) EFLAGS (implicit-def)
11611 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11612 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11614 unsigned DestReg = MI->getOperand(0).getReg();
11615 MachineOperand &Base = MI->getOperand(1);
11616 MachineOperand &Scale = MI->getOperand(2);
11617 MachineOperand &Index = MI->getOperand(3);
11618 MachineOperand &Disp = MI->getOperand(4);
11619 MachineOperand &Segment = MI->getOperand(5);
11620 unsigned ArgSize = MI->getOperand(6).getImm();
11621 unsigned ArgMode = MI->getOperand(7).getImm();
11622 unsigned Align = MI->getOperand(8).getImm();
11624 // Memory Reference
11625 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11626 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11627 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11629 // Machine Information
11630 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11631 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11632 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11633 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11634 DebugLoc DL = MI->getDebugLoc();
11636 // struct va_list {
11639 // i64 overflow_area (address)
11640 // i64 reg_save_area (address)
11642 // sizeof(va_list) = 24
11643 // alignment(va_list) = 8
11645 unsigned TotalNumIntRegs = 6;
11646 unsigned TotalNumXMMRegs = 8;
11647 bool UseGPOffset = (ArgMode == 1);
11648 bool UseFPOffset = (ArgMode == 2);
11649 unsigned MaxOffset = TotalNumIntRegs * 8 +
11650 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11652 /* Align ArgSize to a multiple of 8 */
11653 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11654 bool NeedsAlign = (Align > 8);
11656 MachineBasicBlock *thisMBB = MBB;
11657 MachineBasicBlock *overflowMBB;
11658 MachineBasicBlock *offsetMBB;
11659 MachineBasicBlock *endMBB;
11661 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11662 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11663 unsigned OffsetReg = 0;
11665 if (!UseGPOffset && !UseFPOffset) {
11666 // If we only pull from the overflow region, we don't create a branch.
11667 // We don't need to alter control flow.
11668 OffsetDestReg = 0; // unused
11669 OverflowDestReg = DestReg;
11672 overflowMBB = thisMBB;
11675 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11676 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11677 // If not, pull from overflow_area. (branch to overflowMBB)
11682 // offsetMBB overflowMBB
11687 // Registers for the PHI in endMBB
11688 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11689 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11691 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11692 MachineFunction *MF = MBB->getParent();
11693 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11694 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11695 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11697 MachineFunction::iterator MBBIter = MBB;
11700 // Insert the new basic blocks
11701 MF->insert(MBBIter, offsetMBB);
11702 MF->insert(MBBIter, overflowMBB);
11703 MF->insert(MBBIter, endMBB);
11705 // Transfer the remainder of MBB and its successor edges to endMBB.
11706 endMBB->splice(endMBB->begin(), thisMBB,
11707 llvm::next(MachineBasicBlock::iterator(MI)),
11709 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11711 // Make offsetMBB and overflowMBB successors of thisMBB
11712 thisMBB->addSuccessor(offsetMBB);
11713 thisMBB->addSuccessor(overflowMBB);
11715 // endMBB is a successor of both offsetMBB and overflowMBB
11716 offsetMBB->addSuccessor(endMBB);
11717 overflowMBB->addSuccessor(endMBB);
11719 // Load the offset value into a register
11720 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11721 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11725 .addDisp(Disp, UseFPOffset ? 4 : 0)
11726 .addOperand(Segment)
11727 .setMemRefs(MMOBegin, MMOEnd);
11729 // Check if there is enough room left to pull this argument.
11730 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11732 .addImm(MaxOffset + 8 - ArgSizeA8);
11734 // Branch to "overflowMBB" if offset >= max
11735 // Fall through to "offsetMBB" otherwise
11736 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11737 .addMBB(overflowMBB);
11740 // In offsetMBB, emit code to use the reg_save_area.
11742 assert(OffsetReg != 0);
11744 // Read the reg_save_area address.
11745 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11746 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11751 .addOperand(Segment)
11752 .setMemRefs(MMOBegin, MMOEnd);
11754 // Zero-extend the offset
11755 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11756 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11759 .addImm(X86::sub_32bit);
11761 // Add the offset to the reg_save_area to get the final address.
11762 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11763 .addReg(OffsetReg64)
11764 .addReg(RegSaveReg);
11766 // Compute the offset for the next argument
11767 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11768 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11770 .addImm(UseFPOffset ? 16 : 8);
11772 // Store it back into the va_list.
11773 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11777 .addDisp(Disp, UseFPOffset ? 4 : 0)
11778 .addOperand(Segment)
11779 .addReg(NextOffsetReg)
11780 .setMemRefs(MMOBegin, MMOEnd);
11783 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11788 // Emit code to use overflow area
11791 // Load the overflow_area address into a register.
11792 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11793 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11798 .addOperand(Segment)
11799 .setMemRefs(MMOBegin, MMOEnd);
11801 // If we need to align it, do so. Otherwise, just copy the address
11802 // to OverflowDestReg.
11804 // Align the overflow address
11805 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11806 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11808 // aligned_addr = (addr + (align-1)) & ~(align-1)
11809 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11810 .addReg(OverflowAddrReg)
11813 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11815 .addImm(~(uint64_t)(Align-1));
11817 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11818 .addReg(OverflowAddrReg);
11821 // Compute the next overflow address after this argument.
11822 // (the overflow address should be kept 8-byte aligned)
11823 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11824 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11825 .addReg(OverflowDestReg)
11826 .addImm(ArgSizeA8);
11828 // Store the new overflow address.
11829 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11834 .addOperand(Segment)
11835 .addReg(NextAddrReg)
11836 .setMemRefs(MMOBegin, MMOEnd);
11838 // If we branched, emit the PHI to the front of endMBB.
11840 BuildMI(*endMBB, endMBB->begin(), DL,
11841 TII->get(X86::PHI), DestReg)
11842 .addReg(OffsetDestReg).addMBB(offsetMBB)
11843 .addReg(OverflowDestReg).addMBB(overflowMBB);
11846 // Erase the pseudo instruction
11847 MI->eraseFromParent();
11852 MachineBasicBlock *
11853 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11855 MachineBasicBlock *MBB) const {
11856 // Emit code to save XMM registers to the stack. The ABI says that the
11857 // number of registers to save is given in %al, so it's theoretically
11858 // possible to do an indirect jump trick to avoid saving all of them,
11859 // however this code takes a simpler approach and just executes all
11860 // of the stores if %al is non-zero. It's less code, and it's probably
11861 // easier on the hardware branch predictor, and stores aren't all that
11862 // expensive anyway.
11864 // Create the new basic blocks. One block contains all the XMM stores,
11865 // and one block is the final destination regardless of whether any
11866 // stores were performed.
11867 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11868 MachineFunction *F = MBB->getParent();
11869 MachineFunction::iterator MBBIter = MBB;
11871 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11872 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11873 F->insert(MBBIter, XMMSaveMBB);
11874 F->insert(MBBIter, EndMBB);
11876 // Transfer the remainder of MBB and its successor edges to EndMBB.
11877 EndMBB->splice(EndMBB->begin(), MBB,
11878 llvm::next(MachineBasicBlock::iterator(MI)),
11880 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11882 // The original block will now fall through to the XMM save block.
11883 MBB->addSuccessor(XMMSaveMBB);
11884 // The XMMSaveMBB will fall through to the end block.
11885 XMMSaveMBB->addSuccessor(EndMBB);
11887 // Now add the instructions.
11888 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11889 DebugLoc DL = MI->getDebugLoc();
11891 unsigned CountReg = MI->getOperand(0).getReg();
11892 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11893 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11895 if (!Subtarget->isTargetWin64()) {
11896 // If %al is 0, branch around the XMM save block.
11897 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11898 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11899 MBB->addSuccessor(EndMBB);
11902 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11903 // In the XMM save block, save all the XMM argument registers.
11904 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11905 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11906 MachineMemOperand *MMO =
11907 F->getMachineMemOperand(
11908 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11909 MachineMemOperand::MOStore,
11910 /*Size=*/16, /*Align=*/16);
11911 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11912 .addFrameIndex(RegSaveFrameIndex)
11913 .addImm(/*Scale=*/1)
11914 .addReg(/*IndexReg=*/0)
11915 .addImm(/*Disp=*/Offset)
11916 .addReg(/*Segment=*/0)
11917 .addReg(MI->getOperand(i).getReg())
11918 .addMemOperand(MMO);
11921 MI->eraseFromParent(); // The pseudo instruction is gone now.
11926 MachineBasicBlock *
11927 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11928 MachineBasicBlock *BB) const {
11929 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11930 DebugLoc DL = MI->getDebugLoc();
11932 // To "insert" a SELECT_CC instruction, we actually have to insert the
11933 // diamond control-flow pattern. The incoming instruction knows the
11934 // destination vreg to set, the condition code register to branch on, the
11935 // true/false values to select between, and a branch opcode to use.
11936 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11937 MachineFunction::iterator It = BB;
11943 // cmpTY ccX, r1, r2
11945 // fallthrough --> copy0MBB
11946 MachineBasicBlock *thisMBB = BB;
11947 MachineFunction *F = BB->getParent();
11948 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11949 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11950 F->insert(It, copy0MBB);
11951 F->insert(It, sinkMBB);
11953 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11954 // live into the sink and copy blocks.
11955 if (!MI->killsRegister(X86::EFLAGS)) {
11956 copy0MBB->addLiveIn(X86::EFLAGS);
11957 sinkMBB->addLiveIn(X86::EFLAGS);
11960 // Transfer the remainder of BB and its successor edges to sinkMBB.
11961 sinkMBB->splice(sinkMBB->begin(), BB,
11962 llvm::next(MachineBasicBlock::iterator(MI)),
11964 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11966 // Add the true and fallthrough blocks as its successors.
11967 BB->addSuccessor(copy0MBB);
11968 BB->addSuccessor(sinkMBB);
11970 // Create the conditional branch instruction.
11972 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11973 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11976 // %FalseValue = ...
11977 // # fallthrough to sinkMBB
11978 copy0MBB->addSuccessor(sinkMBB);
11981 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11983 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11984 TII->get(X86::PHI), MI->getOperand(0).getReg())
11985 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11986 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11988 MI->eraseFromParent(); // The pseudo instruction is gone now.
11992 MachineBasicBlock *
11993 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11994 bool Is64Bit) const {
11995 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11996 DebugLoc DL = MI->getDebugLoc();
11997 MachineFunction *MF = BB->getParent();
11998 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12000 assert(getTargetMachine().Options.EnableSegmentedStacks);
12002 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12003 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12006 // ... [Till the alloca]
12007 // If stacklet is not large enough, jump to mallocMBB
12010 // Allocate by subtracting from RSP
12011 // Jump to continueMBB
12014 // Allocate by call to runtime
12018 // [rest of original BB]
12021 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12022 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12023 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12025 MachineRegisterInfo &MRI = MF->getRegInfo();
12026 const TargetRegisterClass *AddrRegClass =
12027 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12029 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12030 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12031 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12032 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12033 sizeVReg = MI->getOperand(1).getReg(),
12034 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12036 MachineFunction::iterator MBBIter = BB;
12039 MF->insert(MBBIter, bumpMBB);
12040 MF->insert(MBBIter, mallocMBB);
12041 MF->insert(MBBIter, continueMBB);
12043 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12044 (MachineBasicBlock::iterator(MI)), BB->end());
12045 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12047 // Add code to the main basic block to check if the stack limit has been hit,
12048 // and if so, jump to mallocMBB otherwise to bumpMBB.
12049 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12050 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12051 .addReg(tmpSPVReg).addReg(sizeVReg);
12052 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12053 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12054 .addReg(SPLimitVReg);
12055 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12057 // bumpMBB simply decreases the stack pointer, since we know the current
12058 // stacklet has enough space.
12059 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12060 .addReg(SPLimitVReg);
12061 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12062 .addReg(SPLimitVReg);
12063 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12065 // Calls into a routine in libgcc to allocate more space from the heap.
12067 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12069 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12070 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12072 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12074 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12075 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12076 .addExternalSymbol("__morestack_allocate_stack_space");
12080 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12083 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12084 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12085 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12087 // Set up the CFG correctly.
12088 BB->addSuccessor(bumpMBB);
12089 BB->addSuccessor(mallocMBB);
12090 mallocMBB->addSuccessor(continueMBB);
12091 bumpMBB->addSuccessor(continueMBB);
12093 // Take care of the PHI nodes.
12094 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12095 MI->getOperand(0).getReg())
12096 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12097 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12099 // Delete the original pseudo instruction.
12100 MI->eraseFromParent();
12103 return continueMBB;
12106 MachineBasicBlock *
12107 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12108 MachineBasicBlock *BB) const {
12109 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12110 DebugLoc DL = MI->getDebugLoc();
12112 assert(!Subtarget->isTargetEnvMacho());
12114 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12115 // non-trivial part is impdef of ESP.
12117 if (Subtarget->isTargetWin64()) {
12118 if (Subtarget->isTargetCygMing()) {
12119 // ___chkstk(Mingw64):
12120 // Clobbers R10, R11, RAX and EFLAGS.
12122 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12123 .addExternalSymbol("___chkstk")
12124 .addReg(X86::RAX, RegState::Implicit)
12125 .addReg(X86::RSP, RegState::Implicit)
12126 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12127 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12128 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12130 // __chkstk(MSVCRT): does not update stack pointer.
12131 // Clobbers R10, R11 and EFLAGS.
12132 // FIXME: RAX(allocated size) might be reused and not killed.
12133 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12134 .addExternalSymbol("__chkstk")
12135 .addReg(X86::RAX, RegState::Implicit)
12136 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12137 // RAX has the offset to subtracted from RSP.
12138 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12143 const char *StackProbeSymbol =
12144 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12146 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12147 .addExternalSymbol(StackProbeSymbol)
12148 .addReg(X86::EAX, RegState::Implicit)
12149 .addReg(X86::ESP, RegState::Implicit)
12150 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12151 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12152 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12155 MI->eraseFromParent(); // The pseudo instruction is gone now.
12159 MachineBasicBlock *
12160 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12161 MachineBasicBlock *BB) const {
12162 // This is pretty easy. We're taking the value that we received from
12163 // our load from the relocation, sticking it in either RDI (x86-64)
12164 // or EAX and doing an indirect call. The return value will then
12165 // be in the normal return register.
12166 const X86InstrInfo *TII
12167 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12168 DebugLoc DL = MI->getDebugLoc();
12169 MachineFunction *F = BB->getParent();
12171 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12172 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12174 if (Subtarget->is64Bit()) {
12175 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12176 TII->get(X86::MOV64rm), X86::RDI)
12178 .addImm(0).addReg(0)
12179 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12180 MI->getOperand(3).getTargetFlags())
12182 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12183 addDirectMem(MIB, X86::RDI);
12184 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12185 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12186 TII->get(X86::MOV32rm), X86::EAX)
12188 .addImm(0).addReg(0)
12189 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12190 MI->getOperand(3).getTargetFlags())
12192 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12193 addDirectMem(MIB, X86::EAX);
12195 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12196 TII->get(X86::MOV32rm), X86::EAX)
12197 .addReg(TII->getGlobalBaseReg(F))
12198 .addImm(0).addReg(0)
12199 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12200 MI->getOperand(3).getTargetFlags())
12202 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12203 addDirectMem(MIB, X86::EAX);
12206 MI->eraseFromParent(); // The pseudo instruction is gone now.
12210 MachineBasicBlock *
12211 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12212 MachineBasicBlock *BB) const {
12213 switch (MI->getOpcode()) {
12214 default: assert(0 && "Unexpected instr type to insert");
12215 case X86::TAILJMPd64:
12216 case X86::TAILJMPr64:
12217 case X86::TAILJMPm64:
12218 assert(0 && "TAILJMP64 would not be touched here.");
12219 case X86::TCRETURNdi64:
12220 case X86::TCRETURNri64:
12221 case X86::TCRETURNmi64:
12222 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12223 // On AMD64, additional defs should be added before register allocation.
12224 if (!Subtarget->isTargetWin64()) {
12225 MI->addRegisterDefined(X86::RSI);
12226 MI->addRegisterDefined(X86::RDI);
12227 MI->addRegisterDefined(X86::XMM6);
12228 MI->addRegisterDefined(X86::XMM7);
12229 MI->addRegisterDefined(X86::XMM8);
12230 MI->addRegisterDefined(X86::XMM9);
12231 MI->addRegisterDefined(X86::XMM10);
12232 MI->addRegisterDefined(X86::XMM11);
12233 MI->addRegisterDefined(X86::XMM12);
12234 MI->addRegisterDefined(X86::XMM13);
12235 MI->addRegisterDefined(X86::XMM14);
12236 MI->addRegisterDefined(X86::XMM15);
12239 case X86::WIN_ALLOCA:
12240 return EmitLoweredWinAlloca(MI, BB);
12241 case X86::SEG_ALLOCA_32:
12242 return EmitLoweredSegAlloca(MI, BB, false);
12243 case X86::SEG_ALLOCA_64:
12244 return EmitLoweredSegAlloca(MI, BB, true);
12245 case X86::TLSCall_32:
12246 case X86::TLSCall_64:
12247 return EmitLoweredTLSCall(MI, BB);
12248 case X86::CMOV_GR8:
12249 case X86::CMOV_FR32:
12250 case X86::CMOV_FR64:
12251 case X86::CMOV_V4F32:
12252 case X86::CMOV_V2F64:
12253 case X86::CMOV_V2I64:
12254 case X86::CMOV_V8F32:
12255 case X86::CMOV_V4F64:
12256 case X86::CMOV_V4I64:
12257 case X86::CMOV_GR16:
12258 case X86::CMOV_GR32:
12259 case X86::CMOV_RFP32:
12260 case X86::CMOV_RFP64:
12261 case X86::CMOV_RFP80:
12262 return EmitLoweredSelect(MI, BB);
12264 case X86::FP32_TO_INT16_IN_MEM:
12265 case X86::FP32_TO_INT32_IN_MEM:
12266 case X86::FP32_TO_INT64_IN_MEM:
12267 case X86::FP64_TO_INT16_IN_MEM:
12268 case X86::FP64_TO_INT32_IN_MEM:
12269 case X86::FP64_TO_INT64_IN_MEM:
12270 case X86::FP80_TO_INT16_IN_MEM:
12271 case X86::FP80_TO_INT32_IN_MEM:
12272 case X86::FP80_TO_INT64_IN_MEM: {
12273 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12274 DebugLoc DL = MI->getDebugLoc();
12276 // Change the floating point control register to use "round towards zero"
12277 // mode when truncating to an integer value.
12278 MachineFunction *F = BB->getParent();
12279 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12280 addFrameReference(BuildMI(*BB, MI, DL,
12281 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12283 // Load the old value of the high byte of the control word...
12285 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12286 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12289 // Set the high part to be round to zero...
12290 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12293 // Reload the modified control word now...
12294 addFrameReference(BuildMI(*BB, MI, DL,
12295 TII->get(X86::FLDCW16m)), CWFrameIdx);
12297 // Restore the memory image of control word to original value
12298 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12301 // Get the X86 opcode to use.
12303 switch (MI->getOpcode()) {
12304 default: llvm_unreachable("illegal opcode!");
12305 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12306 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12307 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12308 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12309 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12310 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12311 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12312 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12313 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12317 MachineOperand &Op = MI->getOperand(0);
12319 AM.BaseType = X86AddressMode::RegBase;
12320 AM.Base.Reg = Op.getReg();
12322 AM.BaseType = X86AddressMode::FrameIndexBase;
12323 AM.Base.FrameIndex = Op.getIndex();
12325 Op = MI->getOperand(1);
12327 AM.Scale = Op.getImm();
12328 Op = MI->getOperand(2);
12330 AM.IndexReg = Op.getImm();
12331 Op = MI->getOperand(3);
12332 if (Op.isGlobal()) {
12333 AM.GV = Op.getGlobal();
12335 AM.Disp = Op.getImm();
12337 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12338 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12340 // Reload the original control word now.
12341 addFrameReference(BuildMI(*BB, MI, DL,
12342 TII->get(X86::FLDCW16m)), CWFrameIdx);
12344 MI->eraseFromParent(); // The pseudo instruction is gone now.
12347 // String/text processing lowering.
12348 case X86::PCMPISTRM128REG:
12349 case X86::VPCMPISTRM128REG:
12350 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12351 case X86::PCMPISTRM128MEM:
12352 case X86::VPCMPISTRM128MEM:
12353 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12354 case X86::PCMPESTRM128REG:
12355 case X86::VPCMPESTRM128REG:
12356 return EmitPCMP(MI, BB, 5, false /* in mem */);
12357 case X86::PCMPESTRM128MEM:
12358 case X86::VPCMPESTRM128MEM:
12359 return EmitPCMP(MI, BB, 5, true /* in mem */);
12361 // Thread synchronization.
12363 return EmitMonitor(MI, BB);
12365 return EmitMwait(MI, BB);
12367 // Atomic Lowering.
12368 case X86::ATOMAND32:
12369 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12370 X86::AND32ri, X86::MOV32rm,
12372 X86::NOT32r, X86::EAX,
12373 X86::GR32RegisterClass);
12374 case X86::ATOMOR32:
12375 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12376 X86::OR32ri, X86::MOV32rm,
12378 X86::NOT32r, X86::EAX,
12379 X86::GR32RegisterClass);
12380 case X86::ATOMXOR32:
12381 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12382 X86::XOR32ri, X86::MOV32rm,
12384 X86::NOT32r, X86::EAX,
12385 X86::GR32RegisterClass);
12386 case X86::ATOMNAND32:
12387 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12388 X86::AND32ri, X86::MOV32rm,
12390 X86::NOT32r, X86::EAX,
12391 X86::GR32RegisterClass, true);
12392 case X86::ATOMMIN32:
12393 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12394 case X86::ATOMMAX32:
12395 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12396 case X86::ATOMUMIN32:
12397 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12398 case X86::ATOMUMAX32:
12399 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12401 case X86::ATOMAND16:
12402 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12403 X86::AND16ri, X86::MOV16rm,
12405 X86::NOT16r, X86::AX,
12406 X86::GR16RegisterClass);
12407 case X86::ATOMOR16:
12408 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12409 X86::OR16ri, X86::MOV16rm,
12411 X86::NOT16r, X86::AX,
12412 X86::GR16RegisterClass);
12413 case X86::ATOMXOR16:
12414 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12415 X86::XOR16ri, X86::MOV16rm,
12417 X86::NOT16r, X86::AX,
12418 X86::GR16RegisterClass);
12419 case X86::ATOMNAND16:
12420 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12421 X86::AND16ri, X86::MOV16rm,
12423 X86::NOT16r, X86::AX,
12424 X86::GR16RegisterClass, true);
12425 case X86::ATOMMIN16:
12426 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12427 case X86::ATOMMAX16:
12428 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12429 case X86::ATOMUMIN16:
12430 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12431 case X86::ATOMUMAX16:
12432 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12434 case X86::ATOMAND8:
12435 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12436 X86::AND8ri, X86::MOV8rm,
12438 X86::NOT8r, X86::AL,
12439 X86::GR8RegisterClass);
12441 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12442 X86::OR8ri, X86::MOV8rm,
12444 X86::NOT8r, X86::AL,
12445 X86::GR8RegisterClass);
12446 case X86::ATOMXOR8:
12447 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12448 X86::XOR8ri, X86::MOV8rm,
12450 X86::NOT8r, X86::AL,
12451 X86::GR8RegisterClass);
12452 case X86::ATOMNAND8:
12453 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12454 X86::AND8ri, X86::MOV8rm,
12456 X86::NOT8r, X86::AL,
12457 X86::GR8RegisterClass, true);
12458 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12459 // This group is for 64-bit host.
12460 case X86::ATOMAND64:
12461 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12462 X86::AND64ri32, X86::MOV64rm,
12464 X86::NOT64r, X86::RAX,
12465 X86::GR64RegisterClass);
12466 case X86::ATOMOR64:
12467 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12468 X86::OR64ri32, X86::MOV64rm,
12470 X86::NOT64r, X86::RAX,
12471 X86::GR64RegisterClass);
12472 case X86::ATOMXOR64:
12473 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12474 X86::XOR64ri32, X86::MOV64rm,
12476 X86::NOT64r, X86::RAX,
12477 X86::GR64RegisterClass);
12478 case X86::ATOMNAND64:
12479 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12480 X86::AND64ri32, X86::MOV64rm,
12482 X86::NOT64r, X86::RAX,
12483 X86::GR64RegisterClass, true);
12484 case X86::ATOMMIN64:
12485 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12486 case X86::ATOMMAX64:
12487 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12488 case X86::ATOMUMIN64:
12489 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12490 case X86::ATOMUMAX64:
12491 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12493 // This group does 64-bit operations on a 32-bit host.
12494 case X86::ATOMAND6432:
12495 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12496 X86::AND32rr, X86::AND32rr,
12497 X86::AND32ri, X86::AND32ri,
12499 case X86::ATOMOR6432:
12500 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12501 X86::OR32rr, X86::OR32rr,
12502 X86::OR32ri, X86::OR32ri,
12504 case X86::ATOMXOR6432:
12505 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12506 X86::XOR32rr, X86::XOR32rr,
12507 X86::XOR32ri, X86::XOR32ri,
12509 case X86::ATOMNAND6432:
12510 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12511 X86::AND32rr, X86::AND32rr,
12512 X86::AND32ri, X86::AND32ri,
12514 case X86::ATOMADD6432:
12515 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12516 X86::ADD32rr, X86::ADC32rr,
12517 X86::ADD32ri, X86::ADC32ri,
12519 case X86::ATOMSUB6432:
12520 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12521 X86::SUB32rr, X86::SBB32rr,
12522 X86::SUB32ri, X86::SBB32ri,
12524 case X86::ATOMSWAP6432:
12525 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12526 X86::MOV32rr, X86::MOV32rr,
12527 X86::MOV32ri, X86::MOV32ri,
12529 case X86::VASTART_SAVE_XMM_REGS:
12530 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12532 case X86::VAARG_64:
12533 return EmitVAARG64WithCustomInserter(MI, BB);
12537 //===----------------------------------------------------------------------===//
12538 // X86 Optimization Hooks
12539 //===----------------------------------------------------------------------===//
12541 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12545 const SelectionDAG &DAG,
12546 unsigned Depth) const {
12547 unsigned Opc = Op.getOpcode();
12548 assert((Opc >= ISD::BUILTIN_OP_END ||
12549 Opc == ISD::INTRINSIC_WO_CHAIN ||
12550 Opc == ISD::INTRINSIC_W_CHAIN ||
12551 Opc == ISD::INTRINSIC_VOID) &&
12552 "Should use MaskedValueIsZero if you don't know whether Op"
12553 " is a target node!");
12555 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12569 // These nodes' second result is a boolean.
12570 if (Op.getResNo() == 0)
12573 case X86ISD::SETCC:
12574 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12575 Mask.getBitWidth() - 1);
12577 case ISD::INTRINSIC_WO_CHAIN: {
12578 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12579 unsigned NumLoBits = 0;
12582 case Intrinsic::x86_sse_movmsk_ps:
12583 case Intrinsic::x86_avx_movmsk_ps_256:
12584 case Intrinsic::x86_sse2_movmsk_pd:
12585 case Intrinsic::x86_avx_movmsk_pd_256:
12586 case Intrinsic::x86_mmx_pmovmskb:
12587 case Intrinsic::x86_sse2_pmovmskb_128: {
12588 // High bits of movmskp{s|d}, pmovmskb are known zero.
12590 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12591 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12592 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12593 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12594 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12595 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12597 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12598 Mask.getBitWidth() - NumLoBits);
12607 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12608 unsigned Depth) const {
12609 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12610 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12611 return Op.getValueType().getScalarType().getSizeInBits();
12617 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12618 /// node is a GlobalAddress + offset.
12619 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12620 const GlobalValue* &GA,
12621 int64_t &Offset) const {
12622 if (N->getOpcode() == X86ISD::Wrapper) {
12623 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12624 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12625 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12629 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12632 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12633 /// same as extracting the high 128-bit part of 256-bit vector and then
12634 /// inserting the result into the low part of a new 256-bit vector
12635 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12636 EVT VT = SVOp->getValueType(0);
12637 int NumElems = VT.getVectorNumElements();
12639 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12640 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12641 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12642 SVOp->getMaskElt(j) >= 0)
12648 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12649 /// same as extracting the low 128-bit part of 256-bit vector and then
12650 /// inserting the result into the high part of a new 256-bit vector
12651 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12652 EVT VT = SVOp->getValueType(0);
12653 int NumElems = VT.getVectorNumElements();
12655 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12656 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12657 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12658 SVOp->getMaskElt(j) >= 0)
12664 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12665 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12666 TargetLowering::DAGCombinerInfo &DCI) {
12667 DebugLoc dl = N->getDebugLoc();
12668 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12669 SDValue V1 = SVOp->getOperand(0);
12670 SDValue V2 = SVOp->getOperand(1);
12671 EVT VT = SVOp->getValueType(0);
12672 int NumElems = VT.getVectorNumElements();
12674 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12675 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12679 // V UNDEF BUILD_VECTOR UNDEF
12681 // CONCAT_VECTOR CONCAT_VECTOR
12684 // RESULT: V + zero extended
12686 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12687 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12688 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12691 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12694 // To match the shuffle mask, the first half of the mask should
12695 // be exactly the first vector, and all the rest a splat with the
12696 // first element of the second one.
12697 for (int i = 0; i < NumElems/2; ++i)
12698 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12699 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12702 // Emit a zeroed vector and insert the desired subvector on its
12704 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
12705 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12706 DAG.getConstant(0, MVT::i32), DAG, dl);
12707 return DCI.CombineTo(N, InsV);
12710 //===--------------------------------------------------------------------===//
12711 // Combine some shuffles into subvector extracts and inserts:
12714 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12715 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12716 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12718 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12719 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12720 return DCI.CombineTo(N, InsV);
12723 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12724 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12725 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12726 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12727 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12728 return DCI.CombineTo(N, InsV);
12734 /// PerformShuffleCombine - Performs several different shuffle combines.
12735 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12736 TargetLowering::DAGCombinerInfo &DCI,
12737 const X86Subtarget *Subtarget) {
12738 DebugLoc dl = N->getDebugLoc();
12739 EVT VT = N->getValueType(0);
12741 // Don't create instructions with illegal types after legalize types has run.
12742 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12743 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12746 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12747 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12748 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12749 return PerformShuffleCombine256(N, DAG, DCI);
12751 // Only handle 128 wide vector from here on.
12752 if (VT.getSizeInBits() != 128)
12755 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12756 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12757 // consecutive, non-overlapping, and in the right order.
12758 SmallVector<SDValue, 16> Elts;
12759 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12760 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12762 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12765 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12766 /// generation and convert it from being a bunch of shuffles and extracts
12767 /// to a simple store and scalar loads to extract the elements.
12768 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12769 const TargetLowering &TLI) {
12770 SDValue InputVector = N->getOperand(0);
12772 // Only operate on vectors of 4 elements, where the alternative shuffling
12773 // gets to be more expensive.
12774 if (InputVector.getValueType() != MVT::v4i32)
12777 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12778 // single use which is a sign-extend or zero-extend, and all elements are
12780 SmallVector<SDNode *, 4> Uses;
12781 unsigned ExtractedElements = 0;
12782 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12783 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12784 if (UI.getUse().getResNo() != InputVector.getResNo())
12787 SDNode *Extract = *UI;
12788 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12791 if (Extract->getValueType(0) != MVT::i32)
12793 if (!Extract->hasOneUse())
12795 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12796 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12798 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12801 // Record which element was extracted.
12802 ExtractedElements |=
12803 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12805 Uses.push_back(Extract);
12808 // If not all the elements were used, this may not be worthwhile.
12809 if (ExtractedElements != 15)
12812 // Ok, we've now decided to do the transformation.
12813 DebugLoc dl = InputVector.getDebugLoc();
12815 // Store the value to a temporary stack slot.
12816 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12817 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12818 MachinePointerInfo(), false, false, 0);
12820 // Replace each use (extract) with a load of the appropriate element.
12821 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12822 UE = Uses.end(); UI != UE; ++UI) {
12823 SDNode *Extract = *UI;
12825 // cOMpute the element's address.
12826 SDValue Idx = Extract->getOperand(1);
12828 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12829 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12830 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12832 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12833 StackPtr, OffsetVal);
12835 // Load the scalar.
12836 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12837 ScalarAddr, MachinePointerInfo(),
12838 false, false, false, 0);
12840 // Replace the exact with the load.
12841 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12844 // The replacement was made in place; don't return anything.
12848 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12850 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12851 const X86Subtarget *Subtarget) {
12852 DebugLoc DL = N->getDebugLoc();
12853 SDValue Cond = N->getOperand(0);
12854 // Get the LHS/RHS of the select.
12855 SDValue LHS = N->getOperand(1);
12856 SDValue RHS = N->getOperand(2);
12857 EVT VT = LHS.getValueType();
12859 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12860 // instructions match the semantics of the common C idiom x<y?x:y but not
12861 // x<=y?x:y, because of how they handle negative zero (which can be
12862 // ignored in unsafe-math mode).
12863 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12864 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12865 (Subtarget->hasXMMInt() ||
12866 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12867 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12869 unsigned Opcode = 0;
12870 // Check for x CC y ? x : y.
12871 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12872 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12876 // Converting this to a min would handle NaNs incorrectly, and swapping
12877 // the operands would cause it to handle comparisons between positive
12878 // and negative zero incorrectly.
12879 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12880 if (!DAG.getTarget().Options.UnsafeFPMath &&
12881 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12883 std::swap(LHS, RHS);
12885 Opcode = X86ISD::FMIN;
12888 // Converting this to a min would handle comparisons between positive
12889 // and negative zero incorrectly.
12890 if (!DAG.getTarget().Options.UnsafeFPMath &&
12891 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12893 Opcode = X86ISD::FMIN;
12896 // Converting this to a min would handle both negative zeros and NaNs
12897 // incorrectly, but we can swap the operands to fix both.
12898 std::swap(LHS, RHS);
12902 Opcode = X86ISD::FMIN;
12906 // Converting this to a max would handle comparisons between positive
12907 // and negative zero incorrectly.
12908 if (!DAG.getTarget().Options.UnsafeFPMath &&
12909 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12911 Opcode = X86ISD::FMAX;
12914 // Converting this to a max would handle NaNs incorrectly, and swapping
12915 // the operands would cause it to handle comparisons between positive
12916 // and negative zero incorrectly.
12917 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12918 if (!DAG.getTarget().Options.UnsafeFPMath &&
12919 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12921 std::swap(LHS, RHS);
12923 Opcode = X86ISD::FMAX;
12926 // Converting this to a max would handle both negative zeros and NaNs
12927 // incorrectly, but we can swap the operands to fix both.
12928 std::swap(LHS, RHS);
12932 Opcode = X86ISD::FMAX;
12935 // Check for x CC y ? y : x -- a min/max with reversed arms.
12936 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12937 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12941 // Converting this to a min would handle comparisons between positive
12942 // and negative zero incorrectly, and swapping the operands would
12943 // cause it to handle NaNs incorrectly.
12944 if (!DAG.getTarget().Options.UnsafeFPMath &&
12945 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12946 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12948 std::swap(LHS, RHS);
12950 Opcode = X86ISD::FMIN;
12953 // Converting this to a min would handle NaNs incorrectly.
12954 if (!DAG.getTarget().Options.UnsafeFPMath &&
12955 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12957 Opcode = X86ISD::FMIN;
12960 // Converting this to a min would handle both negative zeros and NaNs
12961 // incorrectly, but we can swap the operands to fix both.
12962 std::swap(LHS, RHS);
12966 Opcode = X86ISD::FMIN;
12970 // Converting this to a max would handle NaNs incorrectly.
12971 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12973 Opcode = X86ISD::FMAX;
12976 // Converting this to a max would handle comparisons between positive
12977 // and negative zero incorrectly, and swapping the operands would
12978 // cause it to handle NaNs incorrectly.
12979 if (!DAG.getTarget().Options.UnsafeFPMath &&
12980 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12981 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12983 std::swap(LHS, RHS);
12985 Opcode = X86ISD::FMAX;
12988 // Converting this to a max would handle both negative zeros and NaNs
12989 // incorrectly, but we can swap the operands to fix both.
12990 std::swap(LHS, RHS);
12994 Opcode = X86ISD::FMAX;
13000 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13003 // If this is a select between two integer constants, try to do some
13005 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13006 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13007 // Don't do this for crazy integer types.
13008 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13009 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13010 // so that TrueC (the true value) is larger than FalseC.
13011 bool NeedsCondInvert = false;
13013 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13014 // Efficiently invertible.
13015 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13016 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13017 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13018 NeedsCondInvert = true;
13019 std::swap(TrueC, FalseC);
13022 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13023 if (FalseC->getAPIntValue() == 0 &&
13024 TrueC->getAPIntValue().isPowerOf2()) {
13025 if (NeedsCondInvert) // Invert the condition if needed.
13026 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13027 DAG.getConstant(1, Cond.getValueType()));
13029 // Zero extend the condition if needed.
13030 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13032 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13033 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13034 DAG.getConstant(ShAmt, MVT::i8));
13037 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13038 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13039 if (NeedsCondInvert) // Invert the condition if needed.
13040 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13041 DAG.getConstant(1, Cond.getValueType()));
13043 // Zero extend the condition if needed.
13044 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13045 FalseC->getValueType(0), Cond);
13046 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13047 SDValue(FalseC, 0));
13050 // Optimize cases that will turn into an LEA instruction. This requires
13051 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13052 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13053 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13054 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13056 bool isFastMultiplier = false;
13058 switch ((unsigned char)Diff) {
13060 case 1: // result = add base, cond
13061 case 2: // result = lea base( , cond*2)
13062 case 3: // result = lea base(cond, cond*2)
13063 case 4: // result = lea base( , cond*4)
13064 case 5: // result = lea base(cond, cond*4)
13065 case 8: // result = lea base( , cond*8)
13066 case 9: // result = lea base(cond, cond*8)
13067 isFastMultiplier = true;
13072 if (isFastMultiplier) {
13073 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13074 if (NeedsCondInvert) // Invert the condition if needed.
13075 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13076 DAG.getConstant(1, Cond.getValueType()));
13078 // Zero extend the condition if needed.
13079 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13081 // Scale the condition by the difference.
13083 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13084 DAG.getConstant(Diff, Cond.getValueType()));
13086 // Add the base if non-zero.
13087 if (FalseC->getAPIntValue() != 0)
13088 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13089 SDValue(FalseC, 0));
13099 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13100 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13101 TargetLowering::DAGCombinerInfo &DCI) {
13102 DebugLoc DL = N->getDebugLoc();
13104 // If the flag operand isn't dead, don't touch this CMOV.
13105 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13108 SDValue FalseOp = N->getOperand(0);
13109 SDValue TrueOp = N->getOperand(1);
13110 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13111 SDValue Cond = N->getOperand(3);
13112 if (CC == X86::COND_E || CC == X86::COND_NE) {
13113 switch (Cond.getOpcode()) {
13117 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13118 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13119 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13123 // If this is a select between two integer constants, try to do some
13124 // optimizations. Note that the operands are ordered the opposite of SELECT
13126 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13127 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13128 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13129 // larger than FalseC (the false value).
13130 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13131 CC = X86::GetOppositeBranchCondition(CC);
13132 std::swap(TrueC, FalseC);
13135 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13136 // This is efficient for any integer data type (including i8/i16) and
13138 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13139 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13140 DAG.getConstant(CC, MVT::i8), Cond);
13142 // Zero extend the condition if needed.
13143 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13145 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13146 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13147 DAG.getConstant(ShAmt, MVT::i8));
13148 if (N->getNumValues() == 2) // Dead flag value?
13149 return DCI.CombineTo(N, Cond, SDValue());
13153 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13154 // for any integer data type, including i8/i16.
13155 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13156 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13157 DAG.getConstant(CC, MVT::i8), Cond);
13159 // Zero extend the condition if needed.
13160 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13161 FalseC->getValueType(0), Cond);
13162 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13163 SDValue(FalseC, 0));
13165 if (N->getNumValues() == 2) // Dead flag value?
13166 return DCI.CombineTo(N, Cond, SDValue());
13170 // Optimize cases that will turn into an LEA instruction. This requires
13171 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13172 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13173 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13174 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13176 bool isFastMultiplier = false;
13178 switch ((unsigned char)Diff) {
13180 case 1: // result = add base, cond
13181 case 2: // result = lea base( , cond*2)
13182 case 3: // result = lea base(cond, cond*2)
13183 case 4: // result = lea base( , cond*4)
13184 case 5: // result = lea base(cond, cond*4)
13185 case 8: // result = lea base( , cond*8)
13186 case 9: // result = lea base(cond, cond*8)
13187 isFastMultiplier = true;
13192 if (isFastMultiplier) {
13193 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13194 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13195 DAG.getConstant(CC, MVT::i8), Cond);
13196 // Zero extend the condition if needed.
13197 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13199 // Scale the condition by the difference.
13201 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13202 DAG.getConstant(Diff, Cond.getValueType()));
13204 // Add the base if non-zero.
13205 if (FalseC->getAPIntValue() != 0)
13206 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13207 SDValue(FalseC, 0));
13208 if (N->getNumValues() == 2) // Dead flag value?
13209 return DCI.CombineTo(N, Cond, SDValue());
13219 /// PerformMulCombine - Optimize a single multiply with constant into two
13220 /// in order to implement it with two cheaper instructions, e.g.
13221 /// LEA + SHL, LEA + LEA.
13222 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13223 TargetLowering::DAGCombinerInfo &DCI) {
13224 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13227 EVT VT = N->getValueType(0);
13228 if (VT != MVT::i64)
13231 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13234 uint64_t MulAmt = C->getZExtValue();
13235 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13238 uint64_t MulAmt1 = 0;
13239 uint64_t MulAmt2 = 0;
13240 if ((MulAmt % 9) == 0) {
13242 MulAmt2 = MulAmt / 9;
13243 } else if ((MulAmt % 5) == 0) {
13245 MulAmt2 = MulAmt / 5;
13246 } else if ((MulAmt % 3) == 0) {
13248 MulAmt2 = MulAmt / 3;
13251 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13252 DebugLoc DL = N->getDebugLoc();
13254 if (isPowerOf2_64(MulAmt2) &&
13255 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13256 // If second multiplifer is pow2, issue it first. We want the multiply by
13257 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13259 std::swap(MulAmt1, MulAmt2);
13262 if (isPowerOf2_64(MulAmt1))
13263 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13264 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13266 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13267 DAG.getConstant(MulAmt1, VT));
13269 if (isPowerOf2_64(MulAmt2))
13270 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13271 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13273 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13274 DAG.getConstant(MulAmt2, VT));
13276 // Do not add new nodes to DAG combiner worklist.
13277 DCI.CombineTo(N, NewMul, false);
13282 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13283 SDValue N0 = N->getOperand(0);
13284 SDValue N1 = N->getOperand(1);
13285 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13286 EVT VT = N0.getValueType();
13288 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13289 // since the result of setcc_c is all zero's or all ones.
13290 if (VT.isInteger() && !VT.isVector() &&
13291 N1C && N0.getOpcode() == ISD::AND &&
13292 N0.getOperand(1).getOpcode() == ISD::Constant) {
13293 SDValue N00 = N0.getOperand(0);
13294 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13295 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13296 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13297 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13298 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13299 APInt ShAmt = N1C->getAPIntValue();
13300 Mask = Mask.shl(ShAmt);
13302 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13303 N00, DAG.getConstant(Mask, VT));
13308 // Hardware support for vector shifts is sparse which makes us scalarize the
13309 // vector operations in many cases. Also, on sandybridge ADD is faster than
13311 // (shl V, 1) -> add V,V
13312 if (isSplatVector(N1.getNode())) {
13313 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13314 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13315 // We shift all of the values by one. In many cases we do not have
13316 // hardware support for this operation. This is better expressed as an ADD
13318 if (N1C && (1 == N1C->getZExtValue())) {
13319 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13326 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13328 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13329 const X86Subtarget *Subtarget) {
13330 EVT VT = N->getValueType(0);
13331 if (N->getOpcode() == ISD::SHL) {
13332 SDValue V = PerformSHLCombine(N, DAG);
13333 if (V.getNode()) return V;
13336 // On X86 with SSE2 support, we can transform this to a vector shift if
13337 // all elements are shifted by the same amount. We can't do this in legalize
13338 // because the a constant vector is typically transformed to a constant pool
13339 // so we have no knowledge of the shift amount.
13340 if (!Subtarget->hasXMMInt())
13343 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13344 (!Subtarget->hasAVX2() ||
13345 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13348 SDValue ShAmtOp = N->getOperand(1);
13349 EVT EltVT = VT.getVectorElementType();
13350 DebugLoc DL = N->getDebugLoc();
13351 SDValue BaseShAmt = SDValue();
13352 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13353 unsigned NumElts = VT.getVectorNumElements();
13355 for (; i != NumElts; ++i) {
13356 SDValue Arg = ShAmtOp.getOperand(i);
13357 if (Arg.getOpcode() == ISD::UNDEF) continue;
13361 for (; i != NumElts; ++i) {
13362 SDValue Arg = ShAmtOp.getOperand(i);
13363 if (Arg.getOpcode() == ISD::UNDEF) continue;
13364 if (Arg != BaseShAmt) {
13368 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13369 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13370 SDValue InVec = ShAmtOp.getOperand(0);
13371 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13372 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13374 for (; i != NumElts; ++i) {
13375 SDValue Arg = InVec.getOperand(i);
13376 if (Arg.getOpcode() == ISD::UNDEF) continue;
13380 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13381 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13382 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13383 if (C->getZExtValue() == SplatIdx)
13384 BaseShAmt = InVec.getOperand(1);
13387 if (BaseShAmt.getNode() == 0)
13388 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13389 DAG.getIntPtrConstant(0));
13393 // The shift amount is an i32.
13394 if (EltVT.bitsGT(MVT::i32))
13395 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13396 else if (EltVT.bitsLT(MVT::i32))
13397 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13399 // The shift amount is identical so we can do a vector shift.
13400 SDValue ValOp = N->getOperand(0);
13401 switch (N->getOpcode()) {
13403 llvm_unreachable("Unknown shift opcode!");
13406 if (VT == MVT::v2i64)
13407 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13408 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13410 if (VT == MVT::v4i32)
13411 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13412 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13414 if (VT == MVT::v8i16)
13415 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13416 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13418 if (VT == MVT::v4i64)
13419 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13420 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
13422 if (VT == MVT::v8i32)
13423 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13424 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
13426 if (VT == MVT::v16i16)
13427 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13428 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
13432 if (VT == MVT::v4i32)
13433 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13434 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13436 if (VT == MVT::v8i16)
13437 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13438 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13440 if (VT == MVT::v8i32)
13441 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13442 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
13444 if (VT == MVT::v16i16)
13445 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13446 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
13450 if (VT == MVT::v2i64)
13451 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13452 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13454 if (VT == MVT::v4i32)
13455 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13456 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13458 if (VT == MVT::v8i16)
13459 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13460 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13462 if (VT == MVT::v4i64)
13463 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13464 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
13466 if (VT == MVT::v8i32)
13467 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13468 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
13470 if (VT == MVT::v16i16)
13471 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13472 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
13480 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13481 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13482 // and friends. Likewise for OR -> CMPNEQSS.
13483 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13484 TargetLowering::DAGCombinerInfo &DCI,
13485 const X86Subtarget *Subtarget) {
13488 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13489 // we're requiring SSE2 for both.
13490 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13491 SDValue N0 = N->getOperand(0);
13492 SDValue N1 = N->getOperand(1);
13493 SDValue CMP0 = N0->getOperand(1);
13494 SDValue CMP1 = N1->getOperand(1);
13495 DebugLoc DL = N->getDebugLoc();
13497 // The SETCCs should both refer to the same CMP.
13498 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13501 SDValue CMP00 = CMP0->getOperand(0);
13502 SDValue CMP01 = CMP0->getOperand(1);
13503 EVT VT = CMP00.getValueType();
13505 if (VT == MVT::f32 || VT == MVT::f64) {
13506 bool ExpectingFlags = false;
13507 // Check for any users that want flags:
13508 for (SDNode::use_iterator UI = N->use_begin(),
13510 !ExpectingFlags && UI != UE; ++UI)
13511 switch (UI->getOpcode()) {
13516 ExpectingFlags = true;
13518 case ISD::CopyToReg:
13519 case ISD::SIGN_EXTEND:
13520 case ISD::ZERO_EXTEND:
13521 case ISD::ANY_EXTEND:
13525 if (!ExpectingFlags) {
13526 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13527 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13529 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13530 X86::CondCode tmp = cc0;
13535 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13536 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13537 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13538 X86ISD::NodeType NTOperator = is64BitFP ?
13539 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13540 // FIXME: need symbolic constants for these magic numbers.
13541 // See X86ATTInstPrinter.cpp:printSSECC().
13542 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13543 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13544 DAG.getConstant(x86cc, MVT::i8));
13545 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13547 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13548 DAG.getConstant(1, MVT::i32));
13549 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13550 return OneBitOfTruth;
13558 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13559 /// so it can be folded inside ANDNP.
13560 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13561 EVT VT = N->getValueType(0);
13563 // Match direct AllOnes for 128 and 256-bit vectors
13564 if (ISD::isBuildVectorAllOnes(N))
13567 // Look through a bit convert.
13568 if (N->getOpcode() == ISD::BITCAST)
13569 N = N->getOperand(0).getNode();
13571 // Sometimes the operand may come from a insert_subvector building a 256-bit
13573 if (VT.getSizeInBits() == 256 &&
13574 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13575 SDValue V1 = N->getOperand(0);
13576 SDValue V2 = N->getOperand(1);
13578 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13579 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13580 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13581 ISD::isBuildVectorAllOnes(V2.getNode()))
13588 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13589 TargetLowering::DAGCombinerInfo &DCI,
13590 const X86Subtarget *Subtarget) {
13591 if (DCI.isBeforeLegalizeOps())
13594 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13598 EVT VT = N->getValueType(0);
13600 // Create ANDN, BLSI, and BLSR instructions
13601 // BLSI is X & (-X)
13602 // BLSR is X & (X-1)
13603 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13604 SDValue N0 = N->getOperand(0);
13605 SDValue N1 = N->getOperand(1);
13606 DebugLoc DL = N->getDebugLoc();
13608 // Check LHS for not
13609 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13610 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13611 // Check RHS for not
13612 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13613 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13615 // Check LHS for neg
13616 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13617 isZero(N0.getOperand(0)))
13618 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13620 // Check RHS for neg
13621 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13622 isZero(N1.getOperand(0)))
13623 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13625 // Check LHS for X-1
13626 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13627 isAllOnes(N0.getOperand(1)))
13628 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13630 // Check RHS for X-1
13631 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13632 isAllOnes(N1.getOperand(1)))
13633 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13638 // Want to form ANDNP nodes:
13639 // 1) In the hopes of then easily combining them with OR and AND nodes
13640 // to form PBLEND/PSIGN.
13641 // 2) To match ANDN packed intrinsics
13642 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13645 SDValue N0 = N->getOperand(0);
13646 SDValue N1 = N->getOperand(1);
13647 DebugLoc DL = N->getDebugLoc();
13649 // Check LHS for vnot
13650 if (N0.getOpcode() == ISD::XOR &&
13651 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13652 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13653 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13655 // Check RHS for vnot
13656 if (N1.getOpcode() == ISD::XOR &&
13657 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13658 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13659 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13664 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13665 TargetLowering::DAGCombinerInfo &DCI,
13666 const X86Subtarget *Subtarget) {
13667 if (DCI.isBeforeLegalizeOps())
13670 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13674 EVT VT = N->getValueType(0);
13676 SDValue N0 = N->getOperand(0);
13677 SDValue N1 = N->getOperand(1);
13679 // look for psign/blend
13680 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13681 if (!Subtarget->hasSSSE3orAVX() ||
13682 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13685 // Canonicalize pandn to RHS
13686 if (N0.getOpcode() == X86ISD::ANDNP)
13688 // or (and (m, x), (pandn m, y))
13689 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13690 SDValue Mask = N1.getOperand(0);
13691 SDValue X = N1.getOperand(1);
13693 if (N0.getOperand(0) == Mask)
13694 Y = N0.getOperand(1);
13695 if (N0.getOperand(1) == Mask)
13696 Y = N0.getOperand(0);
13698 // Check to see if the mask appeared in both the AND and ANDNP and
13702 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13703 if (Mask.getOpcode() != ISD::BITCAST ||
13704 X.getOpcode() != ISD::BITCAST ||
13705 Y.getOpcode() != ISD::BITCAST)
13708 // Look through mask bitcast.
13709 Mask = Mask.getOperand(0);
13710 EVT MaskVT = Mask.getValueType();
13712 // Validate that the Mask operand is a vector sra node. The sra node
13713 // will be an intrinsic.
13714 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13717 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13718 // there is no psrai.b
13719 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13720 case Intrinsic::x86_sse2_psrai_w:
13721 case Intrinsic::x86_sse2_psrai_d:
13722 case Intrinsic::x86_avx2_psrai_w:
13723 case Intrinsic::x86_avx2_psrai_d:
13725 default: return SDValue();
13728 // Check that the SRA is all signbits.
13729 SDValue SraC = Mask.getOperand(2);
13730 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13731 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13732 if ((SraAmt + 1) != EltBits)
13735 DebugLoc DL = N->getDebugLoc();
13737 // Now we know we at least have a plendvb with the mask val. See if
13738 // we can form a psignb/w/d.
13739 // psign = x.type == y.type == mask.type && y = sub(0, x);
13740 X = X.getOperand(0);
13741 Y = Y.getOperand(0);
13742 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13743 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13744 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
13745 (EltBits == 8 || EltBits == 16 || EltBits == 32)) {
13746 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
13747 Mask.getOperand(1));
13748 return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
13750 // PBLENDVB only available on SSE 4.1
13751 if (!Subtarget->hasSSE41orAVX())
13754 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13756 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13757 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13758 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13759 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13760 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13764 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13767 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13768 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13770 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13772 if (!N0.hasOneUse() || !N1.hasOneUse())
13775 SDValue ShAmt0 = N0.getOperand(1);
13776 if (ShAmt0.getValueType() != MVT::i8)
13778 SDValue ShAmt1 = N1.getOperand(1);
13779 if (ShAmt1.getValueType() != MVT::i8)
13781 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13782 ShAmt0 = ShAmt0.getOperand(0);
13783 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13784 ShAmt1 = ShAmt1.getOperand(0);
13786 DebugLoc DL = N->getDebugLoc();
13787 unsigned Opc = X86ISD::SHLD;
13788 SDValue Op0 = N0.getOperand(0);
13789 SDValue Op1 = N1.getOperand(0);
13790 if (ShAmt0.getOpcode() == ISD::SUB) {
13791 Opc = X86ISD::SHRD;
13792 std::swap(Op0, Op1);
13793 std::swap(ShAmt0, ShAmt1);
13796 unsigned Bits = VT.getSizeInBits();
13797 if (ShAmt1.getOpcode() == ISD::SUB) {
13798 SDValue Sum = ShAmt1.getOperand(0);
13799 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13800 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13801 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13802 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13803 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13804 return DAG.getNode(Opc, DL, VT,
13806 DAG.getNode(ISD::TRUNCATE, DL,
13809 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13810 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13812 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13813 return DAG.getNode(Opc, DL, VT,
13814 N0.getOperand(0), N1.getOperand(0),
13815 DAG.getNode(ISD::TRUNCATE, DL,
13822 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
13823 TargetLowering::DAGCombinerInfo &DCI,
13824 const X86Subtarget *Subtarget) {
13825 if (DCI.isBeforeLegalizeOps())
13828 EVT VT = N->getValueType(0);
13830 if (VT != MVT::i32 && VT != MVT::i64)
13833 // Create BLSMSK instructions by finding X ^ (X-1)
13834 SDValue N0 = N->getOperand(0);
13835 SDValue N1 = N->getOperand(1);
13836 DebugLoc DL = N->getDebugLoc();
13838 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13839 isAllOnes(N0.getOperand(1)))
13840 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
13842 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13843 isAllOnes(N1.getOperand(1)))
13844 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
13849 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13850 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13851 const X86Subtarget *Subtarget) {
13852 LoadSDNode *Ld = cast<LoadSDNode>(N);
13853 EVT RegVT = Ld->getValueType(0);
13854 EVT MemVT = Ld->getMemoryVT();
13855 DebugLoc dl = Ld->getDebugLoc();
13856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13858 ISD::LoadExtType Ext = Ld->getExtensionType();
13860 // If this is a vector EXT Load then attempt to optimize it using a
13861 // shuffle. We need SSE4 for the shuffles.
13862 // TODO: It is possible to support ZExt by zeroing the undef values
13863 // during the shuffle phase or after the shuffle.
13864 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13865 assert(MemVT != RegVT && "Cannot extend to the same type");
13866 assert(MemVT.isVector() && "Must load a vector from memory");
13868 unsigned NumElems = RegVT.getVectorNumElements();
13869 unsigned RegSz = RegVT.getSizeInBits();
13870 unsigned MemSz = MemVT.getSizeInBits();
13871 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13872 // All sizes must be a power of two
13873 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13875 // Attempt to load the original value using a single load op.
13876 // Find a scalar type which is equal to the loaded word size.
13877 MVT SclrLoadTy = MVT::i8;
13878 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13879 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13880 MVT Tp = (MVT::SimpleValueType)tp;
13881 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13887 // Proceed if a load word is found.
13888 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13890 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13891 RegSz/SclrLoadTy.getSizeInBits());
13893 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13894 RegSz/MemVT.getScalarType().getSizeInBits());
13895 // Can't shuffle using an illegal type.
13896 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13898 // Perform a single load.
13899 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13901 Ld->getPointerInfo(), Ld->isVolatile(),
13902 Ld->isNonTemporal(), Ld->isInvariant(),
13903 Ld->getAlignment());
13905 // Insert the word loaded into a vector.
13906 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13907 LoadUnitVecVT, ScalarLoad);
13909 // Bitcast the loaded value to a vector of the original element type, in
13910 // the size of the target vector type.
13911 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector);
13912 unsigned SizeRatio = RegSz/MemSz;
13914 // Redistribute the loaded elements into the different locations.
13915 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13916 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13918 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13919 DAG.getUNDEF(SlicedVec.getValueType()),
13920 ShuffleVec.data());
13922 // Bitcast to the requested type.
13923 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13924 // Replace the original load with the new sequence
13925 // and return the new chain.
13926 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13927 return SDValue(ScalarLoad.getNode(), 1);
13933 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13934 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13935 const X86Subtarget *Subtarget) {
13936 StoreSDNode *St = cast<StoreSDNode>(N);
13937 EVT VT = St->getValue().getValueType();
13938 EVT StVT = St->getMemoryVT();
13939 DebugLoc dl = St->getDebugLoc();
13940 SDValue StoredVal = St->getOperand(1);
13941 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13943 // If we are saving a concatenation of two XMM registers, perform two stores.
13944 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13945 // 128-bit ones. If in the future the cost becomes only one memory access the
13946 // first version would be better.
13947 if (VT.getSizeInBits() == 256 &&
13948 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13949 StoredVal.getNumOperands() == 2) {
13951 SDValue Value0 = StoredVal.getOperand(0);
13952 SDValue Value1 = StoredVal.getOperand(1);
13954 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13955 SDValue Ptr0 = St->getBasePtr();
13956 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13958 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13959 St->getPointerInfo(), St->isVolatile(),
13960 St->isNonTemporal(), St->getAlignment());
13961 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13962 St->getPointerInfo(), St->isVolatile(),
13963 St->isNonTemporal(), St->getAlignment());
13964 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13967 // Optimize trunc store (of multiple scalars) to shuffle and store.
13968 // First, pack all of the elements in one place. Next, store to memory
13969 // in fewer chunks.
13970 if (St->isTruncatingStore() && VT.isVector()) {
13971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13972 unsigned NumElems = VT.getVectorNumElements();
13973 assert(StVT != VT && "Cannot truncate to the same type");
13974 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13975 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13977 // From, To sizes and ElemCount must be pow of two
13978 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13979 // We are going to use the original vector elt for storing.
13980 // Accumulated smaller vector elements must be a multiple of the store size.
13981 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
13983 unsigned SizeRatio = FromSz / ToSz;
13985 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13987 // Create a type on which we perform the shuffle
13988 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13989 StVT.getScalarType(), NumElems*SizeRatio);
13991 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13993 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13994 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13995 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13997 // Can't shuffle using an illegal type
13998 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14000 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14001 DAG.getUNDEF(WideVec.getValueType()),
14002 ShuffleVec.data());
14003 // At this point all of the data is stored at the bottom of the
14004 // register. We now need to save it to mem.
14006 // Find the largest store unit
14007 MVT StoreType = MVT::i8;
14008 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14009 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14010 MVT Tp = (MVT::SimpleValueType)tp;
14011 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14015 // Bitcast the original vector into a vector of store-size units
14016 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14017 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14018 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14019 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14020 SmallVector<SDValue, 8> Chains;
14021 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14022 TLI.getPointerTy());
14023 SDValue Ptr = St->getBasePtr();
14025 // Perform one or more big stores into memory.
14026 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14027 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14028 StoreType, ShuffWide,
14029 DAG.getIntPtrConstant(i));
14030 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14031 St->getPointerInfo(), St->isVolatile(),
14032 St->isNonTemporal(), St->getAlignment());
14033 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14034 Chains.push_back(Ch);
14037 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14042 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14043 // the FP state in cases where an emms may be missing.
14044 // A preferable solution to the general problem is to figure out the right
14045 // places to insert EMMS. This qualifies as a quick hack.
14047 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14048 if (VT.getSizeInBits() != 64)
14051 const Function *F = DAG.getMachineFunction().getFunction();
14052 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14053 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14054 && Subtarget->hasXMMInt();
14055 if ((VT.isVector() ||
14056 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14057 isa<LoadSDNode>(St->getValue()) &&
14058 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14059 St->getChain().hasOneUse() && !St->isVolatile()) {
14060 SDNode* LdVal = St->getValue().getNode();
14061 LoadSDNode *Ld = 0;
14062 int TokenFactorIndex = -1;
14063 SmallVector<SDValue, 8> Ops;
14064 SDNode* ChainVal = St->getChain().getNode();
14065 // Must be a store of a load. We currently handle two cases: the load
14066 // is a direct child, and it's under an intervening TokenFactor. It is
14067 // possible to dig deeper under nested TokenFactors.
14068 if (ChainVal == LdVal)
14069 Ld = cast<LoadSDNode>(St->getChain());
14070 else if (St->getValue().hasOneUse() &&
14071 ChainVal->getOpcode() == ISD::TokenFactor) {
14072 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14073 if (ChainVal->getOperand(i).getNode() == LdVal) {
14074 TokenFactorIndex = i;
14075 Ld = cast<LoadSDNode>(St->getValue());
14077 Ops.push_back(ChainVal->getOperand(i));
14081 if (!Ld || !ISD::isNormalLoad(Ld))
14084 // If this is not the MMX case, i.e. we are just turning i64 load/store
14085 // into f64 load/store, avoid the transformation if there are multiple
14086 // uses of the loaded value.
14087 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14090 DebugLoc LdDL = Ld->getDebugLoc();
14091 DebugLoc StDL = N->getDebugLoc();
14092 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14093 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14095 if (Subtarget->is64Bit() || F64IsLegal) {
14096 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14097 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14098 Ld->getPointerInfo(), Ld->isVolatile(),
14099 Ld->isNonTemporal(), Ld->isInvariant(),
14100 Ld->getAlignment());
14101 SDValue NewChain = NewLd.getValue(1);
14102 if (TokenFactorIndex != -1) {
14103 Ops.push_back(NewChain);
14104 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14107 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14108 St->getPointerInfo(),
14109 St->isVolatile(), St->isNonTemporal(),
14110 St->getAlignment());
14113 // Otherwise, lower to two pairs of 32-bit loads / stores.
14114 SDValue LoAddr = Ld->getBasePtr();
14115 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14116 DAG.getConstant(4, MVT::i32));
14118 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14119 Ld->getPointerInfo(),
14120 Ld->isVolatile(), Ld->isNonTemporal(),
14121 Ld->isInvariant(), Ld->getAlignment());
14122 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14123 Ld->getPointerInfo().getWithOffset(4),
14124 Ld->isVolatile(), Ld->isNonTemporal(),
14126 MinAlign(Ld->getAlignment(), 4));
14128 SDValue NewChain = LoLd.getValue(1);
14129 if (TokenFactorIndex != -1) {
14130 Ops.push_back(LoLd);
14131 Ops.push_back(HiLd);
14132 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14136 LoAddr = St->getBasePtr();
14137 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14138 DAG.getConstant(4, MVT::i32));
14140 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14141 St->getPointerInfo(),
14142 St->isVolatile(), St->isNonTemporal(),
14143 St->getAlignment());
14144 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14145 St->getPointerInfo().getWithOffset(4),
14147 St->isNonTemporal(),
14148 MinAlign(St->getAlignment(), 4));
14149 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14154 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14155 /// and return the operands for the horizontal operation in LHS and RHS. A
14156 /// horizontal operation performs the binary operation on successive elements
14157 /// of its first operand, then on successive elements of its second operand,
14158 /// returning the resulting values in a vector. For example, if
14159 /// A = < float a0, float a1, float a2, float a3 >
14161 /// B = < float b0, float b1, float b2, float b3 >
14162 /// then the result of doing a horizontal operation on A and B is
14163 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14164 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14165 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14166 /// set to A, RHS to B, and the routine returns 'true'.
14167 /// Note that the binary operation should have the property that if one of the
14168 /// operands is UNDEF then the result is UNDEF.
14169 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14170 // Look for the following pattern: if
14171 // A = < float a0, float a1, float a2, float a3 >
14172 // B = < float b0, float b1, float b2, float b3 >
14174 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14175 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14176 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14177 // which is A horizontal-op B.
14179 // At least one of the operands should be a vector shuffle.
14180 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14181 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14184 EVT VT = LHS.getValueType();
14186 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14187 "Unsupported vector type for horizontal add/sub");
14189 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14190 // operate independently on 128-bit lanes.
14191 unsigned NumElts = VT.getVectorNumElements();
14192 unsigned NumLanes = VT.getSizeInBits()/128;
14193 unsigned NumLaneElts = NumElts / NumLanes;
14194 assert((NumLaneElts % 2 == 0) &&
14195 "Vector type should have an even number of elements in each lane");
14196 unsigned HalfLaneElts = NumLaneElts/2;
14198 // View LHS in the form
14199 // LHS = VECTOR_SHUFFLE A, B, LMask
14200 // If LHS is not a shuffle then pretend it is the shuffle
14201 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14202 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14205 SmallVector<int, 16> LMask(NumElts);
14206 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14207 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14208 A = LHS.getOperand(0);
14209 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14210 B = LHS.getOperand(1);
14211 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask);
14213 if (LHS.getOpcode() != ISD::UNDEF)
14215 for (unsigned i = 0; i != NumElts; ++i)
14219 // Likewise, view RHS in the form
14220 // RHS = VECTOR_SHUFFLE C, D, RMask
14222 SmallVector<int, 16> RMask(NumElts);
14223 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14224 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14225 C = RHS.getOperand(0);
14226 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14227 D = RHS.getOperand(1);
14228 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask);
14230 if (RHS.getOpcode() != ISD::UNDEF)
14232 for (unsigned i = 0; i != NumElts; ++i)
14236 // Check that the shuffles are both shuffling the same vectors.
14237 if (!(A == C && B == D) && !(A == D && B == C))
14240 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14241 if (!A.getNode() && !B.getNode())
14244 // If A and B occur in reverse order in RHS, then "swap" them (which means
14245 // rewriting the mask).
14247 CommuteVectorShuffleMask(RMask, NumElts);
14249 // At this point LHS and RHS are equivalent to
14250 // LHS = VECTOR_SHUFFLE A, B, LMask
14251 // RHS = VECTOR_SHUFFLE A, B, RMask
14252 // Check that the masks correspond to performing a horizontal operation.
14253 for (unsigned i = 0; i != NumElts; ++i) {
14254 int LIdx = LMask[i], RIdx = RMask[i];
14256 // Ignore any UNDEF components.
14257 if (LIdx < 0 || RIdx < 0 ||
14258 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14259 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14262 // Check that successive elements are being operated on. If not, this is
14263 // not a horizontal operation.
14264 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14265 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14266 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14267 if (!(LIdx == Index && RIdx == Index + 1) &&
14268 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14272 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14273 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14277 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14278 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14279 const X86Subtarget *Subtarget) {
14280 EVT VT = N->getValueType(0);
14281 SDValue LHS = N->getOperand(0);
14282 SDValue RHS = N->getOperand(1);
14284 // Try to synthesize horizontal adds from adds of shuffles.
14285 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14286 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14287 isHorizontalBinOp(LHS, RHS, true))
14288 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14292 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14293 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14294 const X86Subtarget *Subtarget) {
14295 EVT VT = N->getValueType(0);
14296 SDValue LHS = N->getOperand(0);
14297 SDValue RHS = N->getOperand(1);
14299 // Try to synthesize horizontal subs from subs of shuffles.
14300 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14301 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14302 isHorizontalBinOp(LHS, RHS, false))
14303 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14307 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14308 /// X86ISD::FXOR nodes.
14309 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14310 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14311 // F[X]OR(0.0, x) -> x
14312 // F[X]OR(x, 0.0) -> x
14313 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14314 if (C->getValueAPF().isPosZero())
14315 return N->getOperand(1);
14316 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14317 if (C->getValueAPF().isPosZero())
14318 return N->getOperand(0);
14322 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14323 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14324 // FAND(0.0, x) -> 0.0
14325 // FAND(x, 0.0) -> 0.0
14326 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14327 if (C->getValueAPF().isPosZero())
14328 return N->getOperand(0);
14329 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14330 if (C->getValueAPF().isPosZero())
14331 return N->getOperand(1);
14335 static SDValue PerformBTCombine(SDNode *N,
14337 TargetLowering::DAGCombinerInfo &DCI) {
14338 // BT ignores high bits in the bit index operand.
14339 SDValue Op1 = N->getOperand(1);
14340 if (Op1.hasOneUse()) {
14341 unsigned BitWidth = Op1.getValueSizeInBits();
14342 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14343 APInt KnownZero, KnownOne;
14344 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14345 !DCI.isBeforeLegalizeOps());
14346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14347 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14348 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14349 DCI.CommitTargetLoweringOpt(TLO);
14354 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14355 SDValue Op = N->getOperand(0);
14356 if (Op.getOpcode() == ISD::BITCAST)
14357 Op = Op.getOperand(0);
14358 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14359 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14360 VT.getVectorElementType().getSizeInBits() ==
14361 OpVT.getVectorElementType().getSizeInBits()) {
14362 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14367 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
14368 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14369 // (and (i32 x86isd::setcc_carry), 1)
14370 // This eliminates the zext. This transformation is necessary because
14371 // ISD::SETCC is always legalized to i8.
14372 DebugLoc dl = N->getDebugLoc();
14373 SDValue N0 = N->getOperand(0);
14374 EVT VT = N->getValueType(0);
14375 if (N0.getOpcode() == ISD::AND &&
14377 N0.getOperand(0).hasOneUse()) {
14378 SDValue N00 = N0.getOperand(0);
14379 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14381 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14382 if (!C || C->getZExtValue() != 1)
14384 return DAG.getNode(ISD::AND, dl, VT,
14385 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14386 N00.getOperand(0), N00.getOperand(1)),
14387 DAG.getConstant(1, VT));
14393 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14394 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14395 unsigned X86CC = N->getConstantOperandVal(0);
14396 SDValue EFLAG = N->getOperand(1);
14397 DebugLoc DL = N->getDebugLoc();
14399 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14400 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14402 if (X86CC == X86::COND_B)
14403 return DAG.getNode(ISD::AND, DL, MVT::i8,
14404 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14405 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14406 DAG.getConstant(1, MVT::i8));
14411 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14412 const X86TargetLowering *XTLI) {
14413 SDValue Op0 = N->getOperand(0);
14414 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14415 // a 32-bit target where SSE doesn't support i64->FP operations.
14416 if (Op0.getOpcode() == ISD::LOAD) {
14417 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14418 EVT VT = Ld->getValueType(0);
14419 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14420 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14421 !XTLI->getSubtarget()->is64Bit() &&
14422 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14423 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14424 Ld->getChain(), Op0, DAG);
14425 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14432 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14433 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14434 X86TargetLowering::DAGCombinerInfo &DCI) {
14435 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14436 // the result is either zero or one (depending on the input carry bit).
14437 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14438 if (X86::isZeroNode(N->getOperand(0)) &&
14439 X86::isZeroNode(N->getOperand(1)) &&
14440 // We don't have a good way to replace an EFLAGS use, so only do this when
14442 SDValue(N, 1).use_empty()) {
14443 DebugLoc DL = N->getDebugLoc();
14444 EVT VT = N->getValueType(0);
14445 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14446 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14447 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14448 DAG.getConstant(X86::COND_B,MVT::i8),
14450 DAG.getConstant(1, VT));
14451 return DCI.CombineTo(N, Res1, CarryOut);
14457 // fold (add Y, (sete X, 0)) -> adc 0, Y
14458 // (add Y, (setne X, 0)) -> sbb -1, Y
14459 // (sub (sete X, 0), Y) -> sbb 0, Y
14460 // (sub (setne X, 0), Y) -> adc -1, Y
14461 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14462 DebugLoc DL = N->getDebugLoc();
14464 // Look through ZExts.
14465 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14466 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14469 SDValue SetCC = Ext.getOperand(0);
14470 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14473 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14474 if (CC != X86::COND_E && CC != X86::COND_NE)
14477 SDValue Cmp = SetCC.getOperand(1);
14478 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14479 !X86::isZeroNode(Cmp.getOperand(1)) ||
14480 !Cmp.getOperand(0).getValueType().isInteger())
14483 SDValue CmpOp0 = Cmp.getOperand(0);
14484 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14485 DAG.getConstant(1, CmpOp0.getValueType()));
14487 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14488 if (CC == X86::COND_NE)
14489 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14490 DL, OtherVal.getValueType(), OtherVal,
14491 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14492 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14493 DL, OtherVal.getValueType(), OtherVal,
14494 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14497 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14498 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14499 const X86Subtarget *Subtarget) {
14500 EVT VT = N->getValueType(0);
14501 SDValue Op0 = N->getOperand(0);
14502 SDValue Op1 = N->getOperand(1);
14504 // Try to synthesize horizontal adds from adds of shuffles.
14505 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14506 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || MVT::v8i32))) &&
14507 isHorizontalBinOp(Op0, Op1, true))
14508 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14510 return OptimizeConditionalInDecrement(N, DAG);
14513 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14514 const X86Subtarget *Subtarget) {
14515 SDValue Op0 = N->getOperand(0);
14516 SDValue Op1 = N->getOperand(1);
14518 // X86 can't encode an immediate LHS of a sub. See if we can push the
14519 // negation into a preceding instruction.
14520 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14521 // If the RHS of the sub is a XOR with one use and a constant, invert the
14522 // immediate. Then add one to the LHS of the sub so we can turn
14523 // X-Y -> X+~Y+1, saving one register.
14524 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14525 isa<ConstantSDNode>(Op1.getOperand(1))) {
14526 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14527 EVT VT = Op0.getValueType();
14528 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14530 DAG.getConstant(~XorC, VT));
14531 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14532 DAG.getConstant(C->getAPIntValue()+1, VT));
14536 // Try to synthesize horizontal adds from adds of shuffles.
14537 EVT VT = N->getValueType(0);
14538 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14539 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14540 isHorizontalBinOp(Op0, Op1, true))
14541 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14543 return OptimizeConditionalInDecrement(N, DAG);
14546 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14547 DAGCombinerInfo &DCI) const {
14548 SelectionDAG &DAG = DCI.DAG;
14549 switch (N->getOpcode()) {
14551 case ISD::EXTRACT_VECTOR_ELT:
14552 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14554 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
14555 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14556 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14557 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14558 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14559 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14562 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14563 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14564 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14565 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14566 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14567 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14568 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14569 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14570 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14572 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14573 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14574 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14575 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14576 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
14577 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14578 case X86ISD::SHUFPS: // Handle all target specific shuffles
14579 case X86ISD::SHUFPD:
14580 case X86ISD::PALIGN:
14581 case X86ISD::UNPCKH:
14582 case X86ISD::UNPCKL:
14583 case X86ISD::MOVHLPS:
14584 case X86ISD::MOVLHPS:
14585 case X86ISD::PSHUFD:
14586 case X86ISD::PSHUFHW:
14587 case X86ISD::PSHUFLW:
14588 case X86ISD::MOVSS:
14589 case X86ISD::MOVSD:
14590 case X86ISD::VPERMILP:
14591 case X86ISD::VPERM2X128:
14592 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14598 /// isTypeDesirableForOp - Return true if the target has native support for
14599 /// the specified value type and it is 'desirable' to use the type for the
14600 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14601 /// instruction encodings are longer and some i16 instructions are slow.
14602 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14603 if (!isTypeLegal(VT))
14605 if (VT != MVT::i16)
14612 case ISD::SIGN_EXTEND:
14613 case ISD::ZERO_EXTEND:
14614 case ISD::ANY_EXTEND:
14627 /// IsDesirableToPromoteOp - This method query the target whether it is
14628 /// beneficial for dag combiner to promote the specified node. If true, it
14629 /// should return the desired promotion type by reference.
14630 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14631 EVT VT = Op.getValueType();
14632 if (VT != MVT::i16)
14635 bool Promote = false;
14636 bool Commute = false;
14637 switch (Op.getOpcode()) {
14640 LoadSDNode *LD = cast<LoadSDNode>(Op);
14641 // If the non-extending load has a single use and it's not live out, then it
14642 // might be folded.
14643 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14644 Op.hasOneUse()*/) {
14645 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14646 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14647 // The only case where we'd want to promote LOAD (rather then it being
14648 // promoted as an operand is when it's only use is liveout.
14649 if (UI->getOpcode() != ISD::CopyToReg)
14656 case ISD::SIGN_EXTEND:
14657 case ISD::ZERO_EXTEND:
14658 case ISD::ANY_EXTEND:
14663 SDValue N0 = Op.getOperand(0);
14664 // Look out for (store (shl (load), x)).
14665 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14678 SDValue N0 = Op.getOperand(0);
14679 SDValue N1 = Op.getOperand(1);
14680 if (!Commute && MayFoldLoad(N1))
14682 // Avoid disabling potential load folding opportunities.
14683 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14685 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14695 //===----------------------------------------------------------------------===//
14696 // X86 Inline Assembly Support
14697 //===----------------------------------------------------------------------===//
14700 // Helper to match a string separated by whitespace.
14701 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
14702 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
14704 for (unsigned i = 0, e = args.size(); i != e; ++i) {
14705 StringRef piece(*args[i]);
14706 if (!s.startswith(piece)) // Check if the piece matches.
14709 s = s.substr(piece.size());
14710 StringRef::size_type pos = s.find_first_not_of(" \t");
14711 if (pos == 0) // We matched a prefix.
14719 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
14722 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14723 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14725 std::string AsmStr = IA->getAsmString();
14727 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14728 if (!Ty || Ty->getBitWidth() % 16 != 0)
14731 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14732 SmallVector<StringRef, 4> AsmPieces;
14733 SplitString(AsmStr, AsmPieces, ";\n");
14735 switch (AsmPieces.size()) {
14736 default: return false;
14738 // FIXME: this should verify that we are targeting a 486 or better. If not,
14739 // we will turn this bswap into something that will be lowered to logical
14740 // ops instead of emitting the bswap asm. For now, we don't support 486 or
14741 // lower so don't worry about this.
14743 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
14744 matchAsm(AsmPieces[0], "bswapl", "$0") ||
14745 matchAsm(AsmPieces[0], "bswapq", "$0") ||
14746 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
14747 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
14748 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
14749 // No need to check constraints, nothing other than the equivalent of
14750 // "=r,0" would be valid here.
14751 return IntrinsicLowering::LowerToByteSwap(CI);
14754 // rorw $$8, ${0:w} --> llvm.bswap.i16
14755 if (CI->getType()->isIntegerTy(16) &&
14756 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14757 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
14758 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
14760 const std::string &ConstraintsStr = IA->getConstraintString();
14761 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14762 std::sort(AsmPieces.begin(), AsmPieces.end());
14763 if (AsmPieces.size() == 4 &&
14764 AsmPieces[0] == "~{cc}" &&
14765 AsmPieces[1] == "~{dirflag}" &&
14766 AsmPieces[2] == "~{flags}" &&
14767 AsmPieces[3] == "~{fpsr}")
14768 return IntrinsicLowering::LowerToByteSwap(CI);
14772 if (CI->getType()->isIntegerTy(32) &&
14773 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14774 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
14775 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
14776 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
14778 const std::string &ConstraintsStr = IA->getConstraintString();
14779 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14780 std::sort(AsmPieces.begin(), AsmPieces.end());
14781 if (AsmPieces.size() == 4 &&
14782 AsmPieces[0] == "~{cc}" &&
14783 AsmPieces[1] == "~{dirflag}" &&
14784 AsmPieces[2] == "~{flags}" &&
14785 AsmPieces[3] == "~{fpsr}")
14786 return IntrinsicLowering::LowerToByteSwap(CI);
14789 if (CI->getType()->isIntegerTy(64)) {
14790 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14791 if (Constraints.size() >= 2 &&
14792 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14793 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14794 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14795 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
14796 matchAsm(AsmPieces[1], "bswap", "%edx") &&
14797 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
14798 return IntrinsicLowering::LowerToByteSwap(CI);
14808 /// getConstraintType - Given a constraint letter, return the type of
14809 /// constraint it is for this target.
14810 X86TargetLowering::ConstraintType
14811 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14812 if (Constraint.size() == 1) {
14813 switch (Constraint[0]) {
14824 return C_RegisterClass;
14848 return TargetLowering::getConstraintType(Constraint);
14851 /// Examine constraint type and operand type and determine a weight value.
14852 /// This object must already have been set up with the operand type
14853 /// and the current alternative constraint selected.
14854 TargetLowering::ConstraintWeight
14855 X86TargetLowering::getSingleConstraintMatchWeight(
14856 AsmOperandInfo &info, const char *constraint) const {
14857 ConstraintWeight weight = CW_Invalid;
14858 Value *CallOperandVal = info.CallOperandVal;
14859 // If we don't have a value, we can't do a match,
14860 // but allow it at the lowest weight.
14861 if (CallOperandVal == NULL)
14863 Type *type = CallOperandVal->getType();
14864 // Look at the constraint type.
14865 switch (*constraint) {
14867 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14878 if (CallOperandVal->getType()->isIntegerTy())
14879 weight = CW_SpecificReg;
14884 if (type->isFloatingPointTy())
14885 weight = CW_SpecificReg;
14888 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14889 weight = CW_SpecificReg;
14893 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14894 weight = CW_Register;
14897 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14898 if (C->getZExtValue() <= 31)
14899 weight = CW_Constant;
14903 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14904 if (C->getZExtValue() <= 63)
14905 weight = CW_Constant;
14909 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14910 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14911 weight = CW_Constant;
14915 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14916 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14917 weight = CW_Constant;
14921 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14922 if (C->getZExtValue() <= 3)
14923 weight = CW_Constant;
14927 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14928 if (C->getZExtValue() <= 0xff)
14929 weight = CW_Constant;
14934 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14935 weight = CW_Constant;
14939 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14940 if ((C->getSExtValue() >= -0x80000000LL) &&
14941 (C->getSExtValue() <= 0x7fffffffLL))
14942 weight = CW_Constant;
14946 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14947 if (C->getZExtValue() <= 0xffffffff)
14948 weight = CW_Constant;
14955 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14956 /// with another that has more specific requirements based on the type of the
14957 /// corresponding operand.
14958 const char *X86TargetLowering::
14959 LowerXConstraint(EVT ConstraintVT) const {
14960 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14961 // 'f' like normal targets.
14962 if (ConstraintVT.isFloatingPoint()) {
14963 if (Subtarget->hasXMMInt())
14965 if (Subtarget->hasXMM())
14969 return TargetLowering::LowerXConstraint(ConstraintVT);
14972 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14973 /// vector. If it is invalid, don't add anything to Ops.
14974 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14975 std::string &Constraint,
14976 std::vector<SDValue>&Ops,
14977 SelectionDAG &DAG) const {
14978 SDValue Result(0, 0);
14980 // Only support length 1 constraints for now.
14981 if (Constraint.length() > 1) return;
14983 char ConstraintLetter = Constraint[0];
14984 switch (ConstraintLetter) {
14987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14988 if (C->getZExtValue() <= 31) {
14989 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14995 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14996 if (C->getZExtValue() <= 63) {
14997 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15004 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15005 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15012 if (C->getZExtValue() <= 255) {
15013 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15019 // 32-bit signed value
15020 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15021 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15022 C->getSExtValue())) {
15023 // Widen to 64 bits here to get it sign extended.
15024 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15027 // FIXME gcc accepts some relocatable values here too, but only in certain
15028 // memory models; it's complicated.
15033 // 32-bit unsigned value
15034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15035 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15036 C->getZExtValue())) {
15037 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15041 // FIXME gcc accepts some relocatable values here too, but only in certain
15042 // memory models; it's complicated.
15046 // Literal immediates are always ok.
15047 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15048 // Widen to 64 bits here to get it sign extended.
15049 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15053 // In any sort of PIC mode addresses need to be computed at runtime by
15054 // adding in a register or some sort of table lookup. These can't
15055 // be used as immediates.
15056 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15059 // If we are in non-pic codegen mode, we allow the address of a global (with
15060 // an optional displacement) to be used with 'i'.
15061 GlobalAddressSDNode *GA = 0;
15062 int64_t Offset = 0;
15064 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15066 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15067 Offset += GA->getOffset();
15069 } else if (Op.getOpcode() == ISD::ADD) {
15070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15071 Offset += C->getZExtValue();
15072 Op = Op.getOperand(0);
15075 } else if (Op.getOpcode() == ISD::SUB) {
15076 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15077 Offset += -C->getZExtValue();
15078 Op = Op.getOperand(0);
15083 // Otherwise, this isn't something we can handle, reject it.
15087 const GlobalValue *GV = GA->getGlobal();
15088 // If we require an extra load to get this address, as in PIC mode, we
15089 // can't accept it.
15090 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15091 getTargetMachine())))
15094 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15095 GA->getValueType(0), Offset);
15100 if (Result.getNode()) {
15101 Ops.push_back(Result);
15104 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15107 std::pair<unsigned, const TargetRegisterClass*>
15108 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15110 // First, see if this is a constraint that directly corresponds to an LLVM
15112 if (Constraint.size() == 1) {
15113 // GCC Constraint Letters
15114 switch (Constraint[0]) {
15116 // TODO: Slight differences here in allocation order and leaving
15117 // RIP in the class. Do they matter any more here than they do
15118 // in the normal allocation?
15119 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15120 if (Subtarget->is64Bit()) {
15121 if (VT == MVT::i32 || VT == MVT::f32)
15122 return std::make_pair(0U, X86::GR32RegisterClass);
15123 else if (VT == MVT::i16)
15124 return std::make_pair(0U, X86::GR16RegisterClass);
15125 else if (VT == MVT::i8 || VT == MVT::i1)
15126 return std::make_pair(0U, X86::GR8RegisterClass);
15127 else if (VT == MVT::i64 || VT == MVT::f64)
15128 return std::make_pair(0U, X86::GR64RegisterClass);
15131 // 32-bit fallthrough
15132 case 'Q': // Q_REGS
15133 if (VT == MVT::i32 || VT == MVT::f32)
15134 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15135 else if (VT == MVT::i16)
15136 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15137 else if (VT == MVT::i8 || VT == MVT::i1)
15138 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15139 else if (VT == MVT::i64)
15140 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15142 case 'r': // GENERAL_REGS
15143 case 'l': // INDEX_REGS
15144 if (VT == MVT::i8 || VT == MVT::i1)
15145 return std::make_pair(0U, X86::GR8RegisterClass);
15146 if (VT == MVT::i16)
15147 return std::make_pair(0U, X86::GR16RegisterClass);
15148 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15149 return std::make_pair(0U, X86::GR32RegisterClass);
15150 return std::make_pair(0U, X86::GR64RegisterClass);
15151 case 'R': // LEGACY_REGS
15152 if (VT == MVT::i8 || VT == MVT::i1)
15153 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15154 if (VT == MVT::i16)
15155 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15156 if (VT == MVT::i32 || !Subtarget->is64Bit())
15157 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15158 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15159 case 'f': // FP Stack registers.
15160 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15161 // value to the correct fpstack register class.
15162 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15163 return std::make_pair(0U, X86::RFP32RegisterClass);
15164 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15165 return std::make_pair(0U, X86::RFP64RegisterClass);
15166 return std::make_pair(0U, X86::RFP80RegisterClass);
15167 case 'y': // MMX_REGS if MMX allowed.
15168 if (!Subtarget->hasMMX()) break;
15169 return std::make_pair(0U, X86::VR64RegisterClass);
15170 case 'Y': // SSE_REGS if SSE2 allowed
15171 if (!Subtarget->hasXMMInt()) break;
15173 case 'x': // SSE_REGS if SSE1 allowed
15174 if (!Subtarget->hasXMM()) break;
15176 switch (VT.getSimpleVT().SimpleTy) {
15178 // Scalar SSE types.
15181 return std::make_pair(0U, X86::FR32RegisterClass);
15184 return std::make_pair(0U, X86::FR64RegisterClass);
15192 return std::make_pair(0U, X86::VR128RegisterClass);
15198 // Use the default implementation in TargetLowering to convert the register
15199 // constraint into a member of a register class.
15200 std::pair<unsigned, const TargetRegisterClass*> Res;
15201 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15203 // Not found as a standard register?
15204 if (Res.second == 0) {
15205 // Map st(0) -> st(7) -> ST0
15206 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15207 tolower(Constraint[1]) == 's' &&
15208 tolower(Constraint[2]) == 't' &&
15209 Constraint[3] == '(' &&
15210 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15211 Constraint[5] == ')' &&
15212 Constraint[6] == '}') {
15214 Res.first = X86::ST0+Constraint[4]-'0';
15215 Res.second = X86::RFP80RegisterClass;
15219 // GCC allows "st(0)" to be called just plain "st".
15220 if (StringRef("{st}").equals_lower(Constraint)) {
15221 Res.first = X86::ST0;
15222 Res.second = X86::RFP80RegisterClass;
15227 if (StringRef("{flags}").equals_lower(Constraint)) {
15228 Res.first = X86::EFLAGS;
15229 Res.second = X86::CCRRegisterClass;
15233 // 'A' means EAX + EDX.
15234 if (Constraint == "A") {
15235 Res.first = X86::EAX;
15236 Res.second = X86::GR32_ADRegisterClass;
15242 // Otherwise, check to see if this is a register class of the wrong value
15243 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15244 // turn into {ax},{dx}.
15245 if (Res.second->hasType(VT))
15246 return Res; // Correct type already, nothing to do.
15248 // All of the single-register GCC register classes map their values onto
15249 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15250 // really want an 8-bit or 32-bit register, map to the appropriate register
15251 // class and return the appropriate register.
15252 if (Res.second == X86::GR16RegisterClass) {
15253 if (VT == MVT::i8) {
15254 unsigned DestReg = 0;
15255 switch (Res.first) {
15257 case X86::AX: DestReg = X86::AL; break;
15258 case X86::DX: DestReg = X86::DL; break;
15259 case X86::CX: DestReg = X86::CL; break;
15260 case X86::BX: DestReg = X86::BL; break;
15263 Res.first = DestReg;
15264 Res.second = X86::GR8RegisterClass;
15266 } else if (VT == MVT::i32) {
15267 unsigned DestReg = 0;
15268 switch (Res.first) {
15270 case X86::AX: DestReg = X86::EAX; break;
15271 case X86::DX: DestReg = X86::EDX; break;
15272 case X86::CX: DestReg = X86::ECX; break;
15273 case X86::BX: DestReg = X86::EBX; break;
15274 case X86::SI: DestReg = X86::ESI; break;
15275 case X86::DI: DestReg = X86::EDI; break;
15276 case X86::BP: DestReg = X86::EBP; break;
15277 case X86::SP: DestReg = X86::ESP; break;
15280 Res.first = DestReg;
15281 Res.second = X86::GR32RegisterClass;
15283 } else if (VT == MVT::i64) {
15284 unsigned DestReg = 0;
15285 switch (Res.first) {
15287 case X86::AX: DestReg = X86::RAX; break;
15288 case X86::DX: DestReg = X86::RDX; break;
15289 case X86::CX: DestReg = X86::RCX; break;
15290 case X86::BX: DestReg = X86::RBX; break;
15291 case X86::SI: DestReg = X86::RSI; break;
15292 case X86::DI: DestReg = X86::RDI; break;
15293 case X86::BP: DestReg = X86::RBP; break;
15294 case X86::SP: DestReg = X86::RSP; break;
15297 Res.first = DestReg;
15298 Res.second = X86::GR64RegisterClass;
15301 } else if (Res.second == X86::FR32RegisterClass ||
15302 Res.second == X86::FR64RegisterClass ||
15303 Res.second == X86::VR128RegisterClass) {
15304 // Handle references to XMM physical registers that got mapped into the
15305 // wrong class. This can happen with constraints like {xmm0} where the
15306 // target independent register mapper will just pick the first match it can
15307 // find, ignoring the required type.
15308 if (VT == MVT::f32)
15309 Res.second = X86::FR32RegisterClass;
15310 else if (VT == MVT::f64)
15311 Res.second = X86::FR64RegisterClass;
15312 else if (X86::VR128RegisterClass->hasType(VT))
15313 Res.second = X86::VR128RegisterClass;