1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalAlias.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/LLVMContext.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCExpr.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/Dwarf.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
53 using namespace dwarf;
55 STATISTIC(NumTailCalls, "Number of tail calls");
58 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
66 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
68 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
69 if (is64Bit) return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
71 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
72 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
73 return new X8632_ELFTargetObjectFile(TM);
74 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
75 return new TargetLoweringObjectFileCOFF();
77 llvm_unreachable("unknown subtarget type");
80 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
81 : TargetLowering(TM, createTLOF(TM)) {
82 Subtarget = &TM.getSubtarget<X86Subtarget>();
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
85 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
87 RegInfo = TM.getRegisterInfo();
90 // Set up the TargetLowering object.
92 // X86 is weird, it always uses i8 for shift amounts and setcc results.
93 setShiftAmountType(MVT::i8);
94 setBooleanContents(ZeroOrOneBooleanContent);
95 setSchedulingPreference(Sched::RegPressure);
96 setStackPointerRegisterToSaveRestore(X86StackPtr);
98 if (Subtarget->isTargetDarwin()) {
99 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
100 setUseUnderscoreSetJmp(false);
101 setUseUnderscoreLongJmp(false);
102 } else if (Subtarget->isTargetMingw()) {
103 // MS runtime is weird: it exports _setjmp, but longjmp!
104 setUseUnderscoreSetJmp(true);
105 setUseUnderscoreLongJmp(false);
107 setUseUnderscoreSetJmp(true);
108 setUseUnderscoreLongJmp(true);
111 // Set up the register classes.
112 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
122 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
124 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
128 // SETOEQ and SETUNE require checking two conditions.
129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
145 } else if (!UseSoftFloat) {
146 // We have an algorithm for SSE2->double, and we turn this into a
147 // 64-bit FILD followed by conditional FADD for other targets.
148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
149 // We have an algorithm for SSE2, and we turn this into a 64-bit
150 // FILD for other targets.
151 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
154 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
156 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
157 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
160 // SSE has no i16 to fp conversion, only i32
161 if (X86ScalarSSEf32) {
162 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
163 // f32 and f64 cases are Legal, f80 case is not
164 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
166 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
174 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
175 // are Legal, f80 is custom lowered.
176 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
177 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
179 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
181 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
182 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
184 if (X86ScalarSSEf32) {
185 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
186 // f32 and f64 cases are Legal, f80 case is not
187 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
189 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
193 // Handle FP_TO_UINT by promoting the destination to a larger signed
195 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
196 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
199 if (Subtarget->is64Bit()) {
200 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
202 } else if (!UseSoftFloat) {
203 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
204 // Expand FP_TO_UINT into a select.
205 // FIXME: We would like to use a Custom expander here eventually to do
206 // the optimal thing for SSE vs. the default expansion in the legalizer.
207 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
209 // With SSE3 we can use fisttpll to convert to a signed i64; without
210 // SSE, we're stuck with a fistpll.
211 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
214 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
215 if (!X86ScalarSSEf64) {
216 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
217 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
218 if (Subtarget->is64Bit()) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
220 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
221 if (Subtarget->hasMMX() && !DisableMMX)
222 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
224 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
228 // Scalar integer divide and remainder are lowered to use operations that
229 // produce two results, to match the available instructions. This exposes
230 // the two-result form to trivial CSE, which is able to combine x/y and x%y
231 // into a single instruction.
233 // Scalar integer multiply-high is also lowered to use two-result
234 // operations, to match the available instructions. However, plain multiply
235 // (low) operations are left as Legal, as there are single-result
236 // instructions for this in x86. Using the two-result multiply instructions
237 // when both high and low results are needed must be arranged by dagcombine.
238 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
240 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
241 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
242 setOperationAction(ISD::SREM , MVT::i8 , Expand);
243 setOperationAction(ISD::UREM , MVT::i8 , Expand);
244 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
246 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
247 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
248 setOperationAction(ISD::SREM , MVT::i16 , Expand);
249 setOperationAction(ISD::UREM , MVT::i16 , Expand);
250 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
252 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
253 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
254 setOperationAction(ISD::SREM , MVT::i32 , Expand);
255 setOperationAction(ISD::UREM , MVT::i32 , Expand);
256 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
257 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
258 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
259 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
260 setOperationAction(ISD::SREM , MVT::i64 , Expand);
261 setOperationAction(ISD::UREM , MVT::i64 , Expand);
263 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
264 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
265 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
266 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
267 if (Subtarget->is64Bit())
268 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
272 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
273 setOperationAction(ISD::FREM , MVT::f32 , Expand);
274 setOperationAction(ISD::FREM , MVT::f64 , Expand);
275 setOperationAction(ISD::FREM , MVT::f80 , Expand);
276 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
278 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
279 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
280 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
281 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
282 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
300 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
302 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
305 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
308 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
309 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
315 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
318 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
319 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
320 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
321 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
322 if (Subtarget->is64Bit())
323 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
324 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
325 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
328 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
329 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
330 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
333 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
334 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
335 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
336 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
339 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
340 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
343 if (Subtarget->hasSSE1())
344 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
346 if (!Subtarget->hasSSE2())
347 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
348 // On X86 and X86-64, atomic operations are lowered to locked instructions.
349 // Locked instructions, in turn, have implicit fence semantics (all memory
350 // operations are flushed before issuing the locked instruction, and they
351 // are not buffered), so we can fold away the common pattern of
352 // fence-atomic-fence.
353 setShouldFoldAtomicFences(true);
355 // Expand certain atomics
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
366 if (!Subtarget->is64Bit()) {
367 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
376 // FIXME - use subtarget debug flags
377 if (!Subtarget->isTargetDarwin() &&
378 !Subtarget->isTargetELF() &&
379 !Subtarget->isTargetCygMing()) {
380 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
383 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
384 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
387 if (Subtarget->is64Bit()) {
388 setExceptionPointerRegister(X86::RAX);
389 setExceptionSelectorRegister(X86::RDX);
391 setExceptionPointerRegister(X86::EAX);
392 setExceptionSelectorRegister(X86::EDX);
394 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
397 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
402 setOperationAction(ISD::VASTART , MVT::Other, Custom);
403 setOperationAction(ISD::VAEND , MVT::Other, Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::VAARG , MVT::Other, Custom);
406 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
408 setOperationAction(ISD::VAARG , MVT::Other, Expand);
409 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
412 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
413 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
414 if (Subtarget->is64Bit())
415 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
416 if (Subtarget->isTargetCygMing())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
421 if (!UseSoftFloat && X86ScalarSSEf64) {
422 // f32 and f64 use SSE.
423 // Set up the FP register classes.
424 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
425 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
427 // Use ANDPD to simulate FABS.
428 setOperationAction(ISD::FABS , MVT::f64, Custom);
429 setOperationAction(ISD::FABS , MVT::f32, Custom);
431 // Use XORP to simulate FNEG.
432 setOperationAction(ISD::FNEG , MVT::f64, Custom);
433 setOperationAction(ISD::FNEG , MVT::f32, Custom);
435 // Use ANDPD and ORPD to simulate FCOPYSIGN.
436 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
437 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
439 // We don't support sin/cos/fmod
440 setOperationAction(ISD::FSIN , MVT::f64, Expand);
441 setOperationAction(ISD::FCOS , MVT::f64, Expand);
442 setOperationAction(ISD::FSIN , MVT::f32, Expand);
443 setOperationAction(ISD::FCOS , MVT::f32, Expand);
445 // Expand FP immediates into loads from the stack, except for the special
447 addLegalFPImmediate(APFloat(+0.0)); // xorpd
448 addLegalFPImmediate(APFloat(+0.0f)); // xorps
449 } else if (!UseSoftFloat && X86ScalarSSEf32) {
450 // Use SSE for f32, x87 for f64.
451 // Set up the FP register classes.
452 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
453 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
455 // Use ANDPS to simulate FABS.
456 setOperationAction(ISD::FABS , MVT::f32, Custom);
458 // Use XORP to simulate FNEG.
459 setOperationAction(ISD::FNEG , MVT::f32, Custom);
461 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
463 // Use ANDPS and ORPS to simulate FCOPYSIGN.
464 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
467 // We don't support sin/cos/fmod
468 setOperationAction(ISD::FSIN , MVT::f32, Expand);
469 setOperationAction(ISD::FCOS , MVT::f32, Expand);
471 // Special cases we handle for FP constants.
472 addLegalFPImmediate(APFloat(+0.0f)); // xorps
473 addLegalFPImmediate(APFloat(+0.0)); // FLD0
474 addLegalFPImmediate(APFloat(+1.0)); // FLD1
475 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
476 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
479 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
480 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
482 } else if (!UseSoftFloat) {
483 // f32 and f64 in x87.
484 // Set up the FP register classes.
485 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
486 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
488 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
489 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
494 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
495 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
497 addLegalFPImmediate(APFloat(+0.0)); // FLD0
498 addLegalFPImmediate(APFloat(+1.0)); // FLD1
499 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
500 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
501 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
502 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
503 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
504 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
507 // Long double always uses X87.
509 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
510 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
511 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
514 APFloat TmpFlt(+0.0);
515 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
517 addLegalFPImmediate(TmpFlt); // FLD0
519 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
520 APFloat TmpFlt2(+1.0);
521 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
523 addLegalFPImmediate(TmpFlt2); // FLD1
524 TmpFlt2.changeSign();
525 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
529 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
530 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
534 // Always use a library call for pow.
535 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
536 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
539 setOperationAction(ISD::FLOG, MVT::f80, Expand);
540 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
542 setOperationAction(ISD::FEXP, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
545 // First set operation action for all vector types to either promote
546 // (for widening) or expand (for scalarization). Then we will selectively
547 // turn on ones that can be effectively codegen'd.
548 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
549 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
550 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
565 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
599 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
604 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
605 setTruncStoreAction((MVT::SimpleValueType)VT,
606 (MVT::SimpleValueType)InnerVT, Expand);
607 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
608 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
609 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
612 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
613 // with -msoft-float, disable use of MMX as well.
614 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
615 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
616 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
617 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
619 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
621 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
622 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
623 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
624 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
626 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
627 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
628 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
629 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
631 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
632 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
634 setOperationAction(ISD::AND, MVT::v8i8, Promote);
635 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
636 setOperationAction(ISD::AND, MVT::v4i16, Promote);
637 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
638 setOperationAction(ISD::AND, MVT::v2i32, Promote);
639 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
640 setOperationAction(ISD::AND, MVT::v1i64, Legal);
642 setOperationAction(ISD::OR, MVT::v8i8, Promote);
643 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
644 setOperationAction(ISD::OR, MVT::v4i16, Promote);
645 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
646 setOperationAction(ISD::OR, MVT::v2i32, Promote);
647 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
648 setOperationAction(ISD::OR, MVT::v1i64, Legal);
650 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
651 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
652 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
653 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
654 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
655 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
656 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
658 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
659 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
660 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
661 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
662 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
663 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
664 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
666 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
671 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
672 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
676 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
677 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
680 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
682 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
683 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
684 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
685 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
686 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
687 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
690 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
691 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
692 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
693 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
694 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
698 if (!UseSoftFloat && Subtarget->hasSSE1()) {
699 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
701 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
702 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
703 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
704 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
705 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
706 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
707 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
708 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
709 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
710 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
711 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
712 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
715 if (!UseSoftFloat && Subtarget->hasSSE2()) {
716 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
718 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
719 // registers cannot be used even for integer operations.
720 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
721 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
722 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
723 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
725 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
726 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
727 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
728 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
729 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
730 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
731 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
732 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
733 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
734 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
735 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
736 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
737 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
738 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
739 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
740 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
742 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
743 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
744 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
745 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
747 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
748 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
749 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
750 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
753 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
754 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
759 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
760 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
761 EVT VT = (MVT::SimpleValueType)i;
762 // Do not attempt to custom lower non-power-of-2 vectors
763 if (!isPowerOf2_32(VT.getVectorNumElements()))
765 // Do not attempt to custom lower non-128-bit vectors
766 if (!VT.is128BitVector())
768 setOperationAction(ISD::BUILD_VECTOR,
769 VT.getSimpleVT().SimpleTy, Custom);
770 setOperationAction(ISD::VECTOR_SHUFFLE,
771 VT.getSimpleVT().SimpleTy, Custom);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
773 VT.getSimpleVT().SimpleTy, Custom);
776 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
777 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
778 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
779 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
780 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
783 if (Subtarget->is64Bit()) {
784 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
785 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
788 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
789 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
790 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
793 // Do not attempt to promote non-128-bit vectors
794 if (!VT.is128BitVector())
797 setOperationAction(ISD::AND, SVT, Promote);
798 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
799 setOperationAction(ISD::OR, SVT, Promote);
800 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
801 setOperationAction(ISD::XOR, SVT, Promote);
802 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
803 setOperationAction(ISD::LOAD, SVT, Promote);
804 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
805 setOperationAction(ISD::SELECT, SVT, Promote);
806 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
809 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
811 // Custom lower v2i64 and v2f64 selects.
812 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
813 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
814 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
815 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
817 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
818 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
819 if (!DisableMMX && Subtarget->hasMMX()) {
820 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
821 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
825 if (Subtarget->hasSSE41()) {
826 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
827 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
828 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
829 setOperationAction(ISD::FRINT, MVT::f32, Legal);
830 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
831 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
832 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
833 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
834 setOperationAction(ISD::FRINT, MVT::f64, Legal);
835 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
837 // FIXME: Do we need to handle scalar-to-vector here?
838 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
840 // i8 and i16 vectors are custom , because the source register and source
841 // source memory operand types are not the same width. f32 vectors are
842 // custom since the immediate controlling the insert encodes additional
844 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
854 if (Subtarget->is64Bit()) {
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
860 if (Subtarget->hasSSE42()) {
861 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
864 if (!UseSoftFloat && Subtarget->hasAVX()) {
865 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
866 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
867 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
868 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
870 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
871 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
872 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
873 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
874 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
875 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
876 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
877 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
878 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
879 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
880 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
881 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
882 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
883 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
884 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
886 // Operations to consider commented out -v16i16 v32i8
887 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
888 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
889 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
890 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
891 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
892 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
893 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
894 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
895 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
896 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
897 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
898 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
899 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
900 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
902 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
903 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
904 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
905 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
907 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
908 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
909 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
913 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
914 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
915 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
921 // Not sure we want to do this since there are no 256-bit integer
924 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
925 // This includes 256-bit vectors
926 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
927 EVT VT = (MVT::SimpleValueType)i;
929 // Do not attempt to custom lower non-power-of-2 vectors
930 if (!isPowerOf2_32(VT.getVectorNumElements()))
933 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
934 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
935 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
938 if (Subtarget->is64Bit()) {
939 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
940 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
945 // Not sure we want to do this since there are no 256-bit integer
948 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
949 // Including 256-bit vectors
950 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
951 EVT VT = (MVT::SimpleValueType)i;
953 if (!VT.is256BitVector()) {
956 setOperationAction(ISD::AND, VT, Promote);
957 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
958 setOperationAction(ISD::OR, VT, Promote);
959 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
960 setOperationAction(ISD::XOR, VT, Promote);
961 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
962 setOperationAction(ISD::LOAD, VT, Promote);
963 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
964 setOperationAction(ISD::SELECT, VT, Promote);
965 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
968 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
972 // We want to custom lower some of our intrinsics.
973 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
975 // Add/Sub/Mul with overflow operations are custom lowered.
976 setOperationAction(ISD::SADDO, MVT::i32, Custom);
977 setOperationAction(ISD::UADDO, MVT::i32, Custom);
978 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
979 setOperationAction(ISD::USUBO, MVT::i32, Custom);
980 setOperationAction(ISD::SMULO, MVT::i32, Custom);
982 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
983 // handle type legalization for these operations here.
985 // FIXME: We really should do custom legalization for addition and
986 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
987 // than generic legalization for 64-bit multiplication-with-overflow, though.
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::SADDO, MVT::i64, Custom);
990 setOperationAction(ISD::UADDO, MVT::i64, Custom);
991 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
992 setOperationAction(ISD::USUBO, MVT::i64, Custom);
993 setOperationAction(ISD::SMULO, MVT::i64, Custom);
996 if (!Subtarget->is64Bit()) {
997 // These libcalls are not available in 32-bit.
998 setLibcallName(RTLIB::SHL_I128, 0);
999 setLibcallName(RTLIB::SRL_I128, 0);
1000 setLibcallName(RTLIB::SRA_I128, 0);
1003 // We have target-specific dag combine patterns for the following nodes:
1004 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1005 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1006 setTargetDAGCombine(ISD::BUILD_VECTOR);
1007 setTargetDAGCombine(ISD::SELECT);
1008 setTargetDAGCombine(ISD::SHL);
1009 setTargetDAGCombine(ISD::SRA);
1010 setTargetDAGCombine(ISD::SRL);
1011 setTargetDAGCombine(ISD::OR);
1012 setTargetDAGCombine(ISD::STORE);
1013 setTargetDAGCombine(ISD::ZERO_EXTEND);
1014 if (Subtarget->is64Bit())
1015 setTargetDAGCombine(ISD::MUL);
1017 computeRegisterProperties();
1019 // FIXME: These should be based on subtarget info. Plus, the values should
1020 // be smaller when we are in optimizing for size mode.
1021 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1022 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1023 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1024 setPrefLoopAlignment(16);
1025 benefitFromCodePlacementOpt = true;
1029 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1034 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1035 /// the desired ByVal argument alignment.
1036 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1039 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1040 if (VTy->getBitWidth() == 128)
1042 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1043 unsigned EltAlign = 0;
1044 getMaxByValAlign(ATy->getElementType(), EltAlign);
1045 if (EltAlign > MaxAlign)
1046 MaxAlign = EltAlign;
1047 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1048 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1049 unsigned EltAlign = 0;
1050 getMaxByValAlign(STy->getElementType(i), EltAlign);
1051 if (EltAlign > MaxAlign)
1052 MaxAlign = EltAlign;
1060 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1061 /// function arguments in the caller parameter area. For X86, aggregates
1062 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1063 /// are at 4-byte boundaries.
1064 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1065 if (Subtarget->is64Bit()) {
1066 // Max of 8 and alignment of type.
1067 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1074 if (Subtarget->hasSSE1())
1075 getMaxByValAlign(Ty, Align);
1079 /// getOptimalMemOpType - Returns the target specific optimal type for load
1080 /// and store operations as a result of memset, memcpy, and memmove
1081 /// lowering. If DstAlign is zero that means it's safe to destination
1082 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1083 /// means there isn't a need to check it against alignment requirement,
1084 /// probably because the source does not need to be loaded. If
1085 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1086 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1087 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1088 /// constant so it does not need to be loaded.
1089 /// It returns EVT::Other if the type should be determined using generic
1090 /// target-independent logic.
1092 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1093 unsigned DstAlign, unsigned SrcAlign,
1094 bool NonScalarIntSafe,
1096 MachineFunction &MF) const {
1097 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1098 // linux. This is because the stack realignment code can't handle certain
1099 // cases like PR2962. This should be removed when PR2962 is fixed.
1100 const Function *F = MF.getFunction();
1101 if (NonScalarIntSafe &&
1102 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1104 (Subtarget->isUnalignedMemAccessFast() ||
1105 ((DstAlign == 0 || DstAlign >= 16) &&
1106 (SrcAlign == 0 || SrcAlign >= 16))) &&
1107 Subtarget->getStackAlignment() >= 16) {
1108 if (Subtarget->hasSSE2())
1110 if (Subtarget->hasSSE1())
1112 } else if (!MemcpyStrSrc && Size >= 8 &&
1113 !Subtarget->is64Bit() &&
1114 Subtarget->getStackAlignment() >= 8 &&
1115 Subtarget->hasSSE2()) {
1116 // Do not use f64 to lower memcpy if source is string constant. It's
1117 // better to use i32 to avoid the loads.
1121 if (Subtarget->is64Bit() && Size >= 8)
1126 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1127 /// current function. The returned value is a member of the
1128 /// MachineJumpTableInfo::JTEntryKind enum.
1129 unsigned X86TargetLowering::getJumpTableEncoding() const {
1130 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1132 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1133 Subtarget->isPICStyleGOT())
1134 return MachineJumpTableInfo::EK_Custom32;
1136 // Otherwise, use the normal jump table encoding heuristics.
1137 return TargetLowering::getJumpTableEncoding();
1140 /// getPICBaseSymbol - Return the X86-32 PIC base.
1142 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1143 MCContext &Ctx) const {
1144 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1145 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1146 Twine(MF->getFunctionNumber())+"$pb");
1151 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1152 const MachineBasicBlock *MBB,
1153 unsigned uid,MCContext &Ctx) const{
1154 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1155 Subtarget->isPICStyleGOT());
1156 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1158 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1159 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1162 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1164 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1165 SelectionDAG &DAG) const {
1166 if (!Subtarget->is64Bit())
1167 // This doesn't have DebugLoc associated with it, but is not really the
1168 // same as a Register.
1169 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1173 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1174 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1176 const MCExpr *X86TargetLowering::
1177 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1178 MCContext &Ctx) const {
1179 // X86-64 uses RIP relative addressing based on the jump table label.
1180 if (Subtarget->isPICStyleRIPRel())
1181 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1183 // Otherwise, the reference is relative to the PIC base.
1184 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1187 /// getFunctionAlignment - Return the Log2 alignment of this function.
1188 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1189 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1192 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1193 unsigned &Offset) const {
1194 if (!Subtarget->isTargetLinux())
1197 if (Subtarget->is64Bit()) {
1198 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1200 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1213 //===----------------------------------------------------------------------===//
1214 // Return Value Calling Convention Implementation
1215 //===----------------------------------------------------------------------===//
1217 #include "X86GenCallingConv.inc"
1220 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1221 const SmallVectorImpl<ISD::OutputArg> &Outs,
1222 LLVMContext &Context) const {
1223 SmallVector<CCValAssign, 16> RVLocs;
1224 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1226 return CCInfo.CheckReturn(Outs, RetCC_X86);
1230 X86TargetLowering::LowerReturn(SDValue Chain,
1231 CallingConv::ID CallConv, bool isVarArg,
1232 const SmallVectorImpl<ISD::OutputArg> &Outs,
1233 const SmallVectorImpl<SDValue> &OutVals,
1234 DebugLoc dl, SelectionDAG &DAG) const {
1235 MachineFunction &MF = DAG.getMachineFunction();
1236 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1238 SmallVector<CCValAssign, 16> RVLocs;
1239 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1240 RVLocs, *DAG.getContext());
1241 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1243 // Add the regs to the liveout set for the function.
1244 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1245 for (unsigned i = 0; i != RVLocs.size(); ++i)
1246 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1247 MRI.addLiveOut(RVLocs[i].getLocReg());
1251 SmallVector<SDValue, 6> RetOps;
1252 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1253 // Operand #1 = Bytes To Pop
1254 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1257 // Copy the result values into the output registers.
1258 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1259 CCValAssign &VA = RVLocs[i];
1260 assert(VA.isRegLoc() && "Can only return in registers!");
1261 SDValue ValToCopy = OutVals[i];
1263 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1264 // the RET instruction and handled by the FP Stackifier.
1265 if (VA.getLocReg() == X86::ST0 ||
1266 VA.getLocReg() == X86::ST1) {
1267 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1268 // change the value to the FP stack register class.
1269 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1270 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1271 RetOps.push_back(ValToCopy);
1272 // Don't emit a copytoreg.
1276 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1277 // which is returned in RAX / RDX.
1278 if (Subtarget->is64Bit()) {
1279 EVT ValVT = ValToCopy.getValueType();
1280 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1281 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1282 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1283 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1287 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1288 Flag = Chain.getValue(1);
1291 // The x86-64 ABI for returning structs by value requires that we copy
1292 // the sret argument into %rax for the return. We saved the argument into
1293 // a virtual register in the entry block, so now we copy the value out
1295 if (Subtarget->is64Bit() &&
1296 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1297 MachineFunction &MF = DAG.getMachineFunction();
1298 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1299 unsigned Reg = FuncInfo->getSRetReturnReg();
1301 "SRetReturnReg should have been set in LowerFormalArguments().");
1302 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1304 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1305 Flag = Chain.getValue(1);
1307 // RAX now acts like a return value.
1308 MRI.addLiveOut(X86::RAX);
1311 RetOps[0] = Chain; // Update chain.
1313 // Add the flag if we have it.
1315 RetOps.push_back(Flag);
1317 return DAG.getNode(X86ISD::RET_FLAG, dl,
1318 MVT::Other, &RetOps[0], RetOps.size());
1321 /// LowerCallResult - Lower the result values of a call into the
1322 /// appropriate copies out of appropriate physical registers.
1325 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1326 CallingConv::ID CallConv, bool isVarArg,
1327 const SmallVectorImpl<ISD::InputArg> &Ins,
1328 DebugLoc dl, SelectionDAG &DAG,
1329 SmallVectorImpl<SDValue> &InVals) const {
1331 // Assign locations to each value returned by this call.
1332 SmallVector<CCValAssign, 16> RVLocs;
1333 bool Is64Bit = Subtarget->is64Bit();
1334 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1335 RVLocs, *DAG.getContext());
1336 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1338 // Copy all of the result registers out of their specified physreg.
1339 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1340 CCValAssign &VA = RVLocs[i];
1341 EVT CopyVT = VA.getValVT();
1343 // If this is x86-64, and we disabled SSE, we can't return FP values
1344 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1345 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1346 report_fatal_error("SSE register return with SSE disabled");
1351 // If this is a call to a function that returns an fp value on the floating
1352 // point stack, we must guarantee the the value is popped from the stack, so
1353 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1354 // if the return value is not used. We use the FpGET_ST0 instructions
1356 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1357 // If we prefer to use the value in xmm registers, copy it out as f80 and
1358 // use a truncate to move it from fp stack reg to xmm reg.
1359 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1360 bool isST0 = VA.getLocReg() == X86::ST0;
1362 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1363 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1364 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1365 SDValue Ops[] = { Chain, InFlag };
1366 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1368 Val = Chain.getValue(0);
1370 // Round the f80 to the right size, which also moves it to the appropriate
1372 if (CopyVT != VA.getValVT())
1373 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1374 // This truncation won't change the value.
1375 DAG.getIntPtrConstant(1));
1376 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1377 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1378 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1379 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1380 MVT::v2i64, InFlag).getValue(1);
1381 Val = Chain.getValue(0);
1382 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1383 Val, DAG.getConstant(0, MVT::i64));
1385 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1386 MVT::i64, InFlag).getValue(1);
1387 Val = Chain.getValue(0);
1389 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1391 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1392 CopyVT, InFlag).getValue(1);
1393 Val = Chain.getValue(0);
1395 InFlag = Chain.getValue(2);
1396 InVals.push_back(Val);
1403 //===----------------------------------------------------------------------===//
1404 // C & StdCall & Fast Calling Convention implementation
1405 //===----------------------------------------------------------------------===//
1406 // StdCall calling convention seems to be standard for many Windows' API
1407 // routines and around. It differs from C calling convention just a little:
1408 // callee should clean up the stack, not caller. Symbols should be also
1409 // decorated in some fancy way :) It doesn't support any vector arguments.
1410 // For info on fast calling convention see Fast Calling Convention (tail call)
1411 // implementation LowerX86_32FastCCCallTo.
1413 /// CallIsStructReturn - Determines whether a call uses struct return
1415 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1419 return Outs[0].Flags.isSRet();
1422 /// ArgsAreStructReturn - Determines whether a function uses struct
1423 /// return semantics.
1425 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1429 return Ins[0].Flags.isSRet();
1432 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1433 /// given CallingConvention value.
1434 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1435 if (Subtarget->is64Bit()) {
1436 if (CC == CallingConv::GHC)
1437 return CC_X86_64_GHC;
1438 else if (Subtarget->isTargetWin64())
1439 return CC_X86_Win64_C;
1444 if (CC == CallingConv::X86_FastCall)
1445 return CC_X86_32_FastCall;
1446 else if (CC == CallingConv::X86_ThisCall)
1447 return CC_X86_32_ThisCall;
1448 else if (CC == CallingConv::Fast)
1449 return CC_X86_32_FastCC;
1450 else if (CC == CallingConv::GHC)
1451 return CC_X86_32_GHC;
1456 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1457 /// by "Src" to address "Dst" with size and alignment information specified by
1458 /// the specific parameter attribute. The copy will be passed as a byval
1459 /// function parameter.
1461 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1462 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1464 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1465 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1466 /*isVolatile*/false, /*AlwaysInline=*/true,
1470 /// IsTailCallConvention - Return true if the calling convention is one that
1471 /// supports tail call optimization.
1472 static bool IsTailCallConvention(CallingConv::ID CC) {
1473 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1476 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1477 /// a tailcall target by changing its ABI.
1478 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1479 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1483 X86TargetLowering::LowerMemArgument(SDValue Chain,
1484 CallingConv::ID CallConv,
1485 const SmallVectorImpl<ISD::InputArg> &Ins,
1486 DebugLoc dl, SelectionDAG &DAG,
1487 const CCValAssign &VA,
1488 MachineFrameInfo *MFI,
1490 // Create the nodes corresponding to a load from this parameter slot.
1491 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1492 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1493 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1496 // If value is passed by pointer we have address passed instead of the value
1498 if (VA.getLocInfo() == CCValAssign::Indirect)
1499 ValVT = VA.getLocVT();
1501 ValVT = VA.getValVT();
1503 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1504 // changed with more analysis.
1505 // In case of tail call optimization mark all arguments mutable. Since they
1506 // could be overwritten by lowering of arguments in case of a tail call.
1507 if (Flags.isByVal()) {
1508 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1509 VA.getLocMemOffset(), isImmutable);
1510 return DAG.getFrameIndex(FI, getPointerTy());
1512 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1513 VA.getLocMemOffset(), isImmutable);
1514 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1515 return DAG.getLoad(ValVT, dl, Chain, FIN,
1516 PseudoSourceValue::getFixedStack(FI), 0,
1522 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1523 CallingConv::ID CallConv,
1525 const SmallVectorImpl<ISD::InputArg> &Ins,
1528 SmallVectorImpl<SDValue> &InVals)
1530 MachineFunction &MF = DAG.getMachineFunction();
1531 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1533 const Function* Fn = MF.getFunction();
1534 if (Fn->hasExternalLinkage() &&
1535 Subtarget->isTargetCygMing() &&
1536 Fn->getName() == "main")
1537 FuncInfo->setForceFramePointer(true);
1539 MachineFrameInfo *MFI = MF.getFrameInfo();
1540 bool Is64Bit = Subtarget->is64Bit();
1541 bool IsWin64 = Subtarget->isTargetWin64();
1543 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1544 "Var args not supported with calling convention fastcc or ghc");
1546 // Assign locations to all of the incoming arguments.
1547 SmallVector<CCValAssign, 16> ArgLocs;
1548 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1549 ArgLocs, *DAG.getContext());
1550 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1552 unsigned LastVal = ~0U;
1554 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1555 CCValAssign &VA = ArgLocs[i];
1556 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1558 assert(VA.getValNo() != LastVal &&
1559 "Don't support value assigned to multiple locs yet");
1560 LastVal = VA.getValNo();
1562 if (VA.isRegLoc()) {
1563 EVT RegVT = VA.getLocVT();
1564 TargetRegisterClass *RC = NULL;
1565 if (RegVT == MVT::i32)
1566 RC = X86::GR32RegisterClass;
1567 else if (Is64Bit && RegVT == MVT::i64)
1568 RC = X86::GR64RegisterClass;
1569 else if (RegVT == MVT::f32)
1570 RC = X86::FR32RegisterClass;
1571 else if (RegVT == MVT::f64)
1572 RC = X86::FR64RegisterClass;
1573 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1574 RC = X86::VR128RegisterClass;
1575 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1576 RC = X86::VR64RegisterClass;
1578 llvm_unreachable("Unknown argument type!");
1580 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1581 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1583 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1584 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1586 if (VA.getLocInfo() == CCValAssign::SExt)
1587 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1588 DAG.getValueType(VA.getValVT()));
1589 else if (VA.getLocInfo() == CCValAssign::ZExt)
1590 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1591 DAG.getValueType(VA.getValVT()));
1592 else if (VA.getLocInfo() == CCValAssign::BCvt)
1593 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1595 if (VA.isExtInLoc()) {
1596 // Handle MMX values passed in XMM regs.
1597 if (RegVT.isVector()) {
1598 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1599 ArgValue, DAG.getConstant(0, MVT::i64));
1600 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1602 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1605 assert(VA.isMemLoc());
1606 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1609 // If value is passed via pointer - do a load.
1610 if (VA.getLocInfo() == CCValAssign::Indirect)
1611 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1614 InVals.push_back(ArgValue);
1617 // The x86-64 ABI for returning structs by value requires that we copy
1618 // the sret argument into %rax for the return. Save the argument into
1619 // a virtual register so that we can access it from the return points.
1620 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1621 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1622 unsigned Reg = FuncInfo->getSRetReturnReg();
1624 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1625 FuncInfo->setSRetReturnReg(Reg);
1627 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1628 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1631 unsigned StackSize = CCInfo.getNextStackOffset();
1632 // Align stack specially for tail calls.
1633 if (FuncIsMadeTailCallSafe(CallConv))
1634 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1636 // If the function takes variable number of arguments, make a frame index for
1637 // the start of the first vararg value... for expansion of llvm.va_start.
1639 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1640 CallConv != CallingConv::X86_ThisCall)) {
1641 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1644 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1646 // FIXME: We should really autogenerate these arrays
1647 static const unsigned GPR64ArgRegsWin64[] = {
1648 X86::RCX, X86::RDX, X86::R8, X86::R9
1650 static const unsigned XMMArgRegsWin64[] = {
1651 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1653 static const unsigned GPR64ArgRegs64Bit[] = {
1654 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1656 static const unsigned XMMArgRegs64Bit[] = {
1657 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1658 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1660 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1663 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1664 GPR64ArgRegs = GPR64ArgRegsWin64;
1665 XMMArgRegs = XMMArgRegsWin64;
1667 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1668 GPR64ArgRegs = GPR64ArgRegs64Bit;
1669 XMMArgRegs = XMMArgRegs64Bit;
1671 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1673 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1676 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1677 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1678 "SSE register cannot be used when SSE is disabled!");
1679 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1680 "SSE register cannot be used when SSE is disabled!");
1681 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1682 // Kernel mode asks for SSE to be disabled, so don't push them
1684 TotalNumXMMRegs = 0;
1686 // For X86-64, if there are vararg parameters that are passed via
1687 // registers, then we must store them to their spots on the stack so they
1688 // may be loaded by deferencing the result of va_next.
1689 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1690 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1691 FuncInfo->setRegSaveFrameIndex(
1692 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1695 // Store the integer parameter registers.
1696 SmallVector<SDValue, 8> MemOps;
1697 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1699 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1700 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1701 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1702 DAG.getIntPtrConstant(Offset));
1703 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1704 X86::GR64RegisterClass);
1705 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1707 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1708 PseudoSourceValue::getFixedStack(
1709 FuncInfo->getRegSaveFrameIndex()),
1710 Offset, false, false, 0);
1711 MemOps.push_back(Store);
1715 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1716 // Now store the XMM (fp + vector) parameter registers.
1717 SmallVector<SDValue, 11> SaveXMMOps;
1718 SaveXMMOps.push_back(Chain);
1720 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1721 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1722 SaveXMMOps.push_back(ALVal);
1724 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1725 FuncInfo->getRegSaveFrameIndex()));
1726 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1727 FuncInfo->getVarArgsFPOffset()));
1729 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1730 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1731 X86::VR128RegisterClass);
1732 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1733 SaveXMMOps.push_back(Val);
1735 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1737 &SaveXMMOps[0], SaveXMMOps.size()));
1740 if (!MemOps.empty())
1741 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1742 &MemOps[0], MemOps.size());
1746 // Some CCs need callee pop.
1747 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1748 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1750 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1751 // If this is an sret function, the return should pop the hidden pointer.
1752 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1753 FuncInfo->setBytesToPopOnReturn(4);
1757 // RegSaveFrameIndex is X86-64 only.
1758 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1759 if (CallConv == CallingConv::X86_FastCall ||
1760 CallConv == CallingConv::X86_ThisCall)
1761 // fastcc functions can't have varargs.
1762 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1769 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1770 SDValue StackPtr, SDValue Arg,
1771 DebugLoc dl, SelectionDAG &DAG,
1772 const CCValAssign &VA,
1773 ISD::ArgFlagsTy Flags) const {
1774 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1775 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1776 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1777 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1778 if (Flags.isByVal()) {
1779 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1781 return DAG.getStore(Chain, dl, Arg, PtrOff,
1782 PseudoSourceValue::getStack(), LocMemOffset,
1786 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1787 /// optimization is performed and it is required.
1789 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1790 SDValue &OutRetAddr, SDValue Chain,
1791 bool IsTailCall, bool Is64Bit,
1792 int FPDiff, DebugLoc dl) const {
1793 // Adjust the Return address stack slot.
1794 EVT VT = getPointerTy();
1795 OutRetAddr = getReturnAddressFrameIndex(DAG);
1797 // Load the "old" Return address.
1798 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1799 return SDValue(OutRetAddr.getNode(), 1);
1802 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1803 /// optimization is performed and it is required (FPDiff!=0).
1805 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1806 SDValue Chain, SDValue RetAddrFrIdx,
1807 bool Is64Bit, int FPDiff, DebugLoc dl) {
1808 // Store the return address to the appropriate stack slot.
1809 if (!FPDiff) return Chain;
1810 // Calculate the new stack slot for the return address.
1811 int SlotSize = Is64Bit ? 8 : 4;
1812 int NewReturnAddrFI =
1813 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1814 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1815 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1816 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1817 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1823 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1824 CallingConv::ID CallConv, bool isVarArg,
1826 const SmallVectorImpl<ISD::OutputArg> &Outs,
1827 const SmallVectorImpl<SDValue> &OutVals,
1828 const SmallVectorImpl<ISD::InputArg> &Ins,
1829 DebugLoc dl, SelectionDAG &DAG,
1830 SmallVectorImpl<SDValue> &InVals) const {
1831 MachineFunction &MF = DAG.getMachineFunction();
1832 bool Is64Bit = Subtarget->is64Bit();
1833 bool IsStructRet = CallIsStructReturn(Outs);
1834 bool IsSibcall = false;
1837 // Check if it's really possible to do a tail call.
1838 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1839 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1840 Outs, OutVals, Ins, DAG);
1842 // Sibcalls are automatically detected tailcalls which do not require
1844 if (!GuaranteedTailCallOpt && isTailCall)
1851 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1852 "Var args not supported with calling convention fastcc or ghc");
1854 // Analyze operands of the call, assigning locations to each operand.
1855 SmallVector<CCValAssign, 16> ArgLocs;
1856 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1857 ArgLocs, *DAG.getContext());
1858 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1860 // Get a count of how many bytes are to be pushed on the stack.
1861 unsigned NumBytes = CCInfo.getNextStackOffset();
1863 // This is a sibcall. The memory operands are available in caller's
1864 // own caller's stack.
1866 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1867 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1870 if (isTailCall && !IsSibcall) {
1871 // Lower arguments at fp - stackoffset + fpdiff.
1872 unsigned NumBytesCallerPushed =
1873 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1874 FPDiff = NumBytesCallerPushed - NumBytes;
1876 // Set the delta of movement of the returnaddr stackslot.
1877 // But only set if delta is greater than previous delta.
1878 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1879 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1883 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1885 SDValue RetAddrFrIdx;
1886 // Load return adress for tail calls.
1887 if (isTailCall && FPDiff)
1888 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1889 Is64Bit, FPDiff, dl);
1891 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1892 SmallVector<SDValue, 8> MemOpChains;
1895 // Walk the register/memloc assignments, inserting copies/loads. In the case
1896 // of tail call optimization arguments are handle later.
1897 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1898 CCValAssign &VA = ArgLocs[i];
1899 EVT RegVT = VA.getLocVT();
1900 SDValue Arg = OutVals[i];
1901 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1902 bool isByVal = Flags.isByVal();
1904 // Promote the value if needed.
1905 switch (VA.getLocInfo()) {
1906 default: llvm_unreachable("Unknown loc info!");
1907 case CCValAssign::Full: break;
1908 case CCValAssign::SExt:
1909 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1911 case CCValAssign::ZExt:
1912 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1914 case CCValAssign::AExt:
1915 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1916 // Special case: passing MMX values in XMM registers.
1917 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1918 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1919 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1921 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1923 case CCValAssign::BCvt:
1924 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1926 case CCValAssign::Indirect: {
1927 // Store the argument.
1928 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1929 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1930 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1931 PseudoSourceValue::getFixedStack(FI), 0,
1938 if (VA.isRegLoc()) {
1939 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1940 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1941 assert(VA.isMemLoc());
1942 if (StackPtr.getNode() == 0)
1943 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1944 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1945 dl, DAG, VA, Flags));
1949 if (!MemOpChains.empty())
1950 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1951 &MemOpChains[0], MemOpChains.size());
1953 // Build a sequence of copy-to-reg nodes chained together with token chain
1954 // and flag operands which copy the outgoing args into registers.
1956 // Tail call byval lowering might overwrite argument registers so in case of
1957 // tail call optimization the copies to registers are lowered later.
1959 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1960 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1961 RegsToPass[i].second, InFlag);
1962 InFlag = Chain.getValue(1);
1965 if (Subtarget->isPICStyleGOT()) {
1966 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1969 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1970 DAG.getNode(X86ISD::GlobalBaseReg,
1971 DebugLoc(), getPointerTy()),
1973 InFlag = Chain.getValue(1);
1975 // If we are tail calling and generating PIC/GOT style code load the
1976 // address of the callee into ECX. The value in ecx is used as target of
1977 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1978 // for tail calls on PIC/GOT architectures. Normally we would just put the
1979 // address of GOT into ebx and then call target@PLT. But for tail calls
1980 // ebx would be restored (since ebx is callee saved) before jumping to the
1983 // Note: The actual moving to ECX is done further down.
1984 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1985 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1986 !G->getGlobal()->hasProtectedVisibility())
1987 Callee = LowerGlobalAddress(Callee, DAG);
1988 else if (isa<ExternalSymbolSDNode>(Callee))
1989 Callee = LowerExternalSymbol(Callee, DAG);
1993 if (Is64Bit && isVarArg) {
1994 // From AMD64 ABI document:
1995 // For calls that may call functions that use varargs or stdargs
1996 // (prototype-less calls or calls to functions containing ellipsis (...) in
1997 // the declaration) %al is used as hidden argument to specify the number
1998 // of SSE registers used. The contents of %al do not need to match exactly
1999 // the number of registers, but must be an ubound on the number of SSE
2000 // registers used and is in the range 0 - 8 inclusive.
2002 // FIXME: Verify this on Win64
2003 // Count the number of XMM registers allocated.
2004 static const unsigned XMMArgRegs[] = {
2005 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2006 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2008 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2009 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2010 && "SSE registers cannot be used when SSE is disabled");
2012 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2013 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2014 InFlag = Chain.getValue(1);
2018 // For tail calls lower the arguments to the 'real' stack slot.
2020 // Force all the incoming stack arguments to be loaded from the stack
2021 // before any new outgoing arguments are stored to the stack, because the
2022 // outgoing stack slots may alias the incoming argument stack slots, and
2023 // the alias isn't otherwise explicit. This is slightly more conservative
2024 // than necessary, because it means that each store effectively depends
2025 // on every argument instead of just those arguments it would clobber.
2026 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2028 SmallVector<SDValue, 8> MemOpChains2;
2031 // Do not flag preceeding copytoreg stuff together with the following stuff.
2033 if (GuaranteedTailCallOpt) {
2034 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2035 CCValAssign &VA = ArgLocs[i];
2038 assert(VA.isMemLoc());
2039 SDValue Arg = OutVals[i];
2040 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2041 // Create frame index.
2042 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2043 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2044 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2045 FIN = DAG.getFrameIndex(FI, getPointerTy());
2047 if (Flags.isByVal()) {
2048 // Copy relative to framepointer.
2049 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2050 if (StackPtr.getNode() == 0)
2051 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2053 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2055 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2059 // Store relative to framepointer.
2060 MemOpChains2.push_back(
2061 DAG.getStore(ArgChain, dl, Arg, FIN,
2062 PseudoSourceValue::getFixedStack(FI), 0,
2068 if (!MemOpChains2.empty())
2069 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2070 &MemOpChains2[0], MemOpChains2.size());
2072 // Copy arguments to their registers.
2073 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2074 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2075 RegsToPass[i].second, InFlag);
2076 InFlag = Chain.getValue(1);
2080 // Store the return address to the appropriate stack slot.
2081 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2085 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2086 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2087 // In the 64-bit large code model, we have to make all calls
2088 // through a register, since the call instruction's 32-bit
2089 // pc-relative offset may not be large enough to hold the whole
2091 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2092 // If the callee is a GlobalAddress node (quite common, every direct call
2093 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2096 // We should use extra load for direct calls to dllimported functions in
2098 const GlobalValue *GV = G->getGlobal();
2099 if (!GV->hasDLLImportLinkage()) {
2100 unsigned char OpFlags = 0;
2102 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2103 // external symbols most go through the PLT in PIC mode. If the symbol
2104 // has hidden or protected visibility, or if it is static or local, then
2105 // we don't need to use the PLT - we can directly call it.
2106 if (Subtarget->isTargetELF() &&
2107 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2108 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2109 OpFlags = X86II::MO_PLT;
2110 } else if (Subtarget->isPICStyleStubAny() &&
2111 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2112 Subtarget->getDarwinVers() < 9) {
2113 // PC-relative references to external symbols should go through $stub,
2114 // unless we're building with the leopard linker or later, which
2115 // automatically synthesizes these stubs.
2116 OpFlags = X86II::MO_DARWIN_STUB;
2119 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2120 G->getOffset(), OpFlags);
2122 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2123 unsigned char OpFlags = 0;
2125 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2126 // symbols should go through the PLT.
2127 if (Subtarget->isTargetELF() &&
2128 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2129 OpFlags = X86II::MO_PLT;
2130 } else if (Subtarget->isPICStyleStubAny() &&
2131 Subtarget->getDarwinVers() < 9) {
2132 // PC-relative references to external symbols should go through $stub,
2133 // unless we're building with the leopard linker or later, which
2134 // automatically synthesizes these stubs.
2135 OpFlags = X86II::MO_DARWIN_STUB;
2138 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2142 // Returns a chain & a flag for retval copy to use.
2143 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2144 SmallVector<SDValue, 8> Ops;
2146 if (!IsSibcall && isTailCall) {
2147 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2148 DAG.getIntPtrConstant(0, true), InFlag);
2149 InFlag = Chain.getValue(1);
2152 Ops.push_back(Chain);
2153 Ops.push_back(Callee);
2156 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2158 // Add argument registers to the end of the list so that they are known live
2160 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2161 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2162 RegsToPass[i].second.getValueType()));
2164 // Add an implicit use GOT pointer in EBX.
2165 if (!isTailCall && Subtarget->isPICStyleGOT())
2166 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2168 // Add an implicit use of AL for x86 vararg functions.
2169 if (Is64Bit && isVarArg)
2170 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2172 if (InFlag.getNode())
2173 Ops.push_back(InFlag);
2177 //// If this is the first return lowered for this function, add the regs
2178 //// to the liveout set for the function.
2179 // This isn't right, although it's probably harmless on x86; liveouts
2180 // should be computed from returns not tail calls. Consider a void
2181 // function making a tail call to a function returning int.
2182 return DAG.getNode(X86ISD::TC_RETURN, dl,
2183 NodeTys, &Ops[0], Ops.size());
2186 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2187 InFlag = Chain.getValue(1);
2189 // Create the CALLSEQ_END node.
2190 unsigned NumBytesForCalleeToPush;
2191 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2192 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2193 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2194 // If this is a call to a struct-return function, the callee
2195 // pops the hidden struct pointer, so we have to push it back.
2196 // This is common for Darwin/X86, Linux & Mingw32 targets.
2197 NumBytesForCalleeToPush = 4;
2199 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2201 // Returns a flag for retval copy to use.
2203 Chain = DAG.getCALLSEQ_END(Chain,
2204 DAG.getIntPtrConstant(NumBytes, true),
2205 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2208 InFlag = Chain.getValue(1);
2211 // Handle result values, copying them out of physregs into vregs that we
2213 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2214 Ins, dl, DAG, InVals);
2218 //===----------------------------------------------------------------------===//
2219 // Fast Calling Convention (tail call) implementation
2220 //===----------------------------------------------------------------------===//
2222 // Like std call, callee cleans arguments, convention except that ECX is
2223 // reserved for storing the tail called function address. Only 2 registers are
2224 // free for argument passing (inreg). Tail call optimization is performed
2226 // * tailcallopt is enabled
2227 // * caller/callee are fastcc
2228 // On X86_64 architecture with GOT-style position independent code only local
2229 // (within module) calls are supported at the moment.
2230 // To keep the stack aligned according to platform abi the function
2231 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2232 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2233 // If a tail called function callee has more arguments than the caller the
2234 // caller needs to make sure that there is room to move the RETADDR to. This is
2235 // achieved by reserving an area the size of the argument delta right after the
2236 // original REtADDR, but before the saved framepointer or the spilled registers
2237 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2249 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2250 /// for a 16 byte align requirement.
2252 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2253 SelectionDAG& DAG) const {
2254 MachineFunction &MF = DAG.getMachineFunction();
2255 const TargetMachine &TM = MF.getTarget();
2256 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2257 unsigned StackAlignment = TFI.getStackAlignment();
2258 uint64_t AlignMask = StackAlignment - 1;
2259 int64_t Offset = StackSize;
2260 uint64_t SlotSize = TD->getPointerSize();
2261 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2262 // Number smaller than 12 so just add the difference.
2263 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2265 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2266 Offset = ((~AlignMask) & Offset) + StackAlignment +
2267 (StackAlignment-SlotSize);
2272 /// MatchingStackOffset - Return true if the given stack call argument is
2273 /// already available in the same position (relatively) of the caller's
2274 /// incoming argument stack.
2276 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2277 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2278 const X86InstrInfo *TII) {
2279 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2281 if (Arg.getOpcode() == ISD::CopyFromReg) {
2282 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2283 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2285 MachineInstr *Def = MRI->getVRegDef(VR);
2288 if (!Flags.isByVal()) {
2289 if (!TII->isLoadFromStackSlot(Def, FI))
2292 unsigned Opcode = Def->getOpcode();
2293 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2294 Def->getOperand(1).isFI()) {
2295 FI = Def->getOperand(1).getIndex();
2296 Bytes = Flags.getByValSize();
2300 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2301 if (Flags.isByVal())
2302 // ByVal argument is passed in as a pointer but it's now being
2303 // dereferenced. e.g.
2304 // define @foo(%struct.X* %A) {
2305 // tail call @bar(%struct.X* byval %A)
2308 SDValue Ptr = Ld->getBasePtr();
2309 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2312 FI = FINode->getIndex();
2316 assert(FI != INT_MAX);
2317 if (!MFI->isFixedObjectIndex(FI))
2319 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2322 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2323 /// for tail call optimization. Targets which want to do tail call
2324 /// optimization should implement this function.
2326 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2327 CallingConv::ID CalleeCC,
2329 bool isCalleeStructRet,
2330 bool isCallerStructRet,
2331 const SmallVectorImpl<ISD::OutputArg> &Outs,
2332 const SmallVectorImpl<SDValue> &OutVals,
2333 const SmallVectorImpl<ISD::InputArg> &Ins,
2334 SelectionDAG& DAG) const {
2335 if (!IsTailCallConvention(CalleeCC) &&
2336 CalleeCC != CallingConv::C)
2339 // If -tailcallopt is specified, make fastcc functions tail-callable.
2340 const MachineFunction &MF = DAG.getMachineFunction();
2341 const Function *CallerF = DAG.getMachineFunction().getFunction();
2342 CallingConv::ID CallerCC = CallerF->getCallingConv();
2343 bool CCMatch = CallerCC == CalleeCC;
2345 if (GuaranteedTailCallOpt) {
2346 if (IsTailCallConvention(CalleeCC) && CCMatch)
2351 // Look for obvious safe cases to perform tail call optimization that do not
2352 // require ABI changes. This is what gcc calls sibcall.
2354 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2355 // emit a special epilogue.
2356 if (RegInfo->needsStackRealignment(MF))
2359 // Do not sibcall optimize vararg calls unless the call site is not passing any
2361 if (isVarArg && !Outs.empty())
2364 // Also avoid sibcall optimization if either caller or callee uses struct
2365 // return semantics.
2366 if (isCalleeStructRet || isCallerStructRet)
2369 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2370 // Therefore if it's not used by the call it is not safe to optimize this into
2372 bool Unused = false;
2373 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2380 SmallVector<CCValAssign, 16> RVLocs;
2381 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2382 RVLocs, *DAG.getContext());
2383 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2384 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2385 CCValAssign &VA = RVLocs[i];
2386 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2391 // If the calling conventions do not match, then we'd better make sure the
2392 // results are returned in the same way as what the caller expects.
2394 SmallVector<CCValAssign, 16> RVLocs1;
2395 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2396 RVLocs1, *DAG.getContext());
2397 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2399 SmallVector<CCValAssign, 16> RVLocs2;
2400 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2401 RVLocs2, *DAG.getContext());
2402 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2404 if (RVLocs1.size() != RVLocs2.size())
2406 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2407 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2409 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2411 if (RVLocs1[i].isRegLoc()) {
2412 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2415 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2421 // If the callee takes no arguments then go on to check the results of the
2423 if (!Outs.empty()) {
2424 // Check if stack adjustment is needed. For now, do not do this if any
2425 // argument is passed on the stack.
2426 SmallVector<CCValAssign, 16> ArgLocs;
2427 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2428 ArgLocs, *DAG.getContext());
2429 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2430 if (CCInfo.getNextStackOffset()) {
2431 MachineFunction &MF = DAG.getMachineFunction();
2432 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2434 if (Subtarget->isTargetWin64())
2435 // Win64 ABI has additional complications.
2438 // Check if the arguments are already laid out in the right way as
2439 // the caller's fixed stack objects.
2440 MachineFrameInfo *MFI = MF.getFrameInfo();
2441 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2442 const X86InstrInfo *TII =
2443 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2444 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2445 CCValAssign &VA = ArgLocs[i];
2446 SDValue Arg = OutVals[i];
2447 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2448 if (VA.getLocInfo() == CCValAssign::Indirect)
2450 if (!VA.isRegLoc()) {
2451 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2458 // If the tailcall address may be in a register, then make sure it's
2459 // possible to register allocate for it. In 32-bit, the call address can
2460 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2461 // callee-saved registers are restored. In 64-bit, it's RAX, RCX, RDX, RSI,
2462 // RDI, R8, R9, R11.
2463 if (!isa<GlobalAddressSDNode>(Callee) &&
2464 !isa<ExternalSymbolSDNode>(Callee)) {
2465 unsigned Limit = Subtarget->is64Bit() ? 8 : 3;
2466 unsigned NumInRegs = 0;
2467 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2468 CCValAssign &VA = ArgLocs[i];
2469 if (VA.isRegLoc()) {
2470 if (++NumInRegs == Limit)
2481 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2482 return X86::createFastISel(funcInfo);
2486 //===----------------------------------------------------------------------===//
2487 // Other Lowering Hooks
2488 //===----------------------------------------------------------------------===//
2491 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2492 MachineFunction &MF = DAG.getMachineFunction();
2493 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2494 int ReturnAddrIndex = FuncInfo->getRAIndex();
2496 if (ReturnAddrIndex == 0) {
2497 // Set up a frame object for the return address.
2498 uint64_t SlotSize = TD->getPointerSize();
2499 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2501 FuncInfo->setRAIndex(ReturnAddrIndex);
2504 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2508 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2509 bool hasSymbolicDisplacement) {
2510 // Offset should fit into 32 bit immediate field.
2511 if (!isInt<32>(Offset))
2514 // If we don't have a symbolic displacement - we don't have any extra
2516 if (!hasSymbolicDisplacement)
2519 // FIXME: Some tweaks might be needed for medium code model.
2520 if (M != CodeModel::Small && M != CodeModel::Kernel)
2523 // For small code model we assume that latest object is 16MB before end of 31
2524 // bits boundary. We may also accept pretty large negative constants knowing
2525 // that all objects are in the positive half of address space.
2526 if (M == CodeModel::Small && Offset < 16*1024*1024)
2529 // For kernel code model we know that all object resist in the negative half
2530 // of 32bits address space. We may not accept negative offsets, since they may
2531 // be just off and we may accept pretty large positive ones.
2532 if (M == CodeModel::Kernel && Offset > 0)
2538 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2539 /// specific condition code, returning the condition code and the LHS/RHS of the
2540 /// comparison to make.
2541 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2542 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2544 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2545 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2546 // X > -1 -> X == 0, jump !sign.
2547 RHS = DAG.getConstant(0, RHS.getValueType());
2548 return X86::COND_NS;
2549 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2550 // X < 0 -> X == 0, jump on sign.
2552 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2554 RHS = DAG.getConstant(0, RHS.getValueType());
2555 return X86::COND_LE;
2559 switch (SetCCOpcode) {
2560 default: llvm_unreachable("Invalid integer condition!");
2561 case ISD::SETEQ: return X86::COND_E;
2562 case ISD::SETGT: return X86::COND_G;
2563 case ISD::SETGE: return X86::COND_GE;
2564 case ISD::SETLT: return X86::COND_L;
2565 case ISD::SETLE: return X86::COND_LE;
2566 case ISD::SETNE: return X86::COND_NE;
2567 case ISD::SETULT: return X86::COND_B;
2568 case ISD::SETUGT: return X86::COND_A;
2569 case ISD::SETULE: return X86::COND_BE;
2570 case ISD::SETUGE: return X86::COND_AE;
2574 // First determine if it is required or is profitable to flip the operands.
2576 // If LHS is a foldable load, but RHS is not, flip the condition.
2577 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2578 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2579 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2580 std::swap(LHS, RHS);
2583 switch (SetCCOpcode) {
2589 std::swap(LHS, RHS);
2593 // On a floating point condition, the flags are set as follows:
2595 // 0 | 0 | 0 | X > Y
2596 // 0 | 0 | 1 | X < Y
2597 // 1 | 0 | 0 | X == Y
2598 // 1 | 1 | 1 | unordered
2599 switch (SetCCOpcode) {
2600 default: llvm_unreachable("Condcode should be pre-legalized away");
2602 case ISD::SETEQ: return X86::COND_E;
2603 case ISD::SETOLT: // flipped
2605 case ISD::SETGT: return X86::COND_A;
2606 case ISD::SETOLE: // flipped
2608 case ISD::SETGE: return X86::COND_AE;
2609 case ISD::SETUGT: // flipped
2611 case ISD::SETLT: return X86::COND_B;
2612 case ISD::SETUGE: // flipped
2614 case ISD::SETLE: return X86::COND_BE;
2616 case ISD::SETNE: return X86::COND_NE;
2617 case ISD::SETUO: return X86::COND_P;
2618 case ISD::SETO: return X86::COND_NP;
2620 case ISD::SETUNE: return X86::COND_INVALID;
2624 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2625 /// code. Current x86 isa includes the following FP cmov instructions:
2626 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2627 static bool hasFPCMov(unsigned X86CC) {
2643 /// isFPImmLegal - Returns true if the target can instruction select the
2644 /// specified FP immediate natively. If false, the legalizer will
2645 /// materialize the FP immediate as a load from a constant pool.
2646 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2647 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2648 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2654 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2655 /// the specified range (L, H].
2656 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2657 return (Val < 0) || (Val >= Low && Val < Hi);
2660 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2661 /// specified value.
2662 static bool isUndefOrEqual(int Val, int CmpVal) {
2663 if (Val < 0 || Val == CmpVal)
2668 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2669 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2670 /// the second operand.
2671 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2672 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2673 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2674 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2675 return (Mask[0] < 2 && Mask[1] < 2);
2679 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2680 SmallVector<int, 8> M;
2682 return ::isPSHUFDMask(M, N->getValueType(0));
2685 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2686 /// is suitable for input to PSHUFHW.
2687 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2688 if (VT != MVT::v8i16)
2691 // Lower quadword copied in order or undef.
2692 for (int i = 0; i != 4; ++i)
2693 if (Mask[i] >= 0 && Mask[i] != i)
2696 // Upper quadword shuffled.
2697 for (int i = 4; i != 8; ++i)
2698 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2704 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2705 SmallVector<int, 8> M;
2707 return ::isPSHUFHWMask(M, N->getValueType(0));
2710 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2711 /// is suitable for input to PSHUFLW.
2712 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2713 if (VT != MVT::v8i16)
2716 // Upper quadword copied in order.
2717 for (int i = 4; i != 8; ++i)
2718 if (Mask[i] >= 0 && Mask[i] != i)
2721 // Lower quadword shuffled.
2722 for (int i = 0; i != 4; ++i)
2729 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2730 SmallVector<int, 8> M;
2732 return ::isPSHUFLWMask(M, N->getValueType(0));
2735 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2736 /// is suitable for input to PALIGNR.
2737 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2739 int i, e = VT.getVectorNumElements();
2741 // Do not handle v2i64 / v2f64 shuffles with palignr.
2742 if (e < 4 || !hasSSSE3)
2745 for (i = 0; i != e; ++i)
2749 // All undef, not a palignr.
2753 // Determine if it's ok to perform a palignr with only the LHS, since we
2754 // don't have access to the actual shuffle elements to see if RHS is undef.
2755 bool Unary = Mask[i] < (int)e;
2756 bool NeedsUnary = false;
2758 int s = Mask[i] - i;
2760 // Check the rest of the elements to see if they are consecutive.
2761 for (++i; i != e; ++i) {
2766 Unary = Unary && (m < (int)e);
2767 NeedsUnary = NeedsUnary || (m < s);
2769 if (NeedsUnary && !Unary)
2771 if (Unary && m != ((s+i) & (e-1)))
2773 if (!Unary && m != (s+i))
2779 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2780 SmallVector<int, 8> M;
2782 return ::isPALIGNRMask(M, N->getValueType(0), true);
2785 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2786 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2787 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2788 int NumElems = VT.getVectorNumElements();
2789 if (NumElems != 2 && NumElems != 4)
2792 int Half = NumElems / 2;
2793 for (int i = 0; i < Half; ++i)
2794 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2796 for (int i = Half; i < NumElems; ++i)
2797 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2803 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2804 SmallVector<int, 8> M;
2806 return ::isSHUFPMask(M, N->getValueType(0));
2809 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2810 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2811 /// half elements to come from vector 1 (which would equal the dest.) and
2812 /// the upper half to come from vector 2.
2813 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2814 int NumElems = VT.getVectorNumElements();
2816 if (NumElems != 2 && NumElems != 4)
2819 int Half = NumElems / 2;
2820 for (int i = 0; i < Half; ++i)
2821 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2823 for (int i = Half; i < NumElems; ++i)
2824 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2829 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2830 SmallVector<int, 8> M;
2832 return isCommutedSHUFPMask(M, N->getValueType(0));
2835 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2836 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2837 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2838 if (N->getValueType(0).getVectorNumElements() != 4)
2841 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2842 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2843 isUndefOrEqual(N->getMaskElt(1), 7) &&
2844 isUndefOrEqual(N->getMaskElt(2), 2) &&
2845 isUndefOrEqual(N->getMaskElt(3), 3);
2848 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2849 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2851 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2852 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2857 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2858 isUndefOrEqual(N->getMaskElt(1), 3) &&
2859 isUndefOrEqual(N->getMaskElt(2), 2) &&
2860 isUndefOrEqual(N->getMaskElt(3), 3);
2863 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2864 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2865 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2866 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2868 if (NumElems != 2 && NumElems != 4)
2871 for (unsigned i = 0; i < NumElems/2; ++i)
2872 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2875 for (unsigned i = NumElems/2; i < NumElems; ++i)
2876 if (!isUndefOrEqual(N->getMaskElt(i), i))
2882 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2883 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2884 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2885 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2887 if (NumElems != 2 && NumElems != 4)
2890 for (unsigned i = 0; i < NumElems/2; ++i)
2891 if (!isUndefOrEqual(N->getMaskElt(i), i))
2894 for (unsigned i = 0; i < NumElems/2; ++i)
2895 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2901 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2902 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2903 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2904 bool V2IsSplat = false) {
2905 int NumElts = VT.getVectorNumElements();
2906 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2909 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2911 int BitI1 = Mask[i+1];
2912 if (!isUndefOrEqual(BitI, j))
2915 if (!isUndefOrEqual(BitI1, NumElts))
2918 if (!isUndefOrEqual(BitI1, j + NumElts))
2925 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2926 SmallVector<int, 8> M;
2928 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2931 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2932 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2933 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2934 bool V2IsSplat = false) {
2935 int NumElts = VT.getVectorNumElements();
2936 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2939 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2941 int BitI1 = Mask[i+1];
2942 if (!isUndefOrEqual(BitI, j + NumElts/2))
2945 if (isUndefOrEqual(BitI1, NumElts))
2948 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2955 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2956 SmallVector<int, 8> M;
2958 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2961 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2962 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2964 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2965 int NumElems = VT.getVectorNumElements();
2966 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2969 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2971 int BitI1 = Mask[i+1];
2972 if (!isUndefOrEqual(BitI, j))
2974 if (!isUndefOrEqual(BitI1, j))
2980 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2981 SmallVector<int, 8> M;
2983 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2986 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2987 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2989 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2990 int NumElems = VT.getVectorNumElements();
2991 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2994 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2996 int BitI1 = Mask[i+1];
2997 if (!isUndefOrEqual(BitI, j))
2999 if (!isUndefOrEqual(BitI1, j))
3005 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3006 SmallVector<int, 8> M;
3008 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3011 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3012 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3013 /// MOVSD, and MOVD, i.e. setting the lowest element.
3014 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3015 if (VT.getVectorElementType().getSizeInBits() < 32)
3018 int NumElts = VT.getVectorNumElements();
3020 if (!isUndefOrEqual(Mask[0], NumElts))
3023 for (int i = 1; i < NumElts; ++i)
3024 if (!isUndefOrEqual(Mask[i], i))
3030 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3031 SmallVector<int, 8> M;
3033 return ::isMOVLMask(M, N->getValueType(0));
3036 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3037 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3038 /// element of vector 2 and the other elements to come from vector 1 in order.
3039 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3040 bool V2IsSplat = false, bool V2IsUndef = false) {
3041 int NumOps = VT.getVectorNumElements();
3042 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3045 if (!isUndefOrEqual(Mask[0], 0))
3048 for (int i = 1; i < NumOps; ++i)
3049 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3050 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3051 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3057 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3058 bool V2IsUndef = false) {
3059 SmallVector<int, 8> M;
3061 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3064 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3065 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3066 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3067 if (N->getValueType(0).getVectorNumElements() != 4)
3070 // Expect 1, 1, 3, 3
3071 for (unsigned i = 0; i < 2; ++i) {
3072 int Elt = N->getMaskElt(i);
3073 if (Elt >= 0 && Elt != 1)
3078 for (unsigned i = 2; i < 4; ++i) {
3079 int Elt = N->getMaskElt(i);
3080 if (Elt >= 0 && Elt != 3)
3085 // Don't use movshdup if it can be done with a shufps.
3086 // FIXME: verify that matching u, u, 3, 3 is what we want.
3090 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3091 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3092 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3093 if (N->getValueType(0).getVectorNumElements() != 4)
3096 // Expect 0, 0, 2, 2
3097 for (unsigned i = 0; i < 2; ++i)
3098 if (N->getMaskElt(i) > 0)
3102 for (unsigned i = 2; i < 4; ++i) {
3103 int Elt = N->getMaskElt(i);
3104 if (Elt >= 0 && Elt != 2)
3109 // Don't use movsldup if it can be done with a shufps.
3113 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3114 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3115 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3116 int e = N->getValueType(0).getVectorNumElements() / 2;
3118 for (int i = 0; i < e; ++i)
3119 if (!isUndefOrEqual(N->getMaskElt(i), i))
3121 for (int i = 0; i < e; ++i)
3122 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3127 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3128 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3129 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3130 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3131 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3133 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3135 for (int i = 0; i < NumOperands; ++i) {
3136 int Val = SVOp->getMaskElt(NumOperands-i-1);
3137 if (Val < 0) Val = 0;
3138 if (Val >= NumOperands) Val -= NumOperands;
3140 if (i != NumOperands - 1)
3146 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3147 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3148 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3149 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3151 // 8 nodes, but we only care about the last 4.
3152 for (unsigned i = 7; i >= 4; --i) {
3153 int Val = SVOp->getMaskElt(i);
3162 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3163 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3164 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3165 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3167 // 8 nodes, but we only care about the first 4.
3168 for (int i = 3; i >= 0; --i) {
3169 int Val = SVOp->getMaskElt(i);
3178 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3179 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3180 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3181 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3182 EVT VVT = N->getValueType(0);
3183 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3187 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3188 Val = SVOp->getMaskElt(i);
3192 return (Val - i) * EltSize;
3195 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3197 bool X86::isZeroNode(SDValue Elt) {
3198 return ((isa<ConstantSDNode>(Elt) &&
3199 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3200 (isa<ConstantFPSDNode>(Elt) &&
3201 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3204 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3205 /// their permute mask.
3206 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3207 SelectionDAG &DAG) {
3208 EVT VT = SVOp->getValueType(0);
3209 unsigned NumElems = VT.getVectorNumElements();
3210 SmallVector<int, 8> MaskVec;
3212 for (unsigned i = 0; i != NumElems; ++i) {
3213 int idx = SVOp->getMaskElt(i);
3215 MaskVec.push_back(idx);
3216 else if (idx < (int)NumElems)
3217 MaskVec.push_back(idx + NumElems);
3219 MaskVec.push_back(idx - NumElems);
3221 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3222 SVOp->getOperand(0), &MaskVec[0]);
3225 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3226 /// the two vector operands have swapped position.
3227 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3228 unsigned NumElems = VT.getVectorNumElements();
3229 for (unsigned i = 0; i != NumElems; ++i) {
3233 else if (idx < (int)NumElems)
3234 Mask[i] = idx + NumElems;
3236 Mask[i] = idx - NumElems;
3240 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3241 /// match movhlps. The lower half elements should come from upper half of
3242 /// V1 (and in order), and the upper half elements should come from the upper
3243 /// half of V2 (and in order).
3244 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3245 if (Op->getValueType(0).getVectorNumElements() != 4)
3247 for (unsigned i = 0, e = 2; i != e; ++i)
3248 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3250 for (unsigned i = 2; i != 4; ++i)
3251 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3256 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3257 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3259 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3260 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3262 N = N->getOperand(0).getNode();
3263 if (!ISD::isNON_EXTLoad(N))
3266 *LD = cast<LoadSDNode>(N);
3270 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3271 /// match movlp{s|d}. The lower half elements should come from lower half of
3272 /// V1 (and in order), and the upper half elements should come from the upper
3273 /// half of V2 (and in order). And since V1 will become the source of the
3274 /// MOVLP, it must be either a vector load or a scalar load to vector.
3275 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3276 ShuffleVectorSDNode *Op) {
3277 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3279 // Is V2 is a vector load, don't do this transformation. We will try to use
3280 // load folding shufps op.
3281 if (ISD::isNON_EXTLoad(V2))
3284 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3286 if (NumElems != 2 && NumElems != 4)
3288 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3289 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3291 for (unsigned i = NumElems/2; i != NumElems; ++i)
3292 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3297 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3299 static bool isSplatVector(SDNode *N) {
3300 if (N->getOpcode() != ISD::BUILD_VECTOR)
3303 SDValue SplatValue = N->getOperand(0);
3304 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3305 if (N->getOperand(i) != SplatValue)
3310 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3311 /// to an zero vector.
3312 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3313 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3314 SDValue V1 = N->getOperand(0);
3315 SDValue V2 = N->getOperand(1);
3316 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3317 for (unsigned i = 0; i != NumElems; ++i) {
3318 int Idx = N->getMaskElt(i);
3319 if (Idx >= (int)NumElems) {
3320 unsigned Opc = V2.getOpcode();
3321 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3323 if (Opc != ISD::BUILD_VECTOR ||
3324 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3326 } else if (Idx >= 0) {
3327 unsigned Opc = V1.getOpcode();
3328 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3330 if (Opc != ISD::BUILD_VECTOR ||
3331 !X86::isZeroNode(V1.getOperand(Idx)))
3338 /// getZeroVector - Returns a vector of specified type with all zero elements.
3340 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3342 assert(VT.isVector() && "Expected a vector type");
3344 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3345 // type. This ensures they get CSE'd.
3347 if (VT.getSizeInBits() == 64) { // MMX
3348 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3349 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3350 } else if (HasSSE2) { // SSE2
3351 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3352 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3354 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3355 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3357 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3360 /// getOnesVector - Returns a vector of specified type with all bits set.
3362 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3363 assert(VT.isVector() && "Expected a vector type");
3365 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3366 // type. This ensures they get CSE'd.
3367 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3369 if (VT.getSizeInBits() == 64) // MMX
3370 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3372 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3373 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3377 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3378 /// that point to V2 points to its first element.
3379 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3380 EVT VT = SVOp->getValueType(0);
3381 unsigned NumElems = VT.getVectorNumElements();
3383 bool Changed = false;
3384 SmallVector<int, 8> MaskVec;
3385 SVOp->getMask(MaskVec);
3387 for (unsigned i = 0; i != NumElems; ++i) {
3388 if (MaskVec[i] > (int)NumElems) {
3389 MaskVec[i] = NumElems;
3394 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3395 SVOp->getOperand(1), &MaskVec[0]);
3396 return SDValue(SVOp, 0);
3399 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3400 /// operation of specified width.
3401 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3403 unsigned NumElems = VT.getVectorNumElements();
3404 SmallVector<int, 8> Mask;
3405 Mask.push_back(NumElems);
3406 for (unsigned i = 1; i != NumElems; ++i)
3408 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3411 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3412 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3414 unsigned NumElems = VT.getVectorNumElements();
3415 SmallVector<int, 8> Mask;
3416 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3418 Mask.push_back(i + NumElems);
3420 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3423 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3424 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3426 unsigned NumElems = VT.getVectorNumElements();
3427 unsigned Half = NumElems/2;
3428 SmallVector<int, 8> Mask;
3429 for (unsigned i = 0; i != Half; ++i) {
3430 Mask.push_back(i + Half);
3431 Mask.push_back(i + NumElems + Half);
3433 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3436 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3437 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3439 if (SV->getValueType(0).getVectorNumElements() <= 4)
3440 return SDValue(SV, 0);
3442 EVT PVT = MVT::v4f32;
3443 EVT VT = SV->getValueType(0);
3444 DebugLoc dl = SV->getDebugLoc();
3445 SDValue V1 = SV->getOperand(0);
3446 int NumElems = VT.getVectorNumElements();
3447 int EltNo = SV->getSplatIndex();
3449 // unpack elements to the correct location
3450 while (NumElems > 4) {
3451 if (EltNo < NumElems/2) {
3452 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3454 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3455 EltNo -= NumElems/2;
3460 // Perform the splat.
3461 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3462 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3463 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3464 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3467 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3468 /// vector of zero or undef vector. This produces a shuffle where the low
3469 /// element of V2 is swizzled into the zero/undef vector, landing at element
3470 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3471 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3472 bool isZero, bool HasSSE2,
3473 SelectionDAG &DAG) {
3474 EVT VT = V2.getValueType();
3476 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3477 unsigned NumElems = VT.getVectorNumElements();
3478 SmallVector<int, 16> MaskVec;
3479 for (unsigned i = 0; i != NumElems; ++i)
3480 // If this is the insertion idx, put the low elt of V2 here.
3481 MaskVec.push_back(i == Idx ? NumElems : i);
3482 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3485 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3486 /// a shuffle that is zero.
3488 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3489 bool Low, SelectionDAG &DAG) {
3490 unsigned NumZeros = 0;
3491 for (int i = 0; i < NumElems; ++i) {
3492 unsigned Index = Low ? i : NumElems-i-1;
3493 int Idx = SVOp->getMaskElt(Index);
3498 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3499 if (Elt.getNode() && X86::isZeroNode(Elt))
3507 /// isVectorShift - Returns true if the shuffle can be implemented as a
3508 /// logical left or right shift of a vector.
3509 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3510 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3511 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3512 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3515 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3518 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3522 bool SeenV1 = false;
3523 bool SeenV2 = false;
3524 for (unsigned i = NumZeros; i < NumElems; ++i) {
3525 unsigned Val = isLeft ? (i - NumZeros) : i;
3526 int Idx_ = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3529 unsigned Idx = (unsigned) Idx_;
3539 if (SeenV1 && SeenV2)
3542 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3548 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3550 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3551 unsigned NumNonZero, unsigned NumZero,
3553 const TargetLowering &TLI) {
3557 DebugLoc dl = Op.getDebugLoc();
3560 for (unsigned i = 0; i < 16; ++i) {
3561 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3562 if (ThisIsNonZero && First) {
3564 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3566 V = DAG.getUNDEF(MVT::v8i16);
3571 SDValue ThisElt(0, 0), LastElt(0, 0);
3572 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3573 if (LastIsNonZero) {
3574 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3575 MVT::i16, Op.getOperand(i-1));
3577 if (ThisIsNonZero) {
3578 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3579 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3580 ThisElt, DAG.getConstant(8, MVT::i8));
3582 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3586 if (ThisElt.getNode())
3587 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3588 DAG.getIntPtrConstant(i/2));
3592 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3595 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3597 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3598 unsigned NumNonZero, unsigned NumZero,
3600 const TargetLowering &TLI) {
3604 DebugLoc dl = Op.getDebugLoc();
3607 for (unsigned i = 0; i < 8; ++i) {
3608 bool isNonZero = (NonZeros & (1 << i)) != 0;
3612 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3614 V = DAG.getUNDEF(MVT::v8i16);
3617 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3618 MVT::v8i16, V, Op.getOperand(i),
3619 DAG.getIntPtrConstant(i));
3626 /// getVShift - Return a vector logical shift node.
3628 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3629 unsigned NumBits, SelectionDAG &DAG,
3630 const TargetLowering &TLI, DebugLoc dl) {
3631 bool isMMX = VT.getSizeInBits() == 64;
3632 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3633 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3634 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3635 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3636 DAG.getNode(Opc, dl, ShVT, SrcOp,
3637 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3641 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3642 SelectionDAG &DAG) const {
3644 // Check if the scalar load can be widened into a vector load. And if
3645 // the address is "base + cst" see if the cst can be "absorbed" into
3646 // the shuffle mask.
3647 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3648 SDValue Ptr = LD->getBasePtr();
3649 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3651 EVT PVT = LD->getValueType(0);
3652 if (PVT != MVT::i32 && PVT != MVT::f32)
3657 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3658 FI = FINode->getIndex();
3660 } else if (Ptr.getOpcode() == ISD::ADD &&
3661 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3662 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3663 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3664 Offset = Ptr.getConstantOperandVal(1);
3665 Ptr = Ptr.getOperand(0);
3670 SDValue Chain = LD->getChain();
3671 // Make sure the stack object alignment is at least 16.
3672 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3673 if (DAG.InferPtrAlignment(Ptr) < 16) {
3674 if (MFI->isFixedObjectIndex(FI)) {
3675 // Can't change the alignment. FIXME: It's possible to compute
3676 // the exact stack offset and reference FI + adjust offset instead.
3677 // If someone *really* cares about this. That's the way to implement it.
3680 MFI->setObjectAlignment(FI, 16);
3684 // (Offset % 16) must be multiple of 4. Then address is then
3685 // Ptr + (Offset & ~15).
3688 if ((Offset % 16) & 3)
3690 int64_t StartOffset = Offset & ~15;
3692 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3693 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3695 int EltNo = (Offset - StartOffset) >> 2;
3696 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3697 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3698 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3700 // Canonicalize it to a v4i32 shuffle.
3701 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3702 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3703 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3704 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3710 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
3711 /// vector of type 'VT', see if the elements can be replaced by a single large
3712 /// load which has the same value as a build_vector whose operands are 'elts'.
3714 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
3716 /// FIXME: we'd also like to handle the case where the last elements are zero
3717 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
3718 /// There's even a handy isZeroNode for that purpose.
3719 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
3720 DebugLoc &dl, SelectionDAG &DAG) {
3721 EVT EltVT = VT.getVectorElementType();
3722 unsigned NumElems = Elts.size();
3724 LoadSDNode *LDBase = NULL;
3725 unsigned LastLoadedElt = -1U;
3727 // For each element in the initializer, see if we've found a load or an undef.
3728 // If we don't find an initial load element, or later load elements are
3729 // non-consecutive, bail out.
3730 for (unsigned i = 0; i < NumElems; ++i) {
3731 SDValue Elt = Elts[i];
3733 if (!Elt.getNode() ||
3734 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
3737 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
3739 LDBase = cast<LoadSDNode>(Elt.getNode());
3743 if (Elt.getOpcode() == ISD::UNDEF)
3746 LoadSDNode *LD = cast<LoadSDNode>(Elt);
3747 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
3752 // If we have found an entire vector of loads and undefs, then return a large
3753 // load of the entire vector width starting at the base pointer. If we found
3754 // consecutive loads for the low half, generate a vzext_load node.
3755 if (LastLoadedElt == NumElems - 1) {
3756 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
3757 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3758 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3759 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
3760 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
3761 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
3762 LDBase->isVolatile(), LDBase->isNonTemporal(),
3763 LDBase->getAlignment());
3764 } else if (NumElems == 4 && LastLoadedElt == 1) {
3765 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
3766 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
3767 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
3768 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
3774 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
3775 DebugLoc dl = Op.getDebugLoc();
3776 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3777 if (ISD::isBuildVectorAllZeros(Op.getNode())
3778 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3779 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3780 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3781 // eliminated on x86-32 hosts.
3782 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3785 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3786 return getOnesVector(Op.getValueType(), DAG, dl);
3787 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3790 EVT VT = Op.getValueType();
3791 EVT ExtVT = VT.getVectorElementType();
3792 unsigned EVTBits = ExtVT.getSizeInBits();
3794 unsigned NumElems = Op.getNumOperands();
3795 unsigned NumZero = 0;
3796 unsigned NumNonZero = 0;
3797 unsigned NonZeros = 0;
3798 bool IsAllConstants = true;
3799 SmallSet<SDValue, 8> Values;
3800 for (unsigned i = 0; i < NumElems; ++i) {
3801 SDValue Elt = Op.getOperand(i);
3802 if (Elt.getOpcode() == ISD::UNDEF)
3805 if (Elt.getOpcode() != ISD::Constant &&
3806 Elt.getOpcode() != ISD::ConstantFP)
3807 IsAllConstants = false;
3808 if (X86::isZeroNode(Elt))
3811 NonZeros |= (1 << i);
3816 if (NumNonZero == 0) {
3817 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3818 return DAG.getUNDEF(VT);
3821 // Special case for single non-zero, non-undef, element.
3822 if (NumNonZero == 1) {
3823 unsigned Idx = CountTrailingZeros_32(NonZeros);
3824 SDValue Item = Op.getOperand(Idx);
3826 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3827 // the value are obviously zero, truncate the value to i32 and do the
3828 // insertion that way. Only do this if the value is non-constant or if the
3829 // value is a constant being inserted into element 0. It is cheaper to do
3830 // a constant pool load than it is to do a movd + shuffle.
3831 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3832 (!IsAllConstants || Idx == 0)) {
3833 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3834 // Handle MMX and SSE both.
3835 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3836 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3838 // Truncate the value (which may itself be a constant) to i32, and
3839 // convert it to a vector with movd (S2V+shuffle to zero extend).
3840 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3841 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3842 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3843 Subtarget->hasSSE2(), DAG);
3845 // Now we have our 32-bit value zero extended in the low element of
3846 // a vector. If Idx != 0, swizzle it into place.
3848 SmallVector<int, 4> Mask;
3849 Mask.push_back(Idx);
3850 for (unsigned i = 1; i != VecElts; ++i)
3852 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3853 DAG.getUNDEF(Item.getValueType()),
3856 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3860 // If we have a constant or non-constant insertion into the low element of
3861 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3862 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3863 // depending on what the source datatype is.
3866 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3867 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3868 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3869 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3870 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3871 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3873 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3874 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3875 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3876 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3877 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3878 Subtarget->hasSSE2(), DAG);
3879 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3883 // Is it a vector logical left shift?
3884 if (NumElems == 2 && Idx == 1 &&
3885 X86::isZeroNode(Op.getOperand(0)) &&
3886 !X86::isZeroNode(Op.getOperand(1))) {
3887 unsigned NumBits = VT.getSizeInBits();
3888 return getVShift(true, VT,
3889 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3890 VT, Op.getOperand(1)),
3891 NumBits/2, DAG, *this, dl);
3894 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3897 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3898 // is a non-constant being inserted into an element other than the low one,
3899 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3900 // movd/movss) to move this into the low element, then shuffle it into
3902 if (EVTBits == 32) {
3903 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3905 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3906 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3907 Subtarget->hasSSE2(), DAG);
3908 SmallVector<int, 8> MaskVec;
3909 for (unsigned i = 0; i < NumElems; i++)
3910 MaskVec.push_back(i == Idx ? 0 : 1);
3911 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3915 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3916 if (Values.size() == 1) {
3917 if (EVTBits == 32) {
3918 // Instead of a shuffle like this:
3919 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3920 // Check if it's possible to issue this instead.
3921 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3922 unsigned Idx = CountTrailingZeros_32(NonZeros);
3923 SDValue Item = Op.getOperand(Idx);
3924 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3925 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3930 // A vector full of immediates; various special cases are already
3931 // handled, so this is best done with a single constant-pool load.
3935 // Let legalizer expand 2-wide build_vectors.
3936 if (EVTBits == 64) {
3937 if (NumNonZero == 1) {
3938 // One half is zero or undef.
3939 unsigned Idx = CountTrailingZeros_32(NonZeros);
3940 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3941 Op.getOperand(Idx));
3942 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3943 Subtarget->hasSSE2(), DAG);
3948 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3949 if (EVTBits == 8 && NumElems == 16) {
3950 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3952 if (V.getNode()) return V;
3955 if (EVTBits == 16 && NumElems == 8) {
3956 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3958 if (V.getNode()) return V;
3961 // If element VT is == 32 bits, turn it into a number of shuffles.
3962 SmallVector<SDValue, 8> V;
3964 if (NumElems == 4 && NumZero > 0) {
3965 for (unsigned i = 0; i < 4; ++i) {
3966 bool isZero = !(NonZeros & (1 << i));
3968 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3970 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3973 for (unsigned i = 0; i < 2; ++i) {
3974 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3977 V[i] = V[i*2]; // Must be a zero vector.
3980 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3983 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3986 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3991 SmallVector<int, 8> MaskVec;
3992 bool Reverse = (NonZeros & 0x3) == 2;
3993 for (unsigned i = 0; i < 2; ++i)
3994 MaskVec.push_back(Reverse ? 1-i : i);
3995 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3996 for (unsigned i = 0; i < 2; ++i)
3997 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3998 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4001 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4002 // Check for a build vector of consecutive loads.
4003 for (unsigned i = 0; i < NumElems; ++i)
4004 V[i] = Op.getOperand(i);
4006 // Check for elements which are consecutive loads.
4007 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4011 // For SSE 4.1, use inserts into undef.
4012 if (getSubtarget()->hasSSE41()) {
4013 V[0] = DAG.getUNDEF(VT);
4014 for (unsigned i = 0; i < NumElems; ++i)
4015 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4016 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
4017 Op.getOperand(i), DAG.getIntPtrConstant(i));
4021 // Otherwise, expand into a number of unpckl*
4023 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4024 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4025 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4026 for (unsigned i = 0; i < NumElems; ++i)
4027 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4029 while (NumElems != 0) {
4030 for (unsigned i = 0; i < NumElems; ++i)
4031 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
4040 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4041 // We support concatenate two MMX registers and place them in a MMX
4042 // register. This is better than doing a stack convert.
4043 DebugLoc dl = Op.getDebugLoc();
4044 EVT ResVT = Op.getValueType();
4045 assert(Op.getNumOperands() == 2);
4046 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4047 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4049 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4050 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4051 InVec = Op.getOperand(1);
4052 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4053 unsigned NumElts = ResVT.getVectorNumElements();
4054 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4055 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4056 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4058 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4059 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4060 Mask[0] = 0; Mask[1] = 2;
4061 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4063 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4066 // v8i16 shuffles - Prefer shuffles in the following order:
4067 // 1. [all] pshuflw, pshufhw, optional move
4068 // 2. [ssse3] 1 x pshufb
4069 // 3. [ssse3] 2 x pshufb + 1 x por
4070 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4072 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
4074 const X86TargetLowering &TLI) {
4075 SDValue V1 = SVOp->getOperand(0);
4076 SDValue V2 = SVOp->getOperand(1);
4077 DebugLoc dl = SVOp->getDebugLoc();
4078 SmallVector<int, 8> MaskVals;
4080 // Determine if more than 1 of the words in each of the low and high quadwords
4081 // of the result come from the same quadword of one of the two inputs. Undef
4082 // mask values count as coming from any quadword, for better codegen.
4083 SmallVector<unsigned, 4> LoQuad(4);
4084 SmallVector<unsigned, 4> HiQuad(4);
4085 BitVector InputQuads(4);
4086 for (unsigned i = 0; i < 8; ++i) {
4087 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4088 int EltIdx = SVOp->getMaskElt(i);
4089 MaskVals.push_back(EltIdx);
4098 InputQuads.set(EltIdx / 4);
4101 int BestLoQuad = -1;
4102 unsigned MaxQuad = 1;
4103 for (unsigned i = 0; i < 4; ++i) {
4104 if (LoQuad[i] > MaxQuad) {
4106 MaxQuad = LoQuad[i];
4110 int BestHiQuad = -1;
4112 for (unsigned i = 0; i < 4; ++i) {
4113 if (HiQuad[i] > MaxQuad) {
4115 MaxQuad = HiQuad[i];
4119 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4120 // of the two input vectors, shuffle them into one input vector so only a
4121 // single pshufb instruction is necessary. If There are more than 2 input
4122 // quads, disable the next transformation since it does not help SSSE3.
4123 bool V1Used = InputQuads[0] || InputQuads[1];
4124 bool V2Used = InputQuads[2] || InputQuads[3];
4125 if (TLI.getSubtarget()->hasSSSE3()) {
4126 if (InputQuads.count() == 2 && V1Used && V2Used) {
4127 BestLoQuad = InputQuads.find_first();
4128 BestHiQuad = InputQuads.find_next(BestLoQuad);
4130 if (InputQuads.count() > 2) {
4136 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4137 // the shuffle mask. If a quad is scored as -1, that means that it contains
4138 // words from all 4 input quadwords.
4140 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4141 SmallVector<int, 8> MaskV;
4142 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4143 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4144 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4145 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4146 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4147 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4149 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4150 // source words for the shuffle, to aid later transformations.
4151 bool AllWordsInNewV = true;
4152 bool InOrder[2] = { true, true };
4153 for (unsigned i = 0; i != 8; ++i) {
4154 int idx = MaskVals[i];
4156 InOrder[i/4] = false;
4157 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4159 AllWordsInNewV = false;
4163 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4164 if (AllWordsInNewV) {
4165 for (int i = 0; i != 8; ++i) {
4166 int idx = MaskVals[i];
4169 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4170 if ((idx != i) && idx < 4)
4172 if ((idx != i) && idx > 3)
4181 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4182 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4183 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4184 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4185 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4189 // If we have SSSE3, and all words of the result are from 1 input vector,
4190 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4191 // is present, fall back to case 4.
4192 if (TLI.getSubtarget()->hasSSSE3()) {
4193 SmallVector<SDValue,16> pshufbMask;
4195 // If we have elements from both input vectors, set the high bit of the
4196 // shuffle mask element to zero out elements that come from V2 in the V1
4197 // mask, and elements that come from V1 in the V2 mask, so that the two
4198 // results can be OR'd together.
4199 bool TwoInputs = V1Used && V2Used;
4200 for (unsigned i = 0; i != 8; ++i) {
4201 int EltIdx = MaskVals[i] * 2;
4202 if (TwoInputs && (EltIdx >= 16)) {
4203 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4204 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4207 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4208 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4210 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4211 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4212 DAG.getNode(ISD::BUILD_VECTOR, dl,
4213 MVT::v16i8, &pshufbMask[0], 16));
4215 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4217 // Calculate the shuffle mask for the second input, shuffle it, and
4218 // OR it with the first shuffled input.
4220 for (unsigned i = 0; i != 8; ++i) {
4221 int EltIdx = MaskVals[i] * 2;
4223 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4224 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4227 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4228 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4230 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4231 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4232 DAG.getNode(ISD::BUILD_VECTOR, dl,
4233 MVT::v16i8, &pshufbMask[0], 16));
4234 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4235 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4238 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4239 // and update MaskVals with new element order.
4240 BitVector InOrder(8);
4241 if (BestLoQuad >= 0) {
4242 SmallVector<int, 8> MaskV;
4243 for (int i = 0; i != 4; ++i) {
4244 int idx = MaskVals[i];
4246 MaskV.push_back(-1);
4248 } else if ((idx / 4) == BestLoQuad) {
4249 MaskV.push_back(idx & 3);
4252 MaskV.push_back(-1);
4255 for (unsigned i = 4; i != 8; ++i)
4257 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4261 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4262 // and update MaskVals with the new element order.
4263 if (BestHiQuad >= 0) {
4264 SmallVector<int, 8> MaskV;
4265 for (unsigned i = 0; i != 4; ++i)
4267 for (unsigned i = 4; i != 8; ++i) {
4268 int idx = MaskVals[i];
4270 MaskV.push_back(-1);
4272 } else if ((idx / 4) == BestHiQuad) {
4273 MaskV.push_back((idx & 3) + 4);
4276 MaskV.push_back(-1);
4279 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4283 // In case BestHi & BestLo were both -1, which means each quadword has a word
4284 // from each of the four input quadwords, calculate the InOrder bitvector now
4285 // before falling through to the insert/extract cleanup.
4286 if (BestLoQuad == -1 && BestHiQuad == -1) {
4288 for (int i = 0; i != 8; ++i)
4289 if (MaskVals[i] < 0 || MaskVals[i] == i)
4293 // The other elements are put in the right place using pextrw and pinsrw.
4294 for (unsigned i = 0; i != 8; ++i) {
4297 int EltIdx = MaskVals[i];
4300 SDValue ExtOp = (EltIdx < 8)
4301 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4302 DAG.getIntPtrConstant(EltIdx))
4303 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4304 DAG.getIntPtrConstant(EltIdx - 8));
4305 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4306 DAG.getIntPtrConstant(i));
4311 // v16i8 shuffles - Prefer shuffles in the following order:
4312 // 1. [ssse3] 1 x pshufb
4313 // 2. [ssse3] 2 x pshufb + 1 x por
4314 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4316 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4318 const X86TargetLowering &TLI) {
4319 SDValue V1 = SVOp->getOperand(0);
4320 SDValue V2 = SVOp->getOperand(1);
4321 DebugLoc dl = SVOp->getDebugLoc();
4322 SmallVector<int, 16> MaskVals;
4323 SVOp->getMask(MaskVals);
4325 // If we have SSSE3, case 1 is generated when all result bytes come from
4326 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4327 // present, fall back to case 3.
4328 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4331 for (unsigned i = 0; i < 16; ++i) {
4332 int EltIdx = MaskVals[i];
4341 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4342 if (TLI.getSubtarget()->hasSSSE3()) {
4343 SmallVector<SDValue,16> pshufbMask;
4345 // If all result elements are from one input vector, then only translate
4346 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4348 // Otherwise, we have elements from both input vectors, and must zero out
4349 // elements that come from V2 in the first mask, and V1 in the second mask
4350 // so that we can OR them together.
4351 bool TwoInputs = !(V1Only || V2Only);
4352 for (unsigned i = 0; i != 16; ++i) {
4353 int EltIdx = MaskVals[i];
4354 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4355 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4358 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4360 // If all the elements are from V2, assign it to V1 and return after
4361 // building the first pshufb.
4364 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4365 DAG.getNode(ISD::BUILD_VECTOR, dl,
4366 MVT::v16i8, &pshufbMask[0], 16));
4370 // Calculate the shuffle mask for the second input, shuffle it, and
4371 // OR it with the first shuffled input.
4373 for (unsigned i = 0; i != 16; ++i) {
4374 int EltIdx = MaskVals[i];
4376 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4379 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4381 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4382 DAG.getNode(ISD::BUILD_VECTOR, dl,
4383 MVT::v16i8, &pshufbMask[0], 16));
4384 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4387 // No SSSE3 - Calculate in place words and then fix all out of place words
4388 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4389 // the 16 different words that comprise the two doublequadword input vectors.
4390 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4391 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4392 SDValue NewV = V2Only ? V2 : V1;
4393 for (int i = 0; i != 8; ++i) {
4394 int Elt0 = MaskVals[i*2];
4395 int Elt1 = MaskVals[i*2+1];
4397 // This word of the result is all undef, skip it.
4398 if (Elt0 < 0 && Elt1 < 0)
4401 // This word of the result is already in the correct place, skip it.
4402 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4404 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4407 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4408 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4411 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4412 // using a single extract together, load it and store it.
4413 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4414 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4415 DAG.getIntPtrConstant(Elt1 / 2));
4416 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4417 DAG.getIntPtrConstant(i));
4421 // If Elt1 is defined, extract it from the appropriate source. If the
4422 // source byte is not also odd, shift the extracted word left 8 bits
4423 // otherwise clear the bottom 8 bits if we need to do an or.
4425 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4426 DAG.getIntPtrConstant(Elt1 / 2));
4427 if ((Elt1 & 1) == 0)
4428 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4429 DAG.getConstant(8, TLI.getShiftAmountTy()));
4431 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4432 DAG.getConstant(0xFF00, MVT::i16));
4434 // If Elt0 is defined, extract it from the appropriate source. If the
4435 // source byte is not also even, shift the extracted word right 8 bits. If
4436 // Elt1 was also defined, OR the extracted values together before
4437 // inserting them in the result.
4439 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4440 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4441 if ((Elt0 & 1) != 0)
4442 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4443 DAG.getConstant(8, TLI.getShiftAmountTy()));
4445 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4446 DAG.getConstant(0x00FF, MVT::i16));
4447 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4450 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4451 DAG.getIntPtrConstant(i));
4453 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4456 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4457 /// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be
4458 /// done when every pair / quad of shuffle mask elements point to elements in
4459 /// the right sequence. e.g.
4460 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4462 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4464 const TargetLowering &TLI, DebugLoc dl) {
4465 EVT VT = SVOp->getValueType(0);
4466 SDValue V1 = SVOp->getOperand(0);
4467 SDValue V2 = SVOp->getOperand(1);
4468 unsigned NumElems = VT.getVectorNumElements();
4469 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4470 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4472 switch (VT.getSimpleVT().SimpleTy) {
4473 default: assert(false && "Unexpected!");
4474 case MVT::v4f32: NewVT = MVT::v2f64; break;
4475 case MVT::v4i32: NewVT = MVT::v2i64; break;
4476 case MVT::v8i16: NewVT = MVT::v4i32; break;
4477 case MVT::v16i8: NewVT = MVT::v4i32; break;
4480 if (NewWidth == 2) {
4486 int Scale = NumElems / NewWidth;
4487 SmallVector<int, 8> MaskVec;
4488 for (unsigned i = 0; i < NumElems; i += Scale) {
4490 for (int j = 0; j < Scale; ++j) {
4491 int EltIdx = SVOp->getMaskElt(i+j);
4495 StartIdx = EltIdx - (EltIdx % Scale);
4496 if (EltIdx != StartIdx + j)
4500 MaskVec.push_back(-1);
4502 MaskVec.push_back(StartIdx / Scale);
4505 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4506 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4507 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4510 /// getVZextMovL - Return a zero-extending vector move low node.
4512 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4513 SDValue SrcOp, SelectionDAG &DAG,
4514 const X86Subtarget *Subtarget, DebugLoc dl) {
4515 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4516 LoadSDNode *LD = NULL;
4517 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4518 LD = dyn_cast<LoadSDNode>(SrcOp);
4520 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4522 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4523 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4524 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4525 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4526 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4528 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4529 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4530 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4531 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4539 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4540 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4541 DAG.getNode(ISD::BIT_CONVERT, dl,
4545 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4548 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4549 SDValue V1 = SVOp->getOperand(0);
4550 SDValue V2 = SVOp->getOperand(1);
4551 DebugLoc dl = SVOp->getDebugLoc();
4552 EVT VT = SVOp->getValueType(0);
4554 SmallVector<std::pair<int, int>, 8> Locs;
4556 SmallVector<int, 8> Mask1(4U, -1);
4557 SmallVector<int, 8> PermMask;
4558 SVOp->getMask(PermMask);
4562 for (unsigned i = 0; i != 4; ++i) {
4563 int Idx = PermMask[i];
4565 Locs[i] = std::make_pair(-1, -1);
4567 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4569 Locs[i] = std::make_pair(0, NumLo);
4573 Locs[i] = std::make_pair(1, NumHi);
4575 Mask1[2+NumHi] = Idx;
4581 if (NumLo <= 2 && NumHi <= 2) {
4582 // If no more than two elements come from either vector. This can be
4583 // implemented with two shuffles. First shuffle gather the elements.
4584 // The second shuffle, which takes the first shuffle as both of its
4585 // vector operands, put the elements into the right order.
4586 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4588 SmallVector<int, 8> Mask2(4U, -1);
4590 for (unsigned i = 0; i != 4; ++i) {
4591 if (Locs[i].first == -1)
4594 unsigned Idx = (i < 2) ? 0 : 4;
4595 Idx += Locs[i].first * 2 + Locs[i].second;
4600 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4601 } else if (NumLo == 3 || NumHi == 3) {
4602 // Otherwise, we must have three elements from one vector, call it X, and
4603 // one element from the other, call it Y. First, use a shufps to build an
4604 // intermediate vector with the one element from Y and the element from X
4605 // that will be in the same half in the final destination (the indexes don't
4606 // matter). Then, use a shufps to build the final vector, taking the half
4607 // containing the element from Y from the intermediate, and the other half
4610 // Normalize it so the 3 elements come from V1.
4611 CommuteVectorShuffleMask(PermMask, VT);
4615 // Find the element from V2.
4617 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4618 int Val = PermMask[HiIndex];
4625 Mask1[0] = PermMask[HiIndex];
4627 Mask1[2] = PermMask[HiIndex^1];
4629 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4632 Mask1[0] = PermMask[0];
4633 Mask1[1] = PermMask[1];
4634 Mask1[2] = HiIndex & 1 ? 6 : 4;
4635 Mask1[3] = HiIndex & 1 ? 4 : 6;
4636 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4638 Mask1[0] = HiIndex & 1 ? 2 : 0;
4639 Mask1[1] = HiIndex & 1 ? 0 : 2;
4640 Mask1[2] = PermMask[2];
4641 Mask1[3] = PermMask[3];
4646 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4650 // Break it into (shuffle shuffle_hi, shuffle_lo).
4652 SmallVector<int,8> LoMask(4U, -1);
4653 SmallVector<int,8> HiMask(4U, -1);
4655 SmallVector<int,8> *MaskPtr = &LoMask;
4656 unsigned MaskIdx = 0;
4659 for (unsigned i = 0; i != 4; ++i) {
4666 int Idx = PermMask[i];
4668 Locs[i] = std::make_pair(-1, -1);
4669 } else if (Idx < 4) {
4670 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4671 (*MaskPtr)[LoIdx] = Idx;
4674 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4675 (*MaskPtr)[HiIdx] = Idx;
4680 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4681 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4682 SmallVector<int, 8> MaskOps;
4683 for (unsigned i = 0; i != 4; ++i) {
4684 if (Locs[i].first == -1) {
4685 MaskOps.push_back(-1);
4687 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4688 MaskOps.push_back(Idx);
4691 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4695 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
4696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4697 SDValue V1 = Op.getOperand(0);
4698 SDValue V2 = Op.getOperand(1);
4699 EVT VT = Op.getValueType();
4700 DebugLoc dl = Op.getDebugLoc();
4701 unsigned NumElems = VT.getVectorNumElements();
4702 bool isMMX = VT.getSizeInBits() == 64;
4703 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4704 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4705 bool V1IsSplat = false;
4706 bool V2IsSplat = false;
4708 if (isZeroShuffle(SVOp))
4709 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4711 // Promote splats to v4f32.
4712 if (SVOp->isSplat()) {
4713 if (isMMX || NumElems < 4)
4715 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4718 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4720 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4721 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4722 if (NewOp.getNode())
4723 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4724 LowerVECTOR_SHUFFLE(NewOp, DAG));
4725 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4726 // FIXME: Figure out a cleaner way to do this.
4727 // Try to make use of movq to zero out the top part.
4728 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4729 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4730 if (NewOp.getNode()) {
4731 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4732 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4733 DAG, Subtarget, dl);
4735 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4736 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4737 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4738 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4739 DAG, Subtarget, dl);
4743 if (X86::isPSHUFDMask(SVOp))
4746 // Check if this can be converted into a logical shift.
4747 bool isLeft = false;
4750 bool isShift = getSubtarget()->hasSSE2() &&
4751 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4752 if (isShift && ShVal.hasOneUse()) {
4753 // If the shifted value has multiple uses, it may be cheaper to use
4754 // v_set0 + movlhps or movhlps, etc.
4755 EVT EltVT = VT.getVectorElementType();
4756 ShAmt *= EltVT.getSizeInBits();
4757 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4760 if (X86::isMOVLMask(SVOp)) {
4763 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4764 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4769 // FIXME: fold these into legal mask.
4770 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4771 X86::isMOVSLDUPMask(SVOp) ||
4772 X86::isMOVHLPSMask(SVOp) ||
4773 X86::isMOVLHPSMask(SVOp) ||
4774 X86::isMOVLPMask(SVOp)))
4777 if (ShouldXformToMOVHLPS(SVOp) ||
4778 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4779 return CommuteVectorShuffle(SVOp, DAG);
4782 // No better options. Use a vshl / vsrl.
4783 EVT EltVT = VT.getVectorElementType();
4784 ShAmt *= EltVT.getSizeInBits();
4785 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4788 bool Commuted = false;
4789 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4790 // 1,1,1,1 -> v8i16 though.
4791 V1IsSplat = isSplatVector(V1.getNode());
4792 V2IsSplat = isSplatVector(V2.getNode());
4794 // Canonicalize the splat or undef, if present, to be on the RHS.
4795 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4796 Op = CommuteVectorShuffle(SVOp, DAG);
4797 SVOp = cast<ShuffleVectorSDNode>(Op);
4798 V1 = SVOp->getOperand(0);
4799 V2 = SVOp->getOperand(1);
4800 std::swap(V1IsSplat, V2IsSplat);
4801 std::swap(V1IsUndef, V2IsUndef);
4805 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4806 // Shuffling low element of v1 into undef, just return v1.
4809 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4810 // the instruction selector will not match, so get a canonical MOVL with
4811 // swapped operands to undo the commute.
4812 return getMOVL(DAG, dl, VT, V2, V1);
4815 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4816 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4817 X86::isUNPCKLMask(SVOp) ||
4818 X86::isUNPCKHMask(SVOp))
4822 // Normalize mask so all entries that point to V2 points to its first
4823 // element then try to match unpck{h|l} again. If match, return a
4824 // new vector_shuffle with the corrected mask.
4825 SDValue NewMask = NormalizeMask(SVOp, DAG);
4826 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4827 if (NSVOp != SVOp) {
4828 if (X86::isUNPCKLMask(NSVOp, true)) {
4830 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4837 // Commute is back and try unpck* again.
4838 // FIXME: this seems wrong.
4839 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4840 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4841 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4842 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4843 X86::isUNPCKLMask(NewSVOp) ||
4844 X86::isUNPCKHMask(NewSVOp))
4848 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4850 // Normalize the node to match x86 shuffle ops if needed
4851 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4852 return CommuteVectorShuffle(SVOp, DAG);
4854 // Check for legal shuffle and return?
4855 SmallVector<int, 16> PermMask;
4856 SVOp->getMask(PermMask);
4857 if (isShuffleMaskLegal(PermMask, VT))
4860 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4861 if (VT == MVT::v8i16) {
4862 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4863 if (NewOp.getNode())
4867 if (VT == MVT::v16i8) {
4868 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4869 if (NewOp.getNode())
4873 // Handle all 4 wide cases with a number of shuffles except for MMX.
4874 if (NumElems == 4 && !isMMX)
4875 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4881 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4882 SelectionDAG &DAG) const {
4883 EVT VT = Op.getValueType();
4884 DebugLoc dl = Op.getDebugLoc();
4885 if (VT.getSizeInBits() == 8) {
4886 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4887 Op.getOperand(0), Op.getOperand(1));
4888 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4889 DAG.getValueType(VT));
4890 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4891 } else if (VT.getSizeInBits() == 16) {
4892 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4893 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4895 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4896 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4897 DAG.getNode(ISD::BIT_CONVERT, dl,
4901 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4902 Op.getOperand(0), Op.getOperand(1));
4903 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4904 DAG.getValueType(VT));
4905 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4906 } else if (VT == MVT::f32) {
4907 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4908 // the result back to FR32 register. It's only worth matching if the
4909 // result has a single use which is a store or a bitcast to i32. And in
4910 // the case of a store, it's not worth it if the index is a constant 0,
4911 // because a MOVSSmr can be used instead, which is smaller and faster.
4912 if (!Op.hasOneUse())
4914 SDNode *User = *Op.getNode()->use_begin();
4915 if ((User->getOpcode() != ISD::STORE ||
4916 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4917 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4918 (User->getOpcode() != ISD::BIT_CONVERT ||
4919 User->getValueType(0) != MVT::i32))
4921 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4922 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4925 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4926 } else if (VT == MVT::i32) {
4927 // ExtractPS works with constant index.
4928 if (isa<ConstantSDNode>(Op.getOperand(1)))
4936 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
4937 SelectionDAG &DAG) const {
4938 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4941 if (Subtarget->hasSSE41()) {
4942 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4947 EVT VT = Op.getValueType();
4948 DebugLoc dl = Op.getDebugLoc();
4949 // TODO: handle v16i8.
4950 if (VT.getSizeInBits() == 16) {
4951 SDValue Vec = Op.getOperand(0);
4952 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4954 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4955 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4956 DAG.getNode(ISD::BIT_CONVERT, dl,
4959 // Transform it so it match pextrw which produces a 32-bit result.
4960 EVT EltVT = MVT::i32;
4961 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4962 Op.getOperand(0), Op.getOperand(1));
4963 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4964 DAG.getValueType(VT));
4965 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4966 } else if (VT.getSizeInBits() == 32) {
4967 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4971 // SHUFPS the element to the lowest double word, then movss.
4972 int Mask[4] = { Idx, -1, -1, -1 };
4973 EVT VVT = Op.getOperand(0).getValueType();
4974 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4975 DAG.getUNDEF(VVT), Mask);
4976 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4977 DAG.getIntPtrConstant(0));
4978 } else if (VT.getSizeInBits() == 64) {
4979 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4980 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4981 // to match extract_elt for f64.
4982 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4986 // UNPCKHPD the element to the lowest double word, then movsd.
4987 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4988 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4989 int Mask[2] = { 1, -1 };
4990 EVT VVT = Op.getOperand(0).getValueType();
4991 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4992 DAG.getUNDEF(VVT), Mask);
4993 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4994 DAG.getIntPtrConstant(0));
5001 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5002 SelectionDAG &DAG) const {
5003 EVT VT = Op.getValueType();
5004 EVT EltVT = VT.getVectorElementType();
5005 DebugLoc dl = Op.getDebugLoc();
5007 SDValue N0 = Op.getOperand(0);
5008 SDValue N1 = Op.getOperand(1);
5009 SDValue N2 = Op.getOperand(2);
5011 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5012 isa<ConstantSDNode>(N2)) {
5014 if (VT == MVT::v8i16)
5015 Opc = X86ISD::PINSRW;
5016 else if (VT == MVT::v4i16)
5017 Opc = X86ISD::MMX_PINSRW;
5018 else if (VT == MVT::v16i8)
5019 Opc = X86ISD::PINSRB;
5021 Opc = X86ISD::PINSRB;
5023 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5025 if (N1.getValueType() != MVT::i32)
5026 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5027 if (N2.getValueType() != MVT::i32)
5028 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5029 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5030 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5031 // Bits [7:6] of the constant are the source select. This will always be
5032 // zero here. The DAG Combiner may combine an extract_elt index into these
5033 // bits. For example (insert (extract, 3), 2) could be matched by putting
5034 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5035 // Bits [5:4] of the constant are the destination select. This is the
5036 // value of the incoming immediate.
5037 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5038 // combine either bitwise AND or insert of float 0.0 to set these bits.
5039 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5040 // Create this as a scalar to vector..
5041 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5042 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5043 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5044 // PINSR* works with constant index.
5051 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5052 EVT VT = Op.getValueType();
5053 EVT EltVT = VT.getVectorElementType();
5055 if (Subtarget->hasSSE41())
5056 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5058 if (EltVT == MVT::i8)
5061 DebugLoc dl = Op.getDebugLoc();
5062 SDValue N0 = Op.getOperand(0);
5063 SDValue N1 = Op.getOperand(1);
5064 SDValue N2 = Op.getOperand(2);
5066 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5067 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5068 // as its second argument.
5069 if (N1.getValueType() != MVT::i32)
5070 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5071 if (N2.getValueType() != MVT::i32)
5072 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5073 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5074 dl, VT, N0, N1, N2);
5080 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5081 DebugLoc dl = Op.getDebugLoc();
5083 if (Op.getValueType() == MVT::v1i64 &&
5084 Op.getOperand(0).getValueType() == MVT::i64)
5085 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5087 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5088 EVT VT = MVT::v2i32;
5089 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5096 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5097 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5100 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5101 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5102 // one of the above mentioned nodes. It has to be wrapped because otherwise
5103 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5104 // be used to form addressing mode. These wrapped nodes will be selected
5107 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5108 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5110 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5112 unsigned char OpFlag = 0;
5113 unsigned WrapperKind = X86ISD::Wrapper;
5114 CodeModel::Model M = getTargetMachine().getCodeModel();
5116 if (Subtarget->isPICStyleRIPRel() &&
5117 (M == CodeModel::Small || M == CodeModel::Kernel))
5118 WrapperKind = X86ISD::WrapperRIP;
5119 else if (Subtarget->isPICStyleGOT())
5120 OpFlag = X86II::MO_GOTOFF;
5121 else if (Subtarget->isPICStyleStubPIC())
5122 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5124 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5126 CP->getOffset(), OpFlag);
5127 DebugLoc DL = CP->getDebugLoc();
5128 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5129 // With PIC, the address is actually $g + Offset.
5131 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5132 DAG.getNode(X86ISD::GlobalBaseReg,
5133 DebugLoc(), getPointerTy()),
5140 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5141 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5143 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5145 unsigned char OpFlag = 0;
5146 unsigned WrapperKind = X86ISD::Wrapper;
5147 CodeModel::Model M = getTargetMachine().getCodeModel();
5149 if (Subtarget->isPICStyleRIPRel() &&
5150 (M == CodeModel::Small || M == CodeModel::Kernel))
5151 WrapperKind = X86ISD::WrapperRIP;
5152 else if (Subtarget->isPICStyleGOT())
5153 OpFlag = X86II::MO_GOTOFF;
5154 else if (Subtarget->isPICStyleStubPIC())
5155 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5157 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5159 DebugLoc DL = JT->getDebugLoc();
5160 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5162 // With PIC, the address is actually $g + Offset.
5164 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5165 DAG.getNode(X86ISD::GlobalBaseReg,
5166 DebugLoc(), getPointerTy()),
5174 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5175 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5177 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5179 unsigned char OpFlag = 0;
5180 unsigned WrapperKind = X86ISD::Wrapper;
5181 CodeModel::Model M = getTargetMachine().getCodeModel();
5183 if (Subtarget->isPICStyleRIPRel() &&
5184 (M == CodeModel::Small || M == CodeModel::Kernel))
5185 WrapperKind = X86ISD::WrapperRIP;
5186 else if (Subtarget->isPICStyleGOT())
5187 OpFlag = X86II::MO_GOTOFF;
5188 else if (Subtarget->isPICStyleStubPIC())
5189 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5191 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5193 DebugLoc DL = Op.getDebugLoc();
5194 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5197 // With PIC, the address is actually $g + Offset.
5198 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5199 !Subtarget->is64Bit()) {
5200 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5201 DAG.getNode(X86ISD::GlobalBaseReg,
5202 DebugLoc(), getPointerTy()),
5210 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5211 // Create the TargetBlockAddressAddress node.
5212 unsigned char OpFlags =
5213 Subtarget->ClassifyBlockAddressReference();
5214 CodeModel::Model M = getTargetMachine().getCodeModel();
5215 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5216 DebugLoc dl = Op.getDebugLoc();
5217 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5218 /*isTarget=*/true, OpFlags);
5220 if (Subtarget->isPICStyleRIPRel() &&
5221 (M == CodeModel::Small || M == CodeModel::Kernel))
5222 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5224 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5226 // With PIC, the address is actually $g + Offset.
5227 if (isGlobalRelativeToPICBase(OpFlags)) {
5228 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5229 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5237 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5239 SelectionDAG &DAG) const {
5240 // Create the TargetGlobalAddress node, folding in the constant
5241 // offset if it is legal.
5242 unsigned char OpFlags =
5243 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5244 CodeModel::Model M = getTargetMachine().getCodeModel();
5246 if (OpFlags == X86II::MO_NO_FLAG &&
5247 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5248 // A direct static reference to a global.
5249 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5252 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5255 if (Subtarget->isPICStyleRIPRel() &&
5256 (M == CodeModel::Small || M == CodeModel::Kernel))
5257 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5259 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5261 // With PIC, the address is actually $g + Offset.
5262 if (isGlobalRelativeToPICBase(OpFlags)) {
5263 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5264 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5268 // For globals that require a load from a stub to get the address, emit the
5270 if (isGlobalStubReference(OpFlags))
5271 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5272 PseudoSourceValue::getGOT(), 0, false, false, 0);
5274 // If there was a non-zero offset that we didn't fold, create an explicit
5277 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5278 DAG.getConstant(Offset, getPointerTy()));
5284 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5285 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5286 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5287 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5291 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5292 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5293 unsigned char OperandFlags) {
5294 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5295 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5296 DebugLoc dl = GA->getDebugLoc();
5297 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5298 GA->getValueType(0),
5302 SDValue Ops[] = { Chain, TGA, *InFlag };
5303 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5305 SDValue Ops[] = { Chain, TGA };
5306 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5309 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5310 MFI->setAdjustsStack(true);
5312 SDValue Flag = Chain.getValue(1);
5313 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5316 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5318 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5321 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5322 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5323 DAG.getNode(X86ISD::GlobalBaseReg,
5324 DebugLoc(), PtrVT), InFlag);
5325 InFlag = Chain.getValue(1);
5327 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5330 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5332 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5334 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5335 X86::RAX, X86II::MO_TLSGD);
5338 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5339 // "local exec" model.
5340 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5341 const EVT PtrVT, TLSModel::Model model,
5343 DebugLoc dl = GA->getDebugLoc();
5344 // Get the Thread Pointer
5345 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5347 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5350 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5351 NULL, 0, false, false, 0);
5353 unsigned char OperandFlags = 0;
5354 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5356 unsigned WrapperKind = X86ISD::Wrapper;
5357 if (model == TLSModel::LocalExec) {
5358 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5359 } else if (is64Bit) {
5360 assert(model == TLSModel::InitialExec);
5361 OperandFlags = X86II::MO_GOTTPOFF;
5362 WrapperKind = X86ISD::WrapperRIP;
5364 assert(model == TLSModel::InitialExec);
5365 OperandFlags = X86II::MO_INDNTPOFF;
5368 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5370 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5371 GA->getValueType(0),
5372 GA->getOffset(), OperandFlags);
5373 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5375 if (model == TLSModel::InitialExec)
5376 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5377 PseudoSourceValue::getGOT(), 0, false, false, 0);
5379 // The address of the thread local variable is the add of the thread
5380 // pointer with the offset of the variable.
5381 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5385 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
5387 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5388 const GlobalValue *GV = GA->getGlobal();
5390 if (Subtarget->isTargetELF()) {
5391 // TODO: implement the "local dynamic" model
5392 // TODO: implement the "initial exec"model for pic executables
5394 // If GV is an alias then use the aliasee for determining
5395 // thread-localness.
5396 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5397 GV = GA->resolveAliasedGlobal(false);
5399 TLSModel::Model model
5400 = getTLSModel(GV, getTargetMachine().getRelocationModel());
5403 case TLSModel::GeneralDynamic:
5404 case TLSModel::LocalDynamic: // not implemented
5405 if (Subtarget->is64Bit())
5406 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5407 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5409 case TLSModel::InitialExec:
5410 case TLSModel::LocalExec:
5411 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5412 Subtarget->is64Bit());
5414 } else if (Subtarget->isTargetDarwin()) {
5415 // Darwin only has one model of TLS. Lower to that.
5416 unsigned char OpFlag = 0;
5417 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
5418 X86ISD::WrapperRIP : X86ISD::Wrapper;
5420 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5422 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
5423 !Subtarget->is64Bit();
5425 OpFlag = X86II::MO_TLVP_PIC_BASE;
5427 OpFlag = X86II::MO_TLVP;
5428 DebugLoc DL = Op.getDebugLoc();
5429 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
5431 GA->getOffset(), OpFlag);
5432 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5434 // With PIC32, the address is actually $g + Offset.
5436 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5437 DAG.getNode(X86ISD::GlobalBaseReg,
5438 DebugLoc(), getPointerTy()),
5441 // Lowering the machine isd will make sure everything is in the right
5443 SDValue Args[] = { Offset };
5444 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
5446 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
5447 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5448 MFI->setAdjustsStack(true);
5450 // And our return value (tls address) is in the standard call return value
5452 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
5453 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
5457 "TLS not implemented for this target.");
5459 llvm_unreachable("Unreachable");
5464 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5465 /// take a 2 x i32 value to shift plus a shift amount.
5466 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
5467 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5468 EVT VT = Op.getValueType();
5469 unsigned VTBits = VT.getSizeInBits();
5470 DebugLoc dl = Op.getDebugLoc();
5471 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5472 SDValue ShOpLo = Op.getOperand(0);
5473 SDValue ShOpHi = Op.getOperand(1);
5474 SDValue ShAmt = Op.getOperand(2);
5475 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5476 DAG.getConstant(VTBits - 1, MVT::i8))
5477 : DAG.getConstant(0, VT);
5480 if (Op.getOpcode() == ISD::SHL_PARTS) {
5481 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5482 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5484 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5485 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5488 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5489 DAG.getConstant(VTBits, MVT::i8));
5490 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
5491 AndNode, DAG.getConstant(0, MVT::i8));
5494 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5495 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5496 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5498 if (Op.getOpcode() == ISD::SHL_PARTS) {
5499 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5500 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5502 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5503 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5506 SDValue Ops[2] = { Lo, Hi };
5507 return DAG.getMergeValues(Ops, 2, dl);
5510 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
5511 SelectionDAG &DAG) const {
5512 EVT SrcVT = Op.getOperand(0).getValueType();
5514 if (SrcVT.isVector()) {
5515 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5521 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5522 "Unknown SINT_TO_FP to lower!");
5524 // These are really Legal; return the operand so the caller accepts it as
5526 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5528 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5529 Subtarget->is64Bit()) {
5533 DebugLoc dl = Op.getDebugLoc();
5534 unsigned Size = SrcVT.getSizeInBits()/8;
5535 MachineFunction &MF = DAG.getMachineFunction();
5536 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5537 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5538 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5540 PseudoSourceValue::getFixedStack(SSFI), 0,
5542 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5545 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5547 SelectionDAG &DAG) const {
5549 DebugLoc dl = Op.getDebugLoc();
5551 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5553 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5555 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5556 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5557 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5558 Tys, Ops, array_lengthof(Ops));
5561 Chain = Result.getValue(1);
5562 SDValue InFlag = Result.getValue(2);
5564 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5565 // shouldn't be necessary except that RFP cannot be live across
5566 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5567 MachineFunction &MF = DAG.getMachineFunction();
5568 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5569 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5570 Tys = DAG.getVTList(MVT::Other);
5572 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5574 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5575 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5576 PseudoSourceValue::getFixedStack(SSFI), 0,
5583 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5584 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
5585 SelectionDAG &DAG) const {
5586 // This algorithm is not obvious. Here it is in C code, more or less:
5588 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5589 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5590 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5592 // Copy ints to xmm registers.
5593 __m128i xh = _mm_cvtsi32_si128( hi );
5594 __m128i xl = _mm_cvtsi32_si128( lo );
5596 // Combine into low half of a single xmm register.
5597 __m128i x = _mm_unpacklo_epi32( xh, xl );
5601 // Merge in appropriate exponents to give the integer bits the right
5603 x = _mm_unpacklo_epi32( x, exp );
5605 // Subtract away the biases to deal with the IEEE-754 double precision
5607 d = _mm_sub_pd( (__m128d) x, bias );
5609 // All conversions up to here are exact. The correctly rounded result is
5610 // calculated using the current rounding mode using the following
5612 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5613 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5614 // store doesn't really need to be here (except
5615 // maybe to zero the other double)
5620 DebugLoc dl = Op.getDebugLoc();
5621 LLVMContext *Context = DAG.getContext();
5623 // Build some magic constants.
5624 std::vector<Constant*> CV0;
5625 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5626 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5627 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5628 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5629 Constant *C0 = ConstantVector::get(CV0);
5630 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5632 std::vector<Constant*> CV1;
5634 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5636 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5637 Constant *C1 = ConstantVector::get(CV1);
5638 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5640 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5641 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5643 DAG.getIntPtrConstant(1)));
5644 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5645 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5647 DAG.getIntPtrConstant(0)));
5648 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5649 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5650 PseudoSourceValue::getConstantPool(), 0,
5652 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5653 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5654 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5655 PseudoSourceValue::getConstantPool(), 0,
5657 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5659 // Add the halves; easiest way is to swap them into another reg first.
5660 int ShufMask[2] = { 1, -1 };
5661 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5662 DAG.getUNDEF(MVT::v2f64), ShufMask);
5663 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5664 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5665 DAG.getIntPtrConstant(0));
5668 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5669 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
5670 SelectionDAG &DAG) const {
5671 DebugLoc dl = Op.getDebugLoc();
5672 // FP constant to bias correct the final result.
5673 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5676 // Load the 32-bit value into an XMM register.
5677 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5678 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5680 DAG.getIntPtrConstant(0)));
5682 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5683 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5684 DAG.getIntPtrConstant(0));
5686 // Or the load with the bias.
5687 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5688 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5689 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5691 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5692 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5693 MVT::v2f64, Bias)));
5694 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5695 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5696 DAG.getIntPtrConstant(0));
5698 // Subtract the bias.
5699 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5701 // Handle final rounding.
5702 EVT DestVT = Op.getValueType();
5704 if (DestVT.bitsLT(MVT::f64)) {
5705 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5706 DAG.getIntPtrConstant(0));
5707 } else if (DestVT.bitsGT(MVT::f64)) {
5708 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5711 // Handle final rounding.
5715 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
5716 SelectionDAG &DAG) const {
5717 SDValue N0 = Op.getOperand(0);
5718 DebugLoc dl = Op.getDebugLoc();
5720 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
5721 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5722 // the optimization here.
5723 if (DAG.SignBitIsZero(N0))
5724 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5726 EVT SrcVT = N0.getValueType();
5727 EVT DstVT = Op.getValueType();
5728 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
5729 return LowerUINT_TO_FP_i64(Op, DAG);
5730 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
5731 return LowerUINT_TO_FP_i32(Op, DAG);
5733 // Make a 64-bit buffer, and use it to build an FILD.
5734 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5735 if (SrcVT == MVT::i32) {
5736 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5737 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5738 getPointerTy(), StackSlot, WordOff);
5739 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5740 StackSlot, NULL, 0, false, false, 0);
5741 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5742 OffsetSlot, NULL, 0, false, false, 0);
5743 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5747 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
5748 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5749 StackSlot, NULL, 0, false, false, 0);
5750 // For i64 source, we need to add the appropriate power of 2 if the input
5751 // was negative. This is the same as the optimization in
5752 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
5753 // we must be careful to do the computation in x87 extended precision, not
5754 // in SSE. (The generic code can't know it's OK to do this, or how to.)
5755 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
5756 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
5757 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
5759 APInt FF(32, 0x5F800000ULL);
5761 // Check whether the sign bit is set.
5762 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
5763 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
5766 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
5767 SDValue FudgePtr = DAG.getConstantPool(
5768 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
5771 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
5772 SDValue Zero = DAG.getIntPtrConstant(0);
5773 SDValue Four = DAG.getIntPtrConstant(4);
5774 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
5776 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
5778 // Load the value out, extending it from f32 to f80.
5779 // FIXME: Avoid the extend by constructing the right constant pool?
5780 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
5781 FudgePtr, PseudoSourceValue::getConstantPool(),
5782 0, MVT::f32, false, false, 4);
5783 // Extend everything to 80 bits to force it to be done on x87.
5784 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
5785 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
5788 std::pair<SDValue,SDValue> X86TargetLowering::
5789 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
5790 DebugLoc dl = Op.getDebugLoc();
5792 EVT DstTy = Op.getValueType();
5795 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5799 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5800 DstTy.getSimpleVT() >= MVT::i16 &&
5801 "Unknown FP_TO_SINT to lower!");
5803 // These are really Legal.
5804 if (DstTy == MVT::i32 &&
5805 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5806 return std::make_pair(SDValue(), SDValue());
5807 if (Subtarget->is64Bit() &&
5808 DstTy == MVT::i64 &&
5809 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5810 return std::make_pair(SDValue(), SDValue());
5812 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5814 MachineFunction &MF = DAG.getMachineFunction();
5815 unsigned MemSize = DstTy.getSizeInBits()/8;
5816 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5817 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5820 switch (DstTy.getSimpleVT().SimpleTy) {
5821 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5822 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5823 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5824 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5827 SDValue Chain = DAG.getEntryNode();
5828 SDValue Value = Op.getOperand(0);
5829 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5830 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5831 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5832 PseudoSourceValue::getFixedStack(SSFI), 0,
5834 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5836 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5838 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5839 Chain = Value.getValue(1);
5840 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5841 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5844 // Build the FP_TO_INT*_IN_MEM
5845 SDValue Ops[] = { Chain, Value, StackSlot };
5846 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5848 return std::make_pair(FIST, StackSlot);
5851 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
5852 SelectionDAG &DAG) const {
5853 if (Op.getValueType().isVector()) {
5854 if (Op.getValueType() == MVT::v2i32 &&
5855 Op.getOperand(0).getValueType() == MVT::v2f64) {
5861 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5862 SDValue FIST = Vals.first, StackSlot = Vals.second;
5863 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5864 if (FIST.getNode() == 0) return Op;
5867 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5868 FIST, StackSlot, NULL, 0, false, false, 0);
5871 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
5872 SelectionDAG &DAG) const {
5873 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5874 SDValue FIST = Vals.first, StackSlot = Vals.second;
5875 assert(FIST.getNode() && "Unexpected failure");
5878 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5879 FIST, StackSlot, NULL, 0, false, false, 0);
5882 SDValue X86TargetLowering::LowerFABS(SDValue Op,
5883 SelectionDAG &DAG) const {
5884 LLVMContext *Context = DAG.getContext();
5885 DebugLoc dl = Op.getDebugLoc();
5886 EVT VT = Op.getValueType();
5889 EltVT = VT.getVectorElementType();
5890 std::vector<Constant*> CV;
5891 if (EltVT == MVT::f64) {
5892 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5896 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5902 Constant *C = ConstantVector::get(CV);
5903 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5904 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5905 PseudoSourceValue::getConstantPool(), 0,
5907 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5910 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
5911 LLVMContext *Context = DAG.getContext();
5912 DebugLoc dl = Op.getDebugLoc();
5913 EVT VT = Op.getValueType();
5916 EltVT = VT.getVectorElementType();
5917 std::vector<Constant*> CV;
5918 if (EltVT == MVT::f64) {
5919 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5923 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5929 Constant *C = ConstantVector::get(CV);
5930 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5931 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5932 PseudoSourceValue::getConstantPool(), 0,
5934 if (VT.isVector()) {
5935 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5936 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5937 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5939 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5941 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5945 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5946 LLVMContext *Context = DAG.getContext();
5947 SDValue Op0 = Op.getOperand(0);
5948 SDValue Op1 = Op.getOperand(1);
5949 DebugLoc dl = Op.getDebugLoc();
5950 EVT VT = Op.getValueType();
5951 EVT SrcVT = Op1.getValueType();
5953 // If second operand is smaller, extend it first.
5954 if (SrcVT.bitsLT(VT)) {
5955 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5958 // And if it is bigger, shrink it first.
5959 if (SrcVT.bitsGT(VT)) {
5960 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5964 // At this point the operands and the result should have the same
5965 // type, and that won't be f80 since that is not custom lowered.
5967 // First get the sign bit of second operand.
5968 std::vector<Constant*> CV;
5969 if (SrcVT == MVT::f64) {
5970 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5971 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5973 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5974 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5975 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5976 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5978 Constant *C = ConstantVector::get(CV);
5979 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5980 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5981 PseudoSourceValue::getConstantPool(), 0,
5983 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5985 // Shift sign bit right or left if the two operands have different types.
5986 if (SrcVT.bitsGT(VT)) {
5987 // Op0 is MVT::f32, Op1 is MVT::f64.
5988 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5989 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5990 DAG.getConstant(32, MVT::i32));
5991 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5992 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5993 DAG.getIntPtrConstant(0));
5996 // Clear first operand sign bit.
5998 if (VT == MVT::f64) {
5999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6000 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6003 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6005 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6007 C = ConstantVector::get(CV);
6008 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6009 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6010 PseudoSourceValue::getConstantPool(), 0,
6012 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6014 // Or the value with the sign bit.
6015 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6018 /// Emit nodes that will be selected as "test Op0,Op0", or something
6020 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6021 SelectionDAG &DAG) const {
6022 DebugLoc dl = Op.getDebugLoc();
6024 // CF and OF aren't always set the way we want. Determine which
6025 // of these we need.
6026 bool NeedCF = false;
6027 bool NeedOF = false;
6030 case X86::COND_A: case X86::COND_AE:
6031 case X86::COND_B: case X86::COND_BE:
6034 case X86::COND_G: case X86::COND_GE:
6035 case X86::COND_L: case X86::COND_LE:
6036 case X86::COND_O: case X86::COND_NO:
6041 // See if we can use the EFLAGS value from the operand instead of
6042 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6043 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6044 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6045 // Emit a CMP with 0, which is the TEST pattern.
6046 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6047 DAG.getConstant(0, Op.getValueType()));
6049 unsigned Opcode = 0;
6050 unsigned NumOperands = 0;
6051 switch (Op.getNode()->getOpcode()) {
6053 // Due to an isel shortcoming, be conservative if this add is likely to be
6054 // selected as part of a load-modify-store instruction. When the root node
6055 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6056 // uses of other nodes in the match, such as the ADD in this case. This
6057 // leads to the ADD being left around and reselected, with the result being
6058 // two adds in the output. Alas, even if none our users are stores, that
6059 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6060 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6061 // climbing the DAG back to the root, and it doesn't seem to be worth the
6063 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6064 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6065 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6068 if (ConstantSDNode *C =
6069 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6070 // An add of one will be selected as an INC.
6071 if (C->getAPIntValue() == 1) {
6072 Opcode = X86ISD::INC;
6077 // An add of negative one (subtract of one) will be selected as a DEC.
6078 if (C->getAPIntValue().isAllOnesValue()) {
6079 Opcode = X86ISD::DEC;
6085 // Otherwise use a regular EFLAGS-setting add.
6086 Opcode = X86ISD::ADD;
6090 // If the primary and result isn't used, don't bother using X86ISD::AND,
6091 // because a TEST instruction will be better.
6092 bool NonFlagUse = false;
6093 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6094 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6096 unsigned UOpNo = UI.getOperandNo();
6097 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6098 // Look pass truncate.
6099 UOpNo = User->use_begin().getOperandNo();
6100 User = *User->use_begin();
6103 if (User->getOpcode() != ISD::BRCOND &&
6104 User->getOpcode() != ISD::SETCC &&
6105 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6118 // Due to the ISEL shortcoming noted above, be conservative if this op is
6119 // likely to be selected as part of a load-modify-store instruction.
6120 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6121 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6122 if (UI->getOpcode() == ISD::STORE)
6125 // Otherwise use a regular EFLAGS-setting instruction.
6126 switch (Op.getNode()->getOpcode()) {
6127 default: llvm_unreachable("unexpected operator!");
6128 case ISD::SUB: Opcode = X86ISD::SUB; break;
6129 case ISD::OR: Opcode = X86ISD::OR; break;
6130 case ISD::XOR: Opcode = X86ISD::XOR; break;
6131 case ISD::AND: Opcode = X86ISD::AND; break;
6143 return SDValue(Op.getNode(), 1);
6150 // Emit a CMP with 0, which is the TEST pattern.
6151 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6152 DAG.getConstant(0, Op.getValueType()));
6154 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6155 SmallVector<SDValue, 4> Ops;
6156 for (unsigned i = 0; i != NumOperands; ++i)
6157 Ops.push_back(Op.getOperand(i));
6159 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6160 DAG.ReplaceAllUsesWith(Op, New);
6161 return SDValue(New.getNode(), 1);
6164 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6166 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6167 SelectionDAG &DAG) const {
6168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6169 if (C->getAPIntValue() == 0)
6170 return EmitTest(Op0, X86CC, DAG);
6172 DebugLoc dl = Op0.getDebugLoc();
6173 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6176 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6177 /// if it's possible.
6178 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6179 DebugLoc dl, SelectionDAG &DAG) const {
6180 SDValue Op0 = And.getOperand(0);
6181 SDValue Op1 = And.getOperand(1);
6182 if (Op0.getOpcode() == ISD::TRUNCATE)
6183 Op0 = Op0.getOperand(0);
6184 if (Op1.getOpcode() == ISD::TRUNCATE)
6185 Op1 = Op1.getOperand(0);
6188 if (Op1.getOpcode() == ISD::SHL)
6189 std::swap(Op0, Op1);
6190 if (Op0.getOpcode() == ISD::SHL) {
6191 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6192 if (And00C->getZExtValue() == 1) {
6193 // If we looked past a truncate, check that it's only truncating away
6195 unsigned BitWidth = Op0.getValueSizeInBits();
6196 unsigned AndBitWidth = And.getValueSizeInBits();
6197 if (BitWidth > AndBitWidth) {
6198 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6199 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6200 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6204 RHS = Op0.getOperand(1);
6206 } else if (Op1.getOpcode() == ISD::Constant) {
6207 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6208 SDValue AndLHS = Op0;
6209 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6210 LHS = AndLHS.getOperand(0);
6211 RHS = AndLHS.getOperand(1);
6215 if (LHS.getNode()) {
6216 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6217 // instruction. Since the shift amount is in-range-or-undefined, we know
6218 // that doing a bittest on the i32 value is ok. We extend to i32 because
6219 // the encoding for the i16 version is larger than the i32 version.
6220 // Also promote i16 to i32 for performance / code size reason.
6221 if (LHS.getValueType() == MVT::i8 ||
6222 LHS.getValueType() == MVT::i16)
6223 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6225 // If the operand types disagree, extend the shift amount to match. Since
6226 // BT ignores high bits (like shifts) we can use anyextend.
6227 if (LHS.getValueType() != RHS.getValueType())
6228 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6230 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6231 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6232 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6233 DAG.getConstant(Cond, MVT::i8), BT);
6239 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6240 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6241 SDValue Op0 = Op.getOperand(0);
6242 SDValue Op1 = Op.getOperand(1);
6243 DebugLoc dl = Op.getDebugLoc();
6244 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6246 // Optimize to BT if possible.
6247 // Lower (X & (1 << N)) == 0 to BT(X, N).
6248 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6249 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6250 if (Op0.getOpcode() == ISD::AND &&
6252 Op1.getOpcode() == ISD::Constant &&
6253 cast<ConstantSDNode>(Op1)->isNullValue() &&
6254 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6255 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6256 if (NewSetCC.getNode())
6260 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6261 if (Op0.getOpcode() == X86ISD::SETCC &&
6262 Op1.getOpcode() == ISD::Constant &&
6263 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6264 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6265 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6266 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6267 bool Invert = (CC == ISD::SETNE) ^
6268 cast<ConstantSDNode>(Op1)->isNullValue();
6270 CCode = X86::GetOppositeBranchCondition(CCode);
6271 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6272 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6275 bool isFP = Op1.getValueType().isFloatingPoint();
6276 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6277 if (X86CC == X86::COND_INVALID)
6280 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6282 // Use sbb x, x to materialize carry bit into a GPR.
6283 if (X86CC == X86::COND_B)
6284 return DAG.getNode(ISD::AND, dl, MVT::i8,
6285 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6286 DAG.getConstant(X86CC, MVT::i8), Cond),
6287 DAG.getConstant(1, MVT::i8));
6289 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6290 DAG.getConstant(X86CC, MVT::i8), Cond);
6293 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6295 SDValue Op0 = Op.getOperand(0);
6296 SDValue Op1 = Op.getOperand(1);
6297 SDValue CC = Op.getOperand(2);
6298 EVT VT = Op.getValueType();
6299 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6300 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6301 DebugLoc dl = Op.getDebugLoc();
6305 EVT VT0 = Op0.getValueType();
6306 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6307 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6310 switch (SetCCOpcode) {
6313 case ISD::SETEQ: SSECC = 0; break;
6315 case ISD::SETGT: Swap = true; // Fallthrough
6317 case ISD::SETOLT: SSECC = 1; break;
6319 case ISD::SETGE: Swap = true; // Fallthrough
6321 case ISD::SETOLE: SSECC = 2; break;
6322 case ISD::SETUO: SSECC = 3; break;
6324 case ISD::SETNE: SSECC = 4; break;
6325 case ISD::SETULE: Swap = true;
6326 case ISD::SETUGE: SSECC = 5; break;
6327 case ISD::SETULT: Swap = true;
6328 case ISD::SETUGT: SSECC = 6; break;
6329 case ISD::SETO: SSECC = 7; break;
6332 std::swap(Op0, Op1);
6334 // In the two special cases we can't handle, emit two comparisons.
6336 if (SetCCOpcode == ISD::SETUEQ) {
6338 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6339 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6340 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6342 else if (SetCCOpcode == ISD::SETONE) {
6344 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6345 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6346 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6348 llvm_unreachable("Illegal FP comparison");
6350 // Handle all other FP comparisons here.
6351 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6354 // We are handling one of the integer comparisons here. Since SSE only has
6355 // GT and EQ comparisons for integer, swapping operands and multiple
6356 // operations may be required for some comparisons.
6357 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6358 bool Swap = false, Invert = false, FlipSigns = false;
6360 switch (VT.getSimpleVT().SimpleTy) {
6363 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6365 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6367 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6368 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6371 switch (SetCCOpcode) {
6373 case ISD::SETNE: Invert = true;
6374 case ISD::SETEQ: Opc = EQOpc; break;
6375 case ISD::SETLT: Swap = true;
6376 case ISD::SETGT: Opc = GTOpc; break;
6377 case ISD::SETGE: Swap = true;
6378 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6379 case ISD::SETULT: Swap = true;
6380 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6381 case ISD::SETUGE: Swap = true;
6382 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6385 std::swap(Op0, Op1);
6387 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6388 // bits of the inputs before performing those operations.
6390 EVT EltVT = VT.getVectorElementType();
6391 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6393 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6394 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6396 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6397 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6400 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6402 // If the logical-not of the result is required, perform that now.
6404 Result = DAG.getNOT(dl, Result, VT);
6409 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6410 static bool isX86LogicalCmp(SDValue Op) {
6411 unsigned Opc = Op.getNode()->getOpcode();
6412 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6414 if (Op.getResNo() == 1 &&
6415 (Opc == X86ISD::ADD ||
6416 Opc == X86ISD::SUB ||
6417 Opc == X86ISD::SMUL ||
6418 Opc == X86ISD::UMUL ||
6419 Opc == X86ISD::INC ||
6420 Opc == X86ISD::DEC ||
6421 Opc == X86ISD::OR ||
6422 Opc == X86ISD::XOR ||
6423 Opc == X86ISD::AND))
6429 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
6430 bool addTest = true;
6431 SDValue Cond = Op.getOperand(0);
6432 DebugLoc dl = Op.getDebugLoc();
6435 if (Cond.getOpcode() == ISD::SETCC) {
6436 SDValue NewCond = LowerSETCC(Cond, DAG);
6437 if (NewCond.getNode())
6441 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6442 SDValue Op1 = Op.getOperand(1);
6443 SDValue Op2 = Op.getOperand(2);
6444 if (Cond.getOpcode() == X86ISD::SETCC &&
6445 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6446 SDValue Cmp = Cond.getOperand(1);
6447 if (Cmp.getOpcode() == X86ISD::CMP) {
6448 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6449 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6450 ConstantSDNode *RHSC =
6451 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6452 if (N1C && N1C->isAllOnesValue() &&
6453 N2C && N2C->isNullValue() &&
6454 RHSC && RHSC->isNullValue()) {
6455 SDValue CmpOp0 = Cmp.getOperand(0);
6456 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6457 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6458 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6459 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6464 // Look pass (and (setcc_carry (cmp ...)), 1).
6465 if (Cond.getOpcode() == ISD::AND &&
6466 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6467 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6468 if (C && C->getAPIntValue() == 1)
6469 Cond = Cond.getOperand(0);
6472 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6473 // setting operand in place of the X86ISD::SETCC.
6474 if (Cond.getOpcode() == X86ISD::SETCC ||
6475 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6476 CC = Cond.getOperand(0);
6478 SDValue Cmp = Cond.getOperand(1);
6479 unsigned Opc = Cmp.getOpcode();
6480 EVT VT = Op.getValueType();
6482 bool IllegalFPCMov = false;
6483 if (VT.isFloatingPoint() && !VT.isVector() &&
6484 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6485 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6487 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6488 Opc == X86ISD::BT) { // FIXME
6495 // Look pass the truncate.
6496 if (Cond.getOpcode() == ISD::TRUNCATE)
6497 Cond = Cond.getOperand(0);
6499 // We know the result of AND is compared against zero. Try to match
6501 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6502 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6503 if (NewSetCC.getNode()) {
6504 CC = NewSetCC.getOperand(0);
6505 Cond = NewSetCC.getOperand(1);
6512 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6513 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6516 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6517 // condition is true.
6518 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6519 SDValue Ops[] = { Op2, Op1, CC, Cond };
6520 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6523 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6524 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6525 // from the AND / OR.
6526 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6527 Opc = Op.getOpcode();
6528 if (Opc != ISD::OR && Opc != ISD::AND)
6530 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6531 Op.getOperand(0).hasOneUse() &&
6532 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6533 Op.getOperand(1).hasOneUse());
6536 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6537 // 1 and that the SETCC node has a single use.
6538 static bool isXor1OfSetCC(SDValue Op) {
6539 if (Op.getOpcode() != ISD::XOR)
6541 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6542 if (N1C && N1C->getAPIntValue() == 1) {
6543 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6544 Op.getOperand(0).hasOneUse();
6549 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
6550 bool addTest = true;
6551 SDValue Chain = Op.getOperand(0);
6552 SDValue Cond = Op.getOperand(1);
6553 SDValue Dest = Op.getOperand(2);
6554 DebugLoc dl = Op.getDebugLoc();
6557 if (Cond.getOpcode() == ISD::SETCC) {
6558 SDValue NewCond = LowerSETCC(Cond, DAG);
6559 if (NewCond.getNode())
6563 // FIXME: LowerXALUO doesn't handle these!!
6564 else if (Cond.getOpcode() == X86ISD::ADD ||
6565 Cond.getOpcode() == X86ISD::SUB ||
6566 Cond.getOpcode() == X86ISD::SMUL ||
6567 Cond.getOpcode() == X86ISD::UMUL)
6568 Cond = LowerXALUO(Cond, DAG);
6571 // Look pass (and (setcc_carry (cmp ...)), 1).
6572 if (Cond.getOpcode() == ISD::AND &&
6573 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6574 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6575 if (C && C->getAPIntValue() == 1)
6576 Cond = Cond.getOperand(0);
6579 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6580 // setting operand in place of the X86ISD::SETCC.
6581 if (Cond.getOpcode() == X86ISD::SETCC ||
6582 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6583 CC = Cond.getOperand(0);
6585 SDValue Cmp = Cond.getOperand(1);
6586 unsigned Opc = Cmp.getOpcode();
6587 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6588 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6592 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6596 // These can only come from an arithmetic instruction with overflow,
6597 // e.g. SADDO, UADDO.
6598 Cond = Cond.getNode()->getOperand(1);
6605 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6606 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6607 if (CondOpc == ISD::OR) {
6608 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6609 // two branches instead of an explicit OR instruction with a
6611 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6612 isX86LogicalCmp(Cmp)) {
6613 CC = Cond.getOperand(0).getOperand(0);
6614 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6615 Chain, Dest, CC, Cmp);
6616 CC = Cond.getOperand(1).getOperand(0);
6620 } else { // ISD::AND
6621 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6622 // two branches instead of an explicit AND instruction with a
6623 // separate test. However, we only do this if this block doesn't
6624 // have a fall-through edge, because this requires an explicit
6625 // jmp when the condition is false.
6626 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6627 isX86LogicalCmp(Cmp) &&
6628 Op.getNode()->hasOneUse()) {
6629 X86::CondCode CCode =
6630 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6631 CCode = X86::GetOppositeBranchCondition(CCode);
6632 CC = DAG.getConstant(CCode, MVT::i8);
6633 SDNode *User = *Op.getNode()->use_begin();
6634 // Look for an unconditional branch following this conditional branch.
6635 // We need this because we need to reverse the successors in order
6636 // to implement FCMP_OEQ.
6637 if (User->getOpcode() == ISD::BR) {
6638 SDValue FalseBB = User->getOperand(1);
6640 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
6641 assert(NewBR == User);
6645 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6646 Chain, Dest, CC, Cmp);
6647 X86::CondCode CCode =
6648 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6649 CCode = X86::GetOppositeBranchCondition(CCode);
6650 CC = DAG.getConstant(CCode, MVT::i8);
6656 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6657 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6658 // It should be transformed during dag combiner except when the condition
6659 // is set by a arithmetics with overflow node.
6660 X86::CondCode CCode =
6661 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6662 CCode = X86::GetOppositeBranchCondition(CCode);
6663 CC = DAG.getConstant(CCode, MVT::i8);
6664 Cond = Cond.getOperand(0).getOperand(1);
6670 // Look pass the truncate.
6671 if (Cond.getOpcode() == ISD::TRUNCATE)
6672 Cond = Cond.getOperand(0);
6674 // We know the result of AND is compared against zero. Try to match
6676 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6677 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6678 if (NewSetCC.getNode()) {
6679 CC = NewSetCC.getOperand(0);
6680 Cond = NewSetCC.getOperand(1);
6687 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6688 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6690 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6691 Chain, Dest, CC, Cond);
6695 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6696 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6697 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6698 // that the guard pages used by the OS virtual memory manager are allocated in
6699 // correct sequence.
6701 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6702 SelectionDAG &DAG) const {
6703 assert(Subtarget->isTargetCygMing() &&
6704 "This should be used only on Cygwin/Mingw targets");
6705 DebugLoc dl = Op.getDebugLoc();
6708 SDValue Chain = Op.getOperand(0);
6709 SDValue Size = Op.getOperand(1);
6710 // FIXME: Ensure alignment here
6714 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6716 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6717 Flag = Chain.getValue(1);
6719 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6721 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
6722 Flag = Chain.getValue(1);
6724 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6726 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6727 return DAG.getMergeValues(Ops1, 2, dl);
6730 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
6731 MachineFunction &MF = DAG.getMachineFunction();
6732 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
6734 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6735 DebugLoc dl = Op.getDebugLoc();
6737 if (!Subtarget->is64Bit()) {
6738 // vastart just stores the address of the VarArgsFrameIndex slot into the
6739 // memory location argument.
6740 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6742 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6747 // gp_offset (0 - 6 * 8)
6748 // fp_offset (48 - 48 + 8 * 16)
6749 // overflow_arg_area (point to parameters coming in memory).
6751 SmallVector<SDValue, 8> MemOps;
6752 SDValue FIN = Op.getOperand(1);
6754 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6755 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
6757 FIN, SV, 0, false, false, 0);
6758 MemOps.push_back(Store);
6761 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6762 FIN, DAG.getIntPtrConstant(4));
6763 Store = DAG.getStore(Op.getOperand(0), dl,
6764 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
6766 FIN, SV, 4, false, false, 0);
6767 MemOps.push_back(Store);
6769 // Store ptr to overflow_arg_area
6770 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6771 FIN, DAG.getIntPtrConstant(4));
6772 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
6774 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8,
6776 MemOps.push_back(Store);
6778 // Store ptr to reg_save_area.
6779 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6780 FIN, DAG.getIntPtrConstant(8));
6781 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
6783 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16,
6785 MemOps.push_back(Store);
6786 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6787 &MemOps[0], MemOps.size());
6790 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
6791 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6792 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6794 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
6798 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
6799 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6800 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6801 SDValue Chain = Op.getOperand(0);
6802 SDValue DstPtr = Op.getOperand(1);
6803 SDValue SrcPtr = Op.getOperand(2);
6804 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6805 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6806 DebugLoc dl = Op.getDebugLoc();
6808 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6809 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
6810 false, DstSV, 0, SrcSV, 0);
6814 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
6815 DebugLoc dl = Op.getDebugLoc();
6816 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6818 default: return SDValue(); // Don't custom lower most intrinsics.
6819 // Comparison intrinsics.
6820 case Intrinsic::x86_sse_comieq_ss:
6821 case Intrinsic::x86_sse_comilt_ss:
6822 case Intrinsic::x86_sse_comile_ss:
6823 case Intrinsic::x86_sse_comigt_ss:
6824 case Intrinsic::x86_sse_comige_ss:
6825 case Intrinsic::x86_sse_comineq_ss:
6826 case Intrinsic::x86_sse_ucomieq_ss:
6827 case Intrinsic::x86_sse_ucomilt_ss:
6828 case Intrinsic::x86_sse_ucomile_ss:
6829 case Intrinsic::x86_sse_ucomigt_ss:
6830 case Intrinsic::x86_sse_ucomige_ss:
6831 case Intrinsic::x86_sse_ucomineq_ss:
6832 case Intrinsic::x86_sse2_comieq_sd:
6833 case Intrinsic::x86_sse2_comilt_sd:
6834 case Intrinsic::x86_sse2_comile_sd:
6835 case Intrinsic::x86_sse2_comigt_sd:
6836 case Intrinsic::x86_sse2_comige_sd:
6837 case Intrinsic::x86_sse2_comineq_sd:
6838 case Intrinsic::x86_sse2_ucomieq_sd:
6839 case Intrinsic::x86_sse2_ucomilt_sd:
6840 case Intrinsic::x86_sse2_ucomile_sd:
6841 case Intrinsic::x86_sse2_ucomigt_sd:
6842 case Intrinsic::x86_sse2_ucomige_sd:
6843 case Intrinsic::x86_sse2_ucomineq_sd: {
6845 ISD::CondCode CC = ISD::SETCC_INVALID;
6848 case Intrinsic::x86_sse_comieq_ss:
6849 case Intrinsic::x86_sse2_comieq_sd:
6853 case Intrinsic::x86_sse_comilt_ss:
6854 case Intrinsic::x86_sse2_comilt_sd:
6858 case Intrinsic::x86_sse_comile_ss:
6859 case Intrinsic::x86_sse2_comile_sd:
6863 case Intrinsic::x86_sse_comigt_ss:
6864 case Intrinsic::x86_sse2_comigt_sd:
6868 case Intrinsic::x86_sse_comige_ss:
6869 case Intrinsic::x86_sse2_comige_sd:
6873 case Intrinsic::x86_sse_comineq_ss:
6874 case Intrinsic::x86_sse2_comineq_sd:
6878 case Intrinsic::x86_sse_ucomieq_ss:
6879 case Intrinsic::x86_sse2_ucomieq_sd:
6880 Opc = X86ISD::UCOMI;
6883 case Intrinsic::x86_sse_ucomilt_ss:
6884 case Intrinsic::x86_sse2_ucomilt_sd:
6885 Opc = X86ISD::UCOMI;
6888 case Intrinsic::x86_sse_ucomile_ss:
6889 case Intrinsic::x86_sse2_ucomile_sd:
6890 Opc = X86ISD::UCOMI;
6893 case Intrinsic::x86_sse_ucomigt_ss:
6894 case Intrinsic::x86_sse2_ucomigt_sd:
6895 Opc = X86ISD::UCOMI;
6898 case Intrinsic::x86_sse_ucomige_ss:
6899 case Intrinsic::x86_sse2_ucomige_sd:
6900 Opc = X86ISD::UCOMI;
6903 case Intrinsic::x86_sse_ucomineq_ss:
6904 case Intrinsic::x86_sse2_ucomineq_sd:
6905 Opc = X86ISD::UCOMI;
6910 SDValue LHS = Op.getOperand(1);
6911 SDValue RHS = Op.getOperand(2);
6912 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6913 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6914 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6915 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6916 DAG.getConstant(X86CC, MVT::i8), Cond);
6917 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6919 // ptest intrinsics. The intrinsic these come from are designed to return
6920 // an integer value, not just an instruction so lower it to the ptest
6921 // pattern and a setcc for the result.
6922 case Intrinsic::x86_sse41_ptestz:
6923 case Intrinsic::x86_sse41_ptestc:
6924 case Intrinsic::x86_sse41_ptestnzc:{
6927 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6928 case Intrinsic::x86_sse41_ptestz:
6930 X86CC = X86::COND_E;
6932 case Intrinsic::x86_sse41_ptestc:
6934 X86CC = X86::COND_B;
6936 case Intrinsic::x86_sse41_ptestnzc:
6938 X86CC = X86::COND_A;
6942 SDValue LHS = Op.getOperand(1);
6943 SDValue RHS = Op.getOperand(2);
6944 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6945 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6946 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6947 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6950 // Fix vector shift instructions where the last operand is a non-immediate
6952 case Intrinsic::x86_sse2_pslli_w:
6953 case Intrinsic::x86_sse2_pslli_d:
6954 case Intrinsic::x86_sse2_pslli_q:
6955 case Intrinsic::x86_sse2_psrli_w:
6956 case Intrinsic::x86_sse2_psrli_d:
6957 case Intrinsic::x86_sse2_psrli_q:
6958 case Intrinsic::x86_sse2_psrai_w:
6959 case Intrinsic::x86_sse2_psrai_d:
6960 case Intrinsic::x86_mmx_pslli_w:
6961 case Intrinsic::x86_mmx_pslli_d:
6962 case Intrinsic::x86_mmx_pslli_q:
6963 case Intrinsic::x86_mmx_psrli_w:
6964 case Intrinsic::x86_mmx_psrli_d:
6965 case Intrinsic::x86_mmx_psrli_q:
6966 case Intrinsic::x86_mmx_psrai_w:
6967 case Intrinsic::x86_mmx_psrai_d: {
6968 SDValue ShAmt = Op.getOperand(2);
6969 if (isa<ConstantSDNode>(ShAmt))
6972 unsigned NewIntNo = 0;
6973 EVT ShAmtVT = MVT::v4i32;
6975 case Intrinsic::x86_sse2_pslli_w:
6976 NewIntNo = Intrinsic::x86_sse2_psll_w;
6978 case Intrinsic::x86_sse2_pslli_d:
6979 NewIntNo = Intrinsic::x86_sse2_psll_d;
6981 case Intrinsic::x86_sse2_pslli_q:
6982 NewIntNo = Intrinsic::x86_sse2_psll_q;
6984 case Intrinsic::x86_sse2_psrli_w:
6985 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6987 case Intrinsic::x86_sse2_psrli_d:
6988 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6990 case Intrinsic::x86_sse2_psrli_q:
6991 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6993 case Intrinsic::x86_sse2_psrai_w:
6994 NewIntNo = Intrinsic::x86_sse2_psra_w;
6996 case Intrinsic::x86_sse2_psrai_d:
6997 NewIntNo = Intrinsic::x86_sse2_psra_d;
7000 ShAmtVT = MVT::v2i32;
7002 case Intrinsic::x86_mmx_pslli_w:
7003 NewIntNo = Intrinsic::x86_mmx_psll_w;
7005 case Intrinsic::x86_mmx_pslli_d:
7006 NewIntNo = Intrinsic::x86_mmx_psll_d;
7008 case Intrinsic::x86_mmx_pslli_q:
7009 NewIntNo = Intrinsic::x86_mmx_psll_q;
7011 case Intrinsic::x86_mmx_psrli_w:
7012 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7014 case Intrinsic::x86_mmx_psrli_d:
7015 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7017 case Intrinsic::x86_mmx_psrli_q:
7018 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7020 case Intrinsic::x86_mmx_psrai_w:
7021 NewIntNo = Intrinsic::x86_mmx_psra_w;
7023 case Intrinsic::x86_mmx_psrai_d:
7024 NewIntNo = Intrinsic::x86_mmx_psra_d;
7026 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7032 // The vector shift intrinsics with scalars uses 32b shift amounts but
7033 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7037 ShOps[1] = DAG.getConstant(0, MVT::i32);
7038 if (ShAmtVT == MVT::v4i32) {
7039 ShOps[2] = DAG.getUNDEF(MVT::i32);
7040 ShOps[3] = DAG.getUNDEF(MVT::i32);
7041 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7043 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7046 EVT VT = Op.getValueType();
7047 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7048 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7049 DAG.getConstant(NewIntNo, MVT::i32),
7050 Op.getOperand(1), ShAmt);
7055 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7056 SelectionDAG &DAG) const {
7057 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7058 MFI->setReturnAddressIsTaken(true);
7060 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7061 DebugLoc dl = Op.getDebugLoc();
7064 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7066 DAG.getConstant(TD->getPointerSize(),
7067 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7068 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7069 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7071 NULL, 0, false, false, 0);
7074 // Just load the return address.
7075 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7076 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7077 RetAddrFI, NULL, 0, false, false, 0);
7080 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7081 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7082 MFI->setFrameAddressIsTaken(true);
7084 EVT VT = Op.getValueType();
7085 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7086 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7087 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7088 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7090 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7095 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7096 SelectionDAG &DAG) const {
7097 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7100 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7101 MachineFunction &MF = DAG.getMachineFunction();
7102 SDValue Chain = Op.getOperand(0);
7103 SDValue Offset = Op.getOperand(1);
7104 SDValue Handler = Op.getOperand(2);
7105 DebugLoc dl = Op.getDebugLoc();
7107 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7109 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7111 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7112 DAG.getIntPtrConstant(-TD->getPointerSize()));
7113 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7114 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7115 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7116 MF.getRegInfo().addLiveOut(StoreAddrReg);
7118 return DAG.getNode(X86ISD::EH_RETURN, dl,
7120 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7123 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7124 SelectionDAG &DAG) const {
7125 SDValue Root = Op.getOperand(0);
7126 SDValue Trmp = Op.getOperand(1); // trampoline
7127 SDValue FPtr = Op.getOperand(2); // nested function
7128 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7129 DebugLoc dl = Op.getDebugLoc();
7131 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7133 if (Subtarget->is64Bit()) {
7134 SDValue OutChains[6];
7136 // Large code-model.
7137 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7138 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7140 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7141 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7143 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7145 // Load the pointer to the nested function into R11.
7146 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7147 SDValue Addr = Trmp;
7148 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7149 Addr, TrmpAddr, 0, false, false, 0);
7151 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7152 DAG.getConstant(2, MVT::i64));
7153 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7156 // Load the 'nest' parameter value into R10.
7157 // R10 is specified in X86CallingConv.td
7158 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7159 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7160 DAG.getConstant(10, MVT::i64));
7161 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7162 Addr, TrmpAddr, 10, false, false, 0);
7164 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7165 DAG.getConstant(12, MVT::i64));
7166 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7169 // Jump to the nested function.
7170 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7171 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7172 DAG.getConstant(20, MVT::i64));
7173 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7174 Addr, TrmpAddr, 20, false, false, 0);
7176 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7177 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7178 DAG.getConstant(22, MVT::i64));
7179 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7180 TrmpAddr, 22, false, false, 0);
7183 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7184 return DAG.getMergeValues(Ops, 2, dl);
7186 const Function *Func =
7187 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7188 CallingConv::ID CC = Func->getCallingConv();
7193 llvm_unreachable("Unsupported calling convention");
7194 case CallingConv::C:
7195 case CallingConv::X86_StdCall: {
7196 // Pass 'nest' parameter in ECX.
7197 // Must be kept in sync with X86CallingConv.td
7200 // Check that ECX wasn't needed by an 'inreg' parameter.
7201 const FunctionType *FTy = Func->getFunctionType();
7202 const AttrListPtr &Attrs = Func->getAttributes();
7204 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7205 unsigned InRegCount = 0;
7208 for (FunctionType::param_iterator I = FTy->param_begin(),
7209 E = FTy->param_end(); I != E; ++I, ++Idx)
7210 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7211 // FIXME: should only count parameters that are lowered to integers.
7212 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7214 if (InRegCount > 2) {
7215 report_fatal_error("Nest register in use - reduce number of inreg parameters!");
7220 case CallingConv::X86_FastCall:
7221 case CallingConv::X86_ThisCall:
7222 case CallingConv::Fast:
7223 // Pass 'nest' parameter in EAX.
7224 // Must be kept in sync with X86CallingConv.td
7229 SDValue OutChains[4];
7232 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7233 DAG.getConstant(10, MVT::i32));
7234 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7236 // This is storing the opcode for MOV32ri.
7237 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7238 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7239 OutChains[0] = DAG.getStore(Root, dl,
7240 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7241 Trmp, TrmpAddr, 0, false, false, 0);
7243 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7244 DAG.getConstant(1, MVT::i32));
7245 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7248 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7249 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7250 DAG.getConstant(5, MVT::i32));
7251 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7252 TrmpAddr, 5, false, false, 1);
7254 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7255 DAG.getConstant(6, MVT::i32));
7256 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7260 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7261 return DAG.getMergeValues(Ops, 2, dl);
7265 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7266 SelectionDAG &DAG) const {
7268 The rounding mode is in bits 11:10 of FPSR, and has the following
7275 FLT_ROUNDS, on the other hand, expects the following:
7282 To perform the conversion, we do:
7283 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7286 MachineFunction &MF = DAG.getMachineFunction();
7287 const TargetMachine &TM = MF.getTarget();
7288 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7289 unsigned StackAlignment = TFI.getStackAlignment();
7290 EVT VT = Op.getValueType();
7291 DebugLoc dl = Op.getDebugLoc();
7293 // Save FP Control Word to stack slot
7294 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7295 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7297 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7298 DAG.getEntryNode(), StackSlot);
7300 // Load FP Control Word from stack slot
7301 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7304 // Transform as necessary
7306 DAG.getNode(ISD::SRL, dl, MVT::i16,
7307 DAG.getNode(ISD::AND, dl, MVT::i16,
7308 CWD, DAG.getConstant(0x800, MVT::i16)),
7309 DAG.getConstant(11, MVT::i8));
7311 DAG.getNode(ISD::SRL, dl, MVT::i16,
7312 DAG.getNode(ISD::AND, dl, MVT::i16,
7313 CWD, DAG.getConstant(0x400, MVT::i16)),
7314 DAG.getConstant(9, MVT::i8));
7317 DAG.getNode(ISD::AND, dl, MVT::i16,
7318 DAG.getNode(ISD::ADD, dl, MVT::i16,
7319 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7320 DAG.getConstant(1, MVT::i16)),
7321 DAG.getConstant(3, MVT::i16));
7324 return DAG.getNode((VT.getSizeInBits() < 16 ?
7325 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7328 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
7329 EVT VT = Op.getValueType();
7331 unsigned NumBits = VT.getSizeInBits();
7332 DebugLoc dl = Op.getDebugLoc();
7334 Op = Op.getOperand(0);
7335 if (VT == MVT::i8) {
7336 // Zero extend to i32 since there is not an i8 bsr.
7338 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7341 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7342 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7343 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7345 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7348 DAG.getConstant(NumBits+NumBits-1, OpVT),
7349 DAG.getConstant(X86::COND_E, MVT::i8),
7352 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7354 // Finally xor with NumBits-1.
7355 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7358 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7362 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
7363 EVT VT = Op.getValueType();
7365 unsigned NumBits = VT.getSizeInBits();
7366 DebugLoc dl = Op.getDebugLoc();
7368 Op = Op.getOperand(0);
7369 if (VT == MVT::i8) {
7371 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7374 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7375 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7376 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7378 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7381 DAG.getConstant(NumBits, OpVT),
7382 DAG.getConstant(X86::COND_E, MVT::i8),
7385 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7388 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7392 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
7393 EVT VT = Op.getValueType();
7394 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7395 DebugLoc dl = Op.getDebugLoc();
7397 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7398 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7399 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7400 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7401 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7403 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7404 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7405 // return AloBlo + AloBhi + AhiBlo;
7407 SDValue A = Op.getOperand(0);
7408 SDValue B = Op.getOperand(1);
7410 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7411 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7412 A, DAG.getConstant(32, MVT::i32));
7413 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7414 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7415 B, DAG.getConstant(32, MVT::i32));
7416 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7417 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7419 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7420 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7422 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7423 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7425 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7426 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7427 AloBhi, DAG.getConstant(32, MVT::i32));
7428 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7429 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7430 AhiBlo, DAG.getConstant(32, MVT::i32));
7431 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7432 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7437 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
7438 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7439 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7440 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7441 // has only one use.
7442 SDNode *N = Op.getNode();
7443 SDValue LHS = N->getOperand(0);
7444 SDValue RHS = N->getOperand(1);
7445 unsigned BaseOp = 0;
7447 DebugLoc dl = Op.getDebugLoc();
7449 switch (Op.getOpcode()) {
7450 default: llvm_unreachable("Unknown ovf instruction!");
7452 // A subtract of one will be selected as a INC. Note that INC doesn't
7453 // set CF, so we can't do this for UADDO.
7454 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7455 if (C->getAPIntValue() == 1) {
7456 BaseOp = X86ISD::INC;
7460 BaseOp = X86ISD::ADD;
7464 BaseOp = X86ISD::ADD;
7468 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7469 // set CF, so we can't do this for USUBO.
7470 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7471 if (C->getAPIntValue() == 1) {
7472 BaseOp = X86ISD::DEC;
7476 BaseOp = X86ISD::SUB;
7480 BaseOp = X86ISD::SUB;
7484 BaseOp = X86ISD::SMUL;
7488 BaseOp = X86ISD::UMUL;
7493 // Also sets EFLAGS.
7494 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7495 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7498 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7499 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7501 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7505 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
7506 EVT T = Op.getValueType();
7507 DebugLoc dl = Op.getDebugLoc();
7510 switch(T.getSimpleVT().SimpleTy) {
7512 assert(false && "Invalid value type!");
7513 case MVT::i8: Reg = X86::AL; size = 1; break;
7514 case MVT::i16: Reg = X86::AX; size = 2; break;
7515 case MVT::i32: Reg = X86::EAX; size = 4; break;
7517 assert(Subtarget->is64Bit() && "Node not type legal!");
7518 Reg = X86::RAX; size = 8;
7521 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7522 Op.getOperand(2), SDValue());
7523 SDValue Ops[] = { cpIn.getValue(0),
7526 DAG.getTargetConstant(size, MVT::i8),
7528 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7529 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7531 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7535 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7536 SelectionDAG &DAG) const {
7537 assert(Subtarget->is64Bit() && "Result not type legalized?");
7538 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7539 SDValue TheChain = Op.getOperand(0);
7540 DebugLoc dl = Op.getDebugLoc();
7541 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7542 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7543 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7545 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7546 DAG.getConstant(32, MVT::i8));
7548 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7551 return DAG.getMergeValues(Ops, 2, dl);
7554 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
7555 SelectionDAG &DAG) const {
7556 EVT SrcVT = Op.getOperand(0).getValueType();
7557 EVT DstVT = Op.getValueType();
7558 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
7559 Subtarget->hasMMX() && !DisableMMX) &&
7560 "Unexpected custom BIT_CONVERT");
7561 assert((DstVT == MVT::i64 ||
7562 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
7563 "Unexpected custom BIT_CONVERT");
7564 // i64 <=> MMX conversions are Legal.
7565 if (SrcVT==MVT::i64 && DstVT.isVector())
7567 if (DstVT==MVT::i64 && SrcVT.isVector())
7569 // MMX <=> MMX conversions are Legal.
7570 if (SrcVT.isVector() && DstVT.isVector())
7572 // All other conversions need to be expanded.
7575 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
7576 SDNode *Node = Op.getNode();
7577 DebugLoc dl = Node->getDebugLoc();
7578 EVT T = Node->getValueType(0);
7579 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7580 DAG.getConstant(0, T), Node->getOperand(2));
7581 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7582 cast<AtomicSDNode>(Node)->getMemoryVT(),
7583 Node->getOperand(0),
7584 Node->getOperand(1), negOp,
7585 cast<AtomicSDNode>(Node)->getSrcValue(),
7586 cast<AtomicSDNode>(Node)->getAlignment());
7589 /// LowerOperation - Provide custom lowering hooks for some operations.
7591 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7592 switch (Op.getOpcode()) {
7593 default: llvm_unreachable("Should not custom lower this!");
7594 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7595 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7596 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7597 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7598 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7599 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7600 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7601 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7602 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7603 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7604 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7605 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7606 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7607 case ISD::SHL_PARTS:
7608 case ISD::SRA_PARTS:
7609 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7610 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7611 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7612 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7613 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7614 case ISD::FABS: return LowerFABS(Op, DAG);
7615 case ISD::FNEG: return LowerFNEG(Op, DAG);
7616 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7617 case ISD::SETCC: return LowerSETCC(Op, DAG);
7618 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7619 case ISD::SELECT: return LowerSELECT(Op, DAG);
7620 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7621 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7622 case ISD::VASTART: return LowerVASTART(Op, DAG);
7623 case ISD::VAARG: return LowerVAARG(Op, DAG);
7624 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7625 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7626 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7627 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7628 case ISD::FRAME_TO_ARGS_OFFSET:
7629 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7630 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7631 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7632 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7633 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7634 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7635 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7636 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7642 case ISD::UMULO: return LowerXALUO(Op, DAG);
7643 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7644 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
7648 void X86TargetLowering::
7649 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7650 SelectionDAG &DAG, unsigned NewOp) const {
7651 EVT T = Node->getValueType(0);
7652 DebugLoc dl = Node->getDebugLoc();
7653 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7655 SDValue Chain = Node->getOperand(0);
7656 SDValue In1 = Node->getOperand(1);
7657 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7658 Node->getOperand(2), DAG.getIntPtrConstant(0));
7659 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7660 Node->getOperand(2), DAG.getIntPtrConstant(1));
7661 SDValue Ops[] = { Chain, In1, In2L, In2H };
7662 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7664 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7665 cast<MemSDNode>(Node)->getMemOperand());
7666 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7667 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7668 Results.push_back(Result.getValue(2));
7671 /// ReplaceNodeResults - Replace a node with an illegal result type
7672 /// with a new node built out of custom code.
7673 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7674 SmallVectorImpl<SDValue>&Results,
7675 SelectionDAG &DAG) const {
7676 DebugLoc dl = N->getDebugLoc();
7677 switch (N->getOpcode()) {
7679 assert(false && "Do not know how to custom type legalize this operation!");
7681 case ISD::FP_TO_SINT: {
7682 std::pair<SDValue,SDValue> Vals =
7683 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7684 SDValue FIST = Vals.first, StackSlot = Vals.second;
7685 if (FIST.getNode() != 0) {
7686 EVT VT = N->getValueType(0);
7687 // Return a load from the stack slot.
7688 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7693 case ISD::READCYCLECOUNTER: {
7694 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7695 SDValue TheChain = N->getOperand(0);
7696 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7697 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7699 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7701 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7702 SDValue Ops[] = { eax, edx };
7703 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7704 Results.push_back(edx.getValue(1));
7707 case ISD::ATOMIC_CMP_SWAP: {
7708 EVT T = N->getValueType(0);
7709 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7710 SDValue cpInL, cpInH;
7711 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7712 DAG.getConstant(0, MVT::i32));
7713 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7714 DAG.getConstant(1, MVT::i32));
7715 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7716 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7718 SDValue swapInL, swapInH;
7719 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7720 DAG.getConstant(0, MVT::i32));
7721 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7722 DAG.getConstant(1, MVT::i32));
7723 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7725 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7726 swapInL.getValue(1));
7727 SDValue Ops[] = { swapInH.getValue(0),
7729 swapInH.getValue(1) };
7730 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7731 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7732 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7733 MVT::i32, Result.getValue(1));
7734 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7735 MVT::i32, cpOutL.getValue(2));
7736 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7737 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7738 Results.push_back(cpOutH.getValue(1));
7741 case ISD::ATOMIC_LOAD_ADD:
7742 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7744 case ISD::ATOMIC_LOAD_AND:
7745 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7747 case ISD::ATOMIC_LOAD_NAND:
7748 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7750 case ISD::ATOMIC_LOAD_OR:
7751 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7753 case ISD::ATOMIC_LOAD_SUB:
7754 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7756 case ISD::ATOMIC_LOAD_XOR:
7757 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7759 case ISD::ATOMIC_SWAP:
7760 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7765 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7767 default: return NULL;
7768 case X86ISD::BSF: return "X86ISD::BSF";
7769 case X86ISD::BSR: return "X86ISD::BSR";
7770 case X86ISD::SHLD: return "X86ISD::SHLD";
7771 case X86ISD::SHRD: return "X86ISD::SHRD";
7772 case X86ISD::FAND: return "X86ISD::FAND";
7773 case X86ISD::FOR: return "X86ISD::FOR";
7774 case X86ISD::FXOR: return "X86ISD::FXOR";
7775 case X86ISD::FSRL: return "X86ISD::FSRL";
7776 case X86ISD::FILD: return "X86ISD::FILD";
7777 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7778 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7779 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7780 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7781 case X86ISD::FLD: return "X86ISD::FLD";
7782 case X86ISD::FST: return "X86ISD::FST";
7783 case X86ISD::CALL: return "X86ISD::CALL";
7784 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7785 case X86ISD::BT: return "X86ISD::BT";
7786 case X86ISD::CMP: return "X86ISD::CMP";
7787 case X86ISD::COMI: return "X86ISD::COMI";
7788 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7789 case X86ISD::SETCC: return "X86ISD::SETCC";
7790 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7791 case X86ISD::CMOV: return "X86ISD::CMOV";
7792 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7793 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7794 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7795 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7796 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7797 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7798 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7799 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7800 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7801 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7802 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7803 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7804 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
7805 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7806 case X86ISD::FMAX: return "X86ISD::FMAX";
7807 case X86ISD::FMIN: return "X86ISD::FMIN";
7808 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7809 case X86ISD::FRCP: return "X86ISD::FRCP";
7810 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7811 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
7812 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7813 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7814 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7815 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7816 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7817 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7818 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7819 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7820 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7821 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7822 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7823 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7824 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7825 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7826 case X86ISD::VSHL: return "X86ISD::VSHL";
7827 case X86ISD::VSRL: return "X86ISD::VSRL";
7828 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7829 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7830 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7831 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7832 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7833 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7834 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7835 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7836 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7837 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7838 case X86ISD::ADD: return "X86ISD::ADD";
7839 case X86ISD::SUB: return "X86ISD::SUB";
7840 case X86ISD::SMUL: return "X86ISD::SMUL";
7841 case X86ISD::UMUL: return "X86ISD::UMUL";
7842 case X86ISD::INC: return "X86ISD::INC";
7843 case X86ISD::DEC: return "X86ISD::DEC";
7844 case X86ISD::OR: return "X86ISD::OR";
7845 case X86ISD::XOR: return "X86ISD::XOR";
7846 case X86ISD::AND: return "X86ISD::AND";
7847 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7848 case X86ISD::PTEST: return "X86ISD::PTEST";
7849 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7850 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
7854 // isLegalAddressingMode - Return true if the addressing mode represented
7855 // by AM is legal for this target, for a load/store of the specified type.
7856 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7857 const Type *Ty) const {
7858 // X86 supports extremely general addressing modes.
7859 CodeModel::Model M = getTargetMachine().getCodeModel();
7861 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7862 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7867 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7869 // If a reference to this global requires an extra load, we can't fold it.
7870 if (isGlobalStubReference(GVFlags))
7873 // If BaseGV requires a register for the PIC base, we cannot also have a
7874 // BaseReg specified.
7875 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7878 // If lower 4G is not available, then we must use rip-relative addressing.
7879 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7889 // These scales always work.
7894 // These scales are formed with basereg+scalereg. Only accept if there is
7899 default: // Other stuff never works.
7907 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7908 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7910 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7911 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7912 if (NumBits1 <= NumBits2)
7917 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7918 if (!VT1.isInteger() || !VT2.isInteger())
7920 unsigned NumBits1 = VT1.getSizeInBits();
7921 unsigned NumBits2 = VT2.getSizeInBits();
7922 if (NumBits1 <= NumBits2)
7927 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7928 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7929 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7932 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7933 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7934 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7937 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7938 // i16 instructions are longer (0x66 prefix) and potentially slower.
7939 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7942 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7943 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7944 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7945 /// are assumed to be legal.
7947 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7949 // Very little shuffling can be done for 64-bit vectors right now.
7950 if (VT.getSizeInBits() == 64)
7951 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
7953 // FIXME: pshufb, blends, shifts.
7954 return (VT.getVectorNumElements() == 2 ||
7955 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7956 isMOVLMask(M, VT) ||
7957 isSHUFPMask(M, VT) ||
7958 isPSHUFDMask(M, VT) ||
7959 isPSHUFHWMask(M, VT) ||
7960 isPSHUFLWMask(M, VT) ||
7961 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7962 isUNPCKLMask(M, VT) ||
7963 isUNPCKHMask(M, VT) ||
7964 isUNPCKL_v_undef_Mask(M, VT) ||
7965 isUNPCKH_v_undef_Mask(M, VT));
7969 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7971 unsigned NumElts = VT.getVectorNumElements();
7972 // FIXME: This collection of masks seems suspect.
7975 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7976 return (isMOVLMask(Mask, VT) ||
7977 isCommutedMOVLMask(Mask, VT, true) ||
7978 isSHUFPMask(Mask, VT) ||
7979 isCommutedSHUFPMask(Mask, VT));
7984 //===----------------------------------------------------------------------===//
7985 // X86 Scheduler Hooks
7986 //===----------------------------------------------------------------------===//
7988 // private utility function
7990 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7991 MachineBasicBlock *MBB,
7999 TargetRegisterClass *RC,
8000 bool invSrc) const {
8001 // For the atomic bitwise operator, we generate
8004 // ld t1 = [bitinstr.addr]
8005 // op t2 = t1, [bitinstr.val]
8007 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8009 // fallthrough -->nextMBB
8010 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8011 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8012 MachineFunction::iterator MBBIter = MBB;
8015 /// First build the CFG
8016 MachineFunction *F = MBB->getParent();
8017 MachineBasicBlock *thisMBB = MBB;
8018 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8019 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8020 F->insert(MBBIter, newMBB);
8021 F->insert(MBBIter, nextMBB);
8023 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8024 nextMBB->splice(nextMBB->begin(), thisMBB,
8025 llvm::next(MachineBasicBlock::iterator(bInstr)),
8027 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8029 // Update thisMBB to fall through to newMBB
8030 thisMBB->addSuccessor(newMBB);
8032 // newMBB jumps to itself and fall through to nextMBB
8033 newMBB->addSuccessor(nextMBB);
8034 newMBB->addSuccessor(newMBB);
8036 // Insert instructions into newMBB based on incoming instruction
8037 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8038 "unexpected number of operands");
8039 DebugLoc dl = bInstr->getDebugLoc();
8040 MachineOperand& destOper = bInstr->getOperand(0);
8041 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8042 int numArgs = bInstr->getNumOperands() - 1;
8043 for (int i=0; i < numArgs; ++i)
8044 argOpers[i] = &bInstr->getOperand(i+1);
8046 // x86 address has 4 operands: base, index, scale, and displacement
8047 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8048 int valArgIndx = lastAddrIndx + 1;
8050 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8051 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
8052 for (int i=0; i <= lastAddrIndx; ++i)
8053 (*MIB).addOperand(*argOpers[i]);
8055 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
8057 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
8062 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8063 assert((argOpers[valArgIndx]->isReg() ||
8064 argOpers[valArgIndx]->isImm()) &&
8066 if (argOpers[valArgIndx]->isReg())
8067 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
8069 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
8071 (*MIB).addOperand(*argOpers[valArgIndx]);
8073 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
8076 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
8077 for (int i=0; i <= lastAddrIndx; ++i)
8078 (*MIB).addOperand(*argOpers[i]);
8080 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8081 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8082 bInstr->memoperands_end());
8084 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
8088 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8090 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8094 // private utility function: 64 bit atomics on 32 bit host.
8096 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8097 MachineBasicBlock *MBB,
8102 bool invSrc) const {
8103 // For the atomic bitwise operator, we generate
8104 // thisMBB (instructions are in pairs, except cmpxchg8b)
8105 // ld t1,t2 = [bitinstr.addr]
8107 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8108 // op t5, t6 <- out1, out2, [bitinstr.val]
8109 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8110 // mov ECX, EBX <- t5, t6
8111 // mov EAX, EDX <- t1, t2
8112 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8113 // mov t3, t4 <- EAX, EDX
8115 // result in out1, out2
8116 // fallthrough -->nextMBB
8118 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8119 const unsigned LoadOpc = X86::MOV32rm;
8120 const unsigned copyOpc = X86::MOV32rr;
8121 const unsigned NotOpc = X86::NOT32r;
8122 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8123 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8124 MachineFunction::iterator MBBIter = MBB;
8127 /// First build the CFG
8128 MachineFunction *F = MBB->getParent();
8129 MachineBasicBlock *thisMBB = MBB;
8130 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8131 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8132 F->insert(MBBIter, newMBB);
8133 F->insert(MBBIter, nextMBB);
8135 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8136 nextMBB->splice(nextMBB->begin(), thisMBB,
8137 llvm::next(MachineBasicBlock::iterator(bInstr)),
8139 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8141 // Update thisMBB to fall through to newMBB
8142 thisMBB->addSuccessor(newMBB);
8144 // newMBB jumps to itself and fall through to nextMBB
8145 newMBB->addSuccessor(nextMBB);
8146 newMBB->addSuccessor(newMBB);
8148 DebugLoc dl = bInstr->getDebugLoc();
8149 // Insert instructions into newMBB based on incoming instruction
8150 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8151 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
8152 "unexpected number of operands");
8153 MachineOperand& dest1Oper = bInstr->getOperand(0);
8154 MachineOperand& dest2Oper = bInstr->getOperand(1);
8155 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8156 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
8157 argOpers[i] = &bInstr->getOperand(i+2);
8159 // We use some of the operands multiple times, so conservatively just
8160 // clear any kill flags that might be present.
8161 if (argOpers[i]->isReg() && argOpers[i]->isUse())
8162 argOpers[i]->setIsKill(false);
8165 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8166 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8168 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8169 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8170 for (int i=0; i <= lastAddrIndx; ++i)
8171 (*MIB).addOperand(*argOpers[i]);
8172 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8173 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8174 // add 4 to displacement.
8175 for (int i=0; i <= lastAddrIndx-2; ++i)
8176 (*MIB).addOperand(*argOpers[i]);
8177 MachineOperand newOp3 = *(argOpers[3]);
8179 newOp3.setImm(newOp3.getImm()+4);
8181 newOp3.setOffset(newOp3.getOffset()+4);
8182 (*MIB).addOperand(newOp3);
8183 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8185 // t3/4 are defined later, at the bottom of the loop
8186 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8187 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8188 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8189 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8190 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8191 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8193 // The subsequent operations should be using the destination registers of
8194 //the PHI instructions.
8196 t1 = F->getRegInfo().createVirtualRegister(RC);
8197 t2 = F->getRegInfo().createVirtualRegister(RC);
8198 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8199 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8201 t1 = dest1Oper.getReg();
8202 t2 = dest2Oper.getReg();
8205 int valArgIndx = lastAddrIndx + 1;
8206 assert((argOpers[valArgIndx]->isReg() ||
8207 argOpers[valArgIndx]->isImm()) &&
8209 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8210 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8211 if (argOpers[valArgIndx]->isReg())
8212 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8214 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8215 if (regOpcL != X86::MOV32rr)
8217 (*MIB).addOperand(*argOpers[valArgIndx]);
8218 assert(argOpers[valArgIndx + 1]->isReg() ==
8219 argOpers[valArgIndx]->isReg());
8220 assert(argOpers[valArgIndx + 1]->isImm() ==
8221 argOpers[valArgIndx]->isImm());
8222 if (argOpers[valArgIndx + 1]->isReg())
8223 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8225 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8226 if (regOpcH != X86::MOV32rr)
8228 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8230 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8232 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8235 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8237 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8240 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8241 for (int i=0; i <= lastAddrIndx; ++i)
8242 (*MIB).addOperand(*argOpers[i]);
8244 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8245 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8246 bInstr->memoperands_end());
8248 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8249 MIB.addReg(X86::EAX);
8250 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8251 MIB.addReg(X86::EDX);
8254 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8256 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8260 // private utility function
8262 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8263 MachineBasicBlock *MBB,
8264 unsigned cmovOpc) const {
8265 // For the atomic min/max operator, we generate
8268 // ld t1 = [min/max.addr]
8269 // mov t2 = [min/max.val]
8271 // cmov[cond] t2 = t1
8273 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8275 // fallthrough -->nextMBB
8277 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8278 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8279 MachineFunction::iterator MBBIter = MBB;
8282 /// First build the CFG
8283 MachineFunction *F = MBB->getParent();
8284 MachineBasicBlock *thisMBB = MBB;
8285 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8286 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8287 F->insert(MBBIter, newMBB);
8288 F->insert(MBBIter, nextMBB);
8290 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8291 nextMBB->splice(nextMBB->begin(), thisMBB,
8292 llvm::next(MachineBasicBlock::iterator(mInstr)),
8294 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8296 // Update thisMBB to fall through to newMBB
8297 thisMBB->addSuccessor(newMBB);
8299 // newMBB jumps to newMBB and fall through to nextMBB
8300 newMBB->addSuccessor(nextMBB);
8301 newMBB->addSuccessor(newMBB);
8303 DebugLoc dl = mInstr->getDebugLoc();
8304 // Insert instructions into newMBB based on incoming instruction
8305 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8306 "unexpected number of operands");
8307 MachineOperand& destOper = mInstr->getOperand(0);
8308 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8309 int numArgs = mInstr->getNumOperands() - 1;
8310 for (int i=0; i < numArgs; ++i)
8311 argOpers[i] = &mInstr->getOperand(i+1);
8313 // x86 address has 4 operands: base, index, scale, and displacement
8314 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8315 int valArgIndx = lastAddrIndx + 1;
8317 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8318 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8319 for (int i=0; i <= lastAddrIndx; ++i)
8320 (*MIB).addOperand(*argOpers[i]);
8322 // We only support register and immediate values
8323 assert((argOpers[valArgIndx]->isReg() ||
8324 argOpers[valArgIndx]->isImm()) &&
8327 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8328 if (argOpers[valArgIndx]->isReg())
8329 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8331 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8332 (*MIB).addOperand(*argOpers[valArgIndx]);
8334 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8337 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8342 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8343 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8347 // Cmp and exchange if none has modified the memory location
8348 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8349 for (int i=0; i <= lastAddrIndx; ++i)
8350 (*MIB).addOperand(*argOpers[i]);
8352 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8353 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8354 mInstr->memoperands_end());
8356 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8357 MIB.addReg(X86::EAX);
8360 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8362 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
8366 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8367 // all of this code can be replaced with that in the .td file.
8369 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8370 unsigned numArgs, bool memArg) const {
8372 DebugLoc dl = MI->getDebugLoc();
8373 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8377 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8379 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8381 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8383 for (unsigned i = 0; i < numArgs; ++i) {
8384 MachineOperand &Op = MI->getOperand(i+1);
8386 if (!(Op.isReg() && Op.isImplicit()))
8390 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8393 MI->eraseFromParent();
8399 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8401 MachineBasicBlock *MBB) const {
8402 // Emit code to save XMM registers to the stack. The ABI says that the
8403 // number of registers to save is given in %al, so it's theoretically
8404 // possible to do an indirect jump trick to avoid saving all of them,
8405 // however this code takes a simpler approach and just executes all
8406 // of the stores if %al is non-zero. It's less code, and it's probably
8407 // easier on the hardware branch predictor, and stores aren't all that
8408 // expensive anyway.
8410 // Create the new basic blocks. One block contains all the XMM stores,
8411 // and one block is the final destination regardless of whether any
8412 // stores were performed.
8413 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8414 MachineFunction *F = MBB->getParent();
8415 MachineFunction::iterator MBBIter = MBB;
8417 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8418 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8419 F->insert(MBBIter, XMMSaveMBB);
8420 F->insert(MBBIter, EndMBB);
8422 // Transfer the remainder of MBB and its successor edges to EndMBB.
8423 EndMBB->splice(EndMBB->begin(), MBB,
8424 llvm::next(MachineBasicBlock::iterator(MI)),
8426 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
8428 // The original block will now fall through to the XMM save block.
8429 MBB->addSuccessor(XMMSaveMBB);
8430 // The XMMSaveMBB will fall through to the end block.
8431 XMMSaveMBB->addSuccessor(EndMBB);
8433 // Now add the instructions.
8434 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8435 DebugLoc DL = MI->getDebugLoc();
8437 unsigned CountReg = MI->getOperand(0).getReg();
8438 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8439 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8441 if (!Subtarget->isTargetWin64()) {
8442 // If %al is 0, branch around the XMM save block.
8443 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8444 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8445 MBB->addSuccessor(EndMBB);
8448 // In the XMM save block, save all the XMM argument registers.
8449 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8450 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8451 MachineMemOperand *MMO =
8452 F->getMachineMemOperand(
8453 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8454 MachineMemOperand::MOStore, Offset,
8455 /*Size=*/16, /*Align=*/16);
8456 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8457 .addFrameIndex(RegSaveFrameIndex)
8458 .addImm(/*Scale=*/1)
8459 .addReg(/*IndexReg=*/0)
8460 .addImm(/*Disp=*/Offset)
8461 .addReg(/*Segment=*/0)
8462 .addReg(MI->getOperand(i).getReg())
8463 .addMemOperand(MMO);
8466 MI->eraseFromParent(); // The pseudo instruction is gone now.
8472 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8473 MachineBasicBlock *BB) const {
8474 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8475 DebugLoc DL = MI->getDebugLoc();
8477 // To "insert" a SELECT_CC instruction, we actually have to insert the
8478 // diamond control-flow pattern. The incoming instruction knows the
8479 // destination vreg to set, the condition code register to branch on, the
8480 // true/false values to select between, and a branch opcode to use.
8481 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8482 MachineFunction::iterator It = BB;
8488 // cmpTY ccX, r1, r2
8490 // fallthrough --> copy0MBB
8491 MachineBasicBlock *thisMBB = BB;
8492 MachineFunction *F = BB->getParent();
8493 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8494 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8495 F->insert(It, copy0MBB);
8496 F->insert(It, sinkMBB);
8498 // If the EFLAGS register isn't dead in the terminator, then claim that it's
8499 // live into the sink and copy blocks.
8500 const MachineFunction *MF = BB->getParent();
8501 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
8502 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
8504 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
8505 const MachineOperand &MO = MI->getOperand(I);
8506 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
8507 unsigned Reg = MO.getReg();
8508 if (Reg != X86::EFLAGS) continue;
8509 copy0MBB->addLiveIn(Reg);
8510 sinkMBB->addLiveIn(Reg);
8513 // Transfer the remainder of BB and its successor edges to sinkMBB.
8514 sinkMBB->splice(sinkMBB->begin(), BB,
8515 llvm::next(MachineBasicBlock::iterator(MI)),
8517 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8519 // Add the true and fallthrough blocks as its successors.
8520 BB->addSuccessor(copy0MBB);
8521 BB->addSuccessor(sinkMBB);
8523 // Create the conditional branch instruction.
8525 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8526 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8529 // %FalseValue = ...
8530 // # fallthrough to sinkMBB
8531 copy0MBB->addSuccessor(sinkMBB);
8534 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8536 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8537 TII->get(X86::PHI), MI->getOperand(0).getReg())
8538 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8539 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8541 MI->eraseFromParent(); // The pseudo instruction is gone now.
8546 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
8547 MachineBasicBlock *BB) const {
8548 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8549 DebugLoc DL = MI->getDebugLoc();
8551 // The lowering is pretty easy: we're just emitting the call to _alloca. The
8552 // non-trivial part is impdef of ESP.
8553 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
8556 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
8557 .addExternalSymbol("_alloca")
8558 .addReg(X86::EAX, RegState::Implicit)
8559 .addReg(X86::ESP, RegState::Implicit)
8560 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
8561 .addReg(X86::ESP, RegState::Define | RegState::Implicit);
8563 MI->eraseFromParent(); // The pseudo instruction is gone now.
8568 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
8569 MachineBasicBlock *BB) const {
8570 // This is pretty easy. We're taking the value that we received from
8571 // our load from the relocation, sticking it in either RDI (x86-64)
8572 // or EAX and doing an indirect call. The return value will then
8573 // be in the normal return register.
8574 const X86InstrInfo *TII
8575 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
8576 DebugLoc DL = MI->getDebugLoc();
8577 MachineFunction *F = BB->getParent();
8579 assert(MI->getOperand(3).isGlobal() && "This should be a global");
8581 if (Subtarget->is64Bit()) {
8582 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8583 TII->get(X86::MOV64rm), X86::RDI)
8585 .addImm(0).addReg(0)
8586 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8587 MI->getOperand(3).getTargetFlags())
8589 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
8590 addDirectMem(MIB, X86::RDI);
8591 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
8592 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8593 TII->get(X86::MOV32rm), X86::EAX)
8595 .addImm(0).addReg(0)
8596 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8597 MI->getOperand(3).getTargetFlags())
8599 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8600 addDirectMem(MIB, X86::EAX);
8602 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
8603 TII->get(X86::MOV32rm), X86::EAX)
8604 .addReg(TII->getGlobalBaseReg(F))
8605 .addImm(0).addReg(0)
8606 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
8607 MI->getOperand(3).getTargetFlags())
8609 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
8610 addDirectMem(MIB, X86::EAX);
8613 MI->eraseFromParent(); // The pseudo instruction is gone now.
8618 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8619 MachineBasicBlock *BB) const {
8620 switch (MI->getOpcode()) {
8621 default: assert(false && "Unexpected instr type to insert");
8622 case X86::MINGW_ALLOCA:
8623 return EmitLoweredMingwAlloca(MI, BB);
8624 case X86::TLSCall_32:
8625 case X86::TLSCall_64:
8626 return EmitLoweredTLSCall(MI, BB);
8628 case X86::CMOV_V1I64:
8629 case X86::CMOV_FR32:
8630 case X86::CMOV_FR64:
8631 case X86::CMOV_V4F32:
8632 case X86::CMOV_V2F64:
8633 case X86::CMOV_V2I64:
8634 case X86::CMOV_GR16:
8635 case X86::CMOV_GR32:
8636 case X86::CMOV_RFP32:
8637 case X86::CMOV_RFP64:
8638 case X86::CMOV_RFP80:
8639 return EmitLoweredSelect(MI, BB);
8641 case X86::FP32_TO_INT16_IN_MEM:
8642 case X86::FP32_TO_INT32_IN_MEM:
8643 case X86::FP32_TO_INT64_IN_MEM:
8644 case X86::FP64_TO_INT16_IN_MEM:
8645 case X86::FP64_TO_INT32_IN_MEM:
8646 case X86::FP64_TO_INT64_IN_MEM:
8647 case X86::FP80_TO_INT16_IN_MEM:
8648 case X86::FP80_TO_INT32_IN_MEM:
8649 case X86::FP80_TO_INT64_IN_MEM: {
8650 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8651 DebugLoc DL = MI->getDebugLoc();
8653 // Change the floating point control register to use "round towards zero"
8654 // mode when truncating to an integer value.
8655 MachineFunction *F = BB->getParent();
8656 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8657 addFrameReference(BuildMI(*BB, MI, DL,
8658 TII->get(X86::FNSTCW16m)), CWFrameIdx);
8660 // Load the old value of the high byte of the control word...
8662 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8663 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
8666 // Set the high part to be round to zero...
8667 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8670 // Reload the modified control word now...
8671 addFrameReference(BuildMI(*BB, MI, DL,
8672 TII->get(X86::FLDCW16m)), CWFrameIdx);
8674 // Restore the memory image of control word to original value
8675 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8678 // Get the X86 opcode to use.
8680 switch (MI->getOpcode()) {
8681 default: llvm_unreachable("illegal opcode!");
8682 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8683 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8684 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8685 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8686 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8687 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8688 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8689 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8690 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8694 MachineOperand &Op = MI->getOperand(0);
8696 AM.BaseType = X86AddressMode::RegBase;
8697 AM.Base.Reg = Op.getReg();
8699 AM.BaseType = X86AddressMode::FrameIndexBase;
8700 AM.Base.FrameIndex = Op.getIndex();
8702 Op = MI->getOperand(1);
8704 AM.Scale = Op.getImm();
8705 Op = MI->getOperand(2);
8707 AM.IndexReg = Op.getImm();
8708 Op = MI->getOperand(3);
8709 if (Op.isGlobal()) {
8710 AM.GV = Op.getGlobal();
8712 AM.Disp = Op.getImm();
8714 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
8715 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
8717 // Reload the original control word now.
8718 addFrameReference(BuildMI(*BB, MI, DL,
8719 TII->get(X86::FLDCW16m)), CWFrameIdx);
8721 MI->eraseFromParent(); // The pseudo instruction is gone now.
8724 // String/text processing lowering.
8725 case X86::PCMPISTRM128REG:
8726 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8727 case X86::PCMPISTRM128MEM:
8728 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8729 case X86::PCMPESTRM128REG:
8730 return EmitPCMP(MI, BB, 5, false /* in mem */);
8731 case X86::PCMPESTRM128MEM:
8732 return EmitPCMP(MI, BB, 5, true /* in mem */);
8735 case X86::ATOMAND32:
8736 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8737 X86::AND32ri, X86::MOV32rm,
8738 X86::LCMPXCHG32, X86::MOV32rr,
8739 X86::NOT32r, X86::EAX,
8740 X86::GR32RegisterClass);
8742 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8743 X86::OR32ri, X86::MOV32rm,
8744 X86::LCMPXCHG32, X86::MOV32rr,
8745 X86::NOT32r, X86::EAX,
8746 X86::GR32RegisterClass);
8747 case X86::ATOMXOR32:
8748 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8749 X86::XOR32ri, X86::MOV32rm,
8750 X86::LCMPXCHG32, X86::MOV32rr,
8751 X86::NOT32r, X86::EAX,
8752 X86::GR32RegisterClass);
8753 case X86::ATOMNAND32:
8754 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8755 X86::AND32ri, X86::MOV32rm,
8756 X86::LCMPXCHG32, X86::MOV32rr,
8757 X86::NOT32r, X86::EAX,
8758 X86::GR32RegisterClass, true);
8759 case X86::ATOMMIN32:
8760 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8761 case X86::ATOMMAX32:
8762 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8763 case X86::ATOMUMIN32:
8764 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8765 case X86::ATOMUMAX32:
8766 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8768 case X86::ATOMAND16:
8769 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8770 X86::AND16ri, X86::MOV16rm,
8771 X86::LCMPXCHG16, X86::MOV16rr,
8772 X86::NOT16r, X86::AX,
8773 X86::GR16RegisterClass);
8775 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8776 X86::OR16ri, X86::MOV16rm,
8777 X86::LCMPXCHG16, X86::MOV16rr,
8778 X86::NOT16r, X86::AX,
8779 X86::GR16RegisterClass);
8780 case X86::ATOMXOR16:
8781 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8782 X86::XOR16ri, X86::MOV16rm,
8783 X86::LCMPXCHG16, X86::MOV16rr,
8784 X86::NOT16r, X86::AX,
8785 X86::GR16RegisterClass);
8786 case X86::ATOMNAND16:
8787 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8788 X86::AND16ri, X86::MOV16rm,
8789 X86::LCMPXCHG16, X86::MOV16rr,
8790 X86::NOT16r, X86::AX,
8791 X86::GR16RegisterClass, true);
8792 case X86::ATOMMIN16:
8793 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8794 case X86::ATOMMAX16:
8795 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8796 case X86::ATOMUMIN16:
8797 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8798 case X86::ATOMUMAX16:
8799 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8802 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8803 X86::AND8ri, X86::MOV8rm,
8804 X86::LCMPXCHG8, X86::MOV8rr,
8805 X86::NOT8r, X86::AL,
8806 X86::GR8RegisterClass);
8808 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8809 X86::OR8ri, X86::MOV8rm,
8810 X86::LCMPXCHG8, X86::MOV8rr,
8811 X86::NOT8r, X86::AL,
8812 X86::GR8RegisterClass);
8814 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8815 X86::XOR8ri, X86::MOV8rm,
8816 X86::LCMPXCHG8, X86::MOV8rr,
8817 X86::NOT8r, X86::AL,
8818 X86::GR8RegisterClass);
8819 case X86::ATOMNAND8:
8820 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8821 X86::AND8ri, X86::MOV8rm,
8822 X86::LCMPXCHG8, X86::MOV8rr,
8823 X86::NOT8r, X86::AL,
8824 X86::GR8RegisterClass, true);
8825 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8826 // This group is for 64-bit host.
8827 case X86::ATOMAND64:
8828 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8829 X86::AND64ri32, X86::MOV64rm,
8830 X86::LCMPXCHG64, X86::MOV64rr,
8831 X86::NOT64r, X86::RAX,
8832 X86::GR64RegisterClass);
8834 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8835 X86::OR64ri32, X86::MOV64rm,
8836 X86::LCMPXCHG64, X86::MOV64rr,
8837 X86::NOT64r, X86::RAX,
8838 X86::GR64RegisterClass);
8839 case X86::ATOMXOR64:
8840 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8841 X86::XOR64ri32, X86::MOV64rm,
8842 X86::LCMPXCHG64, X86::MOV64rr,
8843 X86::NOT64r, X86::RAX,
8844 X86::GR64RegisterClass);
8845 case X86::ATOMNAND64:
8846 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8847 X86::AND64ri32, X86::MOV64rm,
8848 X86::LCMPXCHG64, X86::MOV64rr,
8849 X86::NOT64r, X86::RAX,
8850 X86::GR64RegisterClass, true);
8851 case X86::ATOMMIN64:
8852 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8853 case X86::ATOMMAX64:
8854 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8855 case X86::ATOMUMIN64:
8856 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8857 case X86::ATOMUMAX64:
8858 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8860 // This group does 64-bit operations on a 32-bit host.
8861 case X86::ATOMAND6432:
8862 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8863 X86::AND32rr, X86::AND32rr,
8864 X86::AND32ri, X86::AND32ri,
8866 case X86::ATOMOR6432:
8867 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8868 X86::OR32rr, X86::OR32rr,
8869 X86::OR32ri, X86::OR32ri,
8871 case X86::ATOMXOR6432:
8872 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8873 X86::XOR32rr, X86::XOR32rr,
8874 X86::XOR32ri, X86::XOR32ri,
8876 case X86::ATOMNAND6432:
8877 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8878 X86::AND32rr, X86::AND32rr,
8879 X86::AND32ri, X86::AND32ri,
8881 case X86::ATOMADD6432:
8882 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8883 X86::ADD32rr, X86::ADC32rr,
8884 X86::ADD32ri, X86::ADC32ri,
8886 case X86::ATOMSUB6432:
8887 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8888 X86::SUB32rr, X86::SBB32rr,
8889 X86::SUB32ri, X86::SBB32ri,
8891 case X86::ATOMSWAP6432:
8892 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8893 X86::MOV32rr, X86::MOV32rr,
8894 X86::MOV32ri, X86::MOV32ri,
8896 case X86::VASTART_SAVE_XMM_REGS:
8897 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8901 //===----------------------------------------------------------------------===//
8902 // X86 Optimization Hooks
8903 //===----------------------------------------------------------------------===//
8905 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8909 const SelectionDAG &DAG,
8910 unsigned Depth) const {
8911 unsigned Opc = Op.getOpcode();
8912 assert((Opc >= ISD::BUILTIN_OP_END ||
8913 Opc == ISD::INTRINSIC_WO_CHAIN ||
8914 Opc == ISD::INTRINSIC_W_CHAIN ||
8915 Opc == ISD::INTRINSIC_VOID) &&
8916 "Should use MaskedValueIsZero if you don't know whether Op"
8917 " is a target node!");
8919 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8931 // These nodes' second result is a boolean.
8932 if (Op.getResNo() == 0)
8936 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8937 Mask.getBitWidth() - 1);
8942 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8943 /// node is a GlobalAddress + offset.
8944 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8945 const GlobalValue* &GA,
8946 int64_t &Offset) const {
8947 if (N->getOpcode() == X86ISD::Wrapper) {
8948 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8949 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8950 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8954 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8957 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8958 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8959 /// if the load addresses are consecutive, non-overlapping, and in the right
8961 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8962 const TargetLowering &TLI) {
8963 DebugLoc dl = N->getDebugLoc();
8964 EVT VT = N->getValueType(0);
8965 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8967 if (VT.getSizeInBits() != 128)
8970 SmallVector<SDValue, 16> Elts;
8971 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
8972 Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
8974 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
8977 /// PerformShuffleCombine - Detect vector gather/scatter index generation
8978 /// and convert it from being a bunch of shuffles and extracts to a simple
8979 /// store and scalar loads to extract the elements.
8980 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
8981 const TargetLowering &TLI) {
8982 SDValue InputVector = N->getOperand(0);
8984 // Only operate on vectors of 4 elements, where the alternative shuffling
8985 // gets to be more expensive.
8986 if (InputVector.getValueType() != MVT::v4i32)
8989 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
8990 // single use which is a sign-extend or zero-extend, and all elements are
8992 SmallVector<SDNode *, 4> Uses;
8993 unsigned ExtractedElements = 0;
8994 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
8995 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
8996 if (UI.getUse().getResNo() != InputVector.getResNo())
8999 SDNode *Extract = *UI;
9000 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9003 if (Extract->getValueType(0) != MVT::i32)
9005 if (!Extract->hasOneUse())
9007 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
9008 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
9010 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
9013 // Record which element was extracted.
9014 ExtractedElements |=
9015 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
9017 Uses.push_back(Extract);
9020 // If not all the elements were used, this may not be worthwhile.
9021 if (ExtractedElements != 15)
9024 // Ok, we've now decided to do the transformation.
9025 DebugLoc dl = InputVector.getDebugLoc();
9027 // Store the value to a temporary stack slot.
9028 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
9029 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0,
9032 // Replace each use (extract) with a load of the appropriate element.
9033 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
9034 UE = Uses.end(); UI != UE; ++UI) {
9035 SDNode *Extract = *UI;
9037 // Compute the element's address.
9038 SDValue Idx = Extract->getOperand(1);
9040 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
9041 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
9042 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
9044 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr);
9047 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr,
9048 NULL, 0, false, false, 0);
9050 // Replace the exact with the load.
9051 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
9054 // The replacement was made in place; don't return anything.
9058 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
9059 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
9060 const X86Subtarget *Subtarget) {
9061 DebugLoc DL = N->getDebugLoc();
9062 SDValue Cond = N->getOperand(0);
9063 // Get the LHS/RHS of the select.
9064 SDValue LHS = N->getOperand(1);
9065 SDValue RHS = N->getOperand(2);
9067 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
9068 // instructions match the semantics of the common C idiom x<y?x:y but not
9069 // x<=y?x:y, because of how they handle negative zero (which can be
9070 // ignored in unsafe-math mode).
9071 if (Subtarget->hasSSE2() &&
9072 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
9073 Cond.getOpcode() == ISD::SETCC) {
9074 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
9076 unsigned Opcode = 0;
9077 // Check for x CC y ? x : y.
9078 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
9079 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
9083 // Converting this to a min would handle NaNs incorrectly, and swapping
9084 // the operands would cause it to handle comparisons between positive
9085 // and negative zero incorrectly.
9086 if (!FiniteOnlyFPMath() &&
9087 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
9088 if (!UnsafeFPMath &&
9089 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9091 std::swap(LHS, RHS);
9093 Opcode = X86ISD::FMIN;
9096 // Converting this to a min would handle comparisons between positive
9097 // and negative zero incorrectly.
9098 if (!UnsafeFPMath &&
9099 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
9101 Opcode = X86ISD::FMIN;
9104 // Converting this to a min would handle both negative zeros and NaNs
9105 // incorrectly, but we can swap the operands to fix both.
9106 std::swap(LHS, RHS);
9110 Opcode = X86ISD::FMIN;
9114 // Converting this to a max would handle comparisons between positive
9115 // and negative zero incorrectly.
9116 if (!UnsafeFPMath &&
9117 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
9119 Opcode = X86ISD::FMAX;
9122 // Converting this to a max would handle NaNs incorrectly, and swapping
9123 // the operands would cause it to handle comparisons between positive
9124 // and negative zero incorrectly.
9125 if (!FiniteOnlyFPMath() &&
9126 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
9127 if (!UnsafeFPMath &&
9128 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9130 std::swap(LHS, RHS);
9132 Opcode = X86ISD::FMAX;
9135 // Converting this to a max would handle both negative zeros and NaNs
9136 // incorrectly, but we can swap the operands to fix both.
9137 std::swap(LHS, RHS);
9141 Opcode = X86ISD::FMAX;
9144 // Check for x CC y ? y : x -- a min/max with reversed arms.
9145 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
9146 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
9150 // Converting this to a min would handle comparisons between positive
9151 // and negative zero incorrectly, and swapping the operands would
9152 // cause it to handle NaNs incorrectly.
9153 if (!UnsafeFPMath &&
9154 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
9155 if (!FiniteOnlyFPMath() &&
9156 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9158 std::swap(LHS, RHS);
9160 Opcode = X86ISD::FMIN;
9163 // Converting this to a min would handle NaNs incorrectly.
9164 if (!UnsafeFPMath &&
9165 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9167 Opcode = X86ISD::FMIN;
9170 // Converting this to a min would handle both negative zeros and NaNs
9171 // incorrectly, but we can swap the operands to fix both.
9172 std::swap(LHS, RHS);
9176 Opcode = X86ISD::FMIN;
9180 // Converting this to a max would handle NaNs incorrectly.
9181 if (!FiniteOnlyFPMath() &&
9182 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9184 Opcode = X86ISD::FMAX;
9187 // Converting this to a max would handle comparisons between positive
9188 // and negative zero incorrectly, and swapping the operands would
9189 // cause it to handle NaNs incorrectly.
9190 if (!UnsafeFPMath &&
9191 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
9192 if (!FiniteOnlyFPMath() &&
9193 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
9195 std::swap(LHS, RHS);
9197 Opcode = X86ISD::FMAX;
9200 // Converting this to a max would handle both negative zeros and NaNs
9201 // incorrectly, but we can swap the operands to fix both.
9202 std::swap(LHS, RHS);
9206 Opcode = X86ISD::FMAX;
9212 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
9215 // If this is a select between two integer constants, try to do some
9217 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
9218 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
9219 // Don't do this for crazy integer types.
9220 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
9221 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
9222 // so that TrueC (the true value) is larger than FalseC.
9223 bool NeedsCondInvert = false;
9225 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
9226 // Efficiently invertible.
9227 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
9228 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
9229 isa<ConstantSDNode>(Cond.getOperand(1))))) {
9230 NeedsCondInvert = true;
9231 std::swap(TrueC, FalseC);
9234 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
9235 if (FalseC->getAPIntValue() == 0 &&
9236 TrueC->getAPIntValue().isPowerOf2()) {
9237 if (NeedsCondInvert) // Invert the condition if needed.
9238 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9239 DAG.getConstant(1, Cond.getValueType()));
9241 // Zero extend the condition if needed.
9242 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9244 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9245 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9246 DAG.getConstant(ShAmt, MVT::i8));
9249 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9250 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9251 if (NeedsCondInvert) // Invert the condition if needed.
9252 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9253 DAG.getConstant(1, Cond.getValueType()));
9255 // Zero extend the condition if needed.
9256 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9257 FalseC->getValueType(0), Cond);
9258 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9259 SDValue(FalseC, 0));
9262 // Optimize cases that will turn into an LEA instruction. This requires
9263 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9264 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9265 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9266 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9268 bool isFastMultiplier = false;
9270 switch ((unsigned char)Diff) {
9272 case 1: // result = add base, cond
9273 case 2: // result = lea base( , cond*2)
9274 case 3: // result = lea base(cond, cond*2)
9275 case 4: // result = lea base( , cond*4)
9276 case 5: // result = lea base(cond, cond*4)
9277 case 8: // result = lea base( , cond*8)
9278 case 9: // result = lea base(cond, cond*8)
9279 isFastMultiplier = true;
9284 if (isFastMultiplier) {
9285 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9286 if (NeedsCondInvert) // Invert the condition if needed.
9287 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9288 DAG.getConstant(1, Cond.getValueType()));
9290 // Zero extend the condition if needed.
9291 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9293 // Scale the condition by the difference.
9295 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9296 DAG.getConstant(Diff, Cond.getValueType()));
9298 // Add the base if non-zero.
9299 if (FalseC->getAPIntValue() != 0)
9300 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9301 SDValue(FalseC, 0));
9311 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9312 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9313 TargetLowering::DAGCombinerInfo &DCI) {
9314 DebugLoc DL = N->getDebugLoc();
9316 // If the flag operand isn't dead, don't touch this CMOV.
9317 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9320 // If this is a select between two integer constants, try to do some
9321 // optimizations. Note that the operands are ordered the opposite of SELECT
9323 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9324 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9325 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9326 // larger than FalseC (the false value).
9327 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9329 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9330 CC = X86::GetOppositeBranchCondition(CC);
9331 std::swap(TrueC, FalseC);
9334 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9335 // This is efficient for any integer data type (including i8/i16) and
9337 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9338 SDValue Cond = N->getOperand(3);
9339 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9340 DAG.getConstant(CC, MVT::i8), Cond);
9342 // Zero extend the condition if needed.
9343 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9345 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9346 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9347 DAG.getConstant(ShAmt, MVT::i8));
9348 if (N->getNumValues() == 2) // Dead flag value?
9349 return DCI.CombineTo(N, Cond, SDValue());
9353 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9354 // for any integer data type, including i8/i16.
9355 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9356 SDValue Cond = N->getOperand(3);
9357 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9358 DAG.getConstant(CC, MVT::i8), Cond);
9360 // Zero extend the condition if needed.
9361 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9362 FalseC->getValueType(0), Cond);
9363 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9364 SDValue(FalseC, 0));
9366 if (N->getNumValues() == 2) // Dead flag value?
9367 return DCI.CombineTo(N, Cond, SDValue());
9371 // Optimize cases that will turn into an LEA instruction. This requires
9372 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9373 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9374 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9375 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9377 bool isFastMultiplier = false;
9379 switch ((unsigned char)Diff) {
9381 case 1: // result = add base, cond
9382 case 2: // result = lea base( , cond*2)
9383 case 3: // result = lea base(cond, cond*2)
9384 case 4: // result = lea base( , cond*4)
9385 case 5: // result = lea base(cond, cond*4)
9386 case 8: // result = lea base( , cond*8)
9387 case 9: // result = lea base(cond, cond*8)
9388 isFastMultiplier = true;
9393 if (isFastMultiplier) {
9394 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9395 SDValue Cond = N->getOperand(3);
9396 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9397 DAG.getConstant(CC, MVT::i8), Cond);
9398 // Zero extend the condition if needed.
9399 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9401 // Scale the condition by the difference.
9403 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9404 DAG.getConstant(Diff, Cond.getValueType()));
9406 // Add the base if non-zero.
9407 if (FalseC->getAPIntValue() != 0)
9408 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9409 SDValue(FalseC, 0));
9410 if (N->getNumValues() == 2) // Dead flag value?
9411 return DCI.CombineTo(N, Cond, SDValue());
9421 /// PerformMulCombine - Optimize a single multiply with constant into two
9422 /// in order to implement it with two cheaper instructions, e.g.
9423 /// LEA + SHL, LEA + LEA.
9424 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9425 TargetLowering::DAGCombinerInfo &DCI) {
9426 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9429 EVT VT = N->getValueType(0);
9433 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9436 uint64_t MulAmt = C->getZExtValue();
9437 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9440 uint64_t MulAmt1 = 0;
9441 uint64_t MulAmt2 = 0;
9442 if ((MulAmt % 9) == 0) {
9444 MulAmt2 = MulAmt / 9;
9445 } else if ((MulAmt % 5) == 0) {
9447 MulAmt2 = MulAmt / 5;
9448 } else if ((MulAmt % 3) == 0) {
9450 MulAmt2 = MulAmt / 3;
9453 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9454 DebugLoc DL = N->getDebugLoc();
9456 if (isPowerOf2_64(MulAmt2) &&
9457 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9458 // If second multiplifer is pow2, issue it first. We want the multiply by
9459 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9461 std::swap(MulAmt1, MulAmt2);
9464 if (isPowerOf2_64(MulAmt1))
9465 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9466 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9468 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9469 DAG.getConstant(MulAmt1, VT));
9471 if (isPowerOf2_64(MulAmt2))
9472 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9473 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9475 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9476 DAG.getConstant(MulAmt2, VT));
9478 // Do not add new nodes to DAG combiner worklist.
9479 DCI.CombineTo(N, NewMul, false);
9484 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9485 SDValue N0 = N->getOperand(0);
9486 SDValue N1 = N->getOperand(1);
9487 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9488 EVT VT = N0.getValueType();
9490 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9491 // since the result of setcc_c is all zero's or all ones.
9492 if (N1C && N0.getOpcode() == ISD::AND &&
9493 N0.getOperand(1).getOpcode() == ISD::Constant) {
9494 SDValue N00 = N0.getOperand(0);
9495 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9496 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9497 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9498 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9499 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9500 APInt ShAmt = N1C->getAPIntValue();
9501 Mask = Mask.shl(ShAmt);
9503 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9504 N00, DAG.getConstant(Mask, VT));
9511 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9513 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9514 const X86Subtarget *Subtarget) {
9515 EVT VT = N->getValueType(0);
9516 if (!VT.isVector() && VT.isInteger() &&
9517 N->getOpcode() == ISD::SHL)
9518 return PerformSHLCombine(N, DAG);
9520 // On X86 with SSE2 support, we can transform this to a vector shift if
9521 // all elements are shifted by the same amount. We can't do this in legalize
9522 // because the a constant vector is typically transformed to a constant pool
9523 // so we have no knowledge of the shift amount.
9524 if (!Subtarget->hasSSE2())
9527 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9530 SDValue ShAmtOp = N->getOperand(1);
9531 EVT EltVT = VT.getVectorElementType();
9532 DebugLoc DL = N->getDebugLoc();
9533 SDValue BaseShAmt = SDValue();
9534 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9535 unsigned NumElts = VT.getVectorNumElements();
9537 for (; i != NumElts; ++i) {
9538 SDValue Arg = ShAmtOp.getOperand(i);
9539 if (Arg.getOpcode() == ISD::UNDEF) continue;
9543 for (; i != NumElts; ++i) {
9544 SDValue Arg = ShAmtOp.getOperand(i);
9545 if (Arg.getOpcode() == ISD::UNDEF) continue;
9546 if (Arg != BaseShAmt) {
9550 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9551 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9552 SDValue InVec = ShAmtOp.getOperand(0);
9553 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9554 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9556 for (; i != NumElts; ++i) {
9557 SDValue Arg = InVec.getOperand(i);
9558 if (Arg.getOpcode() == ISD::UNDEF) continue;
9562 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9563 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9564 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9565 if (C->getZExtValue() == SplatIdx)
9566 BaseShAmt = InVec.getOperand(1);
9569 if (BaseShAmt.getNode() == 0)
9570 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9571 DAG.getIntPtrConstant(0));
9575 // The shift amount is an i32.
9576 if (EltVT.bitsGT(MVT::i32))
9577 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9578 else if (EltVT.bitsLT(MVT::i32))
9579 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9581 // The shift amount is identical so we can do a vector shift.
9582 SDValue ValOp = N->getOperand(0);
9583 switch (N->getOpcode()) {
9585 llvm_unreachable("Unknown shift opcode!");
9588 if (VT == MVT::v2i64)
9589 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9590 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9592 if (VT == MVT::v4i32)
9593 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9594 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9596 if (VT == MVT::v8i16)
9597 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9598 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9602 if (VT == MVT::v4i32)
9603 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9604 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9606 if (VT == MVT::v8i16)
9607 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9608 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9612 if (VT == MVT::v2i64)
9613 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9614 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9616 if (VT == MVT::v4i32)
9617 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9618 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9620 if (VT == MVT::v8i16)
9621 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9622 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9629 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9630 TargetLowering::DAGCombinerInfo &DCI,
9631 const X86Subtarget *Subtarget) {
9632 if (DCI.isBeforeLegalizeOps())
9635 EVT VT = N->getValueType(0);
9636 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
9639 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9640 SDValue N0 = N->getOperand(0);
9641 SDValue N1 = N->getOperand(1);
9642 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9644 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9646 if (!N0.hasOneUse() || !N1.hasOneUse())
9649 SDValue ShAmt0 = N0.getOperand(1);
9650 if (ShAmt0.getValueType() != MVT::i8)
9652 SDValue ShAmt1 = N1.getOperand(1);
9653 if (ShAmt1.getValueType() != MVT::i8)
9655 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9656 ShAmt0 = ShAmt0.getOperand(0);
9657 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9658 ShAmt1 = ShAmt1.getOperand(0);
9660 DebugLoc DL = N->getDebugLoc();
9661 unsigned Opc = X86ISD::SHLD;
9662 SDValue Op0 = N0.getOperand(0);
9663 SDValue Op1 = N1.getOperand(0);
9664 if (ShAmt0.getOpcode() == ISD::SUB) {
9666 std::swap(Op0, Op1);
9667 std::swap(ShAmt0, ShAmt1);
9670 unsigned Bits = VT.getSizeInBits();
9671 if (ShAmt1.getOpcode() == ISD::SUB) {
9672 SDValue Sum = ShAmt1.getOperand(0);
9673 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9674 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
9675 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
9676 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
9677 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
9678 return DAG.getNode(Opc, DL, VT,
9680 DAG.getNode(ISD::TRUNCATE, DL,
9683 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9684 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9686 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
9687 return DAG.getNode(Opc, DL, VT,
9688 N0.getOperand(0), N1.getOperand(0),
9689 DAG.getNode(ISD::TRUNCATE, DL,
9696 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9697 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9698 const X86Subtarget *Subtarget) {
9699 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9700 // the FP state in cases where an emms may be missing.
9701 // A preferable solution to the general problem is to figure out the right
9702 // places to insert EMMS. This qualifies as a quick hack.
9704 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9705 StoreSDNode *St = cast<StoreSDNode>(N);
9706 EVT VT = St->getValue().getValueType();
9707 if (VT.getSizeInBits() != 64)
9710 const Function *F = DAG.getMachineFunction().getFunction();
9711 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9712 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9713 && Subtarget->hasSSE2();
9714 if ((VT.isVector() ||
9715 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9716 isa<LoadSDNode>(St->getValue()) &&
9717 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9718 St->getChain().hasOneUse() && !St->isVolatile()) {
9719 SDNode* LdVal = St->getValue().getNode();
9721 int TokenFactorIndex = -1;
9722 SmallVector<SDValue, 8> Ops;
9723 SDNode* ChainVal = St->getChain().getNode();
9724 // Must be a store of a load. We currently handle two cases: the load
9725 // is a direct child, and it's under an intervening TokenFactor. It is
9726 // possible to dig deeper under nested TokenFactors.
9727 if (ChainVal == LdVal)
9728 Ld = cast<LoadSDNode>(St->getChain());
9729 else if (St->getValue().hasOneUse() &&
9730 ChainVal->getOpcode() == ISD::TokenFactor) {
9731 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9732 if (ChainVal->getOperand(i).getNode() == LdVal) {
9733 TokenFactorIndex = i;
9734 Ld = cast<LoadSDNode>(St->getValue());
9736 Ops.push_back(ChainVal->getOperand(i));
9740 if (!Ld || !ISD::isNormalLoad(Ld))
9743 // If this is not the MMX case, i.e. we are just turning i64 load/store
9744 // into f64 load/store, avoid the transformation if there are multiple
9745 // uses of the loaded value.
9746 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9749 DebugLoc LdDL = Ld->getDebugLoc();
9750 DebugLoc StDL = N->getDebugLoc();
9751 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9752 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9754 if (Subtarget->is64Bit() || F64IsLegal) {
9755 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9756 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9757 Ld->getBasePtr(), Ld->getSrcValue(),
9758 Ld->getSrcValueOffset(), Ld->isVolatile(),
9759 Ld->isNonTemporal(), Ld->getAlignment());
9760 SDValue NewChain = NewLd.getValue(1);
9761 if (TokenFactorIndex != -1) {
9762 Ops.push_back(NewChain);
9763 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9766 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9767 St->getSrcValue(), St->getSrcValueOffset(),
9768 St->isVolatile(), St->isNonTemporal(),
9769 St->getAlignment());
9772 // Otherwise, lower to two pairs of 32-bit loads / stores.
9773 SDValue LoAddr = Ld->getBasePtr();
9774 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9775 DAG.getConstant(4, MVT::i32));
9777 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9778 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9779 Ld->isVolatile(), Ld->isNonTemporal(),
9780 Ld->getAlignment());
9781 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9782 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9783 Ld->isVolatile(), Ld->isNonTemporal(),
9784 MinAlign(Ld->getAlignment(), 4));
9786 SDValue NewChain = LoLd.getValue(1);
9787 if (TokenFactorIndex != -1) {
9788 Ops.push_back(LoLd);
9789 Ops.push_back(HiLd);
9790 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9794 LoAddr = St->getBasePtr();
9795 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9796 DAG.getConstant(4, MVT::i32));
9798 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9799 St->getSrcValue(), St->getSrcValueOffset(),
9800 St->isVolatile(), St->isNonTemporal(),
9801 St->getAlignment());
9802 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9804 St->getSrcValueOffset() + 4,
9806 St->isNonTemporal(),
9807 MinAlign(St->getAlignment(), 4));
9808 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9813 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9814 /// X86ISD::FXOR nodes.
9815 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9816 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9817 // F[X]OR(0.0, x) -> x
9818 // F[X]OR(x, 0.0) -> x
9819 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9820 if (C->getValueAPF().isPosZero())
9821 return N->getOperand(1);
9822 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9823 if (C->getValueAPF().isPosZero())
9824 return N->getOperand(0);
9828 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9829 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9830 // FAND(0.0, x) -> 0.0
9831 // FAND(x, 0.0) -> 0.0
9832 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9833 if (C->getValueAPF().isPosZero())
9834 return N->getOperand(0);
9835 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9836 if (C->getValueAPF().isPosZero())
9837 return N->getOperand(1);
9841 static SDValue PerformBTCombine(SDNode *N,
9843 TargetLowering::DAGCombinerInfo &DCI) {
9844 // BT ignores high bits in the bit index operand.
9845 SDValue Op1 = N->getOperand(1);
9846 if (Op1.hasOneUse()) {
9847 unsigned BitWidth = Op1.getValueSizeInBits();
9848 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9849 APInt KnownZero, KnownOne;
9850 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
9851 !DCI.isBeforeLegalizeOps());
9852 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9853 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9854 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9855 DCI.CommitTargetLoweringOpt(TLO);
9860 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9861 SDValue Op = N->getOperand(0);
9862 if (Op.getOpcode() == ISD::BIT_CONVERT)
9863 Op = Op.getOperand(0);
9864 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9865 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9866 VT.getVectorElementType().getSizeInBits() ==
9867 OpVT.getVectorElementType().getSizeInBits()) {
9868 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9873 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9874 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9875 // (and (i32 x86isd::setcc_carry), 1)
9876 // This eliminates the zext. This transformation is necessary because
9877 // ISD::SETCC is always legalized to i8.
9878 DebugLoc dl = N->getDebugLoc();
9879 SDValue N0 = N->getOperand(0);
9880 EVT VT = N->getValueType(0);
9881 if (N0.getOpcode() == ISD::AND &&
9883 N0.getOperand(0).hasOneUse()) {
9884 SDValue N00 = N0.getOperand(0);
9885 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9887 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9888 if (!C || C->getZExtValue() != 1)
9890 return DAG.getNode(ISD::AND, dl, VT,
9891 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9892 N00.getOperand(0), N00.getOperand(1)),
9893 DAG.getConstant(1, VT));
9899 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9900 DAGCombinerInfo &DCI) const {
9901 SelectionDAG &DAG = DCI.DAG;
9902 switch (N->getOpcode()) {
9904 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9905 case ISD::EXTRACT_VECTOR_ELT:
9906 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
9907 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9908 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9909 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9912 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9913 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
9914 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9916 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9917 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9918 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9919 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9920 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9926 /// isTypeDesirableForOp - Return true if the target has native support for
9927 /// the specified value type and it is 'desirable' to use the type for the
9928 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
9929 /// instruction encodings are longer and some i16 instructions are slow.
9930 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
9931 if (!isTypeLegal(VT))
9940 case ISD::SIGN_EXTEND:
9941 case ISD::ZERO_EXTEND:
9942 case ISD::ANY_EXTEND:
9955 static bool MayFoldLoad(SDValue Op) {
9956 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
9959 static bool MayFoldIntoStore(SDValue Op) {
9960 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
9963 /// IsDesirableToPromoteOp - This method query the target whether it is
9964 /// beneficial for dag combiner to promote the specified node. If true, it
9965 /// should return the desired promotion type by reference.
9966 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
9967 EVT VT = Op.getValueType();
9971 bool Promote = false;
9972 bool Commute = false;
9973 switch (Op.getOpcode()) {
9976 LoadSDNode *LD = cast<LoadSDNode>(Op);
9977 // If the non-extending load has a single use and it's not live out, then it
9979 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
9981 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9982 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9983 // The only case where we'd want to promote LOAD (rather then it being
9984 // promoted as an operand is when it's only use is liveout.
9985 if (UI->getOpcode() != ISD::CopyToReg)
9992 case ISD::SIGN_EXTEND:
9993 case ISD::ZERO_EXTEND:
9994 case ISD::ANY_EXTEND:
9999 SDValue N0 = Op.getOperand(0);
10000 // Look out for (store (shl (load), x)).
10001 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
10014 SDValue N0 = Op.getOperand(0);
10015 SDValue N1 = Op.getOperand(1);
10016 if (!Commute && MayFoldLoad(N1))
10018 // Avoid disabling potential load folding opportunities.
10019 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
10021 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
10031 //===----------------------------------------------------------------------===//
10032 // X86 Inline Assembly Support
10033 //===----------------------------------------------------------------------===//
10035 static bool LowerToBSwap(CallInst *CI) {
10036 // FIXME: this should verify that we are targetting a 486 or better. If not,
10037 // we will turn this bswap into something that will be lowered to logical ops
10038 // instead of emitting the bswap asm. For now, we don't support 486 or lower
10039 // so don't worry about this.
10041 // Verify this is a simple bswap.
10042 if (CI->getNumArgOperands() != 1 ||
10043 CI->getType() != CI->getArgOperand(0)->getType() ||
10044 !CI->getType()->isIntegerTy())
10047 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10048 if (!Ty || Ty->getBitWidth() % 16 != 0)
10051 // Okay, we can do this xform, do so now.
10052 const Type *Tys[] = { Ty };
10053 Module *M = CI->getParent()->getParent()->getParent();
10054 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
10056 Value *Op = CI->getArgOperand(0);
10057 Op = CallInst::Create(Int, Op, CI->getName(), CI);
10059 CI->replaceAllUsesWith(Op);
10060 CI->eraseFromParent();
10064 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
10065 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10066 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
10068 std::string AsmStr = IA->getAsmString();
10070 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
10071 SmallVector<StringRef, 4> AsmPieces;
10072 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
10074 switch (AsmPieces.size()) {
10075 default: return false;
10077 AsmStr = AsmPieces[0];
10079 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
10082 if (AsmPieces.size() == 2 &&
10083 (AsmPieces[0] == "bswap" ||
10084 AsmPieces[0] == "bswapq" ||
10085 AsmPieces[0] == "bswapl") &&
10086 (AsmPieces[1] == "$0" ||
10087 AsmPieces[1] == "${0:q}")) {
10088 // No need to check constraints, nothing other than the equivalent of
10089 // "=r,0" would be valid here.
10090 return LowerToBSwap(CI);
10092 // rorw $$8, ${0:w} --> llvm.bswap.i16
10093 if (CI->getType()->isIntegerTy(16) &&
10094 AsmPieces.size() == 3 &&
10095 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
10096 AsmPieces[1] == "$$8," &&
10097 AsmPieces[2] == "${0:w}" &&
10098 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
10100 const std::string &Constraints = IA->getConstraintString();
10101 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
10102 std::sort(AsmPieces.begin(), AsmPieces.end());
10103 if (AsmPieces.size() == 4 &&
10104 AsmPieces[0] == "~{cc}" &&
10105 AsmPieces[1] == "~{dirflag}" &&
10106 AsmPieces[2] == "~{flags}" &&
10107 AsmPieces[3] == "~{fpsr}") {
10108 return LowerToBSwap(CI);
10113 if (CI->getType()->isIntegerTy(64) &&
10114 Constraints.size() >= 2 &&
10115 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
10116 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
10117 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
10118 SmallVector<StringRef, 4> Words;
10119 SplitString(AsmPieces[0], Words, " \t");
10120 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
10122 SplitString(AsmPieces[1], Words, " \t");
10123 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
10125 SplitString(AsmPieces[2], Words, " \t,");
10126 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
10127 Words[2] == "%edx") {
10128 return LowerToBSwap(CI);
10140 /// getConstraintType - Given a constraint letter, return the type of
10141 /// constraint it is for this target.
10142 X86TargetLowering::ConstraintType
10143 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
10144 if (Constraint.size() == 1) {
10145 switch (Constraint[0]) {
10157 return C_RegisterClass;
10165 return TargetLowering::getConstraintType(Constraint);
10168 /// LowerXConstraint - try to replace an X constraint, which matches anything,
10169 /// with another that has more specific requirements based on the type of the
10170 /// corresponding operand.
10171 const char *X86TargetLowering::
10172 LowerXConstraint(EVT ConstraintVT) const {
10173 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
10174 // 'f' like normal targets.
10175 if (ConstraintVT.isFloatingPoint()) {
10176 if (Subtarget->hasSSE2())
10178 if (Subtarget->hasSSE1())
10182 return TargetLowering::LowerXConstraint(ConstraintVT);
10185 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10186 /// vector. If it is invalid, don't add anything to Ops.
10187 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10189 std::vector<SDValue>&Ops,
10190 SelectionDAG &DAG) const {
10191 SDValue Result(0, 0);
10193 switch (Constraint) {
10196 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10197 if (C->getZExtValue() <= 31) {
10198 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10204 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10205 if (C->getZExtValue() <= 63) {
10206 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10213 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
10214 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10220 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10221 if (C->getZExtValue() <= 255) {
10222 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10228 // 32-bit signed value
10229 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10230 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10231 C->getSExtValue())) {
10232 // Widen to 64 bits here to get it sign extended.
10233 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
10236 // FIXME gcc accepts some relocatable values here too, but only in certain
10237 // memory models; it's complicated.
10242 // 32-bit unsigned value
10243 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
10244 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
10245 C->getZExtValue())) {
10246 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
10250 // FIXME gcc accepts some relocatable values here too, but only in certain
10251 // memory models; it's complicated.
10255 // Literal immediates are always ok.
10256 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
10257 // Widen to 64 bits here to get it sign extended.
10258 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10262 // In any sort of PIC mode addresses need to be computed at runtime by
10263 // adding in a register or some sort of table lookup. These can't
10264 // be used as immediates.
10265 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
10268 // If we are in non-pic codegen mode, we allow the address of a global (with
10269 // an optional displacement) to be used with 'i'.
10270 GlobalAddressSDNode *GA = 0;
10271 int64_t Offset = 0;
10273 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10275 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10276 Offset += GA->getOffset();
10278 } else if (Op.getOpcode() == ISD::ADD) {
10279 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10280 Offset += C->getZExtValue();
10281 Op = Op.getOperand(0);
10284 } else if (Op.getOpcode() == ISD::SUB) {
10285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10286 Offset += -C->getZExtValue();
10287 Op = Op.getOperand(0);
10292 // Otherwise, this isn't something we can handle, reject it.
10296 const GlobalValue *GV = GA->getGlobal();
10297 // If we require an extra load to get this address, as in PIC mode, we
10298 // can't accept it.
10299 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10300 getTargetMachine())))
10303 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
10304 GA->getValueType(0), Offset);
10309 if (Result.getNode()) {
10310 Ops.push_back(Result);
10313 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10316 std::vector<unsigned> X86TargetLowering::
10317 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10319 if (Constraint.size() == 1) {
10320 // FIXME: not handling fp-stack yet!
10321 switch (Constraint[0]) { // GCC X86 Constraint Letters
10322 default: break; // Unknown constraint letter
10323 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10324 if (Subtarget->is64Bit()) {
10325 if (VT == MVT::i32)
10326 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10327 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10328 X86::R10D,X86::R11D,X86::R12D,
10329 X86::R13D,X86::R14D,X86::R15D,
10330 X86::EBP, X86::ESP, 0);
10331 else if (VT == MVT::i16)
10332 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10333 X86::SI, X86::DI, X86::R8W,X86::R9W,
10334 X86::R10W,X86::R11W,X86::R12W,
10335 X86::R13W,X86::R14W,X86::R15W,
10336 X86::BP, X86::SP, 0);
10337 else if (VT == MVT::i8)
10338 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10339 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10340 X86::R10B,X86::R11B,X86::R12B,
10341 X86::R13B,X86::R14B,X86::R15B,
10342 X86::BPL, X86::SPL, 0);
10344 else if (VT == MVT::i64)
10345 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10346 X86::RSI, X86::RDI, X86::R8, X86::R9,
10347 X86::R10, X86::R11, X86::R12,
10348 X86::R13, X86::R14, X86::R15,
10349 X86::RBP, X86::RSP, 0);
10353 // 32-bit fallthrough
10354 case 'Q': // Q_REGS
10355 if (VT == MVT::i32)
10356 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10357 else if (VT == MVT::i16)
10358 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10359 else if (VT == MVT::i8)
10360 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10361 else if (VT == MVT::i64)
10362 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10367 return std::vector<unsigned>();
10370 std::pair<unsigned, const TargetRegisterClass*>
10371 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10373 // First, see if this is a constraint that directly corresponds to an LLVM
10375 if (Constraint.size() == 1) {
10376 // GCC Constraint Letters
10377 switch (Constraint[0]) {
10379 case 'r': // GENERAL_REGS
10380 case 'l': // INDEX_REGS
10382 return std::make_pair(0U, X86::GR8RegisterClass);
10383 if (VT == MVT::i16)
10384 return std::make_pair(0U, X86::GR16RegisterClass);
10385 if (VT == MVT::i32 || !Subtarget->is64Bit())
10386 return std::make_pair(0U, X86::GR32RegisterClass);
10387 return std::make_pair(0U, X86::GR64RegisterClass);
10388 case 'R': // LEGACY_REGS
10390 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10391 if (VT == MVT::i16)
10392 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10393 if (VT == MVT::i32 || !Subtarget->is64Bit())
10394 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10395 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10396 case 'f': // FP Stack registers.
10397 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10398 // value to the correct fpstack register class.
10399 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10400 return std::make_pair(0U, X86::RFP32RegisterClass);
10401 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10402 return std::make_pair(0U, X86::RFP64RegisterClass);
10403 return std::make_pair(0U, X86::RFP80RegisterClass);
10404 case 'y': // MMX_REGS if MMX allowed.
10405 if (!Subtarget->hasMMX()) break;
10406 return std::make_pair(0U, X86::VR64RegisterClass);
10407 case 'Y': // SSE_REGS if SSE2 allowed
10408 if (!Subtarget->hasSSE2()) break;
10410 case 'x': // SSE_REGS if SSE1 allowed
10411 if (!Subtarget->hasSSE1()) break;
10413 switch (VT.getSimpleVT().SimpleTy) {
10415 // Scalar SSE types.
10418 return std::make_pair(0U, X86::FR32RegisterClass);
10421 return std::make_pair(0U, X86::FR64RegisterClass);
10429 return std::make_pair(0U, X86::VR128RegisterClass);
10435 // Use the default implementation in TargetLowering to convert the register
10436 // constraint into a member of a register class.
10437 std::pair<unsigned, const TargetRegisterClass*> Res;
10438 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10440 // Not found as a standard register?
10441 if (Res.second == 0) {
10442 // Map st(0) -> st(7) -> ST0
10443 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10444 tolower(Constraint[1]) == 's' &&
10445 tolower(Constraint[2]) == 't' &&
10446 Constraint[3] == '(' &&
10447 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10448 Constraint[5] == ')' &&
10449 Constraint[6] == '}') {
10451 Res.first = X86::ST0+Constraint[4]-'0';
10452 Res.second = X86::RFP80RegisterClass;
10456 // GCC allows "st(0)" to be called just plain "st".
10457 if (StringRef("{st}").equals_lower(Constraint)) {
10458 Res.first = X86::ST0;
10459 Res.second = X86::RFP80RegisterClass;
10464 if (StringRef("{flags}").equals_lower(Constraint)) {
10465 Res.first = X86::EFLAGS;
10466 Res.second = X86::CCRRegisterClass;
10470 // 'A' means EAX + EDX.
10471 if (Constraint == "A") {
10472 Res.first = X86::EAX;
10473 Res.second = X86::GR32_ADRegisterClass;
10479 // Otherwise, check to see if this is a register class of the wrong value
10480 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10481 // turn into {ax},{dx}.
10482 if (Res.second->hasType(VT))
10483 return Res; // Correct type already, nothing to do.
10485 // All of the single-register GCC register classes map their values onto
10486 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10487 // really want an 8-bit or 32-bit register, map to the appropriate register
10488 // class and return the appropriate register.
10489 if (Res.second == X86::GR16RegisterClass) {
10490 if (VT == MVT::i8) {
10491 unsigned DestReg = 0;
10492 switch (Res.first) {
10494 case X86::AX: DestReg = X86::AL; break;
10495 case X86::DX: DestReg = X86::DL; break;
10496 case X86::CX: DestReg = X86::CL; break;
10497 case X86::BX: DestReg = X86::BL; break;
10500 Res.first = DestReg;
10501 Res.second = X86::GR8RegisterClass;
10503 } else if (VT == MVT::i32) {
10504 unsigned DestReg = 0;
10505 switch (Res.first) {
10507 case X86::AX: DestReg = X86::EAX; break;
10508 case X86::DX: DestReg = X86::EDX; break;
10509 case X86::CX: DestReg = X86::ECX; break;
10510 case X86::BX: DestReg = X86::EBX; break;
10511 case X86::SI: DestReg = X86::ESI; break;
10512 case X86::DI: DestReg = X86::EDI; break;
10513 case X86::BP: DestReg = X86::EBP; break;
10514 case X86::SP: DestReg = X86::ESP; break;
10517 Res.first = DestReg;
10518 Res.second = X86::GR32RegisterClass;
10520 } else if (VT == MVT::i64) {
10521 unsigned DestReg = 0;
10522 switch (Res.first) {
10524 case X86::AX: DestReg = X86::RAX; break;
10525 case X86::DX: DestReg = X86::RDX; break;
10526 case X86::CX: DestReg = X86::RCX; break;
10527 case X86::BX: DestReg = X86::RBX; break;
10528 case X86::SI: DestReg = X86::RSI; break;
10529 case X86::DI: DestReg = X86::RDI; break;
10530 case X86::BP: DestReg = X86::RBP; break;
10531 case X86::SP: DestReg = X86::RSP; break;
10534 Res.first = DestReg;
10535 Res.second = X86::GR64RegisterClass;
10538 } else if (Res.second == X86::FR32RegisterClass ||
10539 Res.second == X86::FR64RegisterClass ||
10540 Res.second == X86::VR128RegisterClass) {
10541 // Handle references to XMM physical registers that got mapped into the
10542 // wrong class. This can happen with constraints like {xmm0} where the
10543 // target independent register mapper will just pick the first match it can
10544 // find, ignoring the required type.
10545 if (VT == MVT::f32)
10546 Res.second = X86::FR32RegisterClass;
10547 else if (VT == MVT::f64)
10548 Res.second = X86::FR64RegisterClass;
10549 else if (X86::VR128RegisterClass->hasType(VT))
10550 Res.second = X86::VR128RegisterClass;