1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
184 // For 64-bit since we have so many registers use the ILP scheduler, for
185 // 32-bit code use the register pressure specific scheduling.
186 if (Subtarget->is64Bit())
187 setSchedulingPreference(Sched::ILP);
189 setSchedulingPreference(Sched::RegPressure);
190 setStackPointerRegisterToSaveRestore(X86StackPtr);
192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
193 // Setup Windows compiler runtime calls.
194 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
196 setLibcallName(RTLIB::SREM_I64, "_allrem");
197 setLibcallName(RTLIB::UREM_I64, "_aullrem");
198 setLibcallName(RTLIB::MUL_I64, "_allmul");
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
210 if (Subtarget->isTargetDarwin()) {
211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
212 setUseUnderscoreSetJmp(false);
213 setUseUnderscoreLongJmp(false);
214 } else if (Subtarget->isTargetMingw()) {
215 // MS runtime is weird: it exports _setjmp, but longjmp!
216 setUseUnderscoreSetJmp(true);
217 setUseUnderscoreLongJmp(false);
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(true);
223 // Set up the register classes.
224 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
225 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
226 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
227 if (Subtarget->is64Bit())
228 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232 // We don't accept any truncstore of integer registers.
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
240 // SETOEQ and SETUNE require checking two conditions.
241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
257 } else if (!UseSoftFloat) {
258 // We have an algorithm for SSE2->double, and we turn this into a
259 // 64-bit FILD followed by conditional FADD for other targets.
260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
261 // We have an algorithm for SSE2, and we turn this into a 64-bit
262 // FILD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
272 // SSE has no i16 to fp conversion, only i32
273 if (X86ScalarSSEf32) {
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
275 // f32 and f64 cases are Legal, f80 case is not
276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 // are Legal, f80 is custom lowered.
288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
296 if (X86ScalarSSEf32) {
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
298 // f32 and f64 cases are Legal, f80 case is not
299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
305 // Handle FP_TO_UINT by promoting the destination to a larger signed
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
314 } else if (!UseSoftFloat) {
315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasXMM())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
455 // On X86 and X86-64, atomic operations are lowered to locked instructions.
456 // Locked instructions, in turn, have implicit fence semantics (all memory
457 // operations are flushed before issuing the locked instruction, and they
458 // are not buffered), so we can fold away the common pattern of
459 // fence-atomic-fence.
460 setShouldFoldAtomicFences(true);
462 // Expand certain atomics
463 for (unsigned i = 0, e = 4; i != e; ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 if (!Subtarget->is64Bit()) {
470 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
471 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
479 // FIXME - use subtarget debug flags
480 if (!Subtarget->isTargetDarwin() &&
481 !Subtarget->isTargetELF() &&
482 !Subtarget->isTargetCygMing()) {
483 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
486 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
487 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
488 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
489 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
490 if (Subtarget->is64Bit()) {
491 setExceptionPointerRegister(X86::RAX);
492 setExceptionSelectorRegister(X86::RDX);
494 setExceptionPointerRegister(X86::EAX);
495 setExceptionSelectorRegister(X86::EDX);
497 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
498 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
500 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
502 setOperationAction(ISD::TRAP, MVT::Other, Legal);
504 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
505 setOperationAction(ISD::VASTART , MVT::Other, Custom);
506 setOperationAction(ISD::VAEND , MVT::Other, Expand);
507 if (Subtarget->is64Bit()) {
508 setOperationAction(ISD::VAARG , MVT::Other, Custom);
509 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
511 setOperationAction(ISD::VAARG , MVT::Other, Expand);
512 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
515 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
516 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
517 setOperationAction(ISD::DYNAMIC_STACKALLOC,
518 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
519 (Subtarget->isTargetCOFF()
520 && !Subtarget->isTargetEnvMacho()
523 if (!UseSoftFloat && X86ScalarSSEf64) {
524 // f32 and f64 use SSE.
525 // Set up the FP register classes.
526 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
527 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
529 // Use ANDPD to simulate FABS.
530 setOperationAction(ISD::FABS , MVT::f64, Custom);
531 setOperationAction(ISD::FABS , MVT::f32, Custom);
533 // Use XORP to simulate FNEG.
534 setOperationAction(ISD::FNEG , MVT::f64, Custom);
535 setOperationAction(ISD::FNEG , MVT::f32, Custom);
537 // Use ANDPD and ORPD to simulate FCOPYSIGN.
538 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
539 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
541 // Lower this to FGETSIGNx86 plus an AND.
542 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
543 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
545 // We don't support sin/cos/fmod
546 setOperationAction(ISD::FSIN , MVT::f64, Expand);
547 setOperationAction(ISD::FCOS , MVT::f64, Expand);
548 setOperationAction(ISD::FSIN , MVT::f32, Expand);
549 setOperationAction(ISD::FCOS , MVT::f32, Expand);
551 // Expand FP immediates into loads from the stack, except for the special
553 addLegalFPImmediate(APFloat(+0.0)); // xorpd
554 addLegalFPImmediate(APFloat(+0.0f)); // xorps
555 } else if (!UseSoftFloat && X86ScalarSSEf32) {
556 // Use SSE for f32, x87 for f64.
557 // Set up the FP register classes.
558 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
559 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
561 // Use ANDPS to simulate FABS.
562 setOperationAction(ISD::FABS , MVT::f32, Custom);
564 // Use XORP to simulate FNEG.
565 setOperationAction(ISD::FNEG , MVT::f32, Custom);
567 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
569 // Use ANDPS and ORPS to simulate FCOPYSIGN.
570 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
571 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
573 // We don't support sin/cos/fmod
574 setOperationAction(ISD::FSIN , MVT::f32, Expand);
575 setOperationAction(ISD::FCOS , MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
585 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
586 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
588 } else if (!UseSoftFloat) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
592 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
601 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
603 addLegalFPImmediate(APFloat(+0.0)); // FLD0
604 addLegalFPImmediate(APFloat(+1.0)); // FLD1
605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
607 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
613 // We don't support FMA.
614 setOperationAction(ISD::FMA, MVT::f64, Expand);
615 setOperationAction(ISD::FMA, MVT::f32, Expand);
617 // Long double always uses X87.
619 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
620 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
621 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
623 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
624 addLegalFPImmediate(TmpFlt); // FLD0
626 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
629 APFloat TmpFlt2(+1.0);
630 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
632 addLegalFPImmediate(TmpFlt2); // FLD1
633 TmpFlt2.changeSign();
634 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
639 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
642 setOperationAction(ISD::FMA, MVT::f80, Expand);
645 // Always use a library call for pow.
646 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
647 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
648 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
650 setOperationAction(ISD::FLOG, MVT::f80, Expand);
651 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
652 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
653 setOperationAction(ISD::FEXP, MVT::f80, Expand);
654 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
656 // First set operation action for all vector types to either promote
657 // (for widening) or expand (for scalarization). Then we will selectively
658 // turn on ones that can be effectively codegen'd.
659 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
660 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
661 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
662 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
663 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
664 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
665 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
666 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
667 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
668 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
669 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
670 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
671 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
672 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
673 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
676 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
678 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
679 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
711 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
715 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
716 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
717 setTruncStoreAction((MVT::SimpleValueType)VT,
718 (MVT::SimpleValueType)InnerVT, Expand);
719 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
720 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
721 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
724 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
725 // with -msoft-float, disable use of MMX as well.
726 if (!UseSoftFloat && Subtarget->hasMMX()) {
727 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
728 // No operations on x86mmx supported, everything uses intrinsics.
731 // MMX-sized vectors (other than x86mmx) are expected to be expanded
732 // into smaller operations.
733 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
734 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
735 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
736 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
737 setOperationAction(ISD::AND, MVT::v8i8, Expand);
738 setOperationAction(ISD::AND, MVT::v4i16, Expand);
739 setOperationAction(ISD::AND, MVT::v2i32, Expand);
740 setOperationAction(ISD::AND, MVT::v1i64, Expand);
741 setOperationAction(ISD::OR, MVT::v8i8, Expand);
742 setOperationAction(ISD::OR, MVT::v4i16, Expand);
743 setOperationAction(ISD::OR, MVT::v2i32, Expand);
744 setOperationAction(ISD::OR, MVT::v1i64, Expand);
745 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
746 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
747 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
748 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
750 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
754 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
755 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
756 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
757 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
758 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
759 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
760 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
761 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
763 if (!UseSoftFloat && Subtarget->hasXMM()) {
764 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
766 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
767 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
768 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
769 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
770 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
771 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
772 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
773 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
774 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
776 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
777 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
780 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
781 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
783 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
784 // registers cannot be used even for integer operations.
785 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
786 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
787 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
788 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
790 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
791 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
792 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
793 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
794 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
795 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
796 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
797 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
798 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
799 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
800 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
801 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
802 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
803 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
804 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
805 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
807 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
808 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
809 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
810 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
812 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
813 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
821 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
822 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
824 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
825 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
826 EVT VT = (MVT::SimpleValueType)i;
827 // Do not attempt to custom lower non-power-of-2 vectors
828 if (!isPowerOf2_32(VT.getVectorNumElements()))
830 // Do not attempt to custom lower non-128-bit vectors
831 if (!VT.is128BitVector())
833 setOperationAction(ISD::BUILD_VECTOR,
834 VT.getSimpleVT().SimpleTy, Custom);
835 setOperationAction(ISD::VECTOR_SHUFFLE,
836 VT.getSimpleVT().SimpleTy, Custom);
837 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
838 VT.getSimpleVT().SimpleTy, Custom);
841 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
842 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
843 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
844 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
848 if (Subtarget->is64Bit()) {
849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
853 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
854 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
855 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
858 // Do not attempt to promote non-128-bit vectors
859 if (!VT.is128BitVector())
862 setOperationAction(ISD::AND, SVT, Promote);
863 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
864 setOperationAction(ISD::OR, SVT, Promote);
865 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
866 setOperationAction(ISD::XOR, SVT, Promote);
867 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
868 setOperationAction(ISD::LOAD, SVT, Promote);
869 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
870 setOperationAction(ISD::SELECT, SVT, Promote);
871 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
874 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
876 // Custom lower v2i64 and v2f64 selects.
877 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
878 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
879 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
882 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
883 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
886 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
887 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
888 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
889 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
890 setOperationAction(ISD::FRINT, MVT::f32, Legal);
891 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
892 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
893 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
894 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
895 setOperationAction(ISD::FRINT, MVT::f64, Legal);
896 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
898 // FIXME: Do we need to handle scalar-to-vector here?
899 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
901 // Can turn SHL into an integer multiply.
902 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
903 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
905 // i8 and i16 vectors are custom , because the source register and source
906 // source memory operand types are not the same width. f32 vectors are
907 // custom since the immediate controlling the insert encodes additional
909 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
914 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
916 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
919 if (Subtarget->is64Bit()) {
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
925 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
926 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
927 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
928 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
929 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
931 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
932 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
933 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
935 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
936 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
939 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
940 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
942 if (!UseSoftFloat && Subtarget->hasAVX()) {
943 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
944 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
945 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
946 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
947 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
948 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
950 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
951 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
952 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
954 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
955 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
956 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
957 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
958 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
959 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
961 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
962 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
963 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
964 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
965 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
966 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
968 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
969 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
970 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
972 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
973 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
974 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
975 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
976 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
977 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
980 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
981 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
982 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
984 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
985 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
986 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
987 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
989 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
990 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
992 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
993 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
995 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
996 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
997 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
999 // Custom lower several nodes for 256-bit types.
1000 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1001 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1002 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1005 // Extract subvector is special because the value type
1006 // (result) is 128-bit but the source is 256-bit wide.
1007 if (VT.is128BitVector())
1008 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1010 // Do not attempt to custom lower other non-256-bit vectors
1011 if (!VT.is256BitVector())
1014 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1015 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1016 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1018 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1019 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1022 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1023 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1024 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1027 // Do not attempt to promote non-256-bit vectors
1028 if (!VT.is256BitVector())
1031 setOperationAction(ISD::AND, SVT, Promote);
1032 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1033 setOperationAction(ISD::OR, SVT, Promote);
1034 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1035 setOperationAction(ISD::XOR, SVT, Promote);
1036 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1037 setOperationAction(ISD::LOAD, SVT, Promote);
1038 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1039 setOperationAction(ISD::SELECT, SVT, Promote);
1040 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1044 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1045 // of this type with custom code.
1046 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1047 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1048 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1051 // We want to custom lower some of our intrinsics.
1052 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1055 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1056 // handle type legalization for these operations here.
1058 // FIXME: We really should do custom legalization for addition and
1059 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1060 // than generic legalization for 64-bit multiplication-with-overflow, though.
1061 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1062 // Add/Sub/Mul with overflow operations are custom lowered.
1064 setOperationAction(ISD::SADDO, VT, Custom);
1065 setOperationAction(ISD::UADDO, VT, Custom);
1066 setOperationAction(ISD::SSUBO, VT, Custom);
1067 setOperationAction(ISD::USUBO, VT, Custom);
1068 setOperationAction(ISD::SMULO, VT, Custom);
1069 setOperationAction(ISD::UMULO, VT, Custom);
1072 // There are no 8-bit 3-address imul/mul instructions
1073 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1074 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1076 if (!Subtarget->is64Bit()) {
1077 // These libcalls are not available in 32-bit.
1078 setLibcallName(RTLIB::SHL_I128, 0);
1079 setLibcallName(RTLIB::SRL_I128, 0);
1080 setLibcallName(RTLIB::SRA_I128, 0);
1083 // We have target-specific dag combine patterns for the following nodes:
1084 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1085 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1086 setTargetDAGCombine(ISD::BUILD_VECTOR);
1087 setTargetDAGCombine(ISD::SELECT);
1088 setTargetDAGCombine(ISD::SHL);
1089 setTargetDAGCombine(ISD::SRA);
1090 setTargetDAGCombine(ISD::SRL);
1091 setTargetDAGCombine(ISD::OR);
1092 setTargetDAGCombine(ISD::AND);
1093 setTargetDAGCombine(ISD::ADD);
1094 setTargetDAGCombine(ISD::SUB);
1095 setTargetDAGCombine(ISD::STORE);
1096 setTargetDAGCombine(ISD::ZERO_EXTEND);
1097 setTargetDAGCombine(ISD::SINT_TO_FP);
1098 if (Subtarget->is64Bit())
1099 setTargetDAGCombine(ISD::MUL);
1101 computeRegisterProperties();
1103 // On Darwin, -Os means optimize for size without hurting performance,
1104 // do not reduce the limit.
1105 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1106 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1107 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1108 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1109 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1110 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1111 setPrefLoopAlignment(16);
1112 benefitFromCodePlacementOpt = true;
1114 setPrefFunctionAlignment(4);
1118 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1123 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1124 /// the desired ByVal argument alignment.
1125 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1128 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1129 if (VTy->getBitWidth() == 128)
1131 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1132 unsigned EltAlign = 0;
1133 getMaxByValAlign(ATy->getElementType(), EltAlign);
1134 if (EltAlign > MaxAlign)
1135 MaxAlign = EltAlign;
1136 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1137 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1138 unsigned EltAlign = 0;
1139 getMaxByValAlign(STy->getElementType(i), EltAlign);
1140 if (EltAlign > MaxAlign)
1141 MaxAlign = EltAlign;
1149 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1150 /// function arguments in the caller parameter area. For X86, aggregates
1151 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1152 /// are at 4-byte boundaries.
1153 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1154 if (Subtarget->is64Bit()) {
1155 // Max of 8 and alignment of type.
1156 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1163 if (Subtarget->hasXMM())
1164 getMaxByValAlign(Ty, Align);
1168 /// getOptimalMemOpType - Returns the target specific optimal type for load
1169 /// and store operations as a result of memset, memcpy, and memmove
1170 /// lowering. If DstAlign is zero that means it's safe to destination
1171 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1172 /// means there isn't a need to check it against alignment requirement,
1173 /// probably because the source does not need to be loaded. If
1174 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1175 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1176 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1177 /// constant so it does not need to be loaded.
1178 /// It returns EVT::Other if the type should be determined using generic
1179 /// target-independent logic.
1181 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1182 unsigned DstAlign, unsigned SrcAlign,
1183 bool NonScalarIntSafe,
1185 MachineFunction &MF) const {
1186 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1187 // linux. This is because the stack realignment code can't handle certain
1188 // cases like PR2962. This should be removed when PR2962 is fixed.
1189 const Function *F = MF.getFunction();
1190 if (NonScalarIntSafe &&
1191 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1193 (Subtarget->isUnalignedMemAccessFast() ||
1194 ((DstAlign == 0 || DstAlign >= 16) &&
1195 (SrcAlign == 0 || SrcAlign >= 16))) &&
1196 Subtarget->getStackAlignment() >= 16) {
1197 if (Subtarget->hasSSE2())
1199 if (Subtarget->hasSSE1())
1201 } else if (!MemcpyStrSrc && Size >= 8 &&
1202 !Subtarget->is64Bit() &&
1203 Subtarget->getStackAlignment() >= 8 &&
1204 Subtarget->hasXMMInt()) {
1205 // Do not use f64 to lower memcpy if source is string constant. It's
1206 // better to use i32 to avoid the loads.
1210 if (Subtarget->is64Bit() && Size >= 8)
1215 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1216 /// current function. The returned value is a member of the
1217 /// MachineJumpTableInfo::JTEntryKind enum.
1218 unsigned X86TargetLowering::getJumpTableEncoding() const {
1219 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1221 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1222 Subtarget->isPICStyleGOT())
1223 return MachineJumpTableInfo::EK_Custom32;
1225 // Otherwise, use the normal jump table encoding heuristics.
1226 return TargetLowering::getJumpTableEncoding();
1230 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1231 const MachineBasicBlock *MBB,
1232 unsigned uid,MCContext &Ctx) const{
1233 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1234 Subtarget->isPICStyleGOT());
1235 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1237 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1238 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1241 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1243 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1244 SelectionDAG &DAG) const {
1245 if (!Subtarget->is64Bit())
1246 // This doesn't have DebugLoc associated with it, but is not really the
1247 // same as a Register.
1248 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1252 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1253 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1255 const MCExpr *X86TargetLowering::
1256 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1257 MCContext &Ctx) const {
1258 // X86-64 uses RIP relative addressing based on the jump table label.
1259 if (Subtarget->isPICStyleRIPRel())
1260 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1262 // Otherwise, the reference is relative to the PIC base.
1263 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1266 // FIXME: Why this routine is here? Move to RegInfo!
1267 std::pair<const TargetRegisterClass*, uint8_t>
1268 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1269 const TargetRegisterClass *RRC = 0;
1271 switch (VT.getSimpleVT().SimpleTy) {
1273 return TargetLowering::findRepresentativeClass(VT);
1274 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1275 RRC = (Subtarget->is64Bit()
1276 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1279 RRC = X86::VR64RegisterClass;
1281 case MVT::f32: case MVT::f64:
1282 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1283 case MVT::v4f32: case MVT::v2f64:
1284 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1286 RRC = X86::VR128RegisterClass;
1289 return std::make_pair(RRC, Cost);
1292 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1293 unsigned &Offset) const {
1294 if (!Subtarget->isTargetLinux())
1297 if (Subtarget->is64Bit()) {
1298 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1300 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1313 //===----------------------------------------------------------------------===//
1314 // Return Value Calling Convention Implementation
1315 //===----------------------------------------------------------------------===//
1317 #include "X86GenCallingConv.inc"
1320 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1321 MachineFunction &MF, bool isVarArg,
1322 const SmallVectorImpl<ISD::OutputArg> &Outs,
1323 LLVMContext &Context) const {
1324 SmallVector<CCValAssign, 16> RVLocs;
1325 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1327 return CCInfo.CheckReturn(Outs, RetCC_X86);
1331 X86TargetLowering::LowerReturn(SDValue Chain,
1332 CallingConv::ID CallConv, bool isVarArg,
1333 const SmallVectorImpl<ISD::OutputArg> &Outs,
1334 const SmallVectorImpl<SDValue> &OutVals,
1335 DebugLoc dl, SelectionDAG &DAG) const {
1336 MachineFunction &MF = DAG.getMachineFunction();
1337 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1339 SmallVector<CCValAssign, 16> RVLocs;
1340 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1341 RVLocs, *DAG.getContext());
1342 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1344 // Add the regs to the liveout set for the function.
1345 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1346 for (unsigned i = 0; i != RVLocs.size(); ++i)
1347 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1348 MRI.addLiveOut(RVLocs[i].getLocReg());
1352 SmallVector<SDValue, 6> RetOps;
1353 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1354 // Operand #1 = Bytes To Pop
1355 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1358 // Copy the result values into the output registers.
1359 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1360 CCValAssign &VA = RVLocs[i];
1361 assert(VA.isRegLoc() && "Can only return in registers!");
1362 SDValue ValToCopy = OutVals[i];
1363 EVT ValVT = ValToCopy.getValueType();
1365 // If this is x86-64, and we disabled SSE, we can't return FP values,
1366 // or SSE or MMX vectors.
1367 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1368 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1369 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1370 report_fatal_error("SSE register return with SSE disabled");
1372 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1373 // llvm-gcc has never done it right and no one has noticed, so this
1374 // should be OK for now.
1375 if (ValVT == MVT::f64 &&
1376 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1377 report_fatal_error("SSE2 register return with SSE2 disabled");
1379 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1380 // the RET instruction and handled by the FP Stackifier.
1381 if (VA.getLocReg() == X86::ST0 ||
1382 VA.getLocReg() == X86::ST1) {
1383 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1384 // change the value to the FP stack register class.
1385 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1386 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1387 RetOps.push_back(ValToCopy);
1388 // Don't emit a copytoreg.
1392 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1393 // which is returned in RAX / RDX.
1394 if (Subtarget->is64Bit()) {
1395 if (ValVT == MVT::x86mmx) {
1396 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1397 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1398 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1400 // If we don't have SSE2 available, convert to v4f32 so the generated
1401 // register is legal.
1402 if (!Subtarget->hasSSE2())
1403 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1408 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1409 Flag = Chain.getValue(1);
1412 // The x86-64 ABI for returning structs by value requires that we copy
1413 // the sret argument into %rax for the return. We saved the argument into
1414 // a virtual register in the entry block, so now we copy the value out
1416 if (Subtarget->is64Bit() &&
1417 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1418 MachineFunction &MF = DAG.getMachineFunction();
1419 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1420 unsigned Reg = FuncInfo->getSRetReturnReg();
1422 "SRetReturnReg should have been set in LowerFormalArguments().");
1423 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1425 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1426 Flag = Chain.getValue(1);
1428 // RAX now acts like a return value.
1429 MRI.addLiveOut(X86::RAX);
1432 RetOps[0] = Chain; // Update chain.
1434 // Add the flag if we have it.
1436 RetOps.push_back(Flag);
1438 return DAG.getNode(X86ISD::RET_FLAG, dl,
1439 MVT::Other, &RetOps[0], RetOps.size());
1442 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1443 if (N->getNumValues() != 1)
1445 if (!N->hasNUsesOfValue(1, 0))
1448 SDNode *Copy = *N->use_begin();
1449 if (Copy->getOpcode() != ISD::CopyToReg &&
1450 Copy->getOpcode() != ISD::FP_EXTEND)
1453 bool HasRet = false;
1454 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1456 if (UI->getOpcode() != X86ISD::RET_FLAG)
1465 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1466 ISD::NodeType ExtendKind) const {
1468 // TODO: Is this also valid on 32-bit?
1469 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1470 ReturnMVT = MVT::i8;
1472 ReturnMVT = MVT::i32;
1474 EVT MinVT = getRegisterType(Context, ReturnMVT);
1475 return VT.bitsLT(MinVT) ? MinVT : VT;
1478 /// LowerCallResult - Lower the result values of a call into the
1479 /// appropriate copies out of appropriate physical registers.
1482 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1483 CallingConv::ID CallConv, bool isVarArg,
1484 const SmallVectorImpl<ISD::InputArg> &Ins,
1485 DebugLoc dl, SelectionDAG &DAG,
1486 SmallVectorImpl<SDValue> &InVals) const {
1488 // Assign locations to each value returned by this call.
1489 SmallVector<CCValAssign, 16> RVLocs;
1490 bool Is64Bit = Subtarget->is64Bit();
1491 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1492 getTargetMachine(), RVLocs, *DAG.getContext());
1493 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1495 // Copy all of the result registers out of their specified physreg.
1496 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1497 CCValAssign &VA = RVLocs[i];
1498 EVT CopyVT = VA.getValVT();
1500 // If this is x86-64, and we disabled SSE, we can't return FP values
1501 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1502 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1503 report_fatal_error("SSE register return with SSE disabled");
1508 // If this is a call to a function that returns an fp value on the floating
1509 // point stack, we must guarantee the the value is popped from the stack, so
1510 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1511 // if the return value is not used. We use the FpPOP_RETVAL instruction
1513 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1514 // If we prefer to use the value in xmm registers, copy it out as f80 and
1515 // use a truncate to move it from fp stack reg to xmm reg.
1516 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1517 SDValue Ops[] = { Chain, InFlag };
1518 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1519 MVT::Other, MVT::Glue, Ops, 2), 1);
1520 Val = Chain.getValue(0);
1522 // Round the f80 to the right size, which also moves it to the appropriate
1524 if (CopyVT != VA.getValVT())
1525 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1526 // This truncation won't change the value.
1527 DAG.getIntPtrConstant(1));
1529 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1530 CopyVT, InFlag).getValue(1);
1531 Val = Chain.getValue(0);
1533 InFlag = Chain.getValue(2);
1534 InVals.push_back(Val);
1541 //===----------------------------------------------------------------------===//
1542 // C & StdCall & Fast Calling Convention implementation
1543 //===----------------------------------------------------------------------===//
1544 // StdCall calling convention seems to be standard for many Windows' API
1545 // routines and around. It differs from C calling convention just a little:
1546 // callee should clean up the stack, not caller. Symbols should be also
1547 // decorated in some fancy way :) It doesn't support any vector arguments.
1548 // For info on fast calling convention see Fast Calling Convention (tail call)
1549 // implementation LowerX86_32FastCCCallTo.
1551 /// CallIsStructReturn - Determines whether a call uses struct return
1553 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1557 return Outs[0].Flags.isSRet();
1560 /// ArgsAreStructReturn - Determines whether a function uses struct
1561 /// return semantics.
1563 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1567 return Ins[0].Flags.isSRet();
1570 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1571 /// by "Src" to address "Dst" with size and alignment information specified by
1572 /// the specific parameter attribute. The copy will be passed as a byval
1573 /// function parameter.
1575 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1576 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1578 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1580 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1581 /*isVolatile*/false, /*AlwaysInline=*/true,
1582 MachinePointerInfo(), MachinePointerInfo());
1585 /// IsTailCallConvention - Return true if the calling convention is one that
1586 /// supports tail call optimization.
1587 static bool IsTailCallConvention(CallingConv::ID CC) {
1588 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1591 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1592 if (!CI->isTailCall())
1596 CallingConv::ID CalleeCC = CS.getCallingConv();
1597 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1603 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1604 /// a tailcall target by changing its ABI.
1605 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1606 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1610 X86TargetLowering::LowerMemArgument(SDValue Chain,
1611 CallingConv::ID CallConv,
1612 const SmallVectorImpl<ISD::InputArg> &Ins,
1613 DebugLoc dl, SelectionDAG &DAG,
1614 const CCValAssign &VA,
1615 MachineFrameInfo *MFI,
1617 // Create the nodes corresponding to a load from this parameter slot.
1618 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1619 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1620 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1623 // If value is passed by pointer we have address passed instead of the value
1625 if (VA.getLocInfo() == CCValAssign::Indirect)
1626 ValVT = VA.getLocVT();
1628 ValVT = VA.getValVT();
1630 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1631 // changed with more analysis.
1632 // In case of tail call optimization mark all arguments mutable. Since they
1633 // could be overwritten by lowering of arguments in case of a tail call.
1634 if (Flags.isByVal()) {
1635 unsigned Bytes = Flags.getByValSize();
1636 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1637 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1638 return DAG.getFrameIndex(FI, getPointerTy());
1640 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1641 VA.getLocMemOffset(), isImmutable);
1642 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1643 return DAG.getLoad(ValVT, dl, Chain, FIN,
1644 MachinePointerInfo::getFixedStack(FI),
1650 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1651 CallingConv::ID CallConv,
1653 const SmallVectorImpl<ISD::InputArg> &Ins,
1656 SmallVectorImpl<SDValue> &InVals)
1658 MachineFunction &MF = DAG.getMachineFunction();
1659 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1661 const Function* Fn = MF.getFunction();
1662 if (Fn->hasExternalLinkage() &&
1663 Subtarget->isTargetCygMing() &&
1664 Fn->getName() == "main")
1665 FuncInfo->setForceFramePointer(true);
1667 MachineFrameInfo *MFI = MF.getFrameInfo();
1668 bool Is64Bit = Subtarget->is64Bit();
1669 bool IsWin64 = Subtarget->isTargetWin64();
1671 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1672 "Var args not supported with calling convention fastcc or ghc");
1674 // Assign locations to all of the incoming arguments.
1675 SmallVector<CCValAssign, 16> ArgLocs;
1676 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1677 ArgLocs, *DAG.getContext());
1679 // Allocate shadow area for Win64
1681 CCInfo.AllocateStack(32, 8);
1684 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1686 unsigned LastVal = ~0U;
1688 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1689 CCValAssign &VA = ArgLocs[i];
1690 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1692 assert(VA.getValNo() != LastVal &&
1693 "Don't support value assigned to multiple locs yet");
1694 LastVal = VA.getValNo();
1696 if (VA.isRegLoc()) {
1697 EVT RegVT = VA.getLocVT();
1698 TargetRegisterClass *RC = NULL;
1699 if (RegVT == MVT::i32)
1700 RC = X86::GR32RegisterClass;
1701 else if (Is64Bit && RegVT == MVT::i64)
1702 RC = X86::GR64RegisterClass;
1703 else if (RegVT == MVT::f32)
1704 RC = X86::FR32RegisterClass;
1705 else if (RegVT == MVT::f64)
1706 RC = X86::FR64RegisterClass;
1707 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1708 RC = X86::VR256RegisterClass;
1709 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1710 RC = X86::VR128RegisterClass;
1711 else if (RegVT == MVT::x86mmx)
1712 RC = X86::VR64RegisterClass;
1714 llvm_unreachable("Unknown argument type!");
1716 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1717 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1719 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1720 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1722 if (VA.getLocInfo() == CCValAssign::SExt)
1723 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1724 DAG.getValueType(VA.getValVT()));
1725 else if (VA.getLocInfo() == CCValAssign::ZExt)
1726 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1727 DAG.getValueType(VA.getValVT()));
1728 else if (VA.getLocInfo() == CCValAssign::BCvt)
1729 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1731 if (VA.isExtInLoc()) {
1732 // Handle MMX values passed in XMM regs.
1733 if (RegVT.isVector()) {
1734 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1737 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1740 assert(VA.isMemLoc());
1741 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1744 // If value is passed via pointer - do a load.
1745 if (VA.getLocInfo() == CCValAssign::Indirect)
1746 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1747 MachinePointerInfo(), false, false, 0);
1749 InVals.push_back(ArgValue);
1752 // The x86-64 ABI for returning structs by value requires that we copy
1753 // the sret argument into %rax for the return. Save the argument into
1754 // a virtual register so that we can access it from the return points.
1755 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1756 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1757 unsigned Reg = FuncInfo->getSRetReturnReg();
1759 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1760 FuncInfo->setSRetReturnReg(Reg);
1762 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1763 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1766 unsigned StackSize = CCInfo.getNextStackOffset();
1767 // Align stack specially for tail calls.
1768 if (FuncIsMadeTailCallSafe(CallConv))
1769 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1771 // If the function takes variable number of arguments, make a frame index for
1772 // the start of the first vararg value... for expansion of llvm.va_start.
1774 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1775 CallConv != CallingConv::X86_ThisCall)) {
1776 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1779 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1781 // FIXME: We should really autogenerate these arrays
1782 static const unsigned GPR64ArgRegsWin64[] = {
1783 X86::RCX, X86::RDX, X86::R8, X86::R9
1785 static const unsigned GPR64ArgRegs64Bit[] = {
1786 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1788 static const unsigned XMMArgRegs64Bit[] = {
1789 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1790 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1792 const unsigned *GPR64ArgRegs;
1793 unsigned NumXMMRegs = 0;
1796 // The XMM registers which might contain var arg parameters are shadowed
1797 // in their paired GPR. So we only need to save the GPR to their home
1799 TotalNumIntRegs = 4;
1800 GPR64ArgRegs = GPR64ArgRegsWin64;
1802 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1803 GPR64ArgRegs = GPR64ArgRegs64Bit;
1805 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1807 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1810 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1811 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1812 "SSE register cannot be used when SSE is disabled!");
1813 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1814 "SSE register cannot be used when SSE is disabled!");
1815 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1816 // Kernel mode asks for SSE to be disabled, so don't push them
1818 TotalNumXMMRegs = 0;
1821 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1822 // Get to the caller-allocated home save location. Add 8 to account
1823 // for the return address.
1824 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1825 FuncInfo->setRegSaveFrameIndex(
1826 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1827 // Fixup to set vararg frame on shadow area (4 x i64).
1829 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1831 // For X86-64, if there are vararg parameters that are passed via
1832 // registers, then we must store them to their spots on the stack so they
1833 // may be loaded by deferencing the result of va_next.
1834 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1835 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1836 FuncInfo->setRegSaveFrameIndex(
1837 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1841 // Store the integer parameter registers.
1842 SmallVector<SDValue, 8> MemOps;
1843 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1845 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1846 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1847 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1848 DAG.getIntPtrConstant(Offset));
1849 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1850 X86::GR64RegisterClass);
1851 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1853 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1854 MachinePointerInfo::getFixedStack(
1855 FuncInfo->getRegSaveFrameIndex(), Offset),
1857 MemOps.push_back(Store);
1861 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1862 // Now store the XMM (fp + vector) parameter registers.
1863 SmallVector<SDValue, 11> SaveXMMOps;
1864 SaveXMMOps.push_back(Chain);
1866 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1867 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1868 SaveXMMOps.push_back(ALVal);
1870 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1871 FuncInfo->getRegSaveFrameIndex()));
1872 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1873 FuncInfo->getVarArgsFPOffset()));
1875 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1876 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1877 X86::VR128RegisterClass);
1878 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1879 SaveXMMOps.push_back(Val);
1881 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1883 &SaveXMMOps[0], SaveXMMOps.size()));
1886 if (!MemOps.empty())
1887 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1888 &MemOps[0], MemOps.size());
1892 // Some CCs need callee pop.
1893 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1894 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1896 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1897 // If this is an sret function, the return should pop the hidden pointer.
1898 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1899 FuncInfo->setBytesToPopOnReturn(4);
1903 // RegSaveFrameIndex is X86-64 only.
1904 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1905 if (CallConv == CallingConv::X86_FastCall ||
1906 CallConv == CallingConv::X86_ThisCall)
1907 // fastcc functions can't have varargs.
1908 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1915 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1916 SDValue StackPtr, SDValue Arg,
1917 DebugLoc dl, SelectionDAG &DAG,
1918 const CCValAssign &VA,
1919 ISD::ArgFlagsTy Flags) const {
1920 unsigned LocMemOffset = VA.getLocMemOffset();
1921 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1922 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1923 if (Flags.isByVal())
1924 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1926 return DAG.getStore(Chain, dl, Arg, PtrOff,
1927 MachinePointerInfo::getStack(LocMemOffset),
1931 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1932 /// optimization is performed and it is required.
1934 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1935 SDValue &OutRetAddr, SDValue Chain,
1936 bool IsTailCall, bool Is64Bit,
1937 int FPDiff, DebugLoc dl) const {
1938 // Adjust the Return address stack slot.
1939 EVT VT = getPointerTy();
1940 OutRetAddr = getReturnAddressFrameIndex(DAG);
1942 // Load the "old" Return address.
1943 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1945 return SDValue(OutRetAddr.getNode(), 1);
1948 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1949 /// optimization is performed and it is required (FPDiff!=0).
1951 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1952 SDValue Chain, SDValue RetAddrFrIdx,
1953 bool Is64Bit, int FPDiff, DebugLoc dl) {
1954 // Store the return address to the appropriate stack slot.
1955 if (!FPDiff) return Chain;
1956 // Calculate the new stack slot for the return address.
1957 int SlotSize = Is64Bit ? 8 : 4;
1958 int NewReturnAddrFI =
1959 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1960 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1961 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1962 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1963 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1969 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1970 CallingConv::ID CallConv, bool isVarArg,
1972 const SmallVectorImpl<ISD::OutputArg> &Outs,
1973 const SmallVectorImpl<SDValue> &OutVals,
1974 const SmallVectorImpl<ISD::InputArg> &Ins,
1975 DebugLoc dl, SelectionDAG &DAG,
1976 SmallVectorImpl<SDValue> &InVals) const {
1977 MachineFunction &MF = DAG.getMachineFunction();
1978 bool Is64Bit = Subtarget->is64Bit();
1979 bool IsWin64 = Subtarget->isTargetWin64();
1980 bool IsStructRet = CallIsStructReturn(Outs);
1981 bool IsSibcall = false;
1984 // Check if it's really possible to do a tail call.
1985 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1986 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1987 Outs, OutVals, Ins, DAG);
1989 // Sibcalls are automatically detected tailcalls which do not require
1991 if (!GuaranteedTailCallOpt && isTailCall)
1998 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1999 "Var args not supported with calling convention fastcc or ghc");
2001 // Analyze operands of the call, assigning locations to each operand.
2002 SmallVector<CCValAssign, 16> ArgLocs;
2003 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2004 ArgLocs, *DAG.getContext());
2006 // Allocate shadow area for Win64
2008 CCInfo.AllocateStack(32, 8);
2011 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2013 // Get a count of how many bytes are to be pushed on the stack.
2014 unsigned NumBytes = CCInfo.getNextStackOffset();
2016 // This is a sibcall. The memory operands are available in caller's
2017 // own caller's stack.
2019 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2020 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2023 if (isTailCall && !IsSibcall) {
2024 // Lower arguments at fp - stackoffset + fpdiff.
2025 unsigned NumBytesCallerPushed =
2026 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2027 FPDiff = NumBytesCallerPushed - NumBytes;
2029 // Set the delta of movement of the returnaddr stackslot.
2030 // But only set if delta is greater than previous delta.
2031 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2032 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2036 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2038 SDValue RetAddrFrIdx;
2039 // Load return address for tail calls.
2040 if (isTailCall && FPDiff)
2041 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2042 Is64Bit, FPDiff, dl);
2044 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2045 SmallVector<SDValue, 8> MemOpChains;
2048 // Walk the register/memloc assignments, inserting copies/loads. In the case
2049 // of tail call optimization arguments are handle later.
2050 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2051 CCValAssign &VA = ArgLocs[i];
2052 EVT RegVT = VA.getLocVT();
2053 SDValue Arg = OutVals[i];
2054 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2055 bool isByVal = Flags.isByVal();
2057 // Promote the value if needed.
2058 switch (VA.getLocInfo()) {
2059 default: llvm_unreachable("Unknown loc info!");
2060 case CCValAssign::Full: break;
2061 case CCValAssign::SExt:
2062 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2064 case CCValAssign::ZExt:
2065 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2067 case CCValAssign::AExt:
2068 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2069 // Special case: passing MMX values in XMM registers.
2070 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2071 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2072 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2074 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2076 case CCValAssign::BCvt:
2077 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2079 case CCValAssign::Indirect: {
2080 // Store the argument.
2081 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2082 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2083 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2084 MachinePointerInfo::getFixedStack(FI),
2091 if (VA.isRegLoc()) {
2092 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2093 if (isVarArg && IsWin64) {
2094 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2095 // shadow reg if callee is a varargs function.
2096 unsigned ShadowReg = 0;
2097 switch (VA.getLocReg()) {
2098 case X86::XMM0: ShadowReg = X86::RCX; break;
2099 case X86::XMM1: ShadowReg = X86::RDX; break;
2100 case X86::XMM2: ShadowReg = X86::R8; break;
2101 case X86::XMM3: ShadowReg = X86::R9; break;
2104 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2106 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2107 assert(VA.isMemLoc());
2108 if (StackPtr.getNode() == 0)
2109 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2110 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2111 dl, DAG, VA, Flags));
2115 if (!MemOpChains.empty())
2116 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2117 &MemOpChains[0], MemOpChains.size());
2119 // Build a sequence of copy-to-reg nodes chained together with token chain
2120 // and flag operands which copy the outgoing args into registers.
2122 // Tail call byval lowering might overwrite argument registers so in case of
2123 // tail call optimization the copies to registers are lowered later.
2125 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2126 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2127 RegsToPass[i].second, InFlag);
2128 InFlag = Chain.getValue(1);
2131 if (Subtarget->isPICStyleGOT()) {
2132 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2135 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2136 DAG.getNode(X86ISD::GlobalBaseReg,
2137 DebugLoc(), getPointerTy()),
2139 InFlag = Chain.getValue(1);
2141 // If we are tail calling and generating PIC/GOT style code load the
2142 // address of the callee into ECX. The value in ecx is used as target of
2143 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2144 // for tail calls on PIC/GOT architectures. Normally we would just put the
2145 // address of GOT into ebx and then call target@PLT. But for tail calls
2146 // ebx would be restored (since ebx is callee saved) before jumping to the
2149 // Note: The actual moving to ECX is done further down.
2150 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2151 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2152 !G->getGlobal()->hasProtectedVisibility())
2153 Callee = LowerGlobalAddress(Callee, DAG);
2154 else if (isa<ExternalSymbolSDNode>(Callee))
2155 Callee = LowerExternalSymbol(Callee, DAG);
2159 if (Is64Bit && isVarArg && !IsWin64) {
2160 // From AMD64 ABI document:
2161 // For calls that may call functions that use varargs or stdargs
2162 // (prototype-less calls or calls to functions containing ellipsis (...) in
2163 // the declaration) %al is used as hidden argument to specify the number
2164 // of SSE registers used. The contents of %al do not need to match exactly
2165 // the number of registers, but must be an ubound on the number of SSE
2166 // registers used and is in the range 0 - 8 inclusive.
2168 // Count the number of XMM registers allocated.
2169 static const unsigned XMMArgRegs[] = {
2170 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2171 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2173 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2174 assert((Subtarget->hasXMM() || !NumXMMRegs)
2175 && "SSE registers cannot be used when SSE is disabled");
2177 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2178 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2179 InFlag = Chain.getValue(1);
2183 // For tail calls lower the arguments to the 'real' stack slot.
2185 // Force all the incoming stack arguments to be loaded from the stack
2186 // before any new outgoing arguments are stored to the stack, because the
2187 // outgoing stack slots may alias the incoming argument stack slots, and
2188 // the alias isn't otherwise explicit. This is slightly more conservative
2189 // than necessary, because it means that each store effectively depends
2190 // on every argument instead of just those arguments it would clobber.
2191 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2193 SmallVector<SDValue, 8> MemOpChains2;
2196 // Do not flag preceding copytoreg stuff together with the following stuff.
2198 if (GuaranteedTailCallOpt) {
2199 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2200 CCValAssign &VA = ArgLocs[i];
2203 assert(VA.isMemLoc());
2204 SDValue Arg = OutVals[i];
2205 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2206 // Create frame index.
2207 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2208 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2209 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2210 FIN = DAG.getFrameIndex(FI, getPointerTy());
2212 if (Flags.isByVal()) {
2213 // Copy relative to framepointer.
2214 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2215 if (StackPtr.getNode() == 0)
2216 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2218 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2220 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2224 // Store relative to framepointer.
2225 MemOpChains2.push_back(
2226 DAG.getStore(ArgChain, dl, Arg, FIN,
2227 MachinePointerInfo::getFixedStack(FI),
2233 if (!MemOpChains2.empty())
2234 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2235 &MemOpChains2[0], MemOpChains2.size());
2237 // Copy arguments to their registers.
2238 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2239 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2240 RegsToPass[i].second, InFlag);
2241 InFlag = Chain.getValue(1);
2245 // Store the return address to the appropriate stack slot.
2246 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2250 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2251 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2252 // In the 64-bit large code model, we have to make all calls
2253 // through a register, since the call instruction's 32-bit
2254 // pc-relative offset may not be large enough to hold the whole
2256 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2257 // If the callee is a GlobalAddress node (quite common, every direct call
2258 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2261 // We should use extra load for direct calls to dllimported functions in
2263 const GlobalValue *GV = G->getGlobal();
2264 if (!GV->hasDLLImportLinkage()) {
2265 unsigned char OpFlags = 0;
2266 bool ExtraLoad = false;
2267 unsigned WrapperKind = ISD::DELETED_NODE;
2269 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2270 // external symbols most go through the PLT in PIC mode. If the symbol
2271 // has hidden or protected visibility, or if it is static or local, then
2272 // we don't need to use the PLT - we can directly call it.
2273 if (Subtarget->isTargetELF() &&
2274 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2275 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2276 OpFlags = X86II::MO_PLT;
2277 } else if (Subtarget->isPICStyleStubAny() &&
2278 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2279 (!Subtarget->getTargetTriple().isMacOSX() ||
2280 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2281 // PC-relative references to external symbols should go through $stub,
2282 // unless we're building with the leopard linker or later, which
2283 // automatically synthesizes these stubs.
2284 OpFlags = X86II::MO_DARWIN_STUB;
2285 } else if (Subtarget->isPICStyleRIPRel() &&
2286 isa<Function>(GV) &&
2287 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2288 // If the function is marked as non-lazy, generate an indirect call
2289 // which loads from the GOT directly. This avoids runtime overhead
2290 // at the cost of eager binding (and one extra byte of encoding).
2291 OpFlags = X86II::MO_GOTPCREL;
2292 WrapperKind = X86ISD::WrapperRIP;
2296 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2297 G->getOffset(), OpFlags);
2299 // Add a wrapper if needed.
2300 if (WrapperKind != ISD::DELETED_NODE)
2301 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2302 // Add extra indirection if needed.
2304 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2305 MachinePointerInfo::getGOT(),
2308 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2309 unsigned char OpFlags = 0;
2311 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2312 // external symbols should go through the PLT.
2313 if (Subtarget->isTargetELF() &&
2314 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2315 OpFlags = X86II::MO_PLT;
2316 } else if (Subtarget->isPICStyleStubAny() &&
2317 (!Subtarget->getTargetTriple().isMacOSX() ||
2318 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2319 // PC-relative references to external symbols should go through $stub,
2320 // unless we're building with the leopard linker or later, which
2321 // automatically synthesizes these stubs.
2322 OpFlags = X86II::MO_DARWIN_STUB;
2325 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2329 // Returns a chain & a flag for retval copy to use.
2330 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2331 SmallVector<SDValue, 8> Ops;
2333 if (!IsSibcall && isTailCall) {
2334 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2335 DAG.getIntPtrConstant(0, true), InFlag);
2336 InFlag = Chain.getValue(1);
2339 Ops.push_back(Chain);
2340 Ops.push_back(Callee);
2343 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2345 // Add argument registers to the end of the list so that they are known live
2347 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2348 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2349 RegsToPass[i].second.getValueType()));
2351 // Add an implicit use GOT pointer in EBX.
2352 if (!isTailCall && Subtarget->isPICStyleGOT())
2353 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2355 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2356 if (Is64Bit && isVarArg && !IsWin64)
2357 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2359 if (InFlag.getNode())
2360 Ops.push_back(InFlag);
2364 //// If this is the first return lowered for this function, add the regs
2365 //// to the liveout set for the function.
2366 // This isn't right, although it's probably harmless on x86; liveouts
2367 // should be computed from returns not tail calls. Consider a void
2368 // function making a tail call to a function returning int.
2369 return DAG.getNode(X86ISD::TC_RETURN, dl,
2370 NodeTys, &Ops[0], Ops.size());
2373 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2374 InFlag = Chain.getValue(1);
2376 // Create the CALLSEQ_END node.
2377 unsigned NumBytesForCalleeToPush;
2378 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2379 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2380 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2381 // If this is a call to a struct-return function, the callee
2382 // pops the hidden struct pointer, so we have to push it back.
2383 // This is common for Darwin/X86, Linux & Mingw32 targets.
2384 NumBytesForCalleeToPush = 4;
2386 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2388 // Returns a flag for retval copy to use.
2390 Chain = DAG.getCALLSEQ_END(Chain,
2391 DAG.getIntPtrConstant(NumBytes, true),
2392 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2395 InFlag = Chain.getValue(1);
2398 // Handle result values, copying them out of physregs into vregs that we
2400 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2401 Ins, dl, DAG, InVals);
2405 //===----------------------------------------------------------------------===//
2406 // Fast Calling Convention (tail call) implementation
2407 //===----------------------------------------------------------------------===//
2409 // Like std call, callee cleans arguments, convention except that ECX is
2410 // reserved for storing the tail called function address. Only 2 registers are
2411 // free for argument passing (inreg). Tail call optimization is performed
2413 // * tailcallopt is enabled
2414 // * caller/callee are fastcc
2415 // On X86_64 architecture with GOT-style position independent code only local
2416 // (within module) calls are supported at the moment.
2417 // To keep the stack aligned according to platform abi the function
2418 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2419 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2420 // If a tail called function callee has more arguments than the caller the
2421 // caller needs to make sure that there is room to move the RETADDR to. This is
2422 // achieved by reserving an area the size of the argument delta right after the
2423 // original REtADDR, but before the saved framepointer or the spilled registers
2424 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2436 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2437 /// for a 16 byte align requirement.
2439 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2440 SelectionDAG& DAG) const {
2441 MachineFunction &MF = DAG.getMachineFunction();
2442 const TargetMachine &TM = MF.getTarget();
2443 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2444 unsigned StackAlignment = TFI.getStackAlignment();
2445 uint64_t AlignMask = StackAlignment - 1;
2446 int64_t Offset = StackSize;
2447 uint64_t SlotSize = TD->getPointerSize();
2448 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2449 // Number smaller than 12 so just add the difference.
2450 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2452 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2453 Offset = ((~AlignMask) & Offset) + StackAlignment +
2454 (StackAlignment-SlotSize);
2459 /// MatchingStackOffset - Return true if the given stack call argument is
2460 /// already available in the same position (relatively) of the caller's
2461 /// incoming argument stack.
2463 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2464 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2465 const X86InstrInfo *TII) {
2466 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2468 if (Arg.getOpcode() == ISD::CopyFromReg) {
2469 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2470 if (!TargetRegisterInfo::isVirtualRegister(VR))
2472 MachineInstr *Def = MRI->getVRegDef(VR);
2475 if (!Flags.isByVal()) {
2476 if (!TII->isLoadFromStackSlot(Def, FI))
2479 unsigned Opcode = Def->getOpcode();
2480 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2481 Def->getOperand(1).isFI()) {
2482 FI = Def->getOperand(1).getIndex();
2483 Bytes = Flags.getByValSize();
2487 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2488 if (Flags.isByVal())
2489 // ByVal argument is passed in as a pointer but it's now being
2490 // dereferenced. e.g.
2491 // define @foo(%struct.X* %A) {
2492 // tail call @bar(%struct.X* byval %A)
2495 SDValue Ptr = Ld->getBasePtr();
2496 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2499 FI = FINode->getIndex();
2500 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2501 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2502 FI = FINode->getIndex();
2503 Bytes = Flags.getByValSize();
2507 assert(FI != INT_MAX);
2508 if (!MFI->isFixedObjectIndex(FI))
2510 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2513 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2514 /// for tail call optimization. Targets which want to do tail call
2515 /// optimization should implement this function.
2517 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2518 CallingConv::ID CalleeCC,
2520 bool isCalleeStructRet,
2521 bool isCallerStructRet,
2522 const SmallVectorImpl<ISD::OutputArg> &Outs,
2523 const SmallVectorImpl<SDValue> &OutVals,
2524 const SmallVectorImpl<ISD::InputArg> &Ins,
2525 SelectionDAG& DAG) const {
2526 if (!IsTailCallConvention(CalleeCC) &&
2527 CalleeCC != CallingConv::C)
2530 // If -tailcallopt is specified, make fastcc functions tail-callable.
2531 const MachineFunction &MF = DAG.getMachineFunction();
2532 const Function *CallerF = DAG.getMachineFunction().getFunction();
2533 CallingConv::ID CallerCC = CallerF->getCallingConv();
2534 bool CCMatch = CallerCC == CalleeCC;
2536 if (GuaranteedTailCallOpt) {
2537 if (IsTailCallConvention(CalleeCC) && CCMatch)
2542 // Look for obvious safe cases to perform tail call optimization that do not
2543 // require ABI changes. This is what gcc calls sibcall.
2545 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2546 // emit a special epilogue.
2547 if (RegInfo->needsStackRealignment(MF))
2550 // Also avoid sibcall optimization if either caller or callee uses struct
2551 // return semantics.
2552 if (isCalleeStructRet || isCallerStructRet)
2555 // An stdcall caller is expected to clean up its arguments; the callee
2556 // isn't going to do that.
2557 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2560 // Do not sibcall optimize vararg calls unless all arguments are passed via
2562 if (isVarArg && !Outs.empty()) {
2564 // Optimizing for varargs on Win64 is unlikely to be safe without
2565 // additional testing.
2566 if (Subtarget->isTargetWin64())
2569 SmallVector<CCValAssign, 16> ArgLocs;
2570 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2571 getTargetMachine(), ArgLocs, *DAG.getContext());
2573 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2574 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2575 if (!ArgLocs[i].isRegLoc())
2579 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2580 // Therefore if it's not used by the call it is not safe to optimize this into
2582 bool Unused = false;
2583 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2590 SmallVector<CCValAssign, 16> RVLocs;
2591 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2592 getTargetMachine(), RVLocs, *DAG.getContext());
2593 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2594 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2595 CCValAssign &VA = RVLocs[i];
2596 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2601 // If the calling conventions do not match, then we'd better make sure the
2602 // results are returned in the same way as what the caller expects.
2604 SmallVector<CCValAssign, 16> RVLocs1;
2605 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2606 getTargetMachine(), RVLocs1, *DAG.getContext());
2607 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2609 SmallVector<CCValAssign, 16> RVLocs2;
2610 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2611 getTargetMachine(), RVLocs2, *DAG.getContext());
2612 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2614 if (RVLocs1.size() != RVLocs2.size())
2616 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2617 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2619 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2621 if (RVLocs1[i].isRegLoc()) {
2622 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2625 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2631 // If the callee takes no arguments then go on to check the results of the
2633 if (!Outs.empty()) {
2634 // Check if stack adjustment is needed. For now, do not do this if any
2635 // argument is passed on the stack.
2636 SmallVector<CCValAssign, 16> ArgLocs;
2637 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2638 getTargetMachine(), ArgLocs, *DAG.getContext());
2640 // Allocate shadow area for Win64
2641 if (Subtarget->isTargetWin64()) {
2642 CCInfo.AllocateStack(32, 8);
2645 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2646 if (CCInfo.getNextStackOffset()) {
2647 MachineFunction &MF = DAG.getMachineFunction();
2648 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2651 // Check if the arguments are already laid out in the right way as
2652 // the caller's fixed stack objects.
2653 MachineFrameInfo *MFI = MF.getFrameInfo();
2654 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2655 const X86InstrInfo *TII =
2656 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2657 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2658 CCValAssign &VA = ArgLocs[i];
2659 SDValue Arg = OutVals[i];
2660 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2661 if (VA.getLocInfo() == CCValAssign::Indirect)
2663 if (!VA.isRegLoc()) {
2664 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2671 // If the tailcall address may be in a register, then make sure it's
2672 // possible to register allocate for it. In 32-bit, the call address can
2673 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2674 // callee-saved registers are restored. These happen to be the same
2675 // registers used to pass 'inreg' arguments so watch out for those.
2676 if (!Subtarget->is64Bit() &&
2677 !isa<GlobalAddressSDNode>(Callee) &&
2678 !isa<ExternalSymbolSDNode>(Callee)) {
2679 unsigned NumInRegs = 0;
2680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2681 CCValAssign &VA = ArgLocs[i];
2684 unsigned Reg = VA.getLocReg();
2687 case X86::EAX: case X86::EDX: case X86::ECX:
2688 if (++NumInRegs == 3)
2700 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2701 return X86::createFastISel(funcInfo);
2705 //===----------------------------------------------------------------------===//
2706 // Other Lowering Hooks
2707 //===----------------------------------------------------------------------===//
2709 static bool MayFoldLoad(SDValue Op) {
2710 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2713 static bool MayFoldIntoStore(SDValue Op) {
2714 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2717 static bool isTargetShuffle(unsigned Opcode) {
2719 default: return false;
2720 case X86ISD::PSHUFD:
2721 case X86ISD::PSHUFHW:
2722 case X86ISD::PSHUFLW:
2723 case X86ISD::SHUFPD:
2724 case X86ISD::PALIGN:
2725 case X86ISD::SHUFPS:
2726 case X86ISD::MOVLHPS:
2727 case X86ISD::MOVLHPD:
2728 case X86ISD::MOVHLPS:
2729 case X86ISD::MOVLPS:
2730 case X86ISD::MOVLPD:
2731 case X86ISD::MOVSHDUP:
2732 case X86ISD::MOVSLDUP:
2733 case X86ISD::MOVDDUP:
2736 case X86ISD::UNPCKLPS:
2737 case X86ISD::UNPCKLPD:
2738 case X86ISD::VUNPCKLPSY:
2739 case X86ISD::VUNPCKLPDY:
2740 case X86ISD::PUNPCKLWD:
2741 case X86ISD::PUNPCKLBW:
2742 case X86ISD::PUNPCKLDQ:
2743 case X86ISD::PUNPCKLQDQ:
2744 case X86ISD::UNPCKHPS:
2745 case X86ISD::UNPCKHPD:
2746 case X86ISD::VUNPCKHPSY:
2747 case X86ISD::VUNPCKHPDY:
2748 case X86ISD::PUNPCKHWD:
2749 case X86ISD::PUNPCKHBW:
2750 case X86ISD::PUNPCKHDQ:
2751 case X86ISD::PUNPCKHQDQ:
2752 case X86ISD::VPERMILPS:
2753 case X86ISD::VPERMILPSY:
2754 case X86ISD::VPERMILPD:
2755 case X86ISD::VPERMILPDY:
2761 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2762 SDValue V1, SelectionDAG &DAG) {
2764 default: llvm_unreachable("Unknown x86 shuffle node");
2765 case X86ISD::MOVSHDUP:
2766 case X86ISD::MOVSLDUP:
2767 case X86ISD::MOVDDUP:
2768 return DAG.getNode(Opc, dl, VT, V1);
2774 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2775 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2777 default: llvm_unreachable("Unknown x86 shuffle node");
2778 case X86ISD::PSHUFD:
2779 case X86ISD::PSHUFHW:
2780 case X86ISD::PSHUFLW:
2781 case X86ISD::VPERMILPS:
2782 case X86ISD::VPERMILPSY:
2783 case X86ISD::VPERMILPD:
2784 case X86ISD::VPERMILPDY:
2785 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2791 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2792 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2794 default: llvm_unreachable("Unknown x86 shuffle node");
2795 case X86ISD::PALIGN:
2796 case X86ISD::SHUFPD:
2797 case X86ISD::SHUFPS:
2798 return DAG.getNode(Opc, dl, VT, V1, V2,
2799 DAG.getConstant(TargetMask, MVT::i8));
2804 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2805 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2807 default: llvm_unreachable("Unknown x86 shuffle node");
2808 case X86ISD::MOVLHPS:
2809 case X86ISD::MOVLHPD:
2810 case X86ISD::MOVHLPS:
2811 case X86ISD::MOVLPS:
2812 case X86ISD::MOVLPD:
2815 case X86ISD::UNPCKLPS:
2816 case X86ISD::UNPCKLPD:
2817 case X86ISD::VUNPCKLPSY:
2818 case X86ISD::VUNPCKLPDY:
2819 case X86ISD::PUNPCKLWD:
2820 case X86ISD::PUNPCKLBW:
2821 case X86ISD::PUNPCKLDQ:
2822 case X86ISD::PUNPCKLQDQ:
2823 case X86ISD::UNPCKHPS:
2824 case X86ISD::UNPCKHPD:
2825 case X86ISD::VUNPCKHPSY:
2826 case X86ISD::VUNPCKHPDY:
2827 case X86ISD::PUNPCKHWD:
2828 case X86ISD::PUNPCKHBW:
2829 case X86ISD::PUNPCKHDQ:
2830 case X86ISD::PUNPCKHQDQ:
2831 return DAG.getNode(Opc, dl, VT, V1, V2);
2836 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2837 MachineFunction &MF = DAG.getMachineFunction();
2838 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2839 int ReturnAddrIndex = FuncInfo->getRAIndex();
2841 if (ReturnAddrIndex == 0) {
2842 // Set up a frame object for the return address.
2843 uint64_t SlotSize = TD->getPointerSize();
2844 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2846 FuncInfo->setRAIndex(ReturnAddrIndex);
2849 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2853 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2854 bool hasSymbolicDisplacement) {
2855 // Offset should fit into 32 bit immediate field.
2856 if (!isInt<32>(Offset))
2859 // If we don't have a symbolic displacement - we don't have any extra
2861 if (!hasSymbolicDisplacement)
2864 // FIXME: Some tweaks might be needed for medium code model.
2865 if (M != CodeModel::Small && M != CodeModel::Kernel)
2868 // For small code model we assume that latest object is 16MB before end of 31
2869 // bits boundary. We may also accept pretty large negative constants knowing
2870 // that all objects are in the positive half of address space.
2871 if (M == CodeModel::Small && Offset < 16*1024*1024)
2874 // For kernel code model we know that all object resist in the negative half
2875 // of 32bits address space. We may not accept negative offsets, since they may
2876 // be just off and we may accept pretty large positive ones.
2877 if (M == CodeModel::Kernel && Offset > 0)
2883 /// isCalleePop - Determines whether the callee is required to pop its
2884 /// own arguments. Callee pop is necessary to support tail calls.
2885 bool X86::isCalleePop(CallingConv::ID CallingConv,
2886 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2890 switch (CallingConv) {
2893 case CallingConv::X86_StdCall:
2895 case CallingConv::X86_FastCall:
2897 case CallingConv::X86_ThisCall:
2899 case CallingConv::Fast:
2901 case CallingConv::GHC:
2906 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2907 /// specific condition code, returning the condition code and the LHS/RHS of the
2908 /// comparison to make.
2909 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2910 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2912 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2913 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2914 // X > -1 -> X == 0, jump !sign.
2915 RHS = DAG.getConstant(0, RHS.getValueType());
2916 return X86::COND_NS;
2917 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2918 // X < 0 -> X == 0, jump on sign.
2920 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2922 RHS = DAG.getConstant(0, RHS.getValueType());
2923 return X86::COND_LE;
2927 switch (SetCCOpcode) {
2928 default: llvm_unreachable("Invalid integer condition!");
2929 case ISD::SETEQ: return X86::COND_E;
2930 case ISD::SETGT: return X86::COND_G;
2931 case ISD::SETGE: return X86::COND_GE;
2932 case ISD::SETLT: return X86::COND_L;
2933 case ISD::SETLE: return X86::COND_LE;
2934 case ISD::SETNE: return X86::COND_NE;
2935 case ISD::SETULT: return X86::COND_B;
2936 case ISD::SETUGT: return X86::COND_A;
2937 case ISD::SETULE: return X86::COND_BE;
2938 case ISD::SETUGE: return X86::COND_AE;
2942 // First determine if it is required or is profitable to flip the operands.
2944 // If LHS is a foldable load, but RHS is not, flip the condition.
2945 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2946 !ISD::isNON_EXTLoad(RHS.getNode())) {
2947 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2948 std::swap(LHS, RHS);
2951 switch (SetCCOpcode) {
2957 std::swap(LHS, RHS);
2961 // On a floating point condition, the flags are set as follows:
2963 // 0 | 0 | 0 | X > Y
2964 // 0 | 0 | 1 | X < Y
2965 // 1 | 0 | 0 | X == Y
2966 // 1 | 1 | 1 | unordered
2967 switch (SetCCOpcode) {
2968 default: llvm_unreachable("Condcode should be pre-legalized away");
2970 case ISD::SETEQ: return X86::COND_E;
2971 case ISD::SETOLT: // flipped
2973 case ISD::SETGT: return X86::COND_A;
2974 case ISD::SETOLE: // flipped
2976 case ISD::SETGE: return X86::COND_AE;
2977 case ISD::SETUGT: // flipped
2979 case ISD::SETLT: return X86::COND_B;
2980 case ISD::SETUGE: // flipped
2982 case ISD::SETLE: return X86::COND_BE;
2984 case ISD::SETNE: return X86::COND_NE;
2985 case ISD::SETUO: return X86::COND_P;
2986 case ISD::SETO: return X86::COND_NP;
2988 case ISD::SETUNE: return X86::COND_INVALID;
2992 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2993 /// code. Current x86 isa includes the following FP cmov instructions:
2994 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2995 static bool hasFPCMov(unsigned X86CC) {
3011 /// isFPImmLegal - Returns true if the target can instruction select the
3012 /// specified FP immediate natively. If false, the legalizer will
3013 /// materialize the FP immediate as a load from a constant pool.
3014 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3015 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3016 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3022 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3023 /// the specified range (L, H].
3024 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3025 return (Val < 0) || (Val >= Low && Val < Hi);
3028 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3029 /// specified value.
3030 static bool isUndefOrEqual(int Val, int CmpVal) {
3031 if (Val < 0 || Val == CmpVal)
3036 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3037 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3038 /// the second operand.
3039 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3040 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3041 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3042 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3043 return (Mask[0] < 2 && Mask[1] < 2);
3047 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3048 SmallVector<int, 8> M;
3050 return ::isPSHUFDMask(M, N->getValueType(0));
3053 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3054 /// is suitable for input to PSHUFHW.
3055 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3056 if (VT != MVT::v8i16)
3059 // Lower quadword copied in order or undef.
3060 for (int i = 0; i != 4; ++i)
3061 if (Mask[i] >= 0 && Mask[i] != i)
3064 // Upper quadword shuffled.
3065 for (int i = 4; i != 8; ++i)
3066 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3072 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3073 SmallVector<int, 8> M;
3075 return ::isPSHUFHWMask(M, N->getValueType(0));
3078 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3079 /// is suitable for input to PSHUFLW.
3080 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3081 if (VT != MVT::v8i16)
3084 // Upper quadword copied in order.
3085 for (int i = 4; i != 8; ++i)
3086 if (Mask[i] >= 0 && Mask[i] != i)
3089 // Lower quadword shuffled.
3090 for (int i = 0; i != 4; ++i)
3097 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3098 SmallVector<int, 8> M;
3100 return ::isPSHUFLWMask(M, N->getValueType(0));
3103 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3104 /// is suitable for input to PALIGNR.
3105 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3107 int i, e = VT.getVectorNumElements();
3108 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3111 // Do not handle v2i64 / v2f64 shuffles with palignr.
3112 if (e < 4 || !hasSSSE3)
3115 for (i = 0; i != e; ++i)
3119 // All undef, not a palignr.
3123 // Make sure we're shifting in the right direction.
3127 int s = Mask[i] - i;
3129 // Check the rest of the elements to see if they are consecutive.
3130 for (++i; i != e; ++i) {
3132 if (m >= 0 && m != s+i)
3138 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3139 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
3140 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3141 int NumElems = VT.getVectorNumElements();
3142 if (NumElems != 2 && NumElems != 4)
3145 int Half = NumElems / 2;
3146 for (int i = 0; i < Half; ++i)
3147 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3149 for (int i = Half; i < NumElems; ++i)
3150 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3156 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3157 SmallVector<int, 8> M;
3159 return ::isSHUFPMask(M, N->getValueType(0));
3162 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3163 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3164 /// half elements to come from vector 1 (which would equal the dest.) and
3165 /// the upper half to come from vector 2.
3166 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3167 int NumElems = VT.getVectorNumElements();
3169 if (NumElems != 2 && NumElems != 4)
3172 int Half = NumElems / 2;
3173 for (int i = 0; i < Half; ++i)
3174 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3176 for (int i = Half; i < NumElems; ++i)
3177 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3182 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3183 SmallVector<int, 8> M;
3185 return isCommutedSHUFPMask(M, N->getValueType(0));
3188 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3189 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3190 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3191 EVT VT = N->getValueType(0);
3192 unsigned NumElems = VT.getVectorNumElements();
3194 if (VT.getSizeInBits() != 128)
3200 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3201 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3202 isUndefOrEqual(N->getMaskElt(1), 7) &&
3203 isUndefOrEqual(N->getMaskElt(2), 2) &&
3204 isUndefOrEqual(N->getMaskElt(3), 3);
3207 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3208 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3210 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3211 EVT VT = N->getValueType(0);
3212 unsigned NumElems = VT.getVectorNumElements();
3214 if (VT.getSizeInBits() != 128)
3220 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3221 isUndefOrEqual(N->getMaskElt(1), 3) &&
3222 isUndefOrEqual(N->getMaskElt(2), 2) &&
3223 isUndefOrEqual(N->getMaskElt(3), 3);
3226 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3227 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3228 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3229 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3231 if (NumElems != 2 && NumElems != 4)
3234 for (unsigned i = 0; i < NumElems/2; ++i)
3235 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3238 for (unsigned i = NumElems/2; i < NumElems; ++i)
3239 if (!isUndefOrEqual(N->getMaskElt(i), i))
3245 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3246 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3247 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3248 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3250 if ((NumElems != 2 && NumElems != 4)
3251 || N->getValueType(0).getSizeInBits() > 128)
3254 for (unsigned i = 0; i < NumElems/2; ++i)
3255 if (!isUndefOrEqual(N->getMaskElt(i), i))
3258 for (unsigned i = 0; i < NumElems/2; ++i)
3259 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3265 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3266 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3267 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3268 bool V2IsSplat = false) {
3269 int NumElts = VT.getVectorNumElements();
3271 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3272 "Unsupported vector type for unpckh");
3274 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3277 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3278 // independently on 128-bit lanes.
3279 unsigned NumLanes = VT.getSizeInBits()/128;
3280 unsigned NumLaneElts = NumElts/NumLanes;
3283 unsigned End = NumLaneElts;
3284 for (unsigned s = 0; s < NumLanes; ++s) {
3285 for (unsigned i = Start, j = s * NumLaneElts;
3289 int BitI1 = Mask[i+1];
3290 if (!isUndefOrEqual(BitI, j))
3293 if (!isUndefOrEqual(BitI1, NumElts))
3296 if (!isUndefOrEqual(BitI1, j + NumElts))
3300 // Process the next 128 bits.
3301 Start += NumLaneElts;
3308 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3309 SmallVector<int, 8> M;
3311 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3314 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3315 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3316 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3317 bool V2IsSplat = false) {
3318 int NumElts = VT.getVectorNumElements();
3320 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3321 "Unsupported vector type for unpckh");
3323 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3326 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3327 // independently on 128-bit lanes.
3328 unsigned NumLanes = VT.getSizeInBits()/128;
3329 unsigned NumLaneElts = NumElts/NumLanes;
3332 unsigned End = NumLaneElts;
3333 for (unsigned l = 0; l != NumLanes; ++l) {
3334 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3335 i != End; i += 2, ++j) {
3337 int BitI1 = Mask[i+1];
3338 if (!isUndefOrEqual(BitI, j))
3341 if (isUndefOrEqual(BitI1, NumElts))
3344 if (!isUndefOrEqual(BitI1, j+NumElts))
3348 // Process the next 128 bits.
3349 Start += NumLaneElts;
3355 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3356 SmallVector<int, 8> M;
3358 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3361 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3362 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3364 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3365 int NumElems = VT.getVectorNumElements();
3366 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3369 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3370 // independently on 128-bit lanes.
3371 unsigned NumLanes = VT.getSizeInBits() / 128;
3372 unsigned NumLaneElts = NumElems / NumLanes;
3374 for (unsigned s = 0; s < NumLanes; ++s) {
3375 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3376 i != NumLaneElts * (s + 1);
3379 int BitI1 = Mask[i+1];
3381 if (!isUndefOrEqual(BitI, j))
3383 if (!isUndefOrEqual(BitI1, j))
3391 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3392 SmallVector<int, 8> M;
3394 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3397 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3398 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3400 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3401 int NumElems = VT.getVectorNumElements();
3402 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3405 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3407 int BitI1 = Mask[i+1];
3408 if (!isUndefOrEqual(BitI, j))
3410 if (!isUndefOrEqual(BitI1, j))
3416 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3417 SmallVector<int, 8> M;
3419 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3422 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3423 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3424 /// MOVSD, and MOVD, i.e. setting the lowest element.
3425 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3426 if (VT.getVectorElementType().getSizeInBits() < 32)
3429 int NumElts = VT.getVectorNumElements();
3431 if (!isUndefOrEqual(Mask[0], NumElts))
3434 for (int i = 1; i < NumElts; ++i)
3435 if (!isUndefOrEqual(Mask[i], i))
3441 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3442 SmallVector<int, 8> M;
3444 return ::isMOVLMask(M, N->getValueType(0));
3447 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3448 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3449 /// Note that VPERMIL mask matching is different depending whether theunderlying
3450 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3451 /// to the same elements of the low, but to the higher half of the source.
3452 /// In VPERMILPD the two lanes could be shuffled independently of each other
3453 /// with the same restriction that lanes can't be crossed.
3454 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3455 const X86Subtarget *Subtarget) {
3456 int NumElts = VT.getVectorNumElements();
3457 int NumLanes = VT.getSizeInBits()/128;
3459 if (!Subtarget->hasAVX())
3462 // Match any permutation of 128-bit vector with 64-bit types
3463 if (NumLanes == 1 && NumElts != 2)
3466 // Only match 256-bit with 32 types
3467 if (VT.getSizeInBits() == 256 && NumElts != 4)
3470 // The mask on the high lane is independent of the low. Both can match
3471 // any element in inside its own lane, but can't cross.
3472 int LaneSize = NumElts/NumLanes;
3473 for (int l = 0; l < NumLanes; ++l)
3474 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3475 int LaneStart = l*LaneSize;
3476 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3483 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3484 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3485 /// Note that VPERMIL mask matching is different depending whether theunderlying
3486 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3487 /// to the same elements of the low, but to the higher half of the source.
3488 /// In VPERMILPD the two lanes could be shuffled independently of each other
3489 /// with the same restriction that lanes can't be crossed.
3490 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3491 const X86Subtarget *Subtarget) {
3492 unsigned NumElts = VT.getVectorNumElements();
3493 unsigned NumLanes = VT.getSizeInBits()/128;
3495 if (!Subtarget->hasAVX())
3498 // Match any permutation of 128-bit vector with 32-bit types
3499 if (NumLanes == 1 && NumElts != 4)
3502 // Only match 256-bit with 32 types
3503 if (VT.getSizeInBits() == 256 && NumElts != 8)
3506 // The mask on the high lane should be the same as the low. Actually,
3507 // they can differ if any of the corresponding index in a lane is undef
3508 // and the other stays in range.
3509 int LaneSize = NumElts/NumLanes;
3510 for (int i = 0; i < LaneSize; ++i) {
3511 int HighElt = i+LaneSize;
3512 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3513 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3515 if (!HighValid || !LowValid)
3517 if (Mask[i] < 0 || Mask[HighElt] < 0)
3519 if (Mask[HighElt]-Mask[i] != LaneSize)
3526 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3527 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3528 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3529 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3530 EVT VT = SVOp->getValueType(0);
3532 int NumElts = VT.getVectorNumElements();
3533 int NumLanes = VT.getSizeInBits()/128;
3534 int LaneSize = NumElts/NumLanes;
3536 // Although the mask is equal for both lanes do it twice to get the cases
3537 // where a mask will match because the same mask element is undef on the
3538 // first half but valid on the second. This would get pathological cases
3539 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3541 for (int l = 0; l < NumLanes; ++l) {
3542 for (int i = 0; i < LaneSize; ++i) {
3543 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3546 if (MaskElt >= LaneSize)
3547 MaskElt -= LaneSize;
3548 Mask |= MaskElt << (i*2);
3555 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3556 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3557 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3558 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3559 EVT VT = SVOp->getValueType(0);
3561 int NumElts = VT.getVectorNumElements();
3562 int NumLanes = VT.getSizeInBits()/128;
3565 int LaneSize = NumElts/NumLanes;
3566 for (int l = 0; l < NumLanes; ++l)
3567 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3568 int MaskElt = SVOp->getMaskElt(i);
3571 Mask |= (MaskElt-l*LaneSize) << i;
3577 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3578 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3579 /// element of vector 2 and the other elements to come from vector 1 in order.
3580 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3581 bool V2IsSplat = false, bool V2IsUndef = false) {
3582 int NumOps = VT.getVectorNumElements();
3583 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3586 if (!isUndefOrEqual(Mask[0], 0))
3589 for (int i = 1; i < NumOps; ++i)
3590 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3591 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3592 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3598 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3599 bool V2IsUndef = false) {
3600 SmallVector<int, 8> M;
3602 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3605 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3606 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3607 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3608 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3609 const X86Subtarget *Subtarget) {
3610 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3613 // The second vector must be undef
3614 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3617 EVT VT = N->getValueType(0);
3618 unsigned NumElems = VT.getVectorNumElements();
3620 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3621 (VT.getSizeInBits() == 256 && NumElems != 8))
3624 // "i+1" is the value the indexed mask element must have
3625 for (unsigned i = 0; i < NumElems; i += 2)
3626 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3627 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3633 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3634 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3635 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3636 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3637 const X86Subtarget *Subtarget) {
3638 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3641 // The second vector must be undef
3642 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3645 EVT VT = N->getValueType(0);
3646 unsigned NumElems = VT.getVectorNumElements();
3648 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3649 (VT.getSizeInBits() == 256 && NumElems != 8))
3652 // "i" is the value the indexed mask element must have
3653 for (unsigned i = 0; i < NumElems; i += 2)
3654 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3655 !isUndefOrEqual(N->getMaskElt(i+1), i))
3661 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3662 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3663 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3664 int e = N->getValueType(0).getVectorNumElements() / 2;
3666 for (int i = 0; i < e; ++i)
3667 if (!isUndefOrEqual(N->getMaskElt(i), i))
3669 for (int i = 0; i < e; ++i)
3670 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3675 /// isVEXTRACTF128Index - Return true if the specified
3676 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3677 /// suitable for input to VEXTRACTF128.
3678 bool X86::isVEXTRACTF128Index(SDNode *N) {
3679 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3682 // The index should be aligned on a 128-bit boundary.
3684 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3686 unsigned VL = N->getValueType(0).getVectorNumElements();
3687 unsigned VBits = N->getValueType(0).getSizeInBits();
3688 unsigned ElSize = VBits / VL;
3689 bool Result = (Index * ElSize) % 128 == 0;
3694 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3695 /// operand specifies a subvector insert that is suitable for input to
3697 bool X86::isVINSERTF128Index(SDNode *N) {
3698 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3701 // The index should be aligned on a 128-bit boundary.
3703 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3705 unsigned VL = N->getValueType(0).getVectorNumElements();
3706 unsigned VBits = N->getValueType(0).getSizeInBits();
3707 unsigned ElSize = VBits / VL;
3708 bool Result = (Index * ElSize) % 128 == 0;
3713 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3714 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3715 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3716 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3717 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3719 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3721 for (int i = 0; i < NumOperands; ++i) {
3722 int Val = SVOp->getMaskElt(NumOperands-i-1);
3723 if (Val < 0) Val = 0;
3724 if (Val >= NumOperands) Val -= NumOperands;
3726 if (i != NumOperands - 1)
3732 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3733 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3734 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3737 // 8 nodes, but we only care about the last 4.
3738 for (unsigned i = 7; i >= 4; --i) {
3739 int Val = SVOp->getMaskElt(i);
3748 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3749 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3750 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3751 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3753 // 8 nodes, but we only care about the first 4.
3754 for (int i = 3; i >= 0; --i) {
3755 int Val = SVOp->getMaskElt(i);
3764 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3765 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3766 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3767 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3768 EVT VVT = N->getValueType(0);
3769 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3773 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3774 Val = SVOp->getMaskElt(i);
3778 assert(Val - i > 0 && "PALIGNR imm should be positive");
3779 return (Val - i) * EltSize;
3782 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3783 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3785 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3786 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3787 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3790 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3792 EVT VecVT = N->getOperand(0).getValueType();
3793 EVT ElVT = VecVT.getVectorElementType();
3795 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3796 return Index / NumElemsPerChunk;
3799 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3800 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3802 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3803 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3804 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3807 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3809 EVT VecVT = N->getValueType(0);
3810 EVT ElVT = VecVT.getVectorElementType();
3812 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3813 return Index / NumElemsPerChunk;
3816 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3818 bool X86::isZeroNode(SDValue Elt) {
3819 return ((isa<ConstantSDNode>(Elt) &&
3820 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3821 (isa<ConstantFPSDNode>(Elt) &&
3822 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3825 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3826 /// their permute mask.
3827 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3828 SelectionDAG &DAG) {
3829 EVT VT = SVOp->getValueType(0);
3830 unsigned NumElems = VT.getVectorNumElements();
3831 SmallVector<int, 8> MaskVec;
3833 for (unsigned i = 0; i != NumElems; ++i) {
3834 int idx = SVOp->getMaskElt(i);
3836 MaskVec.push_back(idx);
3837 else if (idx < (int)NumElems)
3838 MaskVec.push_back(idx + NumElems);
3840 MaskVec.push_back(idx - NumElems);
3842 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3843 SVOp->getOperand(0), &MaskVec[0]);
3846 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3847 /// the two vector operands have swapped position.
3848 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3849 unsigned NumElems = VT.getVectorNumElements();
3850 for (unsigned i = 0; i != NumElems; ++i) {
3854 else if (idx < (int)NumElems)
3855 Mask[i] = idx + NumElems;
3857 Mask[i] = idx - NumElems;
3861 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3862 /// match movhlps. The lower half elements should come from upper half of
3863 /// V1 (and in order), and the upper half elements should come from the upper
3864 /// half of V2 (and in order).
3865 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3866 EVT VT = Op->getValueType(0);
3867 if (VT.getSizeInBits() != 128)
3869 if (VT.getVectorNumElements() != 4)
3871 for (unsigned i = 0, e = 2; i != e; ++i)
3872 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3874 for (unsigned i = 2; i != 4; ++i)
3875 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3880 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3881 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3883 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3884 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3886 N = N->getOperand(0).getNode();
3887 if (!ISD::isNON_EXTLoad(N))
3890 *LD = cast<LoadSDNode>(N);
3894 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3895 /// match movlp{s|d}. The lower half elements should come from lower half of
3896 /// V1 (and in order), and the upper half elements should come from the upper
3897 /// half of V2 (and in order). And since V1 will become the source of the
3898 /// MOVLP, it must be either a vector load or a scalar load to vector.
3899 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3900 ShuffleVectorSDNode *Op) {
3901 EVT VT = Op->getValueType(0);
3902 if (VT.getSizeInBits() != 128)
3905 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3907 // Is V2 is a vector load, don't do this transformation. We will try to use
3908 // load folding shufps op.
3909 if (ISD::isNON_EXTLoad(V2))
3912 unsigned NumElems = VT.getVectorNumElements();
3914 if (NumElems != 2 && NumElems != 4)
3916 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3917 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3919 for (unsigned i = NumElems/2; i != NumElems; ++i)
3920 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3925 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3927 static bool isSplatVector(SDNode *N) {
3928 if (N->getOpcode() != ISD::BUILD_VECTOR)
3931 SDValue SplatValue = N->getOperand(0);
3932 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3933 if (N->getOperand(i) != SplatValue)
3938 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3939 /// to an zero vector.
3940 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3941 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3942 SDValue V1 = N->getOperand(0);
3943 SDValue V2 = N->getOperand(1);
3944 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3945 for (unsigned i = 0; i != NumElems; ++i) {
3946 int Idx = N->getMaskElt(i);
3947 if (Idx >= (int)NumElems) {
3948 unsigned Opc = V2.getOpcode();
3949 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3951 if (Opc != ISD::BUILD_VECTOR ||
3952 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3954 } else if (Idx >= 0) {
3955 unsigned Opc = V1.getOpcode();
3956 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3958 if (Opc != ISD::BUILD_VECTOR ||
3959 !X86::isZeroNode(V1.getOperand(Idx)))
3966 /// getZeroVector - Returns a vector of specified type with all zero elements.
3968 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3970 assert(VT.isVector() && "Expected a vector type");
3972 // Always build SSE zero vectors as <4 x i32> bitcasted
3973 // to their dest type. This ensures they get CSE'd.
3975 if (VT.getSizeInBits() == 128) { // SSE
3976 if (HasSSE2) { // SSE2
3977 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3978 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3980 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3981 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3983 } else if (VT.getSizeInBits() == 256) { // AVX
3984 // 256-bit logic and arithmetic instructions in AVX are
3985 // all floating-point, no support for integer ops. Default
3986 // to emitting fp zeroed vectors then.
3987 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3988 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3989 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3991 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3994 /// getOnesVector - Returns a vector of specified type with all bits set.
3995 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
3996 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
3997 /// original type, ensuring they get CSE'd.
3998 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3999 assert(VT.isVector() && "Expected a vector type");
4000 assert((VT.is128BitVector() || VT.is256BitVector())
4001 && "Expected a 128-bit or 256-bit vector type");
4003 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4004 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4005 Cst, Cst, Cst, Cst);
4007 if (VT.is256BitVector()) {
4008 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4009 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4010 Vec = Insert128BitVector(InsV, Vec,
4011 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4014 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4017 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4018 /// that point to V2 points to its first element.
4019 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4020 EVT VT = SVOp->getValueType(0);
4021 unsigned NumElems = VT.getVectorNumElements();
4023 bool Changed = false;
4024 SmallVector<int, 8> MaskVec;
4025 SVOp->getMask(MaskVec);
4027 for (unsigned i = 0; i != NumElems; ++i) {
4028 if (MaskVec[i] > (int)NumElems) {
4029 MaskVec[i] = NumElems;
4034 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4035 SVOp->getOperand(1), &MaskVec[0]);
4036 return SDValue(SVOp, 0);
4039 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4040 /// operation of specified width.
4041 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4043 unsigned NumElems = VT.getVectorNumElements();
4044 SmallVector<int, 8> Mask;
4045 Mask.push_back(NumElems);
4046 for (unsigned i = 1; i != NumElems; ++i)
4048 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4051 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4052 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4054 unsigned NumElems = VT.getVectorNumElements();
4055 SmallVector<int, 8> Mask;
4056 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4058 Mask.push_back(i + NumElems);
4060 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4063 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4064 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4066 unsigned NumElems = VT.getVectorNumElements();
4067 unsigned Half = NumElems/2;
4068 SmallVector<int, 8> Mask;
4069 for (unsigned i = 0; i != Half; ++i) {
4070 Mask.push_back(i + Half);
4071 Mask.push_back(i + NumElems + Half);
4073 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4076 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4077 // a generic shuffle instruction because the target has no such instructions.
4078 // Generate shuffles which repeat i16 and i8 several times until they can be
4079 // represented by v4f32 and then be manipulated by target suported shuffles.
4080 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4081 EVT VT = V.getValueType();
4082 int NumElems = VT.getVectorNumElements();
4083 DebugLoc dl = V.getDebugLoc();
4085 while (NumElems > 4) {
4086 if (EltNo < NumElems/2) {
4087 V = getUnpackl(DAG, dl, VT, V, V);
4089 V = getUnpackh(DAG, dl, VT, V, V);
4090 EltNo -= NumElems/2;
4097 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4098 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4099 EVT VT = V.getValueType();
4100 DebugLoc dl = V.getDebugLoc();
4101 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4102 && "Vector size not supported");
4104 bool Is128 = VT.getSizeInBits() == 128;
4105 EVT NVT = Is128 ? MVT::v4f32 : MVT::v8f32;
4106 V = DAG.getNode(ISD::BITCAST, dl, NVT, V);
4109 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4110 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
4112 // The second half of indicies refer to the higher part, which is a
4113 // duplication of the lower one. This makes this shuffle a perfect match
4114 // for the VPERM instruction.
4115 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4116 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4117 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
4120 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4123 /// PromoteVectorToScalarSplat - Since there's no native support for
4124 /// scalar_to_vector for 256-bit AVX, a 128-bit scalar_to_vector +
4125 /// INSERT_SUBVECTOR is generated. Recognize this idiom and do the
4126 /// shuffle before the insertion, this yields less instructions in the end.
4127 static SDValue PromoteVectorToScalarSplat(ShuffleVectorSDNode *SV,
4128 SelectionDAG &DAG) {
4129 EVT SrcVT = SV->getValueType(0);
4130 SDValue V1 = SV->getOperand(0);
4131 DebugLoc dl = SV->getDebugLoc();
4132 int NumElems = SrcVT.getVectorNumElements();
4134 assert(SrcVT.is256BitVector() && "unknown howto handle vector type");
4135 assert(SV->isSplat() && "shuffle must be a splat");
4137 int SplatIdx = SV->getSplatIndex();
4138 const int Mask[4] = { SplatIdx, SplatIdx, SplatIdx, SplatIdx };
4140 EVT SVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
4142 SDValue SV1 = DAG.getVectorShuffle(SVT, dl, V1.getOperand(1),
4143 DAG.getUNDEF(SVT), Mask);
4144 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), SV1,
4145 DAG.getConstant(0, MVT::i32), DAG, dl);
4147 return Insert128BitVector(InsV, SV1,
4148 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4151 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and
4152 /// v8i32, v16i16 or v32i8 to v8f32.
4153 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4154 EVT SrcVT = SV->getValueType(0);
4155 SDValue V1 = SV->getOperand(0);
4156 DebugLoc dl = SV->getDebugLoc();
4158 int EltNo = SV->getSplatIndex();
4159 int NumElems = SrcVT.getVectorNumElements();
4160 unsigned Size = SrcVT.getSizeInBits();
4162 // Extract the 128-bit part containing the splat element and update
4163 // the splat element index when it refers to the higher register.
4165 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4166 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4168 EltNo -= NumElems/2;
4171 // Make this 128-bit vector duplicate i8 and i16 elements
4172 EVT EltVT = SrcVT.getVectorElementType();
4173 if (NumElems > 4 && (EltVT == MVT::i8 || EltVT == MVT::i16))
4174 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4176 // Recreate the 256-bit vector and place the same 128-bit vector
4177 // into the low and high part. This is necessary because we want
4178 // to use VPERM to shuffle the v8f32 vector, and VPERM only shuffles
4179 // inside each separate v4f32 lane.
4181 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4182 DAG.getConstant(0, MVT::i32), DAG, dl);
4183 V1 = Insert128BitVector(InsV, V1,
4184 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4187 return getLegalSplat(DAG, V1, EltNo);
4190 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4191 /// vector of zero or undef vector. This produces a shuffle where the low
4192 /// element of V2 is swizzled into the zero/undef vector, landing at element
4193 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4194 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4195 bool isZero, bool HasSSE2,
4196 SelectionDAG &DAG) {
4197 EVT VT = V2.getValueType();
4199 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4200 unsigned NumElems = VT.getVectorNumElements();
4201 SmallVector<int, 16> MaskVec;
4202 for (unsigned i = 0; i != NumElems; ++i)
4203 // If this is the insertion idx, put the low elt of V2 here.
4204 MaskVec.push_back(i == Idx ? NumElems : i);
4205 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4208 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4209 /// element of the result of the vector shuffle.
4210 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4213 return SDValue(); // Limit search depth.
4215 SDValue V = SDValue(N, 0);
4216 EVT VT = V.getValueType();
4217 unsigned Opcode = V.getOpcode();
4219 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4220 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4221 Index = SV->getMaskElt(Index);
4224 return DAG.getUNDEF(VT.getVectorElementType());
4226 int NumElems = VT.getVectorNumElements();
4227 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4228 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4231 // Recurse into target specific vector shuffles to find scalars.
4232 if (isTargetShuffle(Opcode)) {
4233 int NumElems = VT.getVectorNumElements();
4234 SmallVector<unsigned, 16> ShuffleMask;
4238 case X86ISD::SHUFPS:
4239 case X86ISD::SHUFPD:
4240 ImmN = N->getOperand(N->getNumOperands()-1);
4241 DecodeSHUFPSMask(NumElems,
4242 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4245 case X86ISD::PUNPCKHBW:
4246 case X86ISD::PUNPCKHWD:
4247 case X86ISD::PUNPCKHDQ:
4248 case X86ISD::PUNPCKHQDQ:
4249 DecodePUNPCKHMask(NumElems, ShuffleMask);
4251 case X86ISD::UNPCKHPS:
4252 case X86ISD::UNPCKHPD:
4253 case X86ISD::VUNPCKHPSY:
4254 case X86ISD::VUNPCKHPDY:
4255 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4257 case X86ISD::PUNPCKLBW:
4258 case X86ISD::PUNPCKLWD:
4259 case X86ISD::PUNPCKLDQ:
4260 case X86ISD::PUNPCKLQDQ:
4261 DecodePUNPCKLMask(VT, ShuffleMask);
4263 case X86ISD::UNPCKLPS:
4264 case X86ISD::UNPCKLPD:
4265 case X86ISD::VUNPCKLPSY:
4266 case X86ISD::VUNPCKLPDY:
4267 DecodeUNPCKLPMask(VT, ShuffleMask);
4269 case X86ISD::MOVHLPS:
4270 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4272 case X86ISD::MOVLHPS:
4273 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4275 case X86ISD::PSHUFD:
4276 ImmN = N->getOperand(N->getNumOperands()-1);
4277 DecodePSHUFMask(NumElems,
4278 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4281 case X86ISD::PSHUFHW:
4282 ImmN = N->getOperand(N->getNumOperands()-1);
4283 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4286 case X86ISD::PSHUFLW:
4287 ImmN = N->getOperand(N->getNumOperands()-1);
4288 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4292 case X86ISD::MOVSD: {
4293 // The index 0 always comes from the first element of the second source,
4294 // this is why MOVSS and MOVSD are used in the first place. The other
4295 // elements come from the other positions of the first source vector.
4296 unsigned OpNum = (Index == 0) ? 1 : 0;
4297 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4300 case X86ISD::VPERMILPS:
4301 ImmN = N->getOperand(N->getNumOperands()-1);
4302 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4305 case X86ISD::VPERMILPSY:
4306 ImmN = N->getOperand(N->getNumOperands()-1);
4307 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4310 case X86ISD::VPERMILPD:
4311 ImmN = N->getOperand(N->getNumOperands()-1);
4312 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4315 case X86ISD::VPERMILPDY:
4316 ImmN = N->getOperand(N->getNumOperands()-1);
4317 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4321 assert("not implemented for target shuffle node");
4325 Index = ShuffleMask[Index];
4327 return DAG.getUNDEF(VT.getVectorElementType());
4329 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4330 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4334 // Actual nodes that may contain scalar elements
4335 if (Opcode == ISD::BITCAST) {
4336 V = V.getOperand(0);
4337 EVT SrcVT = V.getValueType();
4338 unsigned NumElems = VT.getVectorNumElements();
4340 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4344 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4345 return (Index == 0) ? V.getOperand(0)
4346 : DAG.getUNDEF(VT.getVectorElementType());
4348 if (V.getOpcode() == ISD::BUILD_VECTOR)
4349 return V.getOperand(Index);
4354 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4355 /// shuffle operation which come from a consecutively from a zero. The
4356 /// search can start in two different directions, from left or right.
4358 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4359 bool ZerosFromLeft, SelectionDAG &DAG) {
4362 while (i < NumElems) {
4363 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4364 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4365 if (!(Elt.getNode() &&
4366 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4374 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4375 /// MaskE correspond consecutively to elements from one of the vector operands,
4376 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4378 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4379 int OpIdx, int NumElems, unsigned &OpNum) {
4380 bool SeenV1 = false;
4381 bool SeenV2 = false;
4383 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4384 int Idx = SVOp->getMaskElt(i);
4385 // Ignore undef indicies
4394 // Only accept consecutive elements from the same vector
4395 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4399 OpNum = SeenV1 ? 0 : 1;
4403 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4404 /// logical left shift of a vector.
4405 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4406 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4407 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4408 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4409 false /* check zeros from right */, DAG);
4415 // Considering the elements in the mask that are not consecutive zeros,
4416 // check if they consecutively come from only one of the source vectors.
4418 // V1 = {X, A, B, C} 0
4420 // vector_shuffle V1, V2 <1, 2, 3, X>
4422 if (!isShuffleMaskConsecutive(SVOp,
4423 0, // Mask Start Index
4424 NumElems-NumZeros-1, // Mask End Index
4425 NumZeros, // Where to start looking in the src vector
4426 NumElems, // Number of elements in vector
4427 OpSrc)) // Which source operand ?
4432 ShVal = SVOp->getOperand(OpSrc);
4436 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4437 /// logical left shift of a vector.
4438 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4439 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4440 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4441 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4442 true /* check zeros from left */, DAG);
4448 // Considering the elements in the mask that are not consecutive zeros,
4449 // check if they consecutively come from only one of the source vectors.
4451 // 0 { A, B, X, X } = V2
4453 // vector_shuffle V1, V2 <X, X, 4, 5>
4455 if (!isShuffleMaskConsecutive(SVOp,
4456 NumZeros, // Mask Start Index
4457 NumElems-1, // Mask End Index
4458 0, // Where to start looking in the src vector
4459 NumElems, // Number of elements in vector
4460 OpSrc)) // Which source operand ?
4465 ShVal = SVOp->getOperand(OpSrc);
4469 /// isVectorShift - Returns true if the shuffle can be implemented as a
4470 /// logical left or right shift of a vector.
4471 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4472 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4473 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4474 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4480 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4482 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4483 unsigned NumNonZero, unsigned NumZero,
4485 const TargetLowering &TLI) {
4489 DebugLoc dl = Op.getDebugLoc();
4492 for (unsigned i = 0; i < 16; ++i) {
4493 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4494 if (ThisIsNonZero && First) {
4496 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4498 V = DAG.getUNDEF(MVT::v8i16);
4503 SDValue ThisElt(0, 0), LastElt(0, 0);
4504 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4505 if (LastIsNonZero) {
4506 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4507 MVT::i16, Op.getOperand(i-1));
4509 if (ThisIsNonZero) {
4510 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4511 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4512 ThisElt, DAG.getConstant(8, MVT::i8));
4514 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4518 if (ThisElt.getNode())
4519 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4520 DAG.getIntPtrConstant(i/2));
4524 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4527 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4529 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4530 unsigned NumNonZero, unsigned NumZero,
4532 const TargetLowering &TLI) {
4536 DebugLoc dl = Op.getDebugLoc();
4539 for (unsigned i = 0; i < 8; ++i) {
4540 bool isNonZero = (NonZeros & (1 << i)) != 0;
4544 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4546 V = DAG.getUNDEF(MVT::v8i16);
4549 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4550 MVT::v8i16, V, Op.getOperand(i),
4551 DAG.getIntPtrConstant(i));
4558 /// getVShift - Return a vector logical shift node.
4560 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4561 unsigned NumBits, SelectionDAG &DAG,
4562 const TargetLowering &TLI, DebugLoc dl) {
4563 EVT ShVT = MVT::v2i64;
4564 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4565 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4566 return DAG.getNode(ISD::BITCAST, dl, VT,
4567 DAG.getNode(Opc, dl, ShVT, SrcOp,
4568 DAG.getConstant(NumBits,
4569 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4573 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4574 SelectionDAG &DAG) const {
4576 // Check if the scalar load can be widened into a vector load. And if
4577 // the address is "base + cst" see if the cst can be "absorbed" into
4578 // the shuffle mask.
4579 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4580 SDValue Ptr = LD->getBasePtr();
4581 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4583 EVT PVT = LD->getValueType(0);
4584 if (PVT != MVT::i32 && PVT != MVT::f32)
4589 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4590 FI = FINode->getIndex();
4592 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4593 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4594 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4595 Offset = Ptr.getConstantOperandVal(1);
4596 Ptr = Ptr.getOperand(0);
4601 // FIXME: 256-bit vector instructions don't require a strict alignment,
4602 // improve this code to support it better.
4603 unsigned RequiredAlign = VT.getSizeInBits()/8;
4604 SDValue Chain = LD->getChain();
4605 // Make sure the stack object alignment is at least 16 or 32.
4606 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4607 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4608 if (MFI->isFixedObjectIndex(FI)) {
4609 // Can't change the alignment. FIXME: It's possible to compute
4610 // the exact stack offset and reference FI + adjust offset instead.
4611 // If someone *really* cares about this. That's the way to implement it.
4614 MFI->setObjectAlignment(FI, RequiredAlign);
4618 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4619 // Ptr + (Offset & ~15).
4622 if ((Offset % RequiredAlign) & 3)
4624 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4626 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4627 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4629 int EltNo = (Offset - StartOffset) >> 2;
4630 int NumElems = VT.getVectorNumElements();
4632 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4633 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4634 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4635 LD->getPointerInfo().getWithOffset(StartOffset),
4638 // Canonicalize it to a v4i32 or v8i32 shuffle.
4639 SmallVector<int, 8> Mask;
4640 for (int i = 0; i < NumElems; ++i)
4641 Mask.push_back(EltNo);
4643 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4644 return DAG.getNode(ISD::BITCAST, dl, NVT,
4645 DAG.getVectorShuffle(CanonVT, dl, V1,
4646 DAG.getUNDEF(CanonVT),&Mask[0]));
4652 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4653 /// vector of type 'VT', see if the elements can be replaced by a single large
4654 /// load which has the same value as a build_vector whose operands are 'elts'.
4656 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4658 /// FIXME: we'd also like to handle the case where the last elements are zero
4659 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4660 /// There's even a handy isZeroNode for that purpose.
4661 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4662 DebugLoc &DL, SelectionDAG &DAG) {
4663 EVT EltVT = VT.getVectorElementType();
4664 unsigned NumElems = Elts.size();
4666 LoadSDNode *LDBase = NULL;
4667 unsigned LastLoadedElt = -1U;
4669 // For each element in the initializer, see if we've found a load or an undef.
4670 // If we don't find an initial load element, or later load elements are
4671 // non-consecutive, bail out.
4672 for (unsigned i = 0; i < NumElems; ++i) {
4673 SDValue Elt = Elts[i];
4675 if (!Elt.getNode() ||
4676 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4679 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4681 LDBase = cast<LoadSDNode>(Elt.getNode());
4685 if (Elt.getOpcode() == ISD::UNDEF)
4688 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4689 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4694 // If we have found an entire vector of loads and undefs, then return a large
4695 // load of the entire vector width starting at the base pointer. If we found
4696 // consecutive loads for the low half, generate a vzext_load node.
4697 if (LastLoadedElt == NumElems - 1) {
4698 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4699 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4700 LDBase->getPointerInfo(),
4701 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4702 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4703 LDBase->getPointerInfo(),
4704 LDBase->isVolatile(), LDBase->isNonTemporal(),
4705 LDBase->getAlignment());
4706 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4707 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4708 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4709 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4710 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4712 LDBase->getMemOperand());
4713 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4719 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4720 DebugLoc dl = Op.getDebugLoc();
4722 EVT VT = Op.getValueType();
4723 EVT ExtVT = VT.getVectorElementType();
4724 unsigned NumElems = Op.getNumOperands();
4726 // Vectors containing all zeros can be matched by pxor and xorps later
4727 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4728 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4729 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4730 if (Op.getValueType() == MVT::v4i32 ||
4731 Op.getValueType() == MVT::v8i32)
4734 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4737 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4738 // vectors or broken into v4i32 operations on 256-bit vectors.
4739 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4740 if (Op.getValueType() == MVT::v4i32)
4743 return getOnesVector(Op.getValueType(), DAG, dl);
4746 unsigned EVTBits = ExtVT.getSizeInBits();
4748 unsigned NumZero = 0;
4749 unsigned NumNonZero = 0;
4750 unsigned NonZeros = 0;
4751 bool IsAllConstants = true;
4752 SmallSet<SDValue, 8> Values;
4753 for (unsigned i = 0; i < NumElems; ++i) {
4754 SDValue Elt = Op.getOperand(i);
4755 if (Elt.getOpcode() == ISD::UNDEF)
4758 if (Elt.getOpcode() != ISD::Constant &&
4759 Elt.getOpcode() != ISD::ConstantFP)
4760 IsAllConstants = false;
4761 if (X86::isZeroNode(Elt))
4764 NonZeros |= (1 << i);
4769 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4770 if (NumNonZero == 0)
4771 return DAG.getUNDEF(VT);
4773 // Special case for single non-zero, non-undef, element.
4774 if (NumNonZero == 1) {
4775 unsigned Idx = CountTrailingZeros_32(NonZeros);
4776 SDValue Item = Op.getOperand(Idx);
4778 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4779 // the value are obviously zero, truncate the value to i32 and do the
4780 // insertion that way. Only do this if the value is non-constant or if the
4781 // value is a constant being inserted into element 0. It is cheaper to do
4782 // a constant pool load than it is to do a movd + shuffle.
4783 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4784 (!IsAllConstants || Idx == 0)) {
4785 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4787 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4788 EVT VecVT = MVT::v4i32;
4789 unsigned VecElts = 4;
4791 // Truncate the value (which may itself be a constant) to i32, and
4792 // convert it to a vector with movd (S2V+shuffle to zero extend).
4793 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4794 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4795 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4796 Subtarget->hasSSE2(), DAG);
4798 // Now we have our 32-bit value zero extended in the low element of
4799 // a vector. If Idx != 0, swizzle it into place.
4801 SmallVector<int, 4> Mask;
4802 Mask.push_back(Idx);
4803 for (unsigned i = 1; i != VecElts; ++i)
4805 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4806 DAG.getUNDEF(Item.getValueType()),
4809 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4813 // If we have a constant or non-constant insertion into the low element of
4814 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4815 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4816 // depending on what the source datatype is.
4819 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4820 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4821 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4822 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4823 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4824 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4826 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4827 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4828 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4829 EVT MiddleVT = MVT::v4i32;
4830 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4831 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4832 Subtarget->hasSSE2(), DAG);
4833 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4837 // Is it a vector logical left shift?
4838 if (NumElems == 2 && Idx == 1 &&
4839 X86::isZeroNode(Op.getOperand(0)) &&
4840 !X86::isZeroNode(Op.getOperand(1))) {
4841 unsigned NumBits = VT.getSizeInBits();
4842 return getVShift(true, VT,
4843 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4844 VT, Op.getOperand(1)),
4845 NumBits/2, DAG, *this, dl);
4848 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4851 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4852 // is a non-constant being inserted into an element other than the low one,
4853 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4854 // movd/movss) to move this into the low element, then shuffle it into
4856 if (EVTBits == 32) {
4857 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4859 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4860 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4861 Subtarget->hasSSE2(), DAG);
4862 SmallVector<int, 8> MaskVec;
4863 for (unsigned i = 0; i < NumElems; i++)
4864 MaskVec.push_back(i == Idx ? 0 : 1);
4865 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4869 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4870 if (Values.size() == 1) {
4871 if (EVTBits == 32) {
4872 // Instead of a shuffle like this:
4873 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4874 // Check if it's possible to issue this instead.
4875 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4876 unsigned Idx = CountTrailingZeros_32(NonZeros);
4877 SDValue Item = Op.getOperand(Idx);
4878 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4879 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4884 // A vector full of immediates; various special cases are already
4885 // handled, so this is best done with a single constant-pool load.
4889 // For AVX-length vectors, build the individual 128-bit pieces and use
4890 // shuffles to put them in place.
4891 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
4892 SmallVector<SDValue, 32> V;
4893 for (unsigned i = 0; i < NumElems; ++i)
4894 V.push_back(Op.getOperand(i));
4896 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
4898 // Build both the lower and upper subvector.
4899 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
4900 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
4903 // Recreate the wider vector with the lower and upper part.
4904 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
4905 DAG.getConstant(0, MVT::i32), DAG, dl);
4906 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
4910 // Let legalizer expand 2-wide build_vectors.
4911 if (EVTBits == 64) {
4912 if (NumNonZero == 1) {
4913 // One half is zero or undef.
4914 unsigned Idx = CountTrailingZeros_32(NonZeros);
4915 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4916 Op.getOperand(Idx));
4917 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4918 Subtarget->hasSSE2(), DAG);
4923 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4924 if (EVTBits == 8 && NumElems == 16) {
4925 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4927 if (V.getNode()) return V;
4930 if (EVTBits == 16 && NumElems == 8) {
4931 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4933 if (V.getNode()) return V;
4936 // If element VT is == 32 bits, turn it into a number of shuffles.
4937 SmallVector<SDValue, 8> V;
4939 if (NumElems == 4 && NumZero > 0) {
4940 for (unsigned i = 0; i < 4; ++i) {
4941 bool isZero = !(NonZeros & (1 << i));
4943 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4945 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4948 for (unsigned i = 0; i < 2; ++i) {
4949 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4952 V[i] = V[i*2]; // Must be a zero vector.
4955 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4958 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4961 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4966 SmallVector<int, 8> MaskVec;
4967 bool Reverse = (NonZeros & 0x3) == 2;
4968 for (unsigned i = 0; i < 2; ++i)
4969 MaskVec.push_back(Reverse ? 1-i : i);
4970 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4971 for (unsigned i = 0; i < 2; ++i)
4972 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4973 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4976 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4977 // Check for a build vector of consecutive loads.
4978 for (unsigned i = 0; i < NumElems; ++i)
4979 V[i] = Op.getOperand(i);
4981 // Check for elements which are consecutive loads.
4982 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4986 // For SSE 4.1, use insertps to put the high elements into the low element.
4987 if (getSubtarget()->hasSSE41()) {
4989 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4990 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4992 Result = DAG.getUNDEF(VT);
4994 for (unsigned i = 1; i < NumElems; ++i) {
4995 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4996 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4997 Op.getOperand(i), DAG.getIntPtrConstant(i));
5002 // Otherwise, expand into a number of unpckl*, start by extending each of
5003 // our (non-undef) elements to the full vector width with the element in the
5004 // bottom slot of the vector (which generates no code for SSE).
5005 for (unsigned i = 0; i < NumElems; ++i) {
5006 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5007 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5009 V[i] = DAG.getUNDEF(VT);
5012 // Next, we iteratively mix elements, e.g. for v4f32:
5013 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5014 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5015 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5016 unsigned EltStride = NumElems >> 1;
5017 while (EltStride != 0) {
5018 for (unsigned i = 0; i < EltStride; ++i) {
5019 // If V[i+EltStride] is undef and this is the first round of mixing,
5020 // then it is safe to just drop this shuffle: V[i] is already in the
5021 // right place, the one element (since it's the first round) being
5022 // inserted as undef can be dropped. This isn't safe for successive
5023 // rounds because they will permute elements within both vectors.
5024 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5025 EltStride == NumElems/2)
5028 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5037 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5038 // them in a MMX register. This is better than doing a stack convert.
5039 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5040 DebugLoc dl = Op.getDebugLoc();
5041 EVT ResVT = Op.getValueType();
5043 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5044 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5046 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5047 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5048 InVec = Op.getOperand(1);
5049 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5050 unsigned NumElts = ResVT.getVectorNumElements();
5051 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5052 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5053 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5055 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5056 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5057 Mask[0] = 0; Mask[1] = 2;
5058 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5060 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5063 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5064 // to create 256-bit vectors from two other 128-bit ones.
5065 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5066 DebugLoc dl = Op.getDebugLoc();
5067 EVT ResVT = Op.getValueType();
5069 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5071 SDValue V1 = Op.getOperand(0);
5072 SDValue V2 = Op.getOperand(1);
5073 unsigned NumElems = ResVT.getVectorNumElements();
5075 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5076 DAG.getConstant(0, MVT::i32), DAG, dl);
5077 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5082 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5083 EVT ResVT = Op.getValueType();
5085 assert(Op.getNumOperands() == 2);
5086 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5087 "Unsupported CONCAT_VECTORS for value type");
5089 // We support concatenate two MMX registers and place them in a MMX register.
5090 // This is better than doing a stack convert.
5091 if (ResVT.is128BitVector())
5092 return LowerMMXCONCAT_VECTORS(Op, DAG);
5094 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5095 // from two other 128-bit ones.
5096 return LowerAVXCONCAT_VECTORS(Op, DAG);
5099 // v8i16 shuffles - Prefer shuffles in the following order:
5100 // 1. [all] pshuflw, pshufhw, optional move
5101 // 2. [ssse3] 1 x pshufb
5102 // 3. [ssse3] 2 x pshufb + 1 x por
5103 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5105 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5106 SelectionDAG &DAG) const {
5107 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5108 SDValue V1 = SVOp->getOperand(0);
5109 SDValue V2 = SVOp->getOperand(1);
5110 DebugLoc dl = SVOp->getDebugLoc();
5111 SmallVector<int, 8> MaskVals;
5113 // Determine if more than 1 of the words in each of the low and high quadwords
5114 // of the result come from the same quadword of one of the two inputs. Undef
5115 // mask values count as coming from any quadword, for better codegen.
5116 SmallVector<unsigned, 4> LoQuad(4);
5117 SmallVector<unsigned, 4> HiQuad(4);
5118 BitVector InputQuads(4);
5119 for (unsigned i = 0; i < 8; ++i) {
5120 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5121 int EltIdx = SVOp->getMaskElt(i);
5122 MaskVals.push_back(EltIdx);
5131 InputQuads.set(EltIdx / 4);
5134 int BestLoQuad = -1;
5135 unsigned MaxQuad = 1;
5136 for (unsigned i = 0; i < 4; ++i) {
5137 if (LoQuad[i] > MaxQuad) {
5139 MaxQuad = LoQuad[i];
5143 int BestHiQuad = -1;
5145 for (unsigned i = 0; i < 4; ++i) {
5146 if (HiQuad[i] > MaxQuad) {
5148 MaxQuad = HiQuad[i];
5152 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5153 // of the two input vectors, shuffle them into one input vector so only a
5154 // single pshufb instruction is necessary. If There are more than 2 input
5155 // quads, disable the next transformation since it does not help SSSE3.
5156 bool V1Used = InputQuads[0] || InputQuads[1];
5157 bool V2Used = InputQuads[2] || InputQuads[3];
5158 if (Subtarget->hasSSSE3()) {
5159 if (InputQuads.count() == 2 && V1Used && V2Used) {
5160 BestLoQuad = InputQuads.find_first();
5161 BestHiQuad = InputQuads.find_next(BestLoQuad);
5163 if (InputQuads.count() > 2) {
5169 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5170 // the shuffle mask. If a quad is scored as -1, that means that it contains
5171 // words from all 4 input quadwords.
5173 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5174 SmallVector<int, 8> MaskV;
5175 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5176 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5177 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5178 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5179 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5180 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5182 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5183 // source words for the shuffle, to aid later transformations.
5184 bool AllWordsInNewV = true;
5185 bool InOrder[2] = { true, true };
5186 for (unsigned i = 0; i != 8; ++i) {
5187 int idx = MaskVals[i];
5189 InOrder[i/4] = false;
5190 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5192 AllWordsInNewV = false;
5196 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5197 if (AllWordsInNewV) {
5198 for (int i = 0; i != 8; ++i) {
5199 int idx = MaskVals[i];
5202 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5203 if ((idx != i) && idx < 4)
5205 if ((idx != i) && idx > 3)
5214 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5215 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5216 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5217 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5218 unsigned TargetMask = 0;
5219 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5220 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5221 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5222 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5223 V1 = NewV.getOperand(0);
5224 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5228 // If we have SSSE3, and all words of the result are from 1 input vector,
5229 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5230 // is present, fall back to case 4.
5231 if (Subtarget->hasSSSE3()) {
5232 SmallVector<SDValue,16> pshufbMask;
5234 // If we have elements from both input vectors, set the high bit of the
5235 // shuffle mask element to zero out elements that come from V2 in the V1
5236 // mask, and elements that come from V1 in the V2 mask, so that the two
5237 // results can be OR'd together.
5238 bool TwoInputs = V1Used && V2Used;
5239 for (unsigned i = 0; i != 8; ++i) {
5240 int EltIdx = MaskVals[i] * 2;
5241 if (TwoInputs && (EltIdx >= 16)) {
5242 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5243 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5246 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5247 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5249 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5250 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5251 DAG.getNode(ISD::BUILD_VECTOR, dl,
5252 MVT::v16i8, &pshufbMask[0], 16));
5254 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5256 // Calculate the shuffle mask for the second input, shuffle it, and
5257 // OR it with the first shuffled input.
5259 for (unsigned i = 0; i != 8; ++i) {
5260 int EltIdx = MaskVals[i] * 2;
5262 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5263 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5266 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5267 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5269 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5270 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5271 DAG.getNode(ISD::BUILD_VECTOR, dl,
5272 MVT::v16i8, &pshufbMask[0], 16));
5273 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5274 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5277 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5278 // and update MaskVals with new element order.
5279 BitVector InOrder(8);
5280 if (BestLoQuad >= 0) {
5281 SmallVector<int, 8> MaskV;
5282 for (int i = 0; i != 4; ++i) {
5283 int idx = MaskVals[i];
5285 MaskV.push_back(-1);
5287 } else if ((idx / 4) == BestLoQuad) {
5288 MaskV.push_back(idx & 3);
5291 MaskV.push_back(-1);
5294 for (unsigned i = 4; i != 8; ++i)
5296 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5299 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5300 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5302 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5306 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5307 // and update MaskVals with the new element order.
5308 if (BestHiQuad >= 0) {
5309 SmallVector<int, 8> MaskV;
5310 for (unsigned i = 0; i != 4; ++i)
5312 for (unsigned i = 4; i != 8; ++i) {
5313 int idx = MaskVals[i];
5315 MaskV.push_back(-1);
5317 } else if ((idx / 4) == BestHiQuad) {
5318 MaskV.push_back((idx & 3) + 4);
5321 MaskV.push_back(-1);
5324 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5327 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5328 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5330 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5334 // In case BestHi & BestLo were both -1, which means each quadword has a word
5335 // from each of the four input quadwords, calculate the InOrder bitvector now
5336 // before falling through to the insert/extract cleanup.
5337 if (BestLoQuad == -1 && BestHiQuad == -1) {
5339 for (int i = 0; i != 8; ++i)
5340 if (MaskVals[i] < 0 || MaskVals[i] == i)
5344 // The other elements are put in the right place using pextrw and pinsrw.
5345 for (unsigned i = 0; i != 8; ++i) {
5348 int EltIdx = MaskVals[i];
5351 SDValue ExtOp = (EltIdx < 8)
5352 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5353 DAG.getIntPtrConstant(EltIdx))
5354 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5355 DAG.getIntPtrConstant(EltIdx - 8));
5356 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5357 DAG.getIntPtrConstant(i));
5362 // v16i8 shuffles - Prefer shuffles in the following order:
5363 // 1. [ssse3] 1 x pshufb
5364 // 2. [ssse3] 2 x pshufb + 1 x por
5365 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5367 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5369 const X86TargetLowering &TLI) {
5370 SDValue V1 = SVOp->getOperand(0);
5371 SDValue V2 = SVOp->getOperand(1);
5372 DebugLoc dl = SVOp->getDebugLoc();
5373 SmallVector<int, 16> MaskVals;
5374 SVOp->getMask(MaskVals);
5376 // If we have SSSE3, case 1 is generated when all result bytes come from
5377 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5378 // present, fall back to case 3.
5379 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5382 for (unsigned i = 0; i < 16; ++i) {
5383 int EltIdx = MaskVals[i];
5392 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5393 if (TLI.getSubtarget()->hasSSSE3()) {
5394 SmallVector<SDValue,16> pshufbMask;
5396 // If all result elements are from one input vector, then only translate
5397 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5399 // Otherwise, we have elements from both input vectors, and must zero out
5400 // elements that come from V2 in the first mask, and V1 in the second mask
5401 // so that we can OR them together.
5402 bool TwoInputs = !(V1Only || V2Only);
5403 for (unsigned i = 0; i != 16; ++i) {
5404 int EltIdx = MaskVals[i];
5405 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5406 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5409 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5411 // If all the elements are from V2, assign it to V1 and return after
5412 // building the first pshufb.
5415 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5416 DAG.getNode(ISD::BUILD_VECTOR, dl,
5417 MVT::v16i8, &pshufbMask[0], 16));
5421 // Calculate the shuffle mask for the second input, shuffle it, and
5422 // OR it with the first shuffled input.
5424 for (unsigned i = 0; i != 16; ++i) {
5425 int EltIdx = MaskVals[i];
5427 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5430 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5432 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5433 DAG.getNode(ISD::BUILD_VECTOR, dl,
5434 MVT::v16i8, &pshufbMask[0], 16));
5435 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5438 // No SSSE3 - Calculate in place words and then fix all out of place words
5439 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5440 // the 16 different words that comprise the two doublequadword input vectors.
5441 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5442 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5443 SDValue NewV = V2Only ? V2 : V1;
5444 for (int i = 0; i != 8; ++i) {
5445 int Elt0 = MaskVals[i*2];
5446 int Elt1 = MaskVals[i*2+1];
5448 // This word of the result is all undef, skip it.
5449 if (Elt0 < 0 && Elt1 < 0)
5452 // This word of the result is already in the correct place, skip it.
5453 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5455 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5458 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5459 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5462 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5463 // using a single extract together, load it and store it.
5464 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5465 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5466 DAG.getIntPtrConstant(Elt1 / 2));
5467 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5468 DAG.getIntPtrConstant(i));
5472 // If Elt1 is defined, extract it from the appropriate source. If the
5473 // source byte is not also odd, shift the extracted word left 8 bits
5474 // otherwise clear the bottom 8 bits if we need to do an or.
5476 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5477 DAG.getIntPtrConstant(Elt1 / 2));
5478 if ((Elt1 & 1) == 0)
5479 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5481 TLI.getShiftAmountTy(InsElt.getValueType())));
5483 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5484 DAG.getConstant(0xFF00, MVT::i16));
5486 // If Elt0 is defined, extract it from the appropriate source. If the
5487 // source byte is not also even, shift the extracted word right 8 bits. If
5488 // Elt1 was also defined, OR the extracted values together before
5489 // inserting them in the result.
5491 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5492 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5493 if ((Elt0 & 1) != 0)
5494 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5496 TLI.getShiftAmountTy(InsElt0.getValueType())));
5498 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5499 DAG.getConstant(0x00FF, MVT::i16));
5500 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5503 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5504 DAG.getIntPtrConstant(i));
5506 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5509 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5510 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5511 /// done when every pair / quad of shuffle mask elements point to elements in
5512 /// the right sequence. e.g.
5513 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5515 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5516 SelectionDAG &DAG, DebugLoc dl) {
5517 EVT VT = SVOp->getValueType(0);
5518 SDValue V1 = SVOp->getOperand(0);
5519 SDValue V2 = SVOp->getOperand(1);
5520 unsigned NumElems = VT.getVectorNumElements();
5521 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5523 switch (VT.getSimpleVT().SimpleTy) {
5524 default: assert(false && "Unexpected!");
5525 case MVT::v4f32: NewVT = MVT::v2f64; break;
5526 case MVT::v4i32: NewVT = MVT::v2i64; break;
5527 case MVT::v8i16: NewVT = MVT::v4i32; break;
5528 case MVT::v16i8: NewVT = MVT::v4i32; break;
5531 int Scale = NumElems / NewWidth;
5532 SmallVector<int, 8> MaskVec;
5533 for (unsigned i = 0; i < NumElems; i += Scale) {
5535 for (int j = 0; j < Scale; ++j) {
5536 int EltIdx = SVOp->getMaskElt(i+j);
5540 StartIdx = EltIdx - (EltIdx % Scale);
5541 if (EltIdx != StartIdx + j)
5545 MaskVec.push_back(-1);
5547 MaskVec.push_back(StartIdx / Scale);
5550 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5551 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5552 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5555 /// getVZextMovL - Return a zero-extending vector move low node.
5557 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5558 SDValue SrcOp, SelectionDAG &DAG,
5559 const X86Subtarget *Subtarget, DebugLoc dl) {
5560 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5561 LoadSDNode *LD = NULL;
5562 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5563 LD = dyn_cast<LoadSDNode>(SrcOp);
5565 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5567 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5568 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5569 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5570 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5571 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5573 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5574 return DAG.getNode(ISD::BITCAST, dl, VT,
5575 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5576 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5584 return DAG.getNode(ISD::BITCAST, dl, VT,
5585 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5586 DAG.getNode(ISD::BITCAST, dl,
5590 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5591 /// which could not be matched by any known target speficic shuffle
5593 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5597 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5598 /// 4 elements, and match them with several different shuffle types.
5600 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5601 SDValue V1 = SVOp->getOperand(0);
5602 SDValue V2 = SVOp->getOperand(1);
5603 DebugLoc dl = SVOp->getDebugLoc();
5604 EVT VT = SVOp->getValueType(0);
5606 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5608 SmallVector<std::pair<int, int>, 8> Locs;
5610 SmallVector<int, 8> Mask1(4U, -1);
5611 SmallVector<int, 8> PermMask;
5612 SVOp->getMask(PermMask);
5616 for (unsigned i = 0; i != 4; ++i) {
5617 int Idx = PermMask[i];
5619 Locs[i] = std::make_pair(-1, -1);
5621 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5623 Locs[i] = std::make_pair(0, NumLo);
5627 Locs[i] = std::make_pair(1, NumHi);
5629 Mask1[2+NumHi] = Idx;
5635 if (NumLo <= 2 && NumHi <= 2) {
5636 // If no more than two elements come from either vector. This can be
5637 // implemented with two shuffles. First shuffle gather the elements.
5638 // The second shuffle, which takes the first shuffle as both of its
5639 // vector operands, put the elements into the right order.
5640 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5642 SmallVector<int, 8> Mask2(4U, -1);
5644 for (unsigned i = 0; i != 4; ++i) {
5645 if (Locs[i].first == -1)
5648 unsigned Idx = (i < 2) ? 0 : 4;
5649 Idx += Locs[i].first * 2 + Locs[i].second;
5654 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5655 } else if (NumLo == 3 || NumHi == 3) {
5656 // Otherwise, we must have three elements from one vector, call it X, and
5657 // one element from the other, call it Y. First, use a shufps to build an
5658 // intermediate vector with the one element from Y and the element from X
5659 // that will be in the same half in the final destination (the indexes don't
5660 // matter). Then, use a shufps to build the final vector, taking the half
5661 // containing the element from Y from the intermediate, and the other half
5664 // Normalize it so the 3 elements come from V1.
5665 CommuteVectorShuffleMask(PermMask, VT);
5669 // Find the element from V2.
5671 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5672 int Val = PermMask[HiIndex];
5679 Mask1[0] = PermMask[HiIndex];
5681 Mask1[2] = PermMask[HiIndex^1];
5683 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5686 Mask1[0] = PermMask[0];
5687 Mask1[1] = PermMask[1];
5688 Mask1[2] = HiIndex & 1 ? 6 : 4;
5689 Mask1[3] = HiIndex & 1 ? 4 : 6;
5690 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5692 Mask1[0] = HiIndex & 1 ? 2 : 0;
5693 Mask1[1] = HiIndex & 1 ? 0 : 2;
5694 Mask1[2] = PermMask[2];
5695 Mask1[3] = PermMask[3];
5700 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5704 // Break it into (shuffle shuffle_hi, shuffle_lo).
5707 SmallVector<int,8> LoMask(4U, -1);
5708 SmallVector<int,8> HiMask(4U, -1);
5710 SmallVector<int,8> *MaskPtr = &LoMask;
5711 unsigned MaskIdx = 0;
5714 for (unsigned i = 0; i != 4; ++i) {
5721 int Idx = PermMask[i];
5723 Locs[i] = std::make_pair(-1, -1);
5724 } else if (Idx < 4) {
5725 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5726 (*MaskPtr)[LoIdx] = Idx;
5729 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5730 (*MaskPtr)[HiIdx] = Idx;
5735 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5736 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5737 SmallVector<int, 8> MaskOps;
5738 for (unsigned i = 0; i != 4; ++i) {
5739 if (Locs[i].first == -1) {
5740 MaskOps.push_back(-1);
5742 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5743 MaskOps.push_back(Idx);
5746 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5749 static bool MayFoldVectorLoad(SDValue V) {
5750 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5751 V = V.getOperand(0);
5752 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5753 V = V.getOperand(0);
5759 // FIXME: the version above should always be used. Since there's
5760 // a bug where several vector shuffles can't be folded because the
5761 // DAG is not updated during lowering and a node claims to have two
5762 // uses while it only has one, use this version, and let isel match
5763 // another instruction if the load really happens to have more than
5764 // one use. Remove this version after this bug get fixed.
5765 // rdar://8434668, PR8156
5766 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5767 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5768 V = V.getOperand(0);
5769 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5770 V = V.getOperand(0);
5771 if (ISD::isNormalLoad(V.getNode()))
5776 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5777 /// a vector extract, and if both can be later optimized into a single load.
5778 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5779 /// here because otherwise a target specific shuffle node is going to be
5780 /// emitted for this shuffle, and the optimization not done.
5781 /// FIXME: This is probably not the best approach, but fix the problem
5782 /// until the right path is decided.
5784 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5785 const TargetLowering &TLI) {
5786 EVT VT = V.getValueType();
5787 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5789 // Be sure that the vector shuffle is present in a pattern like this:
5790 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5794 SDNode *N = *V.getNode()->use_begin();
5795 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5798 SDValue EltNo = N->getOperand(1);
5799 if (!isa<ConstantSDNode>(EltNo))
5802 // If the bit convert changed the number of elements, it is unsafe
5803 // to examine the mask.
5804 bool HasShuffleIntoBitcast = false;
5805 if (V.getOpcode() == ISD::BITCAST) {
5806 EVT SrcVT = V.getOperand(0).getValueType();
5807 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5809 V = V.getOperand(0);
5810 HasShuffleIntoBitcast = true;
5813 // Select the input vector, guarding against out of range extract vector.
5814 unsigned NumElems = VT.getVectorNumElements();
5815 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5816 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5817 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5819 // Skip one more bit_convert if necessary
5820 if (V.getOpcode() == ISD::BITCAST)
5821 V = V.getOperand(0);
5823 if (ISD::isNormalLoad(V.getNode())) {
5824 // Is the original load suitable?
5825 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5827 // FIXME: avoid the multi-use bug that is preventing lots of
5828 // of foldings to be detected, this is still wrong of course, but
5829 // give the temporary desired behavior, and if it happens that
5830 // the load has real more uses, during isel it will not fold, and
5831 // will generate poor code.
5832 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5835 if (!HasShuffleIntoBitcast)
5838 // If there's a bitcast before the shuffle, check if the load type and
5839 // alignment is valid.
5840 unsigned Align = LN0->getAlignment();
5842 TLI.getTargetData()->getABITypeAlignment(
5843 VT.getTypeForEVT(*DAG.getContext()));
5845 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5853 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5854 EVT VT = Op.getValueType();
5856 // Canonizalize to v2f64.
5857 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
5858 return DAG.getNode(ISD::BITCAST, dl, VT,
5859 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5864 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5866 SDValue V1 = Op.getOperand(0);
5867 SDValue V2 = Op.getOperand(1);
5868 EVT VT = Op.getValueType();
5870 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5872 if (HasSSE2 && VT == MVT::v2f64)
5873 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5876 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5880 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5881 SDValue V1 = Op.getOperand(0);
5882 SDValue V2 = Op.getOperand(1);
5883 EVT VT = Op.getValueType();
5885 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5886 "unsupported shuffle type");
5888 if (V2.getOpcode() == ISD::UNDEF)
5892 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5896 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5897 SDValue V1 = Op.getOperand(0);
5898 SDValue V2 = Op.getOperand(1);
5899 EVT VT = Op.getValueType();
5900 unsigned NumElems = VT.getVectorNumElements();
5902 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5903 // operand of these instructions is only memory, so check if there's a
5904 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5906 bool CanFoldLoad = false;
5908 // Trivial case, when V2 comes from a load.
5909 if (MayFoldVectorLoad(V2))
5912 // When V1 is a load, it can be folded later into a store in isel, example:
5913 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5915 // (MOVLPSmr addr:$src1, VR128:$src2)
5916 // So, recognize this potential and also use MOVLPS or MOVLPD
5917 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5920 // Both of them can't be memory operations though.
5921 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
5922 CanFoldLoad = false;
5925 if (HasSSE2 && NumElems == 2)
5926 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5929 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5932 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5933 // movl and movlp will both match v2i64, but v2i64 is never matched by
5934 // movl earlier because we make it strict to avoid messing with the movlp load
5935 // folding logic (see the code above getMOVLP call). Match it here then,
5936 // this is horrible, but will stay like this until we move all shuffle
5937 // matching to x86 specific nodes. Note that for the 1st condition all
5938 // types are matched with movsd.
5939 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5940 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5942 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5945 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5947 // Invert the operand order and use SHUFPS to match it.
5948 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5949 X86::getShuffleSHUFImmediate(SVOp), DAG);
5952 static inline unsigned getUNPCKLOpcode(EVT VT) {
5953 switch(VT.getSimpleVT().SimpleTy) {
5954 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5955 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5956 case MVT::v4f32: return X86ISD::UNPCKLPS;
5957 case MVT::v2f64: return X86ISD::UNPCKLPD;
5958 case MVT::v8i32: // Use fp unit for int unpack.
5959 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
5960 case MVT::v4i64: // Use fp unit for int unpack.
5961 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
5962 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5963 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5965 llvm_unreachable("Unknown type for unpckl");
5970 static inline unsigned getUNPCKHOpcode(EVT VT) {
5971 switch(VT.getSimpleVT().SimpleTy) {
5972 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5973 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5974 case MVT::v4f32: return X86ISD::UNPCKHPS;
5975 case MVT::v2f64: return X86ISD::UNPCKHPD;
5976 case MVT::v8i32: // Use fp unit for int unpack.
5977 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
5978 case MVT::v4i64: // Use fp unit for int unpack.
5979 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
5980 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5981 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5983 llvm_unreachable("Unknown type for unpckh");
5988 static inline unsigned getVPERMILOpcode(EVT VT) {
5989 switch(VT.getSimpleVT().SimpleTy) {
5991 case MVT::v4f32: return X86ISD::VPERMILPS;
5993 case MVT::v2f64: return X86ISD::VPERMILPD;
5995 case MVT::v8f32: return X86ISD::VPERMILPSY;
5997 case MVT::v4f64: return X86ISD::VPERMILPDY;
5999 llvm_unreachable("Unknown type for vpermil");
6005 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6006 const TargetLowering &TLI,
6007 const X86Subtarget *Subtarget) {
6008 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6009 EVT VT = Op.getValueType();
6010 DebugLoc dl = Op.getDebugLoc();
6011 SDValue V1 = Op.getOperand(0);
6012 SDValue V2 = Op.getOperand(1);
6014 if (isZeroShuffle(SVOp))
6015 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6017 // Handle splat operations
6018 if (SVOp->isSplat()) {
6019 unsigned NumElem = VT.getVectorNumElements();
6020 // Special case, this is the only place now where it's allowed to return
6021 // a vector_shuffle operation without using a target specific node, because
6022 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6023 // this be moved to DAGCombine instead?
6024 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6027 // Since there's no native support for scalar_to_vector for 256-bit AVX, a
6028 // 128-bit scalar_to_vector + INSERT_SUBVECTOR is generated. Recognize this
6029 // idiom and do the shuffle before the insertion, this yields less
6030 // instructions in the end.
6031 if (VT.is256BitVector() &&
6032 V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
6033 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
6034 V1.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR)
6035 return PromoteVectorToScalarSplat(SVOp, DAG);
6037 // Handle splats by matching through known shuffle masks
6038 if (VT.is128BitVector() && NumElem <= 4)
6041 // All i16 and i8 vector types can't be used directly by a generic shuffle
6042 // instruction because the target has no such instruction. Generate shuffles
6043 // which repeat i16 and i8 several times until they fit in i32, and then can
6044 // be manipulated by target suported shuffles. After the insertion of the
6045 // necessary shuffles, the result is bitcasted back to v4f32 or v8f32.
6046 return PromoteSplat(SVOp, DAG);
6049 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6051 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6052 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6053 if (NewOp.getNode())
6054 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6055 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6056 // FIXME: Figure out a cleaner way to do this.
6057 // Try to make use of movq to zero out the top part.
6058 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6059 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6060 if (NewOp.getNode()) {
6061 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6062 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6063 DAG, Subtarget, dl);
6065 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6066 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6067 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6068 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6069 DAG, Subtarget, dl);
6076 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6077 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6078 SDValue V1 = Op.getOperand(0);
6079 SDValue V2 = Op.getOperand(1);
6080 EVT VT = Op.getValueType();
6081 DebugLoc dl = Op.getDebugLoc();
6082 unsigned NumElems = VT.getVectorNumElements();
6083 bool isMMX = VT.getSizeInBits() == 64;
6084 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6085 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6086 bool V1IsSplat = false;
6087 bool V2IsSplat = false;
6088 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6089 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6090 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6091 MachineFunction &MF = DAG.getMachineFunction();
6092 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6094 // Shuffle operations on MMX not supported.
6098 // Vector shuffle lowering takes 3 steps:
6100 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6101 // narrowing and commutation of operands should be handled.
6102 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6104 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6105 // so the shuffle can be broken into other shuffles and the legalizer can
6106 // try the lowering again.
6108 // The general ideia is that no vector_shuffle operation should be left to
6109 // be matched during isel, all of them must be converted to a target specific
6112 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6113 // narrowing and commutation of operands should be handled. The actual code
6114 // doesn't include all of those, work in progress...
6115 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6116 if (NewOp.getNode())
6119 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6120 // unpckh_undef). Only use pshufd if speed is more important than size.
6121 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6122 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6123 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6124 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6126 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6127 RelaxedMayFoldVectorLoad(V1))
6128 return getMOVDDup(Op, dl, V1, DAG);
6130 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6131 return getMOVHighToLow(Op, dl, DAG);
6133 // Use to match splats
6134 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6135 (VT == MVT::v2f64 || VT == MVT::v2i64))
6136 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6138 if (X86::isPSHUFDMask(SVOp)) {
6139 // The actual implementation will match the mask in the if above and then
6140 // during isel it can match several different instructions, not only pshufd
6141 // as its name says, sad but true, emulate the behavior for now...
6142 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6143 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6145 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6147 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6148 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6150 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6151 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
6154 if (VT == MVT::v4f32)
6155 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
6159 // Check if this can be converted into a logical shift.
6160 bool isLeft = false;
6163 bool isShift = getSubtarget()->hasSSE2() &&
6164 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6165 if (isShift && ShVal.hasOneUse()) {
6166 // If the shifted value has multiple uses, it may be cheaper to use
6167 // v_set0 + movlhps or movhlps, etc.
6168 EVT EltVT = VT.getVectorElementType();
6169 ShAmt *= EltVT.getSizeInBits();
6170 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6173 if (X86::isMOVLMask(SVOp)) {
6176 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6177 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6178 if (!X86::isMOVLPMask(SVOp)) {
6179 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6180 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6182 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6183 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6187 // FIXME: fold these into legal mask.
6188 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6189 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6191 if (X86::isMOVHLPSMask(SVOp))
6192 return getMOVHighToLow(Op, dl, DAG);
6194 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6195 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6197 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6198 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6200 if (X86::isMOVLPMask(SVOp))
6201 return getMOVLP(Op, dl, DAG, HasSSE2);
6203 if (ShouldXformToMOVHLPS(SVOp) ||
6204 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6205 return CommuteVectorShuffle(SVOp, DAG);
6208 // No better options. Use a vshl / vsrl.
6209 EVT EltVT = VT.getVectorElementType();
6210 ShAmt *= EltVT.getSizeInBits();
6211 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6214 bool Commuted = false;
6215 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6216 // 1,1,1,1 -> v8i16 though.
6217 V1IsSplat = isSplatVector(V1.getNode());
6218 V2IsSplat = isSplatVector(V2.getNode());
6220 // Canonicalize the splat or undef, if present, to be on the RHS.
6221 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6222 Op = CommuteVectorShuffle(SVOp, DAG);
6223 SVOp = cast<ShuffleVectorSDNode>(Op);
6224 V1 = SVOp->getOperand(0);
6225 V2 = SVOp->getOperand(1);
6226 std::swap(V1IsSplat, V2IsSplat);
6227 std::swap(V1IsUndef, V2IsUndef);
6231 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6232 // Shuffling low element of v1 into undef, just return v1.
6235 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6236 // the instruction selector will not match, so get a canonical MOVL with
6237 // swapped operands to undo the commute.
6238 return getMOVL(DAG, dl, VT, V2, V1);
6241 if (X86::isUNPCKLMask(SVOp))
6242 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6244 if (X86::isUNPCKHMask(SVOp))
6245 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6248 // Normalize mask so all entries that point to V2 points to its first
6249 // element then try to match unpck{h|l} again. If match, return a
6250 // new vector_shuffle with the corrected mask.
6251 SDValue NewMask = NormalizeMask(SVOp, DAG);
6252 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6253 if (NSVOp != SVOp) {
6254 if (X86::isUNPCKLMask(NSVOp, true)) {
6256 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6263 // Commute is back and try unpck* again.
6264 // FIXME: this seems wrong.
6265 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6266 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6268 if (X86::isUNPCKLMask(NewSVOp))
6269 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6271 if (X86::isUNPCKHMask(NewSVOp))
6272 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6275 // Normalize the node to match x86 shuffle ops if needed
6276 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6277 return CommuteVectorShuffle(SVOp, DAG);
6279 // The checks below are all present in isShuffleMaskLegal, but they are
6280 // inlined here right now to enable us to directly emit target specific
6281 // nodes, and remove one by one until they don't return Op anymore.
6282 SmallVector<int, 16> M;
6285 if (isPALIGNRMask(M, VT, HasSSSE3))
6286 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6287 X86::getShufflePALIGNRImmediate(SVOp),
6290 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6291 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6292 if (VT == MVT::v2f64)
6293 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6294 if (VT == MVT::v2i64)
6295 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6298 if (isPSHUFHWMask(M, VT))
6299 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6300 X86::getShufflePSHUFHWImmediate(SVOp),
6303 if (isPSHUFLWMask(M, VT))
6304 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6305 X86::getShufflePSHUFLWImmediate(SVOp),
6308 if (isSHUFPMask(M, VT)) {
6309 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6310 if (VT == MVT::v4f32 || VT == MVT::v4i32)
6311 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
6313 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6314 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
6318 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6319 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6320 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6321 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6323 //===--------------------------------------------------------------------===//
6324 // Generate target specific nodes for 128 or 256-bit shuffles only
6325 // supported in the AVX instruction set.
6328 // Handle VPERMILPS* permutations
6329 if (isVPERMILPSMask(M, VT, Subtarget))
6330 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6331 getShuffleVPERMILPSImmediate(SVOp), DAG);
6333 // Handle VPERMILPD* permutations
6334 if (isVPERMILPDMask(M, VT, Subtarget))
6335 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6336 getShuffleVPERMILPDImmediate(SVOp), DAG);
6338 //===--------------------------------------------------------------------===//
6339 // Since no target specific shuffle was selected for this generic one,
6340 // lower it into other known shuffles. FIXME: this isn't true yet, but
6341 // this is the plan.
6344 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6345 if (VT == MVT::v8i16) {
6346 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6347 if (NewOp.getNode())
6351 if (VT == MVT::v16i8) {
6352 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6353 if (NewOp.getNode())
6357 // Handle all 128-bit wide vectors with 4 elements, and match them with
6358 // several different shuffle types.
6359 if (NumElems == 4 && VT.getSizeInBits() == 128)
6360 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6362 // Handle general 256-bit shuffles
6363 if (VT.is256BitVector())
6364 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6370 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6371 SelectionDAG &DAG) const {
6372 EVT VT = Op.getValueType();
6373 DebugLoc dl = Op.getDebugLoc();
6375 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6378 if (VT.getSizeInBits() == 8) {
6379 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6380 Op.getOperand(0), Op.getOperand(1));
6381 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6382 DAG.getValueType(VT));
6383 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6384 } else if (VT.getSizeInBits() == 16) {
6385 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6386 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6388 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6389 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6390 DAG.getNode(ISD::BITCAST, dl,
6394 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6395 Op.getOperand(0), Op.getOperand(1));
6396 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6397 DAG.getValueType(VT));
6398 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6399 } else if (VT == MVT::f32) {
6400 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6401 // the result back to FR32 register. It's only worth matching if the
6402 // result has a single use which is a store or a bitcast to i32. And in
6403 // the case of a store, it's not worth it if the index is a constant 0,
6404 // because a MOVSSmr can be used instead, which is smaller and faster.
6405 if (!Op.hasOneUse())
6407 SDNode *User = *Op.getNode()->use_begin();
6408 if ((User->getOpcode() != ISD::STORE ||
6409 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6410 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6411 (User->getOpcode() != ISD::BITCAST ||
6412 User->getValueType(0) != MVT::i32))
6414 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6415 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6418 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6419 } else if (VT == MVT::i32) {
6420 // ExtractPS works with constant index.
6421 if (isa<ConstantSDNode>(Op.getOperand(1)))
6429 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6430 SelectionDAG &DAG) const {
6431 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6434 SDValue Vec = Op.getOperand(0);
6435 EVT VecVT = Vec.getValueType();
6437 // If this is a 256-bit vector result, first extract the 128-bit vector and
6438 // then extract the element from the 128-bit vector.
6439 if (VecVT.getSizeInBits() == 256) {
6440 DebugLoc dl = Op.getNode()->getDebugLoc();
6441 unsigned NumElems = VecVT.getVectorNumElements();
6442 SDValue Idx = Op.getOperand(1);
6443 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6445 // Get the 128-bit vector.
6446 bool Upper = IdxVal >= NumElems/2;
6447 Vec = Extract128BitVector(Vec,
6448 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6450 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6451 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6454 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6456 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6457 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6462 EVT VT = Op.getValueType();
6463 DebugLoc dl = Op.getDebugLoc();
6464 // TODO: handle v16i8.
6465 if (VT.getSizeInBits() == 16) {
6466 SDValue Vec = Op.getOperand(0);
6467 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6469 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6470 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6471 DAG.getNode(ISD::BITCAST, dl,
6474 // Transform it so it match pextrw which produces a 32-bit result.
6475 EVT EltVT = MVT::i32;
6476 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6477 Op.getOperand(0), Op.getOperand(1));
6478 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6479 DAG.getValueType(VT));
6480 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6481 } else if (VT.getSizeInBits() == 32) {
6482 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6486 // SHUFPS the element to the lowest double word, then movss.
6487 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6488 EVT VVT = Op.getOperand(0).getValueType();
6489 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6490 DAG.getUNDEF(VVT), Mask);
6491 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6492 DAG.getIntPtrConstant(0));
6493 } else if (VT.getSizeInBits() == 64) {
6494 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6495 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6496 // to match extract_elt for f64.
6497 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6501 // UNPCKHPD the element to the lowest double word, then movsd.
6502 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6503 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6504 int Mask[2] = { 1, -1 };
6505 EVT VVT = Op.getOperand(0).getValueType();
6506 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6507 DAG.getUNDEF(VVT), Mask);
6508 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6509 DAG.getIntPtrConstant(0));
6516 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6517 SelectionDAG &DAG) const {
6518 EVT VT = Op.getValueType();
6519 EVT EltVT = VT.getVectorElementType();
6520 DebugLoc dl = Op.getDebugLoc();
6522 SDValue N0 = Op.getOperand(0);
6523 SDValue N1 = Op.getOperand(1);
6524 SDValue N2 = Op.getOperand(2);
6526 if (VT.getSizeInBits() == 256)
6529 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6530 isa<ConstantSDNode>(N2)) {
6532 if (VT == MVT::v8i16)
6533 Opc = X86ISD::PINSRW;
6534 else if (VT == MVT::v16i8)
6535 Opc = X86ISD::PINSRB;
6537 Opc = X86ISD::PINSRB;
6539 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6541 if (N1.getValueType() != MVT::i32)
6542 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6543 if (N2.getValueType() != MVT::i32)
6544 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6545 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6546 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6547 // Bits [7:6] of the constant are the source select. This will always be
6548 // zero here. The DAG Combiner may combine an extract_elt index into these
6549 // bits. For example (insert (extract, 3), 2) could be matched by putting
6550 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6551 // Bits [5:4] of the constant are the destination select. This is the
6552 // value of the incoming immediate.
6553 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6554 // combine either bitwise AND or insert of float 0.0 to set these bits.
6555 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6556 // Create this as a scalar to vector..
6557 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6558 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6559 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6560 // PINSR* works with constant index.
6567 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6568 EVT VT = Op.getValueType();
6569 EVT EltVT = VT.getVectorElementType();
6571 DebugLoc dl = Op.getDebugLoc();
6572 SDValue N0 = Op.getOperand(0);
6573 SDValue N1 = Op.getOperand(1);
6574 SDValue N2 = Op.getOperand(2);
6576 // If this is a 256-bit vector result, first extract the 128-bit vector,
6577 // insert the element into the extracted half and then place it back.
6578 if (VT.getSizeInBits() == 256) {
6579 if (!isa<ConstantSDNode>(N2))
6582 // Get the desired 128-bit vector half.
6583 unsigned NumElems = VT.getVectorNumElements();
6584 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6585 bool Upper = IdxVal >= NumElems/2;
6586 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6587 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6589 // Insert the element into the desired half.
6590 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6591 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6593 // Insert the changed part back to the 256-bit vector
6594 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6597 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
6598 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6600 if (EltVT == MVT::i8)
6603 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6604 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6605 // as its second argument.
6606 if (N1.getValueType() != MVT::i32)
6607 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6608 if (N2.getValueType() != MVT::i32)
6609 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6610 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6616 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6617 LLVMContext *Context = DAG.getContext();
6618 DebugLoc dl = Op.getDebugLoc();
6619 EVT OpVT = Op.getValueType();
6621 // If this is a 256-bit vector result, first insert into a 128-bit
6622 // vector and then insert into the 256-bit vector.
6623 if (OpVT.getSizeInBits() > 128) {
6624 // Insert into a 128-bit vector.
6625 EVT VT128 = EVT::getVectorVT(*Context,
6626 OpVT.getVectorElementType(),
6627 OpVT.getVectorNumElements() / 2);
6629 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6631 // Insert the 128-bit vector.
6632 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6633 DAG.getConstant(0, MVT::i32),
6637 if (Op.getValueType() == MVT::v1i64 &&
6638 Op.getOperand(0).getValueType() == MVT::i64)
6639 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6641 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6642 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6643 "Expected an SSE type!");
6644 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6645 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6648 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6649 // a simple subregister reference or explicit instructions to grab
6650 // upper bits of a vector.
6652 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6653 if (Subtarget->hasAVX()) {
6654 DebugLoc dl = Op.getNode()->getDebugLoc();
6655 SDValue Vec = Op.getNode()->getOperand(0);
6656 SDValue Idx = Op.getNode()->getOperand(1);
6658 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6659 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6660 return Extract128BitVector(Vec, Idx, DAG, dl);
6666 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6667 // simple superregister reference or explicit instructions to insert
6668 // the upper bits of a vector.
6670 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6671 if (Subtarget->hasAVX()) {
6672 DebugLoc dl = Op.getNode()->getDebugLoc();
6673 SDValue Vec = Op.getNode()->getOperand(0);
6674 SDValue SubVec = Op.getNode()->getOperand(1);
6675 SDValue Idx = Op.getNode()->getOperand(2);
6677 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6678 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6679 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6685 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6686 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6687 // one of the above mentioned nodes. It has to be wrapped because otherwise
6688 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6689 // be used to form addressing mode. These wrapped nodes will be selected
6692 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6693 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6695 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6697 unsigned char OpFlag = 0;
6698 unsigned WrapperKind = X86ISD::Wrapper;
6699 CodeModel::Model M = getTargetMachine().getCodeModel();
6701 if (Subtarget->isPICStyleRIPRel() &&
6702 (M == CodeModel::Small || M == CodeModel::Kernel))
6703 WrapperKind = X86ISD::WrapperRIP;
6704 else if (Subtarget->isPICStyleGOT())
6705 OpFlag = X86II::MO_GOTOFF;
6706 else if (Subtarget->isPICStyleStubPIC())
6707 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6709 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6711 CP->getOffset(), OpFlag);
6712 DebugLoc DL = CP->getDebugLoc();
6713 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6714 // With PIC, the address is actually $g + Offset.
6716 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6717 DAG.getNode(X86ISD::GlobalBaseReg,
6718 DebugLoc(), getPointerTy()),
6725 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6726 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6728 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6730 unsigned char OpFlag = 0;
6731 unsigned WrapperKind = X86ISD::Wrapper;
6732 CodeModel::Model M = getTargetMachine().getCodeModel();
6734 if (Subtarget->isPICStyleRIPRel() &&
6735 (M == CodeModel::Small || M == CodeModel::Kernel))
6736 WrapperKind = X86ISD::WrapperRIP;
6737 else if (Subtarget->isPICStyleGOT())
6738 OpFlag = X86II::MO_GOTOFF;
6739 else if (Subtarget->isPICStyleStubPIC())
6740 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6742 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6744 DebugLoc DL = JT->getDebugLoc();
6745 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6747 // With PIC, the address is actually $g + Offset.
6749 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6750 DAG.getNode(X86ISD::GlobalBaseReg,
6751 DebugLoc(), getPointerTy()),
6758 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
6759 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
6761 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6763 unsigned char OpFlag = 0;
6764 unsigned WrapperKind = X86ISD::Wrapper;
6765 CodeModel::Model M = getTargetMachine().getCodeModel();
6767 if (Subtarget->isPICStyleRIPRel() &&
6768 (M == CodeModel::Small || M == CodeModel::Kernel)) {
6769 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
6770 OpFlag = X86II::MO_GOTPCREL;
6771 WrapperKind = X86ISD::WrapperRIP;
6772 } else if (Subtarget->isPICStyleGOT()) {
6773 OpFlag = X86II::MO_GOT;
6774 } else if (Subtarget->isPICStyleStubPIC()) {
6775 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
6776 } else if (Subtarget->isPICStyleStubNoDynamic()) {
6777 OpFlag = X86II::MO_DARWIN_NONLAZY;
6780 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
6782 DebugLoc DL = Op.getDebugLoc();
6783 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6786 // With PIC, the address is actually $g + Offset.
6787 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
6788 !Subtarget->is64Bit()) {
6789 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6790 DAG.getNode(X86ISD::GlobalBaseReg,
6791 DebugLoc(), getPointerTy()),
6795 // For symbols that require a load from a stub to get the address, emit the
6797 if (isGlobalStubReference(OpFlag))
6798 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
6799 MachinePointerInfo::getGOT(), false, false, 0);
6805 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
6806 // Create the TargetBlockAddressAddress node.
6807 unsigned char OpFlags =
6808 Subtarget->ClassifyBlockAddressReference();
6809 CodeModel::Model M = getTargetMachine().getCodeModel();
6810 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
6811 DebugLoc dl = Op.getDebugLoc();
6812 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
6813 /*isTarget=*/true, OpFlags);
6815 if (Subtarget->isPICStyleRIPRel() &&
6816 (M == CodeModel::Small || M == CodeModel::Kernel))
6817 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6819 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6821 // With PIC, the address is actually $g + Offset.
6822 if (isGlobalRelativeToPICBase(OpFlags)) {
6823 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6824 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6832 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
6834 SelectionDAG &DAG) const {
6835 // Create the TargetGlobalAddress node, folding in the constant
6836 // offset if it is legal.
6837 unsigned char OpFlags =
6838 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
6839 CodeModel::Model M = getTargetMachine().getCodeModel();
6841 if (OpFlags == X86II::MO_NO_FLAG &&
6842 X86::isOffsetSuitableForCodeModel(Offset, M)) {
6843 // A direct static reference to a global.
6844 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
6847 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6850 if (Subtarget->isPICStyleRIPRel() &&
6851 (M == CodeModel::Small || M == CodeModel::Kernel))
6852 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6854 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6856 // With PIC, the address is actually $g + Offset.
6857 if (isGlobalRelativeToPICBase(OpFlags)) {
6858 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6859 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6863 // For globals that require a load from a stub to get the address, emit the
6865 if (isGlobalStubReference(OpFlags))
6866 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6867 MachinePointerInfo::getGOT(), false, false, 0);
6869 // If there was a non-zero offset that we didn't fold, create an explicit
6872 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6873 DAG.getConstant(Offset, getPointerTy()));
6879 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6880 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6881 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6882 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6886 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6887 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6888 unsigned char OperandFlags) {
6889 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6890 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6891 DebugLoc dl = GA->getDebugLoc();
6892 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6893 GA->getValueType(0),
6897 SDValue Ops[] = { Chain, TGA, *InFlag };
6898 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6900 SDValue Ops[] = { Chain, TGA };
6901 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6904 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6905 MFI->setAdjustsStack(true);
6907 SDValue Flag = Chain.getValue(1);
6908 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6911 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6913 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6916 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6917 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6918 DAG.getNode(X86ISD::GlobalBaseReg,
6919 DebugLoc(), PtrVT), InFlag);
6920 InFlag = Chain.getValue(1);
6922 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6925 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6927 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6929 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6930 X86::RAX, X86II::MO_TLSGD);
6933 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6934 // "local exec" model.
6935 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6936 const EVT PtrVT, TLSModel::Model model,
6938 DebugLoc dl = GA->getDebugLoc();
6940 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6941 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6942 is64Bit ? 257 : 256));
6944 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6945 DAG.getIntPtrConstant(0),
6946 MachinePointerInfo(Ptr), false, false, 0);
6948 unsigned char OperandFlags = 0;
6949 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6951 unsigned WrapperKind = X86ISD::Wrapper;
6952 if (model == TLSModel::LocalExec) {
6953 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6954 } else if (is64Bit) {
6955 assert(model == TLSModel::InitialExec);
6956 OperandFlags = X86II::MO_GOTTPOFF;
6957 WrapperKind = X86ISD::WrapperRIP;
6959 assert(model == TLSModel::InitialExec);
6960 OperandFlags = X86II::MO_INDNTPOFF;
6963 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6965 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6966 GA->getValueType(0),
6967 GA->getOffset(), OperandFlags);
6968 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6970 if (model == TLSModel::InitialExec)
6971 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6972 MachinePointerInfo::getGOT(), false, false, 0);
6974 // The address of the thread local variable is the add of the thread
6975 // pointer with the offset of the variable.
6976 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6980 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6982 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6983 const GlobalValue *GV = GA->getGlobal();
6985 if (Subtarget->isTargetELF()) {
6986 // TODO: implement the "local dynamic" model
6987 // TODO: implement the "initial exec"model for pic executables
6989 // If GV is an alias then use the aliasee for determining
6990 // thread-localness.
6991 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6992 GV = GA->resolveAliasedGlobal(false);
6994 TLSModel::Model model
6995 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6998 case TLSModel::GeneralDynamic:
6999 case TLSModel::LocalDynamic: // not implemented
7000 if (Subtarget->is64Bit())
7001 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7002 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7004 case TLSModel::InitialExec:
7005 case TLSModel::LocalExec:
7006 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7007 Subtarget->is64Bit());
7009 } else if (Subtarget->isTargetDarwin()) {
7010 // Darwin only has one model of TLS. Lower to that.
7011 unsigned char OpFlag = 0;
7012 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7013 X86ISD::WrapperRIP : X86ISD::Wrapper;
7015 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7017 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7018 !Subtarget->is64Bit();
7020 OpFlag = X86II::MO_TLVP_PIC_BASE;
7022 OpFlag = X86II::MO_TLVP;
7023 DebugLoc DL = Op.getDebugLoc();
7024 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7025 GA->getValueType(0),
7026 GA->getOffset(), OpFlag);
7027 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7029 // With PIC32, the address is actually $g + Offset.
7031 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7032 DAG.getNode(X86ISD::GlobalBaseReg,
7033 DebugLoc(), getPointerTy()),
7036 // Lowering the machine isd will make sure everything is in the right
7038 SDValue Chain = DAG.getEntryNode();
7039 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7040 SDValue Args[] = { Chain, Offset };
7041 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7043 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7044 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7045 MFI->setAdjustsStack(true);
7047 // And our return value (tls address) is in the standard call return value
7049 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7050 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7054 "TLS not implemented for this target.");
7056 llvm_unreachable("Unreachable");
7061 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7062 /// take a 2 x i32 value to shift plus a shift amount.
7063 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7064 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7065 EVT VT = Op.getValueType();
7066 unsigned VTBits = VT.getSizeInBits();
7067 DebugLoc dl = Op.getDebugLoc();
7068 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7069 SDValue ShOpLo = Op.getOperand(0);
7070 SDValue ShOpHi = Op.getOperand(1);
7071 SDValue ShAmt = Op.getOperand(2);
7072 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7073 DAG.getConstant(VTBits - 1, MVT::i8))
7074 : DAG.getConstant(0, VT);
7077 if (Op.getOpcode() == ISD::SHL_PARTS) {
7078 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7079 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7081 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7082 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7085 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7086 DAG.getConstant(VTBits, MVT::i8));
7087 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7088 AndNode, DAG.getConstant(0, MVT::i8));
7091 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7092 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7093 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7095 if (Op.getOpcode() == ISD::SHL_PARTS) {
7096 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7097 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7099 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7100 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7103 SDValue Ops[2] = { Lo, Hi };
7104 return DAG.getMergeValues(Ops, 2, dl);
7107 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7108 SelectionDAG &DAG) const {
7109 EVT SrcVT = Op.getOperand(0).getValueType();
7111 if (SrcVT.isVector())
7114 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7115 "Unknown SINT_TO_FP to lower!");
7117 // These are really Legal; return the operand so the caller accepts it as
7119 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7121 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7122 Subtarget->is64Bit()) {
7126 DebugLoc dl = Op.getDebugLoc();
7127 unsigned Size = SrcVT.getSizeInBits()/8;
7128 MachineFunction &MF = DAG.getMachineFunction();
7129 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7130 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7131 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7133 MachinePointerInfo::getFixedStack(SSFI),
7135 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7138 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7140 SelectionDAG &DAG) const {
7142 DebugLoc DL = Op.getDebugLoc();
7144 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7146 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7148 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7150 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7152 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7153 MachineMemOperand *MMO;
7155 int SSFI = FI->getIndex();
7157 DAG.getMachineFunction()
7158 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7159 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7161 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7162 StackSlot = StackSlot.getOperand(1);
7164 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7165 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7167 Tys, Ops, array_lengthof(Ops),
7171 Chain = Result.getValue(1);
7172 SDValue InFlag = Result.getValue(2);
7174 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7175 // shouldn't be necessary except that RFP cannot be live across
7176 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7177 MachineFunction &MF = DAG.getMachineFunction();
7178 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7179 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7180 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7181 Tys = DAG.getVTList(MVT::Other);
7183 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7185 MachineMemOperand *MMO =
7186 DAG.getMachineFunction()
7187 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7188 MachineMemOperand::MOStore, SSFISize, SSFISize);
7190 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7191 Ops, array_lengthof(Ops),
7192 Op.getValueType(), MMO);
7193 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7194 MachinePointerInfo::getFixedStack(SSFI),
7201 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7202 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7203 SelectionDAG &DAG) const {
7204 // This algorithm is not obvious. Here it is in C code, more or less:
7206 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7207 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7208 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7210 // Copy ints to xmm registers.
7211 __m128i xh = _mm_cvtsi32_si128( hi );
7212 __m128i xl = _mm_cvtsi32_si128( lo );
7214 // Combine into low half of a single xmm register.
7215 __m128i x = _mm_unpacklo_epi32( xh, xl );
7219 // Merge in appropriate exponents to give the integer bits the right
7221 x = _mm_unpacklo_epi32( x, exp );
7223 // Subtract away the biases to deal with the IEEE-754 double precision
7225 d = _mm_sub_pd( (__m128d) x, bias );
7227 // All conversions up to here are exact. The correctly rounded result is
7228 // calculated using the current rounding mode using the following
7230 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7231 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7232 // store doesn't really need to be here (except
7233 // maybe to zero the other double)
7238 DebugLoc dl = Op.getDebugLoc();
7239 LLVMContext *Context = DAG.getContext();
7241 // Build some magic constants.
7242 std::vector<Constant*> CV0;
7243 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7244 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7245 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7246 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7247 Constant *C0 = ConstantVector::get(CV0);
7248 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7250 std::vector<Constant*> CV1;
7252 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7254 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7255 Constant *C1 = ConstantVector::get(CV1);
7256 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7258 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7259 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7261 DAG.getIntPtrConstant(1)));
7262 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7263 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7265 DAG.getIntPtrConstant(0)));
7266 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7267 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7268 MachinePointerInfo::getConstantPool(),
7270 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7271 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7272 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7273 MachinePointerInfo::getConstantPool(),
7275 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7277 // Add the halves; easiest way is to swap them into another reg first.
7278 int ShufMask[2] = { 1, -1 };
7279 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7280 DAG.getUNDEF(MVT::v2f64), ShufMask);
7281 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7282 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7283 DAG.getIntPtrConstant(0));
7286 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7287 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7288 SelectionDAG &DAG) const {
7289 DebugLoc dl = Op.getDebugLoc();
7290 // FP constant to bias correct the final result.
7291 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7294 // Load the 32-bit value into an XMM register.
7295 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7298 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7299 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7300 DAG.getIntPtrConstant(0));
7302 // Or the load with the bias.
7303 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7304 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7305 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7307 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7308 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7309 MVT::v2f64, Bias)));
7310 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7311 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7312 DAG.getIntPtrConstant(0));
7314 // Subtract the bias.
7315 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7317 // Handle final rounding.
7318 EVT DestVT = Op.getValueType();
7320 if (DestVT.bitsLT(MVT::f64)) {
7321 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7322 DAG.getIntPtrConstant(0));
7323 } else if (DestVT.bitsGT(MVT::f64)) {
7324 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7327 // Handle final rounding.
7331 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7332 SelectionDAG &DAG) const {
7333 SDValue N0 = Op.getOperand(0);
7334 DebugLoc dl = Op.getDebugLoc();
7336 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7337 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7338 // the optimization here.
7339 if (DAG.SignBitIsZero(N0))
7340 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7342 EVT SrcVT = N0.getValueType();
7343 EVT DstVT = Op.getValueType();
7344 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7345 return LowerUINT_TO_FP_i64(Op, DAG);
7346 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7347 return LowerUINT_TO_FP_i32(Op, DAG);
7349 // Make a 64-bit buffer, and use it to build an FILD.
7350 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7351 if (SrcVT == MVT::i32) {
7352 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7353 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7354 getPointerTy(), StackSlot, WordOff);
7355 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7356 StackSlot, MachinePointerInfo(),
7358 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7359 OffsetSlot, MachinePointerInfo(),
7361 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7365 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7366 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7367 StackSlot, MachinePointerInfo(),
7369 // For i64 source, we need to add the appropriate power of 2 if the input
7370 // was negative. This is the same as the optimization in
7371 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7372 // we must be careful to do the computation in x87 extended precision, not
7373 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7374 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7375 MachineMemOperand *MMO =
7376 DAG.getMachineFunction()
7377 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7378 MachineMemOperand::MOLoad, 8, 8);
7380 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7381 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7382 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7385 APInt FF(32, 0x5F800000ULL);
7387 // Check whether the sign bit is set.
7388 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7389 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7392 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7393 SDValue FudgePtr = DAG.getConstantPool(
7394 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7397 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7398 SDValue Zero = DAG.getIntPtrConstant(0);
7399 SDValue Four = DAG.getIntPtrConstant(4);
7400 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7402 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7404 // Load the value out, extending it from f32 to f80.
7405 // FIXME: Avoid the extend by constructing the right constant pool?
7406 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7407 FudgePtr, MachinePointerInfo::getConstantPool(),
7408 MVT::f32, false, false, 4);
7409 // Extend everything to 80 bits to force it to be done on x87.
7410 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7411 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7414 std::pair<SDValue,SDValue> X86TargetLowering::
7415 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7416 DebugLoc DL = Op.getDebugLoc();
7418 EVT DstTy = Op.getValueType();
7421 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7425 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7426 DstTy.getSimpleVT() >= MVT::i16 &&
7427 "Unknown FP_TO_SINT to lower!");
7429 // These are really Legal.
7430 if (DstTy == MVT::i32 &&
7431 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7432 return std::make_pair(SDValue(), SDValue());
7433 if (Subtarget->is64Bit() &&
7434 DstTy == MVT::i64 &&
7435 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7436 return std::make_pair(SDValue(), SDValue());
7438 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7440 MachineFunction &MF = DAG.getMachineFunction();
7441 unsigned MemSize = DstTy.getSizeInBits()/8;
7442 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7443 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7448 switch (DstTy.getSimpleVT().SimpleTy) {
7449 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7450 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7451 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7452 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7455 SDValue Chain = DAG.getEntryNode();
7456 SDValue Value = Op.getOperand(0);
7457 EVT TheVT = Op.getOperand(0).getValueType();
7458 if (isScalarFPTypeInSSEReg(TheVT)) {
7459 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7460 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7461 MachinePointerInfo::getFixedStack(SSFI),
7463 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7465 Chain, StackSlot, DAG.getValueType(TheVT)
7468 MachineMemOperand *MMO =
7469 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7470 MachineMemOperand::MOLoad, MemSize, MemSize);
7471 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7473 Chain = Value.getValue(1);
7474 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7475 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7478 MachineMemOperand *MMO =
7479 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7480 MachineMemOperand::MOStore, MemSize, MemSize);
7482 // Build the FP_TO_INT*_IN_MEM
7483 SDValue Ops[] = { Chain, Value, StackSlot };
7484 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7485 Ops, 3, DstTy, MMO);
7487 return std::make_pair(FIST, StackSlot);
7490 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7491 SelectionDAG &DAG) const {
7492 if (Op.getValueType().isVector())
7495 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7496 SDValue FIST = Vals.first, StackSlot = Vals.second;
7497 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7498 if (FIST.getNode() == 0) return Op;
7501 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7502 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7505 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7506 SelectionDAG &DAG) const {
7507 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7508 SDValue FIST = Vals.first, StackSlot = Vals.second;
7509 assert(FIST.getNode() && "Unexpected failure");
7512 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7513 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7516 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7517 SelectionDAG &DAG) const {
7518 LLVMContext *Context = DAG.getContext();
7519 DebugLoc dl = Op.getDebugLoc();
7520 EVT VT = Op.getValueType();
7523 EltVT = VT.getVectorElementType();
7524 std::vector<Constant*> CV;
7525 if (EltVT == MVT::f64) {
7526 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7530 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7536 Constant *C = ConstantVector::get(CV);
7537 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7538 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7539 MachinePointerInfo::getConstantPool(),
7541 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7544 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7545 LLVMContext *Context = DAG.getContext();
7546 DebugLoc dl = Op.getDebugLoc();
7547 EVT VT = Op.getValueType();
7550 EltVT = VT.getVectorElementType();
7551 std::vector<Constant*> CV;
7552 if (EltVT == MVT::f64) {
7553 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7557 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7563 Constant *C = ConstantVector::get(CV);
7564 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7565 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7566 MachinePointerInfo::getConstantPool(),
7568 if (VT.isVector()) {
7569 return DAG.getNode(ISD::BITCAST, dl, VT,
7570 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7571 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7573 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7575 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7579 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7580 LLVMContext *Context = DAG.getContext();
7581 SDValue Op0 = Op.getOperand(0);
7582 SDValue Op1 = Op.getOperand(1);
7583 DebugLoc dl = Op.getDebugLoc();
7584 EVT VT = Op.getValueType();
7585 EVT SrcVT = Op1.getValueType();
7587 // If second operand is smaller, extend it first.
7588 if (SrcVT.bitsLT(VT)) {
7589 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7592 // And if it is bigger, shrink it first.
7593 if (SrcVT.bitsGT(VT)) {
7594 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7598 // At this point the operands and the result should have the same
7599 // type, and that won't be f80 since that is not custom lowered.
7601 // First get the sign bit of second operand.
7602 std::vector<Constant*> CV;
7603 if (SrcVT == MVT::f64) {
7604 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7605 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7607 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7608 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7609 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7610 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7612 Constant *C = ConstantVector::get(CV);
7613 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7614 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7615 MachinePointerInfo::getConstantPool(),
7617 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7619 // Shift sign bit right or left if the two operands have different types.
7620 if (SrcVT.bitsGT(VT)) {
7621 // Op0 is MVT::f32, Op1 is MVT::f64.
7622 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7623 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7624 DAG.getConstant(32, MVT::i32));
7625 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7626 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7627 DAG.getIntPtrConstant(0));
7630 // Clear first operand sign bit.
7632 if (VT == MVT::f64) {
7633 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7634 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7636 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7637 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7638 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7639 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7641 C = ConstantVector::get(CV);
7642 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7643 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7644 MachinePointerInfo::getConstantPool(),
7646 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7648 // Or the value with the sign bit.
7649 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7652 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7653 SDValue N0 = Op.getOperand(0);
7654 DebugLoc dl = Op.getDebugLoc();
7655 EVT VT = Op.getValueType();
7657 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7658 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7659 DAG.getConstant(1, VT));
7660 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7663 /// Emit nodes that will be selected as "test Op0,Op0", or something
7665 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7666 SelectionDAG &DAG) const {
7667 DebugLoc dl = Op.getDebugLoc();
7669 // CF and OF aren't always set the way we want. Determine which
7670 // of these we need.
7671 bool NeedCF = false;
7672 bool NeedOF = false;
7675 case X86::COND_A: case X86::COND_AE:
7676 case X86::COND_B: case X86::COND_BE:
7679 case X86::COND_G: case X86::COND_GE:
7680 case X86::COND_L: case X86::COND_LE:
7681 case X86::COND_O: case X86::COND_NO:
7686 // See if we can use the EFLAGS value from the operand instead of
7687 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
7688 // we prove that the arithmetic won't overflow, we can't use OF or CF.
7689 if (Op.getResNo() != 0 || NeedOF || NeedCF)
7690 // Emit a CMP with 0, which is the TEST pattern.
7691 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7692 DAG.getConstant(0, Op.getValueType()));
7694 unsigned Opcode = 0;
7695 unsigned NumOperands = 0;
7696 switch (Op.getNode()->getOpcode()) {
7698 // Due to an isel shortcoming, be conservative if this add is likely to be
7699 // selected as part of a load-modify-store instruction. When the root node
7700 // in a match is a store, isel doesn't know how to remap non-chain non-flag
7701 // uses of other nodes in the match, such as the ADD in this case. This
7702 // leads to the ADD being left around and reselected, with the result being
7703 // two adds in the output. Alas, even if none our users are stores, that
7704 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
7705 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7706 // climbing the DAG back to the root, and it doesn't seem to be worth the
7708 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7709 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7710 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
7713 if (ConstantSDNode *C =
7714 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
7715 // An add of one will be selected as an INC.
7716 if (C->getAPIntValue() == 1) {
7717 Opcode = X86ISD::INC;
7722 // An add of negative one (subtract of one) will be selected as a DEC.
7723 if (C->getAPIntValue().isAllOnesValue()) {
7724 Opcode = X86ISD::DEC;
7730 // Otherwise use a regular EFLAGS-setting add.
7731 Opcode = X86ISD::ADD;
7735 // If the primary and result isn't used, don't bother using X86ISD::AND,
7736 // because a TEST instruction will be better.
7737 bool NonFlagUse = false;
7738 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7739 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
7741 unsigned UOpNo = UI.getOperandNo();
7742 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
7743 // Look pass truncate.
7744 UOpNo = User->use_begin().getOperandNo();
7745 User = *User->use_begin();
7748 if (User->getOpcode() != ISD::BRCOND &&
7749 User->getOpcode() != ISD::SETCC &&
7750 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
7763 // Due to the ISEL shortcoming noted above, be conservative if this op is
7764 // likely to be selected as part of a load-modify-store instruction.
7765 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7766 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7767 if (UI->getOpcode() == ISD::STORE)
7770 // Otherwise use a regular EFLAGS-setting instruction.
7771 switch (Op.getNode()->getOpcode()) {
7772 default: llvm_unreachable("unexpected operator!");
7773 case ISD::SUB: Opcode = X86ISD::SUB; break;
7774 case ISD::OR: Opcode = X86ISD::OR; break;
7775 case ISD::XOR: Opcode = X86ISD::XOR; break;
7776 case ISD::AND: Opcode = X86ISD::AND; break;
7788 return SDValue(Op.getNode(), 1);
7795 // Emit a CMP with 0, which is the TEST pattern.
7796 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7797 DAG.getConstant(0, Op.getValueType()));
7799 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
7800 SmallVector<SDValue, 4> Ops;
7801 for (unsigned i = 0; i != NumOperands; ++i)
7802 Ops.push_back(Op.getOperand(i));
7804 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
7805 DAG.ReplaceAllUsesWith(Op, New);
7806 return SDValue(New.getNode(), 1);
7809 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
7811 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
7812 SelectionDAG &DAG) const {
7813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
7814 if (C->getAPIntValue() == 0)
7815 return EmitTest(Op0, X86CC, DAG);
7817 DebugLoc dl = Op0.getDebugLoc();
7818 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
7821 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
7822 /// if it's possible.
7823 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
7824 DebugLoc dl, SelectionDAG &DAG) const {
7825 SDValue Op0 = And.getOperand(0);
7826 SDValue Op1 = And.getOperand(1);
7827 if (Op0.getOpcode() == ISD::TRUNCATE)
7828 Op0 = Op0.getOperand(0);
7829 if (Op1.getOpcode() == ISD::TRUNCATE)
7830 Op1 = Op1.getOperand(0);
7833 if (Op1.getOpcode() == ISD::SHL)
7834 std::swap(Op0, Op1);
7835 if (Op0.getOpcode() == ISD::SHL) {
7836 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
7837 if (And00C->getZExtValue() == 1) {
7838 // If we looked past a truncate, check that it's only truncating away
7840 unsigned BitWidth = Op0.getValueSizeInBits();
7841 unsigned AndBitWidth = And.getValueSizeInBits();
7842 if (BitWidth > AndBitWidth) {
7843 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
7844 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
7845 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
7849 RHS = Op0.getOperand(1);
7851 } else if (Op1.getOpcode() == ISD::Constant) {
7852 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
7853 SDValue AndLHS = Op0;
7854 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
7855 LHS = AndLHS.getOperand(0);
7856 RHS = AndLHS.getOperand(1);
7860 if (LHS.getNode()) {
7861 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
7862 // instruction. Since the shift amount is in-range-or-undefined, we know
7863 // that doing a bittest on the i32 value is ok. We extend to i32 because
7864 // the encoding for the i16 version is larger than the i32 version.
7865 // Also promote i16 to i32 for performance / code size reason.
7866 if (LHS.getValueType() == MVT::i8 ||
7867 LHS.getValueType() == MVT::i16)
7868 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7870 // If the operand types disagree, extend the shift amount to match. Since
7871 // BT ignores high bits (like shifts) we can use anyextend.
7872 if (LHS.getValueType() != RHS.getValueType())
7873 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7875 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7876 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7877 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7878 DAG.getConstant(Cond, MVT::i8), BT);
7884 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7885 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7886 SDValue Op0 = Op.getOperand(0);
7887 SDValue Op1 = Op.getOperand(1);
7888 DebugLoc dl = Op.getDebugLoc();
7889 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7891 // Optimize to BT if possible.
7892 // Lower (X & (1 << N)) == 0 to BT(X, N).
7893 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7894 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7895 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
7896 Op1.getOpcode() == ISD::Constant &&
7897 cast<ConstantSDNode>(Op1)->isNullValue() &&
7898 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7899 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7900 if (NewSetCC.getNode())
7904 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
7906 if (Op1.getOpcode() == ISD::Constant &&
7907 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7908 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7909 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7911 // If the input is a setcc, then reuse the input setcc or use a new one with
7912 // the inverted condition.
7913 if (Op0.getOpcode() == X86ISD::SETCC) {
7914 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7915 bool Invert = (CC == ISD::SETNE) ^
7916 cast<ConstantSDNode>(Op1)->isNullValue();
7917 if (!Invert) return Op0;
7919 CCode = X86::GetOppositeBranchCondition(CCode);
7920 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7921 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7925 bool isFP = Op1.getValueType().isFloatingPoint();
7926 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7927 if (X86CC == X86::COND_INVALID)
7930 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
7931 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7932 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
7935 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7937 SDValue Op0 = Op.getOperand(0);
7938 SDValue Op1 = Op.getOperand(1);
7939 SDValue CC = Op.getOperand(2);
7940 EVT VT = Op.getValueType();
7941 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7942 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7943 DebugLoc dl = Op.getDebugLoc();
7947 EVT EltVT = Op0.getValueType().getVectorElementType();
7948 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
7950 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7953 switch (SetCCOpcode) {
7956 case ISD::SETEQ: SSECC = 0; break;
7958 case ISD::SETGT: Swap = true; // Fallthrough
7960 case ISD::SETOLT: SSECC = 1; break;
7962 case ISD::SETGE: Swap = true; // Fallthrough
7964 case ISD::SETOLE: SSECC = 2; break;
7965 case ISD::SETUO: SSECC = 3; break;
7967 case ISD::SETNE: SSECC = 4; break;
7968 case ISD::SETULE: Swap = true;
7969 case ISD::SETUGE: SSECC = 5; break;
7970 case ISD::SETULT: Swap = true;
7971 case ISD::SETUGT: SSECC = 6; break;
7972 case ISD::SETO: SSECC = 7; break;
7975 std::swap(Op0, Op1);
7977 // In the two special cases we can't handle, emit two comparisons.
7979 if (SetCCOpcode == ISD::SETUEQ) {
7981 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7982 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7983 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7985 else if (SetCCOpcode == ISD::SETONE) {
7987 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7988 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7989 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7991 llvm_unreachable("Illegal FP comparison");
7993 // Handle all other FP comparisons here.
7994 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7997 if (!isFP && VT.getSizeInBits() == 256)
8000 // We are handling one of the integer comparisons here. Since SSE only has
8001 // GT and EQ comparisons for integer, swapping operands and multiple
8002 // operations may be required for some comparisons.
8003 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8004 bool Swap = false, Invert = false, FlipSigns = false;
8006 switch (VT.getSimpleVT().SimpleTy) {
8008 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8009 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8010 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8011 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8014 switch (SetCCOpcode) {
8016 case ISD::SETNE: Invert = true;
8017 case ISD::SETEQ: Opc = EQOpc; break;
8018 case ISD::SETLT: Swap = true;
8019 case ISD::SETGT: Opc = GTOpc; break;
8020 case ISD::SETGE: Swap = true;
8021 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8022 case ISD::SETULT: Swap = true;
8023 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8024 case ISD::SETUGE: Swap = true;
8025 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8028 std::swap(Op0, Op1);
8030 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8031 // bits of the inputs before performing those operations.
8033 EVT EltVT = VT.getVectorElementType();
8034 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8036 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8037 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8039 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8040 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8043 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8045 // If the logical-not of the result is required, perform that now.
8047 Result = DAG.getNOT(dl, Result, VT);
8052 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8053 static bool isX86LogicalCmp(SDValue Op) {
8054 unsigned Opc = Op.getNode()->getOpcode();
8055 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8057 if (Op.getResNo() == 1 &&
8058 (Opc == X86ISD::ADD ||
8059 Opc == X86ISD::SUB ||
8060 Opc == X86ISD::ADC ||
8061 Opc == X86ISD::SBB ||
8062 Opc == X86ISD::SMUL ||
8063 Opc == X86ISD::UMUL ||
8064 Opc == X86ISD::INC ||
8065 Opc == X86ISD::DEC ||
8066 Opc == X86ISD::OR ||
8067 Opc == X86ISD::XOR ||
8068 Opc == X86ISD::AND))
8071 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8077 static bool isZero(SDValue V) {
8078 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8079 return C && C->isNullValue();
8082 static bool isAllOnes(SDValue V) {
8083 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8084 return C && C->isAllOnesValue();
8087 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8088 bool addTest = true;
8089 SDValue Cond = Op.getOperand(0);
8090 SDValue Op1 = Op.getOperand(1);
8091 SDValue Op2 = Op.getOperand(2);
8092 DebugLoc DL = Op.getDebugLoc();
8095 if (Cond.getOpcode() == ISD::SETCC) {
8096 SDValue NewCond = LowerSETCC(Cond, DAG);
8097 if (NewCond.getNode())
8101 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8102 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8103 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8104 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8105 if (Cond.getOpcode() == X86ISD::SETCC &&
8106 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8107 isZero(Cond.getOperand(1).getOperand(1))) {
8108 SDValue Cmp = Cond.getOperand(1);
8110 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8112 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8113 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8114 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8116 SDValue CmpOp0 = Cmp.getOperand(0);
8117 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8118 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8120 SDValue Res = // Res = 0 or -1.
8121 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8122 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8124 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8125 Res = DAG.getNOT(DL, Res, Res.getValueType());
8127 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8128 if (N2C == 0 || !N2C->isNullValue())
8129 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8134 // Look past (and (setcc_carry (cmp ...)), 1).
8135 if (Cond.getOpcode() == ISD::AND &&
8136 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8137 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8138 if (C && C->getAPIntValue() == 1)
8139 Cond = Cond.getOperand(0);
8142 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8143 // setting operand in place of the X86ISD::SETCC.
8144 if (Cond.getOpcode() == X86ISD::SETCC ||
8145 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8146 CC = Cond.getOperand(0);
8148 SDValue Cmp = Cond.getOperand(1);
8149 unsigned Opc = Cmp.getOpcode();
8150 EVT VT = Op.getValueType();
8152 bool IllegalFPCMov = false;
8153 if (VT.isFloatingPoint() && !VT.isVector() &&
8154 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8155 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8157 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8158 Opc == X86ISD::BT) { // FIXME
8165 // Look pass the truncate.
8166 if (Cond.getOpcode() == ISD::TRUNCATE)
8167 Cond = Cond.getOperand(0);
8169 // We know the result of AND is compared against zero. Try to match
8171 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8172 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8173 if (NewSetCC.getNode()) {
8174 CC = NewSetCC.getOperand(0);
8175 Cond = NewSetCC.getOperand(1);
8182 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8183 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8186 // a < b ? -1 : 0 -> RES = ~setcc_carry
8187 // a < b ? 0 : -1 -> RES = setcc_carry
8188 // a >= b ? -1 : 0 -> RES = setcc_carry
8189 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8190 if (Cond.getOpcode() == X86ISD::CMP) {
8191 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8193 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8194 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8195 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8196 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8197 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8198 return DAG.getNOT(DL, Res, Res.getValueType());
8203 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8204 // condition is true.
8205 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8206 SDValue Ops[] = { Op2, Op1, CC, Cond };
8207 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8210 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8211 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8212 // from the AND / OR.
8213 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8214 Opc = Op.getOpcode();
8215 if (Opc != ISD::OR && Opc != ISD::AND)
8217 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8218 Op.getOperand(0).hasOneUse() &&
8219 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8220 Op.getOperand(1).hasOneUse());
8223 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8224 // 1 and that the SETCC node has a single use.
8225 static bool isXor1OfSetCC(SDValue Op) {
8226 if (Op.getOpcode() != ISD::XOR)
8228 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8229 if (N1C && N1C->getAPIntValue() == 1) {
8230 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8231 Op.getOperand(0).hasOneUse();
8236 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8237 bool addTest = true;
8238 SDValue Chain = Op.getOperand(0);
8239 SDValue Cond = Op.getOperand(1);
8240 SDValue Dest = Op.getOperand(2);
8241 DebugLoc dl = Op.getDebugLoc();
8244 if (Cond.getOpcode() == ISD::SETCC) {
8245 SDValue NewCond = LowerSETCC(Cond, DAG);
8246 if (NewCond.getNode())
8250 // FIXME: LowerXALUO doesn't handle these!!
8251 else if (Cond.getOpcode() == X86ISD::ADD ||
8252 Cond.getOpcode() == X86ISD::SUB ||
8253 Cond.getOpcode() == X86ISD::SMUL ||
8254 Cond.getOpcode() == X86ISD::UMUL)
8255 Cond = LowerXALUO(Cond, DAG);
8258 // Look pass (and (setcc_carry (cmp ...)), 1).
8259 if (Cond.getOpcode() == ISD::AND &&
8260 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8261 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8262 if (C && C->getAPIntValue() == 1)
8263 Cond = Cond.getOperand(0);
8266 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8267 // setting operand in place of the X86ISD::SETCC.
8268 if (Cond.getOpcode() == X86ISD::SETCC ||
8269 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8270 CC = Cond.getOperand(0);
8272 SDValue Cmp = Cond.getOperand(1);
8273 unsigned Opc = Cmp.getOpcode();
8274 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8275 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8279 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8283 // These can only come from an arithmetic instruction with overflow,
8284 // e.g. SADDO, UADDO.
8285 Cond = Cond.getNode()->getOperand(1);
8292 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8293 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8294 if (CondOpc == ISD::OR) {
8295 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8296 // two branches instead of an explicit OR instruction with a
8298 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8299 isX86LogicalCmp(Cmp)) {
8300 CC = Cond.getOperand(0).getOperand(0);
8301 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8302 Chain, Dest, CC, Cmp);
8303 CC = Cond.getOperand(1).getOperand(0);
8307 } else { // ISD::AND
8308 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8309 // two branches instead of an explicit AND instruction with a
8310 // separate test. However, we only do this if this block doesn't
8311 // have a fall-through edge, because this requires an explicit
8312 // jmp when the condition is false.
8313 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8314 isX86LogicalCmp(Cmp) &&
8315 Op.getNode()->hasOneUse()) {
8316 X86::CondCode CCode =
8317 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8318 CCode = X86::GetOppositeBranchCondition(CCode);
8319 CC = DAG.getConstant(CCode, MVT::i8);
8320 SDNode *User = *Op.getNode()->use_begin();
8321 // Look for an unconditional branch following this conditional branch.
8322 // We need this because we need to reverse the successors in order
8323 // to implement FCMP_OEQ.
8324 if (User->getOpcode() == ISD::BR) {
8325 SDValue FalseBB = User->getOperand(1);
8327 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8328 assert(NewBR == User);
8332 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8333 Chain, Dest, CC, Cmp);
8334 X86::CondCode CCode =
8335 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8336 CCode = X86::GetOppositeBranchCondition(CCode);
8337 CC = DAG.getConstant(CCode, MVT::i8);
8343 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8344 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8345 // It should be transformed during dag combiner except when the condition
8346 // is set by a arithmetics with overflow node.
8347 X86::CondCode CCode =
8348 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8349 CCode = X86::GetOppositeBranchCondition(CCode);
8350 CC = DAG.getConstant(CCode, MVT::i8);
8351 Cond = Cond.getOperand(0).getOperand(1);
8357 // Look pass the truncate.
8358 if (Cond.getOpcode() == ISD::TRUNCATE)
8359 Cond = Cond.getOperand(0);
8361 // We know the result of AND is compared against zero. Try to match
8363 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8364 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8365 if (NewSetCC.getNode()) {
8366 CC = NewSetCC.getOperand(0);
8367 Cond = NewSetCC.getOperand(1);
8374 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8375 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8377 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8378 Chain, Dest, CC, Cond);
8382 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8383 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8384 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8385 // that the guard pages used by the OS virtual memory manager are allocated in
8386 // correct sequence.
8388 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8389 SelectionDAG &DAG) const {
8390 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
8391 "This should be used only on Windows targets");
8392 assert(!Subtarget->isTargetEnvMacho());
8393 DebugLoc dl = Op.getDebugLoc();
8396 SDValue Chain = Op.getOperand(0);
8397 SDValue Size = Op.getOperand(1);
8398 // FIXME: Ensure alignment here
8402 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
8403 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8405 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8406 Flag = Chain.getValue(1);
8408 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8410 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8411 Flag = Chain.getValue(1);
8413 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8415 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8416 return DAG.getMergeValues(Ops1, 2, dl);
8419 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8420 MachineFunction &MF = DAG.getMachineFunction();
8421 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8423 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8424 DebugLoc DL = Op.getDebugLoc();
8426 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8427 // vastart just stores the address of the VarArgsFrameIndex slot into the
8428 // memory location argument.
8429 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8431 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8432 MachinePointerInfo(SV), false, false, 0);
8436 // gp_offset (0 - 6 * 8)
8437 // fp_offset (48 - 48 + 8 * 16)
8438 // overflow_arg_area (point to parameters coming in memory).
8440 SmallVector<SDValue, 8> MemOps;
8441 SDValue FIN = Op.getOperand(1);
8443 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8444 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8446 FIN, MachinePointerInfo(SV), false, false, 0);
8447 MemOps.push_back(Store);
8450 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8451 FIN, DAG.getIntPtrConstant(4));
8452 Store = DAG.getStore(Op.getOperand(0), DL,
8453 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8455 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8456 MemOps.push_back(Store);
8458 // Store ptr to overflow_arg_area
8459 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8460 FIN, DAG.getIntPtrConstant(4));
8461 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8463 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8464 MachinePointerInfo(SV, 8),
8466 MemOps.push_back(Store);
8468 // Store ptr to reg_save_area.
8469 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8470 FIN, DAG.getIntPtrConstant(8));
8471 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8473 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8474 MachinePointerInfo(SV, 16), false, false, 0);
8475 MemOps.push_back(Store);
8476 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8477 &MemOps[0], MemOps.size());
8480 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8481 assert(Subtarget->is64Bit() &&
8482 "LowerVAARG only handles 64-bit va_arg!");
8483 assert((Subtarget->isTargetLinux() ||
8484 Subtarget->isTargetDarwin()) &&
8485 "Unhandled target in LowerVAARG");
8486 assert(Op.getNode()->getNumOperands() == 4);
8487 SDValue Chain = Op.getOperand(0);
8488 SDValue SrcPtr = Op.getOperand(1);
8489 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8490 unsigned Align = Op.getConstantOperandVal(3);
8491 DebugLoc dl = Op.getDebugLoc();
8493 EVT ArgVT = Op.getNode()->getValueType(0);
8494 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8495 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8498 // Decide which area this value should be read from.
8499 // TODO: Implement the AMD64 ABI in its entirety. This simple
8500 // selection mechanism works only for the basic types.
8501 if (ArgVT == MVT::f80) {
8502 llvm_unreachable("va_arg for f80 not yet implemented");
8503 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8504 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8505 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8506 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8508 llvm_unreachable("Unhandled argument type in LowerVAARG");
8512 // Sanity Check: Make sure using fp_offset makes sense.
8513 assert(!UseSoftFloat &&
8514 !(DAG.getMachineFunction()
8515 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8516 Subtarget->hasXMM());
8519 // Insert VAARG_64 node into the DAG
8520 // VAARG_64 returns two values: Variable Argument Address, Chain
8521 SmallVector<SDValue, 11> InstOps;
8522 InstOps.push_back(Chain);
8523 InstOps.push_back(SrcPtr);
8524 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8525 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8526 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8527 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8528 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8529 VTs, &InstOps[0], InstOps.size(),
8531 MachinePointerInfo(SV),
8536 Chain = VAARG.getValue(1);
8538 // Load the next argument and return it
8539 return DAG.getLoad(ArgVT, dl,
8542 MachinePointerInfo(),
8546 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
8547 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
8548 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
8549 SDValue Chain = Op.getOperand(0);
8550 SDValue DstPtr = Op.getOperand(1);
8551 SDValue SrcPtr = Op.getOperand(2);
8552 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
8553 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8554 DebugLoc DL = Op.getDebugLoc();
8556 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
8557 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
8559 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
8563 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
8564 DebugLoc dl = Op.getDebugLoc();
8565 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8567 default: return SDValue(); // Don't custom lower most intrinsics.
8568 // Comparison intrinsics.
8569 case Intrinsic::x86_sse_comieq_ss:
8570 case Intrinsic::x86_sse_comilt_ss:
8571 case Intrinsic::x86_sse_comile_ss:
8572 case Intrinsic::x86_sse_comigt_ss:
8573 case Intrinsic::x86_sse_comige_ss:
8574 case Intrinsic::x86_sse_comineq_ss:
8575 case Intrinsic::x86_sse_ucomieq_ss:
8576 case Intrinsic::x86_sse_ucomilt_ss:
8577 case Intrinsic::x86_sse_ucomile_ss:
8578 case Intrinsic::x86_sse_ucomigt_ss:
8579 case Intrinsic::x86_sse_ucomige_ss:
8580 case Intrinsic::x86_sse_ucomineq_ss:
8581 case Intrinsic::x86_sse2_comieq_sd:
8582 case Intrinsic::x86_sse2_comilt_sd:
8583 case Intrinsic::x86_sse2_comile_sd:
8584 case Intrinsic::x86_sse2_comigt_sd:
8585 case Intrinsic::x86_sse2_comige_sd:
8586 case Intrinsic::x86_sse2_comineq_sd:
8587 case Intrinsic::x86_sse2_ucomieq_sd:
8588 case Intrinsic::x86_sse2_ucomilt_sd:
8589 case Intrinsic::x86_sse2_ucomile_sd:
8590 case Intrinsic::x86_sse2_ucomigt_sd:
8591 case Intrinsic::x86_sse2_ucomige_sd:
8592 case Intrinsic::x86_sse2_ucomineq_sd: {
8594 ISD::CondCode CC = ISD::SETCC_INVALID;
8597 case Intrinsic::x86_sse_comieq_ss:
8598 case Intrinsic::x86_sse2_comieq_sd:
8602 case Intrinsic::x86_sse_comilt_ss:
8603 case Intrinsic::x86_sse2_comilt_sd:
8607 case Intrinsic::x86_sse_comile_ss:
8608 case Intrinsic::x86_sse2_comile_sd:
8612 case Intrinsic::x86_sse_comigt_ss:
8613 case Intrinsic::x86_sse2_comigt_sd:
8617 case Intrinsic::x86_sse_comige_ss:
8618 case Intrinsic::x86_sse2_comige_sd:
8622 case Intrinsic::x86_sse_comineq_ss:
8623 case Intrinsic::x86_sse2_comineq_sd:
8627 case Intrinsic::x86_sse_ucomieq_ss:
8628 case Intrinsic::x86_sse2_ucomieq_sd:
8629 Opc = X86ISD::UCOMI;
8632 case Intrinsic::x86_sse_ucomilt_ss:
8633 case Intrinsic::x86_sse2_ucomilt_sd:
8634 Opc = X86ISD::UCOMI;
8637 case Intrinsic::x86_sse_ucomile_ss:
8638 case Intrinsic::x86_sse2_ucomile_sd:
8639 Opc = X86ISD::UCOMI;
8642 case Intrinsic::x86_sse_ucomigt_ss:
8643 case Intrinsic::x86_sse2_ucomigt_sd:
8644 Opc = X86ISD::UCOMI;
8647 case Intrinsic::x86_sse_ucomige_ss:
8648 case Intrinsic::x86_sse2_ucomige_sd:
8649 Opc = X86ISD::UCOMI;
8652 case Intrinsic::x86_sse_ucomineq_ss:
8653 case Intrinsic::x86_sse2_ucomineq_sd:
8654 Opc = X86ISD::UCOMI;
8659 SDValue LHS = Op.getOperand(1);
8660 SDValue RHS = Op.getOperand(2);
8661 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
8662 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
8663 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
8664 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8665 DAG.getConstant(X86CC, MVT::i8), Cond);
8666 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8668 // ptest and testp intrinsics. The intrinsic these come from are designed to
8669 // return an integer value, not just an instruction so lower it to the ptest
8670 // or testp pattern and a setcc for the result.
8671 case Intrinsic::x86_sse41_ptestz:
8672 case Intrinsic::x86_sse41_ptestc:
8673 case Intrinsic::x86_sse41_ptestnzc:
8674 case Intrinsic::x86_avx_ptestz_256:
8675 case Intrinsic::x86_avx_ptestc_256:
8676 case Intrinsic::x86_avx_ptestnzc_256:
8677 case Intrinsic::x86_avx_vtestz_ps:
8678 case Intrinsic::x86_avx_vtestc_ps:
8679 case Intrinsic::x86_avx_vtestnzc_ps:
8680 case Intrinsic::x86_avx_vtestz_pd:
8681 case Intrinsic::x86_avx_vtestc_pd:
8682 case Intrinsic::x86_avx_vtestnzc_pd:
8683 case Intrinsic::x86_avx_vtestz_ps_256:
8684 case Intrinsic::x86_avx_vtestc_ps_256:
8685 case Intrinsic::x86_avx_vtestnzc_ps_256:
8686 case Intrinsic::x86_avx_vtestz_pd_256:
8687 case Intrinsic::x86_avx_vtestc_pd_256:
8688 case Intrinsic::x86_avx_vtestnzc_pd_256: {
8689 bool IsTestPacked = false;
8692 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
8693 case Intrinsic::x86_avx_vtestz_ps:
8694 case Intrinsic::x86_avx_vtestz_pd:
8695 case Intrinsic::x86_avx_vtestz_ps_256:
8696 case Intrinsic::x86_avx_vtestz_pd_256:
8697 IsTestPacked = true; // Fallthrough
8698 case Intrinsic::x86_sse41_ptestz:
8699 case Intrinsic::x86_avx_ptestz_256:
8701 X86CC = X86::COND_E;
8703 case Intrinsic::x86_avx_vtestc_ps:
8704 case Intrinsic::x86_avx_vtestc_pd:
8705 case Intrinsic::x86_avx_vtestc_ps_256:
8706 case Intrinsic::x86_avx_vtestc_pd_256:
8707 IsTestPacked = true; // Fallthrough
8708 case Intrinsic::x86_sse41_ptestc:
8709 case Intrinsic::x86_avx_ptestc_256:
8711 X86CC = X86::COND_B;
8713 case Intrinsic::x86_avx_vtestnzc_ps:
8714 case Intrinsic::x86_avx_vtestnzc_pd:
8715 case Intrinsic::x86_avx_vtestnzc_ps_256:
8716 case Intrinsic::x86_avx_vtestnzc_pd_256:
8717 IsTestPacked = true; // Fallthrough
8718 case Intrinsic::x86_sse41_ptestnzc:
8719 case Intrinsic::x86_avx_ptestnzc_256:
8721 X86CC = X86::COND_A;
8725 SDValue LHS = Op.getOperand(1);
8726 SDValue RHS = Op.getOperand(2);
8727 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
8728 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
8729 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
8730 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
8731 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8734 // Fix vector shift instructions where the last operand is a non-immediate
8736 case Intrinsic::x86_sse2_pslli_w:
8737 case Intrinsic::x86_sse2_pslli_d:
8738 case Intrinsic::x86_sse2_pslli_q:
8739 case Intrinsic::x86_sse2_psrli_w:
8740 case Intrinsic::x86_sse2_psrli_d:
8741 case Intrinsic::x86_sse2_psrli_q:
8742 case Intrinsic::x86_sse2_psrai_w:
8743 case Intrinsic::x86_sse2_psrai_d:
8744 case Intrinsic::x86_mmx_pslli_w:
8745 case Intrinsic::x86_mmx_pslli_d:
8746 case Intrinsic::x86_mmx_pslli_q:
8747 case Intrinsic::x86_mmx_psrli_w:
8748 case Intrinsic::x86_mmx_psrli_d:
8749 case Intrinsic::x86_mmx_psrli_q:
8750 case Intrinsic::x86_mmx_psrai_w:
8751 case Intrinsic::x86_mmx_psrai_d: {
8752 SDValue ShAmt = Op.getOperand(2);
8753 if (isa<ConstantSDNode>(ShAmt))
8756 unsigned NewIntNo = 0;
8757 EVT ShAmtVT = MVT::v4i32;
8759 case Intrinsic::x86_sse2_pslli_w:
8760 NewIntNo = Intrinsic::x86_sse2_psll_w;
8762 case Intrinsic::x86_sse2_pslli_d:
8763 NewIntNo = Intrinsic::x86_sse2_psll_d;
8765 case Intrinsic::x86_sse2_pslli_q:
8766 NewIntNo = Intrinsic::x86_sse2_psll_q;
8768 case Intrinsic::x86_sse2_psrli_w:
8769 NewIntNo = Intrinsic::x86_sse2_psrl_w;
8771 case Intrinsic::x86_sse2_psrli_d:
8772 NewIntNo = Intrinsic::x86_sse2_psrl_d;
8774 case Intrinsic::x86_sse2_psrli_q:
8775 NewIntNo = Intrinsic::x86_sse2_psrl_q;
8777 case Intrinsic::x86_sse2_psrai_w:
8778 NewIntNo = Intrinsic::x86_sse2_psra_w;
8780 case Intrinsic::x86_sse2_psrai_d:
8781 NewIntNo = Intrinsic::x86_sse2_psra_d;
8784 ShAmtVT = MVT::v2i32;
8786 case Intrinsic::x86_mmx_pslli_w:
8787 NewIntNo = Intrinsic::x86_mmx_psll_w;
8789 case Intrinsic::x86_mmx_pslli_d:
8790 NewIntNo = Intrinsic::x86_mmx_psll_d;
8792 case Intrinsic::x86_mmx_pslli_q:
8793 NewIntNo = Intrinsic::x86_mmx_psll_q;
8795 case Intrinsic::x86_mmx_psrli_w:
8796 NewIntNo = Intrinsic::x86_mmx_psrl_w;
8798 case Intrinsic::x86_mmx_psrli_d:
8799 NewIntNo = Intrinsic::x86_mmx_psrl_d;
8801 case Intrinsic::x86_mmx_psrli_q:
8802 NewIntNo = Intrinsic::x86_mmx_psrl_q;
8804 case Intrinsic::x86_mmx_psrai_w:
8805 NewIntNo = Intrinsic::x86_mmx_psra_w;
8807 case Intrinsic::x86_mmx_psrai_d:
8808 NewIntNo = Intrinsic::x86_mmx_psra_d;
8810 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
8816 // The vector shift intrinsics with scalars uses 32b shift amounts but
8817 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
8821 ShOps[1] = DAG.getConstant(0, MVT::i32);
8822 if (ShAmtVT == MVT::v4i32) {
8823 ShOps[2] = DAG.getUNDEF(MVT::i32);
8824 ShOps[3] = DAG.getUNDEF(MVT::i32);
8825 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
8827 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
8828 // FIXME this must be lowered to get rid of the invalid type.
8831 EVT VT = Op.getValueType();
8832 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
8833 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8834 DAG.getConstant(NewIntNo, MVT::i32),
8835 Op.getOperand(1), ShAmt);
8840 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
8841 SelectionDAG &DAG) const {
8842 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8843 MFI->setReturnAddressIsTaken(true);
8845 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8846 DebugLoc dl = Op.getDebugLoc();
8849 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8851 DAG.getConstant(TD->getPointerSize(),
8852 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8853 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8854 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8856 MachinePointerInfo(), false, false, 0);
8859 // Just load the return address.
8860 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
8861 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8862 RetAddrFI, MachinePointerInfo(), false, false, 0);
8865 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
8866 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8867 MFI->setFrameAddressIsTaken(true);
8869 EVT VT = Op.getValueType();
8870 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
8871 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8872 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
8873 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
8875 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
8876 MachinePointerInfo(),
8881 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
8882 SelectionDAG &DAG) const {
8883 return DAG.getIntPtrConstant(2*TD->getPointerSize());
8886 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
8887 MachineFunction &MF = DAG.getMachineFunction();
8888 SDValue Chain = Op.getOperand(0);
8889 SDValue Offset = Op.getOperand(1);
8890 SDValue Handler = Op.getOperand(2);
8891 DebugLoc dl = Op.getDebugLoc();
8893 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
8894 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
8896 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
8898 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
8899 DAG.getIntPtrConstant(TD->getPointerSize()));
8900 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
8901 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
8903 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
8904 MF.getRegInfo().addLiveOut(StoreAddrReg);
8906 return DAG.getNode(X86ISD::EH_RETURN, dl,
8908 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
8911 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
8912 SelectionDAG &DAG) const {
8913 SDValue Root = Op.getOperand(0);
8914 SDValue Trmp = Op.getOperand(1); // trampoline
8915 SDValue FPtr = Op.getOperand(2); // nested function
8916 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
8917 DebugLoc dl = Op.getDebugLoc();
8919 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8921 if (Subtarget->is64Bit()) {
8922 SDValue OutChains[6];
8924 // Large code-model.
8925 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
8926 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
8928 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
8929 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
8931 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
8933 // Load the pointer to the nested function into R11.
8934 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
8935 SDValue Addr = Trmp;
8936 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8937 Addr, MachinePointerInfo(TrmpAddr),
8940 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8941 DAG.getConstant(2, MVT::i64));
8942 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8943 MachinePointerInfo(TrmpAddr, 2),
8946 // Load the 'nest' parameter value into R10.
8947 // R10 is specified in X86CallingConv.td
8948 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8949 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8950 DAG.getConstant(10, MVT::i64));
8951 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8952 Addr, MachinePointerInfo(TrmpAddr, 10),
8955 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8956 DAG.getConstant(12, MVT::i64));
8957 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8958 MachinePointerInfo(TrmpAddr, 12),
8961 // Jump to the nested function.
8962 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8963 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8964 DAG.getConstant(20, MVT::i64));
8965 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8966 Addr, MachinePointerInfo(TrmpAddr, 20),
8969 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8970 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8971 DAG.getConstant(22, MVT::i64));
8972 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8973 MachinePointerInfo(TrmpAddr, 22),
8977 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8978 return DAG.getMergeValues(Ops, 2, dl);
8980 const Function *Func =
8981 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8982 CallingConv::ID CC = Func->getCallingConv();
8987 llvm_unreachable("Unsupported calling convention");
8988 case CallingConv::C:
8989 case CallingConv::X86_StdCall: {
8990 // Pass 'nest' parameter in ECX.
8991 // Must be kept in sync with X86CallingConv.td
8994 // Check that ECX wasn't needed by an 'inreg' parameter.
8995 FunctionType *FTy = Func->getFunctionType();
8996 const AttrListPtr &Attrs = Func->getAttributes();
8998 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8999 unsigned InRegCount = 0;
9002 for (FunctionType::param_iterator I = FTy->param_begin(),
9003 E = FTy->param_end(); I != E; ++I, ++Idx)
9004 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9005 // FIXME: should only count parameters that are lowered to integers.
9006 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9008 if (InRegCount > 2) {
9009 report_fatal_error("Nest register in use - reduce number of inreg"
9015 case CallingConv::X86_FastCall:
9016 case CallingConv::X86_ThisCall:
9017 case CallingConv::Fast:
9018 // Pass 'nest' parameter in EAX.
9019 // Must be kept in sync with X86CallingConv.td
9024 SDValue OutChains[4];
9027 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9028 DAG.getConstant(10, MVT::i32));
9029 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9031 // This is storing the opcode for MOV32ri.
9032 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9033 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9034 OutChains[0] = DAG.getStore(Root, dl,
9035 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9036 Trmp, MachinePointerInfo(TrmpAddr),
9039 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9040 DAG.getConstant(1, MVT::i32));
9041 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9042 MachinePointerInfo(TrmpAddr, 1),
9045 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9046 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9047 DAG.getConstant(5, MVT::i32));
9048 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9049 MachinePointerInfo(TrmpAddr, 5),
9052 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9053 DAG.getConstant(6, MVT::i32));
9054 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9055 MachinePointerInfo(TrmpAddr, 6),
9059 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
9060 return DAG.getMergeValues(Ops, 2, dl);
9064 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9065 SelectionDAG &DAG) const {
9067 The rounding mode is in bits 11:10 of FPSR, and has the following
9074 FLT_ROUNDS, on the other hand, expects the following:
9081 To perform the conversion, we do:
9082 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9085 MachineFunction &MF = DAG.getMachineFunction();
9086 const TargetMachine &TM = MF.getTarget();
9087 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9088 unsigned StackAlignment = TFI.getStackAlignment();
9089 EVT VT = Op.getValueType();
9090 DebugLoc DL = Op.getDebugLoc();
9092 // Save FP Control Word to stack slot
9093 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9094 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9097 MachineMemOperand *MMO =
9098 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9099 MachineMemOperand::MOStore, 2, 2);
9101 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9102 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9103 DAG.getVTList(MVT::Other),
9104 Ops, 2, MVT::i16, MMO);
9106 // Load FP Control Word from stack slot
9107 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9108 MachinePointerInfo(), false, false, 0);
9110 // Transform as necessary
9112 DAG.getNode(ISD::SRL, DL, MVT::i16,
9113 DAG.getNode(ISD::AND, DL, MVT::i16,
9114 CWD, DAG.getConstant(0x800, MVT::i16)),
9115 DAG.getConstant(11, MVT::i8));
9117 DAG.getNode(ISD::SRL, DL, MVT::i16,
9118 DAG.getNode(ISD::AND, DL, MVT::i16,
9119 CWD, DAG.getConstant(0x400, MVT::i16)),
9120 DAG.getConstant(9, MVT::i8));
9123 DAG.getNode(ISD::AND, DL, MVT::i16,
9124 DAG.getNode(ISD::ADD, DL, MVT::i16,
9125 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9126 DAG.getConstant(1, MVT::i16)),
9127 DAG.getConstant(3, MVT::i16));
9130 return DAG.getNode((VT.getSizeInBits() < 16 ?
9131 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9134 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9135 EVT VT = Op.getValueType();
9137 unsigned NumBits = VT.getSizeInBits();
9138 DebugLoc dl = Op.getDebugLoc();
9140 Op = Op.getOperand(0);
9141 if (VT == MVT::i8) {
9142 // Zero extend to i32 since there is not an i8 bsr.
9144 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9147 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9148 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9149 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9151 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9154 DAG.getConstant(NumBits+NumBits-1, OpVT),
9155 DAG.getConstant(X86::COND_E, MVT::i8),
9158 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9160 // Finally xor with NumBits-1.
9161 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9164 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9168 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9169 EVT VT = Op.getValueType();
9171 unsigned NumBits = VT.getSizeInBits();
9172 DebugLoc dl = Op.getDebugLoc();
9174 Op = Op.getOperand(0);
9175 if (VT == MVT::i8) {
9177 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9180 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9181 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9182 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9184 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9187 DAG.getConstant(NumBits, OpVT),
9188 DAG.getConstant(X86::COND_E, MVT::i8),
9191 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9194 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9198 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
9199 EVT VT = Op.getValueType();
9200 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9201 DebugLoc dl = Op.getDebugLoc();
9203 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9204 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9205 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9206 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9207 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9209 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9210 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9211 // return AloBlo + AloBhi + AhiBlo;
9213 SDValue A = Op.getOperand(0);
9214 SDValue B = Op.getOperand(1);
9216 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9217 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9218 A, DAG.getConstant(32, MVT::i32));
9219 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9220 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9221 B, DAG.getConstant(32, MVT::i32));
9222 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9223 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9225 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9226 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9228 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9229 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9231 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9232 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9233 AloBhi, DAG.getConstant(32, MVT::i32));
9234 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9235 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9236 AhiBlo, DAG.getConstant(32, MVT::i32));
9237 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9238 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9242 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9244 EVT VT = Op.getValueType();
9245 DebugLoc dl = Op.getDebugLoc();
9246 SDValue R = Op.getOperand(0);
9247 SDValue Amt = Op.getOperand(1);
9248 LLVMContext *Context = DAG.getContext();
9250 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9253 // Decompose 256-bit shifts into smaller 128-bit shifts.
9254 if (VT.getSizeInBits() == 256) {
9255 int NumElems = VT.getVectorNumElements();
9256 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9257 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9259 // Extract the two vectors
9260 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9261 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9264 // Recreate the shift amount vectors
9265 SmallVector<SDValue, 4> Amt1Csts;
9266 SmallVector<SDValue, 4> Amt2Csts;
9267 for (int i = 0; i < NumElems/2; ++i)
9268 Amt1Csts.push_back(Amt->getOperand(i));
9269 for (int i = NumElems/2; i < NumElems; ++i)
9270 Amt2Csts.push_back(Amt->getOperand(i));
9272 SDValue Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9273 &Amt1Csts[0], NumElems/2);
9274 SDValue Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9275 &Amt2Csts[0], NumElems/2);
9277 // Issue new vector shifts for the smaller types
9278 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9279 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9281 // Concatenate the result back
9282 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9285 // Optimize shl/srl/sra with constant shift amount.
9286 if (isSplatVector(Amt.getNode())) {
9287 SDValue SclrAmt = Amt->getOperand(0);
9288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9289 uint64_t ShiftAmt = C->getZExtValue();
9291 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9292 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9293 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9294 R, DAG.getConstant(ShiftAmt, MVT::i32));
9296 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9297 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9298 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9299 R, DAG.getConstant(ShiftAmt, MVT::i32));
9301 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9302 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9303 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9304 R, DAG.getConstant(ShiftAmt, MVT::i32));
9306 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9307 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9308 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9309 R, DAG.getConstant(ShiftAmt, MVT::i32));
9311 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9312 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9313 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9314 R, DAG.getConstant(ShiftAmt, MVT::i32));
9316 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9317 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9318 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9319 R, DAG.getConstant(ShiftAmt, MVT::i32));
9321 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9322 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9323 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9324 R, DAG.getConstant(ShiftAmt, MVT::i32));
9326 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9327 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9328 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9329 R, DAG.getConstant(ShiftAmt, MVT::i32));
9333 // Lower SHL with variable shift amount.
9334 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9335 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9336 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9337 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9339 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9341 std::vector<Constant*> CV(4, CI);
9342 Constant *C = ConstantVector::get(CV);
9343 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9344 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9345 MachinePointerInfo::getConstantPool(),
9348 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9349 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9350 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9351 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9353 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9355 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9356 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9357 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9359 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9360 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9362 std::vector<Constant*> CVM1(16, CM1);
9363 std::vector<Constant*> CVM2(16, CM2);
9364 Constant *C = ConstantVector::get(CVM1);
9365 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9366 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9367 MachinePointerInfo::getConstantPool(),
9370 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9371 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9372 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9373 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9374 DAG.getConstant(4, MVT::i32));
9375 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9377 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9379 C = ConstantVector::get(CVM2);
9380 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9381 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9382 MachinePointerInfo::getConstantPool(),
9385 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9386 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9387 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9388 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9389 DAG.getConstant(2, MVT::i32));
9390 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9392 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9394 // return pblendv(r, r+r, a);
9395 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9396 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9402 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9403 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9404 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9405 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9406 // has only one use.
9407 SDNode *N = Op.getNode();
9408 SDValue LHS = N->getOperand(0);
9409 SDValue RHS = N->getOperand(1);
9410 unsigned BaseOp = 0;
9412 DebugLoc DL = Op.getDebugLoc();
9413 switch (Op.getOpcode()) {
9414 default: llvm_unreachable("Unknown ovf instruction!");
9416 // A subtract of one will be selected as a INC. Note that INC doesn't
9417 // set CF, so we can't do this for UADDO.
9418 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9420 BaseOp = X86ISD::INC;
9424 BaseOp = X86ISD::ADD;
9428 BaseOp = X86ISD::ADD;
9432 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9433 // set CF, so we can't do this for USUBO.
9434 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9436 BaseOp = X86ISD::DEC;
9440 BaseOp = X86ISD::SUB;
9444 BaseOp = X86ISD::SUB;
9448 BaseOp = X86ISD::SMUL;
9451 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
9452 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
9454 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
9457 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9458 DAG.getConstant(X86::COND_O, MVT::i32),
9459 SDValue(Sum.getNode(), 2));
9461 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9465 // Also sets EFLAGS.
9466 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
9467 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
9470 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9471 DAG.getConstant(Cond, MVT::i32),
9472 SDValue(Sum.getNode(), 1));
9474 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9477 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
9478 DebugLoc dl = Op.getDebugLoc();
9479 SDNode* Node = Op.getNode();
9480 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
9481 EVT VT = Node->getValueType(0);
9483 if (Subtarget->hasSSE2() && VT.isVector()) {
9484 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
9485 ExtraVT.getScalarType().getSizeInBits();
9486 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
9488 unsigned SHLIntrinsicsID = 0;
9489 unsigned SRAIntrinsicsID = 0;
9490 switch (VT.getSimpleVT().SimpleTy) {
9494 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
9495 SRAIntrinsicsID = 0;
9499 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
9500 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
9504 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
9505 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
9510 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9511 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
9512 Node->getOperand(0), ShAmt);
9514 // In case of 1 bit sext, no need to shr
9515 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
9517 if (SRAIntrinsicsID) {
9518 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9519 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
9529 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
9530 DebugLoc dl = Op.getDebugLoc();
9532 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
9533 // There isn't any reason to disable it if the target processor supports it.
9534 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
9535 SDValue Chain = Op.getOperand(0);
9536 SDValue Zero = DAG.getConstant(0, MVT::i32);
9538 DAG.getRegister(X86::ESP, MVT::i32), // Base
9539 DAG.getTargetConstant(1, MVT::i8), // Scale
9540 DAG.getRegister(0, MVT::i32), // Index
9541 DAG.getTargetConstant(0, MVT::i32), // Disp
9542 DAG.getRegister(0, MVT::i32), // Segment.
9547 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9548 array_lengthof(Ops));
9549 return SDValue(Res, 0);
9552 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
9554 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9556 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9557 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
9558 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
9559 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
9561 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
9562 if (!Op1 && !Op2 && !Op3 && Op4)
9563 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
9565 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
9566 if (Op1 && !Op2 && !Op3 && !Op4)
9567 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
9569 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
9571 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9574 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
9575 SelectionDAG &DAG) const {
9576 DebugLoc dl = Op.getDebugLoc();
9577 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
9578 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
9579 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
9580 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
9582 // The only fence that needs an instruction is a sequentially-consistent
9583 // cross-thread fence.
9584 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
9585 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
9586 // no-sse2). There isn't any reason to disable it if the target processor
9588 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
9589 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9591 SDValue Chain = Op.getOperand(0);
9592 SDValue Zero = DAG.getConstant(0, MVT::i32);
9594 DAG.getRegister(X86::ESP, MVT::i32), // Base
9595 DAG.getTargetConstant(1, MVT::i8), // Scale
9596 DAG.getRegister(0, MVT::i32), // Index
9597 DAG.getTargetConstant(0, MVT::i32), // Disp
9598 DAG.getRegister(0, MVT::i32), // Segment.
9603 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9604 array_lengthof(Ops));
9605 return SDValue(Res, 0);
9608 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
9609 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9613 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
9614 EVT T = Op.getValueType();
9615 DebugLoc DL = Op.getDebugLoc();
9618 switch(T.getSimpleVT().SimpleTy) {
9620 assert(false && "Invalid value type!");
9621 case MVT::i8: Reg = X86::AL; size = 1; break;
9622 case MVT::i16: Reg = X86::AX; size = 2; break;
9623 case MVT::i32: Reg = X86::EAX; size = 4; break;
9625 assert(Subtarget->is64Bit() && "Node not type legal!");
9626 Reg = X86::RAX; size = 8;
9629 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
9630 Op.getOperand(2), SDValue());
9631 SDValue Ops[] = { cpIn.getValue(0),
9634 DAG.getTargetConstant(size, MVT::i8),
9636 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9637 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
9638 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
9641 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
9645 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
9646 SelectionDAG &DAG) const {
9647 assert(Subtarget->is64Bit() && "Result not type legalized?");
9648 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9649 SDValue TheChain = Op.getOperand(0);
9650 DebugLoc dl = Op.getDebugLoc();
9651 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9652 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
9653 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
9655 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
9656 DAG.getConstant(32, MVT::i8));
9658 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
9661 return DAG.getMergeValues(Ops, 2, dl);
9664 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
9665 SelectionDAG &DAG) const {
9666 EVT SrcVT = Op.getOperand(0).getValueType();
9667 EVT DstVT = Op.getValueType();
9668 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
9669 Subtarget->hasMMX() && "Unexpected custom BITCAST");
9670 assert((DstVT == MVT::i64 ||
9671 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
9672 "Unexpected custom BITCAST");
9673 // i64 <=> MMX conversions are Legal.
9674 if (SrcVT==MVT::i64 && DstVT.isVector())
9676 if (DstVT==MVT::i64 && SrcVT.isVector())
9678 // MMX <=> MMX conversions are Legal.
9679 if (SrcVT.isVector() && DstVT.isVector())
9681 // All other conversions need to be expanded.
9685 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
9686 SDNode *Node = Op.getNode();
9687 DebugLoc dl = Node->getDebugLoc();
9688 EVT T = Node->getValueType(0);
9689 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
9690 DAG.getConstant(0, T), Node->getOperand(2));
9691 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
9692 cast<AtomicSDNode>(Node)->getMemoryVT(),
9693 Node->getOperand(0),
9694 Node->getOperand(1), negOp,
9695 cast<AtomicSDNode>(Node)->getSrcValue(),
9696 cast<AtomicSDNode>(Node)->getAlignment(),
9697 cast<AtomicSDNode>(Node)->getOrdering(),
9698 cast<AtomicSDNode>(Node)->getSynchScope());
9701 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
9702 EVT VT = Op.getNode()->getValueType(0);
9704 // Let legalize expand this if it isn't a legal type yet.
9705 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
9708 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9711 bool ExtraOp = false;
9712 switch (Op.getOpcode()) {
9713 default: assert(0 && "Invalid code");
9714 case ISD::ADDC: Opc = X86ISD::ADD; break;
9715 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
9716 case ISD::SUBC: Opc = X86ISD::SUB; break;
9717 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
9721 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9723 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9724 Op.getOperand(1), Op.getOperand(2));
9727 /// LowerOperation - Provide custom lowering hooks for some operations.
9729 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
9730 switch (Op.getOpcode()) {
9731 default: llvm_unreachable("Should not custom lower this!");
9732 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
9733 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
9734 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
9735 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
9736 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
9737 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
9738 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
9739 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
9740 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
9741 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
9742 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
9743 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
9744 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
9745 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
9746 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
9747 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
9748 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
9749 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
9750 case ISD::SHL_PARTS:
9751 case ISD::SRA_PARTS:
9752 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
9753 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
9754 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
9755 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
9756 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
9757 case ISD::FABS: return LowerFABS(Op, DAG);
9758 case ISD::FNEG: return LowerFNEG(Op, DAG);
9759 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
9760 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
9761 case ISD::SETCC: return LowerSETCC(Op, DAG);
9762 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
9763 case ISD::SELECT: return LowerSELECT(Op, DAG);
9764 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
9765 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
9766 case ISD::VASTART: return LowerVASTART(Op, DAG);
9767 case ISD::VAARG: return LowerVAARG(Op, DAG);
9768 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
9769 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
9770 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
9771 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
9772 case ISD::FRAME_TO_ARGS_OFFSET:
9773 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
9774 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
9775 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
9776 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
9777 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
9778 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
9779 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
9780 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
9783 case ISD::SHL: return LowerShift(Op, DAG);
9789 case ISD::UMULO: return LowerXALUO(Op, DAG);
9790 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
9791 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
9795 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
9799 void X86TargetLowering::
9800 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
9801 SelectionDAG &DAG, unsigned NewOp) const {
9802 EVT T = Node->getValueType(0);
9803 DebugLoc dl = Node->getDebugLoc();
9804 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
9806 SDValue Chain = Node->getOperand(0);
9807 SDValue In1 = Node->getOperand(1);
9808 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
9809 Node->getOperand(2), DAG.getIntPtrConstant(0));
9810 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
9811 Node->getOperand(2), DAG.getIntPtrConstant(1));
9812 SDValue Ops[] = { Chain, In1, In2L, In2H };
9813 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
9815 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
9816 cast<MemSDNode>(Node)->getMemOperand());
9817 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
9818 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
9819 Results.push_back(Result.getValue(2));
9822 /// ReplaceNodeResults - Replace a node with an illegal result type
9823 /// with a new node built out of custom code.
9824 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
9825 SmallVectorImpl<SDValue>&Results,
9826 SelectionDAG &DAG) const {
9827 DebugLoc dl = N->getDebugLoc();
9828 switch (N->getOpcode()) {
9830 assert(false && "Do not know how to custom type legalize this operation!");
9832 case ISD::SIGN_EXTEND_INREG:
9837 // We don't want to expand or promote these.
9839 case ISD::FP_TO_SINT: {
9840 std::pair<SDValue,SDValue> Vals =
9841 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
9842 SDValue FIST = Vals.first, StackSlot = Vals.second;
9843 if (FIST.getNode() != 0) {
9844 EVT VT = N->getValueType(0);
9845 // Return a load from the stack slot.
9846 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
9847 MachinePointerInfo(), false, false, 0));
9851 case ISD::READCYCLECOUNTER: {
9852 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9853 SDValue TheChain = N->getOperand(0);
9854 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9855 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
9857 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
9859 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
9860 SDValue Ops[] = { eax, edx };
9861 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
9862 Results.push_back(edx.getValue(1));
9865 case ISD::ATOMIC_CMP_SWAP: {
9866 EVT T = N->getValueType(0);
9867 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
9868 SDValue cpInL, cpInH;
9869 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
9870 DAG.getConstant(0, MVT::i32));
9871 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
9872 DAG.getConstant(1, MVT::i32));
9873 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
9874 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
9876 SDValue swapInL, swapInH;
9877 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
9878 DAG.getConstant(0, MVT::i32));
9879 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
9880 DAG.getConstant(1, MVT::i32));
9881 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
9883 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
9884 swapInL.getValue(1));
9885 SDValue Ops[] = { swapInH.getValue(0),
9887 swapInH.getValue(1) };
9888 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9889 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
9890 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
9892 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
9893 MVT::i32, Result.getValue(1));
9894 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
9895 MVT::i32, cpOutL.getValue(2));
9896 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
9897 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
9898 Results.push_back(cpOutH.getValue(1));
9901 case ISD::ATOMIC_LOAD_ADD:
9902 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
9904 case ISD::ATOMIC_LOAD_AND:
9905 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
9907 case ISD::ATOMIC_LOAD_NAND:
9908 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
9910 case ISD::ATOMIC_LOAD_OR:
9911 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
9913 case ISD::ATOMIC_LOAD_SUB:
9914 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
9916 case ISD::ATOMIC_LOAD_XOR:
9917 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
9919 case ISD::ATOMIC_SWAP:
9920 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
9925 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
9927 default: return NULL;
9928 case X86ISD::BSF: return "X86ISD::BSF";
9929 case X86ISD::BSR: return "X86ISD::BSR";
9930 case X86ISD::SHLD: return "X86ISD::SHLD";
9931 case X86ISD::SHRD: return "X86ISD::SHRD";
9932 case X86ISD::FAND: return "X86ISD::FAND";
9933 case X86ISD::FOR: return "X86ISD::FOR";
9934 case X86ISD::FXOR: return "X86ISD::FXOR";
9935 case X86ISD::FSRL: return "X86ISD::FSRL";
9936 case X86ISD::FILD: return "X86ISD::FILD";
9937 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
9938 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
9939 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
9940 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
9941 case X86ISD::FLD: return "X86ISD::FLD";
9942 case X86ISD::FST: return "X86ISD::FST";
9943 case X86ISD::CALL: return "X86ISD::CALL";
9944 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
9945 case X86ISD::BT: return "X86ISD::BT";
9946 case X86ISD::CMP: return "X86ISD::CMP";
9947 case X86ISD::COMI: return "X86ISD::COMI";
9948 case X86ISD::UCOMI: return "X86ISD::UCOMI";
9949 case X86ISD::SETCC: return "X86ISD::SETCC";
9950 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
9951 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
9952 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
9953 case X86ISD::CMOV: return "X86ISD::CMOV";
9954 case X86ISD::BRCOND: return "X86ISD::BRCOND";
9955 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
9956 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
9957 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
9958 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
9959 case X86ISD::Wrapper: return "X86ISD::Wrapper";
9960 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
9961 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
9962 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
9963 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
9964 case X86ISD::PINSRB: return "X86ISD::PINSRB";
9965 case X86ISD::PINSRW: return "X86ISD::PINSRW";
9966 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
9967 case X86ISD::ANDNP: return "X86ISD::ANDNP";
9968 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
9969 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
9970 case X86ISD::PSIGND: return "X86ISD::PSIGND";
9971 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
9972 case X86ISD::FMAX: return "X86ISD::FMAX";
9973 case X86ISD::FMIN: return "X86ISD::FMIN";
9974 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
9975 case X86ISD::FRCP: return "X86ISD::FRCP";
9976 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
9977 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
9978 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
9979 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
9980 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
9981 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
9982 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
9983 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
9984 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
9985 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
9986 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
9987 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
9988 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
9989 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
9990 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
9991 case X86ISD::VSHL: return "X86ISD::VSHL";
9992 case X86ISD::VSRL: return "X86ISD::VSRL";
9993 case X86ISD::CMPPD: return "X86ISD::CMPPD";
9994 case X86ISD::CMPPS: return "X86ISD::CMPPS";
9995 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
9996 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
9997 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
9998 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
9999 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10000 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10001 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10002 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10003 case X86ISD::ADD: return "X86ISD::ADD";
10004 case X86ISD::SUB: return "X86ISD::SUB";
10005 case X86ISD::ADC: return "X86ISD::ADC";
10006 case X86ISD::SBB: return "X86ISD::SBB";
10007 case X86ISD::SMUL: return "X86ISD::SMUL";
10008 case X86ISD::UMUL: return "X86ISD::UMUL";
10009 case X86ISD::INC: return "X86ISD::INC";
10010 case X86ISD::DEC: return "X86ISD::DEC";
10011 case X86ISD::OR: return "X86ISD::OR";
10012 case X86ISD::XOR: return "X86ISD::XOR";
10013 case X86ISD::AND: return "X86ISD::AND";
10014 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10015 case X86ISD::PTEST: return "X86ISD::PTEST";
10016 case X86ISD::TESTP: return "X86ISD::TESTP";
10017 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10018 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10019 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10020 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10021 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10022 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10023 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10024 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10025 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10026 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10027 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10028 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10029 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10030 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10031 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10032 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10033 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10034 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10035 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10036 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10037 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10038 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10039 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10040 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10041 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10042 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10043 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10044 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10045 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10046 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10047 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10048 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10049 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10050 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10051 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10052 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10053 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10054 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10055 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10056 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10057 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10058 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10062 // isLegalAddressingMode - Return true if the addressing mode represented
10063 // by AM is legal for this target, for a load/store of the specified type.
10064 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10066 // X86 supports extremely general addressing modes.
10067 CodeModel::Model M = getTargetMachine().getCodeModel();
10068 Reloc::Model R = getTargetMachine().getRelocationModel();
10070 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10071 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10076 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10078 // If a reference to this global requires an extra load, we can't fold it.
10079 if (isGlobalStubReference(GVFlags))
10082 // If BaseGV requires a register for the PIC base, we cannot also have a
10083 // BaseReg specified.
10084 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10087 // If lower 4G is not available, then we must use rip-relative addressing.
10088 if ((M != CodeModel::Small || R != Reloc::Static) &&
10089 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10093 switch (AM.Scale) {
10099 // These scales always work.
10104 // These scales are formed with basereg+scalereg. Only accept if there is
10109 default: // Other stuff never works.
10117 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10118 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10120 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10121 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10122 if (NumBits1 <= NumBits2)
10127 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10128 if (!VT1.isInteger() || !VT2.isInteger())
10130 unsigned NumBits1 = VT1.getSizeInBits();
10131 unsigned NumBits2 = VT2.getSizeInBits();
10132 if (NumBits1 <= NumBits2)
10137 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10138 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10139 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10142 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10143 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10144 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10147 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10148 // i16 instructions are longer (0x66 prefix) and potentially slower.
10149 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10152 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10153 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10154 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10155 /// are assumed to be legal.
10157 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10159 // Very little shuffling can be done for 64-bit vectors right now.
10160 if (VT.getSizeInBits() == 64)
10161 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10163 // FIXME: pshufb, blends, shifts.
10164 return (VT.getVectorNumElements() == 2 ||
10165 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10166 isMOVLMask(M, VT) ||
10167 isSHUFPMask(M, VT) ||
10168 isPSHUFDMask(M, VT) ||
10169 isPSHUFHWMask(M, VT) ||
10170 isPSHUFLWMask(M, VT) ||
10171 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10172 isUNPCKLMask(M, VT) ||
10173 isUNPCKHMask(M, VT) ||
10174 isUNPCKL_v_undef_Mask(M, VT) ||
10175 isUNPCKH_v_undef_Mask(M, VT));
10179 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10181 unsigned NumElts = VT.getVectorNumElements();
10182 // FIXME: This collection of masks seems suspect.
10185 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10186 return (isMOVLMask(Mask, VT) ||
10187 isCommutedMOVLMask(Mask, VT, true) ||
10188 isSHUFPMask(Mask, VT) ||
10189 isCommutedSHUFPMask(Mask, VT));
10194 //===----------------------------------------------------------------------===//
10195 // X86 Scheduler Hooks
10196 //===----------------------------------------------------------------------===//
10198 // private utility function
10199 MachineBasicBlock *
10200 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10201 MachineBasicBlock *MBB,
10208 TargetRegisterClass *RC,
10209 bool invSrc) const {
10210 // For the atomic bitwise operator, we generate
10213 // ld t1 = [bitinstr.addr]
10214 // op t2 = t1, [bitinstr.val]
10216 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10218 // fallthrough -->nextMBB
10219 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10220 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10221 MachineFunction::iterator MBBIter = MBB;
10224 /// First build the CFG
10225 MachineFunction *F = MBB->getParent();
10226 MachineBasicBlock *thisMBB = MBB;
10227 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10228 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10229 F->insert(MBBIter, newMBB);
10230 F->insert(MBBIter, nextMBB);
10232 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10233 nextMBB->splice(nextMBB->begin(), thisMBB,
10234 llvm::next(MachineBasicBlock::iterator(bInstr)),
10236 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10238 // Update thisMBB to fall through to newMBB
10239 thisMBB->addSuccessor(newMBB);
10241 // newMBB jumps to itself and fall through to nextMBB
10242 newMBB->addSuccessor(nextMBB);
10243 newMBB->addSuccessor(newMBB);
10245 // Insert instructions into newMBB based on incoming instruction
10246 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10247 "unexpected number of operands");
10248 DebugLoc dl = bInstr->getDebugLoc();
10249 MachineOperand& destOper = bInstr->getOperand(0);
10250 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10251 int numArgs = bInstr->getNumOperands() - 1;
10252 for (int i=0; i < numArgs; ++i)
10253 argOpers[i] = &bInstr->getOperand(i+1);
10255 // x86 address has 4 operands: base, index, scale, and displacement
10256 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10257 int valArgIndx = lastAddrIndx + 1;
10259 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10260 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10261 for (int i=0; i <= lastAddrIndx; ++i)
10262 (*MIB).addOperand(*argOpers[i]);
10264 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10266 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10271 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10272 assert((argOpers[valArgIndx]->isReg() ||
10273 argOpers[valArgIndx]->isImm()) &&
10274 "invalid operand");
10275 if (argOpers[valArgIndx]->isReg())
10276 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10278 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10280 (*MIB).addOperand(*argOpers[valArgIndx]);
10282 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10285 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10286 for (int i=0; i <= lastAddrIndx; ++i)
10287 (*MIB).addOperand(*argOpers[i]);
10289 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10290 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10291 bInstr->memoperands_end());
10293 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10294 MIB.addReg(EAXreg);
10297 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10299 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10303 // private utility function: 64 bit atomics on 32 bit host.
10304 MachineBasicBlock *
10305 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10306 MachineBasicBlock *MBB,
10311 bool invSrc) const {
10312 // For the atomic bitwise operator, we generate
10313 // thisMBB (instructions are in pairs, except cmpxchg8b)
10314 // ld t1,t2 = [bitinstr.addr]
10316 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10317 // op t5, t6 <- out1, out2, [bitinstr.val]
10318 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10319 // mov ECX, EBX <- t5, t6
10320 // mov EAX, EDX <- t1, t2
10321 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10322 // mov t3, t4 <- EAX, EDX
10324 // result in out1, out2
10325 // fallthrough -->nextMBB
10327 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10328 const unsigned LoadOpc = X86::MOV32rm;
10329 const unsigned NotOpc = X86::NOT32r;
10330 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10331 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10332 MachineFunction::iterator MBBIter = MBB;
10335 /// First build the CFG
10336 MachineFunction *F = MBB->getParent();
10337 MachineBasicBlock *thisMBB = MBB;
10338 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10339 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10340 F->insert(MBBIter, newMBB);
10341 F->insert(MBBIter, nextMBB);
10343 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10344 nextMBB->splice(nextMBB->begin(), thisMBB,
10345 llvm::next(MachineBasicBlock::iterator(bInstr)),
10347 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10349 // Update thisMBB to fall through to newMBB
10350 thisMBB->addSuccessor(newMBB);
10352 // newMBB jumps to itself and fall through to nextMBB
10353 newMBB->addSuccessor(nextMBB);
10354 newMBB->addSuccessor(newMBB);
10356 DebugLoc dl = bInstr->getDebugLoc();
10357 // Insert instructions into newMBB based on incoming instruction
10358 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10359 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10360 "unexpected number of operands");
10361 MachineOperand& dest1Oper = bInstr->getOperand(0);
10362 MachineOperand& dest2Oper = bInstr->getOperand(1);
10363 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10364 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10365 argOpers[i] = &bInstr->getOperand(i+2);
10367 // We use some of the operands multiple times, so conservatively just
10368 // clear any kill flags that might be present.
10369 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10370 argOpers[i]->setIsKill(false);
10373 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10374 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10376 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10377 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
10378 for (int i=0; i <= lastAddrIndx; ++i)
10379 (*MIB).addOperand(*argOpers[i]);
10380 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10381 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
10382 // add 4 to displacement.
10383 for (int i=0; i <= lastAddrIndx-2; ++i)
10384 (*MIB).addOperand(*argOpers[i]);
10385 MachineOperand newOp3 = *(argOpers[3]);
10386 if (newOp3.isImm())
10387 newOp3.setImm(newOp3.getImm()+4);
10389 newOp3.setOffset(newOp3.getOffset()+4);
10390 (*MIB).addOperand(newOp3);
10391 (*MIB).addOperand(*argOpers[lastAddrIndx]);
10393 // t3/4 are defined later, at the bottom of the loop
10394 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
10395 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
10396 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
10397 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
10398 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
10399 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
10401 // The subsequent operations should be using the destination registers of
10402 //the PHI instructions.
10404 t1 = F->getRegInfo().createVirtualRegister(RC);
10405 t2 = F->getRegInfo().createVirtualRegister(RC);
10406 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
10407 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
10409 t1 = dest1Oper.getReg();
10410 t2 = dest2Oper.getReg();
10413 int valArgIndx = lastAddrIndx + 1;
10414 assert((argOpers[valArgIndx]->isReg() ||
10415 argOpers[valArgIndx]->isImm()) &&
10416 "invalid operand");
10417 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
10418 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
10419 if (argOpers[valArgIndx]->isReg())
10420 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
10422 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
10423 if (regOpcL != X86::MOV32rr)
10425 (*MIB).addOperand(*argOpers[valArgIndx]);
10426 assert(argOpers[valArgIndx + 1]->isReg() ==
10427 argOpers[valArgIndx]->isReg());
10428 assert(argOpers[valArgIndx + 1]->isImm() ==
10429 argOpers[valArgIndx]->isImm());
10430 if (argOpers[valArgIndx + 1]->isReg())
10431 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
10433 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
10434 if (regOpcH != X86::MOV32rr)
10436 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
10438 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10440 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
10443 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
10445 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
10448 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
10449 for (int i=0; i <= lastAddrIndx; ++i)
10450 (*MIB).addOperand(*argOpers[i]);
10452 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10453 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10454 bInstr->memoperands_end());
10456 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
10457 MIB.addReg(X86::EAX);
10458 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
10459 MIB.addReg(X86::EDX);
10462 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10464 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10468 // private utility function
10469 MachineBasicBlock *
10470 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
10471 MachineBasicBlock *MBB,
10472 unsigned cmovOpc) const {
10473 // For the atomic min/max operator, we generate
10476 // ld t1 = [min/max.addr]
10477 // mov t2 = [min/max.val]
10479 // cmov[cond] t2 = t1
10481 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10483 // fallthrough -->nextMBB
10485 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10486 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10487 MachineFunction::iterator MBBIter = MBB;
10490 /// First build the CFG
10491 MachineFunction *F = MBB->getParent();
10492 MachineBasicBlock *thisMBB = MBB;
10493 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10494 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10495 F->insert(MBBIter, newMBB);
10496 F->insert(MBBIter, nextMBB);
10498 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10499 nextMBB->splice(nextMBB->begin(), thisMBB,
10500 llvm::next(MachineBasicBlock::iterator(mInstr)),
10502 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10504 // Update thisMBB to fall through to newMBB
10505 thisMBB->addSuccessor(newMBB);
10507 // newMBB jumps to newMBB and fall through to nextMBB
10508 newMBB->addSuccessor(nextMBB);
10509 newMBB->addSuccessor(newMBB);
10511 DebugLoc dl = mInstr->getDebugLoc();
10512 // Insert instructions into newMBB based on incoming instruction
10513 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10514 "unexpected number of operands");
10515 MachineOperand& destOper = mInstr->getOperand(0);
10516 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10517 int numArgs = mInstr->getNumOperands() - 1;
10518 for (int i=0; i < numArgs; ++i)
10519 argOpers[i] = &mInstr->getOperand(i+1);
10521 // x86 address has 4 operands: base, index, scale, and displacement
10522 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10523 int valArgIndx = lastAddrIndx + 1;
10525 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10526 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
10527 for (int i=0; i <= lastAddrIndx; ++i)
10528 (*MIB).addOperand(*argOpers[i]);
10530 // We only support register and immediate values
10531 assert((argOpers[valArgIndx]->isReg() ||
10532 argOpers[valArgIndx]->isImm()) &&
10533 "invalid operand");
10535 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10536 if (argOpers[valArgIndx]->isReg())
10537 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
10539 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
10540 (*MIB).addOperand(*argOpers[valArgIndx]);
10542 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10545 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
10550 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10551 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
10555 // Cmp and exchange if none has modified the memory location
10556 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
10557 for (int i=0; i <= lastAddrIndx; ++i)
10558 (*MIB).addOperand(*argOpers[i]);
10560 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10561 (*MIB).setMemRefs(mInstr->memoperands_begin(),
10562 mInstr->memoperands_end());
10564 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10565 MIB.addReg(X86::EAX);
10568 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10570 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
10574 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
10575 // or XMM0_V32I8 in AVX all of this code can be replaced with that
10576 // in the .td file.
10577 MachineBasicBlock *
10578 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
10579 unsigned numArgs, bool memArg) const {
10580 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
10581 "Target must have SSE4.2 or AVX features enabled");
10583 DebugLoc dl = MI->getDebugLoc();
10584 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10586 if (!Subtarget->hasAVX()) {
10588 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
10590 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
10593 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
10595 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
10598 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
10599 for (unsigned i = 0; i < numArgs; ++i) {
10600 MachineOperand &Op = MI->getOperand(i+1);
10601 if (!(Op.isReg() && Op.isImplicit()))
10602 MIB.addOperand(Op);
10604 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
10605 .addReg(X86::XMM0);
10607 MI->eraseFromParent();
10611 MachineBasicBlock *
10612 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
10613 DebugLoc dl = MI->getDebugLoc();
10614 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10616 // Address into RAX/EAX, other two args into ECX, EDX.
10617 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
10618 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10619 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
10620 for (int i = 0; i < X86::AddrNumOperands; ++i)
10621 MIB.addOperand(MI->getOperand(i));
10623 unsigned ValOps = X86::AddrNumOperands;
10624 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10625 .addReg(MI->getOperand(ValOps).getReg());
10626 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
10627 .addReg(MI->getOperand(ValOps+1).getReg());
10629 // The instruction doesn't actually take any operands though.
10630 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
10632 MI->eraseFromParent(); // The pseudo is gone now.
10636 MachineBasicBlock *
10637 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
10638 DebugLoc dl = MI->getDebugLoc();
10639 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10641 // First arg in ECX, the second in EAX.
10642 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10643 .addReg(MI->getOperand(0).getReg());
10644 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
10645 .addReg(MI->getOperand(1).getReg());
10647 // The instruction doesn't actually take any operands though.
10648 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
10650 MI->eraseFromParent(); // The pseudo is gone now.
10654 MachineBasicBlock *
10655 X86TargetLowering::EmitVAARG64WithCustomInserter(
10657 MachineBasicBlock *MBB) const {
10658 // Emit va_arg instruction on X86-64.
10660 // Operands to this pseudo-instruction:
10661 // 0 ) Output : destination address (reg)
10662 // 1-5) Input : va_list address (addr, i64mem)
10663 // 6 ) ArgSize : Size (in bytes) of vararg type
10664 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
10665 // 8 ) Align : Alignment of type
10666 // 9 ) EFLAGS (implicit-def)
10668 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
10669 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
10671 unsigned DestReg = MI->getOperand(0).getReg();
10672 MachineOperand &Base = MI->getOperand(1);
10673 MachineOperand &Scale = MI->getOperand(2);
10674 MachineOperand &Index = MI->getOperand(3);
10675 MachineOperand &Disp = MI->getOperand(4);
10676 MachineOperand &Segment = MI->getOperand(5);
10677 unsigned ArgSize = MI->getOperand(6).getImm();
10678 unsigned ArgMode = MI->getOperand(7).getImm();
10679 unsigned Align = MI->getOperand(8).getImm();
10681 // Memory Reference
10682 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
10683 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
10684 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
10686 // Machine Information
10687 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10688 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
10689 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
10690 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
10691 DebugLoc DL = MI->getDebugLoc();
10693 // struct va_list {
10696 // i64 overflow_area (address)
10697 // i64 reg_save_area (address)
10699 // sizeof(va_list) = 24
10700 // alignment(va_list) = 8
10702 unsigned TotalNumIntRegs = 6;
10703 unsigned TotalNumXMMRegs = 8;
10704 bool UseGPOffset = (ArgMode == 1);
10705 bool UseFPOffset = (ArgMode == 2);
10706 unsigned MaxOffset = TotalNumIntRegs * 8 +
10707 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
10709 /* Align ArgSize to a multiple of 8 */
10710 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
10711 bool NeedsAlign = (Align > 8);
10713 MachineBasicBlock *thisMBB = MBB;
10714 MachineBasicBlock *overflowMBB;
10715 MachineBasicBlock *offsetMBB;
10716 MachineBasicBlock *endMBB;
10718 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
10719 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
10720 unsigned OffsetReg = 0;
10722 if (!UseGPOffset && !UseFPOffset) {
10723 // If we only pull from the overflow region, we don't create a branch.
10724 // We don't need to alter control flow.
10725 OffsetDestReg = 0; // unused
10726 OverflowDestReg = DestReg;
10729 overflowMBB = thisMBB;
10732 // First emit code to check if gp_offset (or fp_offset) is below the bound.
10733 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
10734 // If not, pull from overflow_area. (branch to overflowMBB)
10739 // offsetMBB overflowMBB
10744 // Registers for the PHI in endMBB
10745 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
10746 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
10748 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10749 MachineFunction *MF = MBB->getParent();
10750 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10751 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10752 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10754 MachineFunction::iterator MBBIter = MBB;
10757 // Insert the new basic blocks
10758 MF->insert(MBBIter, offsetMBB);
10759 MF->insert(MBBIter, overflowMBB);
10760 MF->insert(MBBIter, endMBB);
10762 // Transfer the remainder of MBB and its successor edges to endMBB.
10763 endMBB->splice(endMBB->begin(), thisMBB,
10764 llvm::next(MachineBasicBlock::iterator(MI)),
10766 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10768 // Make offsetMBB and overflowMBB successors of thisMBB
10769 thisMBB->addSuccessor(offsetMBB);
10770 thisMBB->addSuccessor(overflowMBB);
10772 // endMBB is a successor of both offsetMBB and overflowMBB
10773 offsetMBB->addSuccessor(endMBB);
10774 overflowMBB->addSuccessor(endMBB);
10776 // Load the offset value into a register
10777 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
10778 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
10782 .addDisp(Disp, UseFPOffset ? 4 : 0)
10783 .addOperand(Segment)
10784 .setMemRefs(MMOBegin, MMOEnd);
10786 // Check if there is enough room left to pull this argument.
10787 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
10789 .addImm(MaxOffset + 8 - ArgSizeA8);
10791 // Branch to "overflowMBB" if offset >= max
10792 // Fall through to "offsetMBB" otherwise
10793 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
10794 .addMBB(overflowMBB);
10797 // In offsetMBB, emit code to use the reg_save_area.
10799 assert(OffsetReg != 0);
10801 // Read the reg_save_area address.
10802 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
10803 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
10808 .addOperand(Segment)
10809 .setMemRefs(MMOBegin, MMOEnd);
10811 // Zero-extend the offset
10812 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
10813 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
10816 .addImm(X86::sub_32bit);
10818 // Add the offset to the reg_save_area to get the final address.
10819 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
10820 .addReg(OffsetReg64)
10821 .addReg(RegSaveReg);
10823 // Compute the offset for the next argument
10824 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
10825 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
10827 .addImm(UseFPOffset ? 16 : 8);
10829 // Store it back into the va_list.
10830 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
10834 .addDisp(Disp, UseFPOffset ? 4 : 0)
10835 .addOperand(Segment)
10836 .addReg(NextOffsetReg)
10837 .setMemRefs(MMOBegin, MMOEnd);
10840 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
10845 // Emit code to use overflow area
10848 // Load the overflow_area address into a register.
10849 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
10850 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
10855 .addOperand(Segment)
10856 .setMemRefs(MMOBegin, MMOEnd);
10858 // If we need to align it, do so. Otherwise, just copy the address
10859 // to OverflowDestReg.
10861 // Align the overflow address
10862 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
10863 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
10865 // aligned_addr = (addr + (align-1)) & ~(align-1)
10866 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
10867 .addReg(OverflowAddrReg)
10870 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
10872 .addImm(~(uint64_t)(Align-1));
10874 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
10875 .addReg(OverflowAddrReg);
10878 // Compute the next overflow address after this argument.
10879 // (the overflow address should be kept 8-byte aligned)
10880 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
10881 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
10882 .addReg(OverflowDestReg)
10883 .addImm(ArgSizeA8);
10885 // Store the new overflow address.
10886 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
10891 .addOperand(Segment)
10892 .addReg(NextAddrReg)
10893 .setMemRefs(MMOBegin, MMOEnd);
10895 // If we branched, emit the PHI to the front of endMBB.
10897 BuildMI(*endMBB, endMBB->begin(), DL,
10898 TII->get(X86::PHI), DestReg)
10899 .addReg(OffsetDestReg).addMBB(offsetMBB)
10900 .addReg(OverflowDestReg).addMBB(overflowMBB);
10903 // Erase the pseudo instruction
10904 MI->eraseFromParent();
10909 MachineBasicBlock *
10910 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
10912 MachineBasicBlock *MBB) const {
10913 // Emit code to save XMM registers to the stack. The ABI says that the
10914 // number of registers to save is given in %al, so it's theoretically
10915 // possible to do an indirect jump trick to avoid saving all of them,
10916 // however this code takes a simpler approach and just executes all
10917 // of the stores if %al is non-zero. It's less code, and it's probably
10918 // easier on the hardware branch predictor, and stores aren't all that
10919 // expensive anyway.
10921 // Create the new basic blocks. One block contains all the XMM stores,
10922 // and one block is the final destination regardless of whether any
10923 // stores were performed.
10924 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10925 MachineFunction *F = MBB->getParent();
10926 MachineFunction::iterator MBBIter = MBB;
10928 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
10929 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
10930 F->insert(MBBIter, XMMSaveMBB);
10931 F->insert(MBBIter, EndMBB);
10933 // Transfer the remainder of MBB and its successor edges to EndMBB.
10934 EndMBB->splice(EndMBB->begin(), MBB,
10935 llvm::next(MachineBasicBlock::iterator(MI)),
10937 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
10939 // The original block will now fall through to the XMM save block.
10940 MBB->addSuccessor(XMMSaveMBB);
10941 // The XMMSaveMBB will fall through to the end block.
10942 XMMSaveMBB->addSuccessor(EndMBB);
10944 // Now add the instructions.
10945 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10946 DebugLoc DL = MI->getDebugLoc();
10948 unsigned CountReg = MI->getOperand(0).getReg();
10949 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
10950 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
10952 if (!Subtarget->isTargetWin64()) {
10953 // If %al is 0, branch around the XMM save block.
10954 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
10955 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
10956 MBB->addSuccessor(EndMBB);
10959 // In the XMM save block, save all the XMM argument registers.
10960 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
10961 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
10962 MachineMemOperand *MMO =
10963 F->getMachineMemOperand(
10964 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
10965 MachineMemOperand::MOStore,
10966 /*Size=*/16, /*Align=*/16);
10967 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
10968 .addFrameIndex(RegSaveFrameIndex)
10969 .addImm(/*Scale=*/1)
10970 .addReg(/*IndexReg=*/0)
10971 .addImm(/*Disp=*/Offset)
10972 .addReg(/*Segment=*/0)
10973 .addReg(MI->getOperand(i).getReg())
10974 .addMemOperand(MMO);
10977 MI->eraseFromParent(); // The pseudo instruction is gone now.
10982 MachineBasicBlock *
10983 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
10984 MachineBasicBlock *BB) const {
10985 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10986 DebugLoc DL = MI->getDebugLoc();
10988 // To "insert" a SELECT_CC instruction, we actually have to insert the
10989 // diamond control-flow pattern. The incoming instruction knows the
10990 // destination vreg to set, the condition code register to branch on, the
10991 // true/false values to select between, and a branch opcode to use.
10992 const BasicBlock *LLVM_BB = BB->getBasicBlock();
10993 MachineFunction::iterator It = BB;
10999 // cmpTY ccX, r1, r2
11001 // fallthrough --> copy0MBB
11002 MachineBasicBlock *thisMBB = BB;
11003 MachineFunction *F = BB->getParent();
11004 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11005 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11006 F->insert(It, copy0MBB);
11007 F->insert(It, sinkMBB);
11009 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11010 // live into the sink and copy blocks.
11011 const MachineFunction *MF = BB->getParent();
11012 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
11013 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
11015 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
11016 const MachineOperand &MO = MI->getOperand(I);
11017 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
11018 unsigned Reg = MO.getReg();
11019 if (Reg != X86::EFLAGS) continue;
11020 copy0MBB->addLiveIn(Reg);
11021 sinkMBB->addLiveIn(Reg);
11024 // Transfer the remainder of BB and its successor edges to sinkMBB.
11025 sinkMBB->splice(sinkMBB->begin(), BB,
11026 llvm::next(MachineBasicBlock::iterator(MI)),
11028 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11030 // Add the true and fallthrough blocks as its successors.
11031 BB->addSuccessor(copy0MBB);
11032 BB->addSuccessor(sinkMBB);
11034 // Create the conditional branch instruction.
11036 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11037 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11040 // %FalseValue = ...
11041 // # fallthrough to sinkMBB
11042 copy0MBB->addSuccessor(sinkMBB);
11045 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11047 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11048 TII->get(X86::PHI), MI->getOperand(0).getReg())
11049 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11050 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11052 MI->eraseFromParent(); // The pseudo instruction is gone now.
11056 MachineBasicBlock *
11057 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11058 MachineBasicBlock *BB) const {
11059 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11060 DebugLoc DL = MI->getDebugLoc();
11062 assert(!Subtarget->isTargetEnvMacho());
11064 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11065 // non-trivial part is impdef of ESP.
11067 if (Subtarget->isTargetWin64()) {
11068 if (Subtarget->isTargetCygMing()) {
11069 // ___chkstk(Mingw64):
11070 // Clobbers R10, R11, RAX and EFLAGS.
11072 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11073 .addExternalSymbol("___chkstk")
11074 .addReg(X86::RAX, RegState::Implicit)
11075 .addReg(X86::RSP, RegState::Implicit)
11076 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11077 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11078 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11080 // __chkstk(MSVCRT): does not update stack pointer.
11081 // Clobbers R10, R11 and EFLAGS.
11082 // FIXME: RAX(allocated size) might be reused and not killed.
11083 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11084 .addExternalSymbol("__chkstk")
11085 .addReg(X86::RAX, RegState::Implicit)
11086 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11087 // RAX has the offset to subtracted from RSP.
11088 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11093 const char *StackProbeSymbol =
11094 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11096 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11097 .addExternalSymbol(StackProbeSymbol)
11098 .addReg(X86::EAX, RegState::Implicit)
11099 .addReg(X86::ESP, RegState::Implicit)
11100 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11101 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11102 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11105 MI->eraseFromParent(); // The pseudo instruction is gone now.
11109 MachineBasicBlock *
11110 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11111 MachineBasicBlock *BB) const {
11112 // This is pretty easy. We're taking the value that we received from
11113 // our load from the relocation, sticking it in either RDI (x86-64)
11114 // or EAX and doing an indirect call. The return value will then
11115 // be in the normal return register.
11116 const X86InstrInfo *TII
11117 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11118 DebugLoc DL = MI->getDebugLoc();
11119 MachineFunction *F = BB->getParent();
11121 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11122 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11124 if (Subtarget->is64Bit()) {
11125 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11126 TII->get(X86::MOV64rm), X86::RDI)
11128 .addImm(0).addReg(0)
11129 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11130 MI->getOperand(3).getTargetFlags())
11132 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11133 addDirectMem(MIB, X86::RDI);
11134 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11135 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11136 TII->get(X86::MOV32rm), X86::EAX)
11138 .addImm(0).addReg(0)
11139 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11140 MI->getOperand(3).getTargetFlags())
11142 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11143 addDirectMem(MIB, X86::EAX);
11145 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11146 TII->get(X86::MOV32rm), X86::EAX)
11147 .addReg(TII->getGlobalBaseReg(F))
11148 .addImm(0).addReg(0)
11149 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11150 MI->getOperand(3).getTargetFlags())
11152 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11153 addDirectMem(MIB, X86::EAX);
11156 MI->eraseFromParent(); // The pseudo instruction is gone now.
11160 MachineBasicBlock *
11161 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11162 MachineBasicBlock *BB) const {
11163 switch (MI->getOpcode()) {
11164 default: assert(false && "Unexpected instr type to insert");
11165 case X86::TAILJMPd64:
11166 case X86::TAILJMPr64:
11167 case X86::TAILJMPm64:
11168 assert(!"TAILJMP64 would not be touched here.");
11169 case X86::TCRETURNdi64:
11170 case X86::TCRETURNri64:
11171 case X86::TCRETURNmi64:
11172 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11173 // On AMD64, additional defs should be added before register allocation.
11174 if (!Subtarget->isTargetWin64()) {
11175 MI->addRegisterDefined(X86::RSI);
11176 MI->addRegisterDefined(X86::RDI);
11177 MI->addRegisterDefined(X86::XMM6);
11178 MI->addRegisterDefined(X86::XMM7);
11179 MI->addRegisterDefined(X86::XMM8);
11180 MI->addRegisterDefined(X86::XMM9);
11181 MI->addRegisterDefined(X86::XMM10);
11182 MI->addRegisterDefined(X86::XMM11);
11183 MI->addRegisterDefined(X86::XMM12);
11184 MI->addRegisterDefined(X86::XMM13);
11185 MI->addRegisterDefined(X86::XMM14);
11186 MI->addRegisterDefined(X86::XMM15);
11189 case X86::WIN_ALLOCA:
11190 return EmitLoweredWinAlloca(MI, BB);
11191 case X86::TLSCall_32:
11192 case X86::TLSCall_64:
11193 return EmitLoweredTLSCall(MI, BB);
11194 case X86::CMOV_GR8:
11195 case X86::CMOV_FR32:
11196 case X86::CMOV_FR64:
11197 case X86::CMOV_V4F32:
11198 case X86::CMOV_V2F64:
11199 case X86::CMOV_V2I64:
11200 case X86::CMOV_V8F32:
11201 case X86::CMOV_V4F64:
11202 case X86::CMOV_V4I64:
11203 case X86::CMOV_GR16:
11204 case X86::CMOV_GR32:
11205 case X86::CMOV_RFP32:
11206 case X86::CMOV_RFP64:
11207 case X86::CMOV_RFP80:
11208 return EmitLoweredSelect(MI, BB);
11210 case X86::FP32_TO_INT16_IN_MEM:
11211 case X86::FP32_TO_INT32_IN_MEM:
11212 case X86::FP32_TO_INT64_IN_MEM:
11213 case X86::FP64_TO_INT16_IN_MEM:
11214 case X86::FP64_TO_INT32_IN_MEM:
11215 case X86::FP64_TO_INT64_IN_MEM:
11216 case X86::FP80_TO_INT16_IN_MEM:
11217 case X86::FP80_TO_INT32_IN_MEM:
11218 case X86::FP80_TO_INT64_IN_MEM: {
11219 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11220 DebugLoc DL = MI->getDebugLoc();
11222 // Change the floating point control register to use "round towards zero"
11223 // mode when truncating to an integer value.
11224 MachineFunction *F = BB->getParent();
11225 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11226 addFrameReference(BuildMI(*BB, MI, DL,
11227 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11229 // Load the old value of the high byte of the control word...
11231 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11232 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11235 // Set the high part to be round to zero...
11236 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11239 // Reload the modified control word now...
11240 addFrameReference(BuildMI(*BB, MI, DL,
11241 TII->get(X86::FLDCW16m)), CWFrameIdx);
11243 // Restore the memory image of control word to original value
11244 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11247 // Get the X86 opcode to use.
11249 switch (MI->getOpcode()) {
11250 default: llvm_unreachable("illegal opcode!");
11251 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11252 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11253 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11254 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11255 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11256 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11257 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
11258 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
11259 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
11263 MachineOperand &Op = MI->getOperand(0);
11265 AM.BaseType = X86AddressMode::RegBase;
11266 AM.Base.Reg = Op.getReg();
11268 AM.BaseType = X86AddressMode::FrameIndexBase;
11269 AM.Base.FrameIndex = Op.getIndex();
11271 Op = MI->getOperand(1);
11273 AM.Scale = Op.getImm();
11274 Op = MI->getOperand(2);
11276 AM.IndexReg = Op.getImm();
11277 Op = MI->getOperand(3);
11278 if (Op.isGlobal()) {
11279 AM.GV = Op.getGlobal();
11281 AM.Disp = Op.getImm();
11283 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
11284 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
11286 // Reload the original control word now.
11287 addFrameReference(BuildMI(*BB, MI, DL,
11288 TII->get(X86::FLDCW16m)), CWFrameIdx);
11290 MI->eraseFromParent(); // The pseudo instruction is gone now.
11293 // String/text processing lowering.
11294 case X86::PCMPISTRM128REG:
11295 case X86::VPCMPISTRM128REG:
11296 return EmitPCMP(MI, BB, 3, false /* in-mem */);
11297 case X86::PCMPISTRM128MEM:
11298 case X86::VPCMPISTRM128MEM:
11299 return EmitPCMP(MI, BB, 3, true /* in-mem */);
11300 case X86::PCMPESTRM128REG:
11301 case X86::VPCMPESTRM128REG:
11302 return EmitPCMP(MI, BB, 5, false /* in mem */);
11303 case X86::PCMPESTRM128MEM:
11304 case X86::VPCMPESTRM128MEM:
11305 return EmitPCMP(MI, BB, 5, true /* in mem */);
11307 // Thread synchronization.
11309 return EmitMonitor(MI, BB);
11311 return EmitMwait(MI, BB);
11313 // Atomic Lowering.
11314 case X86::ATOMAND32:
11315 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11316 X86::AND32ri, X86::MOV32rm,
11318 X86::NOT32r, X86::EAX,
11319 X86::GR32RegisterClass);
11320 case X86::ATOMOR32:
11321 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
11322 X86::OR32ri, X86::MOV32rm,
11324 X86::NOT32r, X86::EAX,
11325 X86::GR32RegisterClass);
11326 case X86::ATOMXOR32:
11327 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
11328 X86::XOR32ri, X86::MOV32rm,
11330 X86::NOT32r, X86::EAX,
11331 X86::GR32RegisterClass);
11332 case X86::ATOMNAND32:
11333 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11334 X86::AND32ri, X86::MOV32rm,
11336 X86::NOT32r, X86::EAX,
11337 X86::GR32RegisterClass, true);
11338 case X86::ATOMMIN32:
11339 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
11340 case X86::ATOMMAX32:
11341 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
11342 case X86::ATOMUMIN32:
11343 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
11344 case X86::ATOMUMAX32:
11345 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
11347 case X86::ATOMAND16:
11348 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11349 X86::AND16ri, X86::MOV16rm,
11351 X86::NOT16r, X86::AX,
11352 X86::GR16RegisterClass);
11353 case X86::ATOMOR16:
11354 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
11355 X86::OR16ri, X86::MOV16rm,
11357 X86::NOT16r, X86::AX,
11358 X86::GR16RegisterClass);
11359 case X86::ATOMXOR16:
11360 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
11361 X86::XOR16ri, X86::MOV16rm,
11363 X86::NOT16r, X86::AX,
11364 X86::GR16RegisterClass);
11365 case X86::ATOMNAND16:
11366 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11367 X86::AND16ri, X86::MOV16rm,
11369 X86::NOT16r, X86::AX,
11370 X86::GR16RegisterClass, true);
11371 case X86::ATOMMIN16:
11372 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
11373 case X86::ATOMMAX16:
11374 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
11375 case X86::ATOMUMIN16:
11376 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
11377 case X86::ATOMUMAX16:
11378 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
11380 case X86::ATOMAND8:
11381 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11382 X86::AND8ri, X86::MOV8rm,
11384 X86::NOT8r, X86::AL,
11385 X86::GR8RegisterClass);
11387 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
11388 X86::OR8ri, X86::MOV8rm,
11390 X86::NOT8r, X86::AL,
11391 X86::GR8RegisterClass);
11392 case X86::ATOMXOR8:
11393 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
11394 X86::XOR8ri, X86::MOV8rm,
11396 X86::NOT8r, X86::AL,
11397 X86::GR8RegisterClass);
11398 case X86::ATOMNAND8:
11399 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11400 X86::AND8ri, X86::MOV8rm,
11402 X86::NOT8r, X86::AL,
11403 X86::GR8RegisterClass, true);
11404 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
11405 // This group is for 64-bit host.
11406 case X86::ATOMAND64:
11407 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11408 X86::AND64ri32, X86::MOV64rm,
11410 X86::NOT64r, X86::RAX,
11411 X86::GR64RegisterClass);
11412 case X86::ATOMOR64:
11413 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
11414 X86::OR64ri32, X86::MOV64rm,
11416 X86::NOT64r, X86::RAX,
11417 X86::GR64RegisterClass);
11418 case X86::ATOMXOR64:
11419 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
11420 X86::XOR64ri32, X86::MOV64rm,
11422 X86::NOT64r, X86::RAX,
11423 X86::GR64RegisterClass);
11424 case X86::ATOMNAND64:
11425 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11426 X86::AND64ri32, X86::MOV64rm,
11428 X86::NOT64r, X86::RAX,
11429 X86::GR64RegisterClass, true);
11430 case X86::ATOMMIN64:
11431 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
11432 case X86::ATOMMAX64:
11433 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
11434 case X86::ATOMUMIN64:
11435 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
11436 case X86::ATOMUMAX64:
11437 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
11439 // This group does 64-bit operations on a 32-bit host.
11440 case X86::ATOMAND6432:
11441 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11442 X86::AND32rr, X86::AND32rr,
11443 X86::AND32ri, X86::AND32ri,
11445 case X86::ATOMOR6432:
11446 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11447 X86::OR32rr, X86::OR32rr,
11448 X86::OR32ri, X86::OR32ri,
11450 case X86::ATOMXOR6432:
11451 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11452 X86::XOR32rr, X86::XOR32rr,
11453 X86::XOR32ri, X86::XOR32ri,
11455 case X86::ATOMNAND6432:
11456 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11457 X86::AND32rr, X86::AND32rr,
11458 X86::AND32ri, X86::AND32ri,
11460 case X86::ATOMADD6432:
11461 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11462 X86::ADD32rr, X86::ADC32rr,
11463 X86::ADD32ri, X86::ADC32ri,
11465 case X86::ATOMSUB6432:
11466 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11467 X86::SUB32rr, X86::SBB32rr,
11468 X86::SUB32ri, X86::SBB32ri,
11470 case X86::ATOMSWAP6432:
11471 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11472 X86::MOV32rr, X86::MOV32rr,
11473 X86::MOV32ri, X86::MOV32ri,
11475 case X86::VASTART_SAVE_XMM_REGS:
11476 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
11478 case X86::VAARG_64:
11479 return EmitVAARG64WithCustomInserter(MI, BB);
11483 //===----------------------------------------------------------------------===//
11484 // X86 Optimization Hooks
11485 //===----------------------------------------------------------------------===//
11487 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
11491 const SelectionDAG &DAG,
11492 unsigned Depth) const {
11493 unsigned Opc = Op.getOpcode();
11494 assert((Opc >= ISD::BUILTIN_OP_END ||
11495 Opc == ISD::INTRINSIC_WO_CHAIN ||
11496 Opc == ISD::INTRINSIC_W_CHAIN ||
11497 Opc == ISD::INTRINSIC_VOID) &&
11498 "Should use MaskedValueIsZero if you don't know whether Op"
11499 " is a target node!");
11501 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
11515 // These nodes' second result is a boolean.
11516 if (Op.getResNo() == 0)
11519 case X86ISD::SETCC:
11520 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
11521 Mask.getBitWidth() - 1);
11526 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
11527 unsigned Depth) const {
11528 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
11529 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
11530 return Op.getValueType().getScalarType().getSizeInBits();
11536 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
11537 /// node is a GlobalAddress + offset.
11538 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
11539 const GlobalValue* &GA,
11540 int64_t &Offset) const {
11541 if (N->getOpcode() == X86ISD::Wrapper) {
11542 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
11543 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
11544 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
11548 return TargetLowering::isGAPlusOffset(N, GA, Offset);
11551 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
11552 /// same as extracting the high 128-bit part of 256-bit vector and then
11553 /// inserting the result into the low part of a new 256-bit vector
11554 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
11555 EVT VT = SVOp->getValueType(0);
11556 int NumElems = VT.getVectorNumElements();
11558 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
11559 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
11560 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
11561 SVOp->getMaskElt(j) >= 0)
11567 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
11568 /// same as extracting the low 128-bit part of 256-bit vector and then
11569 /// inserting the result into the high part of a new 256-bit vector
11570 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
11571 EVT VT = SVOp->getValueType(0);
11572 int NumElems = VT.getVectorNumElements();
11574 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
11575 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
11576 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
11577 SVOp->getMaskElt(j) >= 0)
11583 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
11584 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
11585 TargetLowering::DAGCombinerInfo &DCI) {
11586 DebugLoc dl = N->getDebugLoc();
11587 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
11588 SDValue V1 = SVOp->getOperand(0);
11589 SDValue V2 = SVOp->getOperand(1);
11590 EVT VT = SVOp->getValueType(0);
11591 int NumElems = VT.getVectorNumElements();
11593 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
11594 V2.getOpcode() == ISD::CONCAT_VECTORS) {
11598 // V UNDEF BUILD_VECTOR UNDEF
11600 // CONCAT_VECTOR CONCAT_VECTOR
11603 // RESULT: V + zero extended
11605 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
11606 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
11607 V1.getOperand(1).getOpcode() != ISD::UNDEF)
11610 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
11613 // To match the shuffle mask, the first half of the mask should
11614 // be exactly the first vector, and all the rest a splat with the
11615 // first element of the second one.
11616 for (int i = 0; i < NumElems/2; ++i)
11617 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
11618 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
11621 // Emit a zeroed vector and insert the desired subvector on its
11623 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
11624 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
11625 DAG.getConstant(0, MVT::i32), DAG, dl);
11626 return DCI.CombineTo(N, InsV);
11629 //===--------------------------------------------------------------------===//
11630 // Combine some shuffles into subvector extracts and inserts:
11633 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
11634 if (isShuffleHigh128VectorInsertLow(SVOp)) {
11635 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
11637 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
11638 V, DAG.getConstant(0, MVT::i32), DAG, dl);
11639 return DCI.CombineTo(N, InsV);
11642 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
11643 if (isShuffleLow128VectorInsertHigh(SVOp)) {
11644 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
11645 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
11646 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
11647 return DCI.CombineTo(N, InsV);
11653 /// PerformShuffleCombine - Performs several different shuffle combines.
11654 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
11655 TargetLowering::DAGCombinerInfo &DCI) {
11656 DebugLoc dl = N->getDebugLoc();
11657 EVT VT = N->getValueType(0);
11659 // Don't create instructions with illegal types after legalize types has run.
11660 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11661 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
11664 // Only handle pure VECTOR_SHUFFLE nodes.
11665 if (VT.getSizeInBits() == 256 && N->getOpcode() == ISD::VECTOR_SHUFFLE)
11666 return PerformShuffleCombine256(N, DAG, DCI);
11668 // Only handle 128 wide vector from here on.
11669 if (VT.getSizeInBits() != 128)
11672 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
11673 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
11674 // consecutive, non-overlapping, and in the right order.
11675 SmallVector<SDValue, 16> Elts;
11676 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
11677 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
11679 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
11682 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
11683 /// generation and convert it from being a bunch of shuffles and extracts
11684 /// to a simple store and scalar loads to extract the elements.
11685 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
11686 const TargetLowering &TLI) {
11687 SDValue InputVector = N->getOperand(0);
11689 // Only operate on vectors of 4 elements, where the alternative shuffling
11690 // gets to be more expensive.
11691 if (InputVector.getValueType() != MVT::v4i32)
11694 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
11695 // single use which is a sign-extend or zero-extend, and all elements are
11697 SmallVector<SDNode *, 4> Uses;
11698 unsigned ExtractedElements = 0;
11699 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
11700 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
11701 if (UI.getUse().getResNo() != InputVector.getResNo())
11704 SDNode *Extract = *UI;
11705 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11708 if (Extract->getValueType(0) != MVT::i32)
11710 if (!Extract->hasOneUse())
11712 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
11713 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
11715 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
11718 // Record which element was extracted.
11719 ExtractedElements |=
11720 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
11722 Uses.push_back(Extract);
11725 // If not all the elements were used, this may not be worthwhile.
11726 if (ExtractedElements != 15)
11729 // Ok, we've now decided to do the transformation.
11730 DebugLoc dl = InputVector.getDebugLoc();
11732 // Store the value to a temporary stack slot.
11733 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
11734 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
11735 MachinePointerInfo(), false, false, 0);
11737 // Replace each use (extract) with a load of the appropriate element.
11738 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
11739 UE = Uses.end(); UI != UE; ++UI) {
11740 SDNode *Extract = *UI;
11742 // cOMpute the element's address.
11743 SDValue Idx = Extract->getOperand(1);
11745 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
11746 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
11747 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
11749 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
11750 StackPtr, OffsetVal);
11752 // Load the scalar.
11753 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
11754 ScalarAddr, MachinePointerInfo(),
11757 // Replace the exact with the load.
11758 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
11761 // The replacement was made in place; don't return anything.
11765 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
11766 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
11767 const X86Subtarget *Subtarget) {
11768 DebugLoc DL = N->getDebugLoc();
11769 SDValue Cond = N->getOperand(0);
11770 // Get the LHS/RHS of the select.
11771 SDValue LHS = N->getOperand(1);
11772 SDValue RHS = N->getOperand(2);
11774 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
11775 // instructions match the semantics of the common C idiom x<y?x:y but not
11776 // x<=y?x:y, because of how they handle negative zero (which can be
11777 // ignored in unsafe-math mode).
11778 if (Subtarget->hasSSE2() &&
11779 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
11780 Cond.getOpcode() == ISD::SETCC) {
11781 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
11783 unsigned Opcode = 0;
11784 // Check for x CC y ? x : y.
11785 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
11786 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
11790 // Converting this to a min would handle NaNs incorrectly, and swapping
11791 // the operands would cause it to handle comparisons between positive
11792 // and negative zero incorrectly.
11793 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
11794 if (!UnsafeFPMath &&
11795 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
11797 std::swap(LHS, RHS);
11799 Opcode = X86ISD::FMIN;
11802 // Converting this to a min would handle comparisons between positive
11803 // and negative zero incorrectly.
11804 if (!UnsafeFPMath &&
11805 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
11807 Opcode = X86ISD::FMIN;
11810 // Converting this to a min would handle both negative zeros and NaNs
11811 // incorrectly, but we can swap the operands to fix both.
11812 std::swap(LHS, RHS);
11816 Opcode = X86ISD::FMIN;
11820 // Converting this to a max would handle comparisons between positive
11821 // and negative zero incorrectly.
11822 if (!UnsafeFPMath &&
11823 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
11825 Opcode = X86ISD::FMAX;
11828 // Converting this to a max would handle NaNs incorrectly, and swapping
11829 // the operands would cause it to handle comparisons between positive
11830 // and negative zero incorrectly.
11831 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
11832 if (!UnsafeFPMath &&
11833 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
11835 std::swap(LHS, RHS);
11837 Opcode = X86ISD::FMAX;
11840 // Converting this to a max would handle both negative zeros and NaNs
11841 // incorrectly, but we can swap the operands to fix both.
11842 std::swap(LHS, RHS);
11846 Opcode = X86ISD::FMAX;
11849 // Check for x CC y ? y : x -- a min/max with reversed arms.
11850 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
11851 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
11855 // Converting this to a min would handle comparisons between positive
11856 // and negative zero incorrectly, and swapping the operands would
11857 // cause it to handle NaNs incorrectly.
11858 if (!UnsafeFPMath &&
11859 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
11860 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11862 std::swap(LHS, RHS);
11864 Opcode = X86ISD::FMIN;
11867 // Converting this to a min would handle NaNs incorrectly.
11868 if (!UnsafeFPMath &&
11869 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
11871 Opcode = X86ISD::FMIN;
11874 // Converting this to a min would handle both negative zeros and NaNs
11875 // incorrectly, but we can swap the operands to fix both.
11876 std::swap(LHS, RHS);
11880 Opcode = X86ISD::FMIN;
11884 // Converting this to a max would handle NaNs incorrectly.
11885 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11887 Opcode = X86ISD::FMAX;
11890 // Converting this to a max would handle comparisons between positive
11891 // and negative zero incorrectly, and swapping the operands would
11892 // cause it to handle NaNs incorrectly.
11893 if (!UnsafeFPMath &&
11894 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
11895 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11897 std::swap(LHS, RHS);
11899 Opcode = X86ISD::FMAX;
11902 // Converting this to a max would handle both negative zeros and NaNs
11903 // incorrectly, but we can swap the operands to fix both.
11904 std::swap(LHS, RHS);
11908 Opcode = X86ISD::FMAX;
11914 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
11917 // If this is a select between two integer constants, try to do some
11919 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
11920 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
11921 // Don't do this for crazy integer types.
11922 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
11923 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
11924 // so that TrueC (the true value) is larger than FalseC.
11925 bool NeedsCondInvert = false;
11927 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
11928 // Efficiently invertible.
11929 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
11930 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
11931 isa<ConstantSDNode>(Cond.getOperand(1))))) {
11932 NeedsCondInvert = true;
11933 std::swap(TrueC, FalseC);
11936 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
11937 if (FalseC->getAPIntValue() == 0 &&
11938 TrueC->getAPIntValue().isPowerOf2()) {
11939 if (NeedsCondInvert) // Invert the condition if needed.
11940 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11941 DAG.getConstant(1, Cond.getValueType()));
11943 // Zero extend the condition if needed.
11944 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
11946 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
11947 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
11948 DAG.getConstant(ShAmt, MVT::i8));
11951 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
11952 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
11953 if (NeedsCondInvert) // Invert the condition if needed.
11954 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11955 DAG.getConstant(1, Cond.getValueType()));
11957 // Zero extend the condition if needed.
11958 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
11959 FalseC->getValueType(0), Cond);
11960 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11961 SDValue(FalseC, 0));
11964 // Optimize cases that will turn into an LEA instruction. This requires
11965 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
11966 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
11967 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
11968 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
11970 bool isFastMultiplier = false;
11972 switch ((unsigned char)Diff) {
11974 case 1: // result = add base, cond
11975 case 2: // result = lea base( , cond*2)
11976 case 3: // result = lea base(cond, cond*2)
11977 case 4: // result = lea base( , cond*4)
11978 case 5: // result = lea base(cond, cond*4)
11979 case 8: // result = lea base( , cond*8)
11980 case 9: // result = lea base(cond, cond*8)
11981 isFastMultiplier = true;
11986 if (isFastMultiplier) {
11987 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
11988 if (NeedsCondInvert) // Invert the condition if needed.
11989 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11990 DAG.getConstant(1, Cond.getValueType()));
11992 // Zero extend the condition if needed.
11993 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
11995 // Scale the condition by the difference.
11997 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
11998 DAG.getConstant(Diff, Cond.getValueType()));
12000 // Add the base if non-zero.
12001 if (FalseC->getAPIntValue() != 0)
12002 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12003 SDValue(FalseC, 0));
12013 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12014 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12015 TargetLowering::DAGCombinerInfo &DCI) {
12016 DebugLoc DL = N->getDebugLoc();
12018 // If the flag operand isn't dead, don't touch this CMOV.
12019 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12022 SDValue FalseOp = N->getOperand(0);
12023 SDValue TrueOp = N->getOperand(1);
12024 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12025 SDValue Cond = N->getOperand(3);
12026 if (CC == X86::COND_E || CC == X86::COND_NE) {
12027 switch (Cond.getOpcode()) {
12031 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12032 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12033 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12037 // If this is a select between two integer constants, try to do some
12038 // optimizations. Note that the operands are ordered the opposite of SELECT
12040 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12041 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12042 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12043 // larger than FalseC (the false value).
12044 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12045 CC = X86::GetOppositeBranchCondition(CC);
12046 std::swap(TrueC, FalseC);
12049 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12050 // This is efficient for any integer data type (including i8/i16) and
12052 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12053 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12054 DAG.getConstant(CC, MVT::i8), Cond);
12056 // Zero extend the condition if needed.
12057 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12059 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12060 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12061 DAG.getConstant(ShAmt, MVT::i8));
12062 if (N->getNumValues() == 2) // Dead flag value?
12063 return DCI.CombineTo(N, Cond, SDValue());
12067 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12068 // for any integer data type, including i8/i16.
12069 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12070 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12071 DAG.getConstant(CC, MVT::i8), Cond);
12073 // Zero extend the condition if needed.
12074 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12075 FalseC->getValueType(0), Cond);
12076 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12077 SDValue(FalseC, 0));
12079 if (N->getNumValues() == 2) // Dead flag value?
12080 return DCI.CombineTo(N, Cond, SDValue());
12084 // Optimize cases that will turn into an LEA instruction. This requires
12085 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12086 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12087 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12088 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12090 bool isFastMultiplier = false;
12092 switch ((unsigned char)Diff) {
12094 case 1: // result = add base, cond
12095 case 2: // result = lea base( , cond*2)
12096 case 3: // result = lea base(cond, cond*2)
12097 case 4: // result = lea base( , cond*4)
12098 case 5: // result = lea base(cond, cond*4)
12099 case 8: // result = lea base( , cond*8)
12100 case 9: // result = lea base(cond, cond*8)
12101 isFastMultiplier = true;
12106 if (isFastMultiplier) {
12107 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12108 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12109 DAG.getConstant(CC, MVT::i8), Cond);
12110 // Zero extend the condition if needed.
12111 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12113 // Scale the condition by the difference.
12115 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12116 DAG.getConstant(Diff, Cond.getValueType()));
12118 // Add the base if non-zero.
12119 if (FalseC->getAPIntValue() != 0)
12120 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12121 SDValue(FalseC, 0));
12122 if (N->getNumValues() == 2) // Dead flag value?
12123 return DCI.CombineTo(N, Cond, SDValue());
12133 /// PerformMulCombine - Optimize a single multiply with constant into two
12134 /// in order to implement it with two cheaper instructions, e.g.
12135 /// LEA + SHL, LEA + LEA.
12136 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12137 TargetLowering::DAGCombinerInfo &DCI) {
12138 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12141 EVT VT = N->getValueType(0);
12142 if (VT != MVT::i64)
12145 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12148 uint64_t MulAmt = C->getZExtValue();
12149 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12152 uint64_t MulAmt1 = 0;
12153 uint64_t MulAmt2 = 0;
12154 if ((MulAmt % 9) == 0) {
12156 MulAmt2 = MulAmt / 9;
12157 } else if ((MulAmt % 5) == 0) {
12159 MulAmt2 = MulAmt / 5;
12160 } else if ((MulAmt % 3) == 0) {
12162 MulAmt2 = MulAmt / 3;
12165 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12166 DebugLoc DL = N->getDebugLoc();
12168 if (isPowerOf2_64(MulAmt2) &&
12169 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12170 // If second multiplifer is pow2, issue it first. We want the multiply by
12171 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12173 std::swap(MulAmt1, MulAmt2);
12176 if (isPowerOf2_64(MulAmt1))
12177 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12178 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12180 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12181 DAG.getConstant(MulAmt1, VT));
12183 if (isPowerOf2_64(MulAmt2))
12184 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12185 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12187 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12188 DAG.getConstant(MulAmt2, VT));
12190 // Do not add new nodes to DAG combiner worklist.
12191 DCI.CombineTo(N, NewMul, false);
12196 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12197 SDValue N0 = N->getOperand(0);
12198 SDValue N1 = N->getOperand(1);
12199 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12200 EVT VT = N0.getValueType();
12202 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12203 // since the result of setcc_c is all zero's or all ones.
12204 if (N1C && N0.getOpcode() == ISD::AND &&
12205 N0.getOperand(1).getOpcode() == ISD::Constant) {
12206 SDValue N00 = N0.getOperand(0);
12207 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12208 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12209 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12210 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12211 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12212 APInt ShAmt = N1C->getAPIntValue();
12213 Mask = Mask.shl(ShAmt);
12215 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12216 N00, DAG.getConstant(Mask, VT));
12223 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12225 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12226 const X86Subtarget *Subtarget) {
12227 EVT VT = N->getValueType(0);
12228 if (!VT.isVector() && VT.isInteger() &&
12229 N->getOpcode() == ISD::SHL)
12230 return PerformSHLCombine(N, DAG);
12232 // On X86 with SSE2 support, we can transform this to a vector shift if
12233 // all elements are shifted by the same amount. We can't do this in legalize
12234 // because the a constant vector is typically transformed to a constant pool
12235 // so we have no knowledge of the shift amount.
12236 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
12239 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
12242 SDValue ShAmtOp = N->getOperand(1);
12243 EVT EltVT = VT.getVectorElementType();
12244 DebugLoc DL = N->getDebugLoc();
12245 SDValue BaseShAmt = SDValue();
12246 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
12247 unsigned NumElts = VT.getVectorNumElements();
12249 for (; i != NumElts; ++i) {
12250 SDValue Arg = ShAmtOp.getOperand(i);
12251 if (Arg.getOpcode() == ISD::UNDEF) continue;
12255 for (; i != NumElts; ++i) {
12256 SDValue Arg = ShAmtOp.getOperand(i);
12257 if (Arg.getOpcode() == ISD::UNDEF) continue;
12258 if (Arg != BaseShAmt) {
12262 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
12263 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
12264 SDValue InVec = ShAmtOp.getOperand(0);
12265 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12266 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12268 for (; i != NumElts; ++i) {
12269 SDValue Arg = InVec.getOperand(i);
12270 if (Arg.getOpcode() == ISD::UNDEF) continue;
12274 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12276 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
12277 if (C->getZExtValue() == SplatIdx)
12278 BaseShAmt = InVec.getOperand(1);
12281 if (BaseShAmt.getNode() == 0)
12282 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
12283 DAG.getIntPtrConstant(0));
12287 // The shift amount is an i32.
12288 if (EltVT.bitsGT(MVT::i32))
12289 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
12290 else if (EltVT.bitsLT(MVT::i32))
12291 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
12293 // The shift amount is identical so we can do a vector shift.
12294 SDValue ValOp = N->getOperand(0);
12295 switch (N->getOpcode()) {
12297 llvm_unreachable("Unknown shift opcode!");
12300 if (VT == MVT::v2i64)
12301 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12302 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
12304 if (VT == MVT::v4i32)
12305 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12306 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
12308 if (VT == MVT::v8i16)
12309 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12310 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
12314 if (VT == MVT::v4i32)
12315 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12316 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
12318 if (VT == MVT::v8i16)
12319 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12320 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
12324 if (VT == MVT::v2i64)
12325 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12326 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
12328 if (VT == MVT::v4i32)
12329 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12330 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
12332 if (VT == MVT::v8i16)
12333 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12334 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
12342 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12343 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
12344 // and friends. Likewise for OR -> CMPNEQSS.
12345 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
12346 TargetLowering::DAGCombinerInfo &DCI,
12347 const X86Subtarget *Subtarget) {
12350 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
12351 // we're requiring SSE2 for both.
12352 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
12353 SDValue N0 = N->getOperand(0);
12354 SDValue N1 = N->getOperand(1);
12355 SDValue CMP0 = N0->getOperand(1);
12356 SDValue CMP1 = N1->getOperand(1);
12357 DebugLoc DL = N->getDebugLoc();
12359 // The SETCCs should both refer to the same CMP.
12360 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
12363 SDValue CMP00 = CMP0->getOperand(0);
12364 SDValue CMP01 = CMP0->getOperand(1);
12365 EVT VT = CMP00.getValueType();
12367 if (VT == MVT::f32 || VT == MVT::f64) {
12368 bool ExpectingFlags = false;
12369 // Check for any users that want flags:
12370 for (SDNode::use_iterator UI = N->use_begin(),
12372 !ExpectingFlags && UI != UE; ++UI)
12373 switch (UI->getOpcode()) {
12378 ExpectingFlags = true;
12380 case ISD::CopyToReg:
12381 case ISD::SIGN_EXTEND:
12382 case ISD::ZERO_EXTEND:
12383 case ISD::ANY_EXTEND:
12387 if (!ExpectingFlags) {
12388 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
12389 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
12391 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
12392 X86::CondCode tmp = cc0;
12397 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
12398 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
12399 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
12400 X86ISD::NodeType NTOperator = is64BitFP ?
12401 X86ISD::FSETCCsd : X86ISD::FSETCCss;
12402 // FIXME: need symbolic constants for these magic numbers.
12403 // See X86ATTInstPrinter.cpp:printSSECC().
12404 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
12405 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
12406 DAG.getConstant(x86cc, MVT::i8));
12407 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
12409 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
12410 DAG.getConstant(1, MVT::i32));
12411 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
12412 return OneBitOfTruth;
12420 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
12421 /// so it can be folded inside ANDNP.
12422 static bool CanFoldXORWithAllOnes(const SDNode *N) {
12423 EVT VT = N->getValueType(0);
12425 // Match direct AllOnes for 128 and 256-bit vectors
12426 if (ISD::isBuildVectorAllOnes(N))
12429 // Look through a bit convert.
12430 if (N->getOpcode() == ISD::BITCAST)
12431 N = N->getOperand(0).getNode();
12433 // Sometimes the operand may come from a insert_subvector building a 256-bit
12435 if (VT.getSizeInBits() == 256 &&
12436 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
12437 SDValue V1 = N->getOperand(0);
12438 SDValue V2 = N->getOperand(1);
12440 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
12441 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
12442 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
12443 ISD::isBuildVectorAllOnes(V2.getNode()))
12450 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
12451 TargetLowering::DAGCombinerInfo &DCI,
12452 const X86Subtarget *Subtarget) {
12453 if (DCI.isBeforeLegalizeOps())
12456 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12460 // Want to form ANDNP nodes:
12461 // 1) In the hopes of then easily combining them with OR and AND nodes
12462 // to form PBLEND/PSIGN.
12463 // 2) To match ANDN packed intrinsics
12464 EVT VT = N->getValueType(0);
12465 if (VT != MVT::v2i64 && VT != MVT::v4i64)
12468 SDValue N0 = N->getOperand(0);
12469 SDValue N1 = N->getOperand(1);
12470 DebugLoc DL = N->getDebugLoc();
12472 // Check LHS for vnot
12473 if (N0.getOpcode() == ISD::XOR &&
12474 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
12475 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
12476 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
12478 // Check RHS for vnot
12479 if (N1.getOpcode() == ISD::XOR &&
12480 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
12481 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
12482 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
12487 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
12488 TargetLowering::DAGCombinerInfo &DCI,
12489 const X86Subtarget *Subtarget) {
12490 if (DCI.isBeforeLegalizeOps())
12493 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12497 EVT VT = N->getValueType(0);
12498 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
12501 SDValue N0 = N->getOperand(0);
12502 SDValue N1 = N->getOperand(1);
12504 // look for psign/blend
12505 if (Subtarget->hasSSSE3()) {
12506 if (VT == MVT::v2i64) {
12507 // Canonicalize pandn to RHS
12508 if (N0.getOpcode() == X86ISD::ANDNP)
12510 // or (and (m, x), (pandn m, y))
12511 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
12512 SDValue Mask = N1.getOperand(0);
12513 SDValue X = N1.getOperand(1);
12515 if (N0.getOperand(0) == Mask)
12516 Y = N0.getOperand(1);
12517 if (N0.getOperand(1) == Mask)
12518 Y = N0.getOperand(0);
12520 // Check to see if the mask appeared in both the AND and ANDNP and
12524 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
12525 if (Mask.getOpcode() != ISD::BITCAST ||
12526 X.getOpcode() != ISD::BITCAST ||
12527 Y.getOpcode() != ISD::BITCAST)
12530 // Look through mask bitcast.
12531 Mask = Mask.getOperand(0);
12532 EVT MaskVT = Mask.getValueType();
12534 // Validate that the Mask operand is a vector sra node. The sra node
12535 // will be an intrinsic.
12536 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
12539 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
12540 // there is no psrai.b
12541 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
12542 case Intrinsic::x86_sse2_psrai_w:
12543 case Intrinsic::x86_sse2_psrai_d:
12545 default: return SDValue();
12548 // Check that the SRA is all signbits.
12549 SDValue SraC = Mask.getOperand(2);
12550 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
12551 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
12552 if ((SraAmt + 1) != EltBits)
12555 DebugLoc DL = N->getDebugLoc();
12557 // Now we know we at least have a plendvb with the mask val. See if
12558 // we can form a psignb/w/d.
12559 // psign = x.type == y.type == mask.type && y = sub(0, x);
12560 X = X.getOperand(0);
12561 Y = Y.getOperand(0);
12562 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
12563 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
12564 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
12567 case 8: Opc = X86ISD::PSIGNB; break;
12568 case 16: Opc = X86ISD::PSIGNW; break;
12569 case 32: Opc = X86ISD::PSIGND; break;
12573 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
12574 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
12577 // PBLENDVB only available on SSE 4.1
12578 if (!Subtarget->hasSSE41())
12581 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
12582 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
12583 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
12584 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
12585 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
12590 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
12591 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
12593 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
12595 if (!N0.hasOneUse() || !N1.hasOneUse())
12598 SDValue ShAmt0 = N0.getOperand(1);
12599 if (ShAmt0.getValueType() != MVT::i8)
12601 SDValue ShAmt1 = N1.getOperand(1);
12602 if (ShAmt1.getValueType() != MVT::i8)
12604 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
12605 ShAmt0 = ShAmt0.getOperand(0);
12606 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
12607 ShAmt1 = ShAmt1.getOperand(0);
12609 DebugLoc DL = N->getDebugLoc();
12610 unsigned Opc = X86ISD::SHLD;
12611 SDValue Op0 = N0.getOperand(0);
12612 SDValue Op1 = N1.getOperand(0);
12613 if (ShAmt0.getOpcode() == ISD::SUB) {
12614 Opc = X86ISD::SHRD;
12615 std::swap(Op0, Op1);
12616 std::swap(ShAmt0, ShAmt1);
12619 unsigned Bits = VT.getSizeInBits();
12620 if (ShAmt1.getOpcode() == ISD::SUB) {
12621 SDValue Sum = ShAmt1.getOperand(0);
12622 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
12623 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
12624 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
12625 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
12626 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
12627 return DAG.getNode(Opc, DL, VT,
12629 DAG.getNode(ISD::TRUNCATE, DL,
12632 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
12633 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
12635 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
12636 return DAG.getNode(Opc, DL, VT,
12637 N0.getOperand(0), N1.getOperand(0),
12638 DAG.getNode(ISD::TRUNCATE, DL,
12645 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
12646 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
12647 const X86Subtarget *Subtarget) {
12648 StoreSDNode *St = cast<StoreSDNode>(N);
12649 EVT VT = St->getValue().getValueType();
12650 EVT StVT = St->getMemoryVT();
12651 DebugLoc dl = St->getDebugLoc();
12652 SDValue StoredVal = St->getOperand(1);
12653 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12655 // If we are saving a concatination of two XMM registers, perform two stores.
12656 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
12657 // 128-bit ones. If in the future the cost becomes only one memory access the
12658 // first version would be better.
12659 if (VT.getSizeInBits() == 256 &&
12660 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
12661 StoredVal.getNumOperands() == 2) {
12663 SDValue Value0 = StoredVal.getOperand(0);
12664 SDValue Value1 = StoredVal.getOperand(1);
12666 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
12667 SDValue Ptr0 = St->getBasePtr();
12668 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
12670 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
12671 St->getPointerInfo(), St->isVolatile(),
12672 St->isNonTemporal(), St->getAlignment());
12673 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
12674 St->getPointerInfo(), St->isVolatile(),
12675 St->isNonTemporal(), St->getAlignment());
12676 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
12679 // Optimize trunc store (of multiple scalars) to shuffle and store.
12680 // First, pack all of the elements in one place. Next, store to memory
12681 // in fewer chunks.
12682 if (St->isTruncatingStore() && VT.isVector()) {
12683 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12684 unsigned NumElems = VT.getVectorNumElements();
12685 assert(StVT != VT && "Cannot truncate to the same type");
12686 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
12687 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
12689 // From, To sizes and ElemCount must be pow of two
12690 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
12691 // We are going to use the original vector elt for storing.
12692 // accumulated smaller vector elements must be a multiple of bigger size.
12693 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
12694 unsigned SizeRatio = FromSz / ToSz;
12696 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
12698 // Create a type on which we perform the shuffle
12699 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
12700 StVT.getScalarType(), NumElems*SizeRatio);
12702 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
12704 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
12705 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
12706 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
12708 // Can't shuffle using an illegal type
12709 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
12711 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
12712 DAG.getUNDEF(WideVec.getValueType()),
12713 ShuffleVec.data());
12714 // At this point all of the data is stored at the bottom of the
12715 // register. We now need to save it to mem.
12717 // Find the largest store unit
12718 MVT StoreType = MVT::i8;
12719 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
12720 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
12721 MVT Tp = (MVT::SimpleValueType)tp;
12722 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
12726 // Bitcast the original vector into a vector of store-size units
12727 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
12728 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
12729 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
12730 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
12731 SmallVector<SDValue, 8> Chains;
12732 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
12733 TLI.getPointerTy());
12734 SDValue Ptr = St->getBasePtr();
12736 // Perform one or more big stores into memory.
12737 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
12738 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12739 StoreType, ShuffWide,
12740 DAG.getIntPtrConstant(i));
12741 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
12742 St->getPointerInfo(), St->isVolatile(),
12743 St->isNonTemporal(), St->getAlignment());
12744 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
12745 Chains.push_back(Ch);
12748 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
12753 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
12754 // the FP state in cases where an emms may be missing.
12755 // A preferable solution to the general problem is to figure out the right
12756 // places to insert EMMS. This qualifies as a quick hack.
12758 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
12759 if (VT.getSizeInBits() != 64)
12762 const Function *F = DAG.getMachineFunction().getFunction();
12763 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
12764 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
12765 && Subtarget->hasSSE2();
12766 if ((VT.isVector() ||
12767 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
12768 isa<LoadSDNode>(St->getValue()) &&
12769 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
12770 St->getChain().hasOneUse() && !St->isVolatile()) {
12771 SDNode* LdVal = St->getValue().getNode();
12772 LoadSDNode *Ld = 0;
12773 int TokenFactorIndex = -1;
12774 SmallVector<SDValue, 8> Ops;
12775 SDNode* ChainVal = St->getChain().getNode();
12776 // Must be a store of a load. We currently handle two cases: the load
12777 // is a direct child, and it's under an intervening TokenFactor. It is
12778 // possible to dig deeper under nested TokenFactors.
12779 if (ChainVal == LdVal)
12780 Ld = cast<LoadSDNode>(St->getChain());
12781 else if (St->getValue().hasOneUse() &&
12782 ChainVal->getOpcode() == ISD::TokenFactor) {
12783 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
12784 if (ChainVal->getOperand(i).getNode() == LdVal) {
12785 TokenFactorIndex = i;
12786 Ld = cast<LoadSDNode>(St->getValue());
12788 Ops.push_back(ChainVal->getOperand(i));
12792 if (!Ld || !ISD::isNormalLoad(Ld))
12795 // If this is not the MMX case, i.e. we are just turning i64 load/store
12796 // into f64 load/store, avoid the transformation if there are multiple
12797 // uses of the loaded value.
12798 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
12801 DebugLoc LdDL = Ld->getDebugLoc();
12802 DebugLoc StDL = N->getDebugLoc();
12803 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
12804 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
12806 if (Subtarget->is64Bit() || F64IsLegal) {
12807 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
12808 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
12809 Ld->getPointerInfo(), Ld->isVolatile(),
12810 Ld->isNonTemporal(), Ld->getAlignment());
12811 SDValue NewChain = NewLd.getValue(1);
12812 if (TokenFactorIndex != -1) {
12813 Ops.push_back(NewChain);
12814 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
12817 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
12818 St->getPointerInfo(),
12819 St->isVolatile(), St->isNonTemporal(),
12820 St->getAlignment());
12823 // Otherwise, lower to two pairs of 32-bit loads / stores.
12824 SDValue LoAddr = Ld->getBasePtr();
12825 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
12826 DAG.getConstant(4, MVT::i32));
12828 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
12829 Ld->getPointerInfo(),
12830 Ld->isVolatile(), Ld->isNonTemporal(),
12831 Ld->getAlignment());
12832 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
12833 Ld->getPointerInfo().getWithOffset(4),
12834 Ld->isVolatile(), Ld->isNonTemporal(),
12835 MinAlign(Ld->getAlignment(), 4));
12837 SDValue NewChain = LoLd.getValue(1);
12838 if (TokenFactorIndex != -1) {
12839 Ops.push_back(LoLd);
12840 Ops.push_back(HiLd);
12841 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
12845 LoAddr = St->getBasePtr();
12846 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
12847 DAG.getConstant(4, MVT::i32));
12849 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
12850 St->getPointerInfo(),
12851 St->isVolatile(), St->isNonTemporal(),
12852 St->getAlignment());
12853 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
12854 St->getPointerInfo().getWithOffset(4),
12856 St->isNonTemporal(),
12857 MinAlign(St->getAlignment(), 4));
12858 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
12863 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
12864 /// X86ISD::FXOR nodes.
12865 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
12866 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
12867 // F[X]OR(0.0, x) -> x
12868 // F[X]OR(x, 0.0) -> x
12869 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
12870 if (C->getValueAPF().isPosZero())
12871 return N->getOperand(1);
12872 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
12873 if (C->getValueAPF().isPosZero())
12874 return N->getOperand(0);
12878 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
12879 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
12880 // FAND(0.0, x) -> 0.0
12881 // FAND(x, 0.0) -> 0.0
12882 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
12883 if (C->getValueAPF().isPosZero())
12884 return N->getOperand(0);
12885 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
12886 if (C->getValueAPF().isPosZero())
12887 return N->getOperand(1);
12891 static SDValue PerformBTCombine(SDNode *N,
12893 TargetLowering::DAGCombinerInfo &DCI) {
12894 // BT ignores high bits in the bit index operand.
12895 SDValue Op1 = N->getOperand(1);
12896 if (Op1.hasOneUse()) {
12897 unsigned BitWidth = Op1.getValueSizeInBits();
12898 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
12899 APInt KnownZero, KnownOne;
12900 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
12901 !DCI.isBeforeLegalizeOps());
12902 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12903 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
12904 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
12905 DCI.CommitTargetLoweringOpt(TLO);
12910 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
12911 SDValue Op = N->getOperand(0);
12912 if (Op.getOpcode() == ISD::BITCAST)
12913 Op = Op.getOperand(0);
12914 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
12915 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
12916 VT.getVectorElementType().getSizeInBits() ==
12917 OpVT.getVectorElementType().getSizeInBits()) {
12918 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
12923 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
12924 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
12925 // (and (i32 x86isd::setcc_carry), 1)
12926 // This eliminates the zext. This transformation is necessary because
12927 // ISD::SETCC is always legalized to i8.
12928 DebugLoc dl = N->getDebugLoc();
12929 SDValue N0 = N->getOperand(0);
12930 EVT VT = N->getValueType(0);
12931 if (N0.getOpcode() == ISD::AND &&
12933 N0.getOperand(0).hasOneUse()) {
12934 SDValue N00 = N0.getOperand(0);
12935 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
12937 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
12938 if (!C || C->getZExtValue() != 1)
12940 return DAG.getNode(ISD::AND, dl, VT,
12941 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
12942 N00.getOperand(0), N00.getOperand(1)),
12943 DAG.getConstant(1, VT));
12949 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
12950 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
12951 unsigned X86CC = N->getConstantOperandVal(0);
12952 SDValue EFLAG = N->getOperand(1);
12953 DebugLoc DL = N->getDebugLoc();
12955 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
12956 // a zext and produces an all-ones bit which is more useful than 0/1 in some
12958 if (X86CC == X86::COND_B)
12959 return DAG.getNode(ISD::AND, DL, MVT::i8,
12960 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
12961 DAG.getConstant(X86CC, MVT::i8), EFLAG),
12962 DAG.getConstant(1, MVT::i8));
12967 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
12968 const X86TargetLowering *XTLI) {
12969 SDValue Op0 = N->getOperand(0);
12970 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
12971 // a 32-bit target where SSE doesn't support i64->FP operations.
12972 if (Op0.getOpcode() == ISD::LOAD) {
12973 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
12974 EVT VT = Ld->getValueType(0);
12975 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
12976 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
12977 !XTLI->getSubtarget()->is64Bit() &&
12978 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12979 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
12980 Ld->getChain(), Op0, DAG);
12981 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
12988 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
12989 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
12990 X86TargetLowering::DAGCombinerInfo &DCI) {
12991 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
12992 // the result is either zero or one (depending on the input carry bit).
12993 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
12994 if (X86::isZeroNode(N->getOperand(0)) &&
12995 X86::isZeroNode(N->getOperand(1)) &&
12996 // We don't have a good way to replace an EFLAGS use, so only do this when
12998 SDValue(N, 1).use_empty()) {
12999 DebugLoc DL = N->getDebugLoc();
13000 EVT VT = N->getValueType(0);
13001 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13002 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13003 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13004 DAG.getConstant(X86::COND_B,MVT::i8),
13006 DAG.getConstant(1, VT));
13007 return DCI.CombineTo(N, Res1, CarryOut);
13013 // fold (add Y, (sete X, 0)) -> adc 0, Y
13014 // (add Y, (setne X, 0)) -> sbb -1, Y
13015 // (sub (sete X, 0), Y) -> sbb 0, Y
13016 // (sub (setne X, 0), Y) -> adc -1, Y
13017 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13018 DebugLoc DL = N->getDebugLoc();
13020 // Look through ZExts.
13021 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13022 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13025 SDValue SetCC = Ext.getOperand(0);
13026 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13029 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13030 if (CC != X86::COND_E && CC != X86::COND_NE)
13033 SDValue Cmp = SetCC.getOperand(1);
13034 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13035 !X86::isZeroNode(Cmp.getOperand(1)) ||
13036 !Cmp.getOperand(0).getValueType().isInteger())
13039 SDValue CmpOp0 = Cmp.getOperand(0);
13040 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13041 DAG.getConstant(1, CmpOp0.getValueType()));
13043 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13044 if (CC == X86::COND_NE)
13045 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13046 DL, OtherVal.getValueType(), OtherVal,
13047 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13048 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13049 DL, OtherVal.getValueType(), OtherVal,
13050 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13053 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13054 SDValue Op0 = N->getOperand(0);
13055 SDValue Op1 = N->getOperand(1);
13057 // X86 can't encode an immediate LHS of a sub. See if we can push the
13058 // negation into a preceding instruction.
13059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13060 uint64_t Op0C = C->getSExtValue();
13062 // If the RHS of the sub is a XOR with one use and a constant, invert the
13063 // immediate. Then add one to the LHS of the sub so we can turn
13064 // X-Y -> X+~Y+1, saving one register.
13065 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13066 isa<ConstantSDNode>(Op1.getOperand(1))) {
13067 uint64_t XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getSExtValue();
13068 EVT VT = Op0.getValueType();
13069 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13071 DAG.getConstant(~XorC, VT));
13072 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13073 DAG.getConstant(Op0C+1, VT));
13077 return OptimizeConditionalInDecrement(N, DAG);
13080 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13081 DAGCombinerInfo &DCI) const {
13082 SelectionDAG &DAG = DCI.DAG;
13083 switch (N->getOpcode()) {
13085 case ISD::EXTRACT_VECTOR_ELT:
13086 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13087 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13088 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13089 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13090 case ISD::SUB: return PerformSubCombine(N, DAG);
13091 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13092 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13095 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13096 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13097 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13098 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13099 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13101 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13102 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13103 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13104 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13105 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13106 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13107 case X86ISD::SHUFPS: // Handle all target specific shuffles
13108 case X86ISD::SHUFPD:
13109 case X86ISD::PALIGN:
13110 case X86ISD::PUNPCKHBW:
13111 case X86ISD::PUNPCKHWD:
13112 case X86ISD::PUNPCKHDQ:
13113 case X86ISD::PUNPCKHQDQ:
13114 case X86ISD::UNPCKHPS:
13115 case X86ISD::UNPCKHPD:
13116 case X86ISD::VUNPCKHPSY:
13117 case X86ISD::VUNPCKHPDY:
13118 case X86ISD::PUNPCKLBW:
13119 case X86ISD::PUNPCKLWD:
13120 case X86ISD::PUNPCKLDQ:
13121 case X86ISD::PUNPCKLQDQ:
13122 case X86ISD::UNPCKLPS:
13123 case X86ISD::UNPCKLPD:
13124 case X86ISD::VUNPCKLPSY:
13125 case X86ISD::VUNPCKLPDY:
13126 case X86ISD::MOVHLPS:
13127 case X86ISD::MOVLHPS:
13128 case X86ISD::PSHUFD:
13129 case X86ISD::PSHUFHW:
13130 case X86ISD::PSHUFLW:
13131 case X86ISD::MOVSS:
13132 case X86ISD::MOVSD:
13133 case X86ISD::VPERMILPS:
13134 case X86ISD::VPERMILPSY:
13135 case X86ISD::VPERMILPD:
13136 case X86ISD::VPERMILPDY:
13137 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
13143 /// isTypeDesirableForOp - Return true if the target has native support for
13144 /// the specified value type and it is 'desirable' to use the type for the
13145 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13146 /// instruction encodings are longer and some i16 instructions are slow.
13147 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13148 if (!isTypeLegal(VT))
13150 if (VT != MVT::i16)
13157 case ISD::SIGN_EXTEND:
13158 case ISD::ZERO_EXTEND:
13159 case ISD::ANY_EXTEND:
13172 /// IsDesirableToPromoteOp - This method query the target whether it is
13173 /// beneficial for dag combiner to promote the specified node. If true, it
13174 /// should return the desired promotion type by reference.
13175 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13176 EVT VT = Op.getValueType();
13177 if (VT != MVT::i16)
13180 bool Promote = false;
13181 bool Commute = false;
13182 switch (Op.getOpcode()) {
13185 LoadSDNode *LD = cast<LoadSDNode>(Op);
13186 // If the non-extending load has a single use and it's not live out, then it
13187 // might be folded.
13188 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13189 Op.hasOneUse()*/) {
13190 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13191 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13192 // The only case where we'd want to promote LOAD (rather then it being
13193 // promoted as an operand is when it's only use is liveout.
13194 if (UI->getOpcode() != ISD::CopyToReg)
13201 case ISD::SIGN_EXTEND:
13202 case ISD::ZERO_EXTEND:
13203 case ISD::ANY_EXTEND:
13208 SDValue N0 = Op.getOperand(0);
13209 // Look out for (store (shl (load), x)).
13210 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13223 SDValue N0 = Op.getOperand(0);
13224 SDValue N1 = Op.getOperand(1);
13225 if (!Commute && MayFoldLoad(N1))
13227 // Avoid disabling potential load folding opportunities.
13228 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
13230 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
13240 //===----------------------------------------------------------------------===//
13241 // X86 Inline Assembly Support
13242 //===----------------------------------------------------------------------===//
13244 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
13245 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13247 std::string AsmStr = IA->getAsmString();
13249 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
13250 SmallVector<StringRef, 4> AsmPieces;
13251 SplitString(AsmStr, AsmPieces, ";\n");
13253 switch (AsmPieces.size()) {
13254 default: return false;
13256 AsmStr = AsmPieces[0];
13258 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
13260 // FIXME: this should verify that we are targeting a 486 or better. If not,
13261 // we will turn this bswap into something that will be lowered to logical ops
13262 // instead of emitting the bswap asm. For now, we don't support 486 or lower
13263 // so don't worry about this.
13265 if (AsmPieces.size() == 2 &&
13266 (AsmPieces[0] == "bswap" ||
13267 AsmPieces[0] == "bswapq" ||
13268 AsmPieces[0] == "bswapl") &&
13269 (AsmPieces[1] == "$0" ||
13270 AsmPieces[1] == "${0:q}")) {
13271 // No need to check constraints, nothing other than the equivalent of
13272 // "=r,0" would be valid here.
13273 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13274 if (!Ty || Ty->getBitWidth() % 16 != 0)
13276 return IntrinsicLowering::LowerToByteSwap(CI);
13278 // rorw $$8, ${0:w} --> llvm.bswap.i16
13279 if (CI->getType()->isIntegerTy(16) &&
13280 AsmPieces.size() == 3 &&
13281 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
13282 AsmPieces[1] == "$$8," &&
13283 AsmPieces[2] == "${0:w}" &&
13284 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13286 const std::string &ConstraintsStr = IA->getConstraintString();
13287 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13288 std::sort(AsmPieces.begin(), AsmPieces.end());
13289 if (AsmPieces.size() == 4 &&
13290 AsmPieces[0] == "~{cc}" &&
13291 AsmPieces[1] == "~{dirflag}" &&
13292 AsmPieces[2] == "~{flags}" &&
13293 AsmPieces[3] == "~{fpsr}") {
13294 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13295 if (!Ty || Ty->getBitWidth() % 16 != 0)
13297 return IntrinsicLowering::LowerToByteSwap(CI);
13302 if (CI->getType()->isIntegerTy(32) &&
13303 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13304 SmallVector<StringRef, 4> Words;
13305 SplitString(AsmPieces[0], Words, " \t,");
13306 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13307 Words[2] == "${0:w}") {
13309 SplitString(AsmPieces[1], Words, " \t,");
13310 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
13311 Words[2] == "$0") {
13313 SplitString(AsmPieces[2], Words, " \t,");
13314 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13315 Words[2] == "${0:w}") {
13317 const std::string &ConstraintsStr = IA->getConstraintString();
13318 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13319 std::sort(AsmPieces.begin(), AsmPieces.end());
13320 if (AsmPieces.size() == 4 &&
13321 AsmPieces[0] == "~{cc}" &&
13322 AsmPieces[1] == "~{dirflag}" &&
13323 AsmPieces[2] == "~{flags}" &&
13324 AsmPieces[3] == "~{fpsr}") {
13325 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13326 if (!Ty || Ty->getBitWidth() % 16 != 0)
13328 return IntrinsicLowering::LowerToByteSwap(CI);
13335 if (CI->getType()->isIntegerTy(64)) {
13336 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
13337 if (Constraints.size() >= 2 &&
13338 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
13339 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
13340 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
13341 SmallVector<StringRef, 4> Words;
13342 SplitString(AsmPieces[0], Words, " \t");
13343 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
13345 SplitString(AsmPieces[1], Words, " \t");
13346 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
13348 SplitString(AsmPieces[2], Words, " \t,");
13349 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
13350 Words[2] == "%edx") {
13351 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13352 if (!Ty || Ty->getBitWidth() % 16 != 0)
13354 return IntrinsicLowering::LowerToByteSwap(CI);
13367 /// getConstraintType - Given a constraint letter, return the type of
13368 /// constraint it is for this target.
13369 X86TargetLowering::ConstraintType
13370 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
13371 if (Constraint.size() == 1) {
13372 switch (Constraint[0]) {
13383 return C_RegisterClass;
13407 return TargetLowering::getConstraintType(Constraint);
13410 /// Examine constraint type and operand type and determine a weight value.
13411 /// This object must already have been set up with the operand type
13412 /// and the current alternative constraint selected.
13413 TargetLowering::ConstraintWeight
13414 X86TargetLowering::getSingleConstraintMatchWeight(
13415 AsmOperandInfo &info, const char *constraint) const {
13416 ConstraintWeight weight = CW_Invalid;
13417 Value *CallOperandVal = info.CallOperandVal;
13418 // If we don't have a value, we can't do a match,
13419 // but allow it at the lowest weight.
13420 if (CallOperandVal == NULL)
13422 Type *type = CallOperandVal->getType();
13423 // Look at the constraint type.
13424 switch (*constraint) {
13426 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
13437 if (CallOperandVal->getType()->isIntegerTy())
13438 weight = CW_SpecificReg;
13443 if (type->isFloatingPointTy())
13444 weight = CW_SpecificReg;
13447 if (type->isX86_MMXTy() && Subtarget->hasMMX())
13448 weight = CW_SpecificReg;
13452 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
13453 weight = CW_Register;
13456 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
13457 if (C->getZExtValue() <= 31)
13458 weight = CW_Constant;
13462 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13463 if (C->getZExtValue() <= 63)
13464 weight = CW_Constant;
13468 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13469 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
13470 weight = CW_Constant;
13474 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13475 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
13476 weight = CW_Constant;
13480 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13481 if (C->getZExtValue() <= 3)
13482 weight = CW_Constant;
13486 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13487 if (C->getZExtValue() <= 0xff)
13488 weight = CW_Constant;
13493 if (dyn_cast<ConstantFP>(CallOperandVal)) {
13494 weight = CW_Constant;
13498 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13499 if ((C->getSExtValue() >= -0x80000000LL) &&
13500 (C->getSExtValue() <= 0x7fffffffLL))
13501 weight = CW_Constant;
13505 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13506 if (C->getZExtValue() <= 0xffffffff)
13507 weight = CW_Constant;
13514 /// LowerXConstraint - try to replace an X constraint, which matches anything,
13515 /// with another that has more specific requirements based on the type of the
13516 /// corresponding operand.
13517 const char *X86TargetLowering::
13518 LowerXConstraint(EVT ConstraintVT) const {
13519 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
13520 // 'f' like normal targets.
13521 if (ConstraintVT.isFloatingPoint()) {
13522 if (Subtarget->hasXMMInt())
13524 if (Subtarget->hasXMM())
13528 return TargetLowering::LowerXConstraint(ConstraintVT);
13531 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
13532 /// vector. If it is invalid, don't add anything to Ops.
13533 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
13534 std::string &Constraint,
13535 std::vector<SDValue>&Ops,
13536 SelectionDAG &DAG) const {
13537 SDValue Result(0, 0);
13539 // Only support length 1 constraints for now.
13540 if (Constraint.length() > 1) return;
13542 char ConstraintLetter = Constraint[0];
13543 switch (ConstraintLetter) {
13546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13547 if (C->getZExtValue() <= 31) {
13548 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13554 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13555 if (C->getZExtValue() <= 63) {
13556 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13562 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13563 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
13564 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13570 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13571 if (C->getZExtValue() <= 255) {
13572 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13578 // 32-bit signed value
13579 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13580 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13581 C->getSExtValue())) {
13582 // Widen to 64 bits here to get it sign extended.
13583 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
13586 // FIXME gcc accepts some relocatable values here too, but only in certain
13587 // memory models; it's complicated.
13592 // 32-bit unsigned value
13593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13594 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13595 C->getZExtValue())) {
13596 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13600 // FIXME gcc accepts some relocatable values here too, but only in certain
13601 // memory models; it's complicated.
13605 // Literal immediates are always ok.
13606 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
13607 // Widen to 64 bits here to get it sign extended.
13608 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
13612 // In any sort of PIC mode addresses need to be computed at runtime by
13613 // adding in a register or some sort of table lookup. These can't
13614 // be used as immediates.
13615 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
13618 // If we are in non-pic codegen mode, we allow the address of a global (with
13619 // an optional displacement) to be used with 'i'.
13620 GlobalAddressSDNode *GA = 0;
13621 int64_t Offset = 0;
13623 // Match either (GA), (GA+C), (GA+C1+C2), etc.
13625 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
13626 Offset += GA->getOffset();
13628 } else if (Op.getOpcode() == ISD::ADD) {
13629 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13630 Offset += C->getZExtValue();
13631 Op = Op.getOperand(0);
13634 } else if (Op.getOpcode() == ISD::SUB) {
13635 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13636 Offset += -C->getZExtValue();
13637 Op = Op.getOperand(0);
13642 // Otherwise, this isn't something we can handle, reject it.
13646 const GlobalValue *GV = GA->getGlobal();
13647 // If we require an extra load to get this address, as in PIC mode, we
13648 // can't accept it.
13649 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
13650 getTargetMachine())))
13653 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
13654 GA->getValueType(0), Offset);
13659 if (Result.getNode()) {
13660 Ops.push_back(Result);
13663 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
13666 std::pair<unsigned, const TargetRegisterClass*>
13667 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
13669 // First, see if this is a constraint that directly corresponds to an LLVM
13671 if (Constraint.size() == 1) {
13672 // GCC Constraint Letters
13673 switch (Constraint[0]) {
13675 // TODO: Slight differences here in allocation order and leaving
13676 // RIP in the class. Do they matter any more here than they do
13677 // in the normal allocation?
13678 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
13679 if (Subtarget->is64Bit()) {
13680 if (VT == MVT::i32 || VT == MVT::f32)
13681 return std::make_pair(0U, X86::GR32RegisterClass);
13682 else if (VT == MVT::i16)
13683 return std::make_pair(0U, X86::GR16RegisterClass);
13684 else if (VT == MVT::i8 || VT == MVT::i1)
13685 return std::make_pair(0U, X86::GR8RegisterClass);
13686 else if (VT == MVT::i64 || VT == MVT::f64)
13687 return std::make_pair(0U, X86::GR64RegisterClass);
13690 // 32-bit fallthrough
13691 case 'Q': // Q_REGS
13692 if (VT == MVT::i32 || VT == MVT::f32)
13693 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
13694 else if (VT == MVT::i16)
13695 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
13696 else if (VT == MVT::i8 || VT == MVT::i1)
13697 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
13698 else if (VT == MVT::i64)
13699 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
13701 case 'r': // GENERAL_REGS
13702 case 'l': // INDEX_REGS
13703 if (VT == MVT::i8 || VT == MVT::i1)
13704 return std::make_pair(0U, X86::GR8RegisterClass);
13705 if (VT == MVT::i16)
13706 return std::make_pair(0U, X86::GR16RegisterClass);
13707 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
13708 return std::make_pair(0U, X86::GR32RegisterClass);
13709 return std::make_pair(0U, X86::GR64RegisterClass);
13710 case 'R': // LEGACY_REGS
13711 if (VT == MVT::i8 || VT == MVT::i1)
13712 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
13713 if (VT == MVT::i16)
13714 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
13715 if (VT == MVT::i32 || !Subtarget->is64Bit())
13716 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
13717 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
13718 case 'f': // FP Stack registers.
13719 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
13720 // value to the correct fpstack register class.
13721 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
13722 return std::make_pair(0U, X86::RFP32RegisterClass);
13723 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
13724 return std::make_pair(0U, X86::RFP64RegisterClass);
13725 return std::make_pair(0U, X86::RFP80RegisterClass);
13726 case 'y': // MMX_REGS if MMX allowed.
13727 if (!Subtarget->hasMMX()) break;
13728 return std::make_pair(0U, X86::VR64RegisterClass);
13729 case 'Y': // SSE_REGS if SSE2 allowed
13730 if (!Subtarget->hasXMMInt()) break;
13732 case 'x': // SSE_REGS if SSE1 allowed
13733 if (!Subtarget->hasXMM()) break;
13735 switch (VT.getSimpleVT().SimpleTy) {
13737 // Scalar SSE types.
13740 return std::make_pair(0U, X86::FR32RegisterClass);
13743 return std::make_pair(0U, X86::FR64RegisterClass);
13751 return std::make_pair(0U, X86::VR128RegisterClass);
13757 // Use the default implementation in TargetLowering to convert the register
13758 // constraint into a member of a register class.
13759 std::pair<unsigned, const TargetRegisterClass*> Res;
13760 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
13762 // Not found as a standard register?
13763 if (Res.second == 0) {
13764 // Map st(0) -> st(7) -> ST0
13765 if (Constraint.size() == 7 && Constraint[0] == '{' &&
13766 tolower(Constraint[1]) == 's' &&
13767 tolower(Constraint[2]) == 't' &&
13768 Constraint[3] == '(' &&
13769 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
13770 Constraint[5] == ')' &&
13771 Constraint[6] == '}') {
13773 Res.first = X86::ST0+Constraint[4]-'0';
13774 Res.second = X86::RFP80RegisterClass;
13778 // GCC allows "st(0)" to be called just plain "st".
13779 if (StringRef("{st}").equals_lower(Constraint)) {
13780 Res.first = X86::ST0;
13781 Res.second = X86::RFP80RegisterClass;
13786 if (StringRef("{flags}").equals_lower(Constraint)) {
13787 Res.first = X86::EFLAGS;
13788 Res.second = X86::CCRRegisterClass;
13792 // 'A' means EAX + EDX.
13793 if (Constraint == "A") {
13794 Res.first = X86::EAX;
13795 Res.second = X86::GR32_ADRegisterClass;
13801 // Otherwise, check to see if this is a register class of the wrong value
13802 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
13803 // turn into {ax},{dx}.
13804 if (Res.second->hasType(VT))
13805 return Res; // Correct type already, nothing to do.
13807 // All of the single-register GCC register classes map their values onto
13808 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
13809 // really want an 8-bit or 32-bit register, map to the appropriate register
13810 // class and return the appropriate register.
13811 if (Res.second == X86::GR16RegisterClass) {
13812 if (VT == MVT::i8) {
13813 unsigned DestReg = 0;
13814 switch (Res.first) {
13816 case X86::AX: DestReg = X86::AL; break;
13817 case X86::DX: DestReg = X86::DL; break;
13818 case X86::CX: DestReg = X86::CL; break;
13819 case X86::BX: DestReg = X86::BL; break;
13822 Res.first = DestReg;
13823 Res.second = X86::GR8RegisterClass;
13825 } else if (VT == MVT::i32) {
13826 unsigned DestReg = 0;
13827 switch (Res.first) {
13829 case X86::AX: DestReg = X86::EAX; break;
13830 case X86::DX: DestReg = X86::EDX; break;
13831 case X86::CX: DestReg = X86::ECX; break;
13832 case X86::BX: DestReg = X86::EBX; break;
13833 case X86::SI: DestReg = X86::ESI; break;
13834 case X86::DI: DestReg = X86::EDI; break;
13835 case X86::BP: DestReg = X86::EBP; break;
13836 case X86::SP: DestReg = X86::ESP; break;
13839 Res.first = DestReg;
13840 Res.second = X86::GR32RegisterClass;
13842 } else if (VT == MVT::i64) {
13843 unsigned DestReg = 0;
13844 switch (Res.first) {
13846 case X86::AX: DestReg = X86::RAX; break;
13847 case X86::DX: DestReg = X86::RDX; break;
13848 case X86::CX: DestReg = X86::RCX; break;
13849 case X86::BX: DestReg = X86::RBX; break;
13850 case X86::SI: DestReg = X86::RSI; break;
13851 case X86::DI: DestReg = X86::RDI; break;
13852 case X86::BP: DestReg = X86::RBP; break;
13853 case X86::SP: DestReg = X86::RSP; break;
13856 Res.first = DestReg;
13857 Res.second = X86::GR64RegisterClass;
13860 } else if (Res.second == X86::FR32RegisterClass ||
13861 Res.second == X86::FR64RegisterClass ||
13862 Res.second == X86::VR128RegisterClass) {
13863 // Handle references to XMM physical registers that got mapped into the
13864 // wrong class. This can happen with constraints like {xmm0} where the
13865 // target independent register mapper will just pick the first match it can
13866 // find, ignoring the required type.
13867 if (VT == MVT::f32)
13868 Res.second = X86::FR32RegisterClass;
13869 else if (VT == MVT::f64)
13870 Res.second = X86::FR64RegisterClass;
13871 else if (X86::VR128RegisterClass->hasType(VT))
13872 Res.second = X86::VR128RegisterClass;