1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
65 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
67 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
69 return new X8664_MachoTargetObjectFile();
70 return new TargetLoweringObjectFileMachO();
73 if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
75 return new X8664_ELFTargetObjectFile(TM);
76 return new X8632_ELFTargetObjectFile(TM);
78 if (TM.getSubtarget<X86Subtarget>().isTargetCOFF())
79 return new TargetLoweringObjectFileCOFF();
80 llvm_unreachable("unknown subtarget type");
83 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
84 : TargetLowering(TM, createTLOF(TM)) {
85 Subtarget = &TM.getSubtarget<X86Subtarget>();
86 X86ScalarSSEf64 = Subtarget->hasXMMInt();
87 X86ScalarSSEf32 = Subtarget->hasXMM();
88 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
90 RegInfo = TM.getRegisterInfo();
93 // Set up the TargetLowering object.
94 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
96 // X86 is weird, it always uses i8 for shift amounts and setcc results.
97 setShiftAmountType(MVT::i8);
98 setBooleanContents(ZeroOrOneBooleanContent);
99 setSchedulingPreference(Sched::RegPressure);
100 setStackPointerRegisterToSaveRestore(X86StackPtr);
102 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
103 // Setup Windows compiler runtime calls.
104 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
105 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
106 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
107 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
108 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
109 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
110 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
111 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
114 if (Subtarget->isTargetDarwin()) {
115 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
116 setUseUnderscoreSetJmp(false);
117 setUseUnderscoreLongJmp(false);
118 } else if (Subtarget->isTargetMingw()) {
119 // MS runtime is weird: it exports _setjmp, but longjmp!
120 setUseUnderscoreSetJmp(true);
121 setUseUnderscoreLongJmp(false);
123 setUseUnderscoreSetJmp(true);
124 setUseUnderscoreLongJmp(true);
127 // Set up the register classes.
128 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
129 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
130 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
131 if (Subtarget->is64Bit())
132 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
136 // We don't accept any truncstore of integer registers.
137 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
138 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
139 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
140 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
141 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
142 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
144 // SETOEQ and SETUNE require checking two conditions.
145 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
146 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
147 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
148 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
149 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
150 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
152 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
154 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
155 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
156 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
158 if (Subtarget->is64Bit()) {
159 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
160 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
161 } else if (!UseSoftFloat) {
162 // We have an algorithm for SSE2->double, and we turn this into a
163 // 64-bit FILD followed by conditional FADD for other targets.
164 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
165 // We have an algorithm for SSE2, and we turn this into a 64-bit
166 // FILD for other targets.
167 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
170 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
172 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
176 // SSE has no i16 to fp conversion, only i32
177 if (X86ScalarSSEf32) {
178 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
179 // f32 and f64 cases are Legal, f80 case is not
180 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
183 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
186 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
187 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
190 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
191 // are Legal, f80 is custom lowered.
192 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
193 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
195 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
197 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
198 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
200 if (X86ScalarSSEf32) {
201 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
202 // f32 and f64 cases are Legal, f80 case is not
203 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
206 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
209 // Handle FP_TO_UINT by promoting the destination to a larger signed
211 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
212 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
213 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
215 if (Subtarget->is64Bit()) {
216 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
217 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
218 } else if (!UseSoftFloat) {
219 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
220 // Expand FP_TO_UINT into a select.
221 // FIXME: We would like to use a Custom expander here eventually to do
222 // the optimal thing for SSE vs. the default expansion in the legalizer.
223 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
225 // With SSE3 we can use fisttpll to convert to a signed i64; without
226 // SSE, we're stuck with a fistpll.
227 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
230 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
231 if (!X86ScalarSSEf64) {
232 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
233 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
236 // Without SSE, i64->f64 goes through memory.
237 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
241 // Scalar integer divide and remainder are lowered to use operations that
242 // produce two results, to match the available instructions. This exposes
243 // the two-result form to trivial CSE, which is able to combine x/y and x%y
244 // into a single instruction.
246 // Scalar integer multiply-high is also lowered to use two-result
247 // operations, to match the available instructions. However, plain multiply
248 // (low) operations are left as Legal, as there are single-result
249 // instructions for this in x86. Using the two-result multiply instructions
250 // when both high and low results are needed must be arranged by dagcombine.
251 for (unsigned i = 0, e = 4; i != e; ++i) {
253 setOperationAction(ISD::MULHS, VT, Expand);
254 setOperationAction(ISD::MULHU, VT, Expand);
255 setOperationAction(ISD::SDIV, VT, Expand);
256 setOperationAction(ISD::UDIV, VT, Expand);
257 setOperationAction(ISD::SREM, VT, Expand);
258 setOperationAction(ISD::UREM, VT, Expand);
260 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
261 setOperationAction(ISD::ADDC, VT, Custom);
262 setOperationAction(ISD::ADDE, VT, Custom);
263 setOperationAction(ISD::SUBC, VT, Custom);
264 setOperationAction(ISD::SUBE, VT, Custom);
267 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
268 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
269 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
270 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
271 if (Subtarget->is64Bit())
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
276 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
277 setOperationAction(ISD::FREM , MVT::f32 , Expand);
278 setOperationAction(ISD::FREM , MVT::f64 , Expand);
279 setOperationAction(ISD::FREM , MVT::f80 , Expand);
280 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
282 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
284 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
286 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
287 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
288 if (Subtarget->is64Bit()) {
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 if (Subtarget->hasPOPCNT()) {
294 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
296 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
297 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
298 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
299 if (Subtarget->is64Bit())
300 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
303 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
304 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
306 // These should be promoted to a larger select which is supported.
307 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
308 // X86 wants to expand cmov itself.
309 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
310 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
311 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
312 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
313 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
314 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
316 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
317 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
318 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
319 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
320 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
323 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
325 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
328 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
329 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
330 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
331 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
332 if (Subtarget->is64Bit())
333 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
334 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
335 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
338 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
339 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
340 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
341 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
343 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
344 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
347 if (Subtarget->is64Bit()) {
348 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
349 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
350 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
353 if (Subtarget->hasXMM())
354 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
356 // We may not have a libcall for MEMBARRIER so we should lower this.
357 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
359 // On X86 and X86-64, atomic operations are lowered to locked instructions.
360 // Locked instructions, in turn, have implicit fence semantics (all memory
361 // operations are flushed before issuing the locked instruction, and they
362 // are not buffered), so we can fold away the common pattern of
363 // fence-atomic-fence.
364 setShouldFoldAtomicFences(true);
366 // Expand certain atomics
367 for (unsigned i = 0, e = 4; i != e; ++i) {
369 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
373 if (!Subtarget->is64Bit()) {
374 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
376 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
383 // FIXME - use subtarget debug flags
384 if (!Subtarget->isTargetDarwin() &&
385 !Subtarget->isTargetELF() &&
386 !Subtarget->isTargetCygMing()) {
387 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
390 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
391 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
392 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
393 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
394 if (Subtarget->is64Bit()) {
395 setExceptionPointerRegister(X86::RAX);
396 setExceptionSelectorRegister(X86::RDX);
398 setExceptionPointerRegister(X86::EAX);
399 setExceptionSelectorRegister(X86::EDX);
401 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
402 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
404 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
406 setOperationAction(ISD::TRAP, MVT::Other, Legal);
408 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
409 setOperationAction(ISD::VASTART , MVT::Other, Custom);
410 setOperationAction(ISD::VAEND , MVT::Other, Expand);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::VAARG , MVT::Other, Custom);
413 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
415 setOperationAction(ISD::VAARG , MVT::Other, Expand);
416 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
419 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
420 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
421 if (Subtarget->is64Bit())
422 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
423 if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows())
424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
428 if (!UseSoftFloat && X86ScalarSSEf64) {
429 // f32 and f64 use SSE.
430 // Set up the FP register classes.
431 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
432 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
434 // Use ANDPD to simulate FABS.
435 setOperationAction(ISD::FABS , MVT::f64, Custom);
436 setOperationAction(ISD::FABS , MVT::f32, Custom);
438 // Use XORP to simulate FNEG.
439 setOperationAction(ISD::FNEG , MVT::f64, Custom);
440 setOperationAction(ISD::FNEG , MVT::f32, Custom);
442 // Use ANDPD and ORPD to simulate FCOPYSIGN.
443 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
444 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
446 // We don't support sin/cos/fmod
447 setOperationAction(ISD::FSIN , MVT::f64, Expand);
448 setOperationAction(ISD::FCOS , MVT::f64, Expand);
449 setOperationAction(ISD::FSIN , MVT::f32, Expand);
450 setOperationAction(ISD::FCOS , MVT::f32, Expand);
452 // Expand FP immediates into loads from the stack, except for the special
454 addLegalFPImmediate(APFloat(+0.0)); // xorpd
455 addLegalFPImmediate(APFloat(+0.0f)); // xorps
456 } else if (!UseSoftFloat && X86ScalarSSEf32) {
457 // Use SSE for f32, x87 for f64.
458 // Set up the FP register classes.
459 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
460 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
462 // Use ANDPS to simulate FABS.
463 setOperationAction(ISD::FABS , MVT::f32, Custom);
465 // Use XORP to simulate FNEG.
466 setOperationAction(ISD::FNEG , MVT::f32, Custom);
468 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
470 // Use ANDPS and ORPS to simulate FCOPYSIGN.
471 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
472 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
474 // We don't support sin/cos/fmod
475 setOperationAction(ISD::FSIN , MVT::f32, Expand);
476 setOperationAction(ISD::FCOS , MVT::f32, Expand);
478 // Special cases we handle for FP constants.
479 addLegalFPImmediate(APFloat(+0.0f)); // xorps
480 addLegalFPImmediate(APFloat(+0.0)); // FLD0
481 addLegalFPImmediate(APFloat(+1.0)); // FLD1
482 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
483 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
486 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
487 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
489 } else if (!UseSoftFloat) {
490 // f32 and f64 in x87.
491 // Set up the FP register classes.
492 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
493 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
495 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
496 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
497 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
498 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
501 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
502 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
504 addLegalFPImmediate(APFloat(+0.0)); // FLD0
505 addLegalFPImmediate(APFloat(+1.0)); // FLD1
506 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
507 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
508 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
509 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
510 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
511 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
514 // Long double always uses X87.
516 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
517 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
518 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
520 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
521 addLegalFPImmediate(TmpFlt); // FLD0
523 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
526 APFloat TmpFlt2(+1.0);
527 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
529 addLegalFPImmediate(TmpFlt2); // FLD1
530 TmpFlt2.changeSign();
531 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
535 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
536 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
540 // Always use a library call for pow.
541 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
542 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
543 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
545 setOperationAction(ISD::FLOG, MVT::f80, Expand);
546 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
547 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
548 setOperationAction(ISD::FEXP, MVT::f80, Expand);
549 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
551 // First set operation action for all vector types to either promote
552 // (for widening) or expand (for scalarization). Then we will selectively
553 // turn on ones that can be effectively codegen'd.
554 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
555 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
556 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
571 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
572 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
605 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
608 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
609 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
610 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
611 setTruncStoreAction((MVT::SimpleValueType)VT,
612 (MVT::SimpleValueType)InnerVT, Expand);
613 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
614 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
615 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
618 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
619 // with -msoft-float, disable use of MMX as well.
620 if (!UseSoftFloat && Subtarget->hasMMX()) {
621 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
622 // No operations on x86mmx supported, everything uses intrinsics.
625 // MMX-sized vectors (other than x86mmx) are expected to be expanded
626 // into smaller operations.
627 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
628 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
629 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
630 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
631 setOperationAction(ISD::AND, MVT::v8i8, Expand);
632 setOperationAction(ISD::AND, MVT::v4i16, Expand);
633 setOperationAction(ISD::AND, MVT::v2i32, Expand);
634 setOperationAction(ISD::AND, MVT::v1i64, Expand);
635 setOperationAction(ISD::OR, MVT::v8i8, Expand);
636 setOperationAction(ISD::OR, MVT::v4i16, Expand);
637 setOperationAction(ISD::OR, MVT::v2i32, Expand);
638 setOperationAction(ISD::OR, MVT::v1i64, Expand);
639 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
640 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
641 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
642 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
643 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
644 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
645 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
646 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
647 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
648 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
649 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
650 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
651 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
652 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
653 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
654 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
655 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
657 if (!UseSoftFloat && Subtarget->hasXMM()) {
658 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
660 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
661 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
662 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
663 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
664 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
665 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
666 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
668 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
669 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
670 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
671 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
674 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
675 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
677 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
678 // registers cannot be used even for integer operations.
679 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
680 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
681 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
682 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
684 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
685 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
686 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
687 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
688 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
689 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
690 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
691 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
692 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
693 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
694 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
695 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
696 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
697 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
698 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
699 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
701 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
702 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
703 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
704 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
706 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
707 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
708 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
709 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
710 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
712 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
713 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
714 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
715 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
716 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
718 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
719 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
720 EVT VT = (MVT::SimpleValueType)i;
721 // Do not attempt to custom lower non-power-of-2 vectors
722 if (!isPowerOf2_32(VT.getVectorNumElements()))
724 // Do not attempt to custom lower non-128-bit vectors
725 if (!VT.is128BitVector())
727 setOperationAction(ISD::BUILD_VECTOR,
728 VT.getSimpleVT().SimpleTy, Custom);
729 setOperationAction(ISD::VECTOR_SHUFFLE,
730 VT.getSimpleVT().SimpleTy, Custom);
731 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
732 VT.getSimpleVT().SimpleTy, Custom);
735 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
736 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
737 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
738 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
739 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
740 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
742 if (Subtarget->is64Bit()) {
743 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
744 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
747 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
748 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
749 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
752 // Do not attempt to promote non-128-bit vectors
753 if (!VT.is128BitVector())
756 setOperationAction(ISD::AND, SVT, Promote);
757 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
758 setOperationAction(ISD::OR, SVT, Promote);
759 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
760 setOperationAction(ISD::XOR, SVT, Promote);
761 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
762 setOperationAction(ISD::LOAD, SVT, Promote);
763 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
764 setOperationAction(ISD::SELECT, SVT, Promote);
765 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
768 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
770 // Custom lower v2i64 and v2f64 selects.
771 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
772 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
773 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
774 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
776 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
777 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
780 if (Subtarget->hasSSE41()) {
781 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
782 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
783 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
784 setOperationAction(ISD::FRINT, MVT::f32, Legal);
785 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
786 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
787 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
788 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
789 setOperationAction(ISD::FRINT, MVT::f64, Legal);
790 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
792 // FIXME: Do we need to handle scalar-to-vector here?
793 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
795 // Can turn SHL into an integer multiply.
796 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
797 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
799 // i8 and i16 vectors are custom , because the source register and source
800 // source memory operand types are not the same width. f32 vectors are
801 // custom since the immediate controlling the insert encodes additional
803 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
804 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
806 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
808 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
809 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
810 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
813 if (Subtarget->is64Bit()) {
814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
815 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
819 if (Subtarget->hasSSE42())
820 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
822 if (!UseSoftFloat && Subtarget->hasAVX()) {
823 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
824 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
825 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
826 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
827 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
829 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
830 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
831 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
832 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
833 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
834 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
835 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
836 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
837 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
838 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
839 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
840 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
841 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
842 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
843 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
845 // Operations to consider commented out -v16i16 v32i8
846 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
847 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
848 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
849 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
850 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
851 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
852 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
853 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
854 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
855 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
856 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
857 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
859 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
861 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
862 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
863 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
864 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
866 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
867 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
868 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
870 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
872 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
873 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
874 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
875 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
876 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
877 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
880 // Not sure we want to do this since there are no 256-bit integer
883 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
884 // This includes 256-bit vectors
885 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
886 EVT VT = (MVT::SimpleValueType)i;
888 // Do not attempt to custom lower non-power-of-2 vectors
889 if (!isPowerOf2_32(VT.getVectorNumElements()))
892 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
893 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
904 // Not sure we want to do this since there are no 256-bit integer
907 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
908 // Including 256-bit vectors
909 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
910 EVT VT = (MVT::SimpleValueType)i;
912 if (!VT.is256BitVector()) {
915 setOperationAction(ISD::AND, VT, Promote);
916 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
917 setOperationAction(ISD::OR, VT, Promote);
918 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
919 setOperationAction(ISD::XOR, VT, Promote);
920 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
921 setOperationAction(ISD::LOAD, VT, Promote);
922 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
923 setOperationAction(ISD::SELECT, VT, Promote);
924 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
927 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
931 // We want to custom lower some of our intrinsics.
932 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
935 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
936 // handle type legalization for these operations here.
938 // FIXME: We really should do custom legalization for addition and
939 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
940 // than generic legalization for 64-bit multiplication-with-overflow, though.
941 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
942 // Add/Sub/Mul with overflow operations are custom lowered.
944 setOperationAction(ISD::SADDO, VT, Custom);
945 setOperationAction(ISD::UADDO, VT, Custom);
946 setOperationAction(ISD::SSUBO, VT, Custom);
947 setOperationAction(ISD::USUBO, VT, Custom);
948 setOperationAction(ISD::SMULO, VT, Custom);
949 setOperationAction(ISD::UMULO, VT, Custom);
952 // There are no 8-bit 3-address imul/mul instructions
953 setOperationAction(ISD::SMULO, MVT::i8, Expand);
954 setOperationAction(ISD::UMULO, MVT::i8, Expand);
956 if (!Subtarget->is64Bit()) {
957 // These libcalls are not available in 32-bit.
958 setLibcallName(RTLIB::SHL_I128, 0);
959 setLibcallName(RTLIB::SRL_I128, 0);
960 setLibcallName(RTLIB::SRA_I128, 0);
963 // We have target-specific dag combine patterns for the following nodes:
964 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
965 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
966 setTargetDAGCombine(ISD::BUILD_VECTOR);
967 setTargetDAGCombine(ISD::SELECT);
968 setTargetDAGCombine(ISD::SHL);
969 setTargetDAGCombine(ISD::SRA);
970 setTargetDAGCombine(ISD::SRL);
971 setTargetDAGCombine(ISD::OR);
972 setTargetDAGCombine(ISD::AND);
973 setTargetDAGCombine(ISD::ADD);
974 setTargetDAGCombine(ISD::SUB);
975 setTargetDAGCombine(ISD::STORE);
976 setTargetDAGCombine(ISD::ZERO_EXTEND);
977 if (Subtarget->is64Bit())
978 setTargetDAGCombine(ISD::MUL);
980 computeRegisterProperties();
982 // On Darwin, -Os means optimize for size without hurting performance,
983 // do not reduce the limit.
984 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
985 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
986 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
987 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
988 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
989 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
990 setPrefLoopAlignment(16);
991 benefitFromCodePlacementOpt = true;
995 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1000 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1001 /// the desired ByVal argument alignment.
1002 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1005 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1006 if (VTy->getBitWidth() == 128)
1008 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1009 unsigned EltAlign = 0;
1010 getMaxByValAlign(ATy->getElementType(), EltAlign);
1011 if (EltAlign > MaxAlign)
1012 MaxAlign = EltAlign;
1013 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1014 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1015 unsigned EltAlign = 0;
1016 getMaxByValAlign(STy->getElementType(i), EltAlign);
1017 if (EltAlign > MaxAlign)
1018 MaxAlign = EltAlign;
1026 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1027 /// function arguments in the caller parameter area. For X86, aggregates
1028 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1029 /// are at 4-byte boundaries.
1030 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1031 if (Subtarget->is64Bit()) {
1032 // Max of 8 and alignment of type.
1033 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1040 if (Subtarget->hasXMM())
1041 getMaxByValAlign(Ty, Align);
1045 /// getOptimalMemOpType - Returns the target specific optimal type for load
1046 /// and store operations as a result of memset, memcpy, and memmove
1047 /// lowering. If DstAlign is zero that means it's safe to destination
1048 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1049 /// means there isn't a need to check it against alignment requirement,
1050 /// probably because the source does not need to be loaded. If
1051 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1052 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1053 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1054 /// constant so it does not need to be loaded.
1055 /// It returns EVT::Other if the type should be determined using generic
1056 /// target-independent logic.
1058 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1059 unsigned DstAlign, unsigned SrcAlign,
1060 bool NonScalarIntSafe,
1062 MachineFunction &MF) const {
1063 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1064 // linux. This is because the stack realignment code can't handle certain
1065 // cases like PR2962. This should be removed when PR2962 is fixed.
1066 const Function *F = MF.getFunction();
1067 if (NonScalarIntSafe &&
1068 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1070 (Subtarget->isUnalignedMemAccessFast() ||
1071 ((DstAlign == 0 || DstAlign >= 16) &&
1072 (SrcAlign == 0 || SrcAlign >= 16))) &&
1073 Subtarget->getStackAlignment() >= 16) {
1074 if (Subtarget->hasSSE2())
1076 if (Subtarget->hasSSE1())
1078 } else if (!MemcpyStrSrc && Size >= 8 &&
1079 !Subtarget->is64Bit() &&
1080 Subtarget->getStackAlignment() >= 8 &&
1081 Subtarget->hasXMMInt()) {
1082 // Do not use f64 to lower memcpy if source is string constant. It's
1083 // better to use i32 to avoid the loads.
1087 if (Subtarget->is64Bit() && Size >= 8)
1092 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1093 /// current function. The returned value is a member of the
1094 /// MachineJumpTableInfo::JTEntryKind enum.
1095 unsigned X86TargetLowering::getJumpTableEncoding() const {
1096 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1098 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1099 Subtarget->isPICStyleGOT())
1100 return MachineJumpTableInfo::EK_Custom32;
1102 // Otherwise, use the normal jump table encoding heuristics.
1103 return TargetLowering::getJumpTableEncoding();
1107 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1108 const MachineBasicBlock *MBB,
1109 unsigned uid,MCContext &Ctx) const{
1110 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1111 Subtarget->isPICStyleGOT());
1112 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1114 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1115 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1118 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1120 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1121 SelectionDAG &DAG) const {
1122 if (!Subtarget->is64Bit())
1123 // This doesn't have DebugLoc associated with it, but is not really the
1124 // same as a Register.
1125 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1129 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1130 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1132 const MCExpr *X86TargetLowering::
1133 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1134 MCContext &Ctx) const {
1135 // X86-64 uses RIP relative addressing based on the jump table label.
1136 if (Subtarget->isPICStyleRIPRel())
1137 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1139 // Otherwise, the reference is relative to the PIC base.
1140 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1143 /// getFunctionAlignment - Return the Log2 alignment of this function.
1144 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1145 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1148 std::pair<const TargetRegisterClass*, uint8_t>
1149 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1150 const TargetRegisterClass *RRC = 0;
1152 switch (VT.getSimpleVT().SimpleTy) {
1154 return TargetLowering::findRepresentativeClass(VT);
1155 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1156 RRC = (Subtarget->is64Bit()
1157 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1160 RRC = X86::VR64RegisterClass;
1162 case MVT::f32: case MVT::f64:
1163 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1164 case MVT::v4f32: case MVT::v2f64:
1165 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1167 RRC = X86::VR128RegisterClass;
1170 return std::make_pair(RRC, Cost);
1174 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1175 MachineFunction &MF) const {
1176 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1178 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
1179 switch (RC->getID()) {
1182 case X86::GR32RegClassID:
1184 case X86::GR64RegClassID:
1186 case X86::VR128RegClassID:
1187 return Subtarget->is64Bit() ? 10 : 4;
1188 case X86::VR64RegClassID:
1193 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1194 unsigned &Offset) const {
1195 if (!Subtarget->isTargetLinux())
1198 if (Subtarget->is64Bit()) {
1199 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1201 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1214 //===----------------------------------------------------------------------===//
1215 // Return Value Calling Convention Implementation
1216 //===----------------------------------------------------------------------===//
1218 #include "X86GenCallingConv.inc"
1221 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1222 const SmallVectorImpl<ISD::OutputArg> &Outs,
1223 LLVMContext &Context) const {
1224 SmallVector<CCValAssign, 16> RVLocs;
1225 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1227 return CCInfo.CheckReturn(Outs, RetCC_X86);
1231 X86TargetLowering::LowerReturn(SDValue Chain,
1232 CallingConv::ID CallConv, bool isVarArg,
1233 const SmallVectorImpl<ISD::OutputArg> &Outs,
1234 const SmallVectorImpl<SDValue> &OutVals,
1235 DebugLoc dl, SelectionDAG &DAG) const {
1236 MachineFunction &MF = DAG.getMachineFunction();
1237 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1239 SmallVector<CCValAssign, 16> RVLocs;
1240 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1241 RVLocs, *DAG.getContext());
1242 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1244 // Add the regs to the liveout set for the function.
1245 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1246 for (unsigned i = 0; i != RVLocs.size(); ++i)
1247 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1248 MRI.addLiveOut(RVLocs[i].getLocReg());
1252 SmallVector<SDValue, 6> RetOps;
1253 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1254 // Operand #1 = Bytes To Pop
1255 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1258 // Copy the result values into the output registers.
1259 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1260 CCValAssign &VA = RVLocs[i];
1261 assert(VA.isRegLoc() && "Can only return in registers!");
1262 SDValue ValToCopy = OutVals[i];
1263 EVT ValVT = ValToCopy.getValueType();
1265 // If this is x86-64, and we disabled SSE, we can't return FP values,
1266 // or SSE or MMX vectors.
1267 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1268 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1269 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1270 report_fatal_error("SSE register return with SSE disabled");
1272 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1273 // llvm-gcc has never done it right and no one has noticed, so this
1274 // should be OK for now.
1275 if (ValVT == MVT::f64 &&
1276 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1277 report_fatal_error("SSE2 register return with SSE2 disabled");
1279 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1280 // the RET instruction and handled by the FP Stackifier.
1281 if (VA.getLocReg() == X86::ST0 ||
1282 VA.getLocReg() == X86::ST1) {
1283 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1284 // change the value to the FP stack register class.
1285 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1286 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1287 RetOps.push_back(ValToCopy);
1288 // Don't emit a copytoreg.
1292 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1293 // which is returned in RAX / RDX.
1294 if (Subtarget->is64Bit()) {
1295 if (ValVT == MVT::x86mmx) {
1296 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1297 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1298 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1300 // If we don't have SSE2 available, convert to v4f32 so the generated
1301 // register is legal.
1302 if (!Subtarget->hasSSE2())
1303 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1308 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1309 Flag = Chain.getValue(1);
1312 // The x86-64 ABI for returning structs by value requires that we copy
1313 // the sret argument into %rax for the return. We saved the argument into
1314 // a virtual register in the entry block, so now we copy the value out
1316 if (Subtarget->is64Bit() &&
1317 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1318 MachineFunction &MF = DAG.getMachineFunction();
1319 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1320 unsigned Reg = FuncInfo->getSRetReturnReg();
1322 "SRetReturnReg should have been set in LowerFormalArguments().");
1323 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1325 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1326 Flag = Chain.getValue(1);
1328 // RAX now acts like a return value.
1329 MRI.addLiveOut(X86::RAX);
1332 RetOps[0] = Chain; // Update chain.
1334 // Add the flag if we have it.
1336 RetOps.push_back(Flag);
1338 return DAG.getNode(X86ISD::RET_FLAG, dl,
1339 MVT::Other, &RetOps[0], RetOps.size());
1342 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1343 if (N->getNumValues() != 1)
1345 if (!N->hasNUsesOfValue(1, 0))
1348 SDNode *Copy = *N->use_begin();
1349 if (Copy->getOpcode() != ISD::CopyToReg &&
1350 Copy->getOpcode() != ISD::FP_EXTEND)
1353 bool HasRet = false;
1354 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1356 if (UI->getOpcode() != X86ISD::RET_FLAG)
1364 /// LowerCallResult - Lower the result values of a call into the
1365 /// appropriate copies out of appropriate physical registers.
1368 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1369 CallingConv::ID CallConv, bool isVarArg,
1370 const SmallVectorImpl<ISD::InputArg> &Ins,
1371 DebugLoc dl, SelectionDAG &DAG,
1372 SmallVectorImpl<SDValue> &InVals) const {
1374 // Assign locations to each value returned by this call.
1375 SmallVector<CCValAssign, 16> RVLocs;
1376 bool Is64Bit = Subtarget->is64Bit();
1377 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1378 RVLocs, *DAG.getContext());
1379 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1381 // Copy all of the result registers out of their specified physreg.
1382 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1383 CCValAssign &VA = RVLocs[i];
1384 EVT CopyVT = VA.getValVT();
1386 // If this is x86-64, and we disabled SSE, we can't return FP values
1387 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1388 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1389 report_fatal_error("SSE register return with SSE disabled");
1394 // If this is a call to a function that returns an fp value on the floating
1395 // point stack, we must guarantee the the value is popped from the stack, so
1396 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1397 // if the return value is not used. We use the FpGET_ST0 instructions
1399 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1400 // If we prefer to use the value in xmm registers, copy it out as f80 and
1401 // use a truncate to move it from fp stack reg to xmm reg.
1402 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1403 bool isST0 = VA.getLocReg() == X86::ST0;
1405 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1406 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1407 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1408 SDValue Ops[] = { Chain, InFlag };
1409 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue,
1411 Val = Chain.getValue(0);
1413 // Round the f80 to the right size, which also moves it to the appropriate
1415 if (CopyVT != VA.getValVT())
1416 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1417 // This truncation won't change the value.
1418 DAG.getIntPtrConstant(1));
1419 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1420 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1421 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1422 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1423 MVT::v2i64, InFlag).getValue(1);
1424 Val = Chain.getValue(0);
1425 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1426 Val, DAG.getConstant(0, MVT::i64));
1428 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1429 MVT::i64, InFlag).getValue(1);
1430 Val = Chain.getValue(0);
1432 Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val);
1434 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1435 CopyVT, InFlag).getValue(1);
1436 Val = Chain.getValue(0);
1438 InFlag = Chain.getValue(2);
1439 InVals.push_back(Val);
1446 //===----------------------------------------------------------------------===//
1447 // C & StdCall & Fast Calling Convention implementation
1448 //===----------------------------------------------------------------------===//
1449 // StdCall calling convention seems to be standard for many Windows' API
1450 // routines and around. It differs from C calling convention just a little:
1451 // callee should clean up the stack, not caller. Symbols should be also
1452 // decorated in some fancy way :) It doesn't support any vector arguments.
1453 // For info on fast calling convention see Fast Calling Convention (tail call)
1454 // implementation LowerX86_32FastCCCallTo.
1456 /// CallIsStructReturn - Determines whether a call uses struct return
1458 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1462 return Outs[0].Flags.isSRet();
1465 /// ArgsAreStructReturn - Determines whether a function uses struct
1466 /// return semantics.
1468 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1472 return Ins[0].Flags.isSRet();
1475 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1476 /// by "Src" to address "Dst" with size and alignment information specified by
1477 /// the specific parameter attribute. The copy will be passed as a byval
1478 /// function parameter.
1480 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1481 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1483 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1485 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1486 /*isVolatile*/false, /*AlwaysInline=*/true,
1487 MachinePointerInfo(), MachinePointerInfo());
1490 /// IsTailCallConvention - Return true if the calling convention is one that
1491 /// supports tail call optimization.
1492 static bool IsTailCallConvention(CallingConv::ID CC) {
1493 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1496 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1497 /// a tailcall target by changing its ABI.
1498 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1499 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1503 X86TargetLowering::LowerMemArgument(SDValue Chain,
1504 CallingConv::ID CallConv,
1505 const SmallVectorImpl<ISD::InputArg> &Ins,
1506 DebugLoc dl, SelectionDAG &DAG,
1507 const CCValAssign &VA,
1508 MachineFrameInfo *MFI,
1510 // Create the nodes corresponding to a load from this parameter slot.
1511 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1512 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1513 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1516 // If value is passed by pointer we have address passed instead of the value
1518 if (VA.getLocInfo() == CCValAssign::Indirect)
1519 ValVT = VA.getLocVT();
1521 ValVT = VA.getValVT();
1523 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1524 // changed with more analysis.
1525 // In case of tail call optimization mark all arguments mutable. Since they
1526 // could be overwritten by lowering of arguments in case of a tail call.
1527 if (Flags.isByVal()) {
1528 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1529 VA.getLocMemOffset(), isImmutable);
1530 return DAG.getFrameIndex(FI, getPointerTy());
1532 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1533 VA.getLocMemOffset(), isImmutable);
1534 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1535 return DAG.getLoad(ValVT, dl, Chain, FIN,
1536 MachinePointerInfo::getFixedStack(FI),
1542 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1543 CallingConv::ID CallConv,
1545 const SmallVectorImpl<ISD::InputArg> &Ins,
1548 SmallVectorImpl<SDValue> &InVals)
1550 MachineFunction &MF = DAG.getMachineFunction();
1551 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1553 const Function* Fn = MF.getFunction();
1554 if (Fn->hasExternalLinkage() &&
1555 Subtarget->isTargetCygMing() &&
1556 Fn->getName() == "main")
1557 FuncInfo->setForceFramePointer(true);
1559 MachineFrameInfo *MFI = MF.getFrameInfo();
1560 bool Is64Bit = Subtarget->is64Bit();
1561 bool IsWin64 = Subtarget->isTargetWin64();
1563 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1564 "Var args not supported with calling convention fastcc or ghc");
1566 // Assign locations to all of the incoming arguments.
1567 SmallVector<CCValAssign, 16> ArgLocs;
1568 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1569 ArgLocs, *DAG.getContext());
1570 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1572 unsigned LastVal = ~0U;
1574 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1575 CCValAssign &VA = ArgLocs[i];
1576 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1578 assert(VA.getValNo() != LastVal &&
1579 "Don't support value assigned to multiple locs yet");
1580 LastVal = VA.getValNo();
1582 if (VA.isRegLoc()) {
1583 EVT RegVT = VA.getLocVT();
1584 TargetRegisterClass *RC = NULL;
1585 if (RegVT == MVT::i32)
1586 RC = X86::GR32RegisterClass;
1587 else if (Is64Bit && RegVT == MVT::i64)
1588 RC = X86::GR64RegisterClass;
1589 else if (RegVT == MVT::f32)
1590 RC = X86::FR32RegisterClass;
1591 else if (RegVT == MVT::f64)
1592 RC = X86::FR64RegisterClass;
1593 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1594 RC = X86::VR256RegisterClass;
1595 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1596 RC = X86::VR128RegisterClass;
1597 else if (RegVT == MVT::x86mmx)
1598 RC = X86::VR64RegisterClass;
1600 llvm_unreachable("Unknown argument type!");
1602 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1603 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1605 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1606 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1608 if (VA.getLocInfo() == CCValAssign::SExt)
1609 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1610 DAG.getValueType(VA.getValVT()));
1611 else if (VA.getLocInfo() == CCValAssign::ZExt)
1612 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1613 DAG.getValueType(VA.getValVT()));
1614 else if (VA.getLocInfo() == CCValAssign::BCvt)
1615 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1617 if (VA.isExtInLoc()) {
1618 // Handle MMX values passed in XMM regs.
1619 if (RegVT.isVector()) {
1620 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1623 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1626 assert(VA.isMemLoc());
1627 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1630 // If value is passed via pointer - do a load.
1631 if (VA.getLocInfo() == CCValAssign::Indirect)
1632 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1633 MachinePointerInfo(), false, false, 0);
1635 InVals.push_back(ArgValue);
1638 // The x86-64 ABI for returning structs by value requires that we copy
1639 // the sret argument into %rax for the return. Save the argument into
1640 // a virtual register so that we can access it from the return points.
1641 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1642 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1643 unsigned Reg = FuncInfo->getSRetReturnReg();
1645 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1646 FuncInfo->setSRetReturnReg(Reg);
1648 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1649 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1652 unsigned StackSize = CCInfo.getNextStackOffset();
1653 // Align stack specially for tail calls.
1654 if (FuncIsMadeTailCallSafe(CallConv))
1655 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1657 // If the function takes variable number of arguments, make a frame index for
1658 // the start of the first vararg value... for expansion of llvm.va_start.
1660 if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1661 CallConv != CallingConv::X86_ThisCall))) {
1662 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1665 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1667 // FIXME: We should really autogenerate these arrays
1668 static const unsigned GPR64ArgRegsWin64[] = {
1669 X86::RCX, X86::RDX, X86::R8, X86::R9
1671 static const unsigned GPR64ArgRegs64Bit[] = {
1672 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1674 static const unsigned XMMArgRegs64Bit[] = {
1675 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1676 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1678 const unsigned *GPR64ArgRegs;
1679 unsigned NumXMMRegs = 0;
1682 // The XMM registers which might contain var arg parameters are shadowed
1683 // in their paired GPR. So we only need to save the GPR to their home
1685 TotalNumIntRegs = 4;
1686 GPR64ArgRegs = GPR64ArgRegsWin64;
1688 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1689 GPR64ArgRegs = GPR64ArgRegs64Bit;
1691 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1693 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1696 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1697 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1698 "SSE register cannot be used when SSE is disabled!");
1699 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1700 "SSE register cannot be used when SSE is disabled!");
1701 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1702 // Kernel mode asks for SSE to be disabled, so don't push them
1704 TotalNumXMMRegs = 0;
1707 const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo();
1708 // Get to the caller-allocated home save location. Add 8 to account
1709 // for the return address.
1710 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1711 FuncInfo->setRegSaveFrameIndex(
1712 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1713 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1715 // For X86-64, if there are vararg parameters that are passed via
1716 // registers, then we must store them to their spots on the stack so they
1717 // may be loaded by deferencing the result of va_next.
1718 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1719 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1720 FuncInfo->setRegSaveFrameIndex(
1721 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1725 // Store the integer parameter registers.
1726 SmallVector<SDValue, 8> MemOps;
1727 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1729 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1730 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1731 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1732 DAG.getIntPtrConstant(Offset));
1733 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1734 X86::GR64RegisterClass);
1735 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1737 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1738 MachinePointerInfo::getFixedStack(
1739 FuncInfo->getRegSaveFrameIndex(), Offset),
1741 MemOps.push_back(Store);
1745 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1746 // Now store the XMM (fp + vector) parameter registers.
1747 SmallVector<SDValue, 11> SaveXMMOps;
1748 SaveXMMOps.push_back(Chain);
1750 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1751 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1752 SaveXMMOps.push_back(ALVal);
1754 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1755 FuncInfo->getRegSaveFrameIndex()));
1756 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1757 FuncInfo->getVarArgsFPOffset()));
1759 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1760 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1761 X86::VR128RegisterClass);
1762 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1763 SaveXMMOps.push_back(Val);
1765 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1767 &SaveXMMOps[0], SaveXMMOps.size()));
1770 if (!MemOps.empty())
1771 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1772 &MemOps[0], MemOps.size());
1776 // Some CCs need callee pop.
1777 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1778 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1780 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1781 // If this is an sret function, the return should pop the hidden pointer.
1782 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1783 FuncInfo->setBytesToPopOnReturn(4);
1787 // RegSaveFrameIndex is X86-64 only.
1788 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1789 if (CallConv == CallingConv::X86_FastCall ||
1790 CallConv == CallingConv::X86_ThisCall)
1791 // fastcc functions can't have varargs.
1792 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1799 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1800 SDValue StackPtr, SDValue Arg,
1801 DebugLoc dl, SelectionDAG &DAG,
1802 const CCValAssign &VA,
1803 ISD::ArgFlagsTy Flags) const {
1804 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1805 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1806 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1807 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1808 if (Flags.isByVal())
1809 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1811 return DAG.getStore(Chain, dl, Arg, PtrOff,
1812 MachinePointerInfo::getStack(LocMemOffset),
1816 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1817 /// optimization is performed and it is required.
1819 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1820 SDValue &OutRetAddr, SDValue Chain,
1821 bool IsTailCall, bool Is64Bit,
1822 int FPDiff, DebugLoc dl) const {
1823 // Adjust the Return address stack slot.
1824 EVT VT = getPointerTy();
1825 OutRetAddr = getReturnAddressFrameIndex(DAG);
1827 // Load the "old" Return address.
1828 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1830 return SDValue(OutRetAddr.getNode(), 1);
1833 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1834 /// optimization is performed and it is required (FPDiff!=0).
1836 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1837 SDValue Chain, SDValue RetAddrFrIdx,
1838 bool Is64Bit, int FPDiff, DebugLoc dl) {
1839 // Store the return address to the appropriate stack slot.
1840 if (!FPDiff) return Chain;
1841 // Calculate the new stack slot for the return address.
1842 int SlotSize = Is64Bit ? 8 : 4;
1843 int NewReturnAddrFI =
1844 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1845 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1846 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1847 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1848 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1854 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1855 CallingConv::ID CallConv, bool isVarArg,
1857 const SmallVectorImpl<ISD::OutputArg> &Outs,
1858 const SmallVectorImpl<SDValue> &OutVals,
1859 const SmallVectorImpl<ISD::InputArg> &Ins,
1860 DebugLoc dl, SelectionDAG &DAG,
1861 SmallVectorImpl<SDValue> &InVals) const {
1862 MachineFunction &MF = DAG.getMachineFunction();
1863 bool Is64Bit = Subtarget->is64Bit();
1864 bool IsStructRet = CallIsStructReturn(Outs);
1865 bool IsSibcall = false;
1868 // Check if it's really possible to do a tail call.
1869 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1870 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1871 Outs, OutVals, Ins, DAG);
1873 // Sibcalls are automatically detected tailcalls which do not require
1875 if (!GuaranteedTailCallOpt && isTailCall)
1882 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1883 "Var args not supported with calling convention fastcc or ghc");
1885 // Analyze operands of the call, assigning locations to each operand.
1886 SmallVector<CCValAssign, 16> ArgLocs;
1887 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1888 ArgLocs, *DAG.getContext());
1889 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
1891 // Get a count of how many bytes are to be pushed on the stack.
1892 unsigned NumBytes = CCInfo.getNextStackOffset();
1894 // This is a sibcall. The memory operands are available in caller's
1895 // own caller's stack.
1897 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1898 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1901 if (isTailCall && !IsSibcall) {
1902 // Lower arguments at fp - stackoffset + fpdiff.
1903 unsigned NumBytesCallerPushed =
1904 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1905 FPDiff = NumBytesCallerPushed - NumBytes;
1907 // Set the delta of movement of the returnaddr stackslot.
1908 // But only set if delta is greater than previous delta.
1909 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1910 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1914 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1916 SDValue RetAddrFrIdx;
1917 // Load return adress for tail calls.
1918 if (isTailCall && FPDiff)
1919 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1920 Is64Bit, FPDiff, dl);
1922 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1923 SmallVector<SDValue, 8> MemOpChains;
1926 // Walk the register/memloc assignments, inserting copies/loads. In the case
1927 // of tail call optimization arguments are handle later.
1928 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1929 CCValAssign &VA = ArgLocs[i];
1930 EVT RegVT = VA.getLocVT();
1931 SDValue Arg = OutVals[i];
1932 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1933 bool isByVal = Flags.isByVal();
1935 // Promote the value if needed.
1936 switch (VA.getLocInfo()) {
1937 default: llvm_unreachable("Unknown loc info!");
1938 case CCValAssign::Full: break;
1939 case CCValAssign::SExt:
1940 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1942 case CCValAssign::ZExt:
1943 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1945 case CCValAssign::AExt:
1946 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1947 // Special case: passing MMX values in XMM registers.
1948 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
1949 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1950 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1952 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1954 case CCValAssign::BCvt:
1955 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
1957 case CCValAssign::Indirect: {
1958 // Store the argument.
1959 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1960 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1961 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1962 MachinePointerInfo::getFixedStack(FI),
1969 if (VA.isRegLoc()) {
1970 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1971 if (isVarArg && Subtarget->isTargetWin64()) {
1972 // Win64 ABI requires argument XMM reg to be copied to the corresponding
1973 // shadow reg if callee is a varargs function.
1974 unsigned ShadowReg = 0;
1975 switch (VA.getLocReg()) {
1976 case X86::XMM0: ShadowReg = X86::RCX; break;
1977 case X86::XMM1: ShadowReg = X86::RDX; break;
1978 case X86::XMM2: ShadowReg = X86::R8; break;
1979 case X86::XMM3: ShadowReg = X86::R9; break;
1982 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
1984 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1985 assert(VA.isMemLoc());
1986 if (StackPtr.getNode() == 0)
1987 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1988 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1989 dl, DAG, VA, Flags));
1993 if (!MemOpChains.empty())
1994 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1995 &MemOpChains[0], MemOpChains.size());
1997 // Build a sequence of copy-to-reg nodes chained together with token chain
1998 // and flag operands which copy the outgoing args into registers.
2000 // Tail call byval lowering might overwrite argument registers so in case of
2001 // tail call optimization the copies to registers are lowered later.
2003 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2004 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2005 RegsToPass[i].second, InFlag);
2006 InFlag = Chain.getValue(1);
2009 if (Subtarget->isPICStyleGOT()) {
2010 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2013 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2014 DAG.getNode(X86ISD::GlobalBaseReg,
2015 DebugLoc(), getPointerTy()),
2017 InFlag = Chain.getValue(1);
2019 // If we are tail calling and generating PIC/GOT style code load the
2020 // address of the callee into ECX. The value in ecx is used as target of
2021 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2022 // for tail calls on PIC/GOT architectures. Normally we would just put the
2023 // address of GOT into ebx and then call target@PLT. But for tail calls
2024 // ebx would be restored (since ebx is callee saved) before jumping to the
2027 // Note: The actual moving to ECX is done further down.
2028 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2029 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2030 !G->getGlobal()->hasProtectedVisibility())
2031 Callee = LowerGlobalAddress(Callee, DAG);
2032 else if (isa<ExternalSymbolSDNode>(Callee))
2033 Callee = LowerExternalSymbol(Callee, DAG);
2037 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2038 // From AMD64 ABI document:
2039 // For calls that may call functions that use varargs or stdargs
2040 // (prototype-less calls or calls to functions containing ellipsis (...) in
2041 // the declaration) %al is used as hidden argument to specify the number
2042 // of SSE registers used. The contents of %al do not need to match exactly
2043 // the number of registers, but must be an ubound on the number of SSE
2044 // registers used and is in the range 0 - 8 inclusive.
2046 // Count the number of XMM registers allocated.
2047 static const unsigned XMMArgRegs[] = {
2048 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2049 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2051 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2052 assert((Subtarget->hasXMM() || !NumXMMRegs)
2053 && "SSE registers cannot be used when SSE is disabled");
2055 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2056 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2057 InFlag = Chain.getValue(1);
2061 // For tail calls lower the arguments to the 'real' stack slot.
2063 // Force all the incoming stack arguments to be loaded from the stack
2064 // before any new outgoing arguments are stored to the stack, because the
2065 // outgoing stack slots may alias the incoming argument stack slots, and
2066 // the alias isn't otherwise explicit. This is slightly more conservative
2067 // than necessary, because it means that each store effectively depends
2068 // on every argument instead of just those arguments it would clobber.
2069 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2071 SmallVector<SDValue, 8> MemOpChains2;
2074 // Do not flag preceeding copytoreg stuff together with the following stuff.
2076 if (GuaranteedTailCallOpt) {
2077 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2078 CCValAssign &VA = ArgLocs[i];
2081 assert(VA.isMemLoc());
2082 SDValue Arg = OutVals[i];
2083 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2084 // Create frame index.
2085 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2086 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2087 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2088 FIN = DAG.getFrameIndex(FI, getPointerTy());
2090 if (Flags.isByVal()) {
2091 // Copy relative to framepointer.
2092 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2093 if (StackPtr.getNode() == 0)
2094 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2096 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2098 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2102 // Store relative to framepointer.
2103 MemOpChains2.push_back(
2104 DAG.getStore(ArgChain, dl, Arg, FIN,
2105 MachinePointerInfo::getFixedStack(FI),
2111 if (!MemOpChains2.empty())
2112 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2113 &MemOpChains2[0], MemOpChains2.size());
2115 // Copy arguments to their registers.
2116 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2117 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2118 RegsToPass[i].second, InFlag);
2119 InFlag = Chain.getValue(1);
2123 // Store the return address to the appropriate stack slot.
2124 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2128 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2129 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2130 // In the 64-bit large code model, we have to make all calls
2131 // through a register, since the call instruction's 32-bit
2132 // pc-relative offset may not be large enough to hold the whole
2134 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2135 // If the callee is a GlobalAddress node (quite common, every direct call
2136 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2139 // We should use extra load for direct calls to dllimported functions in
2141 const GlobalValue *GV = G->getGlobal();
2142 if (!GV->hasDLLImportLinkage()) {
2143 unsigned char OpFlags = 0;
2145 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2146 // external symbols most go through the PLT in PIC mode. If the symbol
2147 // has hidden or protected visibility, or if it is static or local, then
2148 // we don't need to use the PLT - we can directly call it.
2149 if (Subtarget->isTargetELF() &&
2150 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2151 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2152 OpFlags = X86II::MO_PLT;
2153 } else if (Subtarget->isPICStyleStubAny() &&
2154 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2155 Subtarget->getDarwinVers() < 9) {
2156 // PC-relative references to external symbols should go through $stub,
2157 // unless we're building with the leopard linker or later, which
2158 // automatically synthesizes these stubs.
2159 OpFlags = X86II::MO_DARWIN_STUB;
2162 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2163 G->getOffset(), OpFlags);
2165 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2166 unsigned char OpFlags = 0;
2168 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2169 // external symbols should go through the PLT.
2170 if (Subtarget->isTargetELF() &&
2171 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2172 OpFlags = X86II::MO_PLT;
2173 } else if (Subtarget->isPICStyleStubAny() &&
2174 Subtarget->getDarwinVers() < 9) {
2175 // PC-relative references to external symbols should go through $stub,
2176 // unless we're building with the leopard linker or later, which
2177 // automatically synthesizes these stubs.
2178 OpFlags = X86II::MO_DARWIN_STUB;
2181 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2185 // Returns a chain & a flag for retval copy to use.
2186 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2187 SmallVector<SDValue, 8> Ops;
2189 if (!IsSibcall && isTailCall) {
2190 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2191 DAG.getIntPtrConstant(0, true), InFlag);
2192 InFlag = Chain.getValue(1);
2195 Ops.push_back(Chain);
2196 Ops.push_back(Callee);
2199 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2201 // Add argument registers to the end of the list so that they are known live
2203 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2204 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2205 RegsToPass[i].second.getValueType()));
2207 // Add an implicit use GOT pointer in EBX.
2208 if (!isTailCall && Subtarget->isPICStyleGOT())
2209 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2211 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2212 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2213 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2215 if (InFlag.getNode())
2216 Ops.push_back(InFlag);
2220 //// If this is the first return lowered for this function, add the regs
2221 //// to the liveout set for the function.
2222 // This isn't right, although it's probably harmless on x86; liveouts
2223 // should be computed from returns not tail calls. Consider a void
2224 // function making a tail call to a function returning int.
2225 return DAG.getNode(X86ISD::TC_RETURN, dl,
2226 NodeTys, &Ops[0], Ops.size());
2229 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2230 InFlag = Chain.getValue(1);
2232 // Create the CALLSEQ_END node.
2233 unsigned NumBytesForCalleeToPush;
2234 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2235 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2236 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2237 // If this is a call to a struct-return function, the callee
2238 // pops the hidden struct pointer, so we have to push it back.
2239 // This is common for Darwin/X86, Linux & Mingw32 targets.
2240 NumBytesForCalleeToPush = 4;
2242 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2244 // Returns a flag for retval copy to use.
2246 Chain = DAG.getCALLSEQ_END(Chain,
2247 DAG.getIntPtrConstant(NumBytes, true),
2248 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2251 InFlag = Chain.getValue(1);
2254 // Handle result values, copying them out of physregs into vregs that we
2256 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2257 Ins, dl, DAG, InVals);
2261 //===----------------------------------------------------------------------===//
2262 // Fast Calling Convention (tail call) implementation
2263 //===----------------------------------------------------------------------===//
2265 // Like std call, callee cleans arguments, convention except that ECX is
2266 // reserved for storing the tail called function address. Only 2 registers are
2267 // free for argument passing (inreg). Tail call optimization is performed
2269 // * tailcallopt is enabled
2270 // * caller/callee are fastcc
2271 // On X86_64 architecture with GOT-style position independent code only local
2272 // (within module) calls are supported at the moment.
2273 // To keep the stack aligned according to platform abi the function
2274 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2275 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2276 // If a tail called function callee has more arguments than the caller the
2277 // caller needs to make sure that there is room to move the RETADDR to. This is
2278 // achieved by reserving an area the size of the argument delta right after the
2279 // original REtADDR, but before the saved framepointer or the spilled registers
2280 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2292 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2293 /// for a 16 byte align requirement.
2295 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2296 SelectionDAG& DAG) const {
2297 MachineFunction &MF = DAG.getMachineFunction();
2298 const TargetMachine &TM = MF.getTarget();
2299 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2300 unsigned StackAlignment = TFI.getStackAlignment();
2301 uint64_t AlignMask = StackAlignment - 1;
2302 int64_t Offset = StackSize;
2303 uint64_t SlotSize = TD->getPointerSize();
2304 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2305 // Number smaller than 12 so just add the difference.
2306 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2308 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2309 Offset = ((~AlignMask) & Offset) + StackAlignment +
2310 (StackAlignment-SlotSize);
2315 /// MatchingStackOffset - Return true if the given stack call argument is
2316 /// already available in the same position (relatively) of the caller's
2317 /// incoming argument stack.
2319 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2320 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2321 const X86InstrInfo *TII) {
2322 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2324 if (Arg.getOpcode() == ISD::CopyFromReg) {
2325 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2326 if (!TargetRegisterInfo::isVirtualRegister(VR))
2328 MachineInstr *Def = MRI->getVRegDef(VR);
2331 if (!Flags.isByVal()) {
2332 if (!TII->isLoadFromStackSlot(Def, FI))
2335 unsigned Opcode = Def->getOpcode();
2336 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2337 Def->getOperand(1).isFI()) {
2338 FI = Def->getOperand(1).getIndex();
2339 Bytes = Flags.getByValSize();
2343 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2344 if (Flags.isByVal())
2345 // ByVal argument is passed in as a pointer but it's now being
2346 // dereferenced. e.g.
2347 // define @foo(%struct.X* %A) {
2348 // tail call @bar(%struct.X* byval %A)
2351 SDValue Ptr = Ld->getBasePtr();
2352 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2355 FI = FINode->getIndex();
2359 assert(FI != INT_MAX);
2360 if (!MFI->isFixedObjectIndex(FI))
2362 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2365 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2366 /// for tail call optimization. Targets which want to do tail call
2367 /// optimization should implement this function.
2369 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2370 CallingConv::ID CalleeCC,
2372 bool isCalleeStructRet,
2373 bool isCallerStructRet,
2374 const SmallVectorImpl<ISD::OutputArg> &Outs,
2375 const SmallVectorImpl<SDValue> &OutVals,
2376 const SmallVectorImpl<ISD::InputArg> &Ins,
2377 SelectionDAG& DAG) const {
2378 if (!IsTailCallConvention(CalleeCC) &&
2379 CalleeCC != CallingConv::C)
2382 // If -tailcallopt is specified, make fastcc functions tail-callable.
2383 const MachineFunction &MF = DAG.getMachineFunction();
2384 const Function *CallerF = DAG.getMachineFunction().getFunction();
2385 CallingConv::ID CallerCC = CallerF->getCallingConv();
2386 bool CCMatch = CallerCC == CalleeCC;
2388 if (GuaranteedTailCallOpt) {
2389 if (IsTailCallConvention(CalleeCC) && CCMatch)
2394 // Look for obvious safe cases to perform tail call optimization that do not
2395 // require ABI changes. This is what gcc calls sibcall.
2397 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2398 // emit a special epilogue.
2399 if (RegInfo->needsStackRealignment(MF))
2402 // Do not sibcall optimize vararg calls unless the call site is not passing
2404 if (isVarArg && !Outs.empty())
2407 // Also avoid sibcall optimization if either caller or callee uses struct
2408 // return semantics.
2409 if (isCalleeStructRet || isCallerStructRet)
2412 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2413 // Therefore if it's not used by the call it is not safe to optimize this into
2415 bool Unused = false;
2416 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2423 SmallVector<CCValAssign, 16> RVLocs;
2424 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2425 RVLocs, *DAG.getContext());
2426 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2427 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2428 CCValAssign &VA = RVLocs[i];
2429 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2434 // If the calling conventions do not match, then we'd better make sure the
2435 // results are returned in the same way as what the caller expects.
2437 SmallVector<CCValAssign, 16> RVLocs1;
2438 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2439 RVLocs1, *DAG.getContext());
2440 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2442 SmallVector<CCValAssign, 16> RVLocs2;
2443 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2444 RVLocs2, *DAG.getContext());
2445 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2447 if (RVLocs1.size() != RVLocs2.size())
2449 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2450 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2452 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2454 if (RVLocs1[i].isRegLoc()) {
2455 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2458 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2464 // If the callee takes no arguments then go on to check the results of the
2466 if (!Outs.empty()) {
2467 // Check if stack adjustment is needed. For now, do not do this if any
2468 // argument is passed on the stack.
2469 SmallVector<CCValAssign, 16> ArgLocs;
2470 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2471 ArgLocs, *DAG.getContext());
2472 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2473 if (CCInfo.getNextStackOffset()) {
2474 MachineFunction &MF = DAG.getMachineFunction();
2475 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2477 if (Subtarget->isTargetWin64())
2478 // Win64 ABI has additional complications.
2481 // Check if the arguments are already laid out in the right way as
2482 // the caller's fixed stack objects.
2483 MachineFrameInfo *MFI = MF.getFrameInfo();
2484 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2485 const X86InstrInfo *TII =
2486 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2487 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2488 CCValAssign &VA = ArgLocs[i];
2489 SDValue Arg = OutVals[i];
2490 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2491 if (VA.getLocInfo() == CCValAssign::Indirect)
2493 if (!VA.isRegLoc()) {
2494 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2501 // If the tailcall address may be in a register, then make sure it's
2502 // possible to register allocate for it. In 32-bit, the call address can
2503 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2504 // callee-saved registers are restored. These happen to be the same
2505 // registers used to pass 'inreg' arguments so watch out for those.
2506 if (!Subtarget->is64Bit() &&
2507 !isa<GlobalAddressSDNode>(Callee) &&
2508 !isa<ExternalSymbolSDNode>(Callee)) {
2509 unsigned NumInRegs = 0;
2510 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2511 CCValAssign &VA = ArgLocs[i];
2514 unsigned Reg = VA.getLocReg();
2517 case X86::EAX: case X86::EDX: case X86::ECX:
2518 if (++NumInRegs == 3)
2526 // An stdcall caller is expected to clean up its arguments; the callee
2527 // isn't going to do that.
2528 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2535 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2536 return X86::createFastISel(funcInfo);
2540 //===----------------------------------------------------------------------===//
2541 // Other Lowering Hooks
2542 //===----------------------------------------------------------------------===//
2544 static bool MayFoldLoad(SDValue Op) {
2545 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2548 static bool MayFoldIntoStore(SDValue Op) {
2549 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2552 static bool isTargetShuffle(unsigned Opcode) {
2554 default: return false;
2555 case X86ISD::PSHUFD:
2556 case X86ISD::PSHUFHW:
2557 case X86ISD::PSHUFLW:
2558 case X86ISD::SHUFPD:
2559 case X86ISD::PALIGN:
2560 case X86ISD::SHUFPS:
2561 case X86ISD::MOVLHPS:
2562 case X86ISD::MOVLHPD:
2563 case X86ISD::MOVHLPS:
2564 case X86ISD::MOVLPS:
2565 case X86ISD::MOVLPD:
2566 case X86ISD::MOVSHDUP:
2567 case X86ISD::MOVSLDUP:
2568 case X86ISD::MOVDDUP:
2571 case X86ISD::UNPCKLPS:
2572 case X86ISD::UNPCKLPD:
2573 case X86ISD::PUNPCKLWD:
2574 case X86ISD::PUNPCKLBW:
2575 case X86ISD::PUNPCKLDQ:
2576 case X86ISD::PUNPCKLQDQ:
2577 case X86ISD::UNPCKHPS:
2578 case X86ISD::UNPCKHPD:
2579 case X86ISD::PUNPCKHWD:
2580 case X86ISD::PUNPCKHBW:
2581 case X86ISD::PUNPCKHDQ:
2582 case X86ISD::PUNPCKHQDQ:
2588 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2589 SDValue V1, SelectionDAG &DAG) {
2591 default: llvm_unreachable("Unknown x86 shuffle node");
2592 case X86ISD::MOVSHDUP:
2593 case X86ISD::MOVSLDUP:
2594 case X86ISD::MOVDDUP:
2595 return DAG.getNode(Opc, dl, VT, V1);
2601 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2602 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2604 default: llvm_unreachable("Unknown x86 shuffle node");
2605 case X86ISD::PSHUFD:
2606 case X86ISD::PSHUFHW:
2607 case X86ISD::PSHUFLW:
2608 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2614 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2615 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2617 default: llvm_unreachable("Unknown x86 shuffle node");
2618 case X86ISD::PALIGN:
2619 case X86ISD::SHUFPD:
2620 case X86ISD::SHUFPS:
2621 return DAG.getNode(Opc, dl, VT, V1, V2,
2622 DAG.getConstant(TargetMask, MVT::i8));
2627 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2628 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2630 default: llvm_unreachable("Unknown x86 shuffle node");
2631 case X86ISD::MOVLHPS:
2632 case X86ISD::MOVLHPD:
2633 case X86ISD::MOVHLPS:
2634 case X86ISD::MOVLPS:
2635 case X86ISD::MOVLPD:
2638 case X86ISD::UNPCKLPS:
2639 case X86ISD::UNPCKLPD:
2640 case X86ISD::PUNPCKLWD:
2641 case X86ISD::PUNPCKLBW:
2642 case X86ISD::PUNPCKLDQ:
2643 case X86ISD::PUNPCKLQDQ:
2644 case X86ISD::UNPCKHPS:
2645 case X86ISD::UNPCKHPD:
2646 case X86ISD::PUNPCKHWD:
2647 case X86ISD::PUNPCKHBW:
2648 case X86ISD::PUNPCKHDQ:
2649 case X86ISD::PUNPCKHQDQ:
2650 return DAG.getNode(Opc, dl, VT, V1, V2);
2655 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2656 MachineFunction &MF = DAG.getMachineFunction();
2657 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2658 int ReturnAddrIndex = FuncInfo->getRAIndex();
2660 if (ReturnAddrIndex == 0) {
2661 // Set up a frame object for the return address.
2662 uint64_t SlotSize = TD->getPointerSize();
2663 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2665 FuncInfo->setRAIndex(ReturnAddrIndex);
2668 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2672 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2673 bool hasSymbolicDisplacement) {
2674 // Offset should fit into 32 bit immediate field.
2675 if (!isInt<32>(Offset))
2678 // If we don't have a symbolic displacement - we don't have any extra
2680 if (!hasSymbolicDisplacement)
2683 // FIXME: Some tweaks might be needed for medium code model.
2684 if (M != CodeModel::Small && M != CodeModel::Kernel)
2687 // For small code model we assume that latest object is 16MB before end of 31
2688 // bits boundary. We may also accept pretty large negative constants knowing
2689 // that all objects are in the positive half of address space.
2690 if (M == CodeModel::Small && Offset < 16*1024*1024)
2693 // For kernel code model we know that all object resist in the negative half
2694 // of 32bits address space. We may not accept negative offsets, since they may
2695 // be just off and we may accept pretty large positive ones.
2696 if (M == CodeModel::Kernel && Offset > 0)
2702 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2703 /// specific condition code, returning the condition code and the LHS/RHS of the
2704 /// comparison to make.
2705 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2706 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2708 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2709 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2710 // X > -1 -> X == 0, jump !sign.
2711 RHS = DAG.getConstant(0, RHS.getValueType());
2712 return X86::COND_NS;
2713 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2714 // X < 0 -> X == 0, jump on sign.
2716 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2718 RHS = DAG.getConstant(0, RHS.getValueType());
2719 return X86::COND_LE;
2723 switch (SetCCOpcode) {
2724 default: llvm_unreachable("Invalid integer condition!");
2725 case ISD::SETEQ: return X86::COND_E;
2726 case ISD::SETGT: return X86::COND_G;
2727 case ISD::SETGE: return X86::COND_GE;
2728 case ISD::SETLT: return X86::COND_L;
2729 case ISD::SETLE: return X86::COND_LE;
2730 case ISD::SETNE: return X86::COND_NE;
2731 case ISD::SETULT: return X86::COND_B;
2732 case ISD::SETUGT: return X86::COND_A;
2733 case ISD::SETULE: return X86::COND_BE;
2734 case ISD::SETUGE: return X86::COND_AE;
2738 // First determine if it is required or is profitable to flip the operands.
2740 // If LHS is a foldable load, but RHS is not, flip the condition.
2741 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2742 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2743 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2744 std::swap(LHS, RHS);
2747 switch (SetCCOpcode) {
2753 std::swap(LHS, RHS);
2757 // On a floating point condition, the flags are set as follows:
2759 // 0 | 0 | 0 | X > Y
2760 // 0 | 0 | 1 | X < Y
2761 // 1 | 0 | 0 | X == Y
2762 // 1 | 1 | 1 | unordered
2763 switch (SetCCOpcode) {
2764 default: llvm_unreachable("Condcode should be pre-legalized away");
2766 case ISD::SETEQ: return X86::COND_E;
2767 case ISD::SETOLT: // flipped
2769 case ISD::SETGT: return X86::COND_A;
2770 case ISD::SETOLE: // flipped
2772 case ISD::SETGE: return X86::COND_AE;
2773 case ISD::SETUGT: // flipped
2775 case ISD::SETLT: return X86::COND_B;
2776 case ISD::SETUGE: // flipped
2778 case ISD::SETLE: return X86::COND_BE;
2780 case ISD::SETNE: return X86::COND_NE;
2781 case ISD::SETUO: return X86::COND_P;
2782 case ISD::SETO: return X86::COND_NP;
2784 case ISD::SETUNE: return X86::COND_INVALID;
2788 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2789 /// code. Current x86 isa includes the following FP cmov instructions:
2790 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2791 static bool hasFPCMov(unsigned X86CC) {
2807 /// isFPImmLegal - Returns true if the target can instruction select the
2808 /// specified FP immediate natively. If false, the legalizer will
2809 /// materialize the FP immediate as a load from a constant pool.
2810 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2811 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2812 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2818 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2819 /// the specified range (L, H].
2820 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2821 return (Val < 0) || (Val >= Low && Val < Hi);
2824 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2825 /// specified value.
2826 static bool isUndefOrEqual(int Val, int CmpVal) {
2827 if (Val < 0 || Val == CmpVal)
2832 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2833 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2834 /// the second operand.
2835 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2836 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
2837 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2838 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2839 return (Mask[0] < 2 && Mask[1] < 2);
2843 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2844 SmallVector<int, 8> M;
2846 return ::isPSHUFDMask(M, N->getValueType(0));
2849 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2850 /// is suitable for input to PSHUFHW.
2851 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2852 if (VT != MVT::v8i16)
2855 // Lower quadword copied in order or undef.
2856 for (int i = 0; i != 4; ++i)
2857 if (Mask[i] >= 0 && Mask[i] != i)
2860 // Upper quadword shuffled.
2861 for (int i = 4; i != 8; ++i)
2862 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2868 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2869 SmallVector<int, 8> M;
2871 return ::isPSHUFHWMask(M, N->getValueType(0));
2874 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2875 /// is suitable for input to PSHUFLW.
2876 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2877 if (VT != MVT::v8i16)
2880 // Upper quadword copied in order.
2881 for (int i = 4; i != 8; ++i)
2882 if (Mask[i] >= 0 && Mask[i] != i)
2885 // Lower quadword shuffled.
2886 for (int i = 0; i != 4; ++i)
2893 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2894 SmallVector<int, 8> M;
2896 return ::isPSHUFLWMask(M, N->getValueType(0));
2899 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2900 /// is suitable for input to PALIGNR.
2901 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2903 int i, e = VT.getVectorNumElements();
2905 // Do not handle v2i64 / v2f64 shuffles with palignr.
2906 if (e < 4 || !hasSSSE3)
2909 for (i = 0; i != e; ++i)
2913 // All undef, not a palignr.
2917 // Determine if it's ok to perform a palignr with only the LHS, since we
2918 // don't have access to the actual shuffle elements to see if RHS is undef.
2919 bool Unary = Mask[i] < (int)e;
2920 bool NeedsUnary = false;
2922 int s = Mask[i] - i;
2924 // Check the rest of the elements to see if they are consecutive.
2925 for (++i; i != e; ++i) {
2930 Unary = Unary && (m < (int)e);
2931 NeedsUnary = NeedsUnary || (m < s);
2933 if (NeedsUnary && !Unary)
2935 if (Unary && m != ((s+i) & (e-1)))
2937 if (!Unary && m != (s+i))
2943 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2944 SmallVector<int, 8> M;
2946 return ::isPALIGNRMask(M, N->getValueType(0), true);
2949 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2950 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2951 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2952 int NumElems = VT.getVectorNumElements();
2953 if (NumElems != 2 && NumElems != 4)
2956 int Half = NumElems / 2;
2957 for (int i = 0; i < Half; ++i)
2958 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2960 for (int i = Half; i < NumElems; ++i)
2961 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2967 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2968 SmallVector<int, 8> M;
2970 return ::isSHUFPMask(M, N->getValueType(0));
2973 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2974 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2975 /// half elements to come from vector 1 (which would equal the dest.) and
2976 /// the upper half to come from vector 2.
2977 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2978 int NumElems = VT.getVectorNumElements();
2980 if (NumElems != 2 && NumElems != 4)
2983 int Half = NumElems / 2;
2984 for (int i = 0; i < Half; ++i)
2985 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2987 for (int i = Half; i < NumElems; ++i)
2988 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2993 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2994 SmallVector<int, 8> M;
2996 return isCommutedSHUFPMask(M, N->getValueType(0));
2999 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3000 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3001 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3002 if (N->getValueType(0).getVectorNumElements() != 4)
3005 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3006 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3007 isUndefOrEqual(N->getMaskElt(1), 7) &&
3008 isUndefOrEqual(N->getMaskElt(2), 2) &&
3009 isUndefOrEqual(N->getMaskElt(3), 3);
3012 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3013 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3015 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3016 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3021 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3022 isUndefOrEqual(N->getMaskElt(1), 3) &&
3023 isUndefOrEqual(N->getMaskElt(2), 2) &&
3024 isUndefOrEqual(N->getMaskElt(3), 3);
3027 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3028 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3029 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3030 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3032 if (NumElems != 2 && NumElems != 4)
3035 for (unsigned i = 0; i < NumElems/2; ++i)
3036 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3039 for (unsigned i = NumElems/2; i < NumElems; ++i)
3040 if (!isUndefOrEqual(N->getMaskElt(i), i))
3046 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3047 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3048 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3049 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3051 if (NumElems != 2 && NumElems != 4)
3054 for (unsigned i = 0; i < NumElems/2; ++i)
3055 if (!isUndefOrEqual(N->getMaskElt(i), i))
3058 for (unsigned i = 0; i < NumElems/2; ++i)
3059 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3065 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3066 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3067 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3068 bool V2IsSplat = false) {
3069 int NumElts = VT.getVectorNumElements();
3070 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3073 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3075 int BitI1 = Mask[i+1];
3076 if (!isUndefOrEqual(BitI, j))
3079 if (!isUndefOrEqual(BitI1, NumElts))
3082 if (!isUndefOrEqual(BitI1, j + NumElts))
3089 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3090 SmallVector<int, 8> M;
3092 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3095 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3096 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3097 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3098 bool V2IsSplat = false) {
3099 int NumElts = VT.getVectorNumElements();
3100 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3103 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3105 int BitI1 = Mask[i+1];
3106 if (!isUndefOrEqual(BitI, j + NumElts/2))
3109 if (isUndefOrEqual(BitI1, NumElts))
3112 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3119 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3120 SmallVector<int, 8> M;
3122 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3125 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3126 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3128 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3129 int NumElems = VT.getVectorNumElements();
3130 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3133 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3135 int BitI1 = Mask[i+1];
3136 if (!isUndefOrEqual(BitI, j))
3138 if (!isUndefOrEqual(BitI1, j))
3144 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3145 SmallVector<int, 8> M;
3147 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3150 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3151 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3153 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3154 int NumElems = VT.getVectorNumElements();
3155 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3158 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3160 int BitI1 = Mask[i+1];
3161 if (!isUndefOrEqual(BitI, j))
3163 if (!isUndefOrEqual(BitI1, j))
3169 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3170 SmallVector<int, 8> M;
3172 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3175 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3176 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3177 /// MOVSD, and MOVD, i.e. setting the lowest element.
3178 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3179 if (VT.getVectorElementType().getSizeInBits() < 32)
3182 int NumElts = VT.getVectorNumElements();
3184 if (!isUndefOrEqual(Mask[0], NumElts))
3187 for (int i = 1; i < NumElts; ++i)
3188 if (!isUndefOrEqual(Mask[i], i))
3194 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3195 SmallVector<int, 8> M;
3197 return ::isMOVLMask(M, N->getValueType(0));
3200 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3201 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3202 /// element of vector 2 and the other elements to come from vector 1 in order.
3203 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3204 bool V2IsSplat = false, bool V2IsUndef = false) {
3205 int NumOps = VT.getVectorNumElements();
3206 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3209 if (!isUndefOrEqual(Mask[0], 0))
3212 for (int i = 1; i < NumOps; ++i)
3213 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3214 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3215 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3221 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3222 bool V2IsUndef = false) {
3223 SmallVector<int, 8> M;
3225 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3228 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3229 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3230 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3231 if (N->getValueType(0).getVectorNumElements() != 4)
3234 // Expect 1, 1, 3, 3
3235 for (unsigned i = 0; i < 2; ++i) {
3236 int Elt = N->getMaskElt(i);
3237 if (Elt >= 0 && Elt != 1)
3242 for (unsigned i = 2; i < 4; ++i) {
3243 int Elt = N->getMaskElt(i);
3244 if (Elt >= 0 && Elt != 3)
3249 // Don't use movshdup if it can be done with a shufps.
3250 // FIXME: verify that matching u, u, 3, 3 is what we want.
3254 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3255 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3256 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3257 if (N->getValueType(0).getVectorNumElements() != 4)
3260 // Expect 0, 0, 2, 2
3261 for (unsigned i = 0; i < 2; ++i)
3262 if (N->getMaskElt(i) > 0)
3266 for (unsigned i = 2; i < 4; ++i) {
3267 int Elt = N->getMaskElt(i);
3268 if (Elt >= 0 && Elt != 2)
3273 // Don't use movsldup if it can be done with a shufps.
3277 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3278 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3279 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3280 int e = N->getValueType(0).getVectorNumElements() / 2;
3282 for (int i = 0; i < e; ++i)
3283 if (!isUndefOrEqual(N->getMaskElt(i), i))
3285 for (int i = 0; i < e; ++i)
3286 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3291 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3292 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3293 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3294 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3295 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3297 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3299 for (int i = 0; i < NumOperands; ++i) {
3300 int Val = SVOp->getMaskElt(NumOperands-i-1);
3301 if (Val < 0) Val = 0;
3302 if (Val >= NumOperands) Val -= NumOperands;
3304 if (i != NumOperands - 1)
3310 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3311 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3312 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3313 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3315 // 8 nodes, but we only care about the last 4.
3316 for (unsigned i = 7; i >= 4; --i) {
3317 int Val = SVOp->getMaskElt(i);
3326 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3327 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3328 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3331 // 8 nodes, but we only care about the first 4.
3332 for (int i = 3; i >= 0; --i) {
3333 int Val = SVOp->getMaskElt(i);
3342 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3343 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3344 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3345 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3346 EVT VVT = N->getValueType(0);
3347 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3351 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3352 Val = SVOp->getMaskElt(i);
3356 return (Val - i) * EltSize;
3359 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3361 bool X86::isZeroNode(SDValue Elt) {
3362 return ((isa<ConstantSDNode>(Elt) &&
3363 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3364 (isa<ConstantFPSDNode>(Elt) &&
3365 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3368 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3369 /// their permute mask.
3370 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3371 SelectionDAG &DAG) {
3372 EVT VT = SVOp->getValueType(0);
3373 unsigned NumElems = VT.getVectorNumElements();
3374 SmallVector<int, 8> MaskVec;
3376 for (unsigned i = 0; i != NumElems; ++i) {
3377 int idx = SVOp->getMaskElt(i);
3379 MaskVec.push_back(idx);
3380 else if (idx < (int)NumElems)
3381 MaskVec.push_back(idx + NumElems);
3383 MaskVec.push_back(idx - NumElems);
3385 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3386 SVOp->getOperand(0), &MaskVec[0]);
3389 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3390 /// the two vector operands have swapped position.
3391 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3392 unsigned NumElems = VT.getVectorNumElements();
3393 for (unsigned i = 0; i != NumElems; ++i) {
3397 else if (idx < (int)NumElems)
3398 Mask[i] = idx + NumElems;
3400 Mask[i] = idx - NumElems;
3404 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3405 /// match movhlps. The lower half elements should come from upper half of
3406 /// V1 (and in order), and the upper half elements should come from the upper
3407 /// half of V2 (and in order).
3408 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3409 if (Op->getValueType(0).getVectorNumElements() != 4)
3411 for (unsigned i = 0, e = 2; i != e; ++i)
3412 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3414 for (unsigned i = 2; i != 4; ++i)
3415 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3420 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3421 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3423 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3424 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3426 N = N->getOperand(0).getNode();
3427 if (!ISD::isNON_EXTLoad(N))
3430 *LD = cast<LoadSDNode>(N);
3434 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3435 /// match movlp{s|d}. The lower half elements should come from lower half of
3436 /// V1 (and in order), and the upper half elements should come from the upper
3437 /// half of V2 (and in order). And since V1 will become the source of the
3438 /// MOVLP, it must be either a vector load or a scalar load to vector.
3439 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3440 ShuffleVectorSDNode *Op) {
3441 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3443 // Is V2 is a vector load, don't do this transformation. We will try to use
3444 // load folding shufps op.
3445 if (ISD::isNON_EXTLoad(V2))
3448 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3450 if (NumElems != 2 && NumElems != 4)
3452 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3453 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3455 for (unsigned i = NumElems/2; i != NumElems; ++i)
3456 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3461 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3463 static bool isSplatVector(SDNode *N) {
3464 if (N->getOpcode() != ISD::BUILD_VECTOR)
3467 SDValue SplatValue = N->getOperand(0);
3468 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3469 if (N->getOperand(i) != SplatValue)
3474 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3475 /// to an zero vector.
3476 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3477 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3478 SDValue V1 = N->getOperand(0);
3479 SDValue V2 = N->getOperand(1);
3480 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3481 for (unsigned i = 0; i != NumElems; ++i) {
3482 int Idx = N->getMaskElt(i);
3483 if (Idx >= (int)NumElems) {
3484 unsigned Opc = V2.getOpcode();
3485 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3487 if (Opc != ISD::BUILD_VECTOR ||
3488 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3490 } else if (Idx >= 0) {
3491 unsigned Opc = V1.getOpcode();
3492 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3494 if (Opc != ISD::BUILD_VECTOR ||
3495 !X86::isZeroNode(V1.getOperand(Idx)))
3502 /// getZeroVector - Returns a vector of specified type with all zero elements.
3504 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3506 assert(VT.isVector() && "Expected a vector type");
3508 // Always build SSE zero vectors as <4 x i32> bitcasted
3509 // to their dest type. This ensures they get CSE'd.
3511 if (VT.getSizeInBits() == 128) { // SSE
3512 if (HasSSE2) { // SSE2
3513 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3514 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3516 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3517 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3519 } else if (VT.getSizeInBits() == 256) { // AVX
3520 // 256-bit logic and arithmetic instructions in AVX are
3521 // all floating-point, no support for integer ops. Default
3522 // to emitting fp zeroed vectors then.
3523 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3524 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3525 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3527 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3530 /// getOnesVector - Returns a vector of specified type with all bits set.
3532 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3533 assert(VT.isVector() && "Expected a vector type");
3535 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3536 // type. This ensures they get CSE'd.
3537 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3539 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3540 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3544 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3545 /// that point to V2 points to its first element.
3546 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3547 EVT VT = SVOp->getValueType(0);
3548 unsigned NumElems = VT.getVectorNumElements();
3550 bool Changed = false;
3551 SmallVector<int, 8> MaskVec;
3552 SVOp->getMask(MaskVec);
3554 for (unsigned i = 0; i != NumElems; ++i) {
3555 if (MaskVec[i] > (int)NumElems) {
3556 MaskVec[i] = NumElems;
3561 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3562 SVOp->getOperand(1), &MaskVec[0]);
3563 return SDValue(SVOp, 0);
3566 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3567 /// operation of specified width.
3568 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3570 unsigned NumElems = VT.getVectorNumElements();
3571 SmallVector<int, 8> Mask;
3572 Mask.push_back(NumElems);
3573 for (unsigned i = 1; i != NumElems; ++i)
3575 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3578 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3579 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3581 unsigned NumElems = VT.getVectorNumElements();
3582 SmallVector<int, 8> Mask;
3583 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3585 Mask.push_back(i + NumElems);
3587 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3590 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3591 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3593 unsigned NumElems = VT.getVectorNumElements();
3594 unsigned Half = NumElems/2;
3595 SmallVector<int, 8> Mask;
3596 for (unsigned i = 0; i != Half; ++i) {
3597 Mask.push_back(i + Half);
3598 Mask.push_back(i + NumElems + Half);
3600 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3603 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3604 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3605 EVT PVT = MVT::v4f32;
3606 EVT VT = SV->getValueType(0);
3607 DebugLoc dl = SV->getDebugLoc();
3608 SDValue V1 = SV->getOperand(0);
3609 int NumElems = VT.getVectorNumElements();
3610 int EltNo = SV->getSplatIndex();
3612 // unpack elements to the correct location
3613 while (NumElems > 4) {
3614 if (EltNo < NumElems/2) {
3615 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3617 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3618 EltNo -= NumElems/2;
3623 // Perform the splat.
3624 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3625 V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1);
3626 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3627 return DAG.getNode(ISD::BITCAST, dl, VT, V1);
3630 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3631 /// vector of zero or undef vector. This produces a shuffle where the low
3632 /// element of V2 is swizzled into the zero/undef vector, landing at element
3633 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3634 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3635 bool isZero, bool HasSSE2,
3636 SelectionDAG &DAG) {
3637 EVT VT = V2.getValueType();
3639 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3640 unsigned NumElems = VT.getVectorNumElements();
3641 SmallVector<int, 16> MaskVec;
3642 for (unsigned i = 0; i != NumElems; ++i)
3643 // If this is the insertion idx, put the low elt of V2 here.
3644 MaskVec.push_back(i == Idx ? NumElems : i);
3645 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3648 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3649 /// element of the result of the vector shuffle.
3650 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3653 return SDValue(); // Limit search depth.
3655 SDValue V = SDValue(N, 0);
3656 EVT VT = V.getValueType();
3657 unsigned Opcode = V.getOpcode();
3659 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3660 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3661 Index = SV->getMaskElt(Index);
3664 return DAG.getUNDEF(VT.getVectorElementType());
3666 int NumElems = VT.getVectorNumElements();
3667 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3668 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3671 // Recurse into target specific vector shuffles to find scalars.
3672 if (isTargetShuffle(Opcode)) {
3673 int NumElems = VT.getVectorNumElements();
3674 SmallVector<unsigned, 16> ShuffleMask;
3678 case X86ISD::SHUFPS:
3679 case X86ISD::SHUFPD:
3680 ImmN = N->getOperand(N->getNumOperands()-1);
3681 DecodeSHUFPSMask(NumElems,
3682 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3685 case X86ISD::PUNPCKHBW:
3686 case X86ISD::PUNPCKHWD:
3687 case X86ISD::PUNPCKHDQ:
3688 case X86ISD::PUNPCKHQDQ:
3689 DecodePUNPCKHMask(NumElems, ShuffleMask);
3691 case X86ISD::UNPCKHPS:
3692 case X86ISD::UNPCKHPD:
3693 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3695 case X86ISD::PUNPCKLBW:
3696 case X86ISD::PUNPCKLWD:
3697 case X86ISD::PUNPCKLDQ:
3698 case X86ISD::PUNPCKLQDQ:
3699 DecodePUNPCKLMask(NumElems, ShuffleMask);
3701 case X86ISD::UNPCKLPS:
3702 case X86ISD::UNPCKLPD:
3703 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3705 case X86ISD::MOVHLPS:
3706 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3708 case X86ISD::MOVLHPS:
3709 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3711 case X86ISD::PSHUFD:
3712 ImmN = N->getOperand(N->getNumOperands()-1);
3713 DecodePSHUFMask(NumElems,
3714 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3717 case X86ISD::PSHUFHW:
3718 ImmN = N->getOperand(N->getNumOperands()-1);
3719 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3722 case X86ISD::PSHUFLW:
3723 ImmN = N->getOperand(N->getNumOperands()-1);
3724 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3728 case X86ISD::MOVSD: {
3729 // The index 0 always comes from the first element of the second source,
3730 // this is why MOVSS and MOVSD are used in the first place. The other
3731 // elements come from the other positions of the first source vector.
3732 unsigned OpNum = (Index == 0) ? 1 : 0;
3733 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3737 assert("not implemented for target shuffle node");
3741 Index = ShuffleMask[Index];
3743 return DAG.getUNDEF(VT.getVectorElementType());
3745 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3746 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3750 // Actual nodes that may contain scalar elements
3751 if (Opcode == ISD::BITCAST) {
3752 V = V.getOperand(0);
3753 EVT SrcVT = V.getValueType();
3754 unsigned NumElems = VT.getVectorNumElements();
3756 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3760 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3761 return (Index == 0) ? V.getOperand(0)
3762 : DAG.getUNDEF(VT.getVectorElementType());
3764 if (V.getOpcode() == ISD::BUILD_VECTOR)
3765 return V.getOperand(Index);
3770 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3771 /// shuffle operation which come from a consecutively from a zero. The
3772 /// search can start in two diferent directions, from left or right.
3774 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3775 bool ZerosFromLeft, SelectionDAG &DAG) {
3778 while (i < NumElems) {
3779 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3780 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3781 if (!(Elt.getNode() &&
3782 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3790 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3791 /// MaskE correspond consecutively to elements from one of the vector operands,
3792 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3794 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3795 int OpIdx, int NumElems, unsigned &OpNum) {
3796 bool SeenV1 = false;
3797 bool SeenV2 = false;
3799 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3800 int Idx = SVOp->getMaskElt(i);
3801 // Ignore undef indicies
3810 // Only accept consecutive elements from the same vector
3811 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3815 OpNum = SeenV1 ? 0 : 1;
3819 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3820 /// logical left shift of a vector.
3821 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3822 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3823 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3824 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3825 false /* check zeros from right */, DAG);
3831 // Considering the elements in the mask that are not consecutive zeros,
3832 // check if they consecutively come from only one of the source vectors.
3834 // V1 = {X, A, B, C} 0
3836 // vector_shuffle V1, V2 <1, 2, 3, X>
3838 if (!isShuffleMaskConsecutive(SVOp,
3839 0, // Mask Start Index
3840 NumElems-NumZeros-1, // Mask End Index
3841 NumZeros, // Where to start looking in the src vector
3842 NumElems, // Number of elements in vector
3843 OpSrc)) // Which source operand ?
3848 ShVal = SVOp->getOperand(OpSrc);
3852 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3853 /// logical left shift of a vector.
3854 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3855 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3856 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3857 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3858 true /* check zeros from left */, DAG);
3864 // Considering the elements in the mask that are not consecutive zeros,
3865 // check if they consecutively come from only one of the source vectors.
3867 // 0 { A, B, X, X } = V2
3869 // vector_shuffle V1, V2 <X, X, 4, 5>
3871 if (!isShuffleMaskConsecutive(SVOp,
3872 NumZeros, // Mask Start Index
3873 NumElems-1, // Mask End Index
3874 0, // Where to start looking in the src vector
3875 NumElems, // Number of elements in vector
3876 OpSrc)) // Which source operand ?
3881 ShVal = SVOp->getOperand(OpSrc);
3885 /// isVectorShift - Returns true if the shuffle can be implemented as a
3886 /// logical left or right shift of a vector.
3887 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3888 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3889 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3890 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3896 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3898 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3899 unsigned NumNonZero, unsigned NumZero,
3901 const TargetLowering &TLI) {
3905 DebugLoc dl = Op.getDebugLoc();
3908 for (unsigned i = 0; i < 16; ++i) {
3909 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3910 if (ThisIsNonZero && First) {
3912 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3914 V = DAG.getUNDEF(MVT::v8i16);
3919 SDValue ThisElt(0, 0), LastElt(0, 0);
3920 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3921 if (LastIsNonZero) {
3922 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3923 MVT::i16, Op.getOperand(i-1));
3925 if (ThisIsNonZero) {
3926 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3927 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3928 ThisElt, DAG.getConstant(8, MVT::i8));
3930 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3934 if (ThisElt.getNode())
3935 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3936 DAG.getIntPtrConstant(i/2));
3940 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
3943 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3945 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3946 unsigned NumNonZero, unsigned NumZero,
3948 const TargetLowering &TLI) {
3952 DebugLoc dl = Op.getDebugLoc();
3955 for (unsigned i = 0; i < 8; ++i) {
3956 bool isNonZero = (NonZeros & (1 << i)) != 0;
3960 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3962 V = DAG.getUNDEF(MVT::v8i16);
3965 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3966 MVT::v8i16, V, Op.getOperand(i),
3967 DAG.getIntPtrConstant(i));
3974 /// getVShift - Return a vector logical shift node.
3976 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3977 unsigned NumBits, SelectionDAG &DAG,
3978 const TargetLowering &TLI, DebugLoc dl) {
3979 EVT ShVT = MVT::v2i64;
3980 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3981 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
3982 return DAG.getNode(ISD::BITCAST, dl, VT,
3983 DAG.getNode(Opc, dl, ShVT, SrcOp,
3984 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3988 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3989 SelectionDAG &DAG) const {
3991 // Check if the scalar load can be widened into a vector load. And if
3992 // the address is "base + cst" see if the cst can be "absorbed" into
3993 // the shuffle mask.
3994 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3995 SDValue Ptr = LD->getBasePtr();
3996 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3998 EVT PVT = LD->getValueType(0);
3999 if (PVT != MVT::i32 && PVT != MVT::f32)
4004 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4005 FI = FINode->getIndex();
4007 } else if (Ptr.getOpcode() == ISD::ADD &&
4008 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4009 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4010 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4011 Offset = Ptr.getConstantOperandVal(1);
4012 Ptr = Ptr.getOperand(0);
4017 SDValue Chain = LD->getChain();
4018 // Make sure the stack object alignment is at least 16.
4019 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4020 if (DAG.InferPtrAlignment(Ptr) < 16) {
4021 if (MFI->isFixedObjectIndex(FI)) {
4022 // Can't change the alignment. FIXME: It's possible to compute
4023 // the exact stack offset and reference FI + adjust offset instead.
4024 // If someone *really* cares about this. That's the way to implement it.
4027 MFI->setObjectAlignment(FI, 16);
4031 // (Offset % 16) must be multiple of 4. Then address is then
4032 // Ptr + (Offset & ~15).
4035 if ((Offset % 16) & 3)
4037 int64_t StartOffset = Offset & ~15;
4039 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4040 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4042 int EltNo = (Offset - StartOffset) >> 2;
4043 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4044 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4045 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4046 LD->getPointerInfo().getWithOffset(StartOffset),
4048 // Canonicalize it to a v4i32 shuffle.
4049 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
4050 return DAG.getNode(ISD::BITCAST, dl, VT,
4051 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4052 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4058 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4059 /// vector of type 'VT', see if the elements can be replaced by a single large
4060 /// load which has the same value as a build_vector whose operands are 'elts'.
4062 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4064 /// FIXME: we'd also like to handle the case where the last elements are zero
4065 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4066 /// There's even a handy isZeroNode for that purpose.
4067 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4068 DebugLoc &DL, SelectionDAG &DAG) {
4069 EVT EltVT = VT.getVectorElementType();
4070 unsigned NumElems = Elts.size();
4072 LoadSDNode *LDBase = NULL;
4073 unsigned LastLoadedElt = -1U;
4075 // For each element in the initializer, see if we've found a load or an undef.
4076 // If we don't find an initial load element, or later load elements are
4077 // non-consecutive, bail out.
4078 for (unsigned i = 0; i < NumElems; ++i) {
4079 SDValue Elt = Elts[i];
4081 if (!Elt.getNode() ||
4082 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4085 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4087 LDBase = cast<LoadSDNode>(Elt.getNode());
4091 if (Elt.getOpcode() == ISD::UNDEF)
4094 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4095 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4100 // If we have found an entire vector of loads and undefs, then return a large
4101 // load of the entire vector width starting at the base pointer. If we found
4102 // consecutive loads for the low half, generate a vzext_load node.
4103 if (LastLoadedElt == NumElems - 1) {
4104 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4105 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4106 LDBase->getPointerInfo(),
4107 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4108 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4109 LDBase->getPointerInfo(),
4110 LDBase->isVolatile(), LDBase->isNonTemporal(),
4111 LDBase->getAlignment());
4112 } else if (NumElems == 4 && LastLoadedElt == 1) {
4113 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4114 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4115 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4117 LDBase->getMemOperand());
4118 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4124 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4125 DebugLoc dl = Op.getDebugLoc();
4126 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4127 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4128 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4129 // is present, so AllOnes is ignored.
4130 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4131 (Op.getValueType().getSizeInBits() != 256 &&
4132 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4133 // Canonicalize this to <4 x i32> (SSE) to
4134 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4135 // eliminated on x86-32 hosts.
4136 if (Op.getValueType() == MVT::v4i32)
4139 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4140 return getOnesVector(Op.getValueType(), DAG, dl);
4141 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4144 EVT VT = Op.getValueType();
4145 EVT ExtVT = VT.getVectorElementType();
4146 unsigned EVTBits = ExtVT.getSizeInBits();
4148 unsigned NumElems = Op.getNumOperands();
4149 unsigned NumZero = 0;
4150 unsigned NumNonZero = 0;
4151 unsigned NonZeros = 0;
4152 bool IsAllConstants = true;
4153 SmallSet<SDValue, 8> Values;
4154 for (unsigned i = 0; i < NumElems; ++i) {
4155 SDValue Elt = Op.getOperand(i);
4156 if (Elt.getOpcode() == ISD::UNDEF)
4159 if (Elt.getOpcode() != ISD::Constant &&
4160 Elt.getOpcode() != ISD::ConstantFP)
4161 IsAllConstants = false;
4162 if (X86::isZeroNode(Elt))
4165 NonZeros |= (1 << i);
4170 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4171 if (NumNonZero == 0)
4172 return DAG.getUNDEF(VT);
4174 // Special case for single non-zero, non-undef, element.
4175 if (NumNonZero == 1) {
4176 unsigned Idx = CountTrailingZeros_32(NonZeros);
4177 SDValue Item = Op.getOperand(Idx);
4179 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4180 // the value are obviously zero, truncate the value to i32 and do the
4181 // insertion that way. Only do this if the value is non-constant or if the
4182 // value is a constant being inserted into element 0. It is cheaper to do
4183 // a constant pool load than it is to do a movd + shuffle.
4184 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4185 (!IsAllConstants || Idx == 0)) {
4186 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4188 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4189 EVT VecVT = MVT::v4i32;
4190 unsigned VecElts = 4;
4192 // Truncate the value (which may itself be a constant) to i32, and
4193 // convert it to a vector with movd (S2V+shuffle to zero extend).
4194 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4195 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4196 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4197 Subtarget->hasSSE2(), DAG);
4199 // Now we have our 32-bit value zero extended in the low element of
4200 // a vector. If Idx != 0, swizzle it into place.
4202 SmallVector<int, 4> Mask;
4203 Mask.push_back(Idx);
4204 for (unsigned i = 1; i != VecElts; ++i)
4206 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4207 DAG.getUNDEF(Item.getValueType()),
4210 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4214 // If we have a constant or non-constant insertion into the low element of
4215 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4216 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4217 // depending on what the source datatype is.
4220 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4221 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4222 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4223 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4224 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4225 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4227 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4228 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4229 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4230 EVT MiddleVT = MVT::v4i32;
4231 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4232 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4233 Subtarget->hasSSE2(), DAG);
4234 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4238 // Is it a vector logical left shift?
4239 if (NumElems == 2 && Idx == 1 &&
4240 X86::isZeroNode(Op.getOperand(0)) &&
4241 !X86::isZeroNode(Op.getOperand(1))) {
4242 unsigned NumBits = VT.getSizeInBits();
4243 return getVShift(true, VT,
4244 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4245 VT, Op.getOperand(1)),
4246 NumBits/2, DAG, *this, dl);
4249 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4252 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4253 // is a non-constant being inserted into an element other than the low one,
4254 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4255 // movd/movss) to move this into the low element, then shuffle it into
4257 if (EVTBits == 32) {
4258 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4260 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4261 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4262 Subtarget->hasSSE2(), DAG);
4263 SmallVector<int, 8> MaskVec;
4264 for (unsigned i = 0; i < NumElems; i++)
4265 MaskVec.push_back(i == Idx ? 0 : 1);
4266 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4270 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4271 if (Values.size() == 1) {
4272 if (EVTBits == 32) {
4273 // Instead of a shuffle like this:
4274 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4275 // Check if it's possible to issue this instead.
4276 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4277 unsigned Idx = CountTrailingZeros_32(NonZeros);
4278 SDValue Item = Op.getOperand(Idx);
4279 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4280 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4285 // A vector full of immediates; various special cases are already
4286 // handled, so this is best done with a single constant-pool load.
4290 // Let legalizer expand 2-wide build_vectors.
4291 if (EVTBits == 64) {
4292 if (NumNonZero == 1) {
4293 // One half is zero or undef.
4294 unsigned Idx = CountTrailingZeros_32(NonZeros);
4295 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4296 Op.getOperand(Idx));
4297 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4298 Subtarget->hasSSE2(), DAG);
4303 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4304 if (EVTBits == 8 && NumElems == 16) {
4305 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4307 if (V.getNode()) return V;
4310 if (EVTBits == 16 && NumElems == 8) {
4311 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4313 if (V.getNode()) return V;
4316 // If element VT is == 32 bits, turn it into a number of shuffles.
4317 SmallVector<SDValue, 8> V;
4319 if (NumElems == 4 && NumZero > 0) {
4320 for (unsigned i = 0; i < 4; ++i) {
4321 bool isZero = !(NonZeros & (1 << i));
4323 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4325 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4328 for (unsigned i = 0; i < 2; ++i) {
4329 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4332 V[i] = V[i*2]; // Must be a zero vector.
4335 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4338 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4341 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4346 SmallVector<int, 8> MaskVec;
4347 bool Reverse = (NonZeros & 0x3) == 2;
4348 for (unsigned i = 0; i < 2; ++i)
4349 MaskVec.push_back(Reverse ? 1-i : i);
4350 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4351 for (unsigned i = 0; i < 2; ++i)
4352 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4353 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4356 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4357 // Check for a build vector of consecutive loads.
4358 for (unsigned i = 0; i < NumElems; ++i)
4359 V[i] = Op.getOperand(i);
4361 // Check for elements which are consecutive loads.
4362 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4366 // For SSE 4.1, use insertps to put the high elements into the low element.
4367 if (getSubtarget()->hasSSE41()) {
4369 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4370 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4372 Result = DAG.getUNDEF(VT);
4374 for (unsigned i = 1; i < NumElems; ++i) {
4375 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4376 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4377 Op.getOperand(i), DAG.getIntPtrConstant(i));
4382 // Otherwise, expand into a number of unpckl*, start by extending each of
4383 // our (non-undef) elements to the full vector width with the element in the
4384 // bottom slot of the vector (which generates no code for SSE).
4385 for (unsigned i = 0; i < NumElems; ++i) {
4386 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4387 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4389 V[i] = DAG.getUNDEF(VT);
4392 // Next, we iteratively mix elements, e.g. for v4f32:
4393 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4394 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4395 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4396 unsigned EltStride = NumElems >> 1;
4397 while (EltStride != 0) {
4398 for (unsigned i = 0; i < EltStride; ++i) {
4399 // If V[i+EltStride] is undef and this is the first round of mixing,
4400 // then it is safe to just drop this shuffle: V[i] is already in the
4401 // right place, the one element (since it's the first round) being
4402 // inserted as undef can be dropped. This isn't safe for successive
4403 // rounds because they will permute elements within both vectors.
4404 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4405 EltStride == NumElems/2)
4408 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4418 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4419 // We support concatenate two MMX registers and place them in a MMX
4420 // register. This is better than doing a stack convert.
4421 DebugLoc dl = Op.getDebugLoc();
4422 EVT ResVT = Op.getValueType();
4423 assert(Op.getNumOperands() == 2);
4424 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4425 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4427 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
4428 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4429 InVec = Op.getOperand(1);
4430 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4431 unsigned NumElts = ResVT.getVectorNumElements();
4432 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4433 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4434 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4436 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
4437 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4438 Mask[0] = 0; Mask[1] = 2;
4439 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4441 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4444 // v8i16 shuffles - Prefer shuffles in the following order:
4445 // 1. [all] pshuflw, pshufhw, optional move
4446 // 2. [ssse3] 1 x pshufb
4447 // 3. [ssse3] 2 x pshufb + 1 x por
4448 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4450 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4451 SelectionDAG &DAG) const {
4452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4453 SDValue V1 = SVOp->getOperand(0);
4454 SDValue V2 = SVOp->getOperand(1);
4455 DebugLoc dl = SVOp->getDebugLoc();
4456 SmallVector<int, 8> MaskVals;
4458 // Determine if more than 1 of the words in each of the low and high quadwords
4459 // of the result come from the same quadword of one of the two inputs. Undef
4460 // mask values count as coming from any quadword, for better codegen.
4461 SmallVector<unsigned, 4> LoQuad(4);
4462 SmallVector<unsigned, 4> HiQuad(4);
4463 BitVector InputQuads(4);
4464 for (unsigned i = 0; i < 8; ++i) {
4465 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4466 int EltIdx = SVOp->getMaskElt(i);
4467 MaskVals.push_back(EltIdx);
4476 InputQuads.set(EltIdx / 4);
4479 int BestLoQuad = -1;
4480 unsigned MaxQuad = 1;
4481 for (unsigned i = 0; i < 4; ++i) {
4482 if (LoQuad[i] > MaxQuad) {
4484 MaxQuad = LoQuad[i];
4488 int BestHiQuad = -1;
4490 for (unsigned i = 0; i < 4; ++i) {
4491 if (HiQuad[i] > MaxQuad) {
4493 MaxQuad = HiQuad[i];
4497 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4498 // of the two input vectors, shuffle them into one input vector so only a
4499 // single pshufb instruction is necessary. If There are more than 2 input
4500 // quads, disable the next transformation since it does not help SSSE3.
4501 bool V1Used = InputQuads[0] || InputQuads[1];
4502 bool V2Used = InputQuads[2] || InputQuads[3];
4503 if (Subtarget->hasSSSE3()) {
4504 if (InputQuads.count() == 2 && V1Used && V2Used) {
4505 BestLoQuad = InputQuads.find_first();
4506 BestHiQuad = InputQuads.find_next(BestLoQuad);
4508 if (InputQuads.count() > 2) {
4514 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4515 // the shuffle mask. If a quad is scored as -1, that means that it contains
4516 // words from all 4 input quadwords.
4518 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4519 SmallVector<int, 8> MaskV;
4520 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4521 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4522 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4523 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
4524 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
4525 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
4527 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4528 // source words for the shuffle, to aid later transformations.
4529 bool AllWordsInNewV = true;
4530 bool InOrder[2] = { true, true };
4531 for (unsigned i = 0; i != 8; ++i) {
4532 int idx = MaskVals[i];
4534 InOrder[i/4] = false;
4535 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4537 AllWordsInNewV = false;
4541 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4542 if (AllWordsInNewV) {
4543 for (int i = 0; i != 8; ++i) {
4544 int idx = MaskVals[i];
4547 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4548 if ((idx != i) && idx < 4)
4550 if ((idx != i) && idx > 3)
4559 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4560 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4561 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4562 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4563 unsigned TargetMask = 0;
4564 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4565 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4566 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4567 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4568 V1 = NewV.getOperand(0);
4569 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4573 // If we have SSSE3, and all words of the result are from 1 input vector,
4574 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4575 // is present, fall back to case 4.
4576 if (Subtarget->hasSSSE3()) {
4577 SmallVector<SDValue,16> pshufbMask;
4579 // If we have elements from both input vectors, set the high bit of the
4580 // shuffle mask element to zero out elements that come from V2 in the V1
4581 // mask, and elements that come from V1 in the V2 mask, so that the two
4582 // results can be OR'd together.
4583 bool TwoInputs = V1Used && V2Used;
4584 for (unsigned i = 0; i != 8; ++i) {
4585 int EltIdx = MaskVals[i] * 2;
4586 if (TwoInputs && (EltIdx >= 16)) {
4587 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4588 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4591 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4592 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4594 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
4595 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4596 DAG.getNode(ISD::BUILD_VECTOR, dl,
4597 MVT::v16i8, &pshufbMask[0], 16));
4599 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4601 // Calculate the shuffle mask for the second input, shuffle it, and
4602 // OR it with the first shuffled input.
4604 for (unsigned i = 0; i != 8; ++i) {
4605 int EltIdx = MaskVals[i] * 2;
4607 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4608 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4611 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4612 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4614 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
4615 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4616 DAG.getNode(ISD::BUILD_VECTOR, dl,
4617 MVT::v16i8, &pshufbMask[0], 16));
4618 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4619 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4622 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4623 // and update MaskVals with new element order.
4624 BitVector InOrder(8);
4625 if (BestLoQuad >= 0) {
4626 SmallVector<int, 8> MaskV;
4627 for (int i = 0; i != 4; ++i) {
4628 int idx = MaskVals[i];
4630 MaskV.push_back(-1);
4632 } else if ((idx / 4) == BestLoQuad) {
4633 MaskV.push_back(idx & 3);
4636 MaskV.push_back(-1);
4639 for (unsigned i = 4; i != 8; ++i)
4641 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4644 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4645 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4647 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4651 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4652 // and update MaskVals with the new element order.
4653 if (BestHiQuad >= 0) {
4654 SmallVector<int, 8> MaskV;
4655 for (unsigned i = 0; i != 4; ++i)
4657 for (unsigned i = 4; i != 8; ++i) {
4658 int idx = MaskVals[i];
4660 MaskV.push_back(-1);
4662 } else if ((idx / 4) == BestHiQuad) {
4663 MaskV.push_back((idx & 3) + 4);
4666 MaskV.push_back(-1);
4669 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4672 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4673 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4675 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4679 // In case BestHi & BestLo were both -1, which means each quadword has a word
4680 // from each of the four input quadwords, calculate the InOrder bitvector now
4681 // before falling through to the insert/extract cleanup.
4682 if (BestLoQuad == -1 && BestHiQuad == -1) {
4684 for (int i = 0; i != 8; ++i)
4685 if (MaskVals[i] < 0 || MaskVals[i] == i)
4689 // The other elements are put in the right place using pextrw and pinsrw.
4690 for (unsigned i = 0; i != 8; ++i) {
4693 int EltIdx = MaskVals[i];
4696 SDValue ExtOp = (EltIdx < 8)
4697 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4698 DAG.getIntPtrConstant(EltIdx))
4699 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4700 DAG.getIntPtrConstant(EltIdx - 8));
4701 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4702 DAG.getIntPtrConstant(i));
4707 // v16i8 shuffles - Prefer shuffles in the following order:
4708 // 1. [ssse3] 1 x pshufb
4709 // 2. [ssse3] 2 x pshufb + 1 x por
4710 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4712 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4714 const X86TargetLowering &TLI) {
4715 SDValue V1 = SVOp->getOperand(0);
4716 SDValue V2 = SVOp->getOperand(1);
4717 DebugLoc dl = SVOp->getDebugLoc();
4718 SmallVector<int, 16> MaskVals;
4719 SVOp->getMask(MaskVals);
4721 // If we have SSSE3, case 1 is generated when all result bytes come from
4722 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4723 // present, fall back to case 3.
4724 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4727 for (unsigned i = 0; i < 16; ++i) {
4728 int EltIdx = MaskVals[i];
4737 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4738 if (TLI.getSubtarget()->hasSSSE3()) {
4739 SmallVector<SDValue,16> pshufbMask;
4741 // If all result elements are from one input vector, then only translate
4742 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4744 // Otherwise, we have elements from both input vectors, and must zero out
4745 // elements that come from V2 in the first mask, and V1 in the second mask
4746 // so that we can OR them together.
4747 bool TwoInputs = !(V1Only || V2Only);
4748 for (unsigned i = 0; i != 16; ++i) {
4749 int EltIdx = MaskVals[i];
4750 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4751 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4754 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4756 // If all the elements are from V2, assign it to V1 and return after
4757 // building the first pshufb.
4760 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4761 DAG.getNode(ISD::BUILD_VECTOR, dl,
4762 MVT::v16i8, &pshufbMask[0], 16));
4766 // Calculate the shuffle mask for the second input, shuffle it, and
4767 // OR it with the first shuffled input.
4769 for (unsigned i = 0; i != 16; ++i) {
4770 int EltIdx = MaskVals[i];
4772 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4775 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4777 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4778 DAG.getNode(ISD::BUILD_VECTOR, dl,
4779 MVT::v16i8, &pshufbMask[0], 16));
4780 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4783 // No SSSE3 - Calculate in place words and then fix all out of place words
4784 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4785 // the 16 different words that comprise the two doublequadword input vectors.
4786 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4787 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
4788 SDValue NewV = V2Only ? V2 : V1;
4789 for (int i = 0; i != 8; ++i) {
4790 int Elt0 = MaskVals[i*2];
4791 int Elt1 = MaskVals[i*2+1];
4793 // This word of the result is all undef, skip it.
4794 if (Elt0 < 0 && Elt1 < 0)
4797 // This word of the result is already in the correct place, skip it.
4798 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4800 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4803 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4804 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4807 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4808 // using a single extract together, load it and store it.
4809 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4810 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4811 DAG.getIntPtrConstant(Elt1 / 2));
4812 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4813 DAG.getIntPtrConstant(i));
4817 // If Elt1 is defined, extract it from the appropriate source. If the
4818 // source byte is not also odd, shift the extracted word left 8 bits
4819 // otherwise clear the bottom 8 bits if we need to do an or.
4821 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4822 DAG.getIntPtrConstant(Elt1 / 2));
4823 if ((Elt1 & 1) == 0)
4824 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4825 DAG.getConstant(8, TLI.getShiftAmountTy()));
4827 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4828 DAG.getConstant(0xFF00, MVT::i16));
4830 // If Elt0 is defined, extract it from the appropriate source. If the
4831 // source byte is not also even, shift the extracted word right 8 bits. If
4832 // Elt1 was also defined, OR the extracted values together before
4833 // inserting them in the result.
4835 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4836 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4837 if ((Elt0 & 1) != 0)
4838 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4839 DAG.getConstant(8, TLI.getShiftAmountTy()));
4841 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4842 DAG.getConstant(0x00FF, MVT::i16));
4843 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4846 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4847 DAG.getIntPtrConstant(i));
4849 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
4852 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4853 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
4854 /// done when every pair / quad of shuffle mask elements point to elements in
4855 /// the right sequence. e.g.
4856 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
4858 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4859 SelectionDAG &DAG, DebugLoc dl) {
4860 EVT VT = SVOp->getValueType(0);
4861 SDValue V1 = SVOp->getOperand(0);
4862 SDValue V2 = SVOp->getOperand(1);
4863 unsigned NumElems = VT.getVectorNumElements();
4864 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4866 switch (VT.getSimpleVT().SimpleTy) {
4867 default: assert(false && "Unexpected!");
4868 case MVT::v4f32: NewVT = MVT::v2f64; break;
4869 case MVT::v4i32: NewVT = MVT::v2i64; break;
4870 case MVT::v8i16: NewVT = MVT::v4i32; break;
4871 case MVT::v16i8: NewVT = MVT::v4i32; break;
4874 int Scale = NumElems / NewWidth;
4875 SmallVector<int, 8> MaskVec;
4876 for (unsigned i = 0; i < NumElems; i += Scale) {
4878 for (int j = 0; j < Scale; ++j) {
4879 int EltIdx = SVOp->getMaskElt(i+j);
4883 StartIdx = EltIdx - (EltIdx % Scale);
4884 if (EltIdx != StartIdx + j)
4888 MaskVec.push_back(-1);
4890 MaskVec.push_back(StartIdx / Scale);
4893 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
4894 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
4895 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4898 /// getVZextMovL - Return a zero-extending vector move low node.
4900 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4901 SDValue SrcOp, SelectionDAG &DAG,
4902 const X86Subtarget *Subtarget, DebugLoc dl) {
4903 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4904 LoadSDNode *LD = NULL;
4905 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4906 LD = dyn_cast<LoadSDNode>(SrcOp);
4908 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4910 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4911 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
4912 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4913 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
4914 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4916 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4917 return DAG.getNode(ISD::BITCAST, dl, VT,
4918 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4919 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4927 return DAG.getNode(ISD::BITCAST, dl, VT,
4928 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4929 DAG.getNode(ISD::BITCAST, dl,
4933 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4936 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4937 SDValue V1 = SVOp->getOperand(0);
4938 SDValue V2 = SVOp->getOperand(1);
4939 DebugLoc dl = SVOp->getDebugLoc();
4940 EVT VT = SVOp->getValueType(0);
4942 SmallVector<std::pair<int, int>, 8> Locs;
4944 SmallVector<int, 8> Mask1(4U, -1);
4945 SmallVector<int, 8> PermMask;
4946 SVOp->getMask(PermMask);
4950 for (unsigned i = 0; i != 4; ++i) {
4951 int Idx = PermMask[i];
4953 Locs[i] = std::make_pair(-1, -1);
4955 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4957 Locs[i] = std::make_pair(0, NumLo);
4961 Locs[i] = std::make_pair(1, NumHi);
4963 Mask1[2+NumHi] = Idx;
4969 if (NumLo <= 2 && NumHi <= 2) {
4970 // If no more than two elements come from either vector. This can be
4971 // implemented with two shuffles. First shuffle gather the elements.
4972 // The second shuffle, which takes the first shuffle as both of its
4973 // vector operands, put the elements into the right order.
4974 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4976 SmallVector<int, 8> Mask2(4U, -1);
4978 for (unsigned i = 0; i != 4; ++i) {
4979 if (Locs[i].first == -1)
4982 unsigned Idx = (i < 2) ? 0 : 4;
4983 Idx += Locs[i].first * 2 + Locs[i].second;
4988 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4989 } else if (NumLo == 3 || NumHi == 3) {
4990 // Otherwise, we must have three elements from one vector, call it X, and
4991 // one element from the other, call it Y. First, use a shufps to build an
4992 // intermediate vector with the one element from Y and the element from X
4993 // that will be in the same half in the final destination (the indexes don't
4994 // matter). Then, use a shufps to build the final vector, taking the half
4995 // containing the element from Y from the intermediate, and the other half
4998 // Normalize it so the 3 elements come from V1.
4999 CommuteVectorShuffleMask(PermMask, VT);
5003 // Find the element from V2.
5005 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5006 int Val = PermMask[HiIndex];
5013 Mask1[0] = PermMask[HiIndex];
5015 Mask1[2] = PermMask[HiIndex^1];
5017 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5020 Mask1[0] = PermMask[0];
5021 Mask1[1] = PermMask[1];
5022 Mask1[2] = HiIndex & 1 ? 6 : 4;
5023 Mask1[3] = HiIndex & 1 ? 4 : 6;
5024 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5026 Mask1[0] = HiIndex & 1 ? 2 : 0;
5027 Mask1[1] = HiIndex & 1 ? 0 : 2;
5028 Mask1[2] = PermMask[2];
5029 Mask1[3] = PermMask[3];
5034 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5038 // Break it into (shuffle shuffle_hi, shuffle_lo).
5040 SmallVector<int,8> LoMask(4U, -1);
5041 SmallVector<int,8> HiMask(4U, -1);
5043 SmallVector<int,8> *MaskPtr = &LoMask;
5044 unsigned MaskIdx = 0;
5047 for (unsigned i = 0; i != 4; ++i) {
5054 int Idx = PermMask[i];
5056 Locs[i] = std::make_pair(-1, -1);
5057 } else if (Idx < 4) {
5058 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5059 (*MaskPtr)[LoIdx] = Idx;
5062 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5063 (*MaskPtr)[HiIdx] = Idx;
5068 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5069 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5070 SmallVector<int, 8> MaskOps;
5071 for (unsigned i = 0; i != 4; ++i) {
5072 if (Locs[i].first == -1) {
5073 MaskOps.push_back(-1);
5075 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5076 MaskOps.push_back(Idx);
5079 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5082 static bool MayFoldVectorLoad(SDValue V) {
5083 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5084 V = V.getOperand(0);
5085 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5086 V = V.getOperand(0);
5092 // FIXME: the version above should always be used. Since there's
5093 // a bug where several vector shuffles can't be folded because the
5094 // DAG is not updated during lowering and a node claims to have two
5095 // uses while it only has one, use this version, and let isel match
5096 // another instruction if the load really happens to have more than
5097 // one use. Remove this version after this bug get fixed.
5098 // rdar://8434668, PR8156
5099 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5100 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5101 V = V.getOperand(0);
5102 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5103 V = V.getOperand(0);
5104 if (ISD::isNormalLoad(V.getNode()))
5109 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5110 /// a vector extract, and if both can be later optimized into a single load.
5111 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5112 /// here because otherwise a target specific shuffle node is going to be
5113 /// emitted for this shuffle, and the optimization not done.
5114 /// FIXME: This is probably not the best approach, but fix the problem
5115 /// until the right path is decided.
5117 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5118 const TargetLowering &TLI) {
5119 EVT VT = V.getValueType();
5120 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5122 // Be sure that the vector shuffle is present in a pattern like this:
5123 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5127 SDNode *N = *V.getNode()->use_begin();
5128 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5131 SDValue EltNo = N->getOperand(1);
5132 if (!isa<ConstantSDNode>(EltNo))
5135 // If the bit convert changed the number of elements, it is unsafe
5136 // to examine the mask.
5137 bool HasShuffleIntoBitcast = false;
5138 if (V.getOpcode() == ISD::BITCAST) {
5139 EVT SrcVT = V.getOperand(0).getValueType();
5140 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5142 V = V.getOperand(0);
5143 HasShuffleIntoBitcast = true;
5146 // Select the input vector, guarding against out of range extract vector.
5147 unsigned NumElems = VT.getVectorNumElements();
5148 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5149 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5150 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5152 // Skip one more bit_convert if necessary
5153 if (V.getOpcode() == ISD::BITCAST)
5154 V = V.getOperand(0);
5156 if (ISD::isNormalLoad(V.getNode())) {
5157 // Is the original load suitable?
5158 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5160 // FIXME: avoid the multi-use bug that is preventing lots of
5161 // of foldings to be detected, this is still wrong of course, but
5162 // give the temporary desired behavior, and if it happens that
5163 // the load has real more uses, during isel it will not fold, and
5164 // will generate poor code.
5165 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5168 if (!HasShuffleIntoBitcast)
5171 // If there's a bitcast before the shuffle, check if the load type and
5172 // alignment is valid.
5173 unsigned Align = LN0->getAlignment();
5175 TLI.getTargetData()->getABITypeAlignment(
5176 VT.getTypeForEVT(*DAG.getContext()));
5178 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5186 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5187 EVT VT = Op.getValueType();
5189 // Canonizalize to v2f64.
5190 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
5191 return DAG.getNode(ISD::BITCAST, dl, VT,
5192 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5197 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5199 SDValue V1 = Op.getOperand(0);
5200 SDValue V2 = Op.getOperand(1);
5201 EVT VT = Op.getValueType();
5203 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5205 if (HasSSE2 && VT == MVT::v2f64)
5206 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5209 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5213 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5214 SDValue V1 = Op.getOperand(0);
5215 SDValue V2 = Op.getOperand(1);
5216 EVT VT = Op.getValueType();
5218 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5219 "unsupported shuffle type");
5221 if (V2.getOpcode() == ISD::UNDEF)
5225 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5229 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5230 SDValue V1 = Op.getOperand(0);
5231 SDValue V2 = Op.getOperand(1);
5232 EVT VT = Op.getValueType();
5233 unsigned NumElems = VT.getVectorNumElements();
5235 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5236 // operand of these instructions is only memory, so check if there's a
5237 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5239 bool CanFoldLoad = false;
5241 // Trivial case, when V2 comes from a load.
5242 if (MayFoldVectorLoad(V2))
5245 // When V1 is a load, it can be folded later into a store in isel, example:
5246 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5248 // (MOVLPSmr addr:$src1, VR128:$src2)
5249 // So, recognize this potential and also use MOVLPS or MOVLPD
5250 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5254 if (HasSSE2 && NumElems == 2)
5255 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5258 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5261 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5262 // movl and movlp will both match v2i64, but v2i64 is never matched by
5263 // movl earlier because we make it strict to avoid messing with the movlp load
5264 // folding logic (see the code above getMOVLP call). Match it here then,
5265 // this is horrible, but will stay like this until we move all shuffle
5266 // matching to x86 specific nodes. Note that for the 1st condition all
5267 // types are matched with movsd.
5268 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5269 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5271 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5274 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5276 // Invert the operand order and use SHUFPS to match it.
5277 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5278 X86::getShuffleSHUFImmediate(SVOp), DAG);
5281 static inline unsigned getUNPCKLOpcode(EVT VT) {
5282 switch(VT.getSimpleVT().SimpleTy) {
5283 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5284 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5285 case MVT::v4f32: return X86ISD::UNPCKLPS;
5286 case MVT::v2f64: return X86ISD::UNPCKLPD;
5287 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5288 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5290 llvm_unreachable("Unknow type for unpckl");
5295 static inline unsigned getUNPCKHOpcode(EVT VT) {
5296 switch(VT.getSimpleVT().SimpleTy) {
5297 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5298 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5299 case MVT::v4f32: return X86ISD::UNPCKHPS;
5300 case MVT::v2f64: return X86ISD::UNPCKHPD;
5301 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5302 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5304 llvm_unreachable("Unknow type for unpckh");
5310 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5311 const TargetLowering &TLI,
5312 const X86Subtarget *Subtarget) {
5313 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5314 EVT VT = Op.getValueType();
5315 DebugLoc dl = Op.getDebugLoc();
5316 SDValue V1 = Op.getOperand(0);
5317 SDValue V2 = Op.getOperand(1);
5319 if (isZeroShuffle(SVOp))
5320 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5322 // Handle splat operations
5323 if (SVOp->isSplat()) {
5324 // Special case, this is the only place now where it's
5325 // allowed to return a vector_shuffle operation without
5326 // using a target specific node, because *hopefully* it
5327 // will be optimized away by the dag combiner.
5328 if (VT.getVectorNumElements() <= 4 &&
5329 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5332 // Handle splats by matching through known masks
5333 if (VT.getVectorNumElements() <= 4)
5336 // Canonicalize all of the remaining to v4f32.
5337 return PromoteSplat(SVOp, DAG);
5340 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5342 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5343 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5344 if (NewOp.getNode())
5345 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
5346 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5347 // FIXME: Figure out a cleaner way to do this.
5348 // Try to make use of movq to zero out the top part.
5349 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5350 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5351 if (NewOp.getNode()) {
5352 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5353 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5354 DAG, Subtarget, dl);
5356 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5357 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5358 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5359 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5360 DAG, Subtarget, dl);
5367 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5369 SDValue V1 = Op.getOperand(0);
5370 SDValue V2 = Op.getOperand(1);
5371 EVT VT = Op.getValueType();
5372 DebugLoc dl = Op.getDebugLoc();
5373 unsigned NumElems = VT.getVectorNumElements();
5374 bool isMMX = VT.getSizeInBits() == 64;
5375 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5376 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5377 bool V1IsSplat = false;
5378 bool V2IsSplat = false;
5379 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5380 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5381 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5382 MachineFunction &MF = DAG.getMachineFunction();
5383 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5385 // Shuffle operations on MMX not supported.
5389 // Vector shuffle lowering takes 3 steps:
5391 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5392 // narrowing and commutation of operands should be handled.
5393 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5395 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5396 // so the shuffle can be broken into other shuffles and the legalizer can
5397 // try the lowering again.
5399 // The general ideia is that no vector_shuffle operation should be left to
5400 // be matched during isel, all of them must be converted to a target specific
5403 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5404 // narrowing and commutation of operands should be handled. The actual code
5405 // doesn't include all of those, work in progress...
5406 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5407 if (NewOp.getNode())
5410 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5411 // unpckh_undef). Only use pshufd if speed is more important than size.
5412 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5413 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5414 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5415 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5416 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5417 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5419 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5420 RelaxedMayFoldVectorLoad(V1))
5421 return getMOVDDup(Op, dl, V1, DAG);
5423 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5424 return getMOVHighToLow(Op, dl, DAG);
5426 // Use to match splats
5427 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5428 (VT == MVT::v2f64 || VT == MVT::v2i64))
5429 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5431 if (X86::isPSHUFDMask(SVOp)) {
5432 // The actual implementation will match the mask in the if above and then
5433 // during isel it can match several different instructions, not only pshufd
5434 // as its name says, sad but true, emulate the behavior for now...
5435 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5436 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5438 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5440 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5441 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5443 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5444 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5447 if (VT == MVT::v4f32)
5448 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5452 // Check if this can be converted into a logical shift.
5453 bool isLeft = false;
5456 bool isShift = getSubtarget()->hasSSE2() &&
5457 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5458 if (isShift && ShVal.hasOneUse()) {
5459 // If the shifted value has multiple uses, it may be cheaper to use
5460 // v_set0 + movlhps or movhlps, etc.
5461 EVT EltVT = VT.getVectorElementType();
5462 ShAmt *= EltVT.getSizeInBits();
5463 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5466 if (X86::isMOVLMask(SVOp)) {
5469 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5470 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5471 if (!X86::isMOVLPMask(SVOp)) {
5472 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5473 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5475 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5476 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5480 // FIXME: fold these into legal mask.
5481 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5482 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5484 if (X86::isMOVHLPSMask(SVOp))
5485 return getMOVHighToLow(Op, dl, DAG);
5487 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5488 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5490 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5491 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5493 if (X86::isMOVLPMask(SVOp))
5494 return getMOVLP(Op, dl, DAG, HasSSE2);
5496 if (ShouldXformToMOVHLPS(SVOp) ||
5497 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5498 return CommuteVectorShuffle(SVOp, DAG);
5501 // No better options. Use a vshl / vsrl.
5502 EVT EltVT = VT.getVectorElementType();
5503 ShAmt *= EltVT.getSizeInBits();
5504 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5507 bool Commuted = false;
5508 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5509 // 1,1,1,1 -> v8i16 though.
5510 V1IsSplat = isSplatVector(V1.getNode());
5511 V2IsSplat = isSplatVector(V2.getNode());
5513 // Canonicalize the splat or undef, if present, to be on the RHS.
5514 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5515 Op = CommuteVectorShuffle(SVOp, DAG);
5516 SVOp = cast<ShuffleVectorSDNode>(Op);
5517 V1 = SVOp->getOperand(0);
5518 V2 = SVOp->getOperand(1);
5519 std::swap(V1IsSplat, V2IsSplat);
5520 std::swap(V1IsUndef, V2IsUndef);
5524 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5525 // Shuffling low element of v1 into undef, just return v1.
5528 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5529 // the instruction selector will not match, so get a canonical MOVL with
5530 // swapped operands to undo the commute.
5531 return getMOVL(DAG, dl, VT, V2, V1);
5534 if (X86::isUNPCKLMask(SVOp))
5535 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5537 if (X86::isUNPCKHMask(SVOp))
5538 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5541 // Normalize mask so all entries that point to V2 points to its first
5542 // element then try to match unpck{h|l} again. If match, return a
5543 // new vector_shuffle with the corrected mask.
5544 SDValue NewMask = NormalizeMask(SVOp, DAG);
5545 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5546 if (NSVOp != SVOp) {
5547 if (X86::isUNPCKLMask(NSVOp, true)) {
5549 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5556 // Commute is back and try unpck* again.
5557 // FIXME: this seems wrong.
5558 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5559 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5561 if (X86::isUNPCKLMask(NewSVOp))
5562 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5564 if (X86::isUNPCKHMask(NewSVOp))
5565 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5568 // Normalize the node to match x86 shuffle ops if needed
5569 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5570 return CommuteVectorShuffle(SVOp, DAG);
5572 // The checks below are all present in isShuffleMaskLegal, but they are
5573 // inlined here right now to enable us to directly emit target specific
5574 // nodes, and remove one by one until they don't return Op anymore.
5575 SmallVector<int, 16> M;
5578 if (isPALIGNRMask(M, VT, HasSSSE3))
5579 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5580 X86::getShufflePALIGNRImmediate(SVOp),
5583 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5584 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5585 if (VT == MVT::v2f64)
5586 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5587 if (VT == MVT::v2i64)
5588 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5591 if (isPSHUFHWMask(M, VT))
5592 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5593 X86::getShufflePSHUFHWImmediate(SVOp),
5596 if (isPSHUFLWMask(M, VT))
5597 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5598 X86::getShufflePSHUFLWImmediate(SVOp),
5601 if (isSHUFPMask(M, VT)) {
5602 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5603 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5604 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5606 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5607 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5611 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5612 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5613 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5614 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5615 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5616 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5618 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5619 if (VT == MVT::v8i16) {
5620 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5621 if (NewOp.getNode())
5625 if (VT == MVT::v16i8) {
5626 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5627 if (NewOp.getNode())
5631 // Handle all 4 wide cases with a number of shuffles.
5633 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5639 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5640 SelectionDAG &DAG) const {
5641 EVT VT = Op.getValueType();
5642 DebugLoc dl = Op.getDebugLoc();
5643 if (VT.getSizeInBits() == 8) {
5644 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5645 Op.getOperand(0), Op.getOperand(1));
5646 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5647 DAG.getValueType(VT));
5648 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5649 } else if (VT.getSizeInBits() == 16) {
5650 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5651 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5653 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5654 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5655 DAG.getNode(ISD::BITCAST, dl,
5659 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5660 Op.getOperand(0), Op.getOperand(1));
5661 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5662 DAG.getValueType(VT));
5663 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5664 } else if (VT == MVT::f32) {
5665 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5666 // the result back to FR32 register. It's only worth matching if the
5667 // result has a single use which is a store or a bitcast to i32. And in
5668 // the case of a store, it's not worth it if the index is a constant 0,
5669 // because a MOVSSmr can be used instead, which is smaller and faster.
5670 if (!Op.hasOneUse())
5672 SDNode *User = *Op.getNode()->use_begin();
5673 if ((User->getOpcode() != ISD::STORE ||
5674 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5675 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5676 (User->getOpcode() != ISD::BITCAST ||
5677 User->getValueType(0) != MVT::i32))
5679 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5680 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
5683 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
5684 } else if (VT == MVT::i32) {
5685 // ExtractPS works with constant index.
5686 if (isa<ConstantSDNode>(Op.getOperand(1)))
5694 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5695 SelectionDAG &DAG) const {
5696 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5699 if (Subtarget->hasSSE41()) {
5700 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5705 EVT VT = Op.getValueType();
5706 DebugLoc dl = Op.getDebugLoc();
5707 // TODO: handle v16i8.
5708 if (VT.getSizeInBits() == 16) {
5709 SDValue Vec = Op.getOperand(0);
5710 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5712 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5713 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5714 DAG.getNode(ISD::BITCAST, dl,
5717 // Transform it so it match pextrw which produces a 32-bit result.
5718 EVT EltVT = MVT::i32;
5719 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5720 Op.getOperand(0), Op.getOperand(1));
5721 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5722 DAG.getValueType(VT));
5723 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5724 } else if (VT.getSizeInBits() == 32) {
5725 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5729 // SHUFPS the element to the lowest double word, then movss.
5730 int Mask[4] = { Idx, -1, -1, -1 };
5731 EVT VVT = Op.getOperand(0).getValueType();
5732 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5733 DAG.getUNDEF(VVT), Mask);
5734 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5735 DAG.getIntPtrConstant(0));
5736 } else if (VT.getSizeInBits() == 64) {
5737 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5738 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5739 // to match extract_elt for f64.
5740 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5744 // UNPCKHPD the element to the lowest double word, then movsd.
5745 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5746 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5747 int Mask[2] = { 1, -1 };
5748 EVT VVT = Op.getOperand(0).getValueType();
5749 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5750 DAG.getUNDEF(VVT), Mask);
5751 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5752 DAG.getIntPtrConstant(0));
5759 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5760 SelectionDAG &DAG) const {
5761 EVT VT = Op.getValueType();
5762 EVT EltVT = VT.getVectorElementType();
5763 DebugLoc dl = Op.getDebugLoc();
5765 SDValue N0 = Op.getOperand(0);
5766 SDValue N1 = Op.getOperand(1);
5767 SDValue N2 = Op.getOperand(2);
5769 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5770 isa<ConstantSDNode>(N2)) {
5772 if (VT == MVT::v8i16)
5773 Opc = X86ISD::PINSRW;
5774 else if (VT == MVT::v16i8)
5775 Opc = X86ISD::PINSRB;
5777 Opc = X86ISD::PINSRB;
5779 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5781 if (N1.getValueType() != MVT::i32)
5782 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5783 if (N2.getValueType() != MVT::i32)
5784 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5785 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5786 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5787 // Bits [7:6] of the constant are the source select. This will always be
5788 // zero here. The DAG Combiner may combine an extract_elt index into these
5789 // bits. For example (insert (extract, 3), 2) could be matched by putting
5790 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5791 // Bits [5:4] of the constant are the destination select. This is the
5792 // value of the incoming immediate.
5793 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5794 // combine either bitwise AND or insert of float 0.0 to set these bits.
5795 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5796 // Create this as a scalar to vector..
5797 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5798 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5799 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5800 // PINSR* works with constant index.
5807 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5808 EVT VT = Op.getValueType();
5809 EVT EltVT = VT.getVectorElementType();
5811 if (Subtarget->hasSSE41())
5812 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5814 if (EltVT == MVT::i8)
5817 DebugLoc dl = Op.getDebugLoc();
5818 SDValue N0 = Op.getOperand(0);
5819 SDValue N1 = Op.getOperand(1);
5820 SDValue N2 = Op.getOperand(2);
5822 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5823 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5824 // as its second argument.
5825 if (N1.getValueType() != MVT::i32)
5826 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5827 if (N2.getValueType() != MVT::i32)
5828 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5829 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
5835 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5836 DebugLoc dl = Op.getDebugLoc();
5838 if (Op.getValueType() == MVT::v1i64 &&
5839 Op.getOperand(0).getValueType() == MVT::i64)
5840 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5842 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5843 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
5844 "Expected an SSE type!");
5845 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
5846 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
5849 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5850 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5851 // one of the above mentioned nodes. It has to be wrapped because otherwise
5852 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5853 // be used to form addressing mode. These wrapped nodes will be selected
5856 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5857 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5859 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5861 unsigned char OpFlag = 0;
5862 unsigned WrapperKind = X86ISD::Wrapper;
5863 CodeModel::Model M = getTargetMachine().getCodeModel();
5865 if (Subtarget->isPICStyleRIPRel() &&
5866 (M == CodeModel::Small || M == CodeModel::Kernel))
5867 WrapperKind = X86ISD::WrapperRIP;
5868 else if (Subtarget->isPICStyleGOT())
5869 OpFlag = X86II::MO_GOTOFF;
5870 else if (Subtarget->isPICStyleStubPIC())
5871 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5873 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5875 CP->getOffset(), OpFlag);
5876 DebugLoc DL = CP->getDebugLoc();
5877 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5878 // With PIC, the address is actually $g + Offset.
5880 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5881 DAG.getNode(X86ISD::GlobalBaseReg,
5882 DebugLoc(), getPointerTy()),
5889 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5890 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5892 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5894 unsigned char OpFlag = 0;
5895 unsigned WrapperKind = X86ISD::Wrapper;
5896 CodeModel::Model M = getTargetMachine().getCodeModel();
5898 if (Subtarget->isPICStyleRIPRel() &&
5899 (M == CodeModel::Small || M == CodeModel::Kernel))
5900 WrapperKind = X86ISD::WrapperRIP;
5901 else if (Subtarget->isPICStyleGOT())
5902 OpFlag = X86II::MO_GOTOFF;
5903 else if (Subtarget->isPICStyleStubPIC())
5904 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5906 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5908 DebugLoc DL = JT->getDebugLoc();
5909 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5911 // With PIC, the address is actually $g + Offset.
5913 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5914 DAG.getNode(X86ISD::GlobalBaseReg,
5915 DebugLoc(), getPointerTy()),
5922 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5923 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5925 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5927 unsigned char OpFlag = 0;
5928 unsigned WrapperKind = X86ISD::Wrapper;
5929 CodeModel::Model M = getTargetMachine().getCodeModel();
5931 if (Subtarget->isPICStyleRIPRel() &&
5932 (M == CodeModel::Small || M == CodeModel::Kernel))
5933 WrapperKind = X86ISD::WrapperRIP;
5934 else if (Subtarget->isPICStyleGOT())
5935 OpFlag = X86II::MO_GOTOFF;
5936 else if (Subtarget->isPICStyleStubPIC())
5937 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5939 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5941 DebugLoc DL = Op.getDebugLoc();
5942 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5945 // With PIC, the address is actually $g + Offset.
5946 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5947 !Subtarget->is64Bit()) {
5948 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5949 DAG.getNode(X86ISD::GlobalBaseReg,
5950 DebugLoc(), getPointerTy()),
5958 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5959 // Create the TargetBlockAddressAddress node.
5960 unsigned char OpFlags =
5961 Subtarget->ClassifyBlockAddressReference();
5962 CodeModel::Model M = getTargetMachine().getCodeModel();
5963 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5964 DebugLoc dl = Op.getDebugLoc();
5965 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5966 /*isTarget=*/true, OpFlags);
5968 if (Subtarget->isPICStyleRIPRel() &&
5969 (M == CodeModel::Small || M == CodeModel::Kernel))
5970 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5972 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5974 // With PIC, the address is actually $g + Offset.
5975 if (isGlobalRelativeToPICBase(OpFlags)) {
5976 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5977 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5985 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5987 SelectionDAG &DAG) const {
5988 // Create the TargetGlobalAddress node, folding in the constant
5989 // offset if it is legal.
5990 unsigned char OpFlags =
5991 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5992 CodeModel::Model M = getTargetMachine().getCodeModel();
5994 if (OpFlags == X86II::MO_NO_FLAG &&
5995 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5996 // A direct static reference to a global.
5997 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
6000 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6003 if (Subtarget->isPICStyleRIPRel() &&
6004 (M == CodeModel::Small || M == CodeModel::Kernel))
6005 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6007 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6009 // With PIC, the address is actually $g + Offset.
6010 if (isGlobalRelativeToPICBase(OpFlags)) {
6011 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6012 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6016 // For globals that require a load from a stub to get the address, emit the
6018 if (isGlobalStubReference(OpFlags))
6019 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6020 MachinePointerInfo::getGOT(), false, false, 0);
6022 // If there was a non-zero offset that we didn't fold, create an explicit
6025 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6026 DAG.getConstant(Offset, getPointerTy()));
6032 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6033 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6034 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6035 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6039 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6040 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6041 unsigned char OperandFlags) {
6042 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6043 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6044 DebugLoc dl = GA->getDebugLoc();
6045 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6046 GA->getValueType(0),
6050 SDValue Ops[] = { Chain, TGA, *InFlag };
6051 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6053 SDValue Ops[] = { Chain, TGA };
6054 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6057 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6058 MFI->setAdjustsStack(true);
6060 SDValue Flag = Chain.getValue(1);
6061 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6064 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6066 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6069 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6070 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6071 DAG.getNode(X86ISD::GlobalBaseReg,
6072 DebugLoc(), PtrVT), InFlag);
6073 InFlag = Chain.getValue(1);
6075 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6078 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6080 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6082 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6083 X86::RAX, X86II::MO_TLSGD);
6086 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6087 // "local exec" model.
6088 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6089 const EVT PtrVT, TLSModel::Model model,
6091 DebugLoc dl = GA->getDebugLoc();
6093 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6094 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6095 is64Bit ? 257 : 256));
6097 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6098 DAG.getIntPtrConstant(0),
6099 MachinePointerInfo(Ptr), false, false, 0);
6101 unsigned char OperandFlags = 0;
6102 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6104 unsigned WrapperKind = X86ISD::Wrapper;
6105 if (model == TLSModel::LocalExec) {
6106 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6107 } else if (is64Bit) {
6108 assert(model == TLSModel::InitialExec);
6109 OperandFlags = X86II::MO_GOTTPOFF;
6110 WrapperKind = X86ISD::WrapperRIP;
6112 assert(model == TLSModel::InitialExec);
6113 OperandFlags = X86II::MO_INDNTPOFF;
6116 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6118 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6119 GA->getValueType(0),
6120 GA->getOffset(), OperandFlags);
6121 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6123 if (model == TLSModel::InitialExec)
6124 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6125 MachinePointerInfo::getGOT(), false, false, 0);
6127 // The address of the thread local variable is the add of the thread
6128 // pointer with the offset of the variable.
6129 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6133 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6135 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6136 const GlobalValue *GV = GA->getGlobal();
6138 if (Subtarget->isTargetELF()) {
6139 // TODO: implement the "local dynamic" model
6140 // TODO: implement the "initial exec"model for pic executables
6142 // If GV is an alias then use the aliasee for determining
6143 // thread-localness.
6144 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6145 GV = GA->resolveAliasedGlobal(false);
6147 TLSModel::Model model
6148 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6151 case TLSModel::GeneralDynamic:
6152 case TLSModel::LocalDynamic: // not implemented
6153 if (Subtarget->is64Bit())
6154 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6155 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6157 case TLSModel::InitialExec:
6158 case TLSModel::LocalExec:
6159 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6160 Subtarget->is64Bit());
6162 } else if (Subtarget->isTargetDarwin()) {
6163 // Darwin only has one model of TLS. Lower to that.
6164 unsigned char OpFlag = 0;
6165 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6166 X86ISD::WrapperRIP : X86ISD::Wrapper;
6168 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6170 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6171 !Subtarget->is64Bit();
6173 OpFlag = X86II::MO_TLVP_PIC_BASE;
6175 OpFlag = X86II::MO_TLVP;
6176 DebugLoc DL = Op.getDebugLoc();
6177 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6178 GA->getValueType(0),
6179 GA->getOffset(), OpFlag);
6180 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6182 // With PIC32, the address is actually $g + Offset.
6184 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6185 DAG.getNode(X86ISD::GlobalBaseReg,
6186 DebugLoc(), getPointerTy()),
6189 // Lowering the machine isd will make sure everything is in the right
6191 SDValue Chain = DAG.getEntryNode();
6192 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6193 SDValue Args[] = { Chain, Offset };
6194 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
6196 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6197 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6198 MFI->setAdjustsStack(true);
6200 // And our return value (tls address) is in the standard call return value
6202 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6203 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6207 "TLS not implemented for this target.");
6209 llvm_unreachable("Unreachable");
6214 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6215 /// take a 2 x i32 value to shift plus a shift amount.
6216 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6217 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6218 EVT VT = Op.getValueType();
6219 unsigned VTBits = VT.getSizeInBits();
6220 DebugLoc dl = Op.getDebugLoc();
6221 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6222 SDValue ShOpLo = Op.getOperand(0);
6223 SDValue ShOpHi = Op.getOperand(1);
6224 SDValue ShAmt = Op.getOperand(2);
6225 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6226 DAG.getConstant(VTBits - 1, MVT::i8))
6227 : DAG.getConstant(0, VT);
6230 if (Op.getOpcode() == ISD::SHL_PARTS) {
6231 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6232 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6234 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6235 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6238 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6239 DAG.getConstant(VTBits, MVT::i8));
6240 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6241 AndNode, DAG.getConstant(0, MVT::i8));
6244 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6245 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6246 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6248 if (Op.getOpcode() == ISD::SHL_PARTS) {
6249 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6250 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6252 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6253 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6256 SDValue Ops[2] = { Lo, Hi };
6257 return DAG.getMergeValues(Ops, 2, dl);
6260 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6261 SelectionDAG &DAG) const {
6262 EVT SrcVT = Op.getOperand(0).getValueType();
6264 if (SrcVT.isVector())
6267 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6268 "Unknown SINT_TO_FP to lower!");
6270 // These are really Legal; return the operand so the caller accepts it as
6272 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6274 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6275 Subtarget->is64Bit()) {
6279 DebugLoc dl = Op.getDebugLoc();
6280 unsigned Size = SrcVT.getSizeInBits()/8;
6281 MachineFunction &MF = DAG.getMachineFunction();
6282 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6283 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6284 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6286 MachinePointerInfo::getFixedStack(SSFI),
6288 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6291 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6293 SelectionDAG &DAG) const {
6295 DebugLoc DL = Op.getDebugLoc();
6297 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6299 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
6301 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6303 unsigned ByteSize = SrcVT.getSizeInBits()/8;
6305 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6306 MachineMemOperand *MMO =
6307 DAG.getMachineFunction()
6308 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6309 MachineMemOperand::MOLoad, ByteSize, ByteSize);
6311 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6312 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
6314 Tys, Ops, array_lengthof(Ops),
6318 Chain = Result.getValue(1);
6319 SDValue InFlag = Result.getValue(2);
6321 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6322 // shouldn't be necessary except that RFP cannot be live across
6323 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6324 MachineFunction &MF = DAG.getMachineFunction();
6325 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
6326 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
6327 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6328 Tys = DAG.getVTList(MVT::Other);
6330 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6332 MachineMemOperand *MMO =
6333 DAG.getMachineFunction()
6334 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6335 MachineMemOperand::MOStore, SSFISize, SSFISize);
6337 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
6338 Ops, array_lengthof(Ops),
6339 Op.getValueType(), MMO);
6340 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
6341 MachinePointerInfo::getFixedStack(SSFI),
6348 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6349 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6350 SelectionDAG &DAG) const {
6351 // This algorithm is not obvious. Here it is in C code, more or less:
6353 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6354 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6355 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6357 // Copy ints to xmm registers.
6358 __m128i xh = _mm_cvtsi32_si128( hi );
6359 __m128i xl = _mm_cvtsi32_si128( lo );
6361 // Combine into low half of a single xmm register.
6362 __m128i x = _mm_unpacklo_epi32( xh, xl );
6366 // Merge in appropriate exponents to give the integer bits the right
6368 x = _mm_unpacklo_epi32( x, exp );
6370 // Subtract away the biases to deal with the IEEE-754 double precision
6372 d = _mm_sub_pd( (__m128d) x, bias );
6374 // All conversions up to here are exact. The correctly rounded result is
6375 // calculated using the current rounding mode using the following
6377 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6378 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6379 // store doesn't really need to be here (except
6380 // maybe to zero the other double)
6385 DebugLoc dl = Op.getDebugLoc();
6386 LLVMContext *Context = DAG.getContext();
6388 // Build some magic constants.
6389 std::vector<Constant*> CV0;
6390 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6391 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6392 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6393 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6394 Constant *C0 = ConstantVector::get(CV0);
6395 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6397 std::vector<Constant*> CV1;
6399 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6401 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6402 Constant *C1 = ConstantVector::get(CV1);
6403 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6405 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6406 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6408 DAG.getIntPtrConstant(1)));
6409 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6410 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6412 DAG.getIntPtrConstant(0)));
6413 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6414 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6415 MachinePointerInfo::getConstantPool(),
6417 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6418 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
6419 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6420 MachinePointerInfo::getConstantPool(),
6422 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6424 // Add the halves; easiest way is to swap them into another reg first.
6425 int ShufMask[2] = { 1, -1 };
6426 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6427 DAG.getUNDEF(MVT::v2f64), ShufMask);
6428 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6429 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6430 DAG.getIntPtrConstant(0));
6433 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6434 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6435 SelectionDAG &DAG) const {
6436 DebugLoc dl = Op.getDebugLoc();
6437 // FP constant to bias correct the final result.
6438 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6441 // Load the 32-bit value into an XMM register.
6442 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6443 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6445 DAG.getIntPtrConstant(0)));
6447 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6448 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
6449 DAG.getIntPtrConstant(0));
6451 // Or the load with the bias.
6452 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6453 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6454 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6456 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6457 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6458 MVT::v2f64, Bias)));
6459 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6460 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
6461 DAG.getIntPtrConstant(0));
6463 // Subtract the bias.
6464 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6466 // Handle final rounding.
6467 EVT DestVT = Op.getValueType();
6469 if (DestVT.bitsLT(MVT::f64)) {
6470 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6471 DAG.getIntPtrConstant(0));
6472 } else if (DestVT.bitsGT(MVT::f64)) {
6473 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6476 // Handle final rounding.
6480 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6481 SelectionDAG &DAG) const {
6482 SDValue N0 = Op.getOperand(0);
6483 DebugLoc dl = Op.getDebugLoc();
6485 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6486 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6487 // the optimization here.
6488 if (DAG.SignBitIsZero(N0))
6489 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6491 EVT SrcVT = N0.getValueType();
6492 EVT DstVT = Op.getValueType();
6493 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6494 return LowerUINT_TO_FP_i64(Op, DAG);
6495 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6496 return LowerUINT_TO_FP_i32(Op, DAG);
6498 // Make a 64-bit buffer, and use it to build an FILD.
6499 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6500 if (SrcVT == MVT::i32) {
6501 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6502 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6503 getPointerTy(), StackSlot, WordOff);
6504 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6505 StackSlot, MachinePointerInfo(),
6507 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6508 OffsetSlot, MachinePointerInfo(),
6510 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6514 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6515 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6516 StackSlot, MachinePointerInfo(),
6518 // For i64 source, we need to add the appropriate power of 2 if the input
6519 // was negative. This is the same as the optimization in
6520 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6521 // we must be careful to do the computation in x87 extended precision, not
6522 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6523 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6524 MachineMemOperand *MMO =
6525 DAG.getMachineFunction()
6526 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6527 MachineMemOperand::MOLoad, 8, 8);
6529 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6530 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6531 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
6534 APInt FF(32, 0x5F800000ULL);
6536 // Check whether the sign bit is set.
6537 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6538 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6541 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6542 SDValue FudgePtr = DAG.getConstantPool(
6543 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6546 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6547 SDValue Zero = DAG.getIntPtrConstant(0);
6548 SDValue Four = DAG.getIntPtrConstant(4);
6549 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6551 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6553 // Load the value out, extending it from f32 to f80.
6554 // FIXME: Avoid the extend by constructing the right constant pool?
6555 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6556 FudgePtr, MachinePointerInfo::getConstantPool(),
6557 MVT::f32, false, false, 4);
6558 // Extend everything to 80 bits to force it to be done on x87.
6559 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6560 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6563 std::pair<SDValue,SDValue> X86TargetLowering::
6564 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6565 DebugLoc DL = Op.getDebugLoc();
6567 EVT DstTy = Op.getValueType();
6570 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6574 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6575 DstTy.getSimpleVT() >= MVT::i16 &&
6576 "Unknown FP_TO_SINT to lower!");
6578 // These are really Legal.
6579 if (DstTy == MVT::i32 &&
6580 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6581 return std::make_pair(SDValue(), SDValue());
6582 if (Subtarget->is64Bit() &&
6583 DstTy == MVT::i64 &&
6584 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6585 return std::make_pair(SDValue(), SDValue());
6587 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6589 MachineFunction &MF = DAG.getMachineFunction();
6590 unsigned MemSize = DstTy.getSizeInBits()/8;
6591 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6592 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6597 switch (DstTy.getSimpleVT().SimpleTy) {
6598 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6599 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6600 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6601 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6604 SDValue Chain = DAG.getEntryNode();
6605 SDValue Value = Op.getOperand(0);
6606 EVT TheVT = Op.getOperand(0).getValueType();
6607 if (isScalarFPTypeInSSEReg(TheVT)) {
6608 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6609 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
6610 MachinePointerInfo::getFixedStack(SSFI),
6612 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6614 Chain, StackSlot, DAG.getValueType(TheVT)
6617 MachineMemOperand *MMO =
6618 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6619 MachineMemOperand::MOLoad, MemSize, MemSize);
6620 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
6622 Chain = Value.getValue(1);
6623 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6624 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6627 MachineMemOperand *MMO =
6628 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6629 MachineMemOperand::MOStore, MemSize, MemSize);
6631 // Build the FP_TO_INT*_IN_MEM
6632 SDValue Ops[] = { Chain, Value, StackSlot };
6633 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
6634 Ops, 3, DstTy, MMO);
6636 return std::make_pair(FIST, StackSlot);
6639 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6640 SelectionDAG &DAG) const {
6641 if (Op.getValueType().isVector())
6644 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6645 SDValue FIST = Vals.first, StackSlot = Vals.second;
6646 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6647 if (FIST.getNode() == 0) return Op;
6650 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6651 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6654 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6655 SelectionDAG &DAG) const {
6656 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6657 SDValue FIST = Vals.first, StackSlot = Vals.second;
6658 assert(FIST.getNode() && "Unexpected failure");
6661 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6662 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6665 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6666 SelectionDAG &DAG) const {
6667 LLVMContext *Context = DAG.getContext();
6668 DebugLoc dl = Op.getDebugLoc();
6669 EVT VT = Op.getValueType();
6672 EltVT = VT.getVectorElementType();
6673 std::vector<Constant*> CV;
6674 if (EltVT == MVT::f64) {
6675 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6679 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6685 Constant *C = ConstantVector::get(CV);
6686 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6687 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6688 MachinePointerInfo::getConstantPool(),
6690 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6693 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6694 LLVMContext *Context = DAG.getContext();
6695 DebugLoc dl = Op.getDebugLoc();
6696 EVT VT = Op.getValueType();
6699 EltVT = VT.getVectorElementType();
6700 std::vector<Constant*> CV;
6701 if (EltVT == MVT::f64) {
6702 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6706 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6712 Constant *C = ConstantVector::get(CV);
6713 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6714 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6715 MachinePointerInfo::getConstantPool(),
6717 if (VT.isVector()) {
6718 return DAG.getNode(ISD::BITCAST, dl, VT,
6719 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6720 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6722 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
6724 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6728 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6729 LLVMContext *Context = DAG.getContext();
6730 SDValue Op0 = Op.getOperand(0);
6731 SDValue Op1 = Op.getOperand(1);
6732 DebugLoc dl = Op.getDebugLoc();
6733 EVT VT = Op.getValueType();
6734 EVT SrcVT = Op1.getValueType();
6736 // If second operand is smaller, extend it first.
6737 if (SrcVT.bitsLT(VT)) {
6738 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6741 // And if it is bigger, shrink it first.
6742 if (SrcVT.bitsGT(VT)) {
6743 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6747 // At this point the operands and the result should have the same
6748 // type, and that won't be f80 since that is not custom lowered.
6750 // First get the sign bit of second operand.
6751 std::vector<Constant*> CV;
6752 if (SrcVT == MVT::f64) {
6753 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6754 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6756 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6757 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6758 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6759 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6761 Constant *C = ConstantVector::get(CV);
6762 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6763 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6764 MachinePointerInfo::getConstantPool(),
6766 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6768 // Shift sign bit right or left if the two operands have different types.
6769 if (SrcVT.bitsGT(VT)) {
6770 // Op0 is MVT::f32, Op1 is MVT::f64.
6771 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6772 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6773 DAG.getConstant(32, MVT::i32));
6774 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
6775 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6776 DAG.getIntPtrConstant(0));
6779 // Clear first operand sign bit.
6781 if (VT == MVT::f64) {
6782 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6783 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6785 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6786 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6787 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6788 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6790 C = ConstantVector::get(CV);
6791 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6792 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6793 MachinePointerInfo::getConstantPool(),
6795 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6797 // Or the value with the sign bit.
6798 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6801 /// Emit nodes that will be selected as "test Op0,Op0", or something
6803 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6804 SelectionDAG &DAG) const {
6805 DebugLoc dl = Op.getDebugLoc();
6807 // CF and OF aren't always set the way we want. Determine which
6808 // of these we need.
6809 bool NeedCF = false;
6810 bool NeedOF = false;
6813 case X86::COND_A: case X86::COND_AE:
6814 case X86::COND_B: case X86::COND_BE:
6817 case X86::COND_G: case X86::COND_GE:
6818 case X86::COND_L: case X86::COND_LE:
6819 case X86::COND_O: case X86::COND_NO:
6824 // See if we can use the EFLAGS value from the operand instead of
6825 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6826 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6827 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6828 // Emit a CMP with 0, which is the TEST pattern.
6829 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6830 DAG.getConstant(0, Op.getValueType()));
6832 unsigned Opcode = 0;
6833 unsigned NumOperands = 0;
6834 switch (Op.getNode()->getOpcode()) {
6836 // Due to an isel shortcoming, be conservative if this add is likely to be
6837 // selected as part of a load-modify-store instruction. When the root node
6838 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6839 // uses of other nodes in the match, such as the ADD in this case. This
6840 // leads to the ADD being left around and reselected, with the result being
6841 // two adds in the output. Alas, even if none our users are stores, that
6842 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6843 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6844 // climbing the DAG back to the root, and it doesn't seem to be worth the
6846 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6847 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6848 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6851 if (ConstantSDNode *C =
6852 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6853 // An add of one will be selected as an INC.
6854 if (C->getAPIntValue() == 1) {
6855 Opcode = X86ISD::INC;
6860 // An add of negative one (subtract of one) will be selected as a DEC.
6861 if (C->getAPIntValue().isAllOnesValue()) {
6862 Opcode = X86ISD::DEC;
6868 // Otherwise use a regular EFLAGS-setting add.
6869 Opcode = X86ISD::ADD;
6873 // If the primary and result isn't used, don't bother using X86ISD::AND,
6874 // because a TEST instruction will be better.
6875 bool NonFlagUse = false;
6876 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6877 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6879 unsigned UOpNo = UI.getOperandNo();
6880 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6881 // Look pass truncate.
6882 UOpNo = User->use_begin().getOperandNo();
6883 User = *User->use_begin();
6886 if (User->getOpcode() != ISD::BRCOND &&
6887 User->getOpcode() != ISD::SETCC &&
6888 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6901 // Due to the ISEL shortcoming noted above, be conservative if this op is
6902 // likely to be selected as part of a load-modify-store instruction.
6903 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6904 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6905 if (UI->getOpcode() == ISD::STORE)
6908 // Otherwise use a regular EFLAGS-setting instruction.
6909 switch (Op.getNode()->getOpcode()) {
6910 default: llvm_unreachable("unexpected operator!");
6911 case ISD::SUB: Opcode = X86ISD::SUB; break;
6912 case ISD::OR: Opcode = X86ISD::OR; break;
6913 case ISD::XOR: Opcode = X86ISD::XOR; break;
6914 case ISD::AND: Opcode = X86ISD::AND; break;
6926 return SDValue(Op.getNode(), 1);
6933 // Emit a CMP with 0, which is the TEST pattern.
6934 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6935 DAG.getConstant(0, Op.getValueType()));
6937 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6938 SmallVector<SDValue, 4> Ops;
6939 for (unsigned i = 0; i != NumOperands; ++i)
6940 Ops.push_back(Op.getOperand(i));
6942 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6943 DAG.ReplaceAllUsesWith(Op, New);
6944 return SDValue(New.getNode(), 1);
6947 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6949 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6950 SelectionDAG &DAG) const {
6951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6952 if (C->getAPIntValue() == 0)
6953 return EmitTest(Op0, X86CC, DAG);
6955 DebugLoc dl = Op0.getDebugLoc();
6956 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6959 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6960 /// if it's possible.
6961 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6962 DebugLoc dl, SelectionDAG &DAG) const {
6963 SDValue Op0 = And.getOperand(0);
6964 SDValue Op1 = And.getOperand(1);
6965 if (Op0.getOpcode() == ISD::TRUNCATE)
6966 Op0 = Op0.getOperand(0);
6967 if (Op1.getOpcode() == ISD::TRUNCATE)
6968 Op1 = Op1.getOperand(0);
6971 if (Op1.getOpcode() == ISD::SHL)
6972 std::swap(Op0, Op1);
6973 if (Op0.getOpcode() == ISD::SHL) {
6974 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6975 if (And00C->getZExtValue() == 1) {
6976 // If we looked past a truncate, check that it's only truncating away
6978 unsigned BitWidth = Op0.getValueSizeInBits();
6979 unsigned AndBitWidth = And.getValueSizeInBits();
6980 if (BitWidth > AndBitWidth) {
6981 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6982 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6983 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6987 RHS = Op0.getOperand(1);
6989 } else if (Op1.getOpcode() == ISD::Constant) {
6990 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6991 SDValue AndLHS = Op0;
6992 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6993 LHS = AndLHS.getOperand(0);
6994 RHS = AndLHS.getOperand(1);
6998 if (LHS.getNode()) {
6999 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
7000 // instruction. Since the shift amount is in-range-or-undefined, we know
7001 // that doing a bittest on the i32 value is ok. We extend to i32 because
7002 // the encoding for the i16 version is larger than the i32 version.
7003 // Also promote i16 to i32 for performance / code size reason.
7004 if (LHS.getValueType() == MVT::i8 ||
7005 LHS.getValueType() == MVT::i16)
7006 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7008 // If the operand types disagree, extend the shift amount to match. Since
7009 // BT ignores high bits (like shifts) we can use anyextend.
7010 if (LHS.getValueType() != RHS.getValueType())
7011 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7013 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7014 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7015 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7016 DAG.getConstant(Cond, MVT::i8), BT);
7022 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7023 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7024 SDValue Op0 = Op.getOperand(0);
7025 SDValue Op1 = Op.getOperand(1);
7026 DebugLoc dl = Op.getDebugLoc();
7027 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7029 // Optimize to BT if possible.
7030 // Lower (X & (1 << N)) == 0 to BT(X, N).
7031 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7032 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7033 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
7034 Op1.getOpcode() == ISD::Constant &&
7035 cast<ConstantSDNode>(Op1)->isNullValue() &&
7036 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7037 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7038 if (NewSetCC.getNode())
7042 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
7044 if (Op1.getOpcode() == ISD::Constant &&
7045 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7046 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7047 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7049 // If the input is a setcc, then reuse the input setcc or use a new one with
7050 // the inverted condition.
7051 if (Op0.getOpcode() == X86ISD::SETCC) {
7052 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7053 bool Invert = (CC == ISD::SETNE) ^
7054 cast<ConstantSDNode>(Op1)->isNullValue();
7055 if (!Invert) return Op0;
7057 CCode = X86::GetOppositeBranchCondition(CCode);
7058 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7059 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7063 bool isFP = Op1.getValueType().isFloatingPoint();
7064 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7065 if (X86CC == X86::COND_INVALID)
7068 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
7069 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7070 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
7073 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7075 SDValue Op0 = Op.getOperand(0);
7076 SDValue Op1 = Op.getOperand(1);
7077 SDValue CC = Op.getOperand(2);
7078 EVT VT = Op.getValueType();
7079 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7080 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7081 DebugLoc dl = Op.getDebugLoc();
7085 EVT VT0 = Op0.getValueType();
7086 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7087 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7090 switch (SetCCOpcode) {
7093 case ISD::SETEQ: SSECC = 0; break;
7095 case ISD::SETGT: Swap = true; // Fallthrough
7097 case ISD::SETOLT: SSECC = 1; break;
7099 case ISD::SETGE: Swap = true; // Fallthrough
7101 case ISD::SETOLE: SSECC = 2; break;
7102 case ISD::SETUO: SSECC = 3; break;
7104 case ISD::SETNE: SSECC = 4; break;
7105 case ISD::SETULE: Swap = true;
7106 case ISD::SETUGE: SSECC = 5; break;
7107 case ISD::SETULT: Swap = true;
7108 case ISD::SETUGT: SSECC = 6; break;
7109 case ISD::SETO: SSECC = 7; break;
7112 std::swap(Op0, Op1);
7114 // In the two special cases we can't handle, emit two comparisons.
7116 if (SetCCOpcode == ISD::SETUEQ) {
7118 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7119 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7120 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7122 else if (SetCCOpcode == ISD::SETONE) {
7124 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7125 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7126 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7128 llvm_unreachable("Illegal FP comparison");
7130 // Handle all other FP comparisons here.
7131 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7134 // We are handling one of the integer comparisons here. Since SSE only has
7135 // GT and EQ comparisons for integer, swapping operands and multiple
7136 // operations may be required for some comparisons.
7137 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7138 bool Swap = false, Invert = false, FlipSigns = false;
7140 switch (VT.getSimpleVT().SimpleTy) {
7142 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7143 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7144 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7145 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7148 switch (SetCCOpcode) {
7150 case ISD::SETNE: Invert = true;
7151 case ISD::SETEQ: Opc = EQOpc; break;
7152 case ISD::SETLT: Swap = true;
7153 case ISD::SETGT: Opc = GTOpc; break;
7154 case ISD::SETGE: Swap = true;
7155 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7156 case ISD::SETULT: Swap = true;
7157 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7158 case ISD::SETUGE: Swap = true;
7159 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7162 std::swap(Op0, Op1);
7164 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7165 // bits of the inputs before performing those operations.
7167 EVT EltVT = VT.getVectorElementType();
7168 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7170 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7171 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7173 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7174 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7177 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7179 // If the logical-not of the result is required, perform that now.
7181 Result = DAG.getNOT(dl, Result, VT);
7186 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7187 static bool isX86LogicalCmp(SDValue Op) {
7188 unsigned Opc = Op.getNode()->getOpcode();
7189 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7191 if (Op.getResNo() == 1 &&
7192 (Opc == X86ISD::ADD ||
7193 Opc == X86ISD::SUB ||
7194 Opc == X86ISD::ADC ||
7195 Opc == X86ISD::SBB ||
7196 Opc == X86ISD::SMUL ||
7197 Opc == X86ISD::UMUL ||
7198 Opc == X86ISD::INC ||
7199 Opc == X86ISD::DEC ||
7200 Opc == X86ISD::OR ||
7201 Opc == X86ISD::XOR ||
7202 Opc == X86ISD::AND))
7205 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
7211 static bool isZero(SDValue V) {
7212 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7213 return C && C->isNullValue();
7216 static bool isAllOnes(SDValue V) {
7217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7218 return C && C->isAllOnesValue();
7221 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7222 bool addTest = true;
7223 SDValue Cond = Op.getOperand(0);
7224 SDValue Op1 = Op.getOperand(1);
7225 SDValue Op2 = Op.getOperand(2);
7226 DebugLoc DL = Op.getDebugLoc();
7229 if (Cond.getOpcode() == ISD::SETCC) {
7230 SDValue NewCond = LowerSETCC(Cond, DAG);
7231 if (NewCond.getNode())
7235 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
7236 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
7237 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
7238 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
7239 if (Cond.getOpcode() == X86ISD::SETCC &&
7240 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
7241 isZero(Cond.getOperand(1).getOperand(1))) {
7242 SDValue Cmp = Cond.getOperand(1);
7244 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
7246 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
7247 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
7248 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
7250 SDValue CmpOp0 = Cmp.getOperand(0);
7251 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
7252 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7254 SDValue Res = // Res = 0 or -1.
7255 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7256 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7258 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
7259 Res = DAG.getNOT(DL, Res, Res.getValueType());
7261 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7262 if (N2C == 0 || !N2C->isNullValue())
7263 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
7268 // Look past (and (setcc_carry (cmp ...)), 1).
7269 if (Cond.getOpcode() == ISD::AND &&
7270 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7271 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7272 if (C && C->getAPIntValue() == 1)
7273 Cond = Cond.getOperand(0);
7276 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7277 // setting operand in place of the X86ISD::SETCC.
7278 if (Cond.getOpcode() == X86ISD::SETCC ||
7279 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7280 CC = Cond.getOperand(0);
7282 SDValue Cmp = Cond.getOperand(1);
7283 unsigned Opc = Cmp.getOpcode();
7284 EVT VT = Op.getValueType();
7286 bool IllegalFPCMov = false;
7287 if (VT.isFloatingPoint() && !VT.isVector() &&
7288 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7289 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7291 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7292 Opc == X86ISD::BT) { // FIXME
7299 // Look pass the truncate.
7300 if (Cond.getOpcode() == ISD::TRUNCATE)
7301 Cond = Cond.getOperand(0);
7303 // We know the result of AND is compared against zero. Try to match
7305 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7306 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
7307 if (NewSetCC.getNode()) {
7308 CC = NewSetCC.getOperand(0);
7309 Cond = NewSetCC.getOperand(1);
7316 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7317 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7320 // a < b ? -1 : 0 -> RES = ~setcc_carry
7321 // a < b ? 0 : -1 -> RES = setcc_carry
7322 // a >= b ? -1 : 0 -> RES = setcc_carry
7323 // a >= b ? 0 : -1 -> RES = ~setcc_carry
7324 if (Cond.getOpcode() == X86ISD::CMP) {
7325 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
7327 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
7328 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
7329 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7330 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
7331 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
7332 return DAG.getNOT(DL, Res, Res.getValueType());
7337 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7338 // condition is true.
7339 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
7340 SDValue Ops[] = { Op2, Op1, CC, Cond };
7341 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
7344 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7345 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7346 // from the AND / OR.
7347 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7348 Opc = Op.getOpcode();
7349 if (Opc != ISD::OR && Opc != ISD::AND)
7351 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7352 Op.getOperand(0).hasOneUse() &&
7353 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7354 Op.getOperand(1).hasOneUse());
7357 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7358 // 1 and that the SETCC node has a single use.
7359 static bool isXor1OfSetCC(SDValue Op) {
7360 if (Op.getOpcode() != ISD::XOR)
7362 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7363 if (N1C && N1C->getAPIntValue() == 1) {
7364 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7365 Op.getOperand(0).hasOneUse();
7370 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7371 bool addTest = true;
7372 SDValue Chain = Op.getOperand(0);
7373 SDValue Cond = Op.getOperand(1);
7374 SDValue Dest = Op.getOperand(2);
7375 DebugLoc dl = Op.getDebugLoc();
7378 if (Cond.getOpcode() == ISD::SETCC) {
7379 SDValue NewCond = LowerSETCC(Cond, DAG);
7380 if (NewCond.getNode())
7384 // FIXME: LowerXALUO doesn't handle these!!
7385 else if (Cond.getOpcode() == X86ISD::ADD ||
7386 Cond.getOpcode() == X86ISD::SUB ||
7387 Cond.getOpcode() == X86ISD::SMUL ||
7388 Cond.getOpcode() == X86ISD::UMUL)
7389 Cond = LowerXALUO(Cond, DAG);
7392 // Look pass (and (setcc_carry (cmp ...)), 1).
7393 if (Cond.getOpcode() == ISD::AND &&
7394 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7395 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7396 if (C && C->getAPIntValue() == 1)
7397 Cond = Cond.getOperand(0);
7400 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7401 // setting operand in place of the X86ISD::SETCC.
7402 if (Cond.getOpcode() == X86ISD::SETCC ||
7403 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7404 CC = Cond.getOperand(0);
7406 SDValue Cmp = Cond.getOperand(1);
7407 unsigned Opc = Cmp.getOpcode();
7408 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7409 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7413 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7417 // These can only come from an arithmetic instruction with overflow,
7418 // e.g. SADDO, UADDO.
7419 Cond = Cond.getNode()->getOperand(1);
7426 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7427 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7428 if (CondOpc == ISD::OR) {
7429 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7430 // two branches instead of an explicit OR instruction with a
7432 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7433 isX86LogicalCmp(Cmp)) {
7434 CC = Cond.getOperand(0).getOperand(0);
7435 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7436 Chain, Dest, CC, Cmp);
7437 CC = Cond.getOperand(1).getOperand(0);
7441 } else { // ISD::AND
7442 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7443 // two branches instead of an explicit AND instruction with a
7444 // separate test. However, we only do this if this block doesn't
7445 // have a fall-through edge, because this requires an explicit
7446 // jmp when the condition is false.
7447 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7448 isX86LogicalCmp(Cmp) &&
7449 Op.getNode()->hasOneUse()) {
7450 X86::CondCode CCode =
7451 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7452 CCode = X86::GetOppositeBranchCondition(CCode);
7453 CC = DAG.getConstant(CCode, MVT::i8);
7454 SDNode *User = *Op.getNode()->use_begin();
7455 // Look for an unconditional branch following this conditional branch.
7456 // We need this because we need to reverse the successors in order
7457 // to implement FCMP_OEQ.
7458 if (User->getOpcode() == ISD::BR) {
7459 SDValue FalseBB = User->getOperand(1);
7461 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7462 assert(NewBR == User);
7466 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7467 Chain, Dest, CC, Cmp);
7468 X86::CondCode CCode =
7469 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7470 CCode = X86::GetOppositeBranchCondition(CCode);
7471 CC = DAG.getConstant(CCode, MVT::i8);
7477 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7478 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7479 // It should be transformed during dag combiner except when the condition
7480 // is set by a arithmetics with overflow node.
7481 X86::CondCode CCode =
7482 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7483 CCode = X86::GetOppositeBranchCondition(CCode);
7484 CC = DAG.getConstant(CCode, MVT::i8);
7485 Cond = Cond.getOperand(0).getOperand(1);
7491 // Look pass the truncate.
7492 if (Cond.getOpcode() == ISD::TRUNCATE)
7493 Cond = Cond.getOperand(0);
7495 // We know the result of AND is compared against zero. Try to match
7497 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7498 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7499 if (NewSetCC.getNode()) {
7500 CC = NewSetCC.getOperand(0);
7501 Cond = NewSetCC.getOperand(1);
7508 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7509 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7511 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7512 Chain, Dest, CC, Cond);
7516 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7517 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7518 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7519 // that the guard pages used by the OS virtual memory manager are allocated in
7520 // correct sequence.
7522 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7523 SelectionDAG &DAG) const {
7524 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
7525 "This should be used only on Windows targets");
7526 DebugLoc dl = Op.getDebugLoc();
7529 SDValue Chain = Op.getOperand(0);
7530 SDValue Size = Op.getOperand(1);
7531 // FIXME: Ensure alignment here
7535 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7537 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7538 Flag = Chain.getValue(1);
7540 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7542 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
7543 Flag = Chain.getValue(1);
7545 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7547 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7548 return DAG.getMergeValues(Ops1, 2, dl);
7551 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7552 MachineFunction &MF = DAG.getMachineFunction();
7553 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7555 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7556 DebugLoc DL = Op.getDebugLoc();
7558 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
7559 // vastart just stores the address of the VarArgsFrameIndex slot into the
7560 // memory location argument.
7561 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7563 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7564 MachinePointerInfo(SV), false, false, 0);
7568 // gp_offset (0 - 6 * 8)
7569 // fp_offset (48 - 48 + 8 * 16)
7570 // overflow_arg_area (point to parameters coming in memory).
7572 SmallVector<SDValue, 8> MemOps;
7573 SDValue FIN = Op.getOperand(1);
7575 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7576 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7578 FIN, MachinePointerInfo(SV), false, false, 0);
7579 MemOps.push_back(Store);
7582 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7583 FIN, DAG.getIntPtrConstant(4));
7584 Store = DAG.getStore(Op.getOperand(0), DL,
7585 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7587 FIN, MachinePointerInfo(SV, 4), false, false, 0);
7588 MemOps.push_back(Store);
7590 // Store ptr to overflow_arg_area
7591 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7592 FIN, DAG.getIntPtrConstant(4));
7593 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7595 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
7596 MachinePointerInfo(SV, 8),
7598 MemOps.push_back(Store);
7600 // Store ptr to reg_save_area.
7601 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7602 FIN, DAG.getIntPtrConstant(8));
7603 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7605 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
7606 MachinePointerInfo(SV, 16), false, false, 0);
7607 MemOps.push_back(Store);
7608 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
7609 &MemOps[0], MemOps.size());
7612 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7613 assert(Subtarget->is64Bit() &&
7614 "LowerVAARG only handles 64-bit va_arg!");
7615 assert((Subtarget->isTargetLinux() ||
7616 Subtarget->isTargetDarwin()) &&
7617 "Unhandled target in LowerVAARG");
7618 assert(Op.getNode()->getNumOperands() == 4);
7619 SDValue Chain = Op.getOperand(0);
7620 SDValue SrcPtr = Op.getOperand(1);
7621 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7622 unsigned Align = Op.getConstantOperandVal(3);
7623 DebugLoc dl = Op.getDebugLoc();
7625 EVT ArgVT = Op.getNode()->getValueType(0);
7626 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
7627 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
7630 // Decide which area this value should be read from.
7631 // TODO: Implement the AMD64 ABI in its entirety. This simple
7632 // selection mechanism works only for the basic types.
7633 if (ArgVT == MVT::f80) {
7634 llvm_unreachable("va_arg for f80 not yet implemented");
7635 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
7636 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
7637 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
7638 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
7640 llvm_unreachable("Unhandled argument type in LowerVAARG");
7644 // Sanity Check: Make sure using fp_offset makes sense.
7645 assert(!UseSoftFloat &&
7646 !(DAG.getMachineFunction()
7647 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
7648 Subtarget->hasXMM());
7651 // Insert VAARG_64 node into the DAG
7652 // VAARG_64 returns two values: Variable Argument Address, Chain
7653 SmallVector<SDValue, 11> InstOps;
7654 InstOps.push_back(Chain);
7655 InstOps.push_back(SrcPtr);
7656 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
7657 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
7658 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
7659 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
7660 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
7661 VTs, &InstOps[0], InstOps.size(),
7663 MachinePointerInfo(SV),
7668 Chain = VAARG.getValue(1);
7670 // Load the next argument and return it
7671 return DAG.getLoad(ArgVT, dl,
7674 MachinePointerInfo(),
7678 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7679 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7680 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7681 SDValue Chain = Op.getOperand(0);
7682 SDValue DstPtr = Op.getOperand(1);
7683 SDValue SrcPtr = Op.getOperand(2);
7684 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7685 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7686 DebugLoc DL = Op.getDebugLoc();
7688 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
7689 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7691 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
7695 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7696 DebugLoc dl = Op.getDebugLoc();
7697 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7699 default: return SDValue(); // Don't custom lower most intrinsics.
7700 // Comparison intrinsics.
7701 case Intrinsic::x86_sse_comieq_ss:
7702 case Intrinsic::x86_sse_comilt_ss:
7703 case Intrinsic::x86_sse_comile_ss:
7704 case Intrinsic::x86_sse_comigt_ss:
7705 case Intrinsic::x86_sse_comige_ss:
7706 case Intrinsic::x86_sse_comineq_ss:
7707 case Intrinsic::x86_sse_ucomieq_ss:
7708 case Intrinsic::x86_sse_ucomilt_ss:
7709 case Intrinsic::x86_sse_ucomile_ss:
7710 case Intrinsic::x86_sse_ucomigt_ss:
7711 case Intrinsic::x86_sse_ucomige_ss:
7712 case Intrinsic::x86_sse_ucomineq_ss:
7713 case Intrinsic::x86_sse2_comieq_sd:
7714 case Intrinsic::x86_sse2_comilt_sd:
7715 case Intrinsic::x86_sse2_comile_sd:
7716 case Intrinsic::x86_sse2_comigt_sd:
7717 case Intrinsic::x86_sse2_comige_sd:
7718 case Intrinsic::x86_sse2_comineq_sd:
7719 case Intrinsic::x86_sse2_ucomieq_sd:
7720 case Intrinsic::x86_sse2_ucomilt_sd:
7721 case Intrinsic::x86_sse2_ucomile_sd:
7722 case Intrinsic::x86_sse2_ucomigt_sd:
7723 case Intrinsic::x86_sse2_ucomige_sd:
7724 case Intrinsic::x86_sse2_ucomineq_sd: {
7726 ISD::CondCode CC = ISD::SETCC_INVALID;
7729 case Intrinsic::x86_sse_comieq_ss:
7730 case Intrinsic::x86_sse2_comieq_sd:
7734 case Intrinsic::x86_sse_comilt_ss:
7735 case Intrinsic::x86_sse2_comilt_sd:
7739 case Intrinsic::x86_sse_comile_ss:
7740 case Intrinsic::x86_sse2_comile_sd:
7744 case Intrinsic::x86_sse_comigt_ss:
7745 case Intrinsic::x86_sse2_comigt_sd:
7749 case Intrinsic::x86_sse_comige_ss:
7750 case Intrinsic::x86_sse2_comige_sd:
7754 case Intrinsic::x86_sse_comineq_ss:
7755 case Intrinsic::x86_sse2_comineq_sd:
7759 case Intrinsic::x86_sse_ucomieq_ss:
7760 case Intrinsic::x86_sse2_ucomieq_sd:
7761 Opc = X86ISD::UCOMI;
7764 case Intrinsic::x86_sse_ucomilt_ss:
7765 case Intrinsic::x86_sse2_ucomilt_sd:
7766 Opc = X86ISD::UCOMI;
7769 case Intrinsic::x86_sse_ucomile_ss:
7770 case Intrinsic::x86_sse2_ucomile_sd:
7771 Opc = X86ISD::UCOMI;
7774 case Intrinsic::x86_sse_ucomigt_ss:
7775 case Intrinsic::x86_sse2_ucomigt_sd:
7776 Opc = X86ISD::UCOMI;
7779 case Intrinsic::x86_sse_ucomige_ss:
7780 case Intrinsic::x86_sse2_ucomige_sd:
7781 Opc = X86ISD::UCOMI;
7784 case Intrinsic::x86_sse_ucomineq_ss:
7785 case Intrinsic::x86_sse2_ucomineq_sd:
7786 Opc = X86ISD::UCOMI;
7791 SDValue LHS = Op.getOperand(1);
7792 SDValue RHS = Op.getOperand(2);
7793 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7794 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7795 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7796 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7797 DAG.getConstant(X86CC, MVT::i8), Cond);
7798 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7800 // ptest and testp intrinsics. The intrinsic these come from are designed to
7801 // return an integer value, not just an instruction so lower it to the ptest
7802 // or testp pattern and a setcc for the result.
7803 case Intrinsic::x86_sse41_ptestz:
7804 case Intrinsic::x86_sse41_ptestc:
7805 case Intrinsic::x86_sse41_ptestnzc:
7806 case Intrinsic::x86_avx_ptestz_256:
7807 case Intrinsic::x86_avx_ptestc_256:
7808 case Intrinsic::x86_avx_ptestnzc_256:
7809 case Intrinsic::x86_avx_vtestz_ps:
7810 case Intrinsic::x86_avx_vtestc_ps:
7811 case Intrinsic::x86_avx_vtestnzc_ps:
7812 case Intrinsic::x86_avx_vtestz_pd:
7813 case Intrinsic::x86_avx_vtestc_pd:
7814 case Intrinsic::x86_avx_vtestnzc_pd:
7815 case Intrinsic::x86_avx_vtestz_ps_256:
7816 case Intrinsic::x86_avx_vtestc_ps_256:
7817 case Intrinsic::x86_avx_vtestnzc_ps_256:
7818 case Intrinsic::x86_avx_vtestz_pd_256:
7819 case Intrinsic::x86_avx_vtestc_pd_256:
7820 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7821 bool IsTestPacked = false;
7824 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7825 case Intrinsic::x86_avx_vtestz_ps:
7826 case Intrinsic::x86_avx_vtestz_pd:
7827 case Intrinsic::x86_avx_vtestz_ps_256:
7828 case Intrinsic::x86_avx_vtestz_pd_256:
7829 IsTestPacked = true; // Fallthrough
7830 case Intrinsic::x86_sse41_ptestz:
7831 case Intrinsic::x86_avx_ptestz_256:
7833 X86CC = X86::COND_E;
7835 case Intrinsic::x86_avx_vtestc_ps:
7836 case Intrinsic::x86_avx_vtestc_pd:
7837 case Intrinsic::x86_avx_vtestc_ps_256:
7838 case Intrinsic::x86_avx_vtestc_pd_256:
7839 IsTestPacked = true; // Fallthrough
7840 case Intrinsic::x86_sse41_ptestc:
7841 case Intrinsic::x86_avx_ptestc_256:
7843 X86CC = X86::COND_B;
7845 case Intrinsic::x86_avx_vtestnzc_ps:
7846 case Intrinsic::x86_avx_vtestnzc_pd:
7847 case Intrinsic::x86_avx_vtestnzc_ps_256:
7848 case Intrinsic::x86_avx_vtestnzc_pd_256:
7849 IsTestPacked = true; // Fallthrough
7850 case Intrinsic::x86_sse41_ptestnzc:
7851 case Intrinsic::x86_avx_ptestnzc_256:
7853 X86CC = X86::COND_A;
7857 SDValue LHS = Op.getOperand(1);
7858 SDValue RHS = Op.getOperand(2);
7859 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7860 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7861 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7862 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7863 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7866 // Fix vector shift instructions where the last operand is a non-immediate
7868 case Intrinsic::x86_sse2_pslli_w:
7869 case Intrinsic::x86_sse2_pslli_d:
7870 case Intrinsic::x86_sse2_pslli_q:
7871 case Intrinsic::x86_sse2_psrli_w:
7872 case Intrinsic::x86_sse2_psrli_d:
7873 case Intrinsic::x86_sse2_psrli_q:
7874 case Intrinsic::x86_sse2_psrai_w:
7875 case Intrinsic::x86_sse2_psrai_d:
7876 case Intrinsic::x86_mmx_pslli_w:
7877 case Intrinsic::x86_mmx_pslli_d:
7878 case Intrinsic::x86_mmx_pslli_q:
7879 case Intrinsic::x86_mmx_psrli_w:
7880 case Intrinsic::x86_mmx_psrli_d:
7881 case Intrinsic::x86_mmx_psrli_q:
7882 case Intrinsic::x86_mmx_psrai_w:
7883 case Intrinsic::x86_mmx_psrai_d: {
7884 SDValue ShAmt = Op.getOperand(2);
7885 if (isa<ConstantSDNode>(ShAmt))
7888 unsigned NewIntNo = 0;
7889 EVT ShAmtVT = MVT::v4i32;
7891 case Intrinsic::x86_sse2_pslli_w:
7892 NewIntNo = Intrinsic::x86_sse2_psll_w;
7894 case Intrinsic::x86_sse2_pslli_d:
7895 NewIntNo = Intrinsic::x86_sse2_psll_d;
7897 case Intrinsic::x86_sse2_pslli_q:
7898 NewIntNo = Intrinsic::x86_sse2_psll_q;
7900 case Intrinsic::x86_sse2_psrli_w:
7901 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7903 case Intrinsic::x86_sse2_psrli_d:
7904 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7906 case Intrinsic::x86_sse2_psrli_q:
7907 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7909 case Intrinsic::x86_sse2_psrai_w:
7910 NewIntNo = Intrinsic::x86_sse2_psra_w;
7912 case Intrinsic::x86_sse2_psrai_d:
7913 NewIntNo = Intrinsic::x86_sse2_psra_d;
7916 ShAmtVT = MVT::v2i32;
7918 case Intrinsic::x86_mmx_pslli_w:
7919 NewIntNo = Intrinsic::x86_mmx_psll_w;
7921 case Intrinsic::x86_mmx_pslli_d:
7922 NewIntNo = Intrinsic::x86_mmx_psll_d;
7924 case Intrinsic::x86_mmx_pslli_q:
7925 NewIntNo = Intrinsic::x86_mmx_psll_q;
7927 case Intrinsic::x86_mmx_psrli_w:
7928 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7930 case Intrinsic::x86_mmx_psrli_d:
7931 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7933 case Intrinsic::x86_mmx_psrli_q:
7934 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7936 case Intrinsic::x86_mmx_psrai_w:
7937 NewIntNo = Intrinsic::x86_mmx_psra_w;
7939 case Intrinsic::x86_mmx_psrai_d:
7940 NewIntNo = Intrinsic::x86_mmx_psra_d;
7942 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7948 // The vector shift intrinsics with scalars uses 32b shift amounts but
7949 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7953 ShOps[1] = DAG.getConstant(0, MVT::i32);
7954 if (ShAmtVT == MVT::v4i32) {
7955 ShOps[2] = DAG.getUNDEF(MVT::i32);
7956 ShOps[3] = DAG.getUNDEF(MVT::i32);
7957 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7959 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7960 // FIXME this must be lowered to get rid of the invalid type.
7963 EVT VT = Op.getValueType();
7964 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
7965 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7966 DAG.getConstant(NewIntNo, MVT::i32),
7967 Op.getOperand(1), ShAmt);
7972 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7973 SelectionDAG &DAG) const {
7974 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7975 MFI->setReturnAddressIsTaken(true);
7977 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7978 DebugLoc dl = Op.getDebugLoc();
7981 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7983 DAG.getConstant(TD->getPointerSize(),
7984 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7985 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7986 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7988 MachinePointerInfo(), false, false, 0);
7991 // Just load the return address.
7992 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7993 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7994 RetAddrFI, MachinePointerInfo(), false, false, 0);
7997 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7998 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7999 MFI->setFrameAddressIsTaken(true);
8001 EVT VT = Op.getValueType();
8002 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
8003 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8004 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
8005 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
8007 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
8008 MachinePointerInfo(),
8013 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
8014 SelectionDAG &DAG) const {
8015 return DAG.getIntPtrConstant(2*TD->getPointerSize());
8018 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
8019 MachineFunction &MF = DAG.getMachineFunction();
8020 SDValue Chain = Op.getOperand(0);
8021 SDValue Offset = Op.getOperand(1);
8022 SDValue Handler = Op.getOperand(2);
8023 DebugLoc dl = Op.getDebugLoc();
8025 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
8026 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
8028 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
8030 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
8031 DAG.getIntPtrConstant(TD->getPointerSize()));
8032 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
8033 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
8035 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
8036 MF.getRegInfo().addLiveOut(StoreAddrReg);
8038 return DAG.getNode(X86ISD::EH_RETURN, dl,
8040 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
8043 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
8044 SelectionDAG &DAG) const {
8045 SDValue Root = Op.getOperand(0);
8046 SDValue Trmp = Op.getOperand(1); // trampoline
8047 SDValue FPtr = Op.getOperand(2); // nested function
8048 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
8049 DebugLoc dl = Op.getDebugLoc();
8051 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8053 if (Subtarget->is64Bit()) {
8054 SDValue OutChains[6];
8056 // Large code-model.
8057 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
8058 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
8060 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
8061 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
8063 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
8065 // Load the pointer to the nested function into R11.
8066 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
8067 SDValue Addr = Trmp;
8068 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8069 Addr, MachinePointerInfo(TrmpAddr),
8072 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8073 DAG.getConstant(2, MVT::i64));
8074 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8075 MachinePointerInfo(TrmpAddr, 2),
8078 // Load the 'nest' parameter value into R10.
8079 // R10 is specified in X86CallingConv.td
8080 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8081 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8082 DAG.getConstant(10, MVT::i64));
8083 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8084 Addr, MachinePointerInfo(TrmpAddr, 10),
8087 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8088 DAG.getConstant(12, MVT::i64));
8089 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8090 MachinePointerInfo(TrmpAddr, 12),
8093 // Jump to the nested function.
8094 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8095 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8096 DAG.getConstant(20, MVT::i64));
8097 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8098 Addr, MachinePointerInfo(TrmpAddr, 20),
8101 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8102 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8103 DAG.getConstant(22, MVT::i64));
8104 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8105 MachinePointerInfo(TrmpAddr, 22),
8109 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8110 return DAG.getMergeValues(Ops, 2, dl);
8112 const Function *Func =
8113 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8114 CallingConv::ID CC = Func->getCallingConv();
8119 llvm_unreachable("Unsupported calling convention");
8120 case CallingConv::C:
8121 case CallingConv::X86_StdCall: {
8122 // Pass 'nest' parameter in ECX.
8123 // Must be kept in sync with X86CallingConv.td
8126 // Check that ECX wasn't needed by an 'inreg' parameter.
8127 const FunctionType *FTy = Func->getFunctionType();
8128 const AttrListPtr &Attrs = Func->getAttributes();
8130 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8131 unsigned InRegCount = 0;
8134 for (FunctionType::param_iterator I = FTy->param_begin(),
8135 E = FTy->param_end(); I != E; ++I, ++Idx)
8136 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8137 // FIXME: should only count parameters that are lowered to integers.
8138 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8140 if (InRegCount > 2) {
8141 report_fatal_error("Nest register in use - reduce number of inreg"
8147 case CallingConv::X86_FastCall:
8148 case CallingConv::X86_ThisCall:
8149 case CallingConv::Fast:
8150 // Pass 'nest' parameter in EAX.
8151 // Must be kept in sync with X86CallingConv.td
8156 SDValue OutChains[4];
8159 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8160 DAG.getConstant(10, MVT::i32));
8161 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8163 // This is storing the opcode for MOV32ri.
8164 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8165 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8166 OutChains[0] = DAG.getStore(Root, dl,
8167 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8168 Trmp, MachinePointerInfo(TrmpAddr),
8171 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8172 DAG.getConstant(1, MVT::i32));
8173 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8174 MachinePointerInfo(TrmpAddr, 1),
8177 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8178 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8179 DAG.getConstant(5, MVT::i32));
8180 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8181 MachinePointerInfo(TrmpAddr, 5),
8184 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8185 DAG.getConstant(6, MVT::i32));
8186 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8187 MachinePointerInfo(TrmpAddr, 6),
8191 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8192 return DAG.getMergeValues(Ops, 2, dl);
8196 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8197 SelectionDAG &DAG) const {
8199 The rounding mode is in bits 11:10 of FPSR, and has the following
8206 FLT_ROUNDS, on the other hand, expects the following:
8213 To perform the conversion, we do:
8214 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8217 MachineFunction &MF = DAG.getMachineFunction();
8218 const TargetMachine &TM = MF.getTarget();
8219 const TargetFrameInfo &TFI = *TM.getFrameInfo();
8220 unsigned StackAlignment = TFI.getStackAlignment();
8221 EVT VT = Op.getValueType();
8222 DebugLoc DL = Op.getDebugLoc();
8224 // Save FP Control Word to stack slot
8225 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8226 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8229 MachineMemOperand *MMO =
8230 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8231 MachineMemOperand::MOStore, 2, 2);
8233 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8234 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8235 DAG.getVTList(MVT::Other),
8236 Ops, 2, MVT::i16, MMO);
8238 // Load FP Control Word from stack slot
8239 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8240 MachinePointerInfo(), false, false, 0);
8242 // Transform as necessary
8244 DAG.getNode(ISD::SRL, DL, MVT::i16,
8245 DAG.getNode(ISD::AND, DL, MVT::i16,
8246 CWD, DAG.getConstant(0x800, MVT::i16)),
8247 DAG.getConstant(11, MVT::i8));
8249 DAG.getNode(ISD::SRL, DL, MVT::i16,
8250 DAG.getNode(ISD::AND, DL, MVT::i16,
8251 CWD, DAG.getConstant(0x400, MVT::i16)),
8252 DAG.getConstant(9, MVT::i8));
8255 DAG.getNode(ISD::AND, DL, MVT::i16,
8256 DAG.getNode(ISD::ADD, DL, MVT::i16,
8257 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8258 DAG.getConstant(1, MVT::i16)),
8259 DAG.getConstant(3, MVT::i16));
8262 return DAG.getNode((VT.getSizeInBits() < 16 ?
8263 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8266 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8267 EVT VT = Op.getValueType();
8269 unsigned NumBits = VT.getSizeInBits();
8270 DebugLoc dl = Op.getDebugLoc();
8272 Op = Op.getOperand(0);
8273 if (VT == MVT::i8) {
8274 // Zero extend to i32 since there is not an i8 bsr.
8276 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8279 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8280 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8281 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8283 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8286 DAG.getConstant(NumBits+NumBits-1, OpVT),
8287 DAG.getConstant(X86::COND_E, MVT::i8),
8290 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8292 // Finally xor with NumBits-1.
8293 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8296 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8300 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8301 EVT VT = Op.getValueType();
8303 unsigned NumBits = VT.getSizeInBits();
8304 DebugLoc dl = Op.getDebugLoc();
8306 Op = Op.getOperand(0);
8307 if (VT == MVT::i8) {
8309 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8312 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8313 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8314 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8316 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8319 DAG.getConstant(NumBits, OpVT),
8320 DAG.getConstant(X86::COND_E, MVT::i8),
8323 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8326 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8330 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8331 EVT VT = Op.getValueType();
8332 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8333 DebugLoc dl = Op.getDebugLoc();
8335 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8336 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8337 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8338 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8339 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8341 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8342 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8343 // return AloBlo + AloBhi + AhiBlo;
8345 SDValue A = Op.getOperand(0);
8346 SDValue B = Op.getOperand(1);
8348 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8349 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8350 A, DAG.getConstant(32, MVT::i32));
8351 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8352 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8353 B, DAG.getConstant(32, MVT::i32));
8354 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8355 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8357 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8358 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8360 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8361 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8363 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8364 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8365 AloBhi, DAG.getConstant(32, MVT::i32));
8366 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8367 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8368 AhiBlo, DAG.getConstant(32, MVT::i32));
8369 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8370 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8374 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8375 EVT VT = Op.getValueType();
8376 DebugLoc dl = Op.getDebugLoc();
8377 SDValue R = Op.getOperand(0);
8379 LLVMContext *Context = DAG.getContext();
8381 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8383 if (VT == MVT::v4i32) {
8384 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8385 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8386 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8388 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8390 std::vector<Constant*> CV(4, CI);
8391 Constant *C = ConstantVector::get(CV);
8392 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8393 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8394 MachinePointerInfo::getConstantPool(),
8397 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8398 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
8399 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8400 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8402 if (VT == MVT::v16i8) {
8404 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8405 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8406 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8408 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8409 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8411 std::vector<Constant*> CVM1(16, CM1);
8412 std::vector<Constant*> CVM2(16, CM2);
8413 Constant *C = ConstantVector::get(CVM1);
8414 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8415 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8416 MachinePointerInfo::getConstantPool(),
8419 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8420 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8421 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8422 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8423 DAG.getConstant(4, MVT::i32));
8424 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8426 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8428 C = ConstantVector::get(CVM2);
8429 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8430 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8431 MachinePointerInfo::getConstantPool(),
8434 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8435 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8436 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8437 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8438 DAG.getConstant(2, MVT::i32));
8439 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8441 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8443 // return pblendv(r, r+r, a);
8444 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
8445 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8451 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8452 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8453 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8454 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8455 // has only one use.
8456 SDNode *N = Op.getNode();
8457 SDValue LHS = N->getOperand(0);
8458 SDValue RHS = N->getOperand(1);
8459 unsigned BaseOp = 0;
8461 DebugLoc DL = Op.getDebugLoc();
8462 switch (Op.getOpcode()) {
8463 default: llvm_unreachable("Unknown ovf instruction!");
8465 // A subtract of one will be selected as a INC. Note that INC doesn't
8466 // set CF, so we can't do this for UADDO.
8467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8468 if (C->getAPIntValue() == 1) {
8469 BaseOp = X86ISD::INC;
8473 BaseOp = X86ISD::ADD;
8477 BaseOp = X86ISD::ADD;
8481 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8482 // set CF, so we can't do this for USUBO.
8483 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8484 if (C->getAPIntValue() == 1) {
8485 BaseOp = X86ISD::DEC;
8489 BaseOp = X86ISD::SUB;
8493 BaseOp = X86ISD::SUB;
8497 BaseOp = X86ISD::SMUL;
8500 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
8501 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
8503 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
8506 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8507 DAG.getConstant(X86::COND_O, MVT::i32),
8508 SDValue(Sum.getNode(), 2));
8510 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8515 // Also sets EFLAGS.
8516 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8517 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
8520 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
8521 DAG.getConstant(Cond, MVT::i32),
8522 SDValue(Sum.getNode(), 1));
8524 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8528 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8529 DebugLoc dl = Op.getDebugLoc();
8531 if (!Subtarget->hasSSE2()) {
8532 SDValue Chain = Op.getOperand(0);
8533 SDValue Zero = DAG.getConstant(0,
8534 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8536 DAG.getRegister(X86::ESP, MVT::i32), // Base
8537 DAG.getTargetConstant(1, MVT::i8), // Scale
8538 DAG.getRegister(0, MVT::i32), // Index
8539 DAG.getTargetConstant(0, MVT::i32), // Disp
8540 DAG.getRegister(0, MVT::i32), // Segment.
8545 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8546 array_lengthof(Ops));
8547 return SDValue(Res, 0);
8550 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8552 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8554 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8555 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8556 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8557 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8559 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8560 if (!Op1 && !Op2 && !Op3 && Op4)
8561 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8563 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8564 if (Op1 && !Op2 && !Op3 && !Op4)
8565 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8567 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8569 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8572 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8573 EVT T = Op.getValueType();
8574 DebugLoc DL = Op.getDebugLoc();
8577 switch(T.getSimpleVT().SimpleTy) {
8579 assert(false && "Invalid value type!");
8580 case MVT::i8: Reg = X86::AL; size = 1; break;
8581 case MVT::i16: Reg = X86::AX; size = 2; break;
8582 case MVT::i32: Reg = X86::EAX; size = 4; break;
8584 assert(Subtarget->is64Bit() && "Node not type legal!");
8585 Reg = X86::RAX; size = 8;
8588 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
8589 Op.getOperand(2), SDValue());
8590 SDValue Ops[] = { cpIn.getValue(0),
8593 DAG.getTargetConstant(size, MVT::i8),
8595 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8596 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
8597 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
8600 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
8604 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8605 SelectionDAG &DAG) const {
8606 assert(Subtarget->is64Bit() && "Result not type legalized?");
8607 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8608 SDValue TheChain = Op.getOperand(0);
8609 DebugLoc dl = Op.getDebugLoc();
8610 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8611 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8612 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8614 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8615 DAG.getConstant(32, MVT::i8));
8617 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8620 return DAG.getMergeValues(Ops, 2, dl);
8623 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
8624 SelectionDAG &DAG) const {
8625 EVT SrcVT = Op.getOperand(0).getValueType();
8626 EVT DstVT = Op.getValueType();
8627 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8628 Subtarget->hasMMX() && "Unexpected custom BITCAST");
8629 assert((DstVT == MVT::i64 ||
8630 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8631 "Unexpected custom BITCAST");
8632 // i64 <=> MMX conversions are Legal.
8633 if (SrcVT==MVT::i64 && DstVT.isVector())
8635 if (DstVT==MVT::i64 && SrcVT.isVector())
8637 // MMX <=> MMX conversions are Legal.
8638 if (SrcVT.isVector() && DstVT.isVector())
8640 // All other conversions need to be expanded.
8644 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8645 SDNode *Node = Op.getNode();
8646 DebugLoc dl = Node->getDebugLoc();
8647 EVT T = Node->getValueType(0);
8648 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8649 DAG.getConstant(0, T), Node->getOperand(2));
8650 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8651 cast<AtomicSDNode>(Node)->getMemoryVT(),
8652 Node->getOperand(0),
8653 Node->getOperand(1), negOp,
8654 cast<AtomicSDNode>(Node)->getSrcValue(),
8655 cast<AtomicSDNode>(Node)->getAlignment());
8658 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
8659 EVT VT = Op.getNode()->getValueType(0);
8661 // Let legalize expand this if it isn't a legal type yet.
8662 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8665 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
8668 bool ExtraOp = false;
8669 switch (Op.getOpcode()) {
8670 default: assert(0 && "Invalid code");
8671 case ISD::ADDC: Opc = X86ISD::ADD; break;
8672 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
8673 case ISD::SUBC: Opc = X86ISD::SUB; break;
8674 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
8678 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
8680 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
8681 Op.getOperand(1), Op.getOperand(2));
8684 /// LowerOperation - Provide custom lowering hooks for some operations.
8686 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8687 switch (Op.getOpcode()) {
8688 default: llvm_unreachable("Should not custom lower this!");
8689 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8690 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8691 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8692 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8693 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8694 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8695 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8696 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8697 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8698 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8699 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8700 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8701 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8702 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8703 case ISD::SHL_PARTS:
8704 case ISD::SRA_PARTS:
8705 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8706 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8707 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8708 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8709 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8710 case ISD::FABS: return LowerFABS(Op, DAG);
8711 case ISD::FNEG: return LowerFNEG(Op, DAG);
8712 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8713 case ISD::SETCC: return LowerSETCC(Op, DAG);
8714 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8715 case ISD::SELECT: return LowerSELECT(Op, DAG);
8716 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8717 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8718 case ISD::VASTART: return LowerVASTART(Op, DAG);
8719 case ISD::VAARG: return LowerVAARG(Op, DAG);
8720 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8721 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8722 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8723 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8724 case ISD::FRAME_TO_ARGS_OFFSET:
8725 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8726 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8727 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8728 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8729 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8730 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8731 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8732 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8733 case ISD::SHL: return LowerSHL(Op, DAG);
8739 case ISD::UMULO: return LowerXALUO(Op, DAG);
8740 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8741 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
8745 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
8749 void X86TargetLowering::
8750 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8751 SelectionDAG &DAG, unsigned NewOp) const {
8752 EVT T = Node->getValueType(0);
8753 DebugLoc dl = Node->getDebugLoc();
8754 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8756 SDValue Chain = Node->getOperand(0);
8757 SDValue In1 = Node->getOperand(1);
8758 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8759 Node->getOperand(2), DAG.getIntPtrConstant(0));
8760 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8761 Node->getOperand(2), DAG.getIntPtrConstant(1));
8762 SDValue Ops[] = { Chain, In1, In2L, In2H };
8763 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8765 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8766 cast<MemSDNode>(Node)->getMemOperand());
8767 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8768 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8769 Results.push_back(Result.getValue(2));
8772 /// ReplaceNodeResults - Replace a node with an illegal result type
8773 /// with a new node built out of custom code.
8774 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8775 SmallVectorImpl<SDValue>&Results,
8776 SelectionDAG &DAG) const {
8777 DebugLoc dl = N->getDebugLoc();
8778 switch (N->getOpcode()) {
8780 assert(false && "Do not know how to custom type legalize this operation!");
8786 // We don't want to expand or promote these.
8788 case ISD::FP_TO_SINT: {
8789 std::pair<SDValue,SDValue> Vals =
8790 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8791 SDValue FIST = Vals.first, StackSlot = Vals.second;
8792 if (FIST.getNode() != 0) {
8793 EVT VT = N->getValueType(0);
8794 // Return a load from the stack slot.
8795 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
8796 MachinePointerInfo(), false, false, 0));
8800 case ISD::READCYCLECOUNTER: {
8801 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8802 SDValue TheChain = N->getOperand(0);
8803 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8804 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8806 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8808 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8809 SDValue Ops[] = { eax, edx };
8810 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8811 Results.push_back(edx.getValue(1));
8814 case ISD::ATOMIC_CMP_SWAP: {
8815 EVT T = N->getValueType(0);
8816 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8817 SDValue cpInL, cpInH;
8818 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8819 DAG.getConstant(0, MVT::i32));
8820 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8821 DAG.getConstant(1, MVT::i32));
8822 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8823 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8825 SDValue swapInL, swapInH;
8826 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8827 DAG.getConstant(0, MVT::i32));
8828 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8829 DAG.getConstant(1, MVT::i32));
8830 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8832 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8833 swapInL.getValue(1));
8834 SDValue Ops[] = { swapInH.getValue(0),
8836 swapInH.getValue(1) };
8837 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8838 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
8839 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
8841 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8842 MVT::i32, Result.getValue(1));
8843 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8844 MVT::i32, cpOutL.getValue(2));
8845 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8846 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8847 Results.push_back(cpOutH.getValue(1));
8850 case ISD::ATOMIC_LOAD_ADD:
8851 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8853 case ISD::ATOMIC_LOAD_AND:
8854 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8856 case ISD::ATOMIC_LOAD_NAND:
8857 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8859 case ISD::ATOMIC_LOAD_OR:
8860 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8862 case ISD::ATOMIC_LOAD_SUB:
8863 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8865 case ISD::ATOMIC_LOAD_XOR:
8866 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8868 case ISD::ATOMIC_SWAP:
8869 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8874 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8876 default: return NULL;
8877 case X86ISD::BSF: return "X86ISD::BSF";
8878 case X86ISD::BSR: return "X86ISD::BSR";
8879 case X86ISD::SHLD: return "X86ISD::SHLD";
8880 case X86ISD::SHRD: return "X86ISD::SHRD";
8881 case X86ISD::FAND: return "X86ISD::FAND";
8882 case X86ISD::FOR: return "X86ISD::FOR";
8883 case X86ISD::FXOR: return "X86ISD::FXOR";
8884 case X86ISD::FSRL: return "X86ISD::FSRL";
8885 case X86ISD::FILD: return "X86ISD::FILD";
8886 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8887 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8888 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8889 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8890 case X86ISD::FLD: return "X86ISD::FLD";
8891 case X86ISD::FST: return "X86ISD::FST";
8892 case X86ISD::CALL: return "X86ISD::CALL";
8893 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8894 case X86ISD::BT: return "X86ISD::BT";
8895 case X86ISD::CMP: return "X86ISD::CMP";
8896 case X86ISD::COMI: return "X86ISD::COMI";
8897 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8898 case X86ISD::SETCC: return "X86ISD::SETCC";
8899 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8900 case X86ISD::CMOV: return "X86ISD::CMOV";
8901 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8902 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8903 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8904 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8905 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8906 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8907 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8908 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8909 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8910 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8911 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8912 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8913 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8914 case X86ISD::PANDN: return "X86ISD::PANDN";
8915 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
8916 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
8917 case X86ISD::PSIGND: return "X86ISD::PSIGND";
8918 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
8919 case X86ISD::FMAX: return "X86ISD::FMAX";
8920 case X86ISD::FMIN: return "X86ISD::FMIN";
8921 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8922 case X86ISD::FRCP: return "X86ISD::FRCP";
8923 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8924 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8925 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8926 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8927 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8928 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8929 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8930 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8931 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8932 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8933 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8934 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8935 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8936 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8937 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8938 case X86ISD::VSHL: return "X86ISD::VSHL";
8939 case X86ISD::VSRL: return "X86ISD::VSRL";
8940 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8941 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8942 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8943 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8944 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8945 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8946 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8947 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8948 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8949 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8950 case X86ISD::ADD: return "X86ISD::ADD";
8951 case X86ISD::SUB: return "X86ISD::SUB";
8952 case X86ISD::ADC: return "X86ISD::ADC";
8953 case X86ISD::SBB: return "X86ISD::SBB";
8954 case X86ISD::SMUL: return "X86ISD::SMUL";
8955 case X86ISD::UMUL: return "X86ISD::UMUL";
8956 case X86ISD::INC: return "X86ISD::INC";
8957 case X86ISD::DEC: return "X86ISD::DEC";
8958 case X86ISD::OR: return "X86ISD::OR";
8959 case X86ISD::XOR: return "X86ISD::XOR";
8960 case X86ISD::AND: return "X86ISD::AND";
8961 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8962 case X86ISD::PTEST: return "X86ISD::PTEST";
8963 case X86ISD::TESTP: return "X86ISD::TESTP";
8964 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8965 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8966 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8967 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8968 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8969 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8970 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8971 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8972 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8973 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8974 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8975 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8976 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8977 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8978 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8979 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8980 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8981 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8982 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8983 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8984 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8985 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8986 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8987 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8988 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8989 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8990 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8991 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8992 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8993 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8994 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8995 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8996 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8997 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8998 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
8999 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
9003 // isLegalAddressingMode - Return true if the addressing mode represented
9004 // by AM is legal for this target, for a load/store of the specified type.
9005 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
9006 const Type *Ty) const {
9007 // X86 supports extremely general addressing modes.
9008 CodeModel::Model M = getTargetMachine().getCodeModel();
9009 Reloc::Model R = getTargetMachine().getRelocationModel();
9011 // X86 allows a sign-extended 32-bit immediate field as a displacement.
9012 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
9017 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
9019 // If a reference to this global requires an extra load, we can't fold it.
9020 if (isGlobalStubReference(GVFlags))
9023 // If BaseGV requires a register for the PIC base, we cannot also have a
9024 // BaseReg specified.
9025 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
9028 // If lower 4G is not available, then we must use rip-relative addressing.
9029 if ((M != CodeModel::Small || R != Reloc::Static) &&
9030 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
9040 // These scales always work.
9045 // These scales are formed with basereg+scalereg. Only accept if there is
9050 default: // Other stuff never works.
9058 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
9059 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9061 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9062 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9063 if (NumBits1 <= NumBits2)
9068 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9069 if (!VT1.isInteger() || !VT2.isInteger())
9071 unsigned NumBits1 = VT1.getSizeInBits();
9072 unsigned NumBits2 = VT2.getSizeInBits();
9073 if (NumBits1 <= NumBits2)
9078 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
9079 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9080 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
9083 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
9084 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9085 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
9088 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
9089 // i16 instructions are longer (0x66 prefix) and potentially slower.
9090 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
9093 /// isShuffleMaskLegal - Targets can use this to indicate that they only
9094 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
9095 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
9096 /// are assumed to be legal.
9098 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
9100 // Very little shuffling can be done for 64-bit vectors right now.
9101 if (VT.getSizeInBits() == 64)
9102 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
9104 // FIXME: pshufb, blends, shifts.
9105 return (VT.getVectorNumElements() == 2 ||
9106 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
9107 isMOVLMask(M, VT) ||
9108 isSHUFPMask(M, VT) ||
9109 isPSHUFDMask(M, VT) ||
9110 isPSHUFHWMask(M, VT) ||
9111 isPSHUFLWMask(M, VT) ||
9112 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
9113 isUNPCKLMask(M, VT) ||
9114 isUNPCKHMask(M, VT) ||
9115 isUNPCKL_v_undef_Mask(M, VT) ||
9116 isUNPCKH_v_undef_Mask(M, VT));
9120 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
9122 unsigned NumElts = VT.getVectorNumElements();
9123 // FIXME: This collection of masks seems suspect.
9126 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9127 return (isMOVLMask(Mask, VT) ||
9128 isCommutedMOVLMask(Mask, VT, true) ||
9129 isSHUFPMask(Mask, VT) ||
9130 isCommutedSHUFPMask(Mask, VT));
9135 //===----------------------------------------------------------------------===//
9136 // X86 Scheduler Hooks
9137 //===----------------------------------------------------------------------===//
9139 // private utility function
9141 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9142 MachineBasicBlock *MBB,
9149 TargetRegisterClass *RC,
9150 bool invSrc) const {
9151 // For the atomic bitwise operator, we generate
9154 // ld t1 = [bitinstr.addr]
9155 // op t2 = t1, [bitinstr.val]
9157 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9159 // fallthrough -->nextMBB
9160 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9161 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9162 MachineFunction::iterator MBBIter = MBB;
9165 /// First build the CFG
9166 MachineFunction *F = MBB->getParent();
9167 MachineBasicBlock *thisMBB = MBB;
9168 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9169 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9170 F->insert(MBBIter, newMBB);
9171 F->insert(MBBIter, nextMBB);
9173 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9174 nextMBB->splice(nextMBB->begin(), thisMBB,
9175 llvm::next(MachineBasicBlock::iterator(bInstr)),
9177 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9179 // Update thisMBB to fall through to newMBB
9180 thisMBB->addSuccessor(newMBB);
9182 // newMBB jumps to itself and fall through to nextMBB
9183 newMBB->addSuccessor(nextMBB);
9184 newMBB->addSuccessor(newMBB);
9186 // Insert instructions into newMBB based on incoming instruction
9187 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9188 "unexpected number of operands");
9189 DebugLoc dl = bInstr->getDebugLoc();
9190 MachineOperand& destOper = bInstr->getOperand(0);
9191 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9192 int numArgs = bInstr->getNumOperands() - 1;
9193 for (int i=0; i < numArgs; ++i)
9194 argOpers[i] = &bInstr->getOperand(i+1);
9196 // x86 address has 4 operands: base, index, scale, and displacement
9197 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9198 int valArgIndx = lastAddrIndx + 1;
9200 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9201 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9202 for (int i=0; i <= lastAddrIndx; ++i)
9203 (*MIB).addOperand(*argOpers[i]);
9205 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9207 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9212 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9213 assert((argOpers[valArgIndx]->isReg() ||
9214 argOpers[valArgIndx]->isImm()) &&
9216 if (argOpers[valArgIndx]->isReg())
9217 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9219 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9221 (*MIB).addOperand(*argOpers[valArgIndx]);
9223 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9226 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9227 for (int i=0; i <= lastAddrIndx; ++i)
9228 (*MIB).addOperand(*argOpers[i]);
9230 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9231 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9232 bInstr->memoperands_end());
9234 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9238 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9240 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9244 // private utility function: 64 bit atomics on 32 bit host.
9246 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9247 MachineBasicBlock *MBB,
9252 bool invSrc) const {
9253 // For the atomic bitwise operator, we generate
9254 // thisMBB (instructions are in pairs, except cmpxchg8b)
9255 // ld t1,t2 = [bitinstr.addr]
9257 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9258 // op t5, t6 <- out1, out2, [bitinstr.val]
9259 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9260 // mov ECX, EBX <- t5, t6
9261 // mov EAX, EDX <- t1, t2
9262 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9263 // mov t3, t4 <- EAX, EDX
9265 // result in out1, out2
9266 // fallthrough -->nextMBB
9268 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9269 const unsigned LoadOpc = X86::MOV32rm;
9270 const unsigned NotOpc = X86::NOT32r;
9271 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9272 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9273 MachineFunction::iterator MBBIter = MBB;
9276 /// First build the CFG
9277 MachineFunction *F = MBB->getParent();
9278 MachineBasicBlock *thisMBB = MBB;
9279 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9280 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9281 F->insert(MBBIter, newMBB);
9282 F->insert(MBBIter, nextMBB);
9284 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9285 nextMBB->splice(nextMBB->begin(), thisMBB,
9286 llvm::next(MachineBasicBlock::iterator(bInstr)),
9288 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9290 // Update thisMBB to fall through to newMBB
9291 thisMBB->addSuccessor(newMBB);
9293 // newMBB jumps to itself and fall through to nextMBB
9294 newMBB->addSuccessor(nextMBB);
9295 newMBB->addSuccessor(newMBB);
9297 DebugLoc dl = bInstr->getDebugLoc();
9298 // Insert instructions into newMBB based on incoming instruction
9299 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9300 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9301 "unexpected number of operands");
9302 MachineOperand& dest1Oper = bInstr->getOperand(0);
9303 MachineOperand& dest2Oper = bInstr->getOperand(1);
9304 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9305 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9306 argOpers[i] = &bInstr->getOperand(i+2);
9308 // We use some of the operands multiple times, so conservatively just
9309 // clear any kill flags that might be present.
9310 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9311 argOpers[i]->setIsKill(false);
9314 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9315 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9317 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9318 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9319 for (int i=0; i <= lastAddrIndx; ++i)
9320 (*MIB).addOperand(*argOpers[i]);
9321 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9322 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9323 // add 4 to displacement.
9324 for (int i=0; i <= lastAddrIndx-2; ++i)
9325 (*MIB).addOperand(*argOpers[i]);
9326 MachineOperand newOp3 = *(argOpers[3]);
9328 newOp3.setImm(newOp3.getImm()+4);
9330 newOp3.setOffset(newOp3.getOffset()+4);
9331 (*MIB).addOperand(newOp3);
9332 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9334 // t3/4 are defined later, at the bottom of the loop
9335 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9336 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9337 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9338 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9339 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9340 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9342 // The subsequent operations should be using the destination registers of
9343 //the PHI instructions.
9345 t1 = F->getRegInfo().createVirtualRegister(RC);
9346 t2 = F->getRegInfo().createVirtualRegister(RC);
9347 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9348 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9350 t1 = dest1Oper.getReg();
9351 t2 = dest2Oper.getReg();
9354 int valArgIndx = lastAddrIndx + 1;
9355 assert((argOpers[valArgIndx]->isReg() ||
9356 argOpers[valArgIndx]->isImm()) &&
9358 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9359 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9360 if (argOpers[valArgIndx]->isReg())
9361 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9363 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9364 if (regOpcL != X86::MOV32rr)
9366 (*MIB).addOperand(*argOpers[valArgIndx]);
9367 assert(argOpers[valArgIndx + 1]->isReg() ==
9368 argOpers[valArgIndx]->isReg());
9369 assert(argOpers[valArgIndx + 1]->isImm() ==
9370 argOpers[valArgIndx]->isImm());
9371 if (argOpers[valArgIndx + 1]->isReg())
9372 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9374 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9375 if (regOpcH != X86::MOV32rr)
9377 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9379 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9381 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9384 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9386 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9389 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9390 for (int i=0; i <= lastAddrIndx; ++i)
9391 (*MIB).addOperand(*argOpers[i]);
9393 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9394 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9395 bInstr->memoperands_end());
9397 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9398 MIB.addReg(X86::EAX);
9399 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9400 MIB.addReg(X86::EDX);
9403 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9405 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9409 // private utility function
9411 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9412 MachineBasicBlock *MBB,
9413 unsigned cmovOpc) const {
9414 // For the atomic min/max operator, we generate
9417 // ld t1 = [min/max.addr]
9418 // mov t2 = [min/max.val]
9420 // cmov[cond] t2 = t1
9422 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9424 // fallthrough -->nextMBB
9426 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9427 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9428 MachineFunction::iterator MBBIter = MBB;
9431 /// First build the CFG
9432 MachineFunction *F = MBB->getParent();
9433 MachineBasicBlock *thisMBB = MBB;
9434 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9435 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9436 F->insert(MBBIter, newMBB);
9437 F->insert(MBBIter, nextMBB);
9439 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9440 nextMBB->splice(nextMBB->begin(), thisMBB,
9441 llvm::next(MachineBasicBlock::iterator(mInstr)),
9443 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9445 // Update thisMBB to fall through to newMBB
9446 thisMBB->addSuccessor(newMBB);
9448 // newMBB jumps to newMBB and fall through to nextMBB
9449 newMBB->addSuccessor(nextMBB);
9450 newMBB->addSuccessor(newMBB);
9452 DebugLoc dl = mInstr->getDebugLoc();
9453 // Insert instructions into newMBB based on incoming instruction
9454 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9455 "unexpected number of operands");
9456 MachineOperand& destOper = mInstr->getOperand(0);
9457 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9458 int numArgs = mInstr->getNumOperands() - 1;
9459 for (int i=0; i < numArgs; ++i)
9460 argOpers[i] = &mInstr->getOperand(i+1);
9462 // x86 address has 4 operands: base, index, scale, and displacement
9463 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9464 int valArgIndx = lastAddrIndx + 1;
9466 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9467 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9468 for (int i=0; i <= lastAddrIndx; ++i)
9469 (*MIB).addOperand(*argOpers[i]);
9471 // We only support register and immediate values
9472 assert((argOpers[valArgIndx]->isReg() ||
9473 argOpers[valArgIndx]->isImm()) &&
9476 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9477 if (argOpers[valArgIndx]->isReg())
9478 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9480 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9481 (*MIB).addOperand(*argOpers[valArgIndx]);
9483 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9486 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9491 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9492 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9496 // Cmp and exchange if none has modified the memory location
9497 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9498 for (int i=0; i <= lastAddrIndx; ++i)
9499 (*MIB).addOperand(*argOpers[i]);
9501 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9502 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9503 mInstr->memoperands_end());
9505 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9506 MIB.addReg(X86::EAX);
9509 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9511 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9515 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9516 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9519 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9520 unsigned numArgs, bool memArg) const {
9521 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9522 "Target must have SSE4.2 or AVX features enabled");
9524 DebugLoc dl = MI->getDebugLoc();
9525 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9527 if (!Subtarget->hasAVX()) {
9529 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9531 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9534 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9536 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9539 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
9540 for (unsigned i = 0; i < numArgs; ++i) {
9541 MachineOperand &Op = MI->getOperand(i+1);
9542 if (!(Op.isReg() && Op.isImplicit()))
9545 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9548 MI->eraseFromParent();
9553 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
9554 DebugLoc dl = MI->getDebugLoc();
9555 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9557 // Address into RAX/EAX, other two args into ECX, EDX.
9558 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
9559 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
9560 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
9561 for (int i = 0; i < X86::AddrNumOperands; ++i)
9562 MIB.addOperand(MI->getOperand(i));
9564 unsigned ValOps = X86::AddrNumOperands;
9565 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9566 .addReg(MI->getOperand(ValOps).getReg());
9567 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
9568 .addReg(MI->getOperand(ValOps+1).getReg());
9570 // The instruction doesn't actually take any operands though.
9571 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
9573 MI->eraseFromParent(); // The pseudo is gone now.
9578 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
9579 DebugLoc dl = MI->getDebugLoc();
9580 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9582 // First arg in ECX, the second in EAX.
9583 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9584 .addReg(MI->getOperand(0).getReg());
9585 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
9586 .addReg(MI->getOperand(1).getReg());
9588 // The instruction doesn't actually take any operands though.
9589 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
9591 MI->eraseFromParent(); // The pseudo is gone now.
9596 X86TargetLowering::EmitVAARG64WithCustomInserter(
9598 MachineBasicBlock *MBB) const {
9599 // Emit va_arg instruction on X86-64.
9601 // Operands to this pseudo-instruction:
9602 // 0 ) Output : destination address (reg)
9603 // 1-5) Input : va_list address (addr, i64mem)
9604 // 6 ) ArgSize : Size (in bytes) of vararg type
9605 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
9606 // 8 ) Align : Alignment of type
9607 // 9 ) EFLAGS (implicit-def)
9609 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
9610 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
9612 unsigned DestReg = MI->getOperand(0).getReg();
9613 MachineOperand &Base = MI->getOperand(1);
9614 MachineOperand &Scale = MI->getOperand(2);
9615 MachineOperand &Index = MI->getOperand(3);
9616 MachineOperand &Disp = MI->getOperand(4);
9617 MachineOperand &Segment = MI->getOperand(5);
9618 unsigned ArgSize = MI->getOperand(6).getImm();
9619 unsigned ArgMode = MI->getOperand(7).getImm();
9620 unsigned Align = MI->getOperand(8).getImm();
9623 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
9624 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
9625 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
9627 // Machine Information
9628 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9629 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
9630 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
9631 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
9632 DebugLoc DL = MI->getDebugLoc();
9637 // i64 overflow_area (address)
9638 // i64 reg_save_area (address)
9640 // sizeof(va_list) = 24
9641 // alignment(va_list) = 8
9643 unsigned TotalNumIntRegs = 6;
9644 unsigned TotalNumXMMRegs = 8;
9645 bool UseGPOffset = (ArgMode == 1);
9646 bool UseFPOffset = (ArgMode == 2);
9647 unsigned MaxOffset = TotalNumIntRegs * 8 +
9648 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
9650 /* Align ArgSize to a multiple of 8 */
9651 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
9652 bool NeedsAlign = (Align > 8);
9654 MachineBasicBlock *thisMBB = MBB;
9655 MachineBasicBlock *overflowMBB;
9656 MachineBasicBlock *offsetMBB;
9657 MachineBasicBlock *endMBB;
9659 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
9660 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
9661 unsigned OffsetReg = 0;
9663 if (!UseGPOffset && !UseFPOffset) {
9664 // If we only pull from the overflow region, we don't create a branch.
9665 // We don't need to alter control flow.
9666 OffsetDestReg = 0; // unused
9667 OverflowDestReg = DestReg;
9670 overflowMBB = thisMBB;
9673 // First emit code to check if gp_offset (or fp_offset) is below the bound.
9674 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
9675 // If not, pull from overflow_area. (branch to overflowMBB)
9680 // offsetMBB overflowMBB
9685 // Registers for the PHI in endMBB
9686 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
9687 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
9689 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9690 MachineFunction *MF = MBB->getParent();
9691 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9692 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9693 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9695 MachineFunction::iterator MBBIter = MBB;
9698 // Insert the new basic blocks
9699 MF->insert(MBBIter, offsetMBB);
9700 MF->insert(MBBIter, overflowMBB);
9701 MF->insert(MBBIter, endMBB);
9703 // Transfer the remainder of MBB and its successor edges to endMBB.
9704 endMBB->splice(endMBB->begin(), thisMBB,
9705 llvm::next(MachineBasicBlock::iterator(MI)),
9707 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9709 // Make offsetMBB and overflowMBB successors of thisMBB
9710 thisMBB->addSuccessor(offsetMBB);
9711 thisMBB->addSuccessor(overflowMBB);
9713 // endMBB is a successor of both offsetMBB and overflowMBB
9714 offsetMBB->addSuccessor(endMBB);
9715 overflowMBB->addSuccessor(endMBB);
9717 // Load the offset value into a register
9718 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9719 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
9723 .addDisp(Disp, UseFPOffset ? 4 : 0)
9724 .addOperand(Segment)
9725 .setMemRefs(MMOBegin, MMOEnd);
9727 // Check if there is enough room left to pull this argument.
9728 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
9730 .addImm(MaxOffset + 8 - ArgSizeA8);
9732 // Branch to "overflowMBB" if offset >= max
9733 // Fall through to "offsetMBB" otherwise
9734 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
9735 .addMBB(overflowMBB);
9738 // In offsetMBB, emit code to use the reg_save_area.
9740 assert(OffsetReg != 0);
9742 // Read the reg_save_area address.
9743 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
9744 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
9749 .addOperand(Segment)
9750 .setMemRefs(MMOBegin, MMOEnd);
9752 // Zero-extend the offset
9753 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
9754 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
9757 .addImm(X86::sub_32bit);
9759 // Add the offset to the reg_save_area to get the final address.
9760 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
9761 .addReg(OffsetReg64)
9762 .addReg(RegSaveReg);
9764 // Compute the offset for the next argument
9765 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9766 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
9768 .addImm(UseFPOffset ? 16 : 8);
9770 // Store it back into the va_list.
9771 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
9775 .addDisp(Disp, UseFPOffset ? 4 : 0)
9776 .addOperand(Segment)
9777 .addReg(NextOffsetReg)
9778 .setMemRefs(MMOBegin, MMOEnd);
9781 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
9786 // Emit code to use overflow area
9789 // Load the overflow_area address into a register.
9790 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
9791 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
9796 .addOperand(Segment)
9797 .setMemRefs(MMOBegin, MMOEnd);
9799 // If we need to align it, do so. Otherwise, just copy the address
9800 // to OverflowDestReg.
9802 // Align the overflow address
9803 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
9804 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
9806 // aligned_addr = (addr + (align-1)) & ~(align-1)
9807 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
9808 .addReg(OverflowAddrReg)
9811 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
9813 .addImm(~(uint64_t)(Align-1));
9815 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
9816 .addReg(OverflowAddrReg);
9819 // Compute the next overflow address after this argument.
9820 // (the overflow address should be kept 8-byte aligned)
9821 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
9822 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
9823 .addReg(OverflowDestReg)
9826 // Store the new overflow address.
9827 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
9832 .addOperand(Segment)
9833 .addReg(NextAddrReg)
9834 .setMemRefs(MMOBegin, MMOEnd);
9836 // If we branched, emit the PHI to the front of endMBB.
9838 BuildMI(*endMBB, endMBB->begin(), DL,
9839 TII->get(X86::PHI), DestReg)
9840 .addReg(OffsetDestReg).addMBB(offsetMBB)
9841 .addReg(OverflowDestReg).addMBB(overflowMBB);
9844 // Erase the pseudo instruction
9845 MI->eraseFromParent();
9851 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9853 MachineBasicBlock *MBB) const {
9854 // Emit code to save XMM registers to the stack. The ABI says that the
9855 // number of registers to save is given in %al, so it's theoretically
9856 // possible to do an indirect jump trick to avoid saving all of them,
9857 // however this code takes a simpler approach and just executes all
9858 // of the stores if %al is non-zero. It's less code, and it's probably
9859 // easier on the hardware branch predictor, and stores aren't all that
9860 // expensive anyway.
9862 // Create the new basic blocks. One block contains all the XMM stores,
9863 // and one block is the final destination regardless of whether any
9864 // stores were performed.
9865 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9866 MachineFunction *F = MBB->getParent();
9867 MachineFunction::iterator MBBIter = MBB;
9869 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9870 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9871 F->insert(MBBIter, XMMSaveMBB);
9872 F->insert(MBBIter, EndMBB);
9874 // Transfer the remainder of MBB and its successor edges to EndMBB.
9875 EndMBB->splice(EndMBB->begin(), MBB,
9876 llvm::next(MachineBasicBlock::iterator(MI)),
9878 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9880 // The original block will now fall through to the XMM save block.
9881 MBB->addSuccessor(XMMSaveMBB);
9882 // The XMMSaveMBB will fall through to the end block.
9883 XMMSaveMBB->addSuccessor(EndMBB);
9885 // Now add the instructions.
9886 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9887 DebugLoc DL = MI->getDebugLoc();
9889 unsigned CountReg = MI->getOperand(0).getReg();
9890 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9891 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9893 if (!Subtarget->isTargetWin64()) {
9894 // If %al is 0, branch around the XMM save block.
9895 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9896 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9897 MBB->addSuccessor(EndMBB);
9900 // In the XMM save block, save all the XMM argument registers.
9901 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9902 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9903 MachineMemOperand *MMO =
9904 F->getMachineMemOperand(
9905 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
9906 MachineMemOperand::MOStore,
9907 /*Size=*/16, /*Align=*/16);
9908 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9909 .addFrameIndex(RegSaveFrameIndex)
9910 .addImm(/*Scale=*/1)
9911 .addReg(/*IndexReg=*/0)
9912 .addImm(/*Disp=*/Offset)
9913 .addReg(/*Segment=*/0)
9914 .addReg(MI->getOperand(i).getReg())
9915 .addMemOperand(MMO);
9918 MI->eraseFromParent(); // The pseudo instruction is gone now.
9924 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9925 MachineBasicBlock *BB) const {
9926 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9927 DebugLoc DL = MI->getDebugLoc();
9929 // To "insert" a SELECT_CC instruction, we actually have to insert the
9930 // diamond control-flow pattern. The incoming instruction knows the
9931 // destination vreg to set, the condition code register to branch on, the
9932 // true/false values to select between, and a branch opcode to use.
9933 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9934 MachineFunction::iterator It = BB;
9940 // cmpTY ccX, r1, r2
9942 // fallthrough --> copy0MBB
9943 MachineBasicBlock *thisMBB = BB;
9944 MachineFunction *F = BB->getParent();
9945 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9946 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9947 F->insert(It, copy0MBB);
9948 F->insert(It, sinkMBB);
9950 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9951 // live into the sink and copy blocks.
9952 const MachineFunction *MF = BB->getParent();
9953 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9954 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9956 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9957 const MachineOperand &MO = MI->getOperand(I);
9958 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9959 unsigned Reg = MO.getReg();
9960 if (Reg != X86::EFLAGS) continue;
9961 copy0MBB->addLiveIn(Reg);
9962 sinkMBB->addLiveIn(Reg);
9965 // Transfer the remainder of BB and its successor edges to sinkMBB.
9966 sinkMBB->splice(sinkMBB->begin(), BB,
9967 llvm::next(MachineBasicBlock::iterator(MI)),
9969 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9971 // Add the true and fallthrough blocks as its successors.
9972 BB->addSuccessor(copy0MBB);
9973 BB->addSuccessor(sinkMBB);
9975 // Create the conditional branch instruction.
9977 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9978 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9981 // %FalseValue = ...
9982 // # fallthrough to sinkMBB
9983 copy0MBB->addSuccessor(sinkMBB);
9986 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9988 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9989 TII->get(X86::PHI), MI->getOperand(0).getReg())
9990 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9991 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9993 MI->eraseFromParent(); // The pseudo instruction is gone now.
9998 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
9999 MachineBasicBlock *BB) const {
10000 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10001 DebugLoc DL = MI->getDebugLoc();
10003 // The lowering is pretty easy: we're just emitting the call to _alloca. The
10004 // non-trivial part is impdef of ESP.
10005 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
10008 const char *StackProbeSymbol =
10009 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
10011 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
10012 .addExternalSymbol(StackProbeSymbol)
10013 .addReg(X86::EAX, RegState::Implicit)
10014 .addReg(X86::ESP, RegState::Implicit)
10015 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
10016 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
10017 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10019 MI->eraseFromParent(); // The pseudo instruction is gone now.
10023 MachineBasicBlock *
10024 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
10025 MachineBasicBlock *BB) const {
10026 // This is pretty easy. We're taking the value that we received from
10027 // our load from the relocation, sticking it in either RDI (x86-64)
10028 // or EAX and doing an indirect call. The return value will then
10029 // be in the normal return register.
10030 const X86InstrInfo *TII
10031 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
10032 DebugLoc DL = MI->getDebugLoc();
10033 MachineFunction *F = BB->getParent();
10035 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
10036 assert(MI->getOperand(3).isGlobal() && "This should be a global");
10038 if (Subtarget->is64Bit()) {
10039 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10040 TII->get(X86::MOV64rm), X86::RDI)
10042 .addImm(0).addReg(0)
10043 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10044 MI->getOperand(3).getTargetFlags())
10046 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
10047 addDirectMem(MIB, X86::RDI);
10048 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
10049 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10050 TII->get(X86::MOV32rm), X86::EAX)
10052 .addImm(0).addReg(0)
10053 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10054 MI->getOperand(3).getTargetFlags())
10056 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10057 addDirectMem(MIB, X86::EAX);
10059 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10060 TII->get(X86::MOV32rm), X86::EAX)
10061 .addReg(TII->getGlobalBaseReg(F))
10062 .addImm(0).addReg(0)
10063 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10064 MI->getOperand(3).getTargetFlags())
10066 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10067 addDirectMem(MIB, X86::EAX);
10070 MI->eraseFromParent(); // The pseudo instruction is gone now.
10074 MachineBasicBlock *
10075 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
10076 MachineBasicBlock *BB) const {
10077 switch (MI->getOpcode()) {
10078 default: assert(false && "Unexpected instr type to insert");
10079 case X86::WIN_ALLOCA:
10080 return EmitLoweredWinAlloca(MI, BB);
10081 case X86::TLSCall_32:
10082 case X86::TLSCall_64:
10083 return EmitLoweredTLSCall(MI, BB);
10084 case X86::CMOV_GR8:
10085 case X86::CMOV_FR32:
10086 case X86::CMOV_FR64:
10087 case X86::CMOV_V4F32:
10088 case X86::CMOV_V2F64:
10089 case X86::CMOV_V2I64:
10090 case X86::CMOV_GR16:
10091 case X86::CMOV_GR32:
10092 case X86::CMOV_RFP32:
10093 case X86::CMOV_RFP64:
10094 case X86::CMOV_RFP80:
10095 return EmitLoweredSelect(MI, BB);
10097 case X86::FP32_TO_INT16_IN_MEM:
10098 case X86::FP32_TO_INT32_IN_MEM:
10099 case X86::FP32_TO_INT64_IN_MEM:
10100 case X86::FP64_TO_INT16_IN_MEM:
10101 case X86::FP64_TO_INT32_IN_MEM:
10102 case X86::FP64_TO_INT64_IN_MEM:
10103 case X86::FP80_TO_INT16_IN_MEM:
10104 case X86::FP80_TO_INT32_IN_MEM:
10105 case X86::FP80_TO_INT64_IN_MEM: {
10106 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10107 DebugLoc DL = MI->getDebugLoc();
10109 // Change the floating point control register to use "round towards zero"
10110 // mode when truncating to an integer value.
10111 MachineFunction *F = BB->getParent();
10112 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
10113 addFrameReference(BuildMI(*BB, MI, DL,
10114 TII->get(X86::FNSTCW16m)), CWFrameIdx);
10116 // Load the old value of the high byte of the control word...
10118 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
10119 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
10122 // Set the high part to be round to zero...
10123 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
10126 // Reload the modified control word now...
10127 addFrameReference(BuildMI(*BB, MI, DL,
10128 TII->get(X86::FLDCW16m)), CWFrameIdx);
10130 // Restore the memory image of control word to original value
10131 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
10134 // Get the X86 opcode to use.
10136 switch (MI->getOpcode()) {
10137 default: llvm_unreachable("illegal opcode!");
10138 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
10139 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
10140 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
10141 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
10142 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
10143 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
10144 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
10145 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
10146 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
10150 MachineOperand &Op = MI->getOperand(0);
10152 AM.BaseType = X86AddressMode::RegBase;
10153 AM.Base.Reg = Op.getReg();
10155 AM.BaseType = X86AddressMode::FrameIndexBase;
10156 AM.Base.FrameIndex = Op.getIndex();
10158 Op = MI->getOperand(1);
10160 AM.Scale = Op.getImm();
10161 Op = MI->getOperand(2);
10163 AM.IndexReg = Op.getImm();
10164 Op = MI->getOperand(3);
10165 if (Op.isGlobal()) {
10166 AM.GV = Op.getGlobal();
10168 AM.Disp = Op.getImm();
10170 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
10171 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
10173 // Reload the original control word now.
10174 addFrameReference(BuildMI(*BB, MI, DL,
10175 TII->get(X86::FLDCW16m)), CWFrameIdx);
10177 MI->eraseFromParent(); // The pseudo instruction is gone now.
10180 // String/text processing lowering.
10181 case X86::PCMPISTRM128REG:
10182 case X86::VPCMPISTRM128REG:
10183 return EmitPCMP(MI, BB, 3, false /* in-mem */);
10184 case X86::PCMPISTRM128MEM:
10185 case X86::VPCMPISTRM128MEM:
10186 return EmitPCMP(MI, BB, 3, true /* in-mem */);
10187 case X86::PCMPESTRM128REG:
10188 case X86::VPCMPESTRM128REG:
10189 return EmitPCMP(MI, BB, 5, false /* in mem */);
10190 case X86::PCMPESTRM128MEM:
10191 case X86::VPCMPESTRM128MEM:
10192 return EmitPCMP(MI, BB, 5, true /* in mem */);
10194 // Thread synchronization.
10196 return EmitMonitor(MI, BB);
10198 return EmitMwait(MI, BB);
10200 // Atomic Lowering.
10201 case X86::ATOMAND32:
10202 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10203 X86::AND32ri, X86::MOV32rm,
10205 X86::NOT32r, X86::EAX,
10206 X86::GR32RegisterClass);
10207 case X86::ATOMOR32:
10208 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
10209 X86::OR32ri, X86::MOV32rm,
10211 X86::NOT32r, X86::EAX,
10212 X86::GR32RegisterClass);
10213 case X86::ATOMXOR32:
10214 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
10215 X86::XOR32ri, X86::MOV32rm,
10217 X86::NOT32r, X86::EAX,
10218 X86::GR32RegisterClass);
10219 case X86::ATOMNAND32:
10220 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10221 X86::AND32ri, X86::MOV32rm,
10223 X86::NOT32r, X86::EAX,
10224 X86::GR32RegisterClass, true);
10225 case X86::ATOMMIN32:
10226 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
10227 case X86::ATOMMAX32:
10228 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
10229 case X86::ATOMUMIN32:
10230 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
10231 case X86::ATOMUMAX32:
10232 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
10234 case X86::ATOMAND16:
10235 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10236 X86::AND16ri, X86::MOV16rm,
10238 X86::NOT16r, X86::AX,
10239 X86::GR16RegisterClass);
10240 case X86::ATOMOR16:
10241 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
10242 X86::OR16ri, X86::MOV16rm,
10244 X86::NOT16r, X86::AX,
10245 X86::GR16RegisterClass);
10246 case X86::ATOMXOR16:
10247 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
10248 X86::XOR16ri, X86::MOV16rm,
10250 X86::NOT16r, X86::AX,
10251 X86::GR16RegisterClass);
10252 case X86::ATOMNAND16:
10253 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10254 X86::AND16ri, X86::MOV16rm,
10256 X86::NOT16r, X86::AX,
10257 X86::GR16RegisterClass, true);
10258 case X86::ATOMMIN16:
10259 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
10260 case X86::ATOMMAX16:
10261 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
10262 case X86::ATOMUMIN16:
10263 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
10264 case X86::ATOMUMAX16:
10265 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
10267 case X86::ATOMAND8:
10268 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10269 X86::AND8ri, X86::MOV8rm,
10271 X86::NOT8r, X86::AL,
10272 X86::GR8RegisterClass);
10274 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
10275 X86::OR8ri, X86::MOV8rm,
10277 X86::NOT8r, X86::AL,
10278 X86::GR8RegisterClass);
10279 case X86::ATOMXOR8:
10280 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
10281 X86::XOR8ri, X86::MOV8rm,
10283 X86::NOT8r, X86::AL,
10284 X86::GR8RegisterClass);
10285 case X86::ATOMNAND8:
10286 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10287 X86::AND8ri, X86::MOV8rm,
10289 X86::NOT8r, X86::AL,
10290 X86::GR8RegisterClass, true);
10291 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
10292 // This group is for 64-bit host.
10293 case X86::ATOMAND64:
10294 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10295 X86::AND64ri32, X86::MOV64rm,
10297 X86::NOT64r, X86::RAX,
10298 X86::GR64RegisterClass);
10299 case X86::ATOMOR64:
10300 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
10301 X86::OR64ri32, X86::MOV64rm,
10303 X86::NOT64r, X86::RAX,
10304 X86::GR64RegisterClass);
10305 case X86::ATOMXOR64:
10306 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
10307 X86::XOR64ri32, X86::MOV64rm,
10309 X86::NOT64r, X86::RAX,
10310 X86::GR64RegisterClass);
10311 case X86::ATOMNAND64:
10312 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10313 X86::AND64ri32, X86::MOV64rm,
10315 X86::NOT64r, X86::RAX,
10316 X86::GR64RegisterClass, true);
10317 case X86::ATOMMIN64:
10318 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
10319 case X86::ATOMMAX64:
10320 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
10321 case X86::ATOMUMIN64:
10322 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
10323 case X86::ATOMUMAX64:
10324 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
10326 // This group does 64-bit operations on a 32-bit host.
10327 case X86::ATOMAND6432:
10328 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10329 X86::AND32rr, X86::AND32rr,
10330 X86::AND32ri, X86::AND32ri,
10332 case X86::ATOMOR6432:
10333 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10334 X86::OR32rr, X86::OR32rr,
10335 X86::OR32ri, X86::OR32ri,
10337 case X86::ATOMXOR6432:
10338 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10339 X86::XOR32rr, X86::XOR32rr,
10340 X86::XOR32ri, X86::XOR32ri,
10342 case X86::ATOMNAND6432:
10343 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10344 X86::AND32rr, X86::AND32rr,
10345 X86::AND32ri, X86::AND32ri,
10347 case X86::ATOMADD6432:
10348 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10349 X86::ADD32rr, X86::ADC32rr,
10350 X86::ADD32ri, X86::ADC32ri,
10352 case X86::ATOMSUB6432:
10353 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10354 X86::SUB32rr, X86::SBB32rr,
10355 X86::SUB32ri, X86::SBB32ri,
10357 case X86::ATOMSWAP6432:
10358 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10359 X86::MOV32rr, X86::MOV32rr,
10360 X86::MOV32ri, X86::MOV32ri,
10362 case X86::VASTART_SAVE_XMM_REGS:
10363 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
10365 case X86::VAARG_64:
10366 return EmitVAARG64WithCustomInserter(MI, BB);
10370 //===----------------------------------------------------------------------===//
10371 // X86 Optimization Hooks
10372 //===----------------------------------------------------------------------===//
10374 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10378 const SelectionDAG &DAG,
10379 unsigned Depth) const {
10380 unsigned Opc = Op.getOpcode();
10381 assert((Opc >= ISD::BUILTIN_OP_END ||
10382 Opc == ISD::INTRINSIC_WO_CHAIN ||
10383 Opc == ISD::INTRINSIC_W_CHAIN ||
10384 Opc == ISD::INTRINSIC_VOID) &&
10385 "Should use MaskedValueIsZero if you don't know whether Op"
10386 " is a target node!");
10388 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
10402 // These nodes' second result is a boolean.
10403 if (Op.getResNo() == 0)
10406 case X86ISD::SETCC:
10407 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
10408 Mask.getBitWidth() - 1);
10413 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
10414 unsigned Depth) const {
10415 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
10416 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
10417 return Op.getValueType().getScalarType().getSizeInBits();
10423 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
10424 /// node is a GlobalAddress + offset.
10425 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
10426 const GlobalValue* &GA,
10427 int64_t &Offset) const {
10428 if (N->getOpcode() == X86ISD::Wrapper) {
10429 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
10430 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
10431 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
10435 return TargetLowering::isGAPlusOffset(N, GA, Offset);
10438 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
10439 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
10440 /// if the load addresses are consecutive, non-overlapping, and in the right
10442 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
10443 TargetLowering::DAGCombinerInfo &DCI) {
10444 DebugLoc dl = N->getDebugLoc();
10445 EVT VT = N->getValueType(0);
10447 if (VT.getSizeInBits() != 128)
10450 // Don't create instructions with illegal types after legalize types has run.
10451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10452 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
10455 SmallVector<SDValue, 16> Elts;
10456 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
10457 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
10459 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
10462 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
10463 /// generation and convert it from being a bunch of shuffles and extracts
10464 /// to a simple store and scalar loads to extract the elements.
10465 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
10466 const TargetLowering &TLI) {
10467 SDValue InputVector = N->getOperand(0);
10469 // Only operate on vectors of 4 elements, where the alternative shuffling
10470 // gets to be more expensive.
10471 if (InputVector.getValueType() != MVT::v4i32)
10474 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
10475 // single use which is a sign-extend or zero-extend, and all elements are
10477 SmallVector<SDNode *, 4> Uses;
10478 unsigned ExtractedElements = 0;
10479 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
10480 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
10481 if (UI.getUse().getResNo() != InputVector.getResNo())
10484 SDNode *Extract = *UI;
10485 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10488 if (Extract->getValueType(0) != MVT::i32)
10490 if (!Extract->hasOneUse())
10492 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
10493 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
10495 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
10498 // Record which element was extracted.
10499 ExtractedElements |=
10500 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
10502 Uses.push_back(Extract);
10505 // If not all the elements were used, this may not be worthwhile.
10506 if (ExtractedElements != 15)
10509 // Ok, we've now decided to do the transformation.
10510 DebugLoc dl = InputVector.getDebugLoc();
10512 // Store the value to a temporary stack slot.
10513 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
10514 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
10515 MachinePointerInfo(), false, false, 0);
10517 // Replace each use (extract) with a load of the appropriate element.
10518 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
10519 UE = Uses.end(); UI != UE; ++UI) {
10520 SDNode *Extract = *UI;
10522 // Compute the element's address.
10523 SDValue Idx = Extract->getOperand(1);
10525 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
10526 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
10527 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
10529 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
10530 StackPtr, OffsetVal);
10532 // Load the scalar.
10533 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
10534 ScalarAddr, MachinePointerInfo(),
10537 // Replace the exact with the load.
10538 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
10541 // The replacement was made in place; don't return anything.
10545 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
10546 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
10547 const X86Subtarget *Subtarget) {
10548 DebugLoc DL = N->getDebugLoc();
10549 SDValue Cond = N->getOperand(0);
10550 // Get the LHS/RHS of the select.
10551 SDValue LHS = N->getOperand(1);
10552 SDValue RHS = N->getOperand(2);
10554 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
10555 // instructions match the semantics of the common C idiom x<y?x:y but not
10556 // x<=y?x:y, because of how they handle negative zero (which can be
10557 // ignored in unsafe-math mode).
10558 if (Subtarget->hasSSE2() &&
10559 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
10560 Cond.getOpcode() == ISD::SETCC) {
10561 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
10563 unsigned Opcode = 0;
10564 // Check for x CC y ? x : y.
10565 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
10566 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
10570 // Converting this to a min would handle NaNs incorrectly, and swapping
10571 // the operands would cause it to handle comparisons between positive
10572 // and negative zero incorrectly.
10573 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10574 if (!UnsafeFPMath &&
10575 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10577 std::swap(LHS, RHS);
10579 Opcode = X86ISD::FMIN;
10582 // Converting this to a min would handle comparisons between positive
10583 // and negative zero incorrectly.
10584 if (!UnsafeFPMath &&
10585 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
10587 Opcode = X86ISD::FMIN;
10590 // Converting this to a min would handle both negative zeros and NaNs
10591 // incorrectly, but we can swap the operands to fix both.
10592 std::swap(LHS, RHS);
10596 Opcode = X86ISD::FMIN;
10600 // Converting this to a max would handle comparisons between positive
10601 // and negative zero incorrectly.
10602 if (!UnsafeFPMath &&
10603 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
10605 Opcode = X86ISD::FMAX;
10608 // Converting this to a max would handle NaNs incorrectly, and swapping
10609 // the operands would cause it to handle comparisons between positive
10610 // and negative zero incorrectly.
10611 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10612 if (!UnsafeFPMath &&
10613 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10615 std::swap(LHS, RHS);
10617 Opcode = X86ISD::FMAX;
10620 // Converting this to a max would handle both negative zeros and NaNs
10621 // incorrectly, but we can swap the operands to fix both.
10622 std::swap(LHS, RHS);
10626 Opcode = X86ISD::FMAX;
10629 // Check for x CC y ? y : x -- a min/max with reversed arms.
10630 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10631 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10635 // Converting this to a min would handle comparisons between positive
10636 // and negative zero incorrectly, and swapping the operands would
10637 // cause it to handle NaNs incorrectly.
10638 if (!UnsafeFPMath &&
10639 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10640 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10642 std::swap(LHS, RHS);
10644 Opcode = X86ISD::FMIN;
10647 // Converting this to a min would handle NaNs incorrectly.
10648 if (!UnsafeFPMath &&
10649 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10651 Opcode = X86ISD::FMIN;
10654 // Converting this to a min would handle both negative zeros and NaNs
10655 // incorrectly, but we can swap the operands to fix both.
10656 std::swap(LHS, RHS);
10660 Opcode = X86ISD::FMIN;
10664 // Converting this to a max would handle NaNs incorrectly.
10665 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10667 Opcode = X86ISD::FMAX;
10670 // Converting this to a max would handle comparisons between positive
10671 // and negative zero incorrectly, and swapping the operands would
10672 // cause it to handle NaNs incorrectly.
10673 if (!UnsafeFPMath &&
10674 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10675 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10677 std::swap(LHS, RHS);
10679 Opcode = X86ISD::FMAX;
10682 // Converting this to a max would handle both negative zeros and NaNs
10683 // incorrectly, but we can swap the operands to fix both.
10684 std::swap(LHS, RHS);
10688 Opcode = X86ISD::FMAX;
10694 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10697 // If this is a select between two integer constants, try to do some
10699 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10700 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10701 // Don't do this for crazy integer types.
10702 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10703 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10704 // so that TrueC (the true value) is larger than FalseC.
10705 bool NeedsCondInvert = false;
10707 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10708 // Efficiently invertible.
10709 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10710 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10711 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10712 NeedsCondInvert = true;
10713 std::swap(TrueC, FalseC);
10716 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10717 if (FalseC->getAPIntValue() == 0 &&
10718 TrueC->getAPIntValue().isPowerOf2()) {
10719 if (NeedsCondInvert) // Invert the condition if needed.
10720 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10721 DAG.getConstant(1, Cond.getValueType()));
10723 // Zero extend the condition if needed.
10724 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10726 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10727 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10728 DAG.getConstant(ShAmt, MVT::i8));
10731 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10732 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10733 if (NeedsCondInvert) // Invert the condition if needed.
10734 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10735 DAG.getConstant(1, Cond.getValueType()));
10737 // Zero extend the condition if needed.
10738 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10739 FalseC->getValueType(0), Cond);
10740 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10741 SDValue(FalseC, 0));
10744 // Optimize cases that will turn into an LEA instruction. This requires
10745 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10746 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10747 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10748 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10750 bool isFastMultiplier = false;
10752 switch ((unsigned char)Diff) {
10754 case 1: // result = add base, cond
10755 case 2: // result = lea base( , cond*2)
10756 case 3: // result = lea base(cond, cond*2)
10757 case 4: // result = lea base( , cond*4)
10758 case 5: // result = lea base(cond, cond*4)
10759 case 8: // result = lea base( , cond*8)
10760 case 9: // result = lea base(cond, cond*8)
10761 isFastMultiplier = true;
10766 if (isFastMultiplier) {
10767 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10768 if (NeedsCondInvert) // Invert the condition if needed.
10769 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10770 DAG.getConstant(1, Cond.getValueType()));
10772 // Zero extend the condition if needed.
10773 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10775 // Scale the condition by the difference.
10777 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10778 DAG.getConstant(Diff, Cond.getValueType()));
10780 // Add the base if non-zero.
10781 if (FalseC->getAPIntValue() != 0)
10782 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10783 SDValue(FalseC, 0));
10793 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10794 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10795 TargetLowering::DAGCombinerInfo &DCI) {
10796 DebugLoc DL = N->getDebugLoc();
10798 // If the flag operand isn't dead, don't touch this CMOV.
10799 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10802 // If this is a select between two integer constants, try to do some
10803 // optimizations. Note that the operands are ordered the opposite of SELECT
10805 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10806 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10807 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10808 // larger than FalseC (the false value).
10809 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10811 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10812 CC = X86::GetOppositeBranchCondition(CC);
10813 std::swap(TrueC, FalseC);
10816 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10817 // This is efficient for any integer data type (including i8/i16) and
10819 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10820 SDValue Cond = N->getOperand(3);
10821 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10822 DAG.getConstant(CC, MVT::i8), Cond);
10824 // Zero extend the condition if needed.
10825 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10827 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10828 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10829 DAG.getConstant(ShAmt, MVT::i8));
10830 if (N->getNumValues() == 2) // Dead flag value?
10831 return DCI.CombineTo(N, Cond, SDValue());
10835 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10836 // for any integer data type, including i8/i16.
10837 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10838 SDValue Cond = N->getOperand(3);
10839 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10840 DAG.getConstant(CC, MVT::i8), Cond);
10842 // Zero extend the condition if needed.
10843 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10844 FalseC->getValueType(0), Cond);
10845 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10846 SDValue(FalseC, 0));
10848 if (N->getNumValues() == 2) // Dead flag value?
10849 return DCI.CombineTo(N, Cond, SDValue());
10853 // Optimize cases that will turn into an LEA instruction. This requires
10854 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10855 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10856 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10857 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10859 bool isFastMultiplier = false;
10861 switch ((unsigned char)Diff) {
10863 case 1: // result = add base, cond
10864 case 2: // result = lea base( , cond*2)
10865 case 3: // result = lea base(cond, cond*2)
10866 case 4: // result = lea base( , cond*4)
10867 case 5: // result = lea base(cond, cond*4)
10868 case 8: // result = lea base( , cond*8)
10869 case 9: // result = lea base(cond, cond*8)
10870 isFastMultiplier = true;
10875 if (isFastMultiplier) {
10876 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10877 SDValue Cond = N->getOperand(3);
10878 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10879 DAG.getConstant(CC, MVT::i8), Cond);
10880 // Zero extend the condition if needed.
10881 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10883 // Scale the condition by the difference.
10885 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10886 DAG.getConstant(Diff, Cond.getValueType()));
10888 // Add the base if non-zero.
10889 if (FalseC->getAPIntValue() != 0)
10890 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10891 SDValue(FalseC, 0));
10892 if (N->getNumValues() == 2) // Dead flag value?
10893 return DCI.CombineTo(N, Cond, SDValue());
10903 /// PerformMulCombine - Optimize a single multiply with constant into two
10904 /// in order to implement it with two cheaper instructions, e.g.
10905 /// LEA + SHL, LEA + LEA.
10906 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10907 TargetLowering::DAGCombinerInfo &DCI) {
10908 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10911 EVT VT = N->getValueType(0);
10912 if (VT != MVT::i64)
10915 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10918 uint64_t MulAmt = C->getZExtValue();
10919 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10922 uint64_t MulAmt1 = 0;
10923 uint64_t MulAmt2 = 0;
10924 if ((MulAmt % 9) == 0) {
10926 MulAmt2 = MulAmt / 9;
10927 } else if ((MulAmt % 5) == 0) {
10929 MulAmt2 = MulAmt / 5;
10930 } else if ((MulAmt % 3) == 0) {
10932 MulAmt2 = MulAmt / 3;
10935 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10936 DebugLoc DL = N->getDebugLoc();
10938 if (isPowerOf2_64(MulAmt2) &&
10939 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10940 // If second multiplifer is pow2, issue it first. We want the multiply by
10941 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10943 std::swap(MulAmt1, MulAmt2);
10946 if (isPowerOf2_64(MulAmt1))
10947 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10948 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10950 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10951 DAG.getConstant(MulAmt1, VT));
10953 if (isPowerOf2_64(MulAmt2))
10954 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10955 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10957 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10958 DAG.getConstant(MulAmt2, VT));
10960 // Do not add new nodes to DAG combiner worklist.
10961 DCI.CombineTo(N, NewMul, false);
10966 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10967 SDValue N0 = N->getOperand(0);
10968 SDValue N1 = N->getOperand(1);
10969 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10970 EVT VT = N0.getValueType();
10972 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10973 // since the result of setcc_c is all zero's or all ones.
10974 if (N1C && N0.getOpcode() == ISD::AND &&
10975 N0.getOperand(1).getOpcode() == ISD::Constant) {
10976 SDValue N00 = N0.getOperand(0);
10977 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10978 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10979 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10980 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10981 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10982 APInt ShAmt = N1C->getAPIntValue();
10983 Mask = Mask.shl(ShAmt);
10985 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10986 N00, DAG.getConstant(Mask, VT));
10993 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10995 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10996 const X86Subtarget *Subtarget) {
10997 EVT VT = N->getValueType(0);
10998 if (!VT.isVector() && VT.isInteger() &&
10999 N->getOpcode() == ISD::SHL)
11000 return PerformSHLCombine(N, DAG);
11002 // On X86 with SSE2 support, we can transform this to a vector shift if
11003 // all elements are shifted by the same amount. We can't do this in legalize
11004 // because the a constant vector is typically transformed to a constant pool
11005 // so we have no knowledge of the shift amount.
11006 if (!Subtarget->hasSSE2())
11009 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
11012 SDValue ShAmtOp = N->getOperand(1);
11013 EVT EltVT = VT.getVectorElementType();
11014 DebugLoc DL = N->getDebugLoc();
11015 SDValue BaseShAmt = SDValue();
11016 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
11017 unsigned NumElts = VT.getVectorNumElements();
11019 for (; i != NumElts; ++i) {
11020 SDValue Arg = ShAmtOp.getOperand(i);
11021 if (Arg.getOpcode() == ISD::UNDEF) continue;
11025 for (; i != NumElts; ++i) {
11026 SDValue Arg = ShAmtOp.getOperand(i);
11027 if (Arg.getOpcode() == ISD::UNDEF) continue;
11028 if (Arg != BaseShAmt) {
11032 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
11033 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
11034 SDValue InVec = ShAmtOp.getOperand(0);
11035 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
11036 unsigned NumElts = InVec.getValueType().getVectorNumElements();
11038 for (; i != NumElts; ++i) {
11039 SDValue Arg = InVec.getOperand(i);
11040 if (Arg.getOpcode() == ISD::UNDEF) continue;
11044 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
11045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
11046 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
11047 if (C->getZExtValue() == SplatIdx)
11048 BaseShAmt = InVec.getOperand(1);
11051 if (BaseShAmt.getNode() == 0)
11052 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
11053 DAG.getIntPtrConstant(0));
11057 // The shift amount is an i32.
11058 if (EltVT.bitsGT(MVT::i32))
11059 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
11060 else if (EltVT.bitsLT(MVT::i32))
11061 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
11063 // The shift amount is identical so we can do a vector shift.
11064 SDValue ValOp = N->getOperand(0);
11065 switch (N->getOpcode()) {
11067 llvm_unreachable("Unknown shift opcode!");
11070 if (VT == MVT::v2i64)
11071 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11072 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
11074 if (VT == MVT::v4i32)
11075 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11076 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
11078 if (VT == MVT::v8i16)
11079 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11080 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
11084 if (VT == MVT::v4i32)
11085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11086 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
11088 if (VT == MVT::v8i16)
11089 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11090 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
11094 if (VT == MVT::v2i64)
11095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11096 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
11098 if (VT == MVT::v4i32)
11099 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11100 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
11102 if (VT == MVT::v8i16)
11103 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11104 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
11112 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
11113 TargetLowering::DAGCombinerInfo &DCI,
11114 const X86Subtarget *Subtarget) {
11115 if (DCI.isBeforeLegalizeOps())
11118 // Want to form PANDN nodes, in the hopes of then easily combining them with
11119 // OR and AND nodes to form PBLEND/PSIGN.
11120 EVT VT = N->getValueType(0);
11121 if (VT != MVT::v2i64)
11124 SDValue N0 = N->getOperand(0);
11125 SDValue N1 = N->getOperand(1);
11126 DebugLoc DL = N->getDebugLoc();
11128 // Check LHS for vnot
11129 if (N0.getOpcode() == ISD::XOR &&
11130 ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
11131 return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1);
11133 // Check RHS for vnot
11134 if (N1.getOpcode() == ISD::XOR &&
11135 ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
11136 return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0);
11141 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
11142 TargetLowering::DAGCombinerInfo &DCI,
11143 const X86Subtarget *Subtarget) {
11144 if (DCI.isBeforeLegalizeOps())
11147 EVT VT = N->getValueType(0);
11148 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
11151 SDValue N0 = N->getOperand(0);
11152 SDValue N1 = N->getOperand(1);
11154 // look for psign/blend
11155 if (Subtarget->hasSSSE3()) {
11156 if (VT == MVT::v2i64) {
11157 // Canonicalize pandn to RHS
11158 if (N0.getOpcode() == X86ISD::PANDN)
11160 // or (and (m, x), (pandn m, y))
11161 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::PANDN) {
11162 SDValue Mask = N1.getOperand(0);
11163 SDValue X = N1.getOperand(1);
11165 if (N0.getOperand(0) == Mask)
11166 Y = N0.getOperand(1);
11167 if (N0.getOperand(1) == Mask)
11168 Y = N0.getOperand(0);
11170 // Check to see if the mask appeared in both the AND and PANDN and
11174 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
11175 if (Mask.getOpcode() != ISD::BITCAST ||
11176 X.getOpcode() != ISD::BITCAST ||
11177 Y.getOpcode() != ISD::BITCAST)
11180 // Look through mask bitcast.
11181 Mask = Mask.getOperand(0);
11182 EVT MaskVT = Mask.getValueType();
11184 // Validate that the Mask operand is a vector sra node. The sra node
11185 // will be an intrinsic.
11186 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
11189 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
11190 // there is no psrai.b
11191 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
11192 case Intrinsic::x86_sse2_psrai_w:
11193 case Intrinsic::x86_sse2_psrai_d:
11195 default: return SDValue();
11198 // Check that the SRA is all signbits.
11199 SDValue SraC = Mask.getOperand(2);
11200 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
11201 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
11202 if ((SraAmt + 1) != EltBits)
11205 DebugLoc DL = N->getDebugLoc();
11207 // Now we know we at least have a plendvb with the mask val. See if
11208 // we can form a psignb/w/d.
11209 // psign = x.type == y.type == mask.type && y = sub(0, x);
11210 X = X.getOperand(0);
11211 Y = Y.getOperand(0);
11212 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
11213 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
11214 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
11217 case 8: Opc = X86ISD::PSIGNB; break;
11218 case 16: Opc = X86ISD::PSIGNW; break;
11219 case 32: Opc = X86ISD::PSIGND; break;
11223 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
11224 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
11227 // PBLENDVB only available on SSE 4.1
11228 if (!Subtarget->hasSSE41())
11231 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
11232 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
11233 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
11234 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
11235 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
11240 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
11241 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
11243 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
11245 if (!N0.hasOneUse() || !N1.hasOneUse())
11248 SDValue ShAmt0 = N0.getOperand(1);
11249 if (ShAmt0.getValueType() != MVT::i8)
11251 SDValue ShAmt1 = N1.getOperand(1);
11252 if (ShAmt1.getValueType() != MVT::i8)
11254 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
11255 ShAmt0 = ShAmt0.getOperand(0);
11256 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
11257 ShAmt1 = ShAmt1.getOperand(0);
11259 DebugLoc DL = N->getDebugLoc();
11260 unsigned Opc = X86ISD::SHLD;
11261 SDValue Op0 = N0.getOperand(0);
11262 SDValue Op1 = N1.getOperand(0);
11263 if (ShAmt0.getOpcode() == ISD::SUB) {
11264 Opc = X86ISD::SHRD;
11265 std::swap(Op0, Op1);
11266 std::swap(ShAmt0, ShAmt1);
11269 unsigned Bits = VT.getSizeInBits();
11270 if (ShAmt1.getOpcode() == ISD::SUB) {
11271 SDValue Sum = ShAmt1.getOperand(0);
11272 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
11273 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
11274 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
11275 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
11276 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
11277 return DAG.getNode(Opc, DL, VT,
11279 DAG.getNode(ISD::TRUNCATE, DL,
11282 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
11283 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
11285 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
11286 return DAG.getNode(Opc, DL, VT,
11287 N0.getOperand(0), N1.getOperand(0),
11288 DAG.getNode(ISD::TRUNCATE, DL,
11295 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
11296 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
11297 const X86Subtarget *Subtarget) {
11298 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
11299 // the FP state in cases where an emms may be missing.
11300 // A preferable solution to the general problem is to figure out the right
11301 // places to insert EMMS. This qualifies as a quick hack.
11303 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
11304 StoreSDNode *St = cast<StoreSDNode>(N);
11305 EVT VT = St->getValue().getValueType();
11306 if (VT.getSizeInBits() != 64)
11309 const Function *F = DAG.getMachineFunction().getFunction();
11310 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
11311 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
11312 && Subtarget->hasSSE2();
11313 if ((VT.isVector() ||
11314 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
11315 isa<LoadSDNode>(St->getValue()) &&
11316 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
11317 St->getChain().hasOneUse() && !St->isVolatile()) {
11318 SDNode* LdVal = St->getValue().getNode();
11319 LoadSDNode *Ld = 0;
11320 int TokenFactorIndex = -1;
11321 SmallVector<SDValue, 8> Ops;
11322 SDNode* ChainVal = St->getChain().getNode();
11323 // Must be a store of a load. We currently handle two cases: the load
11324 // is a direct child, and it's under an intervening TokenFactor. It is
11325 // possible to dig deeper under nested TokenFactors.
11326 if (ChainVal == LdVal)
11327 Ld = cast<LoadSDNode>(St->getChain());
11328 else if (St->getValue().hasOneUse() &&
11329 ChainVal->getOpcode() == ISD::TokenFactor) {
11330 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
11331 if (ChainVal->getOperand(i).getNode() == LdVal) {
11332 TokenFactorIndex = i;
11333 Ld = cast<LoadSDNode>(St->getValue());
11335 Ops.push_back(ChainVal->getOperand(i));
11339 if (!Ld || !ISD::isNormalLoad(Ld))
11342 // If this is not the MMX case, i.e. we are just turning i64 load/store
11343 // into f64 load/store, avoid the transformation if there are multiple
11344 // uses of the loaded value.
11345 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
11348 DebugLoc LdDL = Ld->getDebugLoc();
11349 DebugLoc StDL = N->getDebugLoc();
11350 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
11351 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
11353 if (Subtarget->is64Bit() || F64IsLegal) {
11354 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
11355 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
11356 Ld->getPointerInfo(), Ld->isVolatile(),
11357 Ld->isNonTemporal(), Ld->getAlignment());
11358 SDValue NewChain = NewLd.getValue(1);
11359 if (TokenFactorIndex != -1) {
11360 Ops.push_back(NewChain);
11361 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11364 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
11365 St->getPointerInfo(),
11366 St->isVolatile(), St->isNonTemporal(),
11367 St->getAlignment());
11370 // Otherwise, lower to two pairs of 32-bit loads / stores.
11371 SDValue LoAddr = Ld->getBasePtr();
11372 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
11373 DAG.getConstant(4, MVT::i32));
11375 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
11376 Ld->getPointerInfo(),
11377 Ld->isVolatile(), Ld->isNonTemporal(),
11378 Ld->getAlignment());
11379 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
11380 Ld->getPointerInfo().getWithOffset(4),
11381 Ld->isVolatile(), Ld->isNonTemporal(),
11382 MinAlign(Ld->getAlignment(), 4));
11384 SDValue NewChain = LoLd.getValue(1);
11385 if (TokenFactorIndex != -1) {
11386 Ops.push_back(LoLd);
11387 Ops.push_back(HiLd);
11388 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11392 LoAddr = St->getBasePtr();
11393 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
11394 DAG.getConstant(4, MVT::i32));
11396 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
11397 St->getPointerInfo(),
11398 St->isVolatile(), St->isNonTemporal(),
11399 St->getAlignment());
11400 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
11401 St->getPointerInfo().getWithOffset(4),
11403 St->isNonTemporal(),
11404 MinAlign(St->getAlignment(), 4));
11405 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
11410 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
11411 /// X86ISD::FXOR nodes.
11412 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
11413 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
11414 // F[X]OR(0.0, x) -> x
11415 // F[X]OR(x, 0.0) -> x
11416 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11417 if (C->getValueAPF().isPosZero())
11418 return N->getOperand(1);
11419 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11420 if (C->getValueAPF().isPosZero())
11421 return N->getOperand(0);
11425 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
11426 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
11427 // FAND(0.0, x) -> 0.0
11428 // FAND(x, 0.0) -> 0.0
11429 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11430 if (C->getValueAPF().isPosZero())
11431 return N->getOperand(0);
11432 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11433 if (C->getValueAPF().isPosZero())
11434 return N->getOperand(1);
11438 static SDValue PerformBTCombine(SDNode *N,
11440 TargetLowering::DAGCombinerInfo &DCI) {
11441 // BT ignores high bits in the bit index operand.
11442 SDValue Op1 = N->getOperand(1);
11443 if (Op1.hasOneUse()) {
11444 unsigned BitWidth = Op1.getValueSizeInBits();
11445 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
11446 APInt KnownZero, KnownOne;
11447 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
11448 !DCI.isBeforeLegalizeOps());
11449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11450 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
11451 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
11452 DCI.CommitTargetLoweringOpt(TLO);
11457 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
11458 SDValue Op = N->getOperand(0);
11459 if (Op.getOpcode() == ISD::BITCAST)
11460 Op = Op.getOperand(0);
11461 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
11462 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
11463 VT.getVectorElementType().getSizeInBits() ==
11464 OpVT.getVectorElementType().getSizeInBits()) {
11465 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
11470 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
11471 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
11472 // (and (i32 x86isd::setcc_carry), 1)
11473 // This eliminates the zext. This transformation is necessary because
11474 // ISD::SETCC is always legalized to i8.
11475 DebugLoc dl = N->getDebugLoc();
11476 SDValue N0 = N->getOperand(0);
11477 EVT VT = N->getValueType(0);
11478 if (N0.getOpcode() == ISD::AND &&
11480 N0.getOperand(0).hasOneUse()) {
11481 SDValue N00 = N0.getOperand(0);
11482 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
11484 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11485 if (!C || C->getZExtValue() != 1)
11487 return DAG.getNode(ISD::AND, dl, VT,
11488 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
11489 N00.getOperand(0), N00.getOperand(1)),
11490 DAG.getConstant(1, VT));
11496 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
11497 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
11498 unsigned X86CC = N->getConstantOperandVal(0);
11499 SDValue EFLAG = N->getOperand(1);
11500 DebugLoc DL = N->getDebugLoc();
11502 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
11503 // a zext and produces an all-ones bit which is more useful than 0/1 in some
11505 if (X86CC == X86::COND_B)
11506 return DAG.getNode(ISD::AND, DL, MVT::i8,
11507 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
11508 DAG.getConstant(X86CC, MVT::i8), EFLAG),
11509 DAG.getConstant(1, MVT::i8));
11514 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
11515 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
11516 X86TargetLowering::DAGCombinerInfo &DCI) {
11517 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
11518 // the result is either zero or one (depending on the input carry bit).
11519 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
11520 if (X86::isZeroNode(N->getOperand(0)) &&
11521 X86::isZeroNode(N->getOperand(1)) &&
11522 // We don't have a good way to replace an EFLAGS use, so only do this when
11524 SDValue(N, 1).use_empty()) {
11525 DebugLoc DL = N->getDebugLoc();
11526 EVT VT = N->getValueType(0);
11527 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
11528 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
11529 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
11530 DAG.getConstant(X86::COND_B,MVT::i8),
11532 DAG.getConstant(1, VT));
11533 return DCI.CombineTo(N, Res1, CarryOut);
11539 // fold (add Y, (sete X, 0)) -> adc 0, Y
11540 // (add Y, (setne X, 0)) -> sbb -1, Y
11541 // (sub (sete X, 0), Y) -> sbb 0, Y
11542 // (sub (setne X, 0), Y) -> adc -1, Y
11543 static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) {
11544 DebugLoc DL = N->getDebugLoc();
11546 // Look through ZExts.
11547 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
11548 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
11551 SDValue SetCC = Ext.getOperand(0);
11552 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
11555 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
11556 if (CC != X86::COND_E && CC != X86::COND_NE)
11559 SDValue Cmp = SetCC.getOperand(1);
11560 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
11561 !X86::isZeroNode(Cmp.getOperand(1)))
11564 SDValue CmpOp0 = Cmp.getOperand(0);
11565 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
11566 DAG.getConstant(1, CmpOp0.getValueType()));
11568 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
11569 if (CC == X86::COND_NE)
11570 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
11571 DL, OtherVal.getValueType(), OtherVal,
11572 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
11573 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
11574 DL, OtherVal.getValueType(), OtherVal,
11575 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
11578 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
11579 DAGCombinerInfo &DCI) const {
11580 SelectionDAG &DAG = DCI.DAG;
11581 switch (N->getOpcode()) {
11583 case ISD::EXTRACT_VECTOR_ELT:
11584 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
11585 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
11586 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
11588 case ISD::SUB: return OptimizeConditonalInDecrement(N, DAG);
11589 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
11590 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
11593 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
11594 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
11595 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
11596 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
11598 case X86ISD::FOR: return PerformFORCombine(N, DAG);
11599 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
11600 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
11601 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
11602 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
11603 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
11604 case X86ISD::SHUFPS: // Handle all target specific shuffles
11605 case X86ISD::SHUFPD:
11606 case X86ISD::PALIGN:
11607 case X86ISD::PUNPCKHBW:
11608 case X86ISD::PUNPCKHWD:
11609 case X86ISD::PUNPCKHDQ:
11610 case X86ISD::PUNPCKHQDQ:
11611 case X86ISD::UNPCKHPS:
11612 case X86ISD::UNPCKHPD:
11613 case X86ISD::PUNPCKLBW:
11614 case X86ISD::PUNPCKLWD:
11615 case X86ISD::PUNPCKLDQ:
11616 case X86ISD::PUNPCKLQDQ:
11617 case X86ISD::UNPCKLPS:
11618 case X86ISD::UNPCKLPD:
11619 case X86ISD::MOVHLPS:
11620 case X86ISD::MOVLHPS:
11621 case X86ISD::PSHUFD:
11622 case X86ISD::PSHUFHW:
11623 case X86ISD::PSHUFLW:
11624 case X86ISD::MOVSS:
11625 case X86ISD::MOVSD:
11626 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
11632 /// isTypeDesirableForOp - Return true if the target has native support for
11633 /// the specified value type and it is 'desirable' to use the type for the
11634 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
11635 /// instruction encodings are longer and some i16 instructions are slow.
11636 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
11637 if (!isTypeLegal(VT))
11639 if (VT != MVT::i16)
11646 case ISD::SIGN_EXTEND:
11647 case ISD::ZERO_EXTEND:
11648 case ISD::ANY_EXTEND:
11661 /// IsDesirableToPromoteOp - This method query the target whether it is
11662 /// beneficial for dag combiner to promote the specified node. If true, it
11663 /// should return the desired promotion type by reference.
11664 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
11665 EVT VT = Op.getValueType();
11666 if (VT != MVT::i16)
11669 bool Promote = false;
11670 bool Commute = false;
11671 switch (Op.getOpcode()) {
11674 LoadSDNode *LD = cast<LoadSDNode>(Op);
11675 // If the non-extending load has a single use and it's not live out, then it
11676 // might be folded.
11677 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
11678 Op.hasOneUse()*/) {
11679 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11680 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
11681 // The only case where we'd want to promote LOAD (rather then it being
11682 // promoted as an operand is when it's only use is liveout.
11683 if (UI->getOpcode() != ISD::CopyToReg)
11690 case ISD::SIGN_EXTEND:
11691 case ISD::ZERO_EXTEND:
11692 case ISD::ANY_EXTEND:
11697 SDValue N0 = Op.getOperand(0);
11698 // Look out for (store (shl (load), x)).
11699 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
11712 SDValue N0 = Op.getOperand(0);
11713 SDValue N1 = Op.getOperand(1);
11714 if (!Commute && MayFoldLoad(N1))
11716 // Avoid disabling potential load folding opportunities.
11717 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
11719 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
11729 //===----------------------------------------------------------------------===//
11730 // X86 Inline Assembly Support
11731 //===----------------------------------------------------------------------===//
11733 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
11734 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11736 std::string AsmStr = IA->getAsmString();
11738 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
11739 SmallVector<StringRef, 4> AsmPieces;
11740 SplitString(AsmStr, AsmPieces, ";\n");
11742 switch (AsmPieces.size()) {
11743 default: return false;
11745 AsmStr = AsmPieces[0];
11747 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
11749 // FIXME: this should verify that we are targetting a 486 or better. If not,
11750 // we will turn this bswap into something that will be lowered to logical ops
11751 // instead of emitting the bswap asm. For now, we don't support 486 or lower
11752 // so don't worry about this.
11754 if (AsmPieces.size() == 2 &&
11755 (AsmPieces[0] == "bswap" ||
11756 AsmPieces[0] == "bswapq" ||
11757 AsmPieces[0] == "bswapl") &&
11758 (AsmPieces[1] == "$0" ||
11759 AsmPieces[1] == "${0:q}")) {
11760 // No need to check constraints, nothing other than the equivalent of
11761 // "=r,0" would be valid here.
11762 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11763 if (!Ty || Ty->getBitWidth() % 16 != 0)
11765 return IntrinsicLowering::LowerToByteSwap(CI);
11767 // rorw $$8, ${0:w} --> llvm.bswap.i16
11768 if (CI->getType()->isIntegerTy(16) &&
11769 AsmPieces.size() == 3 &&
11770 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
11771 AsmPieces[1] == "$$8," &&
11772 AsmPieces[2] == "${0:w}" &&
11773 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11775 const std::string &ConstraintsStr = IA->getConstraintString();
11776 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
11777 std::sort(AsmPieces.begin(), AsmPieces.end());
11778 if (AsmPieces.size() == 4 &&
11779 AsmPieces[0] == "~{cc}" &&
11780 AsmPieces[1] == "~{dirflag}" &&
11781 AsmPieces[2] == "~{flags}" &&
11782 AsmPieces[3] == "~{fpsr}") {
11783 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11784 if (!Ty || Ty->getBitWidth() % 16 != 0)
11786 return IntrinsicLowering::LowerToByteSwap(CI);
11791 if (CI->getType()->isIntegerTy(32) &&
11792 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11793 SmallVector<StringRef, 4> Words;
11794 SplitString(AsmPieces[0], Words, " \t,");
11795 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11796 Words[2] == "${0:w}") {
11798 SplitString(AsmPieces[1], Words, " \t,");
11799 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
11800 Words[2] == "$0") {
11802 SplitString(AsmPieces[2], Words, " \t,");
11803 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11804 Words[2] == "${0:w}") {
11806 const std::string &ConstraintsStr = IA->getConstraintString();
11807 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
11808 std::sort(AsmPieces.begin(), AsmPieces.end());
11809 if (AsmPieces.size() == 4 &&
11810 AsmPieces[0] == "~{cc}" &&
11811 AsmPieces[1] == "~{dirflag}" &&
11812 AsmPieces[2] == "~{flags}" &&
11813 AsmPieces[3] == "~{fpsr}") {
11814 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11815 if (!Ty || Ty->getBitWidth() % 16 != 0)
11817 return IntrinsicLowering::LowerToByteSwap(CI);
11824 if (CI->getType()->isIntegerTy(64)) {
11825 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
11826 if (Constraints.size() >= 2 &&
11827 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11828 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11829 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11830 SmallVector<StringRef, 4> Words;
11831 SplitString(AsmPieces[0], Words, " \t");
11832 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11834 SplitString(AsmPieces[1], Words, " \t");
11835 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11837 SplitString(AsmPieces[2], Words, " \t,");
11838 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11839 Words[2] == "%edx") {
11840 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11841 if (!Ty || Ty->getBitWidth() % 16 != 0)
11843 return IntrinsicLowering::LowerToByteSwap(CI);
11856 /// getConstraintType - Given a constraint letter, return the type of
11857 /// constraint it is for this target.
11858 X86TargetLowering::ConstraintType
11859 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11860 if (Constraint.size() == 1) {
11861 switch (Constraint[0]) {
11871 return C_RegisterClass;
11895 return TargetLowering::getConstraintType(Constraint);
11898 /// Examine constraint type and operand type and determine a weight value.
11899 /// This object must already have been set up with the operand type
11900 /// and the current alternative constraint selected.
11901 TargetLowering::ConstraintWeight
11902 X86TargetLowering::getSingleConstraintMatchWeight(
11903 AsmOperandInfo &info, const char *constraint) const {
11904 ConstraintWeight weight = CW_Invalid;
11905 Value *CallOperandVal = info.CallOperandVal;
11906 // If we don't have a value, we can't do a match,
11907 // but allow it at the lowest weight.
11908 if (CallOperandVal == NULL)
11910 const Type *type = CallOperandVal->getType();
11911 // Look at the constraint type.
11912 switch (*constraint) {
11914 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11925 if (CallOperandVal->getType()->isIntegerTy())
11926 weight = CW_SpecificReg;
11931 if (type->isFloatingPointTy())
11932 weight = CW_SpecificReg;
11935 if (type->isX86_MMXTy() && Subtarget->hasMMX())
11936 weight = CW_SpecificReg;
11940 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
11941 weight = CW_Register;
11944 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
11945 if (C->getZExtValue() <= 31)
11946 weight = CW_Constant;
11950 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11951 if (C->getZExtValue() <= 63)
11952 weight = CW_Constant;
11956 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11957 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
11958 weight = CW_Constant;
11962 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11963 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
11964 weight = CW_Constant;
11968 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11969 if (C->getZExtValue() <= 3)
11970 weight = CW_Constant;
11974 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11975 if (C->getZExtValue() <= 0xff)
11976 weight = CW_Constant;
11981 if (dyn_cast<ConstantFP>(CallOperandVal)) {
11982 weight = CW_Constant;
11986 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11987 if ((C->getSExtValue() >= -0x80000000LL) &&
11988 (C->getSExtValue() <= 0x7fffffffLL))
11989 weight = CW_Constant;
11993 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11994 if (C->getZExtValue() <= 0xffffffff)
11995 weight = CW_Constant;
12002 /// LowerXConstraint - try to replace an X constraint, which matches anything,
12003 /// with another that has more specific requirements based on the type of the
12004 /// corresponding operand.
12005 const char *X86TargetLowering::
12006 LowerXConstraint(EVT ConstraintVT) const {
12007 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
12008 // 'f' like normal targets.
12009 if (ConstraintVT.isFloatingPoint()) {
12010 if (Subtarget->hasXMMInt())
12012 if (Subtarget->hasXMM())
12016 return TargetLowering::LowerXConstraint(ConstraintVT);
12019 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
12020 /// vector. If it is invalid, don't add anything to Ops.
12021 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
12023 std::vector<SDValue>&Ops,
12024 SelectionDAG &DAG) const {
12025 SDValue Result(0, 0);
12027 switch (Constraint) {
12030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12031 if (C->getZExtValue() <= 31) {
12032 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12038 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12039 if (C->getZExtValue() <= 63) {
12040 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12047 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
12048 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12054 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12055 if (C->getZExtValue() <= 255) {
12056 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12062 // 32-bit signed value
12063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12064 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12065 C->getSExtValue())) {
12066 // Widen to 64 bits here to get it sign extended.
12067 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
12070 // FIXME gcc accepts some relocatable values here too, but only in certain
12071 // memory models; it's complicated.
12076 // 32-bit unsigned value
12077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12078 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12079 C->getZExtValue())) {
12080 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12084 // FIXME gcc accepts some relocatable values here too, but only in certain
12085 // memory models; it's complicated.
12089 // Literal immediates are always ok.
12090 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
12091 // Widen to 64 bits here to get it sign extended.
12092 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
12096 // In any sort of PIC mode addresses need to be computed at runtime by
12097 // adding in a register or some sort of table lookup. These can't
12098 // be used as immediates.
12099 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
12102 // If we are in non-pic codegen mode, we allow the address of a global (with
12103 // an optional displacement) to be used with 'i'.
12104 GlobalAddressSDNode *GA = 0;
12105 int64_t Offset = 0;
12107 // Match either (GA), (GA+C), (GA+C1+C2), etc.
12109 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
12110 Offset += GA->getOffset();
12112 } else if (Op.getOpcode() == ISD::ADD) {
12113 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12114 Offset += C->getZExtValue();
12115 Op = Op.getOperand(0);
12118 } else if (Op.getOpcode() == ISD::SUB) {
12119 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12120 Offset += -C->getZExtValue();
12121 Op = Op.getOperand(0);
12126 // Otherwise, this isn't something we can handle, reject it.
12130 const GlobalValue *GV = GA->getGlobal();
12131 // If we require an extra load to get this address, as in PIC mode, we
12132 // can't accept it.
12133 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
12134 getTargetMachine())))
12137 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
12138 GA->getValueType(0), Offset);
12143 if (Result.getNode()) {
12144 Ops.push_back(Result);
12147 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
12150 std::vector<unsigned> X86TargetLowering::
12151 getRegClassForInlineAsmConstraint(const std::string &Constraint,
12153 if (Constraint.size() == 1) {
12154 // FIXME: not handling fp-stack yet!
12155 switch (Constraint[0]) { // GCC X86 Constraint Letters
12156 default: break; // Unknown constraint letter
12157 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
12158 if (Subtarget->is64Bit()) {
12159 if (VT == MVT::i32)
12160 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
12161 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
12162 X86::R10D,X86::R11D,X86::R12D,
12163 X86::R13D,X86::R14D,X86::R15D,
12164 X86::EBP, X86::ESP, 0);
12165 else if (VT == MVT::i16)
12166 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
12167 X86::SI, X86::DI, X86::R8W,X86::R9W,
12168 X86::R10W,X86::R11W,X86::R12W,
12169 X86::R13W,X86::R14W,X86::R15W,
12170 X86::BP, X86::SP, 0);
12171 else if (VT == MVT::i8)
12172 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
12173 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
12174 X86::R10B,X86::R11B,X86::R12B,
12175 X86::R13B,X86::R14B,X86::R15B,
12176 X86::BPL, X86::SPL, 0);
12178 else if (VT == MVT::i64)
12179 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
12180 X86::RSI, X86::RDI, X86::R8, X86::R9,
12181 X86::R10, X86::R11, X86::R12,
12182 X86::R13, X86::R14, X86::R15,
12183 X86::RBP, X86::RSP, 0);
12187 // 32-bit fallthrough
12188 case 'Q': // Q_REGS
12189 if (VT == MVT::i32)
12190 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
12191 else if (VT == MVT::i16)
12192 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
12193 else if (VT == MVT::i8)
12194 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
12195 else if (VT == MVT::i64)
12196 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
12201 return std::vector<unsigned>();
12204 std::pair<unsigned, const TargetRegisterClass*>
12205 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
12207 // First, see if this is a constraint that directly corresponds to an LLVM
12209 if (Constraint.size() == 1) {
12210 // GCC Constraint Letters
12211 switch (Constraint[0]) {
12213 case 'r': // GENERAL_REGS
12214 case 'l': // INDEX_REGS
12216 return std::make_pair(0U, X86::GR8RegisterClass);
12217 if (VT == MVT::i16)
12218 return std::make_pair(0U, X86::GR16RegisterClass);
12219 if (VT == MVT::i32 || !Subtarget->is64Bit())
12220 return std::make_pair(0U, X86::GR32RegisterClass);
12221 return std::make_pair(0U, X86::GR64RegisterClass);
12222 case 'R': // LEGACY_REGS
12224 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
12225 if (VT == MVT::i16)
12226 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
12227 if (VT == MVT::i32 || !Subtarget->is64Bit())
12228 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
12229 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
12230 case 'f': // FP Stack registers.
12231 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
12232 // value to the correct fpstack register class.
12233 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
12234 return std::make_pair(0U, X86::RFP32RegisterClass);
12235 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
12236 return std::make_pair(0U, X86::RFP64RegisterClass);
12237 return std::make_pair(0U, X86::RFP80RegisterClass);
12238 case 'y': // MMX_REGS if MMX allowed.
12239 if (!Subtarget->hasMMX()) break;
12240 return std::make_pair(0U, X86::VR64RegisterClass);
12241 case 'Y': // SSE_REGS if SSE2 allowed
12242 if (!Subtarget->hasXMMInt()) break;
12244 case 'x': // SSE_REGS if SSE1 allowed
12245 if (!Subtarget->hasXMM()) break;
12247 switch (VT.getSimpleVT().SimpleTy) {
12249 // Scalar SSE types.
12252 return std::make_pair(0U, X86::FR32RegisterClass);
12255 return std::make_pair(0U, X86::FR64RegisterClass);
12263 return std::make_pair(0U, X86::VR128RegisterClass);
12269 // Use the default implementation in TargetLowering to convert the register
12270 // constraint into a member of a register class.
12271 std::pair<unsigned, const TargetRegisterClass*> Res;
12272 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
12274 // Not found as a standard register?
12275 if (Res.second == 0) {
12276 // Map st(0) -> st(7) -> ST0
12277 if (Constraint.size() == 7 && Constraint[0] == '{' &&
12278 tolower(Constraint[1]) == 's' &&
12279 tolower(Constraint[2]) == 't' &&
12280 Constraint[3] == '(' &&
12281 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
12282 Constraint[5] == ')' &&
12283 Constraint[6] == '}') {
12285 Res.first = X86::ST0+Constraint[4]-'0';
12286 Res.second = X86::RFP80RegisterClass;
12290 // GCC allows "st(0)" to be called just plain "st".
12291 if (StringRef("{st}").equals_lower(Constraint)) {
12292 Res.first = X86::ST0;
12293 Res.second = X86::RFP80RegisterClass;
12298 if (StringRef("{flags}").equals_lower(Constraint)) {
12299 Res.first = X86::EFLAGS;
12300 Res.second = X86::CCRRegisterClass;
12304 // 'A' means EAX + EDX.
12305 if (Constraint == "A") {
12306 Res.first = X86::EAX;
12307 Res.second = X86::GR32_ADRegisterClass;
12313 // Otherwise, check to see if this is a register class of the wrong value
12314 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
12315 // turn into {ax},{dx}.
12316 if (Res.second->hasType(VT))
12317 return Res; // Correct type already, nothing to do.
12319 // All of the single-register GCC register classes map their values onto
12320 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
12321 // really want an 8-bit or 32-bit register, map to the appropriate register
12322 // class and return the appropriate register.
12323 if (Res.second == X86::GR16RegisterClass) {
12324 if (VT == MVT::i8) {
12325 unsigned DestReg = 0;
12326 switch (Res.first) {
12328 case X86::AX: DestReg = X86::AL; break;
12329 case X86::DX: DestReg = X86::DL; break;
12330 case X86::CX: DestReg = X86::CL; break;
12331 case X86::BX: DestReg = X86::BL; break;
12334 Res.first = DestReg;
12335 Res.second = X86::GR8RegisterClass;
12337 } else if (VT == MVT::i32) {
12338 unsigned DestReg = 0;
12339 switch (Res.first) {
12341 case X86::AX: DestReg = X86::EAX; break;
12342 case X86::DX: DestReg = X86::EDX; break;
12343 case X86::CX: DestReg = X86::ECX; break;
12344 case X86::BX: DestReg = X86::EBX; break;
12345 case X86::SI: DestReg = X86::ESI; break;
12346 case X86::DI: DestReg = X86::EDI; break;
12347 case X86::BP: DestReg = X86::EBP; break;
12348 case X86::SP: DestReg = X86::ESP; break;
12351 Res.first = DestReg;
12352 Res.second = X86::GR32RegisterClass;
12354 } else if (VT == MVT::i64) {
12355 unsigned DestReg = 0;
12356 switch (Res.first) {
12358 case X86::AX: DestReg = X86::RAX; break;
12359 case X86::DX: DestReg = X86::RDX; break;
12360 case X86::CX: DestReg = X86::RCX; break;
12361 case X86::BX: DestReg = X86::RBX; break;
12362 case X86::SI: DestReg = X86::RSI; break;
12363 case X86::DI: DestReg = X86::RDI; break;
12364 case X86::BP: DestReg = X86::RBP; break;
12365 case X86::SP: DestReg = X86::RSP; break;
12368 Res.first = DestReg;
12369 Res.second = X86::GR64RegisterClass;
12372 } else if (Res.second == X86::FR32RegisterClass ||
12373 Res.second == X86::FR64RegisterClass ||
12374 Res.second == X86::VR128RegisterClass) {
12375 // Handle references to XMM physical registers that got mapped into the
12376 // wrong class. This can happen with constraints like {xmm0} where the
12377 // target independent register mapper will just pick the first match it can
12378 // find, ignoring the required type.
12379 if (VT == MVT::f32)
12380 Res.second = X86::FR32RegisterClass;
12381 else if (VT == MVT::f64)
12382 Res.second = X86::FR64RegisterClass;
12383 else if (X86::VR128RegisterClass->hasType(VT))
12384 Res.second = X86::VR128RegisterClass;