1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 int Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 EVT VT = Vec.getValueType();
103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
105 EVT ElVT = VT.getVectorElementType();
106 EVT ResultVT = Result.getValueType();
108 // Insert the relevant 128 bits.
109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
111 // This is the index of the first element of the 128-bit chunk
113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
122 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
123 /// instructions. This is used because creating CONCAT_VECTOR nodes of
124 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
125 /// large BUILD_VECTORS.
126 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
127 unsigned NumElems, SelectionDAG &DAG,
129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
133 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
135 bool is64Bit = Subtarget->is64Bit();
137 if (Subtarget->isTargetEnvMacho()) {
139 return new X8664_MachoTargetObjectFile();
140 return new TargetLoweringObjectFileMachO();
143 if (Subtarget->isTargetELF())
144 return new TargetLoweringObjectFileELF();
145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
146 return new TargetLoweringObjectFileCOFF();
147 llvm_unreachable("unknown subtarget type");
150 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
151 : TargetLowering(TM, createTLOF(TM)) {
152 Subtarget = &TM.getSubtarget<X86Subtarget>();
153 X86ScalarSSEf64 = Subtarget->hasSSE2();
154 X86ScalarSSEf32 = Subtarget->hasSSE1();
155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
157 RegInfo = TM.getRegisterInfo();
158 TD = getTargetData();
160 // Set up the TargetLowering object.
161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
163 // X86 is weird, it always uses i8 for shift amounts and setcc results.
164 setBooleanContents(ZeroOrOneBooleanContent);
165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
168 // For 64-bit since we have so many registers use the ILP scheduler, for
169 // 32-bit code use the register pressure specific scheduling.
170 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
171 if (Subtarget->is64Bit())
172 setSchedulingPreference(Sched::ILP);
173 else if (Subtarget->isAtom())
174 setSchedulingPreference(Sched::Hybrid);
176 setSchedulingPreference(Sched::RegPressure);
177 setStackPointerRegisterToSaveRestore(X86StackPtr);
179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
180 // Setup Windows compiler runtime calls.
181 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
183 setLibcallName(RTLIB::SREM_I64, "_allrem");
184 setLibcallName(RTLIB::UREM_I64, "_aullrem");
185 setLibcallName(RTLIB::MUL_I64, "_allmul");
186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
192 // The _ftol2 runtime function has an unusual calling conv, which
193 // is modeled by a special pseudo-instruction.
194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
200 if (Subtarget->isTargetDarwin()) {
201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
202 setUseUnderscoreSetJmp(false);
203 setUseUnderscoreLongJmp(false);
204 } else if (Subtarget->isTargetMingw()) {
205 // MS runtime is weird: it exports _setjmp, but longjmp!
206 setUseUnderscoreSetJmp(true);
207 setUseUnderscoreLongJmp(false);
209 setUseUnderscoreSetJmp(true);
210 setUseUnderscoreLongJmp(true);
213 // Set up the register classes.
214 addRegisterClass(MVT::i8, &X86::GR8RegClass);
215 addRegisterClass(MVT::i16, &X86::GR16RegClass);
216 addRegisterClass(MVT::i32, &X86::GR32RegClass);
217 if (Subtarget->is64Bit())
218 addRegisterClass(MVT::i64, &X86::GR64RegClass);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 // We don't accept any truncstore of integer registers.
223 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
224 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
226 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
228 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
230 // SETOEQ and SETUNE require checking two conditions.
231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
247 } else if (!TM.Options.UseSoftFloat) {
248 // We have an algorithm for SSE2->double, and we turn this into a
249 // 64-bit FILD followed by conditional FADD for other targets.
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 // We have an algorithm for SSE2, and we turn this into a 64-bit
252 // FILD for other targets.
253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
261 if (!TM.Options.UseSoftFloat) {
262 // SSE has no i16 to fp conversion, only i32
263 if (X86ScalarSSEf32) {
264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
265 // f32 and f64 cases are Legal, f80 case is not
266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
277 // are Legal, f80 is custom lowered.
278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
286 if (X86ScalarSSEf32) {
287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
288 // f32 and f64 cases are Legal, f80 case is not
289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 // Handle FP_TO_UINT by promoting the destination to a larger signed
297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
301 if (Subtarget->is64Bit()) {
302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
304 } else if (!TM.Options.UseSoftFloat) {
305 // Since AVX is a superset of SSE3, only check for SSE here.
306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
307 // Expand FP_TO_UINT into a select.
308 // FIXME: We would like to use a Custom expander here eventually to do
309 // the optimal thing for SSE vs. the default expansion in the legalizer.
310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
312 // With SSE3 we can use fisttpll to convert to a signed i64; without
313 // SSE, we're stuck with a fistpll.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
317 if (isTargetFTOL()) {
318 // Use the _ftol2 runtime function, which has a pseudo-instruction
319 // to handle its weird calling convention.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
323 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
324 if (!X86ScalarSSEf64) {
325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
329 // Without SSE, i64->f64 goes through memory.
330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
334 // Scalar integer divide and remainder are lowered to use operations that
335 // produce two results, to match the available instructions. This exposes
336 // the two-result form to trivial CSE, which is able to combine x/y and x%y
337 // into a single instruction.
339 // Scalar integer multiply-high is also lowered to use two-result
340 // operations, to match the available instructions. However, plain multiply
341 // (low) operations are left as Legal, as there are single-result
342 // instructions for this in x86. Using the two-result multiply instructions
343 // when both high and low results are needed must be arranged by dagcombine.
344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
346 setOperationAction(ISD::MULHS, VT, Expand);
347 setOperationAction(ISD::MULHU, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
354 setOperationAction(ISD::ADDC, VT, Custom);
355 setOperationAction(ISD::ADDE, VT, Custom);
356 setOperationAction(ISD::SUBC, VT, Custom);
357 setOperationAction(ISD::SUBE, VT, Custom);
360 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
361 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
362 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f32 , Expand);
371 setOperationAction(ISD::FREM , MVT::f64 , Expand);
372 setOperationAction(ISD::FREM , MVT::f80 , Expand);
373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
375 // Promote the i8 variants and force them on up to i32 which has a shorter
377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 if (Subtarget->hasLZCNT()) {
394 // When promoting the i8 variants, force them to i32 for a shorter
396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
417 if (Subtarget->hasPOPCNT()) {
418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
430 // These should be promoted to a larger select which is supported.
431 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
432 // X86 wants to expand cmov itself.
433 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
435 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
438 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
441 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
444 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
460 if (Subtarget->is64Bit()) {
461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
471 if (Subtarget->is64Bit()) {
472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
477 if (Subtarget->hasSSE1())
478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
483 // On X86 and X86-64, atomic operations are lowered to locked instructions.
484 // Locked instructions, in turn, have implicit fence semantics (all memory
485 // operations are flushed before issuing the locked instruction, and they
486 // are not buffered), so we can fold away the common pattern of
487 // fence-atomic-fence.
488 setShouldFoldAtomicFences(true);
490 // Expand certain atomics
491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
498 if (!Subtarget->is64Bit()) {
499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
509 if (Subtarget->hasCmpxchg16b()) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
513 // FIXME - use subtarget debug flags
514 if (!Subtarget->isTargetDarwin() &&
515 !Subtarget->isTargetELF() &&
516 !Subtarget->isTargetCygMing()) {
517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
524 if (Subtarget->is64Bit()) {
525 setExceptionPointerRegister(X86::RAX);
526 setExceptionSelectorRegister(X86::RDX);
528 setExceptionPointerRegister(X86::EAX);
529 setExceptionSelectorRegister(X86::EDX);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
537 setOperationAction(ISD::TRAP, MVT::Other, Legal);
539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
540 setOperationAction(ISD::VASTART , MVT::Other, Custom);
541 setOperationAction(ISD::VAEND , MVT::Other, Expand);
542 if (Subtarget->is64Bit()) {
543 setOperationAction(ISD::VAARG , MVT::Other, Custom);
544 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
546 setOperationAction(ISD::VAARG , MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
555 MVT::i64 : MVT::i32, Custom);
556 else if (TM.Options.EnableSegmentedStacks)
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Expand);
563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
564 // f32 and f64 use SSE.
565 // Set up the FP register classes.
566 addRegisterClass(MVT::f32, &X86::FR32RegClass);
567 addRegisterClass(MVT::f64, &X86::FR64RegClass);
569 // Use ANDPD to simulate FABS.
570 setOperationAction(ISD::FABS , MVT::f64, Custom);
571 setOperationAction(ISD::FABS , MVT::f32, Custom);
573 // Use XORP to simulate FNEG.
574 setOperationAction(ISD::FNEG , MVT::f64, Custom);
575 setOperationAction(ISD::FNEG , MVT::f32, Custom);
577 // Use ANDPD and ORPD to simulate FCOPYSIGN.
578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
581 // Lower this to FGETSIGNx86 plus an AND.
582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f64, Expand);
587 setOperationAction(ISD::FCOS , MVT::f64, Expand);
588 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FCOS , MVT::f32, Expand);
591 // Expand FP immediates into loads from the stack, except for the special
593 addLegalFPImmediate(APFloat(+0.0)); // xorpd
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
596 // Use SSE for f32, x87 for f64.
597 // Set up the FP register classes.
598 addRegisterClass(MVT::f32, &X86::FR32RegClass);
599 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
601 // Use ANDPS to simulate FABS.
602 setOperationAction(ISD::FABS , MVT::f32, Custom);
604 // Use XORP to simulate FNEG.
605 setOperationAction(ISD::FNEG , MVT::f32, Custom);
607 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
609 // Use ANDPS and ORPS to simulate FCOPYSIGN.
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
613 // We don't support sin/cos/fmod
614 setOperationAction(ISD::FSIN , MVT::f32, Expand);
615 setOperationAction(ISD::FCOS , MVT::f32, Expand);
617 // Special cases we handle for FP constants.
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
624 if (!TM.Options.UnsafeFPMath) {
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 } else if (!TM.Options.UseSoftFloat) {
629 // f32 and f64 in x87.
630 // Set up the FP register classes.
631 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
632 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
634 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
635 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
653 // We don't support FMA.
654 setOperationAction(ISD::FMA, MVT::f64, Expand);
655 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 // Long double always uses X87.
658 if (!TM.Options.UseSoftFloat) {
659 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
664 addLegalFPImmediate(TmpFlt); // FLD0
666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
669 APFloat TmpFlt2(+1.0);
670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
672 addLegalFPImmediate(TmpFlt2); // FLD1
673 TmpFlt2.changeSign();
674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
677 if (!TM.Options.UnsafeFPMath) {
678 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
679 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
683 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
685 setOperationAction(ISD::FRINT, MVT::f80, Expand);
686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
687 setOperationAction(ISD::FMA, MVT::f80, Expand);
690 // Always use a library call for pow.
691 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
693 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
695 setOperationAction(ISD::FLOG, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
697 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP, MVT::f80, Expand);
699 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
701 // First set operation action for all vector types to either promote
702 // (for widening) or expand (for scalarization). Then we will selectively
703 // turn on ones that can be effectively codegen'd.
704 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
705 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
763 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
764 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
765 setTruncStoreAction((MVT::SimpleValueType)VT,
766 (MVT::SimpleValueType)InnerVT, Expand);
767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
773 // with -msoft-float, disable use of MMX as well.
774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
776 // No operations on x86mmx supported, everything uses intrinsics.
779 // MMX-sized vectors (other than x86mmx) are expected to be expanded
780 // into smaller operations.
781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
785 setOperationAction(ISD::AND, MVT::v8i8, Expand);
786 setOperationAction(ISD::AND, MVT::v4i16, Expand);
787 setOperationAction(ISD::AND, MVT::v2i32, Expand);
788 setOperationAction(ISD::AND, MVT::v1i64, Expand);
789 setOperationAction(ISD::OR, MVT::v8i8, Expand);
790 setOperationAction(ISD::OR, MVT::v4i16, Expand);
791 setOperationAction(ISD::OR, MVT::v2i32, Expand);
792 setOperationAction(ISD::OR, MVT::v1i64, Expand);
793 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
794 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
795 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
796 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
814 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
832 // registers cannot be used even for integer operations.
833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
838 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
839 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
840 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
841 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
843 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
844 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
845 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
846 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
848 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR,
882 VT.getSimpleVT().SimpleTy, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE,
884 VT.getSimpleVT().SimpleTy, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
886 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
902 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
906 // Do not attempt to promote non-128-bit vectors
907 if (!VT.is128BitVector())
910 setOperationAction(ISD::AND, SVT, Promote);
911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
912 setOperationAction(ISD::OR, SVT, Promote);
913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
914 setOperationAction(ISD::XOR, SVT, Promote);
915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
916 setOperationAction(ISD::LOAD, SVT, Promote);
917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
918 setOperationAction(ISD::SELECT, SVT, Promote);
919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
922 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
924 // Custom lower v2i64 and v2f64 selects.
925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
934 if (Subtarget->hasSSE41()) {
935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
938 setOperationAction(ISD::FRINT, MVT::f32, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
946 // FIXME: Do we need to handle scalar-to-vector here?
947 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
955 // i8 and i16 vectors are custom , because the source register and source
956 // source memory operand types are not the same width. f32 vectors are
957 // custom since the immediate controlling the insert encodes additional
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
969 // FIXME: these should be Legal but thats only for the case where
970 // the index is constant. For now custom expand to deal with that.
971 if (Subtarget->is64Bit()) {
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
977 if (Subtarget->hasSSE2()) {
978 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
981 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
987 if (Subtarget->hasAVX2()) {
988 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
989 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
991 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
997 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1006 if (Subtarget->hasSSE42())
1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1069 if (Subtarget->hasAVX2()) {
1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1083 // Don't lower v32i8 because there is no 128-bit byte mul
1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1108 // Don't lower v32i8 because there is no 128-bit byte mul
1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1119 // Custom lower several nodes for 256-bit types.
1120 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1125 // Extract subvector is special because the value type
1126 // (result) is 128-bit but the source is 256-bit wide.
1127 if (VT.is128BitVector())
1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1130 // Do not attempt to custom lower other non-256-bit vectors
1131 if (!VT.is256BitVector())
1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1143 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1147 // Do not attempt to promote non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::AND, SVT, Promote);
1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1153 setOperationAction(ISD::OR, SVT, Promote);
1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1155 setOperationAction(ISD::XOR, SVT, Promote);
1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1157 setOperationAction(ISD::LOAD, SVT, Promote);
1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1159 setOperationAction(ISD::SELECT, SVT, Promote);
1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1165 // of this type with custom code.
1166 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1167 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1172 // We want to custom lower some of our intrinsics.
1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1177 // handle type legalization for these operations here.
1179 // FIXME: We really should do custom legalization for addition and
1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1181 // than generic legalization for 64-bit multiplication-with-overflow, though.
1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1183 // Add/Sub/Mul with overflow operations are custom lowered.
1185 setOperationAction(ISD::SADDO, VT, Custom);
1186 setOperationAction(ISD::UADDO, VT, Custom);
1187 setOperationAction(ISD::SSUBO, VT, Custom);
1188 setOperationAction(ISD::USUBO, VT, Custom);
1189 setOperationAction(ISD::SMULO, VT, Custom);
1190 setOperationAction(ISD::UMULO, VT, Custom);
1193 // There are no 8-bit 3-address imul/mul instructions
1194 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1195 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1197 if (!Subtarget->is64Bit()) {
1198 // These libcalls are not available in 32-bit.
1199 setLibcallName(RTLIB::SHL_I128, 0);
1200 setLibcallName(RTLIB::SRL_I128, 0);
1201 setLibcallName(RTLIB::SRA_I128, 0);
1204 // We have target-specific dag combine patterns for the following nodes:
1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1207 setTargetDAGCombine(ISD::VSELECT);
1208 setTargetDAGCombine(ISD::SELECT);
1209 setTargetDAGCombine(ISD::SHL);
1210 setTargetDAGCombine(ISD::SRA);
1211 setTargetDAGCombine(ISD::SRL);
1212 setTargetDAGCombine(ISD::OR);
1213 setTargetDAGCombine(ISD::AND);
1214 setTargetDAGCombine(ISD::ADD);
1215 setTargetDAGCombine(ISD::FADD);
1216 setTargetDAGCombine(ISD::FSUB);
1217 setTargetDAGCombine(ISD::SUB);
1218 setTargetDAGCombine(ISD::LOAD);
1219 setTargetDAGCombine(ISD::STORE);
1220 setTargetDAGCombine(ISD::ZERO_EXTEND);
1221 setTargetDAGCombine(ISD::ANY_EXTEND);
1222 setTargetDAGCombine(ISD::SIGN_EXTEND);
1223 setTargetDAGCombine(ISD::TRUNCATE);
1224 setTargetDAGCombine(ISD::SINT_TO_FP);
1225 if (Subtarget->is64Bit())
1226 setTargetDAGCombine(ISD::MUL);
1227 if (Subtarget->hasBMI())
1228 setTargetDAGCombine(ISD::XOR);
1230 computeRegisterProperties();
1232 // On Darwin, -Os means optimize for size without hurting performance,
1233 // do not reduce the limit.
1234 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1235 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1236 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1237 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1238 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1239 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1240 setPrefLoopAlignment(4); // 2^4 bytes.
1241 benefitFromCodePlacementOpt = true;
1243 setPrefFunctionAlignment(4); // 2^4 bytes.
1247 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1248 if (!VT.isVector()) return MVT::i8;
1249 return VT.changeVectorElementTypeToInteger();
1253 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1254 /// the desired ByVal argument alignment.
1255 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1258 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1259 if (VTy->getBitWidth() == 128)
1261 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1262 unsigned EltAlign = 0;
1263 getMaxByValAlign(ATy->getElementType(), EltAlign);
1264 if (EltAlign > MaxAlign)
1265 MaxAlign = EltAlign;
1266 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1267 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1268 unsigned EltAlign = 0;
1269 getMaxByValAlign(STy->getElementType(i), EltAlign);
1270 if (EltAlign > MaxAlign)
1271 MaxAlign = EltAlign;
1278 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1279 /// function arguments in the caller parameter area. For X86, aggregates
1280 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1281 /// are at 4-byte boundaries.
1282 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1283 if (Subtarget->is64Bit()) {
1284 // Max of 8 and alignment of type.
1285 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1292 if (Subtarget->hasSSE1())
1293 getMaxByValAlign(Ty, Align);
1297 /// getOptimalMemOpType - Returns the target specific optimal type for load
1298 /// and store operations as a result of memset, memcpy, and memmove
1299 /// lowering. If DstAlign is zero that means it's safe to destination
1300 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1301 /// means there isn't a need to check it against alignment requirement,
1302 /// probably because the source does not need to be loaded. If
1303 /// 'IsZeroVal' is true, that means it's safe to return a
1304 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1305 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1306 /// constant so it does not need to be loaded.
1307 /// It returns EVT::Other if the type should be determined using generic
1308 /// target-independent logic.
1310 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1311 unsigned DstAlign, unsigned SrcAlign,
1314 MachineFunction &MF) const {
1315 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1316 // linux. This is because the stack realignment code can't handle certain
1317 // cases like PR2962. This should be removed when PR2962 is fixed.
1318 const Function *F = MF.getFunction();
1320 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1322 (Subtarget->isUnalignedMemAccessFast() ||
1323 ((DstAlign == 0 || DstAlign >= 16) &&
1324 (SrcAlign == 0 || SrcAlign >= 16))) &&
1325 Subtarget->getStackAlignment() >= 16) {
1326 if (Subtarget->getStackAlignment() >= 32) {
1327 if (Subtarget->hasAVX2())
1329 if (Subtarget->hasAVX())
1332 if (Subtarget->hasSSE2())
1334 if (Subtarget->hasSSE1())
1336 } else if (!MemcpyStrSrc && Size >= 8 &&
1337 !Subtarget->is64Bit() &&
1338 Subtarget->getStackAlignment() >= 8 &&
1339 Subtarget->hasSSE2()) {
1340 // Do not use f64 to lower memcpy if source is string constant. It's
1341 // better to use i32 to avoid the loads.
1345 if (Subtarget->is64Bit() && Size >= 8)
1350 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1351 /// current function. The returned value is a member of the
1352 /// MachineJumpTableInfo::JTEntryKind enum.
1353 unsigned X86TargetLowering::getJumpTableEncoding() const {
1354 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1356 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1357 Subtarget->isPICStyleGOT())
1358 return MachineJumpTableInfo::EK_Custom32;
1360 // Otherwise, use the normal jump table encoding heuristics.
1361 return TargetLowering::getJumpTableEncoding();
1365 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1366 const MachineBasicBlock *MBB,
1367 unsigned uid,MCContext &Ctx) const{
1368 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1369 Subtarget->isPICStyleGOT());
1370 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1372 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1373 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1376 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1378 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1379 SelectionDAG &DAG) const {
1380 if (!Subtarget->is64Bit())
1381 // This doesn't have DebugLoc associated with it, but is not really the
1382 // same as a Register.
1383 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1387 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1388 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1390 const MCExpr *X86TargetLowering::
1391 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1392 MCContext &Ctx) const {
1393 // X86-64 uses RIP relative addressing based on the jump table label.
1394 if (Subtarget->isPICStyleRIPRel())
1395 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1397 // Otherwise, the reference is relative to the PIC base.
1398 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1401 // FIXME: Why this routine is here? Move to RegInfo!
1402 std::pair<const TargetRegisterClass*, uint8_t>
1403 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1404 const TargetRegisterClass *RRC = 0;
1406 switch (VT.getSimpleVT().SimpleTy) {
1408 return TargetLowering::findRepresentativeClass(VT);
1409 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1410 RRC = Subtarget->is64Bit() ?
1411 (const TargetRegisterClass*)&X86::GR64RegClass :
1412 (const TargetRegisterClass*)&X86::GR32RegClass;
1415 RRC = &X86::VR64RegClass;
1417 case MVT::f32: case MVT::f64:
1418 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1419 case MVT::v4f32: case MVT::v2f64:
1420 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1422 RRC = &X86::VR128RegClass;
1425 return std::make_pair(RRC, Cost);
1428 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1429 unsigned &Offset) const {
1430 if (!Subtarget->isTargetLinux())
1433 if (Subtarget->is64Bit()) {
1434 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1436 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1449 //===----------------------------------------------------------------------===//
1450 // Return Value Calling Convention Implementation
1451 //===----------------------------------------------------------------------===//
1453 #include "X86GenCallingConv.inc"
1456 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1457 MachineFunction &MF, bool isVarArg,
1458 const SmallVectorImpl<ISD::OutputArg> &Outs,
1459 LLVMContext &Context) const {
1460 SmallVector<CCValAssign, 16> RVLocs;
1461 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1463 return CCInfo.CheckReturn(Outs, RetCC_X86);
1467 X86TargetLowering::LowerReturn(SDValue Chain,
1468 CallingConv::ID CallConv, bool isVarArg,
1469 const SmallVectorImpl<ISD::OutputArg> &Outs,
1470 const SmallVectorImpl<SDValue> &OutVals,
1471 DebugLoc dl, SelectionDAG &DAG) const {
1472 MachineFunction &MF = DAG.getMachineFunction();
1473 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1475 SmallVector<CCValAssign, 16> RVLocs;
1476 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1477 RVLocs, *DAG.getContext());
1478 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1480 // Add the regs to the liveout set for the function.
1481 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1482 for (unsigned i = 0; i != RVLocs.size(); ++i)
1483 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1484 MRI.addLiveOut(RVLocs[i].getLocReg());
1488 SmallVector<SDValue, 6> RetOps;
1489 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1490 // Operand #1 = Bytes To Pop
1491 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1494 // Copy the result values into the output registers.
1495 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1496 CCValAssign &VA = RVLocs[i];
1497 assert(VA.isRegLoc() && "Can only return in registers!");
1498 SDValue ValToCopy = OutVals[i];
1499 EVT ValVT = ValToCopy.getValueType();
1501 // If this is x86-64, and we disabled SSE, we can't return FP values,
1502 // or SSE or MMX vectors.
1503 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1504 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1505 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1506 report_fatal_error("SSE register return with SSE disabled");
1508 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1509 // llvm-gcc has never done it right and no one has noticed, so this
1510 // should be OK for now.
1511 if (ValVT == MVT::f64 &&
1512 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1513 report_fatal_error("SSE2 register return with SSE2 disabled");
1515 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1516 // the RET instruction and handled by the FP Stackifier.
1517 if (VA.getLocReg() == X86::ST0 ||
1518 VA.getLocReg() == X86::ST1) {
1519 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1520 // change the value to the FP stack register class.
1521 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1522 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1523 RetOps.push_back(ValToCopy);
1524 // Don't emit a copytoreg.
1528 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1529 // which is returned in RAX / RDX.
1530 if (Subtarget->is64Bit()) {
1531 if (ValVT == MVT::x86mmx) {
1532 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1533 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1534 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1536 // If we don't have SSE2 available, convert to v4f32 so the generated
1537 // register is legal.
1538 if (!Subtarget->hasSSE2())
1539 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1544 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1545 Flag = Chain.getValue(1);
1548 // The x86-64 ABI for returning structs by value requires that we copy
1549 // the sret argument into %rax for the return. We saved the argument into
1550 // a virtual register in the entry block, so now we copy the value out
1552 if (Subtarget->is64Bit() &&
1553 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1554 MachineFunction &MF = DAG.getMachineFunction();
1555 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1556 unsigned Reg = FuncInfo->getSRetReturnReg();
1558 "SRetReturnReg should have been set in LowerFormalArguments().");
1559 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1561 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1562 Flag = Chain.getValue(1);
1564 // RAX now acts like a return value.
1565 MRI.addLiveOut(X86::RAX);
1568 RetOps[0] = Chain; // Update chain.
1570 // Add the flag if we have it.
1572 RetOps.push_back(Flag);
1574 return DAG.getNode(X86ISD::RET_FLAG, dl,
1575 MVT::Other, &RetOps[0], RetOps.size());
1578 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1579 if (N->getNumValues() != 1)
1581 if (!N->hasNUsesOfValue(1, 0))
1584 SDValue TCChain = Chain;
1585 SDNode *Copy = *N->use_begin();
1586 if (Copy->getOpcode() == ISD::CopyToReg) {
1587 // If the copy has a glue operand, we conservatively assume it isn't safe to
1588 // perform a tail call.
1589 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1591 TCChain = Copy->getOperand(0);
1592 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1595 bool HasRet = false;
1596 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1598 if (UI->getOpcode() != X86ISD::RET_FLAG)
1611 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1612 ISD::NodeType ExtendKind) const {
1614 // TODO: Is this also valid on 32-bit?
1615 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1616 ReturnMVT = MVT::i8;
1618 ReturnMVT = MVT::i32;
1620 EVT MinVT = getRegisterType(Context, ReturnMVT);
1621 return VT.bitsLT(MinVT) ? MinVT : VT;
1624 /// LowerCallResult - Lower the result values of a call into the
1625 /// appropriate copies out of appropriate physical registers.
1628 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1629 CallingConv::ID CallConv, bool isVarArg,
1630 const SmallVectorImpl<ISD::InputArg> &Ins,
1631 DebugLoc dl, SelectionDAG &DAG,
1632 SmallVectorImpl<SDValue> &InVals) const {
1634 // Assign locations to each value returned by this call.
1635 SmallVector<CCValAssign, 16> RVLocs;
1636 bool Is64Bit = Subtarget->is64Bit();
1637 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1638 getTargetMachine(), RVLocs, *DAG.getContext());
1639 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1641 // Copy all of the result registers out of their specified physreg.
1642 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1643 CCValAssign &VA = RVLocs[i];
1644 EVT CopyVT = VA.getValVT();
1646 // If this is x86-64, and we disabled SSE, we can't return FP values
1647 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1648 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1649 report_fatal_error("SSE register return with SSE disabled");
1654 // If this is a call to a function that returns an fp value on the floating
1655 // point stack, we must guarantee the the value is popped from the stack, so
1656 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1657 // if the return value is not used. We use the FpPOP_RETVAL instruction
1659 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1660 // If we prefer to use the value in xmm registers, copy it out as f80 and
1661 // use a truncate to move it from fp stack reg to xmm reg.
1662 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1663 SDValue Ops[] = { Chain, InFlag };
1664 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1665 MVT::Other, MVT::Glue, Ops, 2), 1);
1666 Val = Chain.getValue(0);
1668 // Round the f80 to the right size, which also moves it to the appropriate
1670 if (CopyVT != VA.getValVT())
1671 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1672 // This truncation won't change the value.
1673 DAG.getIntPtrConstant(1));
1675 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1676 CopyVT, InFlag).getValue(1);
1677 Val = Chain.getValue(0);
1679 InFlag = Chain.getValue(2);
1680 InVals.push_back(Val);
1687 //===----------------------------------------------------------------------===//
1688 // C & StdCall & Fast Calling Convention implementation
1689 //===----------------------------------------------------------------------===//
1690 // StdCall calling convention seems to be standard for many Windows' API
1691 // routines and around. It differs from C calling convention just a little:
1692 // callee should clean up the stack, not caller. Symbols should be also
1693 // decorated in some fancy way :) It doesn't support any vector arguments.
1694 // For info on fast calling convention see Fast Calling Convention (tail call)
1695 // implementation LowerX86_32FastCCCallTo.
1697 /// CallIsStructReturn - Determines whether a call uses struct return
1699 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1703 return Outs[0].Flags.isSRet();
1706 /// ArgsAreStructReturn - Determines whether a function uses struct
1707 /// return semantics.
1709 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1713 return Ins[0].Flags.isSRet();
1716 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1717 /// by "Src" to address "Dst" with size and alignment information specified by
1718 /// the specific parameter attribute. The copy will be passed as a byval
1719 /// function parameter.
1721 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1722 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1724 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1726 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1727 /*isVolatile*/false, /*AlwaysInline=*/true,
1728 MachinePointerInfo(), MachinePointerInfo());
1731 /// IsTailCallConvention - Return true if the calling convention is one that
1732 /// supports tail call optimization.
1733 static bool IsTailCallConvention(CallingConv::ID CC) {
1734 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1737 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1738 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1742 CallingConv::ID CalleeCC = CS.getCallingConv();
1743 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1749 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1750 /// a tailcall target by changing its ABI.
1751 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1752 bool GuaranteedTailCallOpt) {
1753 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1757 X86TargetLowering::LowerMemArgument(SDValue Chain,
1758 CallingConv::ID CallConv,
1759 const SmallVectorImpl<ISD::InputArg> &Ins,
1760 DebugLoc dl, SelectionDAG &DAG,
1761 const CCValAssign &VA,
1762 MachineFrameInfo *MFI,
1764 // Create the nodes corresponding to a load from this parameter slot.
1765 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1766 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1767 getTargetMachine().Options.GuaranteedTailCallOpt);
1768 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1771 // If value is passed by pointer we have address passed instead of the value
1773 if (VA.getLocInfo() == CCValAssign::Indirect)
1774 ValVT = VA.getLocVT();
1776 ValVT = VA.getValVT();
1778 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1779 // changed with more analysis.
1780 // In case of tail call optimization mark all arguments mutable. Since they
1781 // could be overwritten by lowering of arguments in case of a tail call.
1782 if (Flags.isByVal()) {
1783 unsigned Bytes = Flags.getByValSize();
1784 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1785 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1786 return DAG.getFrameIndex(FI, getPointerTy());
1788 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1789 VA.getLocMemOffset(), isImmutable);
1790 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1791 return DAG.getLoad(ValVT, dl, Chain, FIN,
1792 MachinePointerInfo::getFixedStack(FI),
1793 false, false, false, 0);
1798 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1799 CallingConv::ID CallConv,
1801 const SmallVectorImpl<ISD::InputArg> &Ins,
1804 SmallVectorImpl<SDValue> &InVals)
1806 MachineFunction &MF = DAG.getMachineFunction();
1807 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1809 const Function* Fn = MF.getFunction();
1810 if (Fn->hasExternalLinkage() &&
1811 Subtarget->isTargetCygMing() &&
1812 Fn->getName() == "main")
1813 FuncInfo->setForceFramePointer(true);
1815 MachineFrameInfo *MFI = MF.getFrameInfo();
1816 bool Is64Bit = Subtarget->is64Bit();
1817 bool IsWindows = Subtarget->isTargetWindows();
1818 bool IsWin64 = Subtarget->isTargetWin64();
1820 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1821 "Var args not supported with calling convention fastcc or ghc");
1823 // Assign locations to all of the incoming arguments.
1824 SmallVector<CCValAssign, 16> ArgLocs;
1825 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1826 ArgLocs, *DAG.getContext());
1828 // Allocate shadow area for Win64
1830 CCInfo.AllocateStack(32, 8);
1833 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1835 unsigned LastVal = ~0U;
1837 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1838 CCValAssign &VA = ArgLocs[i];
1839 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1841 assert(VA.getValNo() != LastVal &&
1842 "Don't support value assigned to multiple locs yet");
1844 LastVal = VA.getValNo();
1846 if (VA.isRegLoc()) {
1847 EVT RegVT = VA.getLocVT();
1848 const TargetRegisterClass *RC;
1849 if (RegVT == MVT::i32)
1850 RC = &X86::GR32RegClass;
1851 else if (Is64Bit && RegVT == MVT::i64)
1852 RC = &X86::GR64RegClass;
1853 else if (RegVT == MVT::f32)
1854 RC = &X86::FR32RegClass;
1855 else if (RegVT == MVT::f64)
1856 RC = &X86::FR64RegClass;
1857 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1858 RC = &X86::VR256RegClass;
1859 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1860 RC = &X86::VR128RegClass;
1861 else if (RegVT == MVT::x86mmx)
1862 RC = &X86::VR64RegClass;
1864 llvm_unreachable("Unknown argument type!");
1866 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1867 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1869 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1870 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1872 if (VA.getLocInfo() == CCValAssign::SExt)
1873 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1874 DAG.getValueType(VA.getValVT()));
1875 else if (VA.getLocInfo() == CCValAssign::ZExt)
1876 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1877 DAG.getValueType(VA.getValVT()));
1878 else if (VA.getLocInfo() == CCValAssign::BCvt)
1879 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1881 if (VA.isExtInLoc()) {
1882 // Handle MMX values passed in XMM regs.
1883 if (RegVT.isVector()) {
1884 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1887 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1890 assert(VA.isMemLoc());
1891 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1894 // If value is passed via pointer - do a load.
1895 if (VA.getLocInfo() == CCValAssign::Indirect)
1896 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1897 MachinePointerInfo(), false, false, false, 0);
1899 InVals.push_back(ArgValue);
1902 // The x86-64 ABI for returning structs by value requires that we copy
1903 // the sret argument into %rax for the return. Save the argument into
1904 // a virtual register so that we can access it from the return points.
1905 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1906 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1907 unsigned Reg = FuncInfo->getSRetReturnReg();
1909 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1910 FuncInfo->setSRetReturnReg(Reg);
1912 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1913 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1916 unsigned StackSize = CCInfo.getNextStackOffset();
1917 // Align stack specially for tail calls.
1918 if (FuncIsMadeTailCallSafe(CallConv,
1919 MF.getTarget().Options.GuaranteedTailCallOpt))
1920 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1922 // If the function takes variable number of arguments, make a frame index for
1923 // the start of the first vararg value... for expansion of llvm.va_start.
1925 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1926 CallConv != CallingConv::X86_ThisCall)) {
1927 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1930 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1932 // FIXME: We should really autogenerate these arrays
1933 static const uint16_t GPR64ArgRegsWin64[] = {
1934 X86::RCX, X86::RDX, X86::R8, X86::R9
1936 static const uint16_t GPR64ArgRegs64Bit[] = {
1937 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1939 static const uint16_t XMMArgRegs64Bit[] = {
1940 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1941 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1943 const uint16_t *GPR64ArgRegs;
1944 unsigned NumXMMRegs = 0;
1947 // The XMM registers which might contain var arg parameters are shadowed
1948 // in their paired GPR. So we only need to save the GPR to their home
1950 TotalNumIntRegs = 4;
1951 GPR64ArgRegs = GPR64ArgRegsWin64;
1953 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1954 GPR64ArgRegs = GPR64ArgRegs64Bit;
1956 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1959 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1962 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1963 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1964 "SSE register cannot be used when SSE is disabled!");
1965 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1966 NoImplicitFloatOps) &&
1967 "SSE register cannot be used when SSE is disabled!");
1968 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1969 !Subtarget->hasSSE1())
1970 // Kernel mode asks for SSE to be disabled, so don't push them
1972 TotalNumXMMRegs = 0;
1975 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1976 // Get to the caller-allocated home save location. Add 8 to account
1977 // for the return address.
1978 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1979 FuncInfo->setRegSaveFrameIndex(
1980 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1981 // Fixup to set vararg frame on shadow area (4 x i64).
1983 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1985 // For X86-64, if there are vararg parameters that are passed via
1986 // registers, then we must store them to their spots on the stack so
1987 // they may be loaded by deferencing the result of va_next.
1988 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1989 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1990 FuncInfo->setRegSaveFrameIndex(
1991 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1995 // Store the integer parameter registers.
1996 SmallVector<SDValue, 8> MemOps;
1997 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1999 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2000 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2001 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2002 DAG.getIntPtrConstant(Offset));
2003 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2004 &X86::GR64RegClass);
2005 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2007 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2008 MachinePointerInfo::getFixedStack(
2009 FuncInfo->getRegSaveFrameIndex(), Offset),
2011 MemOps.push_back(Store);
2015 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2016 // Now store the XMM (fp + vector) parameter registers.
2017 SmallVector<SDValue, 11> SaveXMMOps;
2018 SaveXMMOps.push_back(Chain);
2020 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2021 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2022 SaveXMMOps.push_back(ALVal);
2024 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2025 FuncInfo->getRegSaveFrameIndex()));
2026 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2027 FuncInfo->getVarArgsFPOffset()));
2029 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2030 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2031 &X86::VR128RegClass);
2032 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2033 SaveXMMOps.push_back(Val);
2035 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2037 &SaveXMMOps[0], SaveXMMOps.size()));
2040 if (!MemOps.empty())
2041 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2042 &MemOps[0], MemOps.size());
2046 // Some CCs need callee pop.
2047 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2048 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2049 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2051 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2052 // If this is an sret function, the return should pop the hidden pointer.
2053 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2054 ArgsAreStructReturn(Ins))
2055 FuncInfo->setBytesToPopOnReturn(4);
2059 // RegSaveFrameIndex is X86-64 only.
2060 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2061 if (CallConv == CallingConv::X86_FastCall ||
2062 CallConv == CallingConv::X86_ThisCall)
2063 // fastcc functions can't have varargs.
2064 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2067 FuncInfo->setArgumentStackSize(StackSize);
2073 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2074 SDValue StackPtr, SDValue Arg,
2075 DebugLoc dl, SelectionDAG &DAG,
2076 const CCValAssign &VA,
2077 ISD::ArgFlagsTy Flags) const {
2078 unsigned LocMemOffset = VA.getLocMemOffset();
2079 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2080 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2081 if (Flags.isByVal())
2082 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2084 return DAG.getStore(Chain, dl, Arg, PtrOff,
2085 MachinePointerInfo::getStack(LocMemOffset),
2089 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2090 /// optimization is performed and it is required.
2092 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2093 SDValue &OutRetAddr, SDValue Chain,
2094 bool IsTailCall, bool Is64Bit,
2095 int FPDiff, DebugLoc dl) const {
2096 // Adjust the Return address stack slot.
2097 EVT VT = getPointerTy();
2098 OutRetAddr = getReturnAddressFrameIndex(DAG);
2100 // Load the "old" Return address.
2101 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2102 false, false, false, 0);
2103 return SDValue(OutRetAddr.getNode(), 1);
2106 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2107 /// optimization is performed and it is required (FPDiff!=0).
2109 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2110 SDValue Chain, SDValue RetAddrFrIdx,
2111 bool Is64Bit, int FPDiff, DebugLoc dl) {
2112 // Store the return address to the appropriate stack slot.
2113 if (!FPDiff) return Chain;
2114 // Calculate the new stack slot for the return address.
2115 int SlotSize = Is64Bit ? 8 : 4;
2116 int NewReturnAddrFI =
2117 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2118 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2119 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2120 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2121 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2127 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2128 CallingConv::ID CallConv, bool isVarArg,
2129 bool doesNotRet, bool &isTailCall,
2130 const SmallVectorImpl<ISD::OutputArg> &Outs,
2131 const SmallVectorImpl<SDValue> &OutVals,
2132 const SmallVectorImpl<ISD::InputArg> &Ins,
2133 DebugLoc dl, SelectionDAG &DAG,
2134 SmallVectorImpl<SDValue> &InVals) const {
2135 MachineFunction &MF = DAG.getMachineFunction();
2136 bool Is64Bit = Subtarget->is64Bit();
2137 bool IsWin64 = Subtarget->isTargetWin64();
2138 bool IsWindows = Subtarget->isTargetWindows();
2139 bool IsStructRet = CallIsStructReturn(Outs);
2140 bool IsSibcall = false;
2142 if (MF.getTarget().Options.DisableTailCalls)
2146 // Check if it's really possible to do a tail call.
2147 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2148 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2149 Outs, OutVals, Ins, DAG);
2151 // Sibcalls are automatically detected tailcalls which do not require
2153 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2160 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2161 "Var args not supported with calling convention fastcc or ghc");
2163 // Analyze operands of the call, assigning locations to each operand.
2164 SmallVector<CCValAssign, 16> ArgLocs;
2165 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2166 ArgLocs, *DAG.getContext());
2168 // Allocate shadow area for Win64
2170 CCInfo.AllocateStack(32, 8);
2173 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2175 // Get a count of how many bytes are to be pushed on the stack.
2176 unsigned NumBytes = CCInfo.getNextStackOffset();
2178 // This is a sibcall. The memory operands are available in caller's
2179 // own caller's stack.
2181 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2182 IsTailCallConvention(CallConv))
2183 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2186 if (isTailCall && !IsSibcall) {
2187 // Lower arguments at fp - stackoffset + fpdiff.
2188 unsigned NumBytesCallerPushed =
2189 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2190 FPDiff = NumBytesCallerPushed - NumBytes;
2192 // Set the delta of movement of the returnaddr stackslot.
2193 // But only set if delta is greater than previous delta.
2194 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2195 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2199 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2201 SDValue RetAddrFrIdx;
2202 // Load return address for tail calls.
2203 if (isTailCall && FPDiff)
2204 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2205 Is64Bit, FPDiff, dl);
2207 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2208 SmallVector<SDValue, 8> MemOpChains;
2211 // Walk the register/memloc assignments, inserting copies/loads. In the case
2212 // of tail call optimization arguments are handle later.
2213 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2214 CCValAssign &VA = ArgLocs[i];
2215 EVT RegVT = VA.getLocVT();
2216 SDValue Arg = OutVals[i];
2217 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2218 bool isByVal = Flags.isByVal();
2220 // Promote the value if needed.
2221 switch (VA.getLocInfo()) {
2222 default: llvm_unreachable("Unknown loc info!");
2223 case CCValAssign::Full: break;
2224 case CCValAssign::SExt:
2225 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2227 case CCValAssign::ZExt:
2228 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2230 case CCValAssign::AExt:
2231 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2232 // Special case: passing MMX values in XMM registers.
2233 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2234 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2235 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2237 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2239 case CCValAssign::BCvt:
2240 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2242 case CCValAssign::Indirect: {
2243 // Store the argument.
2244 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2245 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2246 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2247 MachinePointerInfo::getFixedStack(FI),
2254 if (VA.isRegLoc()) {
2255 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2256 if (isVarArg && IsWin64) {
2257 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2258 // shadow reg if callee is a varargs function.
2259 unsigned ShadowReg = 0;
2260 switch (VA.getLocReg()) {
2261 case X86::XMM0: ShadowReg = X86::RCX; break;
2262 case X86::XMM1: ShadowReg = X86::RDX; break;
2263 case X86::XMM2: ShadowReg = X86::R8; break;
2264 case X86::XMM3: ShadowReg = X86::R9; break;
2267 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2269 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2270 assert(VA.isMemLoc());
2271 if (StackPtr.getNode() == 0)
2272 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2273 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2274 dl, DAG, VA, Flags));
2278 if (!MemOpChains.empty())
2279 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2280 &MemOpChains[0], MemOpChains.size());
2282 // Build a sequence of copy-to-reg nodes chained together with token chain
2283 // and flag operands which copy the outgoing args into registers.
2285 // Tail call byval lowering might overwrite argument registers so in case of
2286 // tail call optimization the copies to registers are lowered later.
2288 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2289 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2290 RegsToPass[i].second, InFlag);
2291 InFlag = Chain.getValue(1);
2294 if (Subtarget->isPICStyleGOT()) {
2295 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2298 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2299 DAG.getNode(X86ISD::GlobalBaseReg,
2300 DebugLoc(), getPointerTy()),
2302 InFlag = Chain.getValue(1);
2304 // If we are tail calling and generating PIC/GOT style code load the
2305 // address of the callee into ECX. The value in ecx is used as target of
2306 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2307 // for tail calls on PIC/GOT architectures. Normally we would just put the
2308 // address of GOT into ebx and then call target@PLT. But for tail calls
2309 // ebx would be restored (since ebx is callee saved) before jumping to the
2312 // Note: The actual moving to ECX is done further down.
2313 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2314 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2315 !G->getGlobal()->hasProtectedVisibility())
2316 Callee = LowerGlobalAddress(Callee, DAG);
2317 else if (isa<ExternalSymbolSDNode>(Callee))
2318 Callee = LowerExternalSymbol(Callee, DAG);
2322 if (Is64Bit && isVarArg && !IsWin64) {
2323 // From AMD64 ABI document:
2324 // For calls that may call functions that use varargs or stdargs
2325 // (prototype-less calls or calls to functions containing ellipsis (...) in
2326 // the declaration) %al is used as hidden argument to specify the number
2327 // of SSE registers used. The contents of %al do not need to match exactly
2328 // the number of registers, but must be an ubound on the number of SSE
2329 // registers used and is in the range 0 - 8 inclusive.
2331 // Count the number of XMM registers allocated.
2332 static const uint16_t XMMArgRegs[] = {
2333 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2334 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2336 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2337 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2338 && "SSE registers cannot be used when SSE is disabled");
2340 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2341 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2342 InFlag = Chain.getValue(1);
2346 // For tail calls lower the arguments to the 'real' stack slot.
2348 // Force all the incoming stack arguments to be loaded from the stack
2349 // before any new outgoing arguments are stored to the stack, because the
2350 // outgoing stack slots may alias the incoming argument stack slots, and
2351 // the alias isn't otherwise explicit. This is slightly more conservative
2352 // than necessary, because it means that each store effectively depends
2353 // on every argument instead of just those arguments it would clobber.
2354 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2356 SmallVector<SDValue, 8> MemOpChains2;
2359 // Do not flag preceding copytoreg stuff together with the following stuff.
2361 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2362 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2363 CCValAssign &VA = ArgLocs[i];
2366 assert(VA.isMemLoc());
2367 SDValue Arg = OutVals[i];
2368 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2369 // Create frame index.
2370 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2371 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2372 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2373 FIN = DAG.getFrameIndex(FI, getPointerTy());
2375 if (Flags.isByVal()) {
2376 // Copy relative to framepointer.
2377 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2378 if (StackPtr.getNode() == 0)
2379 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2381 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2383 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2387 // Store relative to framepointer.
2388 MemOpChains2.push_back(
2389 DAG.getStore(ArgChain, dl, Arg, FIN,
2390 MachinePointerInfo::getFixedStack(FI),
2396 if (!MemOpChains2.empty())
2397 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2398 &MemOpChains2[0], MemOpChains2.size());
2400 // Copy arguments to their registers.
2401 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2402 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2403 RegsToPass[i].second, InFlag);
2404 InFlag = Chain.getValue(1);
2408 // Store the return address to the appropriate stack slot.
2409 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2413 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2414 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2415 // In the 64-bit large code model, we have to make all calls
2416 // through a register, since the call instruction's 32-bit
2417 // pc-relative offset may not be large enough to hold the whole
2419 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2420 // If the callee is a GlobalAddress node (quite common, every direct call
2421 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2424 // We should use extra load for direct calls to dllimported functions in
2426 const GlobalValue *GV = G->getGlobal();
2427 if (!GV->hasDLLImportLinkage()) {
2428 unsigned char OpFlags = 0;
2429 bool ExtraLoad = false;
2430 unsigned WrapperKind = ISD::DELETED_NODE;
2432 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2433 // external symbols most go through the PLT in PIC mode. If the symbol
2434 // has hidden or protected visibility, or if it is static or local, then
2435 // we don't need to use the PLT - we can directly call it.
2436 if (Subtarget->isTargetELF() &&
2437 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2438 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2439 OpFlags = X86II::MO_PLT;
2440 } else if (Subtarget->isPICStyleStubAny() &&
2441 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2442 (!Subtarget->getTargetTriple().isMacOSX() ||
2443 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2444 // PC-relative references to external symbols should go through $stub,
2445 // unless we're building with the leopard linker or later, which
2446 // automatically synthesizes these stubs.
2447 OpFlags = X86II::MO_DARWIN_STUB;
2448 } else if (Subtarget->isPICStyleRIPRel() &&
2449 isa<Function>(GV) &&
2450 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2451 // If the function is marked as non-lazy, generate an indirect call
2452 // which loads from the GOT directly. This avoids runtime overhead
2453 // at the cost of eager binding (and one extra byte of encoding).
2454 OpFlags = X86II::MO_GOTPCREL;
2455 WrapperKind = X86ISD::WrapperRIP;
2459 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2460 G->getOffset(), OpFlags);
2462 // Add a wrapper if needed.
2463 if (WrapperKind != ISD::DELETED_NODE)
2464 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2465 // Add extra indirection if needed.
2467 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2468 MachinePointerInfo::getGOT(),
2469 false, false, false, 0);
2471 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2472 unsigned char OpFlags = 0;
2474 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2475 // external symbols should go through the PLT.
2476 if (Subtarget->isTargetELF() &&
2477 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2478 OpFlags = X86II::MO_PLT;
2479 } else if (Subtarget->isPICStyleStubAny() &&
2480 (!Subtarget->getTargetTriple().isMacOSX() ||
2481 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2482 // PC-relative references to external symbols should go through $stub,
2483 // unless we're building with the leopard linker or later, which
2484 // automatically synthesizes these stubs.
2485 OpFlags = X86II::MO_DARWIN_STUB;
2488 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2492 // Returns a chain & a flag for retval copy to use.
2493 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2494 SmallVector<SDValue, 8> Ops;
2496 if (!IsSibcall && isTailCall) {
2497 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2498 DAG.getIntPtrConstant(0, true), InFlag);
2499 InFlag = Chain.getValue(1);
2502 Ops.push_back(Chain);
2503 Ops.push_back(Callee);
2506 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2508 // Add argument registers to the end of the list so that they are known live
2510 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2511 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2512 RegsToPass[i].second.getValueType()));
2514 // Add an implicit use GOT pointer in EBX.
2515 if (!isTailCall && Subtarget->isPICStyleGOT())
2516 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2518 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2519 if (Is64Bit && isVarArg && !IsWin64)
2520 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2522 // Add a register mask operand representing the call-preserved registers.
2523 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2524 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2525 assert(Mask && "Missing call preserved mask for calling convention");
2526 Ops.push_back(DAG.getRegisterMask(Mask));
2528 if (InFlag.getNode())
2529 Ops.push_back(InFlag);
2533 //// If this is the first return lowered for this function, add the regs
2534 //// to the liveout set for the function.
2535 // This isn't right, although it's probably harmless on x86; liveouts
2536 // should be computed from returns not tail calls. Consider a void
2537 // function making a tail call to a function returning int.
2538 return DAG.getNode(X86ISD::TC_RETURN, dl,
2539 NodeTys, &Ops[0], Ops.size());
2542 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2543 InFlag = Chain.getValue(1);
2545 // Create the CALLSEQ_END node.
2546 unsigned NumBytesForCalleeToPush;
2547 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2548 getTargetMachine().Options.GuaranteedTailCallOpt))
2549 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2550 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2552 // If this is a call to a struct-return function, the callee
2553 // pops the hidden struct pointer, so we have to push it back.
2554 // This is common for Darwin/X86, Linux & Mingw32 targets.
2555 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2556 NumBytesForCalleeToPush = 4;
2558 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2560 // Returns a flag for retval copy to use.
2562 Chain = DAG.getCALLSEQ_END(Chain,
2563 DAG.getIntPtrConstant(NumBytes, true),
2564 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2567 InFlag = Chain.getValue(1);
2570 // Handle result values, copying them out of physregs into vregs that we
2572 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2573 Ins, dl, DAG, InVals);
2577 //===----------------------------------------------------------------------===//
2578 // Fast Calling Convention (tail call) implementation
2579 //===----------------------------------------------------------------------===//
2581 // Like std call, callee cleans arguments, convention except that ECX is
2582 // reserved for storing the tail called function address. Only 2 registers are
2583 // free for argument passing (inreg). Tail call optimization is performed
2585 // * tailcallopt is enabled
2586 // * caller/callee are fastcc
2587 // On X86_64 architecture with GOT-style position independent code only local
2588 // (within module) calls are supported at the moment.
2589 // To keep the stack aligned according to platform abi the function
2590 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2591 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2592 // If a tail called function callee has more arguments than the caller the
2593 // caller needs to make sure that there is room to move the RETADDR to. This is
2594 // achieved by reserving an area the size of the argument delta right after the
2595 // original REtADDR, but before the saved framepointer or the spilled registers
2596 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2608 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2609 /// for a 16 byte align requirement.
2611 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2612 SelectionDAG& DAG) const {
2613 MachineFunction &MF = DAG.getMachineFunction();
2614 const TargetMachine &TM = MF.getTarget();
2615 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2616 unsigned StackAlignment = TFI.getStackAlignment();
2617 uint64_t AlignMask = StackAlignment - 1;
2618 int64_t Offset = StackSize;
2619 uint64_t SlotSize = TD->getPointerSize();
2620 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2621 // Number smaller than 12 so just add the difference.
2622 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2624 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2625 Offset = ((~AlignMask) & Offset) + StackAlignment +
2626 (StackAlignment-SlotSize);
2631 /// MatchingStackOffset - Return true if the given stack call argument is
2632 /// already available in the same position (relatively) of the caller's
2633 /// incoming argument stack.
2635 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2636 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2637 const X86InstrInfo *TII) {
2638 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2640 if (Arg.getOpcode() == ISD::CopyFromReg) {
2641 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2642 if (!TargetRegisterInfo::isVirtualRegister(VR))
2644 MachineInstr *Def = MRI->getVRegDef(VR);
2647 if (!Flags.isByVal()) {
2648 if (!TII->isLoadFromStackSlot(Def, FI))
2651 unsigned Opcode = Def->getOpcode();
2652 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2653 Def->getOperand(1).isFI()) {
2654 FI = Def->getOperand(1).getIndex();
2655 Bytes = Flags.getByValSize();
2659 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2660 if (Flags.isByVal())
2661 // ByVal argument is passed in as a pointer but it's now being
2662 // dereferenced. e.g.
2663 // define @foo(%struct.X* %A) {
2664 // tail call @bar(%struct.X* byval %A)
2667 SDValue Ptr = Ld->getBasePtr();
2668 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2671 FI = FINode->getIndex();
2672 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2673 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2674 FI = FINode->getIndex();
2675 Bytes = Flags.getByValSize();
2679 assert(FI != INT_MAX);
2680 if (!MFI->isFixedObjectIndex(FI))
2682 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2685 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2686 /// for tail call optimization. Targets which want to do tail call
2687 /// optimization should implement this function.
2689 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2690 CallingConv::ID CalleeCC,
2692 bool isCalleeStructRet,
2693 bool isCallerStructRet,
2694 const SmallVectorImpl<ISD::OutputArg> &Outs,
2695 const SmallVectorImpl<SDValue> &OutVals,
2696 const SmallVectorImpl<ISD::InputArg> &Ins,
2697 SelectionDAG& DAG) const {
2698 if (!IsTailCallConvention(CalleeCC) &&
2699 CalleeCC != CallingConv::C)
2702 // If -tailcallopt is specified, make fastcc functions tail-callable.
2703 const MachineFunction &MF = DAG.getMachineFunction();
2704 const Function *CallerF = DAG.getMachineFunction().getFunction();
2705 CallingConv::ID CallerCC = CallerF->getCallingConv();
2706 bool CCMatch = CallerCC == CalleeCC;
2708 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2709 if (IsTailCallConvention(CalleeCC) && CCMatch)
2714 // Look for obvious safe cases to perform tail call optimization that do not
2715 // require ABI changes. This is what gcc calls sibcall.
2717 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2718 // emit a special epilogue.
2719 if (RegInfo->needsStackRealignment(MF))
2722 // Also avoid sibcall optimization if either caller or callee uses struct
2723 // return semantics.
2724 if (isCalleeStructRet || isCallerStructRet)
2727 // An stdcall caller is expected to clean up its arguments; the callee
2728 // isn't going to do that.
2729 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2732 // Do not sibcall optimize vararg calls unless all arguments are passed via
2734 if (isVarArg && !Outs.empty()) {
2736 // Optimizing for varargs on Win64 is unlikely to be safe without
2737 // additional testing.
2738 if (Subtarget->isTargetWin64())
2741 SmallVector<CCValAssign, 16> ArgLocs;
2742 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2743 getTargetMachine(), ArgLocs, *DAG.getContext());
2745 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2746 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2747 if (!ArgLocs[i].isRegLoc())
2751 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2752 // stack. Therefore, if it's not used by the call it is not safe to optimize
2753 // this into a sibcall.
2754 bool Unused = false;
2755 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2762 SmallVector<CCValAssign, 16> RVLocs;
2763 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2764 getTargetMachine(), RVLocs, *DAG.getContext());
2765 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2766 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2767 CCValAssign &VA = RVLocs[i];
2768 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2773 // If the calling conventions do not match, then we'd better make sure the
2774 // results are returned in the same way as what the caller expects.
2776 SmallVector<CCValAssign, 16> RVLocs1;
2777 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2778 getTargetMachine(), RVLocs1, *DAG.getContext());
2779 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2781 SmallVector<CCValAssign, 16> RVLocs2;
2782 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2783 getTargetMachine(), RVLocs2, *DAG.getContext());
2784 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2786 if (RVLocs1.size() != RVLocs2.size())
2788 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2789 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2791 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2793 if (RVLocs1[i].isRegLoc()) {
2794 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2797 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2803 // If the callee takes no arguments then go on to check the results of the
2805 if (!Outs.empty()) {
2806 // Check if stack adjustment is needed. For now, do not do this if any
2807 // argument is passed on the stack.
2808 SmallVector<CCValAssign, 16> ArgLocs;
2809 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2810 getTargetMachine(), ArgLocs, *DAG.getContext());
2812 // Allocate shadow area for Win64
2813 if (Subtarget->isTargetWin64()) {
2814 CCInfo.AllocateStack(32, 8);
2817 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2818 if (CCInfo.getNextStackOffset()) {
2819 MachineFunction &MF = DAG.getMachineFunction();
2820 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2823 // Check if the arguments are already laid out in the right way as
2824 // the caller's fixed stack objects.
2825 MachineFrameInfo *MFI = MF.getFrameInfo();
2826 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2827 const X86InstrInfo *TII =
2828 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2830 CCValAssign &VA = ArgLocs[i];
2831 SDValue Arg = OutVals[i];
2832 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2833 if (VA.getLocInfo() == CCValAssign::Indirect)
2835 if (!VA.isRegLoc()) {
2836 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2843 // If the tailcall address may be in a register, then make sure it's
2844 // possible to register allocate for it. In 32-bit, the call address can
2845 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2846 // callee-saved registers are restored. These happen to be the same
2847 // registers used to pass 'inreg' arguments so watch out for those.
2848 if (!Subtarget->is64Bit() &&
2849 !isa<GlobalAddressSDNode>(Callee) &&
2850 !isa<ExternalSymbolSDNode>(Callee)) {
2851 unsigned NumInRegs = 0;
2852 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2853 CCValAssign &VA = ArgLocs[i];
2856 unsigned Reg = VA.getLocReg();
2859 case X86::EAX: case X86::EDX: case X86::ECX:
2860 if (++NumInRegs == 3)
2872 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2873 return X86::createFastISel(funcInfo);
2877 //===----------------------------------------------------------------------===//
2878 // Other Lowering Hooks
2879 //===----------------------------------------------------------------------===//
2881 static bool MayFoldLoad(SDValue Op) {
2882 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2885 static bool MayFoldIntoStore(SDValue Op) {
2886 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2889 static bool isTargetShuffle(unsigned Opcode) {
2891 default: return false;
2892 case X86ISD::PSHUFD:
2893 case X86ISD::PSHUFHW:
2894 case X86ISD::PSHUFLW:
2896 case X86ISD::PALIGN:
2897 case X86ISD::MOVLHPS:
2898 case X86ISD::MOVLHPD:
2899 case X86ISD::MOVHLPS:
2900 case X86ISD::MOVLPS:
2901 case X86ISD::MOVLPD:
2902 case X86ISD::MOVSHDUP:
2903 case X86ISD::MOVSLDUP:
2904 case X86ISD::MOVDDUP:
2907 case X86ISD::UNPCKL:
2908 case X86ISD::UNPCKH:
2909 case X86ISD::VPERMILP:
2910 case X86ISD::VPERM2X128:
2915 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2916 SDValue V1, SelectionDAG &DAG) {
2918 default: llvm_unreachable("Unknown x86 shuffle node");
2919 case X86ISD::MOVSHDUP:
2920 case X86ISD::MOVSLDUP:
2921 case X86ISD::MOVDDUP:
2922 return DAG.getNode(Opc, dl, VT, V1);
2926 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2927 SDValue V1, unsigned TargetMask,
2928 SelectionDAG &DAG) {
2930 default: llvm_unreachable("Unknown x86 shuffle node");
2931 case X86ISD::PSHUFD:
2932 case X86ISD::PSHUFHW:
2933 case X86ISD::PSHUFLW:
2934 case X86ISD::VPERMILP:
2935 case X86ISD::VPERMI:
2936 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2940 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2941 SDValue V1, SDValue V2, unsigned TargetMask,
2942 SelectionDAG &DAG) {
2944 default: llvm_unreachable("Unknown x86 shuffle node");
2945 case X86ISD::PALIGN:
2947 case X86ISD::VPERM2X128:
2948 return DAG.getNode(Opc, dl, VT, V1, V2,
2949 DAG.getConstant(TargetMask, MVT::i8));
2953 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2954 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2956 default: llvm_unreachable("Unknown x86 shuffle node");
2957 case X86ISD::MOVLHPS:
2958 case X86ISD::MOVLHPD:
2959 case X86ISD::MOVHLPS:
2960 case X86ISD::MOVLPS:
2961 case X86ISD::MOVLPD:
2964 case X86ISD::UNPCKL:
2965 case X86ISD::UNPCKH:
2966 return DAG.getNode(Opc, dl, VT, V1, V2);
2970 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2971 MachineFunction &MF = DAG.getMachineFunction();
2972 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2973 int ReturnAddrIndex = FuncInfo->getRAIndex();
2975 if (ReturnAddrIndex == 0) {
2976 // Set up a frame object for the return address.
2977 uint64_t SlotSize = TD->getPointerSize();
2978 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2980 FuncInfo->setRAIndex(ReturnAddrIndex);
2983 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2987 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2988 bool hasSymbolicDisplacement) {
2989 // Offset should fit into 32 bit immediate field.
2990 if (!isInt<32>(Offset))
2993 // If we don't have a symbolic displacement - we don't have any extra
2995 if (!hasSymbolicDisplacement)
2998 // FIXME: Some tweaks might be needed for medium code model.
2999 if (M != CodeModel::Small && M != CodeModel::Kernel)
3002 // For small code model we assume that latest object is 16MB before end of 31
3003 // bits boundary. We may also accept pretty large negative constants knowing
3004 // that all objects are in the positive half of address space.
3005 if (M == CodeModel::Small && Offset < 16*1024*1024)
3008 // For kernel code model we know that all object resist in the negative half
3009 // of 32bits address space. We may not accept negative offsets, since they may
3010 // be just off and we may accept pretty large positive ones.
3011 if (M == CodeModel::Kernel && Offset > 0)
3017 /// isCalleePop - Determines whether the callee is required to pop its
3018 /// own arguments. Callee pop is necessary to support tail calls.
3019 bool X86::isCalleePop(CallingConv::ID CallingConv,
3020 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3024 switch (CallingConv) {
3027 case CallingConv::X86_StdCall:
3029 case CallingConv::X86_FastCall:
3031 case CallingConv::X86_ThisCall:
3033 case CallingConv::Fast:
3035 case CallingConv::GHC:
3040 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3041 /// specific condition code, returning the condition code and the LHS/RHS of the
3042 /// comparison to make.
3043 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3044 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3046 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3047 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3048 // X > -1 -> X == 0, jump !sign.
3049 RHS = DAG.getConstant(0, RHS.getValueType());
3050 return X86::COND_NS;
3051 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3052 // X < 0 -> X == 0, jump on sign.
3054 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3056 RHS = DAG.getConstant(0, RHS.getValueType());
3057 return X86::COND_LE;
3061 switch (SetCCOpcode) {
3062 default: llvm_unreachable("Invalid integer condition!");
3063 case ISD::SETEQ: return X86::COND_E;
3064 case ISD::SETGT: return X86::COND_G;
3065 case ISD::SETGE: return X86::COND_GE;
3066 case ISD::SETLT: return X86::COND_L;
3067 case ISD::SETLE: return X86::COND_LE;
3068 case ISD::SETNE: return X86::COND_NE;
3069 case ISD::SETULT: return X86::COND_B;
3070 case ISD::SETUGT: return X86::COND_A;
3071 case ISD::SETULE: return X86::COND_BE;
3072 case ISD::SETUGE: return X86::COND_AE;
3076 // First determine if it is required or is profitable to flip the operands.
3078 // If LHS is a foldable load, but RHS is not, flip the condition.
3079 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3080 !ISD::isNON_EXTLoad(RHS.getNode())) {
3081 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3082 std::swap(LHS, RHS);
3085 switch (SetCCOpcode) {
3091 std::swap(LHS, RHS);
3095 // On a floating point condition, the flags are set as follows:
3097 // 0 | 0 | 0 | X > Y
3098 // 0 | 0 | 1 | X < Y
3099 // 1 | 0 | 0 | X == Y
3100 // 1 | 1 | 1 | unordered
3101 switch (SetCCOpcode) {
3102 default: llvm_unreachable("Condcode should be pre-legalized away");
3104 case ISD::SETEQ: return X86::COND_E;
3105 case ISD::SETOLT: // flipped
3107 case ISD::SETGT: return X86::COND_A;
3108 case ISD::SETOLE: // flipped
3110 case ISD::SETGE: return X86::COND_AE;
3111 case ISD::SETUGT: // flipped
3113 case ISD::SETLT: return X86::COND_B;
3114 case ISD::SETUGE: // flipped
3116 case ISD::SETLE: return X86::COND_BE;
3118 case ISD::SETNE: return X86::COND_NE;
3119 case ISD::SETUO: return X86::COND_P;
3120 case ISD::SETO: return X86::COND_NP;
3122 case ISD::SETUNE: return X86::COND_INVALID;
3126 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3127 /// code. Current x86 isa includes the following FP cmov instructions:
3128 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3129 static bool hasFPCMov(unsigned X86CC) {
3145 /// isFPImmLegal - Returns true if the target can instruction select the
3146 /// specified FP immediate natively. If false, the legalizer will
3147 /// materialize the FP immediate as a load from a constant pool.
3148 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3149 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3150 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3156 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3157 /// the specified range (L, H].
3158 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3159 return (Val < 0) || (Val >= Low && Val < Hi);
3162 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3163 /// specified value.
3164 static bool isUndefOrEqual(int Val, int CmpVal) {
3165 if (Val < 0 || Val == CmpVal)
3170 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3171 /// from position Pos and ending in Pos+Size, falls within the specified
3172 /// sequential range (L, L+Pos]. or is undef.
3173 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3174 int Pos, int Size, int Low) {
3175 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3176 if (!isUndefOrEqual(Mask[i], Low))
3181 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3182 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3183 /// the second operand.
3184 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3185 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3186 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3187 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3188 return (Mask[0] < 2 && Mask[1] < 2);
3192 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3193 /// is suitable for input to PSHUFHW.
3194 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3195 if (VT != MVT::v8i16)
3198 // Lower quadword copied in order or undef.
3199 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3202 // Upper quadword shuffled.
3203 for (unsigned i = 4; i != 8; ++i)
3204 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3210 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3211 /// is suitable for input to PSHUFLW.
3212 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3213 if (VT != MVT::v8i16)
3216 // Upper quadword copied in order.
3217 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3220 // Lower quadword shuffled.
3221 for (unsigned i = 0; i != 4; ++i)
3228 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3229 /// is suitable for input to PALIGNR.
3230 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3231 const X86Subtarget *Subtarget) {
3232 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3233 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3236 unsigned NumElts = VT.getVectorNumElements();
3237 unsigned NumLanes = VT.getSizeInBits()/128;
3238 unsigned NumLaneElts = NumElts/NumLanes;
3240 // Do not handle 64-bit element shuffles with palignr.
3241 if (NumLaneElts == 2)
3244 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3246 for (i = 0; i != NumLaneElts; ++i) {
3251 // Lane is all undef, go to next lane
3252 if (i == NumLaneElts)
3255 int Start = Mask[i+l];
3257 // Make sure its in this lane in one of the sources
3258 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3259 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3262 // If not lane 0, then we must match lane 0
3263 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3266 // Correct second source to be contiguous with first source
3267 if (Start >= (int)NumElts)
3268 Start -= NumElts - NumLaneElts;
3270 // Make sure we're shifting in the right direction.
3271 if (Start <= (int)(i+l))
3276 // Check the rest of the elements to see if they are consecutive.
3277 for (++i; i != NumLaneElts; ++i) {
3278 int Idx = Mask[i+l];
3280 // Make sure its in this lane
3281 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3282 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3285 // If not lane 0, then we must match lane 0
3286 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3289 if (Idx >= (int)NumElts)
3290 Idx -= NumElts - NumLaneElts;
3292 if (!isUndefOrEqual(Idx, Start+i))
3301 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3302 /// the two vector operands have swapped position.
3303 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3304 unsigned NumElems) {
3305 for (unsigned i = 0; i != NumElems; ++i) {
3309 else if (idx < (int)NumElems)
3310 Mask[i] = idx + NumElems;
3312 Mask[i] = idx - NumElems;
3316 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3317 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3318 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3319 /// reverse of what x86 shuffles want.
3320 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3321 bool Commuted = false) {
3322 if (!HasAVX && VT.getSizeInBits() == 256)
3325 unsigned NumElems = VT.getVectorNumElements();
3326 unsigned NumLanes = VT.getSizeInBits()/128;
3327 unsigned NumLaneElems = NumElems/NumLanes;
3329 if (NumLaneElems != 2 && NumLaneElems != 4)
3332 // VSHUFPSY divides the resulting vector into 4 chunks.
3333 // The sources are also splitted into 4 chunks, and each destination
3334 // chunk must come from a different source chunk.
3336 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3337 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3339 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3340 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3342 // VSHUFPDY divides the resulting vector into 4 chunks.
3343 // The sources are also splitted into 4 chunks, and each destination
3344 // chunk must come from a different source chunk.
3346 // SRC1 => X3 X2 X1 X0
3347 // SRC2 => Y3 Y2 Y1 Y0
3349 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3351 unsigned HalfLaneElems = NumLaneElems/2;
3352 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3353 for (unsigned i = 0; i != NumLaneElems; ++i) {
3354 int Idx = Mask[i+l];
3355 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3356 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3358 // For VSHUFPSY, the mask of the second half must be the same as the
3359 // first but with the appropriate offsets. This works in the same way as
3360 // VPERMILPS works with masks.
3361 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3363 if (!isUndefOrEqual(Idx, Mask[i]+l))
3371 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3372 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3373 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3374 unsigned NumElems = VT.getVectorNumElements();
3376 if (VT.getSizeInBits() != 128)
3382 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3383 return isUndefOrEqual(Mask[0], 6) &&
3384 isUndefOrEqual(Mask[1], 7) &&
3385 isUndefOrEqual(Mask[2], 2) &&
3386 isUndefOrEqual(Mask[3], 3);
3389 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3390 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3392 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3393 unsigned NumElems = VT.getVectorNumElements();
3395 if (VT.getSizeInBits() != 128)
3401 return isUndefOrEqual(Mask[0], 2) &&
3402 isUndefOrEqual(Mask[1], 3) &&
3403 isUndefOrEqual(Mask[2], 2) &&
3404 isUndefOrEqual(Mask[3], 3);
3407 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3408 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3409 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3410 if (VT.getSizeInBits() != 128)
3413 unsigned NumElems = VT.getVectorNumElements();
3415 if (NumElems != 2 && NumElems != 4)
3418 for (unsigned i = 0; i != NumElems/2; ++i)
3419 if (!isUndefOrEqual(Mask[i], i + NumElems))
3422 for (unsigned i = NumElems/2; i != NumElems; ++i)
3423 if (!isUndefOrEqual(Mask[i], i))
3429 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3430 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3431 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3432 unsigned NumElems = VT.getVectorNumElements();
3434 if ((NumElems != 2 && NumElems != 4)
3435 || VT.getSizeInBits() > 128)
3438 for (unsigned i = 0; i != NumElems/2; ++i)
3439 if (!isUndefOrEqual(Mask[i], i))
3442 for (unsigned i = 0; i != NumElems/2; ++i)
3443 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3449 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3450 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3451 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3452 bool HasAVX2, bool V2IsSplat = false) {
3453 unsigned NumElts = VT.getVectorNumElements();
3455 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3456 "Unsupported vector type for unpckh");
3458 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3459 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3462 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3463 // independently on 128-bit lanes.
3464 unsigned NumLanes = VT.getSizeInBits()/128;
3465 unsigned NumLaneElts = NumElts/NumLanes;
3467 for (unsigned l = 0; l != NumLanes; ++l) {
3468 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3469 i != (l+1)*NumLaneElts;
3472 int BitI1 = Mask[i+1];
3473 if (!isUndefOrEqual(BitI, j))
3476 if (!isUndefOrEqual(BitI1, NumElts))
3479 if (!isUndefOrEqual(BitI1, j + NumElts))
3488 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3489 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3490 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3491 bool HasAVX2, bool V2IsSplat = false) {
3492 unsigned NumElts = VT.getVectorNumElements();
3494 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3495 "Unsupported vector type for unpckh");
3497 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3498 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3501 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3502 // independently on 128-bit lanes.
3503 unsigned NumLanes = VT.getSizeInBits()/128;
3504 unsigned NumLaneElts = NumElts/NumLanes;
3506 for (unsigned l = 0; l != NumLanes; ++l) {
3507 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3508 i != (l+1)*NumLaneElts; i += 2, ++j) {
3510 int BitI1 = Mask[i+1];
3511 if (!isUndefOrEqual(BitI, j))
3514 if (isUndefOrEqual(BitI1, NumElts))
3517 if (!isUndefOrEqual(BitI1, j+NumElts))
3525 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3526 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3528 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3530 unsigned NumElts = VT.getVectorNumElements();
3532 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3533 "Unsupported vector type for unpckh");
3535 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3536 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3539 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3540 // FIXME: Need a better way to get rid of this, there's no latency difference
3541 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3542 // the former later. We should also remove the "_undef" special mask.
3543 if (NumElts == 4 && VT.getSizeInBits() == 256)
3546 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3547 // independently on 128-bit lanes.
3548 unsigned NumLanes = VT.getSizeInBits()/128;
3549 unsigned NumLaneElts = NumElts/NumLanes;
3551 for (unsigned l = 0; l != NumLanes; ++l) {
3552 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3553 i != (l+1)*NumLaneElts;
3556 int BitI1 = Mask[i+1];
3558 if (!isUndefOrEqual(BitI, j))
3560 if (!isUndefOrEqual(BitI1, j))
3568 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3569 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3571 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3572 unsigned NumElts = VT.getVectorNumElements();
3574 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3575 "Unsupported vector type for unpckh");
3577 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3578 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3581 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3582 // independently on 128-bit lanes.
3583 unsigned NumLanes = VT.getSizeInBits()/128;
3584 unsigned NumLaneElts = NumElts/NumLanes;
3586 for (unsigned l = 0; l != NumLanes; ++l) {
3587 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3588 i != (l+1)*NumLaneElts; i += 2, ++j) {
3590 int BitI1 = Mask[i+1];
3591 if (!isUndefOrEqual(BitI, j))
3593 if (!isUndefOrEqual(BitI1, j))
3600 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3601 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3602 /// MOVSD, and MOVD, i.e. setting the lowest element.
3603 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3604 if (VT.getVectorElementType().getSizeInBits() < 32)
3606 if (VT.getSizeInBits() == 256)
3609 unsigned NumElts = VT.getVectorNumElements();
3611 if (!isUndefOrEqual(Mask[0], NumElts))
3614 for (unsigned i = 1; i != NumElts; ++i)
3615 if (!isUndefOrEqual(Mask[i], i))
3621 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3622 /// as permutations between 128-bit chunks or halves. As an example: this
3624 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3625 /// The first half comes from the second half of V1 and the second half from the
3626 /// the second half of V2.
3627 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3628 if (!HasAVX || VT.getSizeInBits() != 256)
3631 // The shuffle result is divided into half A and half B. In total the two
3632 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3633 // B must come from C, D, E or F.
3634 unsigned HalfSize = VT.getVectorNumElements()/2;
3635 bool MatchA = false, MatchB = false;
3637 // Check if A comes from one of C, D, E, F.
3638 for (unsigned Half = 0; Half != 4; ++Half) {
3639 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3645 // Check if B comes from one of C, D, E, F.
3646 for (unsigned Half = 0; Half != 4; ++Half) {
3647 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3653 return MatchA && MatchB;
3656 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3657 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3658 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3659 EVT VT = SVOp->getValueType(0);
3661 unsigned HalfSize = VT.getVectorNumElements()/2;
3663 unsigned FstHalf = 0, SndHalf = 0;
3664 for (unsigned i = 0; i < HalfSize; ++i) {
3665 if (SVOp->getMaskElt(i) > 0) {
3666 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3670 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3671 if (SVOp->getMaskElt(i) > 0) {
3672 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3677 return (FstHalf | (SndHalf << 4));
3680 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3681 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3682 /// Note that VPERMIL mask matching is different depending whether theunderlying
3683 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3684 /// to the same elements of the low, but to the higher half of the source.
3685 /// In VPERMILPD the two lanes could be shuffled independently of each other
3686 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3687 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3691 unsigned NumElts = VT.getVectorNumElements();
3692 // Only match 256-bit with 32/64-bit types
3693 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3696 unsigned NumLanes = VT.getSizeInBits()/128;
3697 unsigned LaneSize = NumElts/NumLanes;
3698 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3699 for (unsigned i = 0; i != LaneSize; ++i) {
3700 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3702 if (NumElts != 8 || l == 0)
3704 // VPERMILPS handling
3707 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3715 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3716 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3717 /// element of vector 2 and the other elements to come from vector 1 in order.
3718 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3719 bool V2IsSplat = false, bool V2IsUndef = false) {
3720 unsigned NumOps = VT.getVectorNumElements();
3721 if (VT.getSizeInBits() == 256)
3723 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3726 if (!isUndefOrEqual(Mask[0], 0))
3729 for (unsigned i = 1; i != NumOps; ++i)
3730 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3731 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3732 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3738 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3739 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3740 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3741 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3742 const X86Subtarget *Subtarget) {
3743 if (!Subtarget->hasSSE3())
3746 unsigned NumElems = VT.getVectorNumElements();
3748 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3749 (VT.getSizeInBits() == 256 && NumElems != 8))
3752 // "i+1" is the value the indexed mask element must have
3753 for (unsigned i = 0; i != NumElems; i += 2)
3754 if (!isUndefOrEqual(Mask[i], i+1) ||
3755 !isUndefOrEqual(Mask[i+1], i+1))
3761 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3762 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3763 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3764 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3765 const X86Subtarget *Subtarget) {
3766 if (!Subtarget->hasSSE3())
3769 unsigned NumElems = VT.getVectorNumElements();
3771 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3772 (VT.getSizeInBits() == 256 && NumElems != 8))
3775 // "i" is the value the indexed mask element must have
3776 for (unsigned i = 0; i != NumElems; i += 2)
3777 if (!isUndefOrEqual(Mask[i], i) ||
3778 !isUndefOrEqual(Mask[i+1], i))
3784 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3785 /// specifies a shuffle of elements that is suitable for input to 256-bit
3786 /// version of MOVDDUP.
3787 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3788 unsigned NumElts = VT.getVectorNumElements();
3790 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3793 for (unsigned i = 0; i != NumElts/2; ++i)
3794 if (!isUndefOrEqual(Mask[i], 0))
3796 for (unsigned i = NumElts/2; i != NumElts; ++i)
3797 if (!isUndefOrEqual(Mask[i], NumElts/2))
3802 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3803 /// specifies a shuffle of elements that is suitable for input to 128-bit
3804 /// version of MOVDDUP.
3805 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3806 if (VT.getSizeInBits() != 128)
3809 unsigned e = VT.getVectorNumElements() / 2;
3810 for (unsigned i = 0; i != e; ++i)
3811 if (!isUndefOrEqual(Mask[i], i))
3813 for (unsigned i = 0; i != e; ++i)
3814 if (!isUndefOrEqual(Mask[e+i], i))
3819 /// isVEXTRACTF128Index - Return true if the specified
3820 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3821 /// suitable for input to VEXTRACTF128.
3822 bool X86::isVEXTRACTF128Index(SDNode *N) {
3823 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3826 // The index should be aligned on a 128-bit boundary.
3828 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3830 unsigned VL = N->getValueType(0).getVectorNumElements();
3831 unsigned VBits = N->getValueType(0).getSizeInBits();
3832 unsigned ElSize = VBits / VL;
3833 bool Result = (Index * ElSize) % 128 == 0;
3838 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3839 /// operand specifies a subvector insert that is suitable for input to
3841 bool X86::isVINSERTF128Index(SDNode *N) {
3842 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3845 // The index should be aligned on a 128-bit boundary.
3847 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3849 unsigned VL = N->getValueType(0).getVectorNumElements();
3850 unsigned VBits = N->getValueType(0).getSizeInBits();
3851 unsigned ElSize = VBits / VL;
3852 bool Result = (Index * ElSize) % 128 == 0;
3857 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3858 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3859 /// Handles 128-bit and 256-bit.
3860 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3861 EVT VT = N->getValueType(0);
3863 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3864 "Unsupported vector type for PSHUF/SHUFP");
3866 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3867 // independently on 128-bit lanes.
3868 unsigned NumElts = VT.getVectorNumElements();
3869 unsigned NumLanes = VT.getSizeInBits()/128;
3870 unsigned NumLaneElts = NumElts/NumLanes;
3872 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3873 "Only supports 2 or 4 elements per lane");
3875 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3877 for (unsigned i = 0; i != NumElts; ++i) {
3878 int Elt = N->getMaskElt(i);
3879 if (Elt < 0) continue;
3881 unsigned ShAmt = i << Shift;
3882 if (ShAmt >= 8) ShAmt -= 8;
3883 Mask |= Elt << ShAmt;
3889 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3890 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3891 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3893 // 8 nodes, but we only care about the last 4.
3894 for (unsigned i = 7; i >= 4; --i) {
3895 int Val = N->getMaskElt(i);
3904 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3905 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3906 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3908 // 8 nodes, but we only care about the first 4.
3909 for (int i = 3; i >= 0; --i) {
3910 int Val = N->getMaskElt(i);
3919 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3920 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3921 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3922 EVT VT = SVOp->getValueType(0);
3923 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3925 unsigned NumElts = VT.getVectorNumElements();
3926 unsigned NumLanes = VT.getSizeInBits()/128;
3927 unsigned NumLaneElts = NumElts/NumLanes;
3931 for (i = 0; i != NumElts; ++i) {
3932 Val = SVOp->getMaskElt(i);
3936 if (Val >= (int)NumElts)
3937 Val -= NumElts - NumLaneElts;
3939 assert(Val - i > 0 && "PALIGNR imm should be positive");
3940 return (Val - i) * EltSize;
3943 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3944 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3946 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3947 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3948 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3951 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3953 EVT VecVT = N->getOperand(0).getValueType();
3954 EVT ElVT = VecVT.getVectorElementType();
3956 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3957 return Index / NumElemsPerChunk;
3960 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3961 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3963 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3964 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3965 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3968 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3970 EVT VecVT = N->getValueType(0);
3971 EVT ElVT = VecVT.getVectorElementType();
3973 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3974 return Index / NumElemsPerChunk;
3977 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
3978 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
3979 /// Handles 256-bit.
3980 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
3981 EVT VT = N->getValueType(0);
3983 unsigned NumElts = VT.getVectorNumElements();
3985 assert((VT.is256BitVector() && NumElts == 4) &&
3986 "Unsupported vector type for VPERMQ/VPERMPD");
3989 for (unsigned i = 0; i != NumElts; ++i) {
3990 int Elt = N->getMaskElt(i);
3993 Mask |= Elt << (i*2);
3998 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4000 bool X86::isZeroNode(SDValue Elt) {
4001 return ((isa<ConstantSDNode>(Elt) &&
4002 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4003 (isa<ConstantFPSDNode>(Elt) &&
4004 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4007 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4008 /// their permute mask.
4009 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4010 SelectionDAG &DAG) {
4011 EVT VT = SVOp->getValueType(0);
4012 unsigned NumElems = VT.getVectorNumElements();
4013 SmallVector<int, 8> MaskVec;
4015 for (unsigned i = 0; i != NumElems; ++i) {
4016 int idx = SVOp->getMaskElt(i);
4018 MaskVec.push_back(idx);
4019 else if (idx < (int)NumElems)
4020 MaskVec.push_back(idx + NumElems);
4022 MaskVec.push_back(idx - NumElems);
4024 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4025 SVOp->getOperand(0), &MaskVec[0]);
4028 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4029 /// match movhlps. The lower half elements should come from upper half of
4030 /// V1 (and in order), and the upper half elements should come from the upper
4031 /// half of V2 (and in order).
4032 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4033 if (VT.getSizeInBits() != 128)
4035 if (VT.getVectorNumElements() != 4)
4037 for (unsigned i = 0, e = 2; i != e; ++i)
4038 if (!isUndefOrEqual(Mask[i], i+2))
4040 for (unsigned i = 2; i != 4; ++i)
4041 if (!isUndefOrEqual(Mask[i], i+4))
4046 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4047 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4049 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4050 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4052 N = N->getOperand(0).getNode();
4053 if (!ISD::isNON_EXTLoad(N))
4056 *LD = cast<LoadSDNode>(N);
4060 // Test whether the given value is a vector value which will be legalized
4062 static bool WillBeConstantPoolLoad(SDNode *N) {
4063 if (N->getOpcode() != ISD::BUILD_VECTOR)
4066 // Check for any non-constant elements.
4067 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4068 switch (N->getOperand(i).getNode()->getOpcode()) {
4070 case ISD::ConstantFP:
4077 // Vectors of all-zeros and all-ones are materialized with special
4078 // instructions rather than being loaded.
4079 return !ISD::isBuildVectorAllZeros(N) &&
4080 !ISD::isBuildVectorAllOnes(N);
4083 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4084 /// match movlp{s|d}. The lower half elements should come from lower half of
4085 /// V1 (and in order), and the upper half elements should come from the upper
4086 /// half of V2 (and in order). And since V1 will become the source of the
4087 /// MOVLP, it must be either a vector load or a scalar load to vector.
4088 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4089 ArrayRef<int> Mask, EVT VT) {
4090 if (VT.getSizeInBits() != 128)
4093 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4095 // Is V2 is a vector load, don't do this transformation. We will try to use
4096 // load folding shufps op.
4097 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4100 unsigned NumElems = VT.getVectorNumElements();
4102 if (NumElems != 2 && NumElems != 4)
4104 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4105 if (!isUndefOrEqual(Mask[i], i))
4107 for (unsigned i = NumElems/2; i != NumElems; ++i)
4108 if (!isUndefOrEqual(Mask[i], i+NumElems))
4113 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4115 static bool isSplatVector(SDNode *N) {
4116 if (N->getOpcode() != ISD::BUILD_VECTOR)
4119 SDValue SplatValue = N->getOperand(0);
4120 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4121 if (N->getOperand(i) != SplatValue)
4126 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4127 /// to an zero vector.
4128 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4129 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4130 SDValue V1 = N->getOperand(0);
4131 SDValue V2 = N->getOperand(1);
4132 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4133 for (unsigned i = 0; i != NumElems; ++i) {
4134 int Idx = N->getMaskElt(i);
4135 if (Idx >= (int)NumElems) {
4136 unsigned Opc = V2.getOpcode();
4137 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4139 if (Opc != ISD::BUILD_VECTOR ||
4140 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4142 } else if (Idx >= 0) {
4143 unsigned Opc = V1.getOpcode();
4144 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4146 if (Opc != ISD::BUILD_VECTOR ||
4147 !X86::isZeroNode(V1.getOperand(Idx)))
4154 /// getZeroVector - Returns a vector of specified type with all zero elements.
4156 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4157 SelectionDAG &DAG, DebugLoc dl) {
4158 assert(VT.isVector() && "Expected a vector type");
4160 // Always build SSE zero vectors as <4 x i32> bitcasted
4161 // to their dest type. This ensures they get CSE'd.
4163 if (VT.getSizeInBits() == 128) { // SSE
4164 if (Subtarget->hasSSE2()) { // SSE2
4165 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4166 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4168 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4169 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4171 } else if (VT.getSizeInBits() == 256) { // AVX
4172 if (Subtarget->hasAVX2()) { // AVX2
4173 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4174 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4175 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4177 // 256-bit logic and arithmetic instructions in AVX are all
4178 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4179 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4180 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4181 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4184 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4187 /// getOnesVector - Returns a vector of specified type with all bits set.
4188 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4189 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4190 /// Then bitcast to their original type, ensuring they get CSE'd.
4191 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4193 assert(VT.isVector() && "Expected a vector type");
4194 assert((VT.is128BitVector() || VT.is256BitVector())
4195 && "Expected a 128-bit or 256-bit vector type");
4197 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4199 if (VT.getSizeInBits() == 256) {
4200 if (HasAVX2) { // AVX2
4201 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4202 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4204 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4205 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4208 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4211 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4214 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4215 /// that point to V2 points to its first element.
4216 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4217 for (unsigned i = 0; i != NumElems; ++i) {
4218 if (Mask[i] > (int)NumElems) {
4224 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4225 /// operation of specified width.
4226 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4228 unsigned NumElems = VT.getVectorNumElements();
4229 SmallVector<int, 8> Mask;
4230 Mask.push_back(NumElems);
4231 for (unsigned i = 1; i != NumElems; ++i)
4233 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4236 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4237 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4239 unsigned NumElems = VT.getVectorNumElements();
4240 SmallVector<int, 8> Mask;
4241 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4243 Mask.push_back(i + NumElems);
4245 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4248 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4249 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4251 unsigned NumElems = VT.getVectorNumElements();
4252 unsigned Half = NumElems/2;
4253 SmallVector<int, 8> Mask;
4254 for (unsigned i = 0; i != Half; ++i) {
4255 Mask.push_back(i + Half);
4256 Mask.push_back(i + NumElems + Half);
4258 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4261 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4262 // a generic shuffle instruction because the target has no such instructions.
4263 // Generate shuffles which repeat i16 and i8 several times until they can be
4264 // represented by v4f32 and then be manipulated by target suported shuffles.
4265 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4266 EVT VT = V.getValueType();
4267 int NumElems = VT.getVectorNumElements();
4268 DebugLoc dl = V.getDebugLoc();
4270 while (NumElems > 4) {
4271 if (EltNo < NumElems/2) {
4272 V = getUnpackl(DAG, dl, VT, V, V);
4274 V = getUnpackh(DAG, dl, VT, V, V);
4275 EltNo -= NumElems/2;
4282 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4283 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4284 EVT VT = V.getValueType();
4285 DebugLoc dl = V.getDebugLoc();
4286 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4287 && "Vector size not supported");
4289 if (VT.getSizeInBits() == 128) {
4290 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4291 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4292 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4295 // To use VPERMILPS to splat scalars, the second half of indicies must
4296 // refer to the higher part, which is a duplication of the lower one,
4297 // because VPERMILPS can only handle in-lane permutations.
4298 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4299 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4301 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4302 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4306 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4309 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4310 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4311 EVT SrcVT = SV->getValueType(0);
4312 SDValue V1 = SV->getOperand(0);
4313 DebugLoc dl = SV->getDebugLoc();
4315 int EltNo = SV->getSplatIndex();
4316 int NumElems = SrcVT.getVectorNumElements();
4317 unsigned Size = SrcVT.getSizeInBits();
4319 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4320 "Unknown how to promote splat for type");
4322 // Extract the 128-bit part containing the splat element and update
4323 // the splat element index when it refers to the higher register.
4325 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4326 V1 = Extract128BitVector(V1, Idx, DAG, dl);
4328 EltNo -= NumElems/2;
4331 // All i16 and i8 vector types can't be used directly by a generic shuffle
4332 // instruction because the target has no such instruction. Generate shuffles
4333 // which repeat i16 and i8 several times until they fit in i32, and then can
4334 // be manipulated by target suported shuffles.
4335 EVT EltVT = SrcVT.getVectorElementType();
4336 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4337 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4339 // Recreate the 256-bit vector and place the same 128-bit vector
4340 // into the low and high part. This is necessary because we want
4341 // to use VPERM* to shuffle the vectors
4343 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4346 return getLegalSplat(DAG, V1, EltNo);
4349 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4350 /// vector of zero or undef vector. This produces a shuffle where the low
4351 /// element of V2 is swizzled into the zero/undef vector, landing at element
4352 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4353 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4355 const X86Subtarget *Subtarget,
4356 SelectionDAG &DAG) {
4357 EVT VT = V2.getValueType();
4359 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4360 unsigned NumElems = VT.getVectorNumElements();
4361 SmallVector<int, 16> MaskVec;
4362 for (unsigned i = 0; i != NumElems; ++i)
4363 // If this is the insertion idx, put the low elt of V2 here.
4364 MaskVec.push_back(i == Idx ? NumElems : i);
4365 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4368 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4369 /// target specific opcode. Returns true if the Mask could be calculated.
4370 /// Sets IsUnary to true if only uses one source.
4371 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4372 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4373 unsigned NumElems = VT.getVectorNumElements();
4377 switch(N->getOpcode()) {
4379 ImmN = N->getOperand(N->getNumOperands()-1);
4380 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4382 case X86ISD::UNPCKH:
4383 DecodeUNPCKHMask(VT, Mask);
4385 case X86ISD::UNPCKL:
4386 DecodeUNPCKLMask(VT, Mask);
4388 case X86ISD::MOVHLPS:
4389 DecodeMOVHLPSMask(NumElems, Mask);
4391 case X86ISD::MOVLHPS:
4392 DecodeMOVLHPSMask(NumElems, Mask);
4394 case X86ISD::PSHUFD:
4395 case X86ISD::VPERMILP:
4396 ImmN = N->getOperand(N->getNumOperands()-1);
4397 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4400 case X86ISD::PSHUFHW:
4401 ImmN = N->getOperand(N->getNumOperands()-1);
4402 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4405 case X86ISD::PSHUFLW:
4406 ImmN = N->getOperand(N->getNumOperands()-1);
4407 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4411 case X86ISD::MOVSD: {
4412 // The index 0 always comes from the first element of the second source,
4413 // this is why MOVSS and MOVSD are used in the first place. The other
4414 // elements come from the other positions of the first source vector
4415 Mask.push_back(NumElems);
4416 for (unsigned i = 1; i != NumElems; ++i) {
4421 case X86ISD::VPERM2X128:
4422 ImmN = N->getOperand(N->getNumOperands()-1);
4423 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4424 if (Mask.empty()) return false;
4426 case X86ISD::MOVDDUP:
4427 case X86ISD::MOVLHPD:
4428 case X86ISD::MOVLPD:
4429 case X86ISD::MOVLPS:
4430 case X86ISD::MOVSHDUP:
4431 case X86ISD::MOVSLDUP:
4432 case X86ISD::PALIGN:
4433 // Not yet implemented
4435 default: llvm_unreachable("unknown target shuffle node");
4441 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4442 /// element of the result of the vector shuffle.
4443 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4446 return SDValue(); // Limit search depth.
4448 SDValue V = SDValue(N, 0);
4449 EVT VT = V.getValueType();
4450 unsigned Opcode = V.getOpcode();
4452 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4453 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4454 int Elt = SV->getMaskElt(Index);
4457 return DAG.getUNDEF(VT.getVectorElementType());
4459 unsigned NumElems = VT.getVectorNumElements();
4460 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4461 : SV->getOperand(1);
4462 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4465 // Recurse into target specific vector shuffles to find scalars.
4466 if (isTargetShuffle(Opcode)) {
4467 unsigned NumElems = VT.getVectorNumElements();
4468 SmallVector<int, 16> ShuffleMask;
4472 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4475 int Elt = ShuffleMask[Index];
4477 return DAG.getUNDEF(VT.getVectorElementType());
4479 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4481 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4485 // Actual nodes that may contain scalar elements
4486 if (Opcode == ISD::BITCAST) {
4487 V = V.getOperand(0);
4488 EVT SrcVT = V.getValueType();
4489 unsigned NumElems = VT.getVectorNumElements();
4491 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4495 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4496 return (Index == 0) ? V.getOperand(0)
4497 : DAG.getUNDEF(VT.getVectorElementType());
4499 if (V.getOpcode() == ISD::BUILD_VECTOR)
4500 return V.getOperand(Index);
4505 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4506 /// shuffle operation which come from a consecutively from a zero. The
4507 /// search can start in two different directions, from left or right.
4509 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4510 bool ZerosFromLeft, SelectionDAG &DAG) {
4512 for (i = 0; i != NumElems; ++i) {
4513 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4514 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4515 if (!(Elt.getNode() &&
4516 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4523 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4524 /// correspond consecutively to elements from one of the vector operands,
4525 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4527 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4528 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4529 unsigned NumElems, unsigned &OpNum) {
4530 bool SeenV1 = false;
4531 bool SeenV2 = false;
4533 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4534 int Idx = SVOp->getMaskElt(i);
4535 // Ignore undef indicies
4539 if (Idx < (int)NumElems)
4544 // Only accept consecutive elements from the same vector
4545 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4549 OpNum = SeenV1 ? 0 : 1;
4553 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4554 /// logical left shift of a vector.
4555 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4556 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4557 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4558 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4559 false /* check zeros from right */, DAG);
4565 // Considering the elements in the mask that are not consecutive zeros,
4566 // check if they consecutively come from only one of the source vectors.
4568 // V1 = {X, A, B, C} 0
4570 // vector_shuffle V1, V2 <1, 2, 3, X>
4572 if (!isShuffleMaskConsecutive(SVOp,
4573 0, // Mask Start Index
4574 NumElems-NumZeros, // Mask End Index(exclusive)
4575 NumZeros, // Where to start looking in the src vector
4576 NumElems, // Number of elements in vector
4577 OpSrc)) // Which source operand ?
4582 ShVal = SVOp->getOperand(OpSrc);
4586 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4587 /// logical left shift of a vector.
4588 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4589 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4590 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4591 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4592 true /* check zeros from left */, DAG);
4598 // Considering the elements in the mask that are not consecutive zeros,
4599 // check if they consecutively come from only one of the source vectors.
4601 // 0 { A, B, X, X } = V2
4603 // vector_shuffle V1, V2 <X, X, 4, 5>
4605 if (!isShuffleMaskConsecutive(SVOp,
4606 NumZeros, // Mask Start Index
4607 NumElems, // Mask End Index(exclusive)
4608 0, // Where to start looking in the src vector
4609 NumElems, // Number of elements in vector
4610 OpSrc)) // Which source operand ?
4615 ShVal = SVOp->getOperand(OpSrc);
4619 /// isVectorShift - Returns true if the shuffle can be implemented as a
4620 /// logical left or right shift of a vector.
4621 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4622 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4623 // Although the logic below support any bitwidth size, there are no
4624 // shift instructions which handle more than 128-bit vectors.
4625 if (SVOp->getValueType(0).getSizeInBits() > 128)
4628 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4629 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4635 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4637 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4638 unsigned NumNonZero, unsigned NumZero,
4640 const X86Subtarget* Subtarget,
4641 const TargetLowering &TLI) {
4645 DebugLoc dl = Op.getDebugLoc();
4648 for (unsigned i = 0; i < 16; ++i) {
4649 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4650 if (ThisIsNonZero && First) {
4652 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4654 V = DAG.getUNDEF(MVT::v8i16);
4659 SDValue ThisElt(0, 0), LastElt(0, 0);
4660 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4661 if (LastIsNonZero) {
4662 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4663 MVT::i16, Op.getOperand(i-1));
4665 if (ThisIsNonZero) {
4666 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4667 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4668 ThisElt, DAG.getConstant(8, MVT::i8));
4670 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4674 if (ThisElt.getNode())
4675 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4676 DAG.getIntPtrConstant(i/2));
4680 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4683 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4685 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4686 unsigned NumNonZero, unsigned NumZero,
4688 const X86Subtarget* Subtarget,
4689 const TargetLowering &TLI) {
4693 DebugLoc dl = Op.getDebugLoc();
4696 for (unsigned i = 0; i < 8; ++i) {
4697 bool isNonZero = (NonZeros & (1 << i)) != 0;
4701 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4703 V = DAG.getUNDEF(MVT::v8i16);
4706 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4707 MVT::v8i16, V, Op.getOperand(i),
4708 DAG.getIntPtrConstant(i));
4715 /// getVShift - Return a vector logical shift node.
4717 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4718 unsigned NumBits, SelectionDAG &DAG,
4719 const TargetLowering &TLI, DebugLoc dl) {
4720 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4721 EVT ShVT = MVT::v2i64;
4722 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4723 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4724 return DAG.getNode(ISD::BITCAST, dl, VT,
4725 DAG.getNode(Opc, dl, ShVT, SrcOp,
4726 DAG.getConstant(NumBits,
4727 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4731 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4732 SelectionDAG &DAG) const {
4734 // Check if the scalar load can be widened into a vector load. And if
4735 // the address is "base + cst" see if the cst can be "absorbed" into
4736 // the shuffle mask.
4737 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4738 SDValue Ptr = LD->getBasePtr();
4739 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4741 EVT PVT = LD->getValueType(0);
4742 if (PVT != MVT::i32 && PVT != MVT::f32)
4747 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4748 FI = FINode->getIndex();
4750 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4751 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4752 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4753 Offset = Ptr.getConstantOperandVal(1);
4754 Ptr = Ptr.getOperand(0);
4759 // FIXME: 256-bit vector instructions don't require a strict alignment,
4760 // improve this code to support it better.
4761 unsigned RequiredAlign = VT.getSizeInBits()/8;
4762 SDValue Chain = LD->getChain();
4763 // Make sure the stack object alignment is at least 16 or 32.
4764 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4765 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4766 if (MFI->isFixedObjectIndex(FI)) {
4767 // Can't change the alignment. FIXME: It's possible to compute
4768 // the exact stack offset and reference FI + adjust offset instead.
4769 // If someone *really* cares about this. That's the way to implement it.
4772 MFI->setObjectAlignment(FI, RequiredAlign);
4776 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4777 // Ptr + (Offset & ~15).
4780 if ((Offset % RequiredAlign) & 3)
4782 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4784 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4785 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4787 int EltNo = (Offset - StartOffset) >> 2;
4788 int NumElems = VT.getVectorNumElements();
4790 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4791 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4792 LD->getPointerInfo().getWithOffset(StartOffset),
4793 false, false, false, 0);
4795 SmallVector<int, 8> Mask;
4796 for (int i = 0; i < NumElems; ++i)
4797 Mask.push_back(EltNo);
4799 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4805 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4806 /// vector of type 'VT', see if the elements can be replaced by a single large
4807 /// load which has the same value as a build_vector whose operands are 'elts'.
4809 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4811 /// FIXME: we'd also like to handle the case where the last elements are zero
4812 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4813 /// There's even a handy isZeroNode for that purpose.
4814 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4815 DebugLoc &DL, SelectionDAG &DAG) {
4816 EVT EltVT = VT.getVectorElementType();
4817 unsigned NumElems = Elts.size();
4819 LoadSDNode *LDBase = NULL;
4820 unsigned LastLoadedElt = -1U;
4822 // For each element in the initializer, see if we've found a load or an undef.
4823 // If we don't find an initial load element, or later load elements are
4824 // non-consecutive, bail out.
4825 for (unsigned i = 0; i < NumElems; ++i) {
4826 SDValue Elt = Elts[i];
4828 if (!Elt.getNode() ||
4829 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4832 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4834 LDBase = cast<LoadSDNode>(Elt.getNode());
4838 if (Elt.getOpcode() == ISD::UNDEF)
4841 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4842 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4847 // If we have found an entire vector of loads and undefs, then return a large
4848 // load of the entire vector width starting at the base pointer. If we found
4849 // consecutive loads for the low half, generate a vzext_load node.
4850 if (LastLoadedElt == NumElems - 1) {
4851 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4852 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4853 LDBase->getPointerInfo(),
4854 LDBase->isVolatile(), LDBase->isNonTemporal(),
4855 LDBase->isInvariant(), 0);
4856 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4857 LDBase->getPointerInfo(),
4858 LDBase->isVolatile(), LDBase->isNonTemporal(),
4859 LDBase->isInvariant(), LDBase->getAlignment());
4860 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4861 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4862 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4863 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4865 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4866 LDBase->getPointerInfo(),
4867 LDBase->getAlignment(),
4868 false/*isVolatile*/, true/*ReadMem*/,
4870 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4875 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4876 /// to generate a splat value for the following cases:
4877 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4878 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4879 /// a scalar load, or a constant.
4880 /// The VBROADCAST node is returned when a pattern is found,
4881 /// or SDValue() otherwise.
4883 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4884 if (!Subtarget->hasAVX())
4887 EVT VT = Op.getValueType();
4888 DebugLoc dl = Op.getDebugLoc();
4893 switch (Op.getOpcode()) {
4895 // Unknown pattern found.
4898 case ISD::BUILD_VECTOR: {
4899 // The BUILD_VECTOR node must be a splat.
4900 if (!isSplatVector(Op.getNode()))
4903 Ld = Op.getOperand(0);
4904 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4905 Ld.getOpcode() == ISD::ConstantFP);
4907 // The suspected load node has several users. Make sure that all
4908 // of its users are from the BUILD_VECTOR node.
4909 // Constants may have multiple users.
4910 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4915 case ISD::VECTOR_SHUFFLE: {
4916 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4918 // Shuffles must have a splat mask where the first element is
4920 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4923 SDValue Sc = Op.getOperand(0);
4924 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4927 Ld = Sc.getOperand(0);
4928 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4929 Ld.getOpcode() == ISD::ConstantFP);
4931 // The scalar_to_vector node and the suspected
4932 // load node must have exactly one user.
4933 // Constants may have multiple users.
4934 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4940 bool Is256 = VT.getSizeInBits() == 256;
4941 bool Is128 = VT.getSizeInBits() == 128;
4943 // Handle the broadcasting a single constant scalar from the constant pool
4944 // into a vector. On Sandybridge it is still better to load a constant vector
4945 // from the constant pool and not to broadcast it from a scalar.
4946 if (ConstSplatVal && Subtarget->hasAVX2()) {
4947 EVT CVT = Ld.getValueType();
4948 assert(!CVT.isVector() && "Must not broadcast a vector type");
4949 unsigned ScalarSize = CVT.getSizeInBits();
4951 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4952 (Is128 && (ScalarSize == 32))) {
4954 const Constant *C = 0;
4955 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4956 C = CI->getConstantIntValue();
4957 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4958 C = CF->getConstantFPValue();
4960 assert(C && "Invalid constant type");
4962 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4963 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4964 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4965 MachinePointerInfo::getConstantPool(),
4966 false, false, false, Alignment);
4968 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4972 // The scalar source must be a normal load.
4973 if (!ISD::isNormalLoad(Ld.getNode()))
4976 // Reject loads that have uses of the chain result
4977 if (Ld->hasAnyUseOfValue(1))
4980 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4982 // VBroadcast to YMM
4983 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4984 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4986 // VBroadcast to XMM
4987 if (Is128 && (ScalarSize == 32))
4988 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4990 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4991 // double since there is vbroadcastsd xmm
4992 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
4993 // VBroadcast to YMM
4994 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
4995 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4997 // VBroadcast to XMM
4998 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
4999 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5002 // Unsupported broadcast.
5007 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5008 DebugLoc dl = Op.getDebugLoc();
5010 EVT VT = Op.getValueType();
5011 EVT ExtVT = VT.getVectorElementType();
5012 unsigned NumElems = Op.getNumOperands();
5014 // Vectors containing all zeros can be matched by pxor and xorps later
5015 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5016 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5017 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5018 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5021 return getZeroVector(VT, Subtarget, DAG, dl);
5024 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5025 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5026 // vpcmpeqd on 256-bit vectors.
5027 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5028 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5031 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5034 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5035 if (Broadcast.getNode())
5038 unsigned EVTBits = ExtVT.getSizeInBits();
5040 unsigned NumZero = 0;
5041 unsigned NumNonZero = 0;
5042 unsigned NonZeros = 0;
5043 bool IsAllConstants = true;
5044 SmallSet<SDValue, 8> Values;
5045 for (unsigned i = 0; i < NumElems; ++i) {
5046 SDValue Elt = Op.getOperand(i);
5047 if (Elt.getOpcode() == ISD::UNDEF)
5050 if (Elt.getOpcode() != ISD::Constant &&
5051 Elt.getOpcode() != ISD::ConstantFP)
5052 IsAllConstants = false;
5053 if (X86::isZeroNode(Elt))
5056 NonZeros |= (1 << i);
5061 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5062 if (NumNonZero == 0)
5063 return DAG.getUNDEF(VT);
5065 // Special case for single non-zero, non-undef, element.
5066 if (NumNonZero == 1) {
5067 unsigned Idx = CountTrailingZeros_32(NonZeros);
5068 SDValue Item = Op.getOperand(Idx);
5070 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5071 // the value are obviously zero, truncate the value to i32 and do the
5072 // insertion that way. Only do this if the value is non-constant or if the
5073 // value is a constant being inserted into element 0. It is cheaper to do
5074 // a constant pool load than it is to do a movd + shuffle.
5075 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5076 (!IsAllConstants || Idx == 0)) {
5077 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5079 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5080 EVT VecVT = MVT::v4i32;
5081 unsigned VecElts = 4;
5083 // Truncate the value (which may itself be a constant) to i32, and
5084 // convert it to a vector with movd (S2V+shuffle to zero extend).
5085 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5086 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5087 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5089 // Now we have our 32-bit value zero extended in the low element of
5090 // a vector. If Idx != 0, swizzle it into place.
5092 SmallVector<int, 4> Mask;
5093 Mask.push_back(Idx);
5094 for (unsigned i = 1; i != VecElts; ++i)
5096 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5103 // If we have a constant or non-constant insertion into the low element of
5104 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5105 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5106 // depending on what the source datatype is.
5109 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5111 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5112 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5113 if (VT.getSizeInBits() == 256) {
5114 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5115 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5116 Item, DAG.getIntPtrConstant(0));
5118 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5119 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5120 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5121 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5124 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5125 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5126 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5127 if (VT.getSizeInBits() == 256) {
5128 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5129 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5131 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5132 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5134 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5138 // Is it a vector logical left shift?
5139 if (NumElems == 2 && Idx == 1 &&
5140 X86::isZeroNode(Op.getOperand(0)) &&
5141 !X86::isZeroNode(Op.getOperand(1))) {
5142 unsigned NumBits = VT.getSizeInBits();
5143 return getVShift(true, VT,
5144 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5145 VT, Op.getOperand(1)),
5146 NumBits/2, DAG, *this, dl);
5149 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5152 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5153 // is a non-constant being inserted into an element other than the low one,
5154 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5155 // movd/movss) to move this into the low element, then shuffle it into
5157 if (EVTBits == 32) {
5158 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5160 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5161 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5162 SmallVector<int, 8> MaskVec;
5163 for (unsigned i = 0; i < NumElems; i++)
5164 MaskVec.push_back(i == Idx ? 0 : 1);
5165 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5169 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5170 if (Values.size() == 1) {
5171 if (EVTBits == 32) {
5172 // Instead of a shuffle like this:
5173 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5174 // Check if it's possible to issue this instead.
5175 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5176 unsigned Idx = CountTrailingZeros_32(NonZeros);
5177 SDValue Item = Op.getOperand(Idx);
5178 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5179 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5184 // A vector full of immediates; various special cases are already
5185 // handled, so this is best done with a single constant-pool load.
5189 // For AVX-length vectors, build the individual 128-bit pieces and use
5190 // shuffles to put them in place.
5191 if (VT.getSizeInBits() == 256) {
5192 SmallVector<SDValue, 32> V;
5193 for (unsigned i = 0; i != NumElems; ++i)
5194 V.push_back(Op.getOperand(i));
5196 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5198 // Build both the lower and upper subvector.
5199 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5200 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5203 // Recreate the wider vector with the lower and upper part.
5204 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5207 // Let legalizer expand 2-wide build_vectors.
5208 if (EVTBits == 64) {
5209 if (NumNonZero == 1) {
5210 // One half is zero or undef.
5211 unsigned Idx = CountTrailingZeros_32(NonZeros);
5212 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5213 Op.getOperand(Idx));
5214 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5219 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5220 if (EVTBits == 8 && NumElems == 16) {
5221 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5223 if (V.getNode()) return V;
5226 if (EVTBits == 16 && NumElems == 8) {
5227 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5229 if (V.getNode()) return V;
5232 // If element VT is == 32 bits, turn it into a number of shuffles.
5233 SmallVector<SDValue, 8> V(NumElems);
5234 if (NumElems == 4 && NumZero > 0) {
5235 for (unsigned i = 0; i < 4; ++i) {
5236 bool isZero = !(NonZeros & (1 << i));
5238 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5240 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5243 for (unsigned i = 0; i < 2; ++i) {
5244 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5247 V[i] = V[i*2]; // Must be a zero vector.
5250 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5253 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5256 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5261 bool Reverse1 = (NonZeros & 0x3) == 2;
5262 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5266 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5267 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5269 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5272 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5273 // Check for a build vector of consecutive loads.
5274 for (unsigned i = 0; i < NumElems; ++i)
5275 V[i] = Op.getOperand(i);
5277 // Check for elements which are consecutive loads.
5278 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5282 // For SSE 4.1, use insertps to put the high elements into the low element.
5283 if (getSubtarget()->hasSSE41()) {
5285 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5286 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5288 Result = DAG.getUNDEF(VT);
5290 for (unsigned i = 1; i < NumElems; ++i) {
5291 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5292 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5293 Op.getOperand(i), DAG.getIntPtrConstant(i));
5298 // Otherwise, expand into a number of unpckl*, start by extending each of
5299 // our (non-undef) elements to the full vector width with the element in the
5300 // bottom slot of the vector (which generates no code for SSE).
5301 for (unsigned i = 0; i < NumElems; ++i) {
5302 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5303 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5305 V[i] = DAG.getUNDEF(VT);
5308 // Next, we iteratively mix elements, e.g. for v4f32:
5309 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5310 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5311 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5312 unsigned EltStride = NumElems >> 1;
5313 while (EltStride != 0) {
5314 for (unsigned i = 0; i < EltStride; ++i) {
5315 // If V[i+EltStride] is undef and this is the first round of mixing,
5316 // then it is safe to just drop this shuffle: V[i] is already in the
5317 // right place, the one element (since it's the first round) being
5318 // inserted as undef can be dropped. This isn't safe for successive
5319 // rounds because they will permute elements within both vectors.
5320 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5321 EltStride == NumElems/2)
5324 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5333 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5334 // them in a MMX register. This is better than doing a stack convert.
5335 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5336 DebugLoc dl = Op.getDebugLoc();
5337 EVT ResVT = Op.getValueType();
5339 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5340 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5342 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5343 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5344 InVec = Op.getOperand(1);
5345 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5346 unsigned NumElts = ResVT.getVectorNumElements();
5347 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5348 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5349 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5351 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5352 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5353 Mask[0] = 0; Mask[1] = 2;
5354 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5356 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5359 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5360 // to create 256-bit vectors from two other 128-bit ones.
5361 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5362 DebugLoc dl = Op.getDebugLoc();
5363 EVT ResVT = Op.getValueType();
5365 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5367 SDValue V1 = Op.getOperand(0);
5368 SDValue V2 = Op.getOperand(1);
5369 unsigned NumElems = ResVT.getVectorNumElements();
5371 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5375 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5376 EVT ResVT = Op.getValueType();
5378 assert(Op.getNumOperands() == 2);
5379 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5380 "Unsupported CONCAT_VECTORS for value type");
5382 // We support concatenate two MMX registers and place them in a MMX register.
5383 // This is better than doing a stack convert.
5384 if (ResVT.is128BitVector())
5385 return LowerMMXCONCAT_VECTORS(Op, DAG);
5387 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5388 // from two other 128-bit ones.
5389 return LowerAVXCONCAT_VECTORS(Op, DAG);
5392 // Try to lower a shuffle node into a simple blend instruction.
5393 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5394 const X86Subtarget *Subtarget,
5395 SelectionDAG &DAG) {
5396 SDValue V1 = SVOp->getOperand(0);
5397 SDValue V2 = SVOp->getOperand(1);
5398 DebugLoc dl = SVOp->getDebugLoc();
5399 EVT VT = SVOp->getValueType(0);
5400 unsigned NumElems = VT.getVectorNumElements();
5402 if (!Subtarget->hasSSE41())
5408 switch (VT.getSimpleVT().SimpleTy) {
5409 default: return SDValue();
5411 ISDNo = X86ISD::BLENDPW;
5416 ISDNo = X86ISD::BLENDPS;
5421 ISDNo = X86ISD::BLENDPD;
5426 if (!Subtarget->hasAVX())
5428 ISDNo = X86ISD::BLENDPS;
5433 if (!Subtarget->hasAVX())
5435 ISDNo = X86ISD::BLENDPD;
5439 if (!Subtarget->hasAVX2())
5441 ISDNo = X86ISD::BLENDPW;
5445 assert(ISDNo && "Invalid Op Number");
5447 unsigned MaskVals = 0;
5449 for (unsigned i = 0; i != NumElems; ++i) {
5450 int EltIdx = SVOp->getMaskElt(i);
5451 if (EltIdx == (int)i || EltIdx < 0)
5453 else if (EltIdx == (int)(i + NumElems))
5454 continue; // Bit is set to zero;
5459 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5460 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5461 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5462 DAG.getConstant(MaskVals, MVT::i32));
5463 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5466 // v8i16 shuffles - Prefer shuffles in the following order:
5467 // 1. [all] pshuflw, pshufhw, optional move
5468 // 2. [ssse3] 1 x pshufb
5469 // 3. [ssse3] 2 x pshufb + 1 x por
5470 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5472 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5473 SelectionDAG &DAG) const {
5474 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5475 SDValue V1 = SVOp->getOperand(0);
5476 SDValue V2 = SVOp->getOperand(1);
5477 DebugLoc dl = SVOp->getDebugLoc();
5478 SmallVector<int, 8> MaskVals;
5480 // Determine if more than 1 of the words in each of the low and high quadwords
5481 // of the result come from the same quadword of one of the two inputs. Undef
5482 // mask values count as coming from any quadword, for better codegen.
5483 unsigned LoQuad[] = { 0, 0, 0, 0 };
5484 unsigned HiQuad[] = { 0, 0, 0, 0 };
5485 std::bitset<4> InputQuads;
5486 for (unsigned i = 0; i < 8; ++i) {
5487 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5488 int EltIdx = SVOp->getMaskElt(i);
5489 MaskVals.push_back(EltIdx);
5498 InputQuads.set(EltIdx / 4);
5501 int BestLoQuad = -1;
5502 unsigned MaxQuad = 1;
5503 for (unsigned i = 0; i < 4; ++i) {
5504 if (LoQuad[i] > MaxQuad) {
5506 MaxQuad = LoQuad[i];
5510 int BestHiQuad = -1;
5512 for (unsigned i = 0; i < 4; ++i) {
5513 if (HiQuad[i] > MaxQuad) {
5515 MaxQuad = HiQuad[i];
5519 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5520 // of the two input vectors, shuffle them into one input vector so only a
5521 // single pshufb instruction is necessary. If There are more than 2 input
5522 // quads, disable the next transformation since it does not help SSSE3.
5523 bool V1Used = InputQuads[0] || InputQuads[1];
5524 bool V2Used = InputQuads[2] || InputQuads[3];
5525 if (Subtarget->hasSSSE3()) {
5526 if (InputQuads.count() == 2 && V1Used && V2Used) {
5527 BestLoQuad = InputQuads[0] ? 0 : 1;
5528 BestHiQuad = InputQuads[2] ? 2 : 3;
5530 if (InputQuads.count() > 2) {
5536 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5537 // the shuffle mask. If a quad is scored as -1, that means that it contains
5538 // words from all 4 input quadwords.
5540 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5542 BestLoQuad < 0 ? 0 : BestLoQuad,
5543 BestHiQuad < 0 ? 1 : BestHiQuad
5545 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5546 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5547 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5548 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5550 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5551 // source words for the shuffle, to aid later transformations.
5552 bool AllWordsInNewV = true;
5553 bool InOrder[2] = { true, true };
5554 for (unsigned i = 0; i != 8; ++i) {
5555 int idx = MaskVals[i];
5557 InOrder[i/4] = false;
5558 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5560 AllWordsInNewV = false;
5564 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5565 if (AllWordsInNewV) {
5566 for (int i = 0; i != 8; ++i) {
5567 int idx = MaskVals[i];
5570 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5571 if ((idx != i) && idx < 4)
5573 if ((idx != i) && idx > 3)
5582 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5583 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5584 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5585 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5586 unsigned TargetMask = 0;
5587 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5588 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5589 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5590 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5591 getShufflePSHUFLWImmediate(SVOp);
5592 V1 = NewV.getOperand(0);
5593 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5597 // If we have SSSE3, and all words of the result are from 1 input vector,
5598 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5599 // is present, fall back to case 4.
5600 if (Subtarget->hasSSSE3()) {
5601 SmallVector<SDValue,16> pshufbMask;
5603 // If we have elements from both input vectors, set the high bit of the
5604 // shuffle mask element to zero out elements that come from V2 in the V1
5605 // mask, and elements that come from V1 in the V2 mask, so that the two
5606 // results can be OR'd together.
5607 bool TwoInputs = V1Used && V2Used;
5608 for (unsigned i = 0; i != 8; ++i) {
5609 int EltIdx = MaskVals[i] * 2;
5610 if (TwoInputs && (EltIdx >= 16)) {
5611 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5612 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5615 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5616 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5618 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5619 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5620 DAG.getNode(ISD::BUILD_VECTOR, dl,
5621 MVT::v16i8, &pshufbMask[0], 16));
5623 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5625 // Calculate the shuffle mask for the second input, shuffle it, and
5626 // OR it with the first shuffled input.
5628 for (unsigned i = 0; i != 8; ++i) {
5629 int EltIdx = MaskVals[i] * 2;
5631 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5632 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5635 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5636 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5638 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5639 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5640 DAG.getNode(ISD::BUILD_VECTOR, dl,
5641 MVT::v16i8, &pshufbMask[0], 16));
5642 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5643 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5646 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5647 // and update MaskVals with new element order.
5648 std::bitset<8> InOrder;
5649 if (BestLoQuad >= 0) {
5650 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5651 for (int i = 0; i != 4; ++i) {
5652 int idx = MaskVals[i];
5655 } else if ((idx / 4) == BestLoQuad) {
5660 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5663 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5664 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5665 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5667 getShufflePSHUFLWImmediate(SVOp), DAG);
5671 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5672 // and update MaskVals with the new element order.
5673 if (BestHiQuad >= 0) {
5674 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5675 for (unsigned i = 4; i != 8; ++i) {
5676 int idx = MaskVals[i];
5679 } else if ((idx / 4) == BestHiQuad) {
5680 MaskV[i] = (idx & 3) + 4;
5684 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5687 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5689 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5691 getShufflePSHUFHWImmediate(SVOp), DAG);
5695 // In case BestHi & BestLo were both -1, which means each quadword has a word
5696 // from each of the four input quadwords, calculate the InOrder bitvector now
5697 // before falling through to the insert/extract cleanup.
5698 if (BestLoQuad == -1 && BestHiQuad == -1) {
5700 for (int i = 0; i != 8; ++i)
5701 if (MaskVals[i] < 0 || MaskVals[i] == i)
5705 // The other elements are put in the right place using pextrw and pinsrw.
5706 for (unsigned i = 0; i != 8; ++i) {
5709 int EltIdx = MaskVals[i];
5712 SDValue ExtOp = (EltIdx < 8)
5713 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5714 DAG.getIntPtrConstant(EltIdx))
5715 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5716 DAG.getIntPtrConstant(EltIdx - 8));
5717 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5718 DAG.getIntPtrConstant(i));
5723 // v16i8 shuffles - Prefer shuffles in the following order:
5724 // 1. [ssse3] 1 x pshufb
5725 // 2. [ssse3] 2 x pshufb + 1 x por
5726 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5728 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5730 const X86TargetLowering &TLI) {
5731 SDValue V1 = SVOp->getOperand(0);
5732 SDValue V2 = SVOp->getOperand(1);
5733 DebugLoc dl = SVOp->getDebugLoc();
5734 ArrayRef<int> MaskVals = SVOp->getMask();
5736 // If we have SSSE3, case 1 is generated when all result bytes come from
5737 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5738 // present, fall back to case 3.
5739 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5742 for (unsigned i = 0; i < 16; ++i) {
5743 int EltIdx = MaskVals[i];
5752 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5753 if (TLI.getSubtarget()->hasSSSE3()) {
5754 SmallVector<SDValue,16> pshufbMask;
5756 // If all result elements are from one input vector, then only translate
5757 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5759 // Otherwise, we have elements from both input vectors, and must zero out
5760 // elements that come from V2 in the first mask, and V1 in the second mask
5761 // so that we can OR them together.
5762 bool TwoInputs = !(V1Only || V2Only);
5763 for (unsigned i = 0; i != 16; ++i) {
5764 int EltIdx = MaskVals[i];
5765 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5766 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5769 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5771 // If all the elements are from V2, assign it to V1 and return after
5772 // building the first pshufb.
5775 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5776 DAG.getNode(ISD::BUILD_VECTOR, dl,
5777 MVT::v16i8, &pshufbMask[0], 16));
5781 // Calculate the shuffle mask for the second input, shuffle it, and
5782 // OR it with the first shuffled input.
5784 for (unsigned i = 0; i != 16; ++i) {
5785 int EltIdx = MaskVals[i];
5787 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5790 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5792 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5793 DAG.getNode(ISD::BUILD_VECTOR, dl,
5794 MVT::v16i8, &pshufbMask[0], 16));
5795 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5798 // No SSSE3 - Calculate in place words and then fix all out of place words
5799 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5800 // the 16 different words that comprise the two doublequadword input vectors.
5801 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5802 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5803 SDValue NewV = V2Only ? V2 : V1;
5804 for (int i = 0; i != 8; ++i) {
5805 int Elt0 = MaskVals[i*2];
5806 int Elt1 = MaskVals[i*2+1];
5808 // This word of the result is all undef, skip it.
5809 if (Elt0 < 0 && Elt1 < 0)
5812 // This word of the result is already in the correct place, skip it.
5813 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5815 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5818 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5819 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5822 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5823 // using a single extract together, load it and store it.
5824 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5825 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5826 DAG.getIntPtrConstant(Elt1 / 2));
5827 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5828 DAG.getIntPtrConstant(i));
5832 // If Elt1 is defined, extract it from the appropriate source. If the
5833 // source byte is not also odd, shift the extracted word left 8 bits
5834 // otherwise clear the bottom 8 bits if we need to do an or.
5836 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5837 DAG.getIntPtrConstant(Elt1 / 2));
5838 if ((Elt1 & 1) == 0)
5839 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5841 TLI.getShiftAmountTy(InsElt.getValueType())));
5843 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5844 DAG.getConstant(0xFF00, MVT::i16));
5846 // If Elt0 is defined, extract it from the appropriate source. If the
5847 // source byte is not also even, shift the extracted word right 8 bits. If
5848 // Elt1 was also defined, OR the extracted values together before
5849 // inserting them in the result.
5851 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5852 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5853 if ((Elt0 & 1) != 0)
5854 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5856 TLI.getShiftAmountTy(InsElt0.getValueType())));
5858 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5859 DAG.getConstant(0x00FF, MVT::i16));
5860 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5863 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5864 DAG.getIntPtrConstant(i));
5866 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5869 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5870 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5871 /// done when every pair / quad of shuffle mask elements point to elements in
5872 /// the right sequence. e.g.
5873 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5875 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5876 SelectionDAG &DAG, DebugLoc dl) {
5877 EVT VT = SVOp->getValueType(0);
5878 SDValue V1 = SVOp->getOperand(0);
5879 SDValue V2 = SVOp->getOperand(1);
5880 unsigned NumElems = VT.getVectorNumElements();
5881 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5883 switch (VT.getSimpleVT().SimpleTy) {
5884 default: llvm_unreachable("Unexpected!");
5885 case MVT::v4f32: NewVT = MVT::v2f64; break;
5886 case MVT::v4i32: NewVT = MVT::v2i64; break;
5887 case MVT::v8i16: NewVT = MVT::v4i32; break;
5888 case MVT::v16i8: NewVT = MVT::v4i32; break;
5891 int Scale = NumElems / NewWidth;
5892 SmallVector<int, 8> MaskVec;
5893 for (unsigned i = 0; i < NumElems; i += Scale) {
5895 for (int j = 0; j < Scale; ++j) {
5896 int EltIdx = SVOp->getMaskElt(i+j);
5900 StartIdx = EltIdx - (EltIdx % Scale);
5901 if (EltIdx != StartIdx + j)
5905 MaskVec.push_back(-1);
5907 MaskVec.push_back(StartIdx / Scale);
5910 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5911 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5912 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5915 /// getVZextMovL - Return a zero-extending vector move low node.
5917 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5918 SDValue SrcOp, SelectionDAG &DAG,
5919 const X86Subtarget *Subtarget, DebugLoc dl) {
5920 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5921 LoadSDNode *LD = NULL;
5922 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5923 LD = dyn_cast<LoadSDNode>(SrcOp);
5925 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5927 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5928 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5929 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5930 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5931 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5933 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5934 return DAG.getNode(ISD::BITCAST, dl, VT,
5935 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5936 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5944 return DAG.getNode(ISD::BITCAST, dl, VT,
5945 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5946 DAG.getNode(ISD::BITCAST, dl,
5950 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5951 /// which could not be matched by any known target speficic shuffle
5953 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5954 EVT VT = SVOp->getValueType(0);
5956 unsigned NumElems = VT.getVectorNumElements();
5957 unsigned NumLaneElems = NumElems / 2;
5959 DebugLoc dl = SVOp->getDebugLoc();
5960 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5961 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5964 SmallVector<int, 16> Mask;
5965 for (unsigned l = 0; l < 2; ++l) {
5966 // Build a shuffle mask for the output, discovering on the fly which
5967 // input vectors to use as shuffle operands (recorded in InputUsed).
5968 // If building a suitable shuffle vector proves too hard, then bail
5969 // out with useBuildVector set.
5970 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5971 unsigned LaneStart = l * NumLaneElems;
5972 for (unsigned i = 0; i != NumLaneElems; ++i) {
5973 // The mask element. This indexes into the input.
5974 int Idx = SVOp->getMaskElt(i+LaneStart);
5976 // the mask element does not index into any input vector.
5981 // The input vector this mask element indexes into.
5982 int Input = Idx / NumLaneElems;
5984 // Turn the index into an offset from the start of the input vector.
5985 Idx -= Input * NumLaneElems;
5987 // Find or create a shuffle vector operand to hold this input.
5989 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
5990 if (InputUsed[OpNo] == Input)
5991 // This input vector is already an operand.
5993 if (InputUsed[OpNo] < 0) {
5994 // Create a new operand for this input vector.
5995 InputUsed[OpNo] = Input;
6000 if (OpNo >= array_lengthof(InputUsed)) {
6001 // More than two input vectors used! Give up.
6005 // Add the mask index for the new shuffle vector.
6006 Mask.push_back(Idx + OpNo * NumLaneElems);
6009 if (InputUsed[0] < 0) {
6010 // No input vectors were used! The result is undefined.
6011 Shufs[l] = DAG.getUNDEF(NVT);
6013 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6014 (InputUsed[0] % 2) * NumLaneElems,
6016 // If only one input was used, use an undefined vector for the other.
6017 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6018 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6019 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6020 // At least one input vector was used. Create a new shuffle vector.
6021 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6027 // Concatenate the result back
6028 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]);
6031 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6032 /// 4 elements, and match them with several different shuffle types.
6034 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6035 SDValue V1 = SVOp->getOperand(0);
6036 SDValue V2 = SVOp->getOperand(1);
6037 DebugLoc dl = SVOp->getDebugLoc();
6038 EVT VT = SVOp->getValueType(0);
6040 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6042 std::pair<int, int> Locs[4];
6043 int Mask1[] = { -1, -1, -1, -1 };
6044 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6048 for (unsigned i = 0; i != 4; ++i) {
6049 int Idx = PermMask[i];
6051 Locs[i] = std::make_pair(-1, -1);
6053 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6055 Locs[i] = std::make_pair(0, NumLo);
6059 Locs[i] = std::make_pair(1, NumHi);
6061 Mask1[2+NumHi] = Idx;
6067 if (NumLo <= 2 && NumHi <= 2) {
6068 // If no more than two elements come from either vector. This can be
6069 // implemented with two shuffles. First shuffle gather the elements.
6070 // The second shuffle, which takes the first shuffle as both of its
6071 // vector operands, put the elements into the right order.
6072 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6074 int Mask2[] = { -1, -1, -1, -1 };
6076 for (unsigned i = 0; i != 4; ++i)
6077 if (Locs[i].first != -1) {
6078 unsigned Idx = (i < 2) ? 0 : 4;
6079 Idx += Locs[i].first * 2 + Locs[i].second;
6083 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6084 } else if (NumLo == 3 || NumHi == 3) {
6085 // Otherwise, we must have three elements from one vector, call it X, and
6086 // one element from the other, call it Y. First, use a shufps to build an
6087 // intermediate vector with the one element from Y and the element from X
6088 // that will be in the same half in the final destination (the indexes don't
6089 // matter). Then, use a shufps to build the final vector, taking the half
6090 // containing the element from Y from the intermediate, and the other half
6093 // Normalize it so the 3 elements come from V1.
6094 CommuteVectorShuffleMask(PermMask, 4);
6098 // Find the element from V2.
6100 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6101 int Val = PermMask[HiIndex];
6108 Mask1[0] = PermMask[HiIndex];
6110 Mask1[2] = PermMask[HiIndex^1];
6112 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6115 Mask1[0] = PermMask[0];
6116 Mask1[1] = PermMask[1];
6117 Mask1[2] = HiIndex & 1 ? 6 : 4;
6118 Mask1[3] = HiIndex & 1 ? 4 : 6;
6119 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6121 Mask1[0] = HiIndex & 1 ? 2 : 0;
6122 Mask1[1] = HiIndex & 1 ? 0 : 2;
6123 Mask1[2] = PermMask[2];
6124 Mask1[3] = PermMask[3];
6129 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6133 // Break it into (shuffle shuffle_hi, shuffle_lo).
6134 int LoMask[] = { -1, -1, -1, -1 };
6135 int HiMask[] = { -1, -1, -1, -1 };
6137 int *MaskPtr = LoMask;
6138 unsigned MaskIdx = 0;
6141 for (unsigned i = 0; i != 4; ++i) {
6148 int Idx = PermMask[i];
6150 Locs[i] = std::make_pair(-1, -1);
6151 } else if (Idx < 4) {
6152 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6153 MaskPtr[LoIdx] = Idx;
6156 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6157 MaskPtr[HiIdx] = Idx;
6162 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6163 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6164 int MaskOps[] = { -1, -1, -1, -1 };
6165 for (unsigned i = 0; i != 4; ++i)
6166 if (Locs[i].first != -1)
6167 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6168 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6171 static bool MayFoldVectorLoad(SDValue V) {
6172 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6173 V = V.getOperand(0);
6174 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6175 V = V.getOperand(0);
6176 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6177 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6178 // BUILD_VECTOR (load), undef
6179 V = V.getOperand(0);
6185 // FIXME: the version above should always be used. Since there's
6186 // a bug where several vector shuffles can't be folded because the
6187 // DAG is not updated during lowering and a node claims to have two
6188 // uses while it only has one, use this version, and let isel match
6189 // another instruction if the load really happens to have more than
6190 // one use. Remove this version after this bug get fixed.
6191 // rdar://8434668, PR8156
6192 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6193 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6194 V = V.getOperand(0);
6195 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6196 V = V.getOperand(0);
6197 if (ISD::isNormalLoad(V.getNode()))
6203 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6204 EVT VT = Op.getValueType();
6206 // Canonizalize to v2f64.
6207 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6208 return DAG.getNode(ISD::BITCAST, dl, VT,
6209 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6214 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6216 SDValue V1 = Op.getOperand(0);
6217 SDValue V2 = Op.getOperand(1);
6218 EVT VT = Op.getValueType();
6220 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6222 if (HasSSE2 && VT == MVT::v2f64)
6223 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6225 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6226 return DAG.getNode(ISD::BITCAST, dl, VT,
6227 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6228 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6229 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6233 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6234 SDValue V1 = Op.getOperand(0);
6235 SDValue V2 = Op.getOperand(1);
6236 EVT VT = Op.getValueType();
6238 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6239 "unsupported shuffle type");
6241 if (V2.getOpcode() == ISD::UNDEF)
6245 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6249 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6250 SDValue V1 = Op.getOperand(0);
6251 SDValue V2 = Op.getOperand(1);
6252 EVT VT = Op.getValueType();
6253 unsigned NumElems = VT.getVectorNumElements();
6255 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6256 // operand of these instructions is only memory, so check if there's a
6257 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6259 bool CanFoldLoad = false;
6261 // Trivial case, when V2 comes from a load.
6262 if (MayFoldVectorLoad(V2))
6265 // When V1 is a load, it can be folded later into a store in isel, example:
6266 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6268 // (MOVLPSmr addr:$src1, VR128:$src2)
6269 // So, recognize this potential and also use MOVLPS or MOVLPD
6270 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6273 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6275 if (HasSSE2 && NumElems == 2)
6276 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6279 // If we don't care about the second element, procede to use movss.
6280 if (SVOp->getMaskElt(1) != -1)
6281 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6284 // movl and movlp will both match v2i64, but v2i64 is never matched by
6285 // movl earlier because we make it strict to avoid messing with the movlp load
6286 // folding logic (see the code above getMOVLP call). Match it here then,
6287 // this is horrible, but will stay like this until we move all shuffle
6288 // matching to x86 specific nodes. Note that for the 1st condition all
6289 // types are matched with movsd.
6291 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6292 // as to remove this logic from here, as much as possible
6293 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6294 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6295 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6298 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6300 // Invert the operand order and use SHUFPS to match it.
6301 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6302 getShuffleSHUFImmediate(SVOp), DAG);
6306 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6307 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6308 EVT VT = Op.getValueType();
6309 DebugLoc dl = Op.getDebugLoc();
6310 SDValue V1 = Op.getOperand(0);
6311 SDValue V2 = Op.getOperand(1);
6313 if (isZeroShuffle(SVOp))
6314 return getZeroVector(VT, Subtarget, DAG, dl);
6316 // Handle splat operations
6317 if (SVOp->isSplat()) {
6318 unsigned NumElem = VT.getVectorNumElements();
6319 int Size = VT.getSizeInBits();
6321 // Use vbroadcast whenever the splat comes from a foldable load
6322 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6323 if (Broadcast.getNode())
6326 // Handle splats by matching through known shuffle masks
6327 if ((Size == 128 && NumElem <= 4) ||
6328 (Size == 256 && NumElem < 8))
6331 // All remaning splats are promoted to target supported vector shuffles.
6332 return PromoteSplat(SVOp, DAG);
6335 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6337 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6338 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6339 if (NewOp.getNode())
6340 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6341 } else if ((VT == MVT::v4i32 ||
6342 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6343 // FIXME: Figure out a cleaner way to do this.
6344 // Try to make use of movq to zero out the top part.
6345 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6346 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6347 if (NewOp.getNode()) {
6348 EVT NewVT = NewOp.getValueType();
6349 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6350 NewVT, true, false))
6351 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6352 DAG, Subtarget, dl);
6354 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6355 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6356 if (NewOp.getNode()) {
6357 EVT NewVT = NewOp.getValueType();
6358 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6359 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6360 DAG, Subtarget, dl);
6368 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6369 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6370 SDValue V1 = Op.getOperand(0);
6371 SDValue V2 = Op.getOperand(1);
6372 EVT VT = Op.getValueType();
6373 DebugLoc dl = Op.getDebugLoc();
6374 unsigned NumElems = VT.getVectorNumElements();
6375 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6376 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6377 bool V1IsSplat = false;
6378 bool V2IsSplat = false;
6379 bool HasSSE2 = Subtarget->hasSSE2();
6380 bool HasAVX = Subtarget->hasAVX();
6381 bool HasAVX2 = Subtarget->hasAVX2();
6382 MachineFunction &MF = DAG.getMachineFunction();
6383 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6385 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6387 if (V1IsUndef && V2IsUndef)
6388 return DAG.getUNDEF(VT);
6390 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6392 // Vector shuffle lowering takes 3 steps:
6394 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6395 // narrowing and commutation of operands should be handled.
6396 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6398 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6399 // so the shuffle can be broken into other shuffles and the legalizer can
6400 // try the lowering again.
6402 // The general idea is that no vector_shuffle operation should be left to
6403 // be matched during isel, all of them must be converted to a target specific
6406 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6407 // narrowing and commutation of operands should be handled. The actual code
6408 // doesn't include all of those, work in progress...
6409 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6410 if (NewOp.getNode())
6413 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6415 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6416 // unpckh_undef). Only use pshufd if speed is more important than size.
6417 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6418 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6419 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6420 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6422 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6423 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6424 return getMOVDDup(Op, dl, V1, DAG);
6426 if (isMOVHLPS_v_undef_Mask(M, VT))
6427 return getMOVHighToLow(Op, dl, DAG);
6429 // Use to match splats
6430 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6431 (VT == MVT::v2f64 || VT == MVT::v2i64))
6432 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6434 if (isPSHUFDMask(M, VT)) {
6435 // The actual implementation will match the mask in the if above and then
6436 // during isel it can match several different instructions, not only pshufd
6437 // as its name says, sad but true, emulate the behavior for now...
6438 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6439 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6441 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6443 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6444 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6446 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6447 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6449 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6453 // Check if this can be converted into a logical shift.
6454 bool isLeft = false;
6457 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6458 if (isShift && ShVal.hasOneUse()) {
6459 // If the shifted value has multiple uses, it may be cheaper to use
6460 // v_set0 + movlhps or movhlps, etc.
6461 EVT EltVT = VT.getVectorElementType();
6462 ShAmt *= EltVT.getSizeInBits();
6463 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6466 if (isMOVLMask(M, VT)) {
6467 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6468 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6469 if (!isMOVLPMask(M, VT)) {
6470 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6471 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6473 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6474 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6478 // FIXME: fold these into legal mask.
6479 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6480 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6482 if (isMOVHLPSMask(M, VT))
6483 return getMOVHighToLow(Op, dl, DAG);
6485 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6486 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6488 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6489 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6491 if (isMOVLPMask(M, VT))
6492 return getMOVLP(Op, dl, DAG, HasSSE2);
6494 if (ShouldXformToMOVHLPS(M, VT) ||
6495 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6496 return CommuteVectorShuffle(SVOp, DAG);
6499 // No better options. Use a vshldq / vsrldq.
6500 EVT EltVT = VT.getVectorElementType();
6501 ShAmt *= EltVT.getSizeInBits();
6502 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6505 bool Commuted = false;
6506 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6507 // 1,1,1,1 -> v8i16 though.
6508 V1IsSplat = isSplatVector(V1.getNode());
6509 V2IsSplat = isSplatVector(V2.getNode());
6511 // Canonicalize the splat or undef, if present, to be on the RHS.
6512 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6513 CommuteVectorShuffleMask(M, NumElems);
6515 std::swap(V1IsSplat, V2IsSplat);
6519 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6520 // Shuffling low element of v1 into undef, just return v1.
6523 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6524 // the instruction selector will not match, so get a canonical MOVL with
6525 // swapped operands to undo the commute.
6526 return getMOVL(DAG, dl, VT, V2, V1);
6529 if (isUNPCKLMask(M, VT, HasAVX2))
6530 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6532 if (isUNPCKHMask(M, VT, HasAVX2))
6533 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6536 // Normalize mask so all entries that point to V2 points to its first
6537 // element then try to match unpck{h|l} again. If match, return a
6538 // new vector_shuffle with the corrected mask.p
6539 SmallVector<int, 8> NewMask(M.begin(), M.end());
6540 NormalizeMask(NewMask, NumElems);
6541 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) {
6542 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6543 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) {
6544 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6549 // Commute is back and try unpck* again.
6550 // FIXME: this seems wrong.
6551 CommuteVectorShuffleMask(M, NumElems);
6553 std::swap(V1IsSplat, V2IsSplat);
6556 if (isUNPCKLMask(M, VT, HasAVX2))
6557 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6559 if (isUNPCKHMask(M, VT, HasAVX2))
6560 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6563 // Normalize the node to match x86 shuffle ops if needed
6564 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6565 return CommuteVectorShuffle(SVOp, DAG);
6567 // The checks below are all present in isShuffleMaskLegal, but they are
6568 // inlined here right now to enable us to directly emit target specific
6569 // nodes, and remove one by one until they don't return Op anymore.
6571 if (isPALIGNRMask(M, VT, Subtarget))
6572 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6573 getShufflePALIGNRImmediate(SVOp),
6576 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6577 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6578 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6579 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6582 if (isPSHUFHWMask(M, VT))
6583 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6584 getShufflePSHUFHWImmediate(SVOp),
6587 if (isPSHUFLWMask(M, VT))
6588 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6589 getShufflePSHUFLWImmediate(SVOp),
6592 if (isSHUFPMask(M, VT, HasAVX))
6593 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6594 getShuffleSHUFImmediate(SVOp), DAG);
6596 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6597 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6598 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6599 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6601 //===--------------------------------------------------------------------===//
6602 // Generate target specific nodes for 128 or 256-bit shuffles only
6603 // supported in the AVX instruction set.
6606 // Handle VMOVDDUPY permutations
6607 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6608 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6610 // Handle VPERMILPS/D* permutations
6611 if (isVPERMILPMask(M, VT, HasAVX)) {
6612 if (HasAVX2 && VT == MVT::v8i32)
6613 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6614 getShuffleSHUFImmediate(SVOp), DAG);
6615 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6616 getShuffleSHUFImmediate(SVOp), DAG);
6619 // Handle VPERM2F128/VPERM2I128 permutations
6620 if (isVPERM2X128Mask(M, VT, HasAVX))
6621 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6622 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6624 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6625 if (BlendOp.getNode())
6628 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6629 SmallVector<SDValue, 8> permclMask;
6630 for (unsigned i = 0; i != 8; ++i) {
6631 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6633 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6635 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6636 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6637 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6640 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6641 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6642 getShuffleCLImmediate(SVOp), DAG);
6645 //===--------------------------------------------------------------------===//
6646 // Since no target specific shuffle was selected for this generic one,
6647 // lower it into other known shuffles. FIXME: this isn't true yet, but
6648 // this is the plan.
6651 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6652 if (VT == MVT::v8i16) {
6653 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6654 if (NewOp.getNode())
6658 if (VT == MVT::v16i8) {
6659 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6660 if (NewOp.getNode())
6664 // Handle all 128-bit wide vectors with 4 elements, and match them with
6665 // several different shuffle types.
6666 if (NumElems == 4 && VT.getSizeInBits() == 128)
6667 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6669 // Handle general 256-bit shuffles
6670 if (VT.is256BitVector())
6671 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6677 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6678 SelectionDAG &DAG) const {
6679 EVT VT = Op.getValueType();
6680 DebugLoc dl = Op.getDebugLoc();
6682 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6685 if (VT.getSizeInBits() == 8) {
6686 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6687 Op.getOperand(0), Op.getOperand(1));
6688 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6689 DAG.getValueType(VT));
6690 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6691 } else if (VT.getSizeInBits() == 16) {
6692 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6693 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6695 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6696 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6697 DAG.getNode(ISD::BITCAST, dl,
6701 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6702 Op.getOperand(0), Op.getOperand(1));
6703 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6704 DAG.getValueType(VT));
6705 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6706 } else if (VT == MVT::f32) {
6707 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6708 // the result back to FR32 register. It's only worth matching if the
6709 // result has a single use which is a store or a bitcast to i32. And in
6710 // the case of a store, it's not worth it if the index is a constant 0,
6711 // because a MOVSSmr can be used instead, which is smaller and faster.
6712 if (!Op.hasOneUse())
6714 SDNode *User = *Op.getNode()->use_begin();
6715 if ((User->getOpcode() != ISD::STORE ||
6716 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6717 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6718 (User->getOpcode() != ISD::BITCAST ||
6719 User->getValueType(0) != MVT::i32))
6721 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6722 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6725 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6726 } else if (VT == MVT::i32 || VT == MVT::i64) {
6727 // ExtractPS/pextrq works with constant index.
6728 if (isa<ConstantSDNode>(Op.getOperand(1)))
6736 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6737 SelectionDAG &DAG) const {
6738 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6741 SDValue Vec = Op.getOperand(0);
6742 EVT VecVT = Vec.getValueType();
6744 // If this is a 256-bit vector result, first extract the 128-bit vector and
6745 // then extract the element from the 128-bit vector.
6746 if (VecVT.getSizeInBits() == 256) {
6747 DebugLoc dl = Op.getNode()->getDebugLoc();
6748 unsigned NumElems = VecVT.getVectorNumElements();
6749 SDValue Idx = Op.getOperand(1);
6750 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6752 // Get the 128-bit vector.
6753 bool Upper = IdxVal >= NumElems/2;
6754 Vec = Extract128BitVector(Vec, Upper ? NumElems/2 : 0, DAG, dl);
6756 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6757 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6760 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6762 if (Subtarget->hasSSE41()) {
6763 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6768 EVT VT = Op.getValueType();
6769 DebugLoc dl = Op.getDebugLoc();
6770 // TODO: handle v16i8.
6771 if (VT.getSizeInBits() == 16) {
6772 SDValue Vec = Op.getOperand(0);
6773 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6775 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6776 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6777 DAG.getNode(ISD::BITCAST, dl,
6780 // Transform it so it match pextrw which produces a 32-bit result.
6781 EVT EltVT = MVT::i32;
6782 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6783 Op.getOperand(0), Op.getOperand(1));
6784 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6785 DAG.getValueType(VT));
6786 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6787 } else if (VT.getSizeInBits() == 32) {
6788 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6792 // SHUFPS the element to the lowest double word, then movss.
6793 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6794 EVT VVT = Op.getOperand(0).getValueType();
6795 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6796 DAG.getUNDEF(VVT), Mask);
6797 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6798 DAG.getIntPtrConstant(0));
6799 } else if (VT.getSizeInBits() == 64) {
6800 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6801 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6802 // to match extract_elt for f64.
6803 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6807 // UNPCKHPD the element to the lowest double word, then movsd.
6808 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6809 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6810 int Mask[2] = { 1, -1 };
6811 EVT VVT = Op.getOperand(0).getValueType();
6812 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6813 DAG.getUNDEF(VVT), Mask);
6814 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6815 DAG.getIntPtrConstant(0));
6822 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6823 SelectionDAG &DAG) const {
6824 EVT VT = Op.getValueType();
6825 EVT EltVT = VT.getVectorElementType();
6826 DebugLoc dl = Op.getDebugLoc();
6828 SDValue N0 = Op.getOperand(0);
6829 SDValue N1 = Op.getOperand(1);
6830 SDValue N2 = Op.getOperand(2);
6832 if (VT.getSizeInBits() == 256)
6835 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6836 isa<ConstantSDNode>(N2)) {
6838 if (VT == MVT::v8i16)
6839 Opc = X86ISD::PINSRW;
6840 else if (VT == MVT::v16i8)
6841 Opc = X86ISD::PINSRB;
6843 Opc = X86ISD::PINSRB;
6845 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6847 if (N1.getValueType() != MVT::i32)
6848 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6849 if (N2.getValueType() != MVT::i32)
6850 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6851 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6852 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6853 // Bits [7:6] of the constant are the source select. This will always be
6854 // zero here. The DAG Combiner may combine an extract_elt index into these
6855 // bits. For example (insert (extract, 3), 2) could be matched by putting
6856 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6857 // Bits [5:4] of the constant are the destination select. This is the
6858 // value of the incoming immediate.
6859 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6860 // combine either bitwise AND or insert of float 0.0 to set these bits.
6861 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6862 // Create this as a scalar to vector..
6863 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6864 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6865 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6866 isa<ConstantSDNode>(N2)) {
6867 // PINSR* works with constant index.
6874 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6875 EVT VT = Op.getValueType();
6876 EVT EltVT = VT.getVectorElementType();
6878 DebugLoc dl = Op.getDebugLoc();
6879 SDValue N0 = Op.getOperand(0);
6880 SDValue N1 = Op.getOperand(1);
6881 SDValue N2 = Op.getOperand(2);
6883 // If this is a 256-bit vector result, first extract the 128-bit vector,
6884 // insert the element into the extracted half and then place it back.
6885 if (VT.getSizeInBits() == 256) {
6886 if (!isa<ConstantSDNode>(N2))
6889 // Get the desired 128-bit vector half.
6890 unsigned NumElems = VT.getVectorNumElements();
6891 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6892 bool Upper = IdxVal >= NumElems/2;
6893 unsigned Ins128Idx = Upper ? NumElems/2 : 0;
6894 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6896 // Insert the element into the desired half.
6897 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6898 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6900 // Insert the changed part back to the 256-bit vector
6901 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6904 if (Subtarget->hasSSE41())
6905 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6907 if (EltVT == MVT::i8)
6910 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6911 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6912 // as its second argument.
6913 if (N1.getValueType() != MVT::i32)
6914 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6915 if (N2.getValueType() != MVT::i32)
6916 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6917 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6923 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6924 LLVMContext *Context = DAG.getContext();
6925 DebugLoc dl = Op.getDebugLoc();
6926 EVT OpVT = Op.getValueType();
6928 // If this is a 256-bit vector result, first insert into a 128-bit
6929 // vector and then insert into the 256-bit vector.
6930 if (OpVT.getSizeInBits() > 128) {
6931 // Insert into a 128-bit vector.
6932 EVT VT128 = EVT::getVectorVT(*Context,
6933 OpVT.getVectorElementType(),
6934 OpVT.getVectorNumElements() / 2);
6936 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6938 // Insert the 128-bit vector.
6939 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
6942 if (Op.getValueType() == MVT::v1i64 &&
6943 Op.getOperand(0).getValueType() == MVT::i64)
6944 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6946 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6947 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6948 "Expected an SSE type!");
6949 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6950 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6953 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6954 // a simple subregister reference or explicit instructions to grab
6955 // upper bits of a vector.
6957 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6958 if (Subtarget->hasAVX()) {
6959 DebugLoc dl = Op.getNode()->getDebugLoc();
6960 SDValue Vec = Op.getNode()->getOperand(0);
6961 SDValue Idx = Op.getNode()->getOperand(1);
6963 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
6964 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
6965 isa<ConstantSDNode>(Idx)) {
6966 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6967 return Extract128BitVector(Vec, IdxVal, DAG, dl);
6973 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6974 // simple superregister reference or explicit instructions to insert
6975 // the upper bits of a vector.
6977 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6978 if (Subtarget->hasAVX()) {
6979 DebugLoc dl = Op.getNode()->getDebugLoc();
6980 SDValue Vec = Op.getNode()->getOperand(0);
6981 SDValue SubVec = Op.getNode()->getOperand(1);
6982 SDValue Idx = Op.getNode()->getOperand(2);
6984 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
6985 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
6986 isa<ConstantSDNode>(Idx)) {
6987 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6988 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
6994 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6995 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6996 // one of the above mentioned nodes. It has to be wrapped because otherwise
6997 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6998 // be used to form addressing mode. These wrapped nodes will be selected
7001 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7002 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7004 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7006 unsigned char OpFlag = 0;
7007 unsigned WrapperKind = X86ISD::Wrapper;
7008 CodeModel::Model M = getTargetMachine().getCodeModel();
7010 if (Subtarget->isPICStyleRIPRel() &&
7011 (M == CodeModel::Small || M == CodeModel::Kernel))
7012 WrapperKind = X86ISD::WrapperRIP;
7013 else if (Subtarget->isPICStyleGOT())
7014 OpFlag = X86II::MO_GOTOFF;
7015 else if (Subtarget->isPICStyleStubPIC())
7016 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7018 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7020 CP->getOffset(), OpFlag);
7021 DebugLoc DL = CP->getDebugLoc();
7022 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7023 // With PIC, the address is actually $g + Offset.
7025 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7026 DAG.getNode(X86ISD::GlobalBaseReg,
7027 DebugLoc(), getPointerTy()),
7034 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7035 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7037 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7039 unsigned char OpFlag = 0;
7040 unsigned WrapperKind = X86ISD::Wrapper;
7041 CodeModel::Model M = getTargetMachine().getCodeModel();
7043 if (Subtarget->isPICStyleRIPRel() &&
7044 (M == CodeModel::Small || M == CodeModel::Kernel))
7045 WrapperKind = X86ISD::WrapperRIP;
7046 else if (Subtarget->isPICStyleGOT())
7047 OpFlag = X86II::MO_GOTOFF;
7048 else if (Subtarget->isPICStyleStubPIC())
7049 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7051 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7053 DebugLoc DL = JT->getDebugLoc();
7054 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7056 // With PIC, the address is actually $g + Offset.
7058 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7059 DAG.getNode(X86ISD::GlobalBaseReg,
7060 DebugLoc(), getPointerTy()),
7067 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7068 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7070 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7072 unsigned char OpFlag = 0;
7073 unsigned WrapperKind = X86ISD::Wrapper;
7074 CodeModel::Model M = getTargetMachine().getCodeModel();
7076 if (Subtarget->isPICStyleRIPRel() &&
7077 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7078 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7079 OpFlag = X86II::MO_GOTPCREL;
7080 WrapperKind = X86ISD::WrapperRIP;
7081 } else if (Subtarget->isPICStyleGOT()) {
7082 OpFlag = X86II::MO_GOT;
7083 } else if (Subtarget->isPICStyleStubPIC()) {
7084 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7085 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7086 OpFlag = X86II::MO_DARWIN_NONLAZY;
7089 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7091 DebugLoc DL = Op.getDebugLoc();
7092 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7095 // With PIC, the address is actually $g + Offset.
7096 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7097 !Subtarget->is64Bit()) {
7098 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7099 DAG.getNode(X86ISD::GlobalBaseReg,
7100 DebugLoc(), getPointerTy()),
7104 // For symbols that require a load from a stub to get the address, emit the
7106 if (isGlobalStubReference(OpFlag))
7107 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7108 MachinePointerInfo::getGOT(), false, false, false, 0);
7114 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7115 // Create the TargetBlockAddressAddress node.
7116 unsigned char OpFlags =
7117 Subtarget->ClassifyBlockAddressReference();
7118 CodeModel::Model M = getTargetMachine().getCodeModel();
7119 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7120 DebugLoc dl = Op.getDebugLoc();
7121 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7122 /*isTarget=*/true, OpFlags);
7124 if (Subtarget->isPICStyleRIPRel() &&
7125 (M == CodeModel::Small || M == CodeModel::Kernel))
7126 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7128 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7130 // With PIC, the address is actually $g + Offset.
7131 if (isGlobalRelativeToPICBase(OpFlags)) {
7132 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7133 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7141 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7143 SelectionDAG &DAG) const {
7144 // Create the TargetGlobalAddress node, folding in the constant
7145 // offset if it is legal.
7146 unsigned char OpFlags =
7147 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7148 CodeModel::Model M = getTargetMachine().getCodeModel();
7150 if (OpFlags == X86II::MO_NO_FLAG &&
7151 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7152 // A direct static reference to a global.
7153 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7156 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7159 if (Subtarget->isPICStyleRIPRel() &&
7160 (M == CodeModel::Small || M == CodeModel::Kernel))
7161 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7163 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7165 // With PIC, the address is actually $g + Offset.
7166 if (isGlobalRelativeToPICBase(OpFlags)) {
7167 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7168 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7172 // For globals that require a load from a stub to get the address, emit the
7174 if (isGlobalStubReference(OpFlags))
7175 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7176 MachinePointerInfo::getGOT(), false, false, false, 0);
7178 // If there was a non-zero offset that we didn't fold, create an explicit
7181 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7182 DAG.getConstant(Offset, getPointerTy()));
7188 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7189 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7190 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7191 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7195 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7196 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7197 unsigned char OperandFlags) {
7198 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7199 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7200 DebugLoc dl = GA->getDebugLoc();
7201 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7202 GA->getValueType(0),
7206 SDValue Ops[] = { Chain, TGA, *InFlag };
7207 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7209 SDValue Ops[] = { Chain, TGA };
7210 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7213 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7214 MFI->setAdjustsStack(true);
7216 SDValue Flag = Chain.getValue(1);
7217 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7220 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7222 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7225 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7226 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7227 DAG.getNode(X86ISD::GlobalBaseReg,
7228 DebugLoc(), PtrVT), InFlag);
7229 InFlag = Chain.getValue(1);
7231 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7234 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7236 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7238 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7239 X86::RAX, X86II::MO_TLSGD);
7242 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7243 // "local exec" model.
7244 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7245 const EVT PtrVT, TLSModel::Model model,
7247 DebugLoc dl = GA->getDebugLoc();
7249 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7250 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7251 is64Bit ? 257 : 256));
7253 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7254 DAG.getIntPtrConstant(0),
7255 MachinePointerInfo(Ptr),
7256 false, false, false, 0);
7258 unsigned char OperandFlags = 0;
7259 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7261 unsigned WrapperKind = X86ISD::Wrapper;
7262 if (model == TLSModel::LocalExec) {
7263 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7264 } else if (is64Bit) {
7265 assert(model == TLSModel::InitialExec);
7266 OperandFlags = X86II::MO_GOTTPOFF;
7267 WrapperKind = X86ISD::WrapperRIP;
7269 assert(model == TLSModel::InitialExec);
7270 OperandFlags = X86II::MO_INDNTPOFF;
7273 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7275 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7276 GA->getValueType(0),
7277 GA->getOffset(), OperandFlags);
7278 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7280 if (model == TLSModel::InitialExec)
7281 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7282 MachinePointerInfo::getGOT(), false, false, false, 0);
7284 // The address of the thread local variable is the add of the thread
7285 // pointer with the offset of the variable.
7286 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7290 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7292 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7293 const GlobalValue *GV = GA->getGlobal();
7295 if (Subtarget->isTargetELF()) {
7296 // TODO: implement the "local dynamic" model
7297 // TODO: implement the "initial exec"model for pic executables
7299 // If GV is an alias then use the aliasee for determining
7300 // thread-localness.
7301 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7302 GV = GA->resolveAliasedGlobal(false);
7304 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7307 case TLSModel::GeneralDynamic:
7308 case TLSModel::LocalDynamic: // not implemented
7309 if (Subtarget->is64Bit())
7310 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7311 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7313 case TLSModel::InitialExec:
7314 case TLSModel::LocalExec:
7315 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7316 Subtarget->is64Bit());
7318 llvm_unreachable("Unknown TLS model.");
7321 if (Subtarget->isTargetDarwin()) {
7322 // Darwin only has one model of TLS. Lower to that.
7323 unsigned char OpFlag = 0;
7324 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7325 X86ISD::WrapperRIP : X86ISD::Wrapper;
7327 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7329 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7330 !Subtarget->is64Bit();
7332 OpFlag = X86II::MO_TLVP_PIC_BASE;
7334 OpFlag = X86II::MO_TLVP;
7335 DebugLoc DL = Op.getDebugLoc();
7336 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7337 GA->getValueType(0),
7338 GA->getOffset(), OpFlag);
7339 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7341 // With PIC32, the address is actually $g + Offset.
7343 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7344 DAG.getNode(X86ISD::GlobalBaseReg,
7345 DebugLoc(), getPointerTy()),
7348 // Lowering the machine isd will make sure everything is in the right
7350 SDValue Chain = DAG.getEntryNode();
7351 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7352 SDValue Args[] = { Chain, Offset };
7353 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7355 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7356 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7357 MFI->setAdjustsStack(true);
7359 // And our return value (tls address) is in the standard call return value
7361 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7362 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7366 if (Subtarget->isTargetWindows()) {
7367 // Just use the implicit TLS architecture
7368 // Need to generate someting similar to:
7369 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7371 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7372 // mov rcx, qword [rdx+rcx*8]
7373 // mov eax, .tls$:tlsvar
7374 // [rax+rcx] contains the address
7375 // Windows 64bit: gs:0x58
7376 // Windows 32bit: fs:__tls_array
7378 // If GV is an alias then use the aliasee for determining
7379 // thread-localness.
7380 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7381 GV = GA->resolveAliasedGlobal(false);
7382 DebugLoc dl = GA->getDebugLoc();
7383 SDValue Chain = DAG.getEntryNode();
7385 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7386 // %gs:0x58 (64-bit).
7387 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7388 ? Type::getInt8PtrTy(*DAG.getContext(),
7390 : Type::getInt32PtrTy(*DAG.getContext(),
7393 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7394 Subtarget->is64Bit()
7395 ? DAG.getIntPtrConstant(0x58)
7396 : DAG.getExternalSymbol("_tls_array",
7398 MachinePointerInfo(Ptr),
7399 false, false, false, 0);
7401 // Load the _tls_index variable
7402 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7403 if (Subtarget->is64Bit())
7404 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7405 IDX, MachinePointerInfo(), MVT::i32,
7408 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7409 false, false, false, 0);
7411 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7413 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7415 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7416 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7417 false, false, false, 0);
7419 // Get the offset of start of .tls section
7420 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7421 GA->getValueType(0),
7422 GA->getOffset(), X86II::MO_SECREL);
7423 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7425 // The address of the thread local variable is the add of the thread
7426 // pointer with the offset of the variable.
7427 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7430 llvm_unreachable("TLS not implemented for this target.");
7434 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7435 /// and take a 2 x i32 value to shift plus a shift amount.
7436 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7437 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7438 EVT VT = Op.getValueType();
7439 unsigned VTBits = VT.getSizeInBits();
7440 DebugLoc dl = Op.getDebugLoc();
7441 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7442 SDValue ShOpLo = Op.getOperand(0);
7443 SDValue ShOpHi = Op.getOperand(1);
7444 SDValue ShAmt = Op.getOperand(2);
7445 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7446 DAG.getConstant(VTBits - 1, MVT::i8))
7447 : DAG.getConstant(0, VT);
7450 if (Op.getOpcode() == ISD::SHL_PARTS) {
7451 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7452 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7454 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7455 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7458 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7459 DAG.getConstant(VTBits, MVT::i8));
7460 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7461 AndNode, DAG.getConstant(0, MVT::i8));
7464 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7465 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7466 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7468 if (Op.getOpcode() == ISD::SHL_PARTS) {
7469 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7470 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7472 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7473 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7476 SDValue Ops[2] = { Lo, Hi };
7477 return DAG.getMergeValues(Ops, 2, dl);
7480 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7481 SelectionDAG &DAG) const {
7482 EVT SrcVT = Op.getOperand(0).getValueType();
7484 if (SrcVT.isVector())
7487 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7488 "Unknown SINT_TO_FP to lower!");
7490 // These are really Legal; return the operand so the caller accepts it as
7492 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7494 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7495 Subtarget->is64Bit()) {
7499 DebugLoc dl = Op.getDebugLoc();
7500 unsigned Size = SrcVT.getSizeInBits()/8;
7501 MachineFunction &MF = DAG.getMachineFunction();
7502 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7503 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7504 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7506 MachinePointerInfo::getFixedStack(SSFI),
7508 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7511 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7513 SelectionDAG &DAG) const {
7515 DebugLoc DL = Op.getDebugLoc();
7517 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7519 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7521 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7523 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7525 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7526 MachineMemOperand *MMO;
7528 int SSFI = FI->getIndex();
7530 DAG.getMachineFunction()
7531 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7532 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7534 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7535 StackSlot = StackSlot.getOperand(1);
7537 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7538 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7540 Tys, Ops, array_lengthof(Ops),
7544 Chain = Result.getValue(1);
7545 SDValue InFlag = Result.getValue(2);
7547 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7548 // shouldn't be necessary except that RFP cannot be live across
7549 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7550 MachineFunction &MF = DAG.getMachineFunction();
7551 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7552 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7553 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7554 Tys = DAG.getVTList(MVT::Other);
7556 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7558 MachineMemOperand *MMO =
7559 DAG.getMachineFunction()
7560 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7561 MachineMemOperand::MOStore, SSFISize, SSFISize);
7563 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7564 Ops, array_lengthof(Ops),
7565 Op.getValueType(), MMO);
7566 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7567 MachinePointerInfo::getFixedStack(SSFI),
7568 false, false, false, 0);
7574 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7575 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7576 SelectionDAG &DAG) const {
7577 // This algorithm is not obvious. Here it is what we're trying to output:
7580 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7581 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7585 pshufd $0x4e, %xmm0, %xmm1
7590 DebugLoc dl = Op.getDebugLoc();
7591 LLVMContext *Context = DAG.getContext();
7593 // Build some magic constants.
7594 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7595 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7596 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7598 SmallVector<Constant*,2> CV1;
7600 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7602 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7603 Constant *C1 = ConstantVector::get(CV1);
7604 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7606 // Load the 64-bit value into an XMM register.
7607 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7609 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7610 MachinePointerInfo::getConstantPool(),
7611 false, false, false, 16);
7612 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7613 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7616 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7617 MachinePointerInfo::getConstantPool(),
7618 false, false, false, 16);
7619 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7620 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7623 if (Subtarget->hasSSE3()) {
7624 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7625 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7627 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7628 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7630 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7631 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7635 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7636 DAG.getIntPtrConstant(0));
7639 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7640 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7641 SelectionDAG &DAG) const {
7642 DebugLoc dl = Op.getDebugLoc();
7643 // FP constant to bias correct the final result.
7644 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7647 // Load the 32-bit value into an XMM register.
7648 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7651 // Zero out the upper parts of the register.
7652 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7654 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7655 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7656 DAG.getIntPtrConstant(0));
7658 // Or the load with the bias.
7659 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7660 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7661 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7663 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7664 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7665 MVT::v2f64, Bias)));
7666 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7667 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7668 DAG.getIntPtrConstant(0));
7670 // Subtract the bias.
7671 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7673 // Handle final rounding.
7674 EVT DestVT = Op.getValueType();
7676 if (DestVT.bitsLT(MVT::f64)) {
7677 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7678 DAG.getIntPtrConstant(0));
7679 } else if (DestVT.bitsGT(MVT::f64)) {
7680 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7683 // Handle final rounding.
7687 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7688 SelectionDAG &DAG) const {
7689 SDValue N0 = Op.getOperand(0);
7690 DebugLoc dl = Op.getDebugLoc();
7692 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7693 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7694 // the optimization here.
7695 if (DAG.SignBitIsZero(N0))
7696 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7698 EVT SrcVT = N0.getValueType();
7699 EVT DstVT = Op.getValueType();
7700 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7701 return LowerUINT_TO_FP_i64(Op, DAG);
7702 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7703 return LowerUINT_TO_FP_i32(Op, DAG);
7704 else if (Subtarget->is64Bit() &&
7705 SrcVT == MVT::i64 && DstVT == MVT::f32)
7708 // Make a 64-bit buffer, and use it to build an FILD.
7709 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7710 if (SrcVT == MVT::i32) {
7711 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7712 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7713 getPointerTy(), StackSlot, WordOff);
7714 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7715 StackSlot, MachinePointerInfo(),
7717 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7718 OffsetSlot, MachinePointerInfo(),
7720 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7724 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7725 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7726 StackSlot, MachinePointerInfo(),
7728 // For i64 source, we need to add the appropriate power of 2 if the input
7729 // was negative. This is the same as the optimization in
7730 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7731 // we must be careful to do the computation in x87 extended precision, not
7732 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7733 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7734 MachineMemOperand *MMO =
7735 DAG.getMachineFunction()
7736 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7737 MachineMemOperand::MOLoad, 8, 8);
7739 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7740 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7741 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7744 APInt FF(32, 0x5F800000ULL);
7746 // Check whether the sign bit is set.
7747 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7748 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7751 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7752 SDValue FudgePtr = DAG.getConstantPool(
7753 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7756 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7757 SDValue Zero = DAG.getIntPtrConstant(0);
7758 SDValue Four = DAG.getIntPtrConstant(4);
7759 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7761 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7763 // Load the value out, extending it from f32 to f80.
7764 // FIXME: Avoid the extend by constructing the right constant pool?
7765 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7766 FudgePtr, MachinePointerInfo::getConstantPool(),
7767 MVT::f32, false, false, 4);
7768 // Extend everything to 80 bits to force it to be done on x87.
7769 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7770 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7773 std::pair<SDValue,SDValue> X86TargetLowering::
7774 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7775 DebugLoc DL = Op.getDebugLoc();
7777 EVT DstTy = Op.getValueType();
7779 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7780 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7784 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7785 DstTy.getSimpleVT() >= MVT::i16 &&
7786 "Unknown FP_TO_INT to lower!");
7788 // These are really Legal.
7789 if (DstTy == MVT::i32 &&
7790 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7791 return std::make_pair(SDValue(), SDValue());
7792 if (Subtarget->is64Bit() &&
7793 DstTy == MVT::i64 &&
7794 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7795 return std::make_pair(SDValue(), SDValue());
7797 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7798 // stack slot, or into the FTOL runtime function.
7799 MachineFunction &MF = DAG.getMachineFunction();
7800 unsigned MemSize = DstTy.getSizeInBits()/8;
7801 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7802 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7805 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7806 Opc = X86ISD::WIN_FTOL;
7808 switch (DstTy.getSimpleVT().SimpleTy) {
7809 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7810 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7811 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7812 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7815 SDValue Chain = DAG.getEntryNode();
7816 SDValue Value = Op.getOperand(0);
7817 EVT TheVT = Op.getOperand(0).getValueType();
7818 // FIXME This causes a redundant load/store if the SSE-class value is already
7819 // in memory, such as if it is on the callstack.
7820 if (isScalarFPTypeInSSEReg(TheVT)) {
7821 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7822 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7823 MachinePointerInfo::getFixedStack(SSFI),
7825 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7827 Chain, StackSlot, DAG.getValueType(TheVT)
7830 MachineMemOperand *MMO =
7831 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7832 MachineMemOperand::MOLoad, MemSize, MemSize);
7833 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7835 Chain = Value.getValue(1);
7836 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7837 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7840 MachineMemOperand *MMO =
7841 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7842 MachineMemOperand::MOStore, MemSize, MemSize);
7844 if (Opc != X86ISD::WIN_FTOL) {
7845 // Build the FP_TO_INT*_IN_MEM
7846 SDValue Ops[] = { Chain, Value, StackSlot };
7847 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7848 Ops, 3, DstTy, MMO);
7849 return std::make_pair(FIST, StackSlot);
7851 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7852 DAG.getVTList(MVT::Other, MVT::Glue),
7854 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7855 MVT::i32, ftol.getValue(1));
7856 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7857 MVT::i32, eax.getValue(2));
7858 SDValue Ops[] = { eax, edx };
7859 SDValue pair = IsReplace
7860 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7861 : DAG.getMergeValues(Ops, 2, DL);
7862 return std::make_pair(pair, SDValue());
7866 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7867 SelectionDAG &DAG) const {
7868 if (Op.getValueType().isVector())
7871 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7872 /*IsSigned=*/ true, /*IsReplace=*/ false);
7873 SDValue FIST = Vals.first, StackSlot = Vals.second;
7874 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7875 if (FIST.getNode() == 0) return Op;
7877 if (StackSlot.getNode())
7879 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7880 FIST, StackSlot, MachinePointerInfo(),
7881 false, false, false, 0);
7883 // The node is the result.
7887 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7888 SelectionDAG &DAG) const {
7889 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7890 /*IsSigned=*/ false, /*IsReplace=*/ false);
7891 SDValue FIST = Vals.first, StackSlot = Vals.second;
7892 assert(FIST.getNode() && "Unexpected failure");
7894 if (StackSlot.getNode())
7896 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7897 FIST, StackSlot, MachinePointerInfo(),
7898 false, false, false, 0);
7900 // The node is the result.
7904 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7905 SelectionDAG &DAG) const {
7906 LLVMContext *Context = DAG.getContext();
7907 DebugLoc dl = Op.getDebugLoc();
7908 EVT VT = Op.getValueType();
7911 EltVT = VT.getVectorElementType();
7913 if (EltVT == MVT::f64) {
7914 C = ConstantVector::getSplat(2,
7915 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7917 C = ConstantVector::getSplat(4,
7918 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7920 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7921 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7922 MachinePointerInfo::getConstantPool(),
7923 false, false, false, 16);
7924 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7927 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7928 LLVMContext *Context = DAG.getContext();
7929 DebugLoc dl = Op.getDebugLoc();
7930 EVT VT = Op.getValueType();
7932 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7933 if (VT.isVector()) {
7934 EltVT = VT.getVectorElementType();
7935 NumElts = VT.getVectorNumElements();
7938 if (EltVT == MVT::f64)
7939 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7941 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7942 C = ConstantVector::getSplat(NumElts, C);
7943 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7944 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7945 MachinePointerInfo::getConstantPool(),
7946 false, false, false, 16);
7947 if (VT.isVector()) {
7948 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7949 return DAG.getNode(ISD::BITCAST, dl, VT,
7950 DAG.getNode(ISD::XOR, dl, XORVT,
7951 DAG.getNode(ISD::BITCAST, dl, XORVT,
7953 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7955 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7959 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7960 LLVMContext *Context = DAG.getContext();
7961 SDValue Op0 = Op.getOperand(0);
7962 SDValue Op1 = Op.getOperand(1);
7963 DebugLoc dl = Op.getDebugLoc();
7964 EVT VT = Op.getValueType();
7965 EVT SrcVT = Op1.getValueType();
7967 // If second operand is smaller, extend it first.
7968 if (SrcVT.bitsLT(VT)) {
7969 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7972 // And if it is bigger, shrink it first.
7973 if (SrcVT.bitsGT(VT)) {
7974 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7978 // At this point the operands and the result should have the same
7979 // type, and that won't be f80 since that is not custom lowered.
7981 // First get the sign bit of second operand.
7982 SmallVector<Constant*,4> CV;
7983 if (SrcVT == MVT::f64) {
7984 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7985 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7987 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7988 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7989 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7990 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7992 Constant *C = ConstantVector::get(CV);
7993 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7994 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7995 MachinePointerInfo::getConstantPool(),
7996 false, false, false, 16);
7997 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7999 // Shift sign bit right or left if the two operands have different types.
8000 if (SrcVT.bitsGT(VT)) {
8001 // Op0 is MVT::f32, Op1 is MVT::f64.
8002 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8003 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8004 DAG.getConstant(32, MVT::i32));
8005 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8006 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8007 DAG.getIntPtrConstant(0));
8010 // Clear first operand sign bit.
8012 if (VT == MVT::f64) {
8013 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8014 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8016 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8017 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8018 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8019 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8021 C = ConstantVector::get(CV);
8022 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8023 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8024 MachinePointerInfo::getConstantPool(),
8025 false, false, false, 16);
8026 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8028 // Or the value with the sign bit.
8029 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8032 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8033 SDValue N0 = Op.getOperand(0);
8034 DebugLoc dl = Op.getDebugLoc();
8035 EVT VT = Op.getValueType();
8037 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8038 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8039 DAG.getConstant(1, VT));
8040 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8043 /// Emit nodes that will be selected as "test Op0,Op0", or something
8045 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8046 SelectionDAG &DAG) const {
8047 DebugLoc dl = Op.getDebugLoc();
8049 // CF and OF aren't always set the way we want. Determine which
8050 // of these we need.
8051 bool NeedCF = false;
8052 bool NeedOF = false;
8055 case X86::COND_A: case X86::COND_AE:
8056 case X86::COND_B: case X86::COND_BE:
8059 case X86::COND_G: case X86::COND_GE:
8060 case X86::COND_L: case X86::COND_LE:
8061 case X86::COND_O: case X86::COND_NO:
8066 // See if we can use the EFLAGS value from the operand instead of
8067 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8068 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8069 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8070 // Emit a CMP with 0, which is the TEST pattern.
8071 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8072 DAG.getConstant(0, Op.getValueType()));
8074 unsigned Opcode = 0;
8075 unsigned NumOperands = 0;
8076 switch (Op.getNode()->getOpcode()) {
8078 // Due to an isel shortcoming, be conservative if this add is likely to be
8079 // selected as part of a load-modify-store instruction. When the root node
8080 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8081 // uses of other nodes in the match, such as the ADD in this case. This
8082 // leads to the ADD being left around and reselected, with the result being
8083 // two adds in the output. Alas, even if none our users are stores, that
8084 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8085 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8086 // climbing the DAG back to the root, and it doesn't seem to be worth the
8088 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8089 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8090 if (UI->getOpcode() != ISD::CopyToReg &&
8091 UI->getOpcode() != ISD::SETCC &&
8092 UI->getOpcode() != ISD::STORE)
8095 if (ConstantSDNode *C =
8096 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8097 // An add of one will be selected as an INC.
8098 if (C->getAPIntValue() == 1) {
8099 Opcode = X86ISD::INC;
8104 // An add of negative one (subtract of one) will be selected as a DEC.
8105 if (C->getAPIntValue().isAllOnesValue()) {
8106 Opcode = X86ISD::DEC;
8112 // Otherwise use a regular EFLAGS-setting add.
8113 Opcode = X86ISD::ADD;
8117 // If the primary and result isn't used, don't bother using X86ISD::AND,
8118 // because a TEST instruction will be better.
8119 bool NonFlagUse = false;
8120 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8121 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8123 unsigned UOpNo = UI.getOperandNo();
8124 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8125 // Look pass truncate.
8126 UOpNo = User->use_begin().getOperandNo();
8127 User = *User->use_begin();
8130 if (User->getOpcode() != ISD::BRCOND &&
8131 User->getOpcode() != ISD::SETCC &&
8132 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8145 // Due to the ISEL shortcoming noted above, be conservative if this op is
8146 // likely to be selected as part of a load-modify-store instruction.
8147 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8148 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8149 if (UI->getOpcode() == ISD::STORE)
8152 // Otherwise use a regular EFLAGS-setting instruction.
8153 switch (Op.getNode()->getOpcode()) {
8154 default: llvm_unreachable("unexpected operator!");
8155 case ISD::SUB: Opcode = X86ISD::SUB; break;
8156 case ISD::OR: Opcode = X86ISD::OR; break;
8157 case ISD::XOR: Opcode = X86ISD::XOR; break;
8158 case ISD::AND: Opcode = X86ISD::AND; break;
8170 return SDValue(Op.getNode(), 1);
8177 // Emit a CMP with 0, which is the TEST pattern.
8178 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8179 DAG.getConstant(0, Op.getValueType()));
8181 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8182 SmallVector<SDValue, 4> Ops;
8183 for (unsigned i = 0; i != NumOperands; ++i)
8184 Ops.push_back(Op.getOperand(i));
8186 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8187 DAG.ReplaceAllUsesWith(Op, New);
8188 return SDValue(New.getNode(), 1);
8191 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8193 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8194 SelectionDAG &DAG) const {
8195 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8196 if (C->getAPIntValue() == 0)
8197 return EmitTest(Op0, X86CC, DAG);
8199 DebugLoc dl = Op0.getDebugLoc();
8200 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8203 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8204 /// if it's possible.
8205 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8206 DebugLoc dl, SelectionDAG &DAG) const {
8207 SDValue Op0 = And.getOperand(0);
8208 SDValue Op1 = And.getOperand(1);
8209 if (Op0.getOpcode() == ISD::TRUNCATE)
8210 Op0 = Op0.getOperand(0);
8211 if (Op1.getOpcode() == ISD::TRUNCATE)
8212 Op1 = Op1.getOperand(0);
8215 if (Op1.getOpcode() == ISD::SHL)
8216 std::swap(Op0, Op1);
8217 if (Op0.getOpcode() == ISD::SHL) {
8218 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8219 if (And00C->getZExtValue() == 1) {
8220 // If we looked past a truncate, check that it's only truncating away
8222 unsigned BitWidth = Op0.getValueSizeInBits();
8223 unsigned AndBitWidth = And.getValueSizeInBits();
8224 if (BitWidth > AndBitWidth) {
8226 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8227 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8231 RHS = Op0.getOperand(1);
8233 } else if (Op1.getOpcode() == ISD::Constant) {
8234 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8235 uint64_t AndRHSVal = AndRHS->getZExtValue();
8236 SDValue AndLHS = Op0;
8238 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8239 LHS = AndLHS.getOperand(0);
8240 RHS = AndLHS.getOperand(1);
8243 // Use BT if the immediate can't be encoded in a TEST instruction.
8244 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8246 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8250 if (LHS.getNode()) {
8251 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8252 // instruction. Since the shift amount is in-range-or-undefined, we know
8253 // that doing a bittest on the i32 value is ok. We extend to i32 because
8254 // the encoding for the i16 version is larger than the i32 version.
8255 // Also promote i16 to i32 for performance / code size reason.
8256 if (LHS.getValueType() == MVT::i8 ||
8257 LHS.getValueType() == MVT::i16)
8258 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8260 // If the operand types disagree, extend the shift amount to match. Since
8261 // BT ignores high bits (like shifts) we can use anyextend.
8262 if (LHS.getValueType() != RHS.getValueType())
8263 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8265 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8266 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8267 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8268 DAG.getConstant(Cond, MVT::i8), BT);
8274 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8276 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8278 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8279 SDValue Op0 = Op.getOperand(0);
8280 SDValue Op1 = Op.getOperand(1);
8281 DebugLoc dl = Op.getDebugLoc();
8282 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8284 // Optimize to BT if possible.
8285 // Lower (X & (1 << N)) == 0 to BT(X, N).
8286 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8287 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8288 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8289 Op1.getOpcode() == ISD::Constant &&
8290 cast<ConstantSDNode>(Op1)->isNullValue() &&
8291 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8292 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8293 if (NewSetCC.getNode())
8297 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8299 if (Op1.getOpcode() == ISD::Constant &&
8300 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8301 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8302 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8304 // If the input is a setcc, then reuse the input setcc or use a new one with
8305 // the inverted condition.
8306 if (Op0.getOpcode() == X86ISD::SETCC) {
8307 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8308 bool Invert = (CC == ISD::SETNE) ^
8309 cast<ConstantSDNode>(Op1)->isNullValue();
8310 if (!Invert) return Op0;
8312 CCode = X86::GetOppositeBranchCondition(CCode);
8313 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8314 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8318 bool isFP = Op1.getValueType().isFloatingPoint();
8319 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8320 if (X86CC == X86::COND_INVALID)
8323 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8324 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8325 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8328 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8329 // ones, and then concatenate the result back.
8330 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8331 EVT VT = Op.getValueType();
8333 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8334 "Unsupported value type for operation");
8336 int NumElems = VT.getVectorNumElements();
8337 DebugLoc dl = Op.getDebugLoc();
8338 SDValue CC = Op.getOperand(2);
8340 // Extract the LHS vectors
8341 SDValue LHS = Op.getOperand(0);
8342 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8343 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8345 // Extract the RHS vectors
8346 SDValue RHS = Op.getOperand(1);
8347 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8348 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8350 // Issue the operation on the smaller types and concatenate the result back
8351 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8352 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8353 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8354 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8355 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8359 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8361 SDValue Op0 = Op.getOperand(0);
8362 SDValue Op1 = Op.getOperand(1);
8363 SDValue CC = Op.getOperand(2);
8364 EVT VT = Op.getValueType();
8365 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8366 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8367 DebugLoc dl = Op.getDebugLoc();
8371 EVT EltVT = Op0.getValueType().getVectorElementType();
8372 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8376 // SSE Condition code mapping:
8385 switch (SetCCOpcode) {
8388 case ISD::SETEQ: SSECC = 0; break;
8390 case ISD::SETGT: Swap = true; // Fallthrough
8392 case ISD::SETOLT: SSECC = 1; break;
8394 case ISD::SETGE: Swap = true; // Fallthrough
8396 case ISD::SETOLE: SSECC = 2; break;
8397 case ISD::SETUO: SSECC = 3; break;
8399 case ISD::SETNE: SSECC = 4; break;
8400 case ISD::SETULE: Swap = true;
8401 case ISD::SETUGE: SSECC = 5; break;
8402 case ISD::SETULT: Swap = true;
8403 case ISD::SETUGT: SSECC = 6; break;
8404 case ISD::SETO: SSECC = 7; break;
8407 std::swap(Op0, Op1);
8409 // In the two special cases we can't handle, emit two comparisons.
8411 if (SetCCOpcode == ISD::SETUEQ) {
8413 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8414 DAG.getConstant(3, MVT::i8));
8415 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8416 DAG.getConstant(0, MVT::i8));
8417 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8418 } else if (SetCCOpcode == ISD::SETONE) {
8420 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8421 DAG.getConstant(7, MVT::i8));
8422 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8423 DAG.getConstant(4, MVT::i8));
8424 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8426 llvm_unreachable("Illegal FP comparison");
8428 // Handle all other FP comparisons here.
8429 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8430 DAG.getConstant(SSECC, MVT::i8));
8433 // Break 256-bit integer vector compare into smaller ones.
8434 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8435 return Lower256IntVSETCC(Op, DAG);
8437 // We are handling one of the integer comparisons here. Since SSE only has
8438 // GT and EQ comparisons for integer, swapping operands and multiple
8439 // operations may be required for some comparisons.
8441 bool Swap = false, Invert = false, FlipSigns = false;
8443 switch (SetCCOpcode) {
8445 case ISD::SETNE: Invert = true;
8446 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8447 case ISD::SETLT: Swap = true;
8448 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8449 case ISD::SETGE: Swap = true;
8450 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8451 case ISD::SETULT: Swap = true;
8452 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8453 case ISD::SETUGE: Swap = true;
8454 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8457 std::swap(Op0, Op1);
8459 // Check that the operation in question is available (most are plain SSE2,
8460 // but PCMPGTQ and PCMPEQQ have different requirements).
8461 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8463 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8466 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8467 // bits of the inputs before performing those operations.
8469 EVT EltVT = VT.getVectorElementType();
8470 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8472 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8473 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8475 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8476 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8479 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8481 // If the logical-not of the result is required, perform that now.
8483 Result = DAG.getNOT(dl, Result, VT);
8488 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8489 static bool isX86LogicalCmp(SDValue Op) {
8490 unsigned Opc = Op.getNode()->getOpcode();
8491 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8493 if (Op.getResNo() == 1 &&
8494 (Opc == X86ISD::ADD ||
8495 Opc == X86ISD::SUB ||
8496 Opc == X86ISD::ADC ||
8497 Opc == X86ISD::SBB ||
8498 Opc == X86ISD::SMUL ||
8499 Opc == X86ISD::UMUL ||
8500 Opc == X86ISD::INC ||
8501 Opc == X86ISD::DEC ||
8502 Opc == X86ISD::OR ||
8503 Opc == X86ISD::XOR ||
8504 Opc == X86ISD::AND))
8507 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8513 static bool isZero(SDValue V) {
8514 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8515 return C && C->isNullValue();
8518 static bool isAllOnes(SDValue V) {
8519 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8520 return C && C->isAllOnesValue();
8523 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8524 bool addTest = true;
8525 SDValue Cond = Op.getOperand(0);
8526 SDValue Op1 = Op.getOperand(1);
8527 SDValue Op2 = Op.getOperand(2);
8528 DebugLoc DL = Op.getDebugLoc();
8531 if (Cond.getOpcode() == ISD::SETCC) {
8532 SDValue NewCond = LowerSETCC(Cond, DAG);
8533 if (NewCond.getNode())
8537 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8538 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8539 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8540 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8541 if (Cond.getOpcode() == X86ISD::SETCC &&
8542 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8543 isZero(Cond.getOperand(1).getOperand(1))) {
8544 SDValue Cmp = Cond.getOperand(1);
8546 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8548 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8549 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8550 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8552 SDValue CmpOp0 = Cmp.getOperand(0);
8553 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8554 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8556 SDValue Res = // Res = 0 or -1.
8557 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8558 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8560 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8561 Res = DAG.getNOT(DL, Res, Res.getValueType());
8563 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8564 if (N2C == 0 || !N2C->isNullValue())
8565 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8570 // Look past (and (setcc_carry (cmp ...)), 1).
8571 if (Cond.getOpcode() == ISD::AND &&
8572 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8573 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8574 if (C && C->getAPIntValue() == 1)
8575 Cond = Cond.getOperand(0);
8578 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8579 // setting operand in place of the X86ISD::SETCC.
8580 unsigned CondOpcode = Cond.getOpcode();
8581 if (CondOpcode == X86ISD::SETCC ||
8582 CondOpcode == X86ISD::SETCC_CARRY) {
8583 CC = Cond.getOperand(0);
8585 SDValue Cmp = Cond.getOperand(1);
8586 unsigned Opc = Cmp.getOpcode();
8587 EVT VT = Op.getValueType();
8589 bool IllegalFPCMov = false;
8590 if (VT.isFloatingPoint() && !VT.isVector() &&
8591 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8592 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8594 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8595 Opc == X86ISD::BT) { // FIXME
8599 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8600 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8601 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8602 Cond.getOperand(0).getValueType() != MVT::i8)) {
8603 SDValue LHS = Cond.getOperand(0);
8604 SDValue RHS = Cond.getOperand(1);
8608 switch (CondOpcode) {
8609 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8610 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8611 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8612 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8613 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8614 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8615 default: llvm_unreachable("unexpected overflowing operator");
8617 if (CondOpcode == ISD::UMULO)
8618 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8621 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8623 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8625 if (CondOpcode == ISD::UMULO)
8626 Cond = X86Op.getValue(2);
8628 Cond = X86Op.getValue(1);
8630 CC = DAG.getConstant(X86Cond, MVT::i8);
8635 // Look pass the truncate.
8636 if (Cond.getOpcode() == ISD::TRUNCATE)
8637 Cond = Cond.getOperand(0);
8639 // We know the result of AND is compared against zero. Try to match
8641 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8642 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8643 if (NewSetCC.getNode()) {
8644 CC = NewSetCC.getOperand(0);
8645 Cond = NewSetCC.getOperand(1);
8652 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8653 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8656 // a < b ? -1 : 0 -> RES = ~setcc_carry
8657 // a < b ? 0 : -1 -> RES = setcc_carry
8658 // a >= b ? -1 : 0 -> RES = setcc_carry
8659 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8660 if (Cond.getOpcode() == X86ISD::CMP) {
8661 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8663 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8664 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8665 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8666 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8667 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8668 return DAG.getNOT(DL, Res, Res.getValueType());
8673 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8674 // condition is true.
8675 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8676 SDValue Ops[] = { Op2, Op1, CC, Cond };
8677 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8680 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8681 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8682 // from the AND / OR.
8683 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8684 Opc = Op.getOpcode();
8685 if (Opc != ISD::OR && Opc != ISD::AND)
8687 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8688 Op.getOperand(0).hasOneUse() &&
8689 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8690 Op.getOperand(1).hasOneUse());
8693 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8694 // 1 and that the SETCC node has a single use.
8695 static bool isXor1OfSetCC(SDValue Op) {
8696 if (Op.getOpcode() != ISD::XOR)
8698 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8699 if (N1C && N1C->getAPIntValue() == 1) {
8700 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8701 Op.getOperand(0).hasOneUse();
8706 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8707 bool addTest = true;
8708 SDValue Chain = Op.getOperand(0);
8709 SDValue Cond = Op.getOperand(1);
8710 SDValue Dest = Op.getOperand(2);
8711 DebugLoc dl = Op.getDebugLoc();
8713 bool Inverted = false;
8715 if (Cond.getOpcode() == ISD::SETCC) {
8716 // Check for setcc([su]{add,sub,mul}o == 0).
8717 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8718 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8719 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8720 Cond.getOperand(0).getResNo() == 1 &&
8721 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8722 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8723 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8724 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8725 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8726 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8728 Cond = Cond.getOperand(0);
8730 SDValue NewCond = LowerSETCC(Cond, DAG);
8731 if (NewCond.getNode())
8736 // FIXME: LowerXALUO doesn't handle these!!
8737 else if (Cond.getOpcode() == X86ISD::ADD ||
8738 Cond.getOpcode() == X86ISD::SUB ||
8739 Cond.getOpcode() == X86ISD::SMUL ||
8740 Cond.getOpcode() == X86ISD::UMUL)
8741 Cond = LowerXALUO(Cond, DAG);
8744 // Look pass (and (setcc_carry (cmp ...)), 1).
8745 if (Cond.getOpcode() == ISD::AND &&
8746 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8747 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8748 if (C && C->getAPIntValue() == 1)
8749 Cond = Cond.getOperand(0);
8752 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8753 // setting operand in place of the X86ISD::SETCC.
8754 unsigned CondOpcode = Cond.getOpcode();
8755 if (CondOpcode == X86ISD::SETCC ||
8756 CondOpcode == X86ISD::SETCC_CARRY) {
8757 CC = Cond.getOperand(0);
8759 SDValue Cmp = Cond.getOperand(1);
8760 unsigned Opc = Cmp.getOpcode();
8761 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8762 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8766 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8770 // These can only come from an arithmetic instruction with overflow,
8771 // e.g. SADDO, UADDO.
8772 Cond = Cond.getNode()->getOperand(1);
8778 CondOpcode = Cond.getOpcode();
8779 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8780 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8781 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8782 Cond.getOperand(0).getValueType() != MVT::i8)) {
8783 SDValue LHS = Cond.getOperand(0);
8784 SDValue RHS = Cond.getOperand(1);
8788 switch (CondOpcode) {
8789 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8790 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8791 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8792 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8793 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8794 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8795 default: llvm_unreachable("unexpected overflowing operator");
8798 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8799 if (CondOpcode == ISD::UMULO)
8800 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8803 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8805 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8807 if (CondOpcode == ISD::UMULO)
8808 Cond = X86Op.getValue(2);
8810 Cond = X86Op.getValue(1);
8812 CC = DAG.getConstant(X86Cond, MVT::i8);
8816 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8817 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8818 if (CondOpc == ISD::OR) {
8819 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8820 // two branches instead of an explicit OR instruction with a
8822 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8823 isX86LogicalCmp(Cmp)) {
8824 CC = Cond.getOperand(0).getOperand(0);
8825 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8826 Chain, Dest, CC, Cmp);
8827 CC = Cond.getOperand(1).getOperand(0);
8831 } else { // ISD::AND
8832 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8833 // two branches instead of an explicit AND instruction with a
8834 // separate test. However, we only do this if this block doesn't
8835 // have a fall-through edge, because this requires an explicit
8836 // jmp when the condition is false.
8837 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8838 isX86LogicalCmp(Cmp) &&
8839 Op.getNode()->hasOneUse()) {
8840 X86::CondCode CCode =
8841 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8842 CCode = X86::GetOppositeBranchCondition(CCode);
8843 CC = DAG.getConstant(CCode, MVT::i8);
8844 SDNode *User = *Op.getNode()->use_begin();
8845 // Look for an unconditional branch following this conditional branch.
8846 // We need this because we need to reverse the successors in order
8847 // to implement FCMP_OEQ.
8848 if (User->getOpcode() == ISD::BR) {
8849 SDValue FalseBB = User->getOperand(1);
8851 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8852 assert(NewBR == User);
8856 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8857 Chain, Dest, CC, Cmp);
8858 X86::CondCode CCode =
8859 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8860 CCode = X86::GetOppositeBranchCondition(CCode);
8861 CC = DAG.getConstant(CCode, MVT::i8);
8867 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8868 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8869 // It should be transformed during dag combiner except when the condition
8870 // is set by a arithmetics with overflow node.
8871 X86::CondCode CCode =
8872 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8873 CCode = X86::GetOppositeBranchCondition(CCode);
8874 CC = DAG.getConstant(CCode, MVT::i8);
8875 Cond = Cond.getOperand(0).getOperand(1);
8877 } else if (Cond.getOpcode() == ISD::SETCC &&
8878 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8879 // For FCMP_OEQ, we can emit
8880 // two branches instead of an explicit AND instruction with a
8881 // separate test. However, we only do this if this block doesn't
8882 // have a fall-through edge, because this requires an explicit
8883 // jmp when the condition is false.
8884 if (Op.getNode()->hasOneUse()) {
8885 SDNode *User = *Op.getNode()->use_begin();
8886 // Look for an unconditional branch following this conditional branch.
8887 // We need this because we need to reverse the successors in order
8888 // to implement FCMP_OEQ.
8889 if (User->getOpcode() == ISD::BR) {
8890 SDValue FalseBB = User->getOperand(1);
8892 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8893 assert(NewBR == User);
8897 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8898 Cond.getOperand(0), Cond.getOperand(1));
8899 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8900 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8901 Chain, Dest, CC, Cmp);
8902 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8907 } else if (Cond.getOpcode() == ISD::SETCC &&
8908 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8909 // For FCMP_UNE, we can emit
8910 // two branches instead of an explicit AND instruction with a
8911 // separate test. However, we only do this if this block doesn't
8912 // have a fall-through edge, because this requires an explicit
8913 // jmp when the condition is false.
8914 if (Op.getNode()->hasOneUse()) {
8915 SDNode *User = *Op.getNode()->use_begin();
8916 // Look for an unconditional branch following this conditional branch.
8917 // We need this because we need to reverse the successors in order
8918 // to implement FCMP_UNE.
8919 if (User->getOpcode() == ISD::BR) {
8920 SDValue FalseBB = User->getOperand(1);
8922 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8923 assert(NewBR == User);
8926 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8927 Cond.getOperand(0), Cond.getOperand(1));
8928 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8929 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8930 Chain, Dest, CC, Cmp);
8931 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8941 // Look pass the truncate.
8942 if (Cond.getOpcode() == ISD::TRUNCATE)
8943 Cond = Cond.getOperand(0);
8945 // We know the result of AND is compared against zero. Try to match
8947 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8948 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8949 if (NewSetCC.getNode()) {
8950 CC = NewSetCC.getOperand(0);
8951 Cond = NewSetCC.getOperand(1);
8958 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8959 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8961 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8962 Chain, Dest, CC, Cond);
8966 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8967 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8968 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8969 // that the guard pages used by the OS virtual memory manager are allocated in
8970 // correct sequence.
8972 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8973 SelectionDAG &DAG) const {
8974 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8975 getTargetMachine().Options.EnableSegmentedStacks) &&
8976 "This should be used only on Windows targets or when segmented stacks "
8978 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8979 DebugLoc dl = Op.getDebugLoc();
8982 SDValue Chain = Op.getOperand(0);
8983 SDValue Size = Op.getOperand(1);
8984 // FIXME: Ensure alignment here
8986 bool Is64Bit = Subtarget->is64Bit();
8987 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8989 if (getTargetMachine().Options.EnableSegmentedStacks) {
8990 MachineFunction &MF = DAG.getMachineFunction();
8991 MachineRegisterInfo &MRI = MF.getRegInfo();
8994 // The 64 bit implementation of segmented stacks needs to clobber both r10
8995 // r11. This makes it impossible to use it along with nested parameters.
8996 const Function *F = MF.getFunction();
8998 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9000 if (I->hasNestAttr())
9001 report_fatal_error("Cannot use segmented stacks with functions that "
9002 "have nested arguments.");
9005 const TargetRegisterClass *AddrRegClass =
9006 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9007 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9008 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9009 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9010 DAG.getRegister(Vreg, SPTy));
9011 SDValue Ops1[2] = { Value, Chain };
9012 return DAG.getMergeValues(Ops1, 2, dl);
9015 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9017 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9018 Flag = Chain.getValue(1);
9019 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9021 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9022 Flag = Chain.getValue(1);
9024 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9026 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9027 return DAG.getMergeValues(Ops1, 2, dl);
9031 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9032 MachineFunction &MF = DAG.getMachineFunction();
9033 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9035 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9036 DebugLoc DL = Op.getDebugLoc();
9038 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9039 // vastart just stores the address of the VarArgsFrameIndex slot into the
9040 // memory location argument.
9041 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9043 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9044 MachinePointerInfo(SV), false, false, 0);
9048 // gp_offset (0 - 6 * 8)
9049 // fp_offset (48 - 48 + 8 * 16)
9050 // overflow_arg_area (point to parameters coming in memory).
9052 SmallVector<SDValue, 8> MemOps;
9053 SDValue FIN = Op.getOperand(1);
9055 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9056 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9058 FIN, MachinePointerInfo(SV), false, false, 0);
9059 MemOps.push_back(Store);
9062 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9063 FIN, DAG.getIntPtrConstant(4));
9064 Store = DAG.getStore(Op.getOperand(0), DL,
9065 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9067 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9068 MemOps.push_back(Store);
9070 // Store ptr to overflow_arg_area
9071 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9072 FIN, DAG.getIntPtrConstant(4));
9073 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9075 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9076 MachinePointerInfo(SV, 8),
9078 MemOps.push_back(Store);
9080 // Store ptr to reg_save_area.
9081 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9082 FIN, DAG.getIntPtrConstant(8));
9083 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9085 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9086 MachinePointerInfo(SV, 16), false, false, 0);
9087 MemOps.push_back(Store);
9088 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9089 &MemOps[0], MemOps.size());
9092 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9093 assert(Subtarget->is64Bit() &&
9094 "LowerVAARG only handles 64-bit va_arg!");
9095 assert((Subtarget->isTargetLinux() ||
9096 Subtarget->isTargetDarwin()) &&
9097 "Unhandled target in LowerVAARG");
9098 assert(Op.getNode()->getNumOperands() == 4);
9099 SDValue Chain = Op.getOperand(0);
9100 SDValue SrcPtr = Op.getOperand(1);
9101 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9102 unsigned Align = Op.getConstantOperandVal(3);
9103 DebugLoc dl = Op.getDebugLoc();
9105 EVT ArgVT = Op.getNode()->getValueType(0);
9106 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9107 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9110 // Decide which area this value should be read from.
9111 // TODO: Implement the AMD64 ABI in its entirety. This simple
9112 // selection mechanism works only for the basic types.
9113 if (ArgVT == MVT::f80) {
9114 llvm_unreachable("va_arg for f80 not yet implemented");
9115 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9116 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9117 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9118 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9120 llvm_unreachable("Unhandled argument type in LowerVAARG");
9124 // Sanity Check: Make sure using fp_offset makes sense.
9125 assert(!getTargetMachine().Options.UseSoftFloat &&
9126 !(DAG.getMachineFunction()
9127 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9128 Subtarget->hasSSE1());
9131 // Insert VAARG_64 node into the DAG
9132 // VAARG_64 returns two values: Variable Argument Address, Chain
9133 SmallVector<SDValue, 11> InstOps;
9134 InstOps.push_back(Chain);
9135 InstOps.push_back(SrcPtr);
9136 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9137 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9138 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9139 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9140 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9141 VTs, &InstOps[0], InstOps.size(),
9143 MachinePointerInfo(SV),
9148 Chain = VAARG.getValue(1);
9150 // Load the next argument and return it
9151 return DAG.getLoad(ArgVT, dl,
9154 MachinePointerInfo(),
9155 false, false, false, 0);
9158 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9159 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9160 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9161 SDValue Chain = Op.getOperand(0);
9162 SDValue DstPtr = Op.getOperand(1);
9163 SDValue SrcPtr = Op.getOperand(2);
9164 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9165 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9166 DebugLoc DL = Op.getDebugLoc();
9168 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9169 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9171 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9174 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9175 // may or may not be a constant. Takes immediate version of shift as input.
9176 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9177 SDValue SrcOp, SDValue ShAmt,
9178 SelectionDAG &DAG) {
9179 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9181 if (isa<ConstantSDNode>(ShAmt)) {
9183 default: llvm_unreachable("Unknown target vector shift node");
9187 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9191 // Change opcode to non-immediate version
9193 default: llvm_unreachable("Unknown target vector shift node");
9194 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9195 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9196 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9199 // Need to build a vector containing shift amount
9200 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9203 ShOps[1] = DAG.getConstant(0, MVT::i32);
9204 ShOps[2] = DAG.getUNDEF(MVT::i32);
9205 ShOps[3] = DAG.getUNDEF(MVT::i32);
9206 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9207 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9208 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9212 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9213 DebugLoc dl = Op.getDebugLoc();
9214 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9216 default: return SDValue(); // Don't custom lower most intrinsics.
9217 // Comparison intrinsics.
9218 case Intrinsic::x86_sse_comieq_ss:
9219 case Intrinsic::x86_sse_comilt_ss:
9220 case Intrinsic::x86_sse_comile_ss:
9221 case Intrinsic::x86_sse_comigt_ss:
9222 case Intrinsic::x86_sse_comige_ss:
9223 case Intrinsic::x86_sse_comineq_ss:
9224 case Intrinsic::x86_sse_ucomieq_ss:
9225 case Intrinsic::x86_sse_ucomilt_ss:
9226 case Intrinsic::x86_sse_ucomile_ss:
9227 case Intrinsic::x86_sse_ucomigt_ss:
9228 case Intrinsic::x86_sse_ucomige_ss:
9229 case Intrinsic::x86_sse_ucomineq_ss:
9230 case Intrinsic::x86_sse2_comieq_sd:
9231 case Intrinsic::x86_sse2_comilt_sd:
9232 case Intrinsic::x86_sse2_comile_sd:
9233 case Intrinsic::x86_sse2_comigt_sd:
9234 case Intrinsic::x86_sse2_comige_sd:
9235 case Intrinsic::x86_sse2_comineq_sd:
9236 case Intrinsic::x86_sse2_ucomieq_sd:
9237 case Intrinsic::x86_sse2_ucomilt_sd:
9238 case Intrinsic::x86_sse2_ucomile_sd:
9239 case Intrinsic::x86_sse2_ucomigt_sd:
9240 case Intrinsic::x86_sse2_ucomige_sd:
9241 case Intrinsic::x86_sse2_ucomineq_sd: {
9243 ISD::CondCode CC = ISD::SETCC_INVALID;
9245 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9246 case Intrinsic::x86_sse_comieq_ss:
9247 case Intrinsic::x86_sse2_comieq_sd:
9251 case Intrinsic::x86_sse_comilt_ss:
9252 case Intrinsic::x86_sse2_comilt_sd:
9256 case Intrinsic::x86_sse_comile_ss:
9257 case Intrinsic::x86_sse2_comile_sd:
9261 case Intrinsic::x86_sse_comigt_ss:
9262 case Intrinsic::x86_sse2_comigt_sd:
9266 case Intrinsic::x86_sse_comige_ss:
9267 case Intrinsic::x86_sse2_comige_sd:
9271 case Intrinsic::x86_sse_comineq_ss:
9272 case Intrinsic::x86_sse2_comineq_sd:
9276 case Intrinsic::x86_sse_ucomieq_ss:
9277 case Intrinsic::x86_sse2_ucomieq_sd:
9278 Opc = X86ISD::UCOMI;
9281 case Intrinsic::x86_sse_ucomilt_ss:
9282 case Intrinsic::x86_sse2_ucomilt_sd:
9283 Opc = X86ISD::UCOMI;
9286 case Intrinsic::x86_sse_ucomile_ss:
9287 case Intrinsic::x86_sse2_ucomile_sd:
9288 Opc = X86ISD::UCOMI;
9291 case Intrinsic::x86_sse_ucomigt_ss:
9292 case Intrinsic::x86_sse2_ucomigt_sd:
9293 Opc = X86ISD::UCOMI;
9296 case Intrinsic::x86_sse_ucomige_ss:
9297 case Intrinsic::x86_sse2_ucomige_sd:
9298 Opc = X86ISD::UCOMI;
9301 case Intrinsic::x86_sse_ucomineq_ss:
9302 case Intrinsic::x86_sse2_ucomineq_sd:
9303 Opc = X86ISD::UCOMI;
9308 SDValue LHS = Op.getOperand(1);
9309 SDValue RHS = Op.getOperand(2);
9310 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9311 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9312 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9313 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9314 DAG.getConstant(X86CC, MVT::i8), Cond);
9315 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9317 // XOP comparison intrinsics
9318 case Intrinsic::x86_xop_vpcomltb:
9319 case Intrinsic::x86_xop_vpcomltw:
9320 case Intrinsic::x86_xop_vpcomltd:
9321 case Intrinsic::x86_xop_vpcomltq:
9322 case Intrinsic::x86_xop_vpcomltub:
9323 case Intrinsic::x86_xop_vpcomltuw:
9324 case Intrinsic::x86_xop_vpcomltud:
9325 case Intrinsic::x86_xop_vpcomltuq:
9326 case Intrinsic::x86_xop_vpcomleb:
9327 case Intrinsic::x86_xop_vpcomlew:
9328 case Intrinsic::x86_xop_vpcomled:
9329 case Intrinsic::x86_xop_vpcomleq:
9330 case Intrinsic::x86_xop_vpcomleub:
9331 case Intrinsic::x86_xop_vpcomleuw:
9332 case Intrinsic::x86_xop_vpcomleud:
9333 case Intrinsic::x86_xop_vpcomleuq:
9334 case Intrinsic::x86_xop_vpcomgtb:
9335 case Intrinsic::x86_xop_vpcomgtw:
9336 case Intrinsic::x86_xop_vpcomgtd:
9337 case Intrinsic::x86_xop_vpcomgtq:
9338 case Intrinsic::x86_xop_vpcomgtub:
9339 case Intrinsic::x86_xop_vpcomgtuw:
9340 case Intrinsic::x86_xop_vpcomgtud:
9341 case Intrinsic::x86_xop_vpcomgtuq:
9342 case Intrinsic::x86_xop_vpcomgeb:
9343 case Intrinsic::x86_xop_vpcomgew:
9344 case Intrinsic::x86_xop_vpcomged:
9345 case Intrinsic::x86_xop_vpcomgeq:
9346 case Intrinsic::x86_xop_vpcomgeub:
9347 case Intrinsic::x86_xop_vpcomgeuw:
9348 case Intrinsic::x86_xop_vpcomgeud:
9349 case Intrinsic::x86_xop_vpcomgeuq:
9350 case Intrinsic::x86_xop_vpcomeqb:
9351 case Intrinsic::x86_xop_vpcomeqw:
9352 case Intrinsic::x86_xop_vpcomeqd:
9353 case Intrinsic::x86_xop_vpcomeqq:
9354 case Intrinsic::x86_xop_vpcomequb:
9355 case Intrinsic::x86_xop_vpcomequw:
9356 case Intrinsic::x86_xop_vpcomequd:
9357 case Intrinsic::x86_xop_vpcomequq:
9358 case Intrinsic::x86_xop_vpcomneb:
9359 case Intrinsic::x86_xop_vpcomnew:
9360 case Intrinsic::x86_xop_vpcomned:
9361 case Intrinsic::x86_xop_vpcomneq:
9362 case Intrinsic::x86_xop_vpcomneub:
9363 case Intrinsic::x86_xop_vpcomneuw:
9364 case Intrinsic::x86_xop_vpcomneud:
9365 case Intrinsic::x86_xop_vpcomneuq:
9366 case Intrinsic::x86_xop_vpcomfalseb:
9367 case Intrinsic::x86_xop_vpcomfalsew:
9368 case Intrinsic::x86_xop_vpcomfalsed:
9369 case Intrinsic::x86_xop_vpcomfalseq:
9370 case Intrinsic::x86_xop_vpcomfalseub:
9371 case Intrinsic::x86_xop_vpcomfalseuw:
9372 case Intrinsic::x86_xop_vpcomfalseud:
9373 case Intrinsic::x86_xop_vpcomfalseuq:
9374 case Intrinsic::x86_xop_vpcomtrueb:
9375 case Intrinsic::x86_xop_vpcomtruew:
9376 case Intrinsic::x86_xop_vpcomtrued:
9377 case Intrinsic::x86_xop_vpcomtrueq:
9378 case Intrinsic::x86_xop_vpcomtrueub:
9379 case Intrinsic::x86_xop_vpcomtrueuw:
9380 case Intrinsic::x86_xop_vpcomtrueud:
9381 case Intrinsic::x86_xop_vpcomtrueuq: {
9386 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9387 case Intrinsic::x86_xop_vpcomltb:
9388 case Intrinsic::x86_xop_vpcomltw:
9389 case Intrinsic::x86_xop_vpcomltd:
9390 case Intrinsic::x86_xop_vpcomltq:
9392 Opc = X86ISD::VPCOM;
9394 case Intrinsic::x86_xop_vpcomltub:
9395 case Intrinsic::x86_xop_vpcomltuw:
9396 case Intrinsic::x86_xop_vpcomltud:
9397 case Intrinsic::x86_xop_vpcomltuq:
9399 Opc = X86ISD::VPCOMU;
9401 case Intrinsic::x86_xop_vpcomleb:
9402 case Intrinsic::x86_xop_vpcomlew:
9403 case Intrinsic::x86_xop_vpcomled:
9404 case Intrinsic::x86_xop_vpcomleq:
9406 Opc = X86ISD::VPCOM;
9408 case Intrinsic::x86_xop_vpcomleub:
9409 case Intrinsic::x86_xop_vpcomleuw:
9410 case Intrinsic::x86_xop_vpcomleud:
9411 case Intrinsic::x86_xop_vpcomleuq:
9413 Opc = X86ISD::VPCOMU;
9415 case Intrinsic::x86_xop_vpcomgtb:
9416 case Intrinsic::x86_xop_vpcomgtw:
9417 case Intrinsic::x86_xop_vpcomgtd:
9418 case Intrinsic::x86_xop_vpcomgtq:
9420 Opc = X86ISD::VPCOM;
9422 case Intrinsic::x86_xop_vpcomgtub:
9423 case Intrinsic::x86_xop_vpcomgtuw:
9424 case Intrinsic::x86_xop_vpcomgtud:
9425 case Intrinsic::x86_xop_vpcomgtuq:
9427 Opc = X86ISD::VPCOMU;
9429 case Intrinsic::x86_xop_vpcomgeb:
9430 case Intrinsic::x86_xop_vpcomgew:
9431 case Intrinsic::x86_xop_vpcomged:
9432 case Intrinsic::x86_xop_vpcomgeq:
9434 Opc = X86ISD::VPCOM;
9436 case Intrinsic::x86_xop_vpcomgeub:
9437 case Intrinsic::x86_xop_vpcomgeuw:
9438 case Intrinsic::x86_xop_vpcomgeud:
9439 case Intrinsic::x86_xop_vpcomgeuq:
9441 Opc = X86ISD::VPCOMU;
9443 case Intrinsic::x86_xop_vpcomeqb:
9444 case Intrinsic::x86_xop_vpcomeqw:
9445 case Intrinsic::x86_xop_vpcomeqd:
9446 case Intrinsic::x86_xop_vpcomeqq:
9448 Opc = X86ISD::VPCOM;
9450 case Intrinsic::x86_xop_vpcomequb:
9451 case Intrinsic::x86_xop_vpcomequw:
9452 case Intrinsic::x86_xop_vpcomequd:
9453 case Intrinsic::x86_xop_vpcomequq:
9455 Opc = X86ISD::VPCOMU;
9457 case Intrinsic::x86_xop_vpcomneb:
9458 case Intrinsic::x86_xop_vpcomnew:
9459 case Intrinsic::x86_xop_vpcomned:
9460 case Intrinsic::x86_xop_vpcomneq:
9462 Opc = X86ISD::VPCOM;
9464 case Intrinsic::x86_xop_vpcomneub:
9465 case Intrinsic::x86_xop_vpcomneuw:
9466 case Intrinsic::x86_xop_vpcomneud:
9467 case Intrinsic::x86_xop_vpcomneuq:
9469 Opc = X86ISD::VPCOMU;
9471 case Intrinsic::x86_xop_vpcomfalseb:
9472 case Intrinsic::x86_xop_vpcomfalsew:
9473 case Intrinsic::x86_xop_vpcomfalsed:
9474 case Intrinsic::x86_xop_vpcomfalseq:
9476 Opc = X86ISD::VPCOM;
9478 case Intrinsic::x86_xop_vpcomfalseub:
9479 case Intrinsic::x86_xop_vpcomfalseuw:
9480 case Intrinsic::x86_xop_vpcomfalseud:
9481 case Intrinsic::x86_xop_vpcomfalseuq:
9483 Opc = X86ISD::VPCOMU;
9485 case Intrinsic::x86_xop_vpcomtrueb:
9486 case Intrinsic::x86_xop_vpcomtruew:
9487 case Intrinsic::x86_xop_vpcomtrued:
9488 case Intrinsic::x86_xop_vpcomtrueq:
9490 Opc = X86ISD::VPCOM;
9492 case Intrinsic::x86_xop_vpcomtrueub:
9493 case Intrinsic::x86_xop_vpcomtrueuw:
9494 case Intrinsic::x86_xop_vpcomtrueud:
9495 case Intrinsic::x86_xop_vpcomtrueuq:
9497 Opc = X86ISD::VPCOMU;
9501 SDValue LHS = Op.getOperand(1);
9502 SDValue RHS = Op.getOperand(2);
9503 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9504 DAG.getConstant(CC, MVT::i8));
9507 // Arithmetic intrinsics.
9508 case Intrinsic::x86_sse2_pmulu_dq:
9509 case Intrinsic::x86_avx2_pmulu_dq:
9510 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9511 Op.getOperand(1), Op.getOperand(2));
9512 case Intrinsic::x86_sse3_hadd_ps:
9513 case Intrinsic::x86_sse3_hadd_pd:
9514 case Intrinsic::x86_avx_hadd_ps_256:
9515 case Intrinsic::x86_avx_hadd_pd_256:
9516 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9517 Op.getOperand(1), Op.getOperand(2));
9518 case Intrinsic::x86_sse3_hsub_ps:
9519 case Intrinsic::x86_sse3_hsub_pd:
9520 case Intrinsic::x86_avx_hsub_ps_256:
9521 case Intrinsic::x86_avx_hsub_pd_256:
9522 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9523 Op.getOperand(1), Op.getOperand(2));
9524 case Intrinsic::x86_ssse3_phadd_w_128:
9525 case Intrinsic::x86_ssse3_phadd_d_128:
9526 case Intrinsic::x86_avx2_phadd_w:
9527 case Intrinsic::x86_avx2_phadd_d:
9528 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9529 Op.getOperand(1), Op.getOperand(2));
9530 case Intrinsic::x86_ssse3_phsub_w_128:
9531 case Intrinsic::x86_ssse3_phsub_d_128:
9532 case Intrinsic::x86_avx2_phsub_w:
9533 case Intrinsic::x86_avx2_phsub_d:
9534 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9535 Op.getOperand(1), Op.getOperand(2));
9536 case Intrinsic::x86_avx2_psllv_d:
9537 case Intrinsic::x86_avx2_psllv_q:
9538 case Intrinsic::x86_avx2_psllv_d_256:
9539 case Intrinsic::x86_avx2_psllv_q_256:
9540 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9541 Op.getOperand(1), Op.getOperand(2));
9542 case Intrinsic::x86_avx2_psrlv_d:
9543 case Intrinsic::x86_avx2_psrlv_q:
9544 case Intrinsic::x86_avx2_psrlv_d_256:
9545 case Intrinsic::x86_avx2_psrlv_q_256:
9546 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9547 Op.getOperand(1), Op.getOperand(2));
9548 case Intrinsic::x86_avx2_psrav_d:
9549 case Intrinsic::x86_avx2_psrav_d_256:
9550 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9551 Op.getOperand(1), Op.getOperand(2));
9552 case Intrinsic::x86_ssse3_pshuf_b_128:
9553 case Intrinsic::x86_avx2_pshuf_b:
9554 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9555 Op.getOperand(1), Op.getOperand(2));
9556 case Intrinsic::x86_ssse3_psign_b_128:
9557 case Intrinsic::x86_ssse3_psign_w_128:
9558 case Intrinsic::x86_ssse3_psign_d_128:
9559 case Intrinsic::x86_avx2_psign_b:
9560 case Intrinsic::x86_avx2_psign_w:
9561 case Intrinsic::x86_avx2_psign_d:
9562 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9563 Op.getOperand(1), Op.getOperand(2));
9564 case Intrinsic::x86_sse41_insertps:
9565 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9566 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9567 case Intrinsic::x86_avx_vperm2f128_ps_256:
9568 case Intrinsic::x86_avx_vperm2f128_pd_256:
9569 case Intrinsic::x86_avx_vperm2f128_si_256:
9570 case Intrinsic::x86_avx2_vperm2i128:
9571 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9572 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9573 case Intrinsic::x86_avx2_permd:
9574 case Intrinsic::x86_avx2_permps:
9575 // Operands intentionally swapped. Mask is last operand to intrinsic,
9576 // but second operand for node/intruction.
9577 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9578 Op.getOperand(2), Op.getOperand(1));
9580 // ptest and testp intrinsics. The intrinsic these come from are designed to
9581 // return an integer value, not just an instruction so lower it to the ptest
9582 // or testp pattern and a setcc for the result.
9583 case Intrinsic::x86_sse41_ptestz:
9584 case Intrinsic::x86_sse41_ptestc:
9585 case Intrinsic::x86_sse41_ptestnzc:
9586 case Intrinsic::x86_avx_ptestz_256:
9587 case Intrinsic::x86_avx_ptestc_256:
9588 case Intrinsic::x86_avx_ptestnzc_256:
9589 case Intrinsic::x86_avx_vtestz_ps:
9590 case Intrinsic::x86_avx_vtestc_ps:
9591 case Intrinsic::x86_avx_vtestnzc_ps:
9592 case Intrinsic::x86_avx_vtestz_pd:
9593 case Intrinsic::x86_avx_vtestc_pd:
9594 case Intrinsic::x86_avx_vtestnzc_pd:
9595 case Intrinsic::x86_avx_vtestz_ps_256:
9596 case Intrinsic::x86_avx_vtestc_ps_256:
9597 case Intrinsic::x86_avx_vtestnzc_ps_256:
9598 case Intrinsic::x86_avx_vtestz_pd_256:
9599 case Intrinsic::x86_avx_vtestc_pd_256:
9600 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9601 bool IsTestPacked = false;
9604 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9605 case Intrinsic::x86_avx_vtestz_ps:
9606 case Intrinsic::x86_avx_vtestz_pd:
9607 case Intrinsic::x86_avx_vtestz_ps_256:
9608 case Intrinsic::x86_avx_vtestz_pd_256:
9609 IsTestPacked = true; // Fallthrough
9610 case Intrinsic::x86_sse41_ptestz:
9611 case Intrinsic::x86_avx_ptestz_256:
9613 X86CC = X86::COND_E;
9615 case Intrinsic::x86_avx_vtestc_ps:
9616 case Intrinsic::x86_avx_vtestc_pd:
9617 case Intrinsic::x86_avx_vtestc_ps_256:
9618 case Intrinsic::x86_avx_vtestc_pd_256:
9619 IsTestPacked = true; // Fallthrough
9620 case Intrinsic::x86_sse41_ptestc:
9621 case Intrinsic::x86_avx_ptestc_256:
9623 X86CC = X86::COND_B;
9625 case Intrinsic::x86_avx_vtestnzc_ps:
9626 case Intrinsic::x86_avx_vtestnzc_pd:
9627 case Intrinsic::x86_avx_vtestnzc_ps_256:
9628 case Intrinsic::x86_avx_vtestnzc_pd_256:
9629 IsTestPacked = true; // Fallthrough
9630 case Intrinsic::x86_sse41_ptestnzc:
9631 case Intrinsic::x86_avx_ptestnzc_256:
9633 X86CC = X86::COND_A;
9637 SDValue LHS = Op.getOperand(1);
9638 SDValue RHS = Op.getOperand(2);
9639 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9640 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9641 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9642 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9643 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9646 // SSE/AVX shift intrinsics
9647 case Intrinsic::x86_sse2_psll_w:
9648 case Intrinsic::x86_sse2_psll_d:
9649 case Intrinsic::x86_sse2_psll_q:
9650 case Intrinsic::x86_avx2_psll_w:
9651 case Intrinsic::x86_avx2_psll_d:
9652 case Intrinsic::x86_avx2_psll_q:
9653 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9654 Op.getOperand(1), Op.getOperand(2));
9655 case Intrinsic::x86_sse2_psrl_w:
9656 case Intrinsic::x86_sse2_psrl_d:
9657 case Intrinsic::x86_sse2_psrl_q:
9658 case Intrinsic::x86_avx2_psrl_w:
9659 case Intrinsic::x86_avx2_psrl_d:
9660 case Intrinsic::x86_avx2_psrl_q:
9661 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9662 Op.getOperand(1), Op.getOperand(2));
9663 case Intrinsic::x86_sse2_psra_w:
9664 case Intrinsic::x86_sse2_psra_d:
9665 case Intrinsic::x86_avx2_psra_w:
9666 case Intrinsic::x86_avx2_psra_d:
9667 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9668 Op.getOperand(1), Op.getOperand(2));
9669 case Intrinsic::x86_sse2_pslli_w:
9670 case Intrinsic::x86_sse2_pslli_d:
9671 case Intrinsic::x86_sse2_pslli_q:
9672 case Intrinsic::x86_avx2_pslli_w:
9673 case Intrinsic::x86_avx2_pslli_d:
9674 case Intrinsic::x86_avx2_pslli_q:
9675 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9676 Op.getOperand(1), Op.getOperand(2), DAG);
9677 case Intrinsic::x86_sse2_psrli_w:
9678 case Intrinsic::x86_sse2_psrli_d:
9679 case Intrinsic::x86_sse2_psrli_q:
9680 case Intrinsic::x86_avx2_psrli_w:
9681 case Intrinsic::x86_avx2_psrli_d:
9682 case Intrinsic::x86_avx2_psrli_q:
9683 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9684 Op.getOperand(1), Op.getOperand(2), DAG);
9685 case Intrinsic::x86_sse2_psrai_w:
9686 case Intrinsic::x86_sse2_psrai_d:
9687 case Intrinsic::x86_avx2_psrai_w:
9688 case Intrinsic::x86_avx2_psrai_d:
9689 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9690 Op.getOperand(1), Op.getOperand(2), DAG);
9691 // Fix vector shift instructions where the last operand is a non-immediate
9693 case Intrinsic::x86_mmx_pslli_w:
9694 case Intrinsic::x86_mmx_pslli_d:
9695 case Intrinsic::x86_mmx_pslli_q:
9696 case Intrinsic::x86_mmx_psrli_w:
9697 case Intrinsic::x86_mmx_psrli_d:
9698 case Intrinsic::x86_mmx_psrli_q:
9699 case Intrinsic::x86_mmx_psrai_w:
9700 case Intrinsic::x86_mmx_psrai_d: {
9701 SDValue ShAmt = Op.getOperand(2);
9702 if (isa<ConstantSDNode>(ShAmt))
9705 unsigned NewIntNo = 0;
9707 case Intrinsic::x86_mmx_pslli_w:
9708 NewIntNo = Intrinsic::x86_mmx_psll_w;
9710 case Intrinsic::x86_mmx_pslli_d:
9711 NewIntNo = Intrinsic::x86_mmx_psll_d;
9713 case Intrinsic::x86_mmx_pslli_q:
9714 NewIntNo = Intrinsic::x86_mmx_psll_q;
9716 case Intrinsic::x86_mmx_psrli_w:
9717 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9719 case Intrinsic::x86_mmx_psrli_d:
9720 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9722 case Intrinsic::x86_mmx_psrli_q:
9723 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9725 case Intrinsic::x86_mmx_psrai_w:
9726 NewIntNo = Intrinsic::x86_mmx_psra_w;
9728 case Intrinsic::x86_mmx_psrai_d:
9729 NewIntNo = Intrinsic::x86_mmx_psra_d;
9731 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9734 // The vector shift intrinsics with scalars uses 32b shift amounts but
9735 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9737 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9738 DAG.getConstant(0, MVT::i32));
9739 // FIXME this must be lowered to get rid of the invalid type.
9741 EVT VT = Op.getValueType();
9742 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9743 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9744 DAG.getConstant(NewIntNo, MVT::i32),
9745 Op.getOperand(1), ShAmt);
9750 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9751 SelectionDAG &DAG) const {
9752 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9753 MFI->setReturnAddressIsTaken(true);
9755 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9756 DebugLoc dl = Op.getDebugLoc();
9759 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9761 DAG.getConstant(TD->getPointerSize(),
9762 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9763 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9764 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9766 MachinePointerInfo(), false, false, false, 0);
9769 // Just load the return address.
9770 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9771 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9772 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9775 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9776 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9777 MFI->setFrameAddressIsTaken(true);
9779 EVT VT = Op.getValueType();
9780 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9781 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9782 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9783 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9785 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9786 MachinePointerInfo(),
9787 false, false, false, 0);
9791 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9792 SelectionDAG &DAG) const {
9793 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9796 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9797 MachineFunction &MF = DAG.getMachineFunction();
9798 SDValue Chain = Op.getOperand(0);
9799 SDValue Offset = Op.getOperand(1);
9800 SDValue Handler = Op.getOperand(2);
9801 DebugLoc dl = Op.getDebugLoc();
9803 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9804 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9806 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9808 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9809 DAG.getIntPtrConstant(TD->getPointerSize()));
9810 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9811 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9813 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9814 MF.getRegInfo().addLiveOut(StoreAddrReg);
9816 return DAG.getNode(X86ISD::EH_RETURN, dl,
9818 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9821 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9822 SelectionDAG &DAG) const {
9823 return Op.getOperand(0);
9826 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9827 SelectionDAG &DAG) const {
9828 SDValue Root = Op.getOperand(0);
9829 SDValue Trmp = Op.getOperand(1); // trampoline
9830 SDValue FPtr = Op.getOperand(2); // nested function
9831 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9832 DebugLoc dl = Op.getDebugLoc();
9834 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9836 if (Subtarget->is64Bit()) {
9837 SDValue OutChains[6];
9839 // Large code-model.
9840 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9841 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9843 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9844 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9846 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9848 // Load the pointer to the nested function into R11.
9849 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9850 SDValue Addr = Trmp;
9851 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9852 Addr, MachinePointerInfo(TrmpAddr),
9855 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9856 DAG.getConstant(2, MVT::i64));
9857 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9858 MachinePointerInfo(TrmpAddr, 2),
9861 // Load the 'nest' parameter value into R10.
9862 // R10 is specified in X86CallingConv.td
9863 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9864 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9865 DAG.getConstant(10, MVT::i64));
9866 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9867 Addr, MachinePointerInfo(TrmpAddr, 10),
9870 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9871 DAG.getConstant(12, MVT::i64));
9872 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9873 MachinePointerInfo(TrmpAddr, 12),
9876 // Jump to the nested function.
9877 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9878 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9879 DAG.getConstant(20, MVT::i64));
9880 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9881 Addr, MachinePointerInfo(TrmpAddr, 20),
9884 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9886 DAG.getConstant(22, MVT::i64));
9887 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9888 MachinePointerInfo(TrmpAddr, 22),
9891 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9893 const Function *Func =
9894 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9895 CallingConv::ID CC = Func->getCallingConv();
9900 llvm_unreachable("Unsupported calling convention");
9901 case CallingConv::C:
9902 case CallingConv::X86_StdCall: {
9903 // Pass 'nest' parameter in ECX.
9904 // Must be kept in sync with X86CallingConv.td
9907 // Check that ECX wasn't needed by an 'inreg' parameter.
9908 FunctionType *FTy = Func->getFunctionType();
9909 const AttrListPtr &Attrs = Func->getAttributes();
9911 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9912 unsigned InRegCount = 0;
9915 for (FunctionType::param_iterator I = FTy->param_begin(),
9916 E = FTy->param_end(); I != E; ++I, ++Idx)
9917 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9918 // FIXME: should only count parameters that are lowered to integers.
9919 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9921 if (InRegCount > 2) {
9922 report_fatal_error("Nest register in use - reduce number of inreg"
9928 case CallingConv::X86_FastCall:
9929 case CallingConv::X86_ThisCall:
9930 case CallingConv::Fast:
9931 // Pass 'nest' parameter in EAX.
9932 // Must be kept in sync with X86CallingConv.td
9937 SDValue OutChains[4];
9940 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9941 DAG.getConstant(10, MVT::i32));
9942 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9944 // This is storing the opcode for MOV32ri.
9945 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9946 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9947 OutChains[0] = DAG.getStore(Root, dl,
9948 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9949 Trmp, MachinePointerInfo(TrmpAddr),
9952 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9953 DAG.getConstant(1, MVT::i32));
9954 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9955 MachinePointerInfo(TrmpAddr, 1),
9958 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9959 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9960 DAG.getConstant(5, MVT::i32));
9961 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9962 MachinePointerInfo(TrmpAddr, 5),
9965 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9966 DAG.getConstant(6, MVT::i32));
9967 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9968 MachinePointerInfo(TrmpAddr, 6),
9971 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9975 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9976 SelectionDAG &DAG) const {
9978 The rounding mode is in bits 11:10 of FPSR, and has the following
9985 FLT_ROUNDS, on the other hand, expects the following:
9992 To perform the conversion, we do:
9993 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9996 MachineFunction &MF = DAG.getMachineFunction();
9997 const TargetMachine &TM = MF.getTarget();
9998 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9999 unsigned StackAlignment = TFI.getStackAlignment();
10000 EVT VT = Op.getValueType();
10001 DebugLoc DL = Op.getDebugLoc();
10003 // Save FP Control Word to stack slot
10004 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10005 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10008 MachineMemOperand *MMO =
10009 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10010 MachineMemOperand::MOStore, 2, 2);
10012 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10013 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10014 DAG.getVTList(MVT::Other),
10015 Ops, 2, MVT::i16, MMO);
10017 // Load FP Control Word from stack slot
10018 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10019 MachinePointerInfo(), false, false, false, 0);
10021 // Transform as necessary
10023 DAG.getNode(ISD::SRL, DL, MVT::i16,
10024 DAG.getNode(ISD::AND, DL, MVT::i16,
10025 CWD, DAG.getConstant(0x800, MVT::i16)),
10026 DAG.getConstant(11, MVT::i8));
10028 DAG.getNode(ISD::SRL, DL, MVT::i16,
10029 DAG.getNode(ISD::AND, DL, MVT::i16,
10030 CWD, DAG.getConstant(0x400, MVT::i16)),
10031 DAG.getConstant(9, MVT::i8));
10034 DAG.getNode(ISD::AND, DL, MVT::i16,
10035 DAG.getNode(ISD::ADD, DL, MVT::i16,
10036 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10037 DAG.getConstant(1, MVT::i16)),
10038 DAG.getConstant(3, MVT::i16));
10041 return DAG.getNode((VT.getSizeInBits() < 16 ?
10042 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10045 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10046 EVT VT = Op.getValueType();
10048 unsigned NumBits = VT.getSizeInBits();
10049 DebugLoc dl = Op.getDebugLoc();
10051 Op = Op.getOperand(0);
10052 if (VT == MVT::i8) {
10053 // Zero extend to i32 since there is not an i8 bsr.
10055 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10058 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10059 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10060 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10062 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10065 DAG.getConstant(NumBits+NumBits-1, OpVT),
10066 DAG.getConstant(X86::COND_E, MVT::i8),
10069 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10071 // Finally xor with NumBits-1.
10072 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10075 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10079 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10080 SelectionDAG &DAG) const {
10081 EVT VT = Op.getValueType();
10083 unsigned NumBits = VT.getSizeInBits();
10084 DebugLoc dl = Op.getDebugLoc();
10086 Op = Op.getOperand(0);
10087 if (VT == MVT::i8) {
10088 // Zero extend to i32 since there is not an i8 bsr.
10090 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10093 // Issue a bsr (scan bits in reverse).
10094 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10095 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10097 // And xor with NumBits-1.
10098 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10101 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10105 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10106 EVT VT = Op.getValueType();
10107 unsigned NumBits = VT.getSizeInBits();
10108 DebugLoc dl = Op.getDebugLoc();
10109 Op = Op.getOperand(0);
10111 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10112 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10113 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10115 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10118 DAG.getConstant(NumBits, VT),
10119 DAG.getConstant(X86::COND_E, MVT::i8),
10122 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10125 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10126 // ones, and then concatenate the result back.
10127 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10128 EVT VT = Op.getValueType();
10130 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10131 "Unsupported value type for operation");
10133 int NumElems = VT.getVectorNumElements();
10134 DebugLoc dl = Op.getDebugLoc();
10136 // Extract the LHS vectors
10137 SDValue LHS = Op.getOperand(0);
10138 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10139 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10141 // Extract the RHS vectors
10142 SDValue RHS = Op.getOperand(1);
10143 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10144 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10146 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10147 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10149 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10150 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10151 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10154 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10155 assert(Op.getValueType().getSizeInBits() == 256 &&
10156 Op.getValueType().isInteger() &&
10157 "Only handle AVX 256-bit vector integer operation");
10158 return Lower256IntArith(Op, DAG);
10161 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10162 assert(Op.getValueType().getSizeInBits() == 256 &&
10163 Op.getValueType().isInteger() &&
10164 "Only handle AVX 256-bit vector integer operation");
10165 return Lower256IntArith(Op, DAG);
10168 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10169 EVT VT = Op.getValueType();
10171 // Decompose 256-bit ops into smaller 128-bit ops.
10172 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10173 return Lower256IntArith(Op, DAG);
10175 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10176 "Only know how to lower V2I64/V4I64 multiply");
10178 DebugLoc dl = Op.getDebugLoc();
10180 // Ahi = psrlqi(a, 32);
10181 // Bhi = psrlqi(b, 32);
10183 // AloBlo = pmuludq(a, b);
10184 // AloBhi = pmuludq(a, Bhi);
10185 // AhiBlo = pmuludq(Ahi, b);
10187 // AloBhi = psllqi(AloBhi, 32);
10188 // AhiBlo = psllqi(AhiBlo, 32);
10189 // return AloBlo + AloBhi + AhiBlo;
10191 SDValue A = Op.getOperand(0);
10192 SDValue B = Op.getOperand(1);
10194 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10196 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10197 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10199 // Bit cast to 32-bit vectors for MULUDQ
10200 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10201 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10202 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10203 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10204 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10206 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10207 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10208 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10210 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10211 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10213 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10214 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10217 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10219 EVT VT = Op.getValueType();
10220 DebugLoc dl = Op.getDebugLoc();
10221 SDValue R = Op.getOperand(0);
10222 SDValue Amt = Op.getOperand(1);
10223 LLVMContext *Context = DAG.getContext();
10225 if (!Subtarget->hasSSE2())
10228 // Optimize shl/srl/sra with constant shift amount.
10229 if (isSplatVector(Amt.getNode())) {
10230 SDValue SclrAmt = Amt->getOperand(0);
10231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10232 uint64_t ShiftAmt = C->getZExtValue();
10234 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10235 (Subtarget->hasAVX2() &&
10236 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10237 if (Op.getOpcode() == ISD::SHL)
10238 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10239 DAG.getConstant(ShiftAmt, MVT::i32));
10240 if (Op.getOpcode() == ISD::SRL)
10241 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10242 DAG.getConstant(ShiftAmt, MVT::i32));
10243 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10244 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10245 DAG.getConstant(ShiftAmt, MVT::i32));
10248 if (VT == MVT::v16i8) {
10249 if (Op.getOpcode() == ISD::SHL) {
10250 // Make a large shift.
10251 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10252 DAG.getConstant(ShiftAmt, MVT::i32));
10253 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10254 // Zero out the rightmost bits.
10255 SmallVector<SDValue, 16> V(16,
10256 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10258 return DAG.getNode(ISD::AND, dl, VT, SHL,
10259 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10261 if (Op.getOpcode() == ISD::SRL) {
10262 // Make a large shift.
10263 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10264 DAG.getConstant(ShiftAmt, MVT::i32));
10265 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10266 // Zero out the leftmost bits.
10267 SmallVector<SDValue, 16> V(16,
10268 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10270 return DAG.getNode(ISD::AND, dl, VT, SRL,
10271 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10273 if (Op.getOpcode() == ISD::SRA) {
10274 if (ShiftAmt == 7) {
10275 // R s>> 7 === R s< 0
10276 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10277 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10280 // R s>> a === ((R u>> a) ^ m) - m
10281 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10282 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10284 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10285 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10286 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10289 llvm_unreachable("Unknown shift opcode.");
10292 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10293 if (Op.getOpcode() == ISD::SHL) {
10294 // Make a large shift.
10295 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10296 DAG.getConstant(ShiftAmt, MVT::i32));
10297 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10298 // Zero out the rightmost bits.
10299 SmallVector<SDValue, 32> V(32,
10300 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10302 return DAG.getNode(ISD::AND, dl, VT, SHL,
10303 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10305 if (Op.getOpcode() == ISD::SRL) {
10306 // Make a large shift.
10307 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10308 DAG.getConstant(ShiftAmt, MVT::i32));
10309 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10310 // Zero out the leftmost bits.
10311 SmallVector<SDValue, 32> V(32,
10312 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10314 return DAG.getNode(ISD::AND, dl, VT, SRL,
10315 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10317 if (Op.getOpcode() == ISD::SRA) {
10318 if (ShiftAmt == 7) {
10319 // R s>> 7 === R s< 0
10320 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10321 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10324 // R s>> a === ((R u>> a) ^ m) - m
10325 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10326 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10328 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10329 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10330 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10333 llvm_unreachable("Unknown shift opcode.");
10338 // Lower SHL with variable shift amount.
10339 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10340 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10341 DAG.getConstant(23, MVT::i32));
10343 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10344 Constant *C = ConstantDataVector::get(*Context, CV);
10345 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10346 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10347 MachinePointerInfo::getConstantPool(),
10348 false, false, false, 16);
10350 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10351 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10352 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10353 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10355 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10356 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10359 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10360 DAG.getConstant(5, MVT::i32));
10361 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10363 // Turn 'a' into a mask suitable for VSELECT
10364 SDValue VSelM = DAG.getConstant(0x80, VT);
10365 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10366 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10368 SDValue CM1 = DAG.getConstant(0x0f, VT);
10369 SDValue CM2 = DAG.getConstant(0x3f, VT);
10371 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10372 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10373 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10374 DAG.getConstant(4, MVT::i32), DAG);
10375 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10376 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10379 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10380 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10381 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10383 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10384 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10385 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10386 DAG.getConstant(2, MVT::i32), DAG);
10387 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10388 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10391 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10392 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10393 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10395 // return VSELECT(r, r+r, a);
10396 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10397 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10401 // Decompose 256-bit shifts into smaller 128-bit shifts.
10402 if (VT.getSizeInBits() == 256) {
10403 unsigned NumElems = VT.getVectorNumElements();
10404 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10405 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10407 // Extract the two vectors
10408 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10409 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10411 // Recreate the shift amount vectors
10412 SDValue Amt1, Amt2;
10413 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10414 // Constant shift amount
10415 SmallVector<SDValue, 4> Amt1Csts;
10416 SmallVector<SDValue, 4> Amt2Csts;
10417 for (unsigned i = 0; i != NumElems/2; ++i)
10418 Amt1Csts.push_back(Amt->getOperand(i));
10419 for (unsigned i = NumElems/2; i != NumElems; ++i)
10420 Amt2Csts.push_back(Amt->getOperand(i));
10422 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10423 &Amt1Csts[0], NumElems/2);
10424 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10425 &Amt2Csts[0], NumElems/2);
10427 // Variable shift amount
10428 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10429 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10432 // Issue new vector shifts for the smaller types
10433 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10434 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10436 // Concatenate the result back
10437 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10443 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10444 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10445 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10446 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10447 // has only one use.
10448 SDNode *N = Op.getNode();
10449 SDValue LHS = N->getOperand(0);
10450 SDValue RHS = N->getOperand(1);
10451 unsigned BaseOp = 0;
10453 DebugLoc DL = Op.getDebugLoc();
10454 switch (Op.getOpcode()) {
10455 default: llvm_unreachable("Unknown ovf instruction!");
10457 // A subtract of one will be selected as a INC. Note that INC doesn't
10458 // set CF, so we can't do this for UADDO.
10459 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10461 BaseOp = X86ISD::INC;
10462 Cond = X86::COND_O;
10465 BaseOp = X86ISD::ADD;
10466 Cond = X86::COND_O;
10469 BaseOp = X86ISD::ADD;
10470 Cond = X86::COND_B;
10473 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10474 // set CF, so we can't do this for USUBO.
10475 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10477 BaseOp = X86ISD::DEC;
10478 Cond = X86::COND_O;
10481 BaseOp = X86ISD::SUB;
10482 Cond = X86::COND_O;
10485 BaseOp = X86ISD::SUB;
10486 Cond = X86::COND_B;
10489 BaseOp = X86ISD::SMUL;
10490 Cond = X86::COND_O;
10492 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10493 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10495 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10498 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10499 DAG.getConstant(X86::COND_O, MVT::i32),
10500 SDValue(Sum.getNode(), 2));
10502 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10506 // Also sets EFLAGS.
10507 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10508 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10511 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10512 DAG.getConstant(Cond, MVT::i32),
10513 SDValue(Sum.getNode(), 1));
10515 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10518 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10519 SelectionDAG &DAG) const {
10520 DebugLoc dl = Op.getDebugLoc();
10521 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10522 EVT VT = Op.getValueType();
10524 if (!Subtarget->hasSSE2() || !VT.isVector())
10527 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10528 ExtraVT.getScalarType().getSizeInBits();
10529 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10531 switch (VT.getSimpleVT().SimpleTy) {
10532 default: return SDValue();
10535 if (!Subtarget->hasAVX())
10537 if (!Subtarget->hasAVX2()) {
10538 // needs to be split
10539 int NumElems = VT.getVectorNumElements();
10541 // Extract the LHS vectors
10542 SDValue LHS = Op.getOperand(0);
10543 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10544 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10546 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10547 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10549 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10550 int ExtraNumElems = ExtraVT.getVectorNumElements();
10551 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10553 SDValue Extra = DAG.getValueType(ExtraVT);
10555 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10556 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10558 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10563 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10564 Op.getOperand(0), ShAmt, DAG);
10565 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10571 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10572 DebugLoc dl = Op.getDebugLoc();
10574 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10575 // There isn't any reason to disable it if the target processor supports it.
10576 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10577 SDValue Chain = Op.getOperand(0);
10578 SDValue Zero = DAG.getConstant(0, MVT::i32);
10580 DAG.getRegister(X86::ESP, MVT::i32), // Base
10581 DAG.getTargetConstant(1, MVT::i8), // Scale
10582 DAG.getRegister(0, MVT::i32), // Index
10583 DAG.getTargetConstant(0, MVT::i32), // Disp
10584 DAG.getRegister(0, MVT::i32), // Segment.
10589 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10590 array_lengthof(Ops));
10591 return SDValue(Res, 0);
10594 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10596 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10598 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10599 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10600 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10601 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10603 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10604 if (!Op1 && !Op2 && !Op3 && Op4)
10605 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10607 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10608 if (Op1 && !Op2 && !Op3 && !Op4)
10609 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10611 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10613 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10616 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10617 SelectionDAG &DAG) const {
10618 DebugLoc dl = Op.getDebugLoc();
10619 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10620 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10621 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10622 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10624 // The only fence that needs an instruction is a sequentially-consistent
10625 // cross-thread fence.
10626 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10627 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10628 // no-sse2). There isn't any reason to disable it if the target processor
10630 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10631 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10633 SDValue Chain = Op.getOperand(0);
10634 SDValue Zero = DAG.getConstant(0, MVT::i32);
10636 DAG.getRegister(X86::ESP, MVT::i32), // Base
10637 DAG.getTargetConstant(1, MVT::i8), // Scale
10638 DAG.getRegister(0, MVT::i32), // Index
10639 DAG.getTargetConstant(0, MVT::i32), // Disp
10640 DAG.getRegister(0, MVT::i32), // Segment.
10645 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10646 array_lengthof(Ops));
10647 return SDValue(Res, 0);
10650 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10651 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10655 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10656 EVT T = Op.getValueType();
10657 DebugLoc DL = Op.getDebugLoc();
10660 switch(T.getSimpleVT().SimpleTy) {
10661 default: llvm_unreachable("Invalid value type!");
10662 case MVT::i8: Reg = X86::AL; size = 1; break;
10663 case MVT::i16: Reg = X86::AX; size = 2; break;
10664 case MVT::i32: Reg = X86::EAX; size = 4; break;
10666 assert(Subtarget->is64Bit() && "Node not type legal!");
10667 Reg = X86::RAX; size = 8;
10670 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10671 Op.getOperand(2), SDValue());
10672 SDValue Ops[] = { cpIn.getValue(0),
10675 DAG.getTargetConstant(size, MVT::i8),
10676 cpIn.getValue(1) };
10677 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10678 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10679 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10682 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10686 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10687 SelectionDAG &DAG) const {
10688 assert(Subtarget->is64Bit() && "Result not type legalized?");
10689 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10690 SDValue TheChain = Op.getOperand(0);
10691 DebugLoc dl = Op.getDebugLoc();
10692 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10693 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10694 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10696 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10697 DAG.getConstant(32, MVT::i8));
10699 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10702 return DAG.getMergeValues(Ops, 2, dl);
10705 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10706 SelectionDAG &DAG) const {
10707 EVT SrcVT = Op.getOperand(0).getValueType();
10708 EVT DstVT = Op.getValueType();
10709 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10710 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10711 assert((DstVT == MVT::i64 ||
10712 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10713 "Unexpected custom BITCAST");
10714 // i64 <=> MMX conversions are Legal.
10715 if (SrcVT==MVT::i64 && DstVT.isVector())
10717 if (DstVT==MVT::i64 && SrcVT.isVector())
10719 // MMX <=> MMX conversions are Legal.
10720 if (SrcVT.isVector() && DstVT.isVector())
10722 // All other conversions need to be expanded.
10726 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10727 SDNode *Node = Op.getNode();
10728 DebugLoc dl = Node->getDebugLoc();
10729 EVT T = Node->getValueType(0);
10730 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10731 DAG.getConstant(0, T), Node->getOperand(2));
10732 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10733 cast<AtomicSDNode>(Node)->getMemoryVT(),
10734 Node->getOperand(0),
10735 Node->getOperand(1), negOp,
10736 cast<AtomicSDNode>(Node)->getSrcValue(),
10737 cast<AtomicSDNode>(Node)->getAlignment(),
10738 cast<AtomicSDNode>(Node)->getOrdering(),
10739 cast<AtomicSDNode>(Node)->getSynchScope());
10742 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10743 SDNode *Node = Op.getNode();
10744 DebugLoc dl = Node->getDebugLoc();
10745 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10747 // Convert seq_cst store -> xchg
10748 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10749 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10750 // (The only way to get a 16-byte store is cmpxchg16b)
10751 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10752 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10753 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10754 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10755 cast<AtomicSDNode>(Node)->getMemoryVT(),
10756 Node->getOperand(0),
10757 Node->getOperand(1), Node->getOperand(2),
10758 cast<AtomicSDNode>(Node)->getMemOperand(),
10759 cast<AtomicSDNode>(Node)->getOrdering(),
10760 cast<AtomicSDNode>(Node)->getSynchScope());
10761 return Swap.getValue(1);
10763 // Other atomic stores have a simple pattern.
10767 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10768 EVT VT = Op.getNode()->getValueType(0);
10770 // Let legalize expand this if it isn't a legal type yet.
10771 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10774 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10777 bool ExtraOp = false;
10778 switch (Op.getOpcode()) {
10779 default: llvm_unreachable("Invalid code");
10780 case ISD::ADDC: Opc = X86ISD::ADD; break;
10781 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10782 case ISD::SUBC: Opc = X86ISD::SUB; break;
10783 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10787 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10789 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10790 Op.getOperand(1), Op.getOperand(2));
10793 /// LowerOperation - Provide custom lowering hooks for some operations.
10795 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10796 switch (Op.getOpcode()) {
10797 default: llvm_unreachable("Should not custom lower this!");
10798 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10799 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10800 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10801 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10802 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10803 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10804 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10805 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10806 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10807 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10808 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10809 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10810 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10811 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10812 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10813 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10814 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10815 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10816 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10817 case ISD::SHL_PARTS:
10818 case ISD::SRA_PARTS:
10819 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10820 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10821 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10822 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10823 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10824 case ISD::FABS: return LowerFABS(Op, DAG);
10825 case ISD::FNEG: return LowerFNEG(Op, DAG);
10826 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10827 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10828 case ISD::SETCC: return LowerSETCC(Op, DAG);
10829 case ISD::SELECT: return LowerSELECT(Op, DAG);
10830 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10831 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10832 case ISD::VASTART: return LowerVASTART(Op, DAG);
10833 case ISD::VAARG: return LowerVAARG(Op, DAG);
10834 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10835 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10836 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10837 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10838 case ISD::FRAME_TO_ARGS_OFFSET:
10839 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10840 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10841 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10842 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10843 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10844 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10845 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10846 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10847 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10848 case ISD::MUL: return LowerMUL(Op, DAG);
10851 case ISD::SHL: return LowerShift(Op, DAG);
10857 case ISD::UMULO: return LowerXALUO(Op, DAG);
10858 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10859 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10863 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10864 case ISD::ADD: return LowerADD(Op, DAG);
10865 case ISD::SUB: return LowerSUB(Op, DAG);
10869 static void ReplaceATOMIC_LOAD(SDNode *Node,
10870 SmallVectorImpl<SDValue> &Results,
10871 SelectionDAG &DAG) {
10872 DebugLoc dl = Node->getDebugLoc();
10873 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10875 // Convert wide load -> cmpxchg8b/cmpxchg16b
10876 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10877 // (The only way to get a 16-byte load is cmpxchg16b)
10878 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10879 SDValue Zero = DAG.getConstant(0, VT);
10880 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10881 Node->getOperand(0),
10882 Node->getOperand(1), Zero, Zero,
10883 cast<AtomicSDNode>(Node)->getMemOperand(),
10884 cast<AtomicSDNode>(Node)->getOrdering(),
10885 cast<AtomicSDNode>(Node)->getSynchScope());
10886 Results.push_back(Swap.getValue(0));
10887 Results.push_back(Swap.getValue(1));
10890 void X86TargetLowering::
10891 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10892 SelectionDAG &DAG, unsigned NewOp) const {
10893 DebugLoc dl = Node->getDebugLoc();
10894 assert (Node->getValueType(0) == MVT::i64 &&
10895 "Only know how to expand i64 atomics");
10897 SDValue Chain = Node->getOperand(0);
10898 SDValue In1 = Node->getOperand(1);
10899 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10900 Node->getOperand(2), DAG.getIntPtrConstant(0));
10901 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10902 Node->getOperand(2), DAG.getIntPtrConstant(1));
10903 SDValue Ops[] = { Chain, In1, In2L, In2H };
10904 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10906 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10907 cast<MemSDNode>(Node)->getMemOperand());
10908 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10909 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10910 Results.push_back(Result.getValue(2));
10913 /// ReplaceNodeResults - Replace a node with an illegal result type
10914 /// with a new node built out of custom code.
10915 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10916 SmallVectorImpl<SDValue>&Results,
10917 SelectionDAG &DAG) const {
10918 DebugLoc dl = N->getDebugLoc();
10919 switch (N->getOpcode()) {
10921 llvm_unreachable("Do not know how to custom type legalize this operation!");
10922 case ISD::SIGN_EXTEND_INREG:
10927 // We don't want to expand or promote these.
10929 case ISD::FP_TO_SINT:
10930 case ISD::FP_TO_UINT: {
10931 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10933 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10936 std::pair<SDValue,SDValue> Vals =
10937 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10938 SDValue FIST = Vals.first, StackSlot = Vals.second;
10939 if (FIST.getNode() != 0) {
10940 EVT VT = N->getValueType(0);
10941 // Return a load from the stack slot.
10942 if (StackSlot.getNode() != 0)
10943 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10944 MachinePointerInfo(),
10945 false, false, false, 0));
10947 Results.push_back(FIST);
10951 case ISD::READCYCLECOUNTER: {
10952 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10953 SDValue TheChain = N->getOperand(0);
10954 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10955 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10957 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10959 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10960 SDValue Ops[] = { eax, edx };
10961 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10962 Results.push_back(edx.getValue(1));
10965 case ISD::ATOMIC_CMP_SWAP: {
10966 EVT T = N->getValueType(0);
10967 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10968 bool Regs64bit = T == MVT::i128;
10969 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10970 SDValue cpInL, cpInH;
10971 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10972 DAG.getConstant(0, HalfT));
10973 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10974 DAG.getConstant(1, HalfT));
10975 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10976 Regs64bit ? X86::RAX : X86::EAX,
10978 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10979 Regs64bit ? X86::RDX : X86::EDX,
10980 cpInH, cpInL.getValue(1));
10981 SDValue swapInL, swapInH;
10982 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10983 DAG.getConstant(0, HalfT));
10984 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10985 DAG.getConstant(1, HalfT));
10986 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10987 Regs64bit ? X86::RBX : X86::EBX,
10988 swapInL, cpInH.getValue(1));
10989 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10990 Regs64bit ? X86::RCX : X86::ECX,
10991 swapInH, swapInL.getValue(1));
10992 SDValue Ops[] = { swapInH.getValue(0),
10994 swapInH.getValue(1) };
10995 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10996 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10997 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10998 X86ISD::LCMPXCHG8_DAG;
10999 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11001 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11002 Regs64bit ? X86::RAX : X86::EAX,
11003 HalfT, Result.getValue(1));
11004 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11005 Regs64bit ? X86::RDX : X86::EDX,
11006 HalfT, cpOutL.getValue(2));
11007 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11008 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11009 Results.push_back(cpOutH.getValue(1));
11012 case ISD::ATOMIC_LOAD_ADD:
11013 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11015 case ISD::ATOMIC_LOAD_AND:
11016 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11018 case ISD::ATOMIC_LOAD_NAND:
11019 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11021 case ISD::ATOMIC_LOAD_OR:
11022 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11024 case ISD::ATOMIC_LOAD_SUB:
11025 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11027 case ISD::ATOMIC_LOAD_XOR:
11028 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11030 case ISD::ATOMIC_SWAP:
11031 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11033 case ISD::ATOMIC_LOAD:
11034 ReplaceATOMIC_LOAD(N, Results, DAG);
11038 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11040 default: return NULL;
11041 case X86ISD::BSF: return "X86ISD::BSF";
11042 case X86ISD::BSR: return "X86ISD::BSR";
11043 case X86ISD::SHLD: return "X86ISD::SHLD";
11044 case X86ISD::SHRD: return "X86ISD::SHRD";
11045 case X86ISD::FAND: return "X86ISD::FAND";
11046 case X86ISD::FOR: return "X86ISD::FOR";
11047 case X86ISD::FXOR: return "X86ISD::FXOR";
11048 case X86ISD::FSRL: return "X86ISD::FSRL";
11049 case X86ISD::FILD: return "X86ISD::FILD";
11050 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11051 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11052 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11053 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11054 case X86ISD::FLD: return "X86ISD::FLD";
11055 case X86ISD::FST: return "X86ISD::FST";
11056 case X86ISD::CALL: return "X86ISD::CALL";
11057 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11058 case X86ISD::BT: return "X86ISD::BT";
11059 case X86ISD::CMP: return "X86ISD::CMP";
11060 case X86ISD::COMI: return "X86ISD::COMI";
11061 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11062 case X86ISD::SETCC: return "X86ISD::SETCC";
11063 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11064 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11065 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11066 case X86ISD::CMOV: return "X86ISD::CMOV";
11067 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11068 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11069 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11070 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11071 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11072 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11073 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11074 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11075 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11076 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11077 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11078 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11079 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11080 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11081 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11082 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11083 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11084 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11085 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11086 case X86ISD::HADD: return "X86ISD::HADD";
11087 case X86ISD::HSUB: return "X86ISD::HSUB";
11088 case X86ISD::FHADD: return "X86ISD::FHADD";
11089 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11090 case X86ISD::FMAX: return "X86ISD::FMAX";
11091 case X86ISD::FMIN: return "X86ISD::FMIN";
11092 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11093 case X86ISD::FRCP: return "X86ISD::FRCP";
11094 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11095 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11096 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11097 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11098 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11099 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11100 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11101 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11102 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11103 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11104 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11105 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11106 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11107 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11108 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11109 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11110 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11111 case X86ISD::VSHL: return "X86ISD::VSHL";
11112 case X86ISD::VSRL: return "X86ISD::VSRL";
11113 case X86ISD::VSRA: return "X86ISD::VSRA";
11114 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11115 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11116 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11117 case X86ISD::CMPP: return "X86ISD::CMPP";
11118 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11119 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11120 case X86ISD::ADD: return "X86ISD::ADD";
11121 case X86ISD::SUB: return "X86ISD::SUB";
11122 case X86ISD::ADC: return "X86ISD::ADC";
11123 case X86ISD::SBB: return "X86ISD::SBB";
11124 case X86ISD::SMUL: return "X86ISD::SMUL";
11125 case X86ISD::UMUL: return "X86ISD::UMUL";
11126 case X86ISD::INC: return "X86ISD::INC";
11127 case X86ISD::DEC: return "X86ISD::DEC";
11128 case X86ISD::OR: return "X86ISD::OR";
11129 case X86ISD::XOR: return "X86ISD::XOR";
11130 case X86ISD::AND: return "X86ISD::AND";
11131 case X86ISD::ANDN: return "X86ISD::ANDN";
11132 case X86ISD::BLSI: return "X86ISD::BLSI";
11133 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11134 case X86ISD::BLSR: return "X86ISD::BLSR";
11135 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11136 case X86ISD::PTEST: return "X86ISD::PTEST";
11137 case X86ISD::TESTP: return "X86ISD::TESTP";
11138 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11139 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11140 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11141 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11142 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11143 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11144 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11145 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11146 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11147 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11148 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11149 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11150 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11151 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11152 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11153 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11154 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11155 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11156 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11157 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11158 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11159 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11160 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11161 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11162 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11163 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11164 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11165 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11166 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11170 // isLegalAddressingMode - Return true if the addressing mode represented
11171 // by AM is legal for this target, for a load/store of the specified type.
11172 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11174 // X86 supports extremely general addressing modes.
11175 CodeModel::Model M = getTargetMachine().getCodeModel();
11176 Reloc::Model R = getTargetMachine().getRelocationModel();
11178 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11179 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11184 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11186 // If a reference to this global requires an extra load, we can't fold it.
11187 if (isGlobalStubReference(GVFlags))
11190 // If BaseGV requires a register for the PIC base, we cannot also have a
11191 // BaseReg specified.
11192 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11195 // If lower 4G is not available, then we must use rip-relative addressing.
11196 if ((M != CodeModel::Small || R != Reloc::Static) &&
11197 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11201 switch (AM.Scale) {
11207 // These scales always work.
11212 // These scales are formed with basereg+scalereg. Only accept if there is
11217 default: // Other stuff never works.
11225 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11226 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11228 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11229 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11230 if (NumBits1 <= NumBits2)
11235 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11236 if (!VT1.isInteger() || !VT2.isInteger())
11238 unsigned NumBits1 = VT1.getSizeInBits();
11239 unsigned NumBits2 = VT2.getSizeInBits();
11240 if (NumBits1 <= NumBits2)
11245 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11246 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11247 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11250 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11251 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11252 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11255 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11256 // i16 instructions are longer (0x66 prefix) and potentially slower.
11257 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11260 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11261 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11262 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11263 /// are assumed to be legal.
11265 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11267 // Very little shuffling can be done for 64-bit vectors right now.
11268 if (VT.getSizeInBits() == 64)
11271 // FIXME: pshufb, blends, shifts.
11272 return (VT.getVectorNumElements() == 2 ||
11273 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11274 isMOVLMask(M, VT) ||
11275 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11276 isPSHUFDMask(M, VT) ||
11277 isPSHUFHWMask(M, VT) ||
11278 isPSHUFLWMask(M, VT) ||
11279 isPALIGNRMask(M, VT, Subtarget) ||
11280 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11281 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11282 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11283 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11287 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11289 unsigned NumElts = VT.getVectorNumElements();
11290 // FIXME: This collection of masks seems suspect.
11293 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11294 return (isMOVLMask(Mask, VT) ||
11295 isCommutedMOVLMask(Mask, VT, true) ||
11296 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11297 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11302 //===----------------------------------------------------------------------===//
11303 // X86 Scheduler Hooks
11304 //===----------------------------------------------------------------------===//
11306 // private utility function
11307 MachineBasicBlock *
11308 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11309 MachineBasicBlock *MBB,
11316 const TargetRegisterClass *RC,
11317 bool Invert) const {
11318 // For the atomic bitwise operator, we generate
11321 // ld t1 = [bitinstr.addr]
11322 // op t2 = t1, [bitinstr.val]
11323 // not t3 = t2 (if Invert)
11325 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11327 // fallthrough -->nextMBB
11328 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11329 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11330 MachineFunction::iterator MBBIter = MBB;
11333 /// First build the CFG
11334 MachineFunction *F = MBB->getParent();
11335 MachineBasicBlock *thisMBB = MBB;
11336 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11337 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11338 F->insert(MBBIter, newMBB);
11339 F->insert(MBBIter, nextMBB);
11341 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11342 nextMBB->splice(nextMBB->begin(), thisMBB,
11343 llvm::next(MachineBasicBlock::iterator(bInstr)),
11345 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11347 // Update thisMBB to fall through to newMBB
11348 thisMBB->addSuccessor(newMBB);
11350 // newMBB jumps to itself and fall through to nextMBB
11351 newMBB->addSuccessor(nextMBB);
11352 newMBB->addSuccessor(newMBB);
11354 // Insert instructions into newMBB based on incoming instruction
11355 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11356 "unexpected number of operands");
11357 DebugLoc dl = bInstr->getDebugLoc();
11358 MachineOperand& destOper = bInstr->getOperand(0);
11359 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11360 int numArgs = bInstr->getNumOperands() - 1;
11361 for (int i=0; i < numArgs; ++i)
11362 argOpers[i] = &bInstr->getOperand(i+1);
11364 // x86 address has 4 operands: base, index, scale, and displacement
11365 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11366 int valArgIndx = lastAddrIndx + 1;
11368 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11369 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11370 for (int i=0; i <= lastAddrIndx; ++i)
11371 (*MIB).addOperand(*argOpers[i]);
11373 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11374 assert((argOpers[valArgIndx]->isReg() ||
11375 argOpers[valArgIndx]->isImm()) &&
11376 "invalid operand");
11377 if (argOpers[valArgIndx]->isReg())
11378 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11380 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11382 (*MIB).addOperand(*argOpers[valArgIndx]);
11384 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11386 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11391 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11394 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11395 for (int i=0; i <= lastAddrIndx; ++i)
11396 (*MIB).addOperand(*argOpers[i]);
11398 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11399 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11400 bInstr->memoperands_end());
11402 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11403 MIB.addReg(EAXreg);
11406 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11408 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11412 // private utility function: 64 bit atomics on 32 bit host.
11413 MachineBasicBlock *
11414 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11415 MachineBasicBlock *MBB,
11420 bool Invert) const {
11421 // For the atomic bitwise operator, we generate
11422 // thisMBB (instructions are in pairs, except cmpxchg8b)
11423 // ld t1,t2 = [bitinstr.addr]
11425 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11426 // op t5, t6 <- out1, out2, [bitinstr.val]
11427 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11428 // neg t7, t8 < t5, t6 (if Invert)
11429 // mov ECX, EBX <- t5, t6
11430 // mov EAX, EDX <- t1, t2
11431 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11432 // mov t3, t4 <- EAX, EDX
11434 // result in out1, out2
11435 // fallthrough -->nextMBB
11437 const TargetRegisterClass *RC = &X86::GR32RegClass;
11438 const unsigned LoadOpc = X86::MOV32rm;
11439 const unsigned NotOpc = X86::NOT32r;
11440 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11441 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11442 MachineFunction::iterator MBBIter = MBB;
11445 /// First build the CFG
11446 MachineFunction *F = MBB->getParent();
11447 MachineBasicBlock *thisMBB = MBB;
11448 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11449 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11450 F->insert(MBBIter, newMBB);
11451 F->insert(MBBIter, nextMBB);
11453 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11454 nextMBB->splice(nextMBB->begin(), thisMBB,
11455 llvm::next(MachineBasicBlock::iterator(bInstr)),
11457 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11459 // Update thisMBB to fall through to newMBB
11460 thisMBB->addSuccessor(newMBB);
11462 // newMBB jumps to itself and fall through to nextMBB
11463 newMBB->addSuccessor(nextMBB);
11464 newMBB->addSuccessor(newMBB);
11466 DebugLoc dl = bInstr->getDebugLoc();
11467 // Insert instructions into newMBB based on incoming instruction
11468 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11469 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11470 "unexpected number of operands");
11471 MachineOperand& dest1Oper = bInstr->getOperand(0);
11472 MachineOperand& dest2Oper = bInstr->getOperand(1);
11473 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11474 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11475 argOpers[i] = &bInstr->getOperand(i+2);
11477 // We use some of the operands multiple times, so conservatively just
11478 // clear any kill flags that might be present.
11479 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11480 argOpers[i]->setIsKill(false);
11483 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11484 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11486 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11487 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11488 for (int i=0; i <= lastAddrIndx; ++i)
11489 (*MIB).addOperand(*argOpers[i]);
11490 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11491 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11492 // add 4 to displacement.
11493 for (int i=0; i <= lastAddrIndx-2; ++i)
11494 (*MIB).addOperand(*argOpers[i]);
11495 MachineOperand newOp3 = *(argOpers[3]);
11496 if (newOp3.isImm())
11497 newOp3.setImm(newOp3.getImm()+4);
11499 newOp3.setOffset(newOp3.getOffset()+4);
11500 (*MIB).addOperand(newOp3);
11501 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11503 // t3/4 are defined later, at the bottom of the loop
11504 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11505 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11506 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11507 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11508 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11509 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11511 // The subsequent operations should be using the destination registers of
11512 // the PHI instructions.
11513 t1 = dest1Oper.getReg();
11514 t2 = dest2Oper.getReg();
11516 int valArgIndx = lastAddrIndx + 1;
11517 assert((argOpers[valArgIndx]->isReg() ||
11518 argOpers[valArgIndx]->isImm()) &&
11519 "invalid operand");
11520 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11521 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11522 if (argOpers[valArgIndx]->isReg())
11523 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11525 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11526 if (regOpcL != X86::MOV32rr)
11528 (*MIB).addOperand(*argOpers[valArgIndx]);
11529 assert(argOpers[valArgIndx + 1]->isReg() ==
11530 argOpers[valArgIndx]->isReg());
11531 assert(argOpers[valArgIndx + 1]->isImm() ==
11532 argOpers[valArgIndx]->isImm());
11533 if (argOpers[valArgIndx + 1]->isReg())
11534 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11536 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11537 if (regOpcH != X86::MOV32rr)
11539 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11543 t7 = F->getRegInfo().createVirtualRegister(RC);
11544 t8 = F->getRegInfo().createVirtualRegister(RC);
11545 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11546 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11552 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11554 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11557 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11559 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11562 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11563 for (int i=0; i <= lastAddrIndx; ++i)
11564 (*MIB).addOperand(*argOpers[i]);
11566 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11567 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11568 bInstr->memoperands_end());
11570 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11571 MIB.addReg(X86::EAX);
11572 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11573 MIB.addReg(X86::EDX);
11576 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11578 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11582 // private utility function
11583 MachineBasicBlock *
11584 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11585 MachineBasicBlock *MBB,
11586 unsigned cmovOpc) const {
11587 // For the atomic min/max operator, we generate
11590 // ld t1 = [min/max.addr]
11591 // mov t2 = [min/max.val]
11593 // cmov[cond] t2 = t1
11595 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11597 // fallthrough -->nextMBB
11599 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11600 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11601 MachineFunction::iterator MBBIter = MBB;
11604 /// First build the CFG
11605 MachineFunction *F = MBB->getParent();
11606 MachineBasicBlock *thisMBB = MBB;
11607 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11608 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11609 F->insert(MBBIter, newMBB);
11610 F->insert(MBBIter, nextMBB);
11612 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11613 nextMBB->splice(nextMBB->begin(), thisMBB,
11614 llvm::next(MachineBasicBlock::iterator(mInstr)),
11616 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11618 // Update thisMBB to fall through to newMBB
11619 thisMBB->addSuccessor(newMBB);
11621 // newMBB jumps to newMBB and fall through to nextMBB
11622 newMBB->addSuccessor(nextMBB);
11623 newMBB->addSuccessor(newMBB);
11625 DebugLoc dl = mInstr->getDebugLoc();
11626 // Insert instructions into newMBB based on incoming instruction
11627 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11628 "unexpected number of operands");
11629 MachineOperand& destOper = mInstr->getOperand(0);
11630 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11631 int numArgs = mInstr->getNumOperands() - 1;
11632 for (int i=0; i < numArgs; ++i)
11633 argOpers[i] = &mInstr->getOperand(i+1);
11635 // x86 address has 4 operands: base, index, scale, and displacement
11636 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11637 int valArgIndx = lastAddrIndx + 1;
11639 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11640 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11641 for (int i=0; i <= lastAddrIndx; ++i)
11642 (*MIB).addOperand(*argOpers[i]);
11644 // We only support register and immediate values
11645 assert((argOpers[valArgIndx]->isReg() ||
11646 argOpers[valArgIndx]->isImm()) &&
11647 "invalid operand");
11649 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11650 if (argOpers[valArgIndx]->isReg())
11651 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11653 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11654 (*MIB).addOperand(*argOpers[valArgIndx]);
11656 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11659 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11664 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11665 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11669 // Cmp and exchange if none has modified the memory location
11670 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11671 for (int i=0; i <= lastAddrIndx; ++i)
11672 (*MIB).addOperand(*argOpers[i]);
11674 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11675 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11676 mInstr->memoperands_end());
11678 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11679 MIB.addReg(X86::EAX);
11682 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11684 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11688 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11689 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11690 // in the .td file.
11691 MachineBasicBlock *
11692 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11693 unsigned numArgs, bool memArg) const {
11694 assert(Subtarget->hasSSE42() &&
11695 "Target must have SSE4.2 or AVX features enabled");
11697 DebugLoc dl = MI->getDebugLoc();
11698 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11700 if (!Subtarget->hasAVX()) {
11702 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11704 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11707 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11709 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11712 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11713 for (unsigned i = 0; i < numArgs; ++i) {
11714 MachineOperand &Op = MI->getOperand(i+1);
11715 if (!(Op.isReg() && Op.isImplicit()))
11716 MIB.addOperand(Op);
11718 BuildMI(*BB, MI, dl,
11719 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11720 MI->getOperand(0).getReg())
11721 .addReg(X86::XMM0);
11723 MI->eraseFromParent();
11727 MachineBasicBlock *
11728 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11729 DebugLoc dl = MI->getDebugLoc();
11730 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11732 // Address into RAX/EAX, other two args into ECX, EDX.
11733 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11734 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11735 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11736 for (int i = 0; i < X86::AddrNumOperands; ++i)
11737 MIB.addOperand(MI->getOperand(i));
11739 unsigned ValOps = X86::AddrNumOperands;
11740 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11741 .addReg(MI->getOperand(ValOps).getReg());
11742 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11743 .addReg(MI->getOperand(ValOps+1).getReg());
11745 // The instruction doesn't actually take any operands though.
11746 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11748 MI->eraseFromParent(); // The pseudo is gone now.
11752 MachineBasicBlock *
11753 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11754 DebugLoc dl = MI->getDebugLoc();
11755 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11757 // First arg in ECX, the second in EAX.
11758 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11759 .addReg(MI->getOperand(0).getReg());
11760 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11761 .addReg(MI->getOperand(1).getReg());
11763 // The instruction doesn't actually take any operands though.
11764 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11766 MI->eraseFromParent(); // The pseudo is gone now.
11770 MachineBasicBlock *
11771 X86TargetLowering::EmitVAARG64WithCustomInserter(
11773 MachineBasicBlock *MBB) const {
11774 // Emit va_arg instruction on X86-64.
11776 // Operands to this pseudo-instruction:
11777 // 0 ) Output : destination address (reg)
11778 // 1-5) Input : va_list address (addr, i64mem)
11779 // 6 ) ArgSize : Size (in bytes) of vararg type
11780 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11781 // 8 ) Align : Alignment of type
11782 // 9 ) EFLAGS (implicit-def)
11784 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11785 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11787 unsigned DestReg = MI->getOperand(0).getReg();
11788 MachineOperand &Base = MI->getOperand(1);
11789 MachineOperand &Scale = MI->getOperand(2);
11790 MachineOperand &Index = MI->getOperand(3);
11791 MachineOperand &Disp = MI->getOperand(4);
11792 MachineOperand &Segment = MI->getOperand(5);
11793 unsigned ArgSize = MI->getOperand(6).getImm();
11794 unsigned ArgMode = MI->getOperand(7).getImm();
11795 unsigned Align = MI->getOperand(8).getImm();
11797 // Memory Reference
11798 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11799 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11800 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11802 // Machine Information
11803 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11804 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11805 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11806 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11807 DebugLoc DL = MI->getDebugLoc();
11809 // struct va_list {
11812 // i64 overflow_area (address)
11813 // i64 reg_save_area (address)
11815 // sizeof(va_list) = 24
11816 // alignment(va_list) = 8
11818 unsigned TotalNumIntRegs = 6;
11819 unsigned TotalNumXMMRegs = 8;
11820 bool UseGPOffset = (ArgMode == 1);
11821 bool UseFPOffset = (ArgMode == 2);
11822 unsigned MaxOffset = TotalNumIntRegs * 8 +
11823 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11825 /* Align ArgSize to a multiple of 8 */
11826 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11827 bool NeedsAlign = (Align > 8);
11829 MachineBasicBlock *thisMBB = MBB;
11830 MachineBasicBlock *overflowMBB;
11831 MachineBasicBlock *offsetMBB;
11832 MachineBasicBlock *endMBB;
11834 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11835 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11836 unsigned OffsetReg = 0;
11838 if (!UseGPOffset && !UseFPOffset) {
11839 // If we only pull from the overflow region, we don't create a branch.
11840 // We don't need to alter control flow.
11841 OffsetDestReg = 0; // unused
11842 OverflowDestReg = DestReg;
11845 overflowMBB = thisMBB;
11848 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11849 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11850 // If not, pull from overflow_area. (branch to overflowMBB)
11855 // offsetMBB overflowMBB
11860 // Registers for the PHI in endMBB
11861 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11862 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11864 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11865 MachineFunction *MF = MBB->getParent();
11866 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11867 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11868 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11870 MachineFunction::iterator MBBIter = MBB;
11873 // Insert the new basic blocks
11874 MF->insert(MBBIter, offsetMBB);
11875 MF->insert(MBBIter, overflowMBB);
11876 MF->insert(MBBIter, endMBB);
11878 // Transfer the remainder of MBB and its successor edges to endMBB.
11879 endMBB->splice(endMBB->begin(), thisMBB,
11880 llvm::next(MachineBasicBlock::iterator(MI)),
11882 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11884 // Make offsetMBB and overflowMBB successors of thisMBB
11885 thisMBB->addSuccessor(offsetMBB);
11886 thisMBB->addSuccessor(overflowMBB);
11888 // endMBB is a successor of both offsetMBB and overflowMBB
11889 offsetMBB->addSuccessor(endMBB);
11890 overflowMBB->addSuccessor(endMBB);
11892 // Load the offset value into a register
11893 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11894 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11898 .addDisp(Disp, UseFPOffset ? 4 : 0)
11899 .addOperand(Segment)
11900 .setMemRefs(MMOBegin, MMOEnd);
11902 // Check if there is enough room left to pull this argument.
11903 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11905 .addImm(MaxOffset + 8 - ArgSizeA8);
11907 // Branch to "overflowMBB" if offset >= max
11908 // Fall through to "offsetMBB" otherwise
11909 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11910 .addMBB(overflowMBB);
11913 // In offsetMBB, emit code to use the reg_save_area.
11915 assert(OffsetReg != 0);
11917 // Read the reg_save_area address.
11918 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11919 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11924 .addOperand(Segment)
11925 .setMemRefs(MMOBegin, MMOEnd);
11927 // Zero-extend the offset
11928 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11929 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11932 .addImm(X86::sub_32bit);
11934 // Add the offset to the reg_save_area to get the final address.
11935 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11936 .addReg(OffsetReg64)
11937 .addReg(RegSaveReg);
11939 // Compute the offset for the next argument
11940 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11941 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11943 .addImm(UseFPOffset ? 16 : 8);
11945 // Store it back into the va_list.
11946 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11950 .addDisp(Disp, UseFPOffset ? 4 : 0)
11951 .addOperand(Segment)
11952 .addReg(NextOffsetReg)
11953 .setMemRefs(MMOBegin, MMOEnd);
11956 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11961 // Emit code to use overflow area
11964 // Load the overflow_area address into a register.
11965 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11966 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11971 .addOperand(Segment)
11972 .setMemRefs(MMOBegin, MMOEnd);
11974 // If we need to align it, do so. Otherwise, just copy the address
11975 // to OverflowDestReg.
11977 // Align the overflow address
11978 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11979 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11981 // aligned_addr = (addr + (align-1)) & ~(align-1)
11982 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11983 .addReg(OverflowAddrReg)
11986 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11988 .addImm(~(uint64_t)(Align-1));
11990 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11991 .addReg(OverflowAddrReg);
11994 // Compute the next overflow address after this argument.
11995 // (the overflow address should be kept 8-byte aligned)
11996 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11997 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11998 .addReg(OverflowDestReg)
11999 .addImm(ArgSizeA8);
12001 // Store the new overflow address.
12002 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12007 .addOperand(Segment)
12008 .addReg(NextAddrReg)
12009 .setMemRefs(MMOBegin, MMOEnd);
12011 // If we branched, emit the PHI to the front of endMBB.
12013 BuildMI(*endMBB, endMBB->begin(), DL,
12014 TII->get(X86::PHI), DestReg)
12015 .addReg(OffsetDestReg).addMBB(offsetMBB)
12016 .addReg(OverflowDestReg).addMBB(overflowMBB);
12019 // Erase the pseudo instruction
12020 MI->eraseFromParent();
12025 MachineBasicBlock *
12026 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12028 MachineBasicBlock *MBB) const {
12029 // Emit code to save XMM registers to the stack. The ABI says that the
12030 // number of registers to save is given in %al, so it's theoretically
12031 // possible to do an indirect jump trick to avoid saving all of them,
12032 // however this code takes a simpler approach and just executes all
12033 // of the stores if %al is non-zero. It's less code, and it's probably
12034 // easier on the hardware branch predictor, and stores aren't all that
12035 // expensive anyway.
12037 // Create the new basic blocks. One block contains all the XMM stores,
12038 // and one block is the final destination regardless of whether any
12039 // stores were performed.
12040 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12041 MachineFunction *F = MBB->getParent();
12042 MachineFunction::iterator MBBIter = MBB;
12044 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12045 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12046 F->insert(MBBIter, XMMSaveMBB);
12047 F->insert(MBBIter, EndMBB);
12049 // Transfer the remainder of MBB and its successor edges to EndMBB.
12050 EndMBB->splice(EndMBB->begin(), MBB,
12051 llvm::next(MachineBasicBlock::iterator(MI)),
12053 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12055 // The original block will now fall through to the XMM save block.
12056 MBB->addSuccessor(XMMSaveMBB);
12057 // The XMMSaveMBB will fall through to the end block.
12058 XMMSaveMBB->addSuccessor(EndMBB);
12060 // Now add the instructions.
12061 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12062 DebugLoc DL = MI->getDebugLoc();
12064 unsigned CountReg = MI->getOperand(0).getReg();
12065 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12066 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12068 if (!Subtarget->isTargetWin64()) {
12069 // If %al is 0, branch around the XMM save block.
12070 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12071 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12072 MBB->addSuccessor(EndMBB);
12075 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12076 // In the XMM save block, save all the XMM argument registers.
12077 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12078 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12079 MachineMemOperand *MMO =
12080 F->getMachineMemOperand(
12081 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12082 MachineMemOperand::MOStore,
12083 /*Size=*/16, /*Align=*/16);
12084 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12085 .addFrameIndex(RegSaveFrameIndex)
12086 .addImm(/*Scale=*/1)
12087 .addReg(/*IndexReg=*/0)
12088 .addImm(/*Disp=*/Offset)
12089 .addReg(/*Segment=*/0)
12090 .addReg(MI->getOperand(i).getReg())
12091 .addMemOperand(MMO);
12094 MI->eraseFromParent(); // The pseudo instruction is gone now.
12099 // The EFLAGS operand of SelectItr might be missing a kill marker
12100 // because there were multiple uses of EFLAGS, and ISel didn't know
12101 // which to mark. Figure out whether SelectItr should have had a
12102 // kill marker, and set it if it should. Returns the correct kill
12104 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12105 MachineBasicBlock* BB,
12106 const TargetRegisterInfo* TRI) {
12107 // Scan forward through BB for a use/def of EFLAGS.
12108 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12109 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12110 const MachineInstr& mi = *miI;
12111 if (mi.readsRegister(X86::EFLAGS))
12113 if (mi.definesRegister(X86::EFLAGS))
12114 break; // Should have kill-flag - update below.
12117 // If we hit the end of the block, check whether EFLAGS is live into a
12119 if (miI == BB->end()) {
12120 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12121 sEnd = BB->succ_end();
12122 sItr != sEnd; ++sItr) {
12123 MachineBasicBlock* succ = *sItr;
12124 if (succ->isLiveIn(X86::EFLAGS))
12129 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12130 // out. SelectMI should have a kill flag on EFLAGS.
12131 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12135 MachineBasicBlock *
12136 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12137 MachineBasicBlock *BB) const {
12138 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12139 DebugLoc DL = MI->getDebugLoc();
12141 // To "insert" a SELECT_CC instruction, we actually have to insert the
12142 // diamond control-flow pattern. The incoming instruction knows the
12143 // destination vreg to set, the condition code register to branch on, the
12144 // true/false values to select between, and a branch opcode to use.
12145 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12146 MachineFunction::iterator It = BB;
12152 // cmpTY ccX, r1, r2
12154 // fallthrough --> copy0MBB
12155 MachineBasicBlock *thisMBB = BB;
12156 MachineFunction *F = BB->getParent();
12157 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12158 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12159 F->insert(It, copy0MBB);
12160 F->insert(It, sinkMBB);
12162 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12163 // live into the sink and copy blocks.
12164 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12165 if (!MI->killsRegister(X86::EFLAGS) &&
12166 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12167 copy0MBB->addLiveIn(X86::EFLAGS);
12168 sinkMBB->addLiveIn(X86::EFLAGS);
12171 // Transfer the remainder of BB and its successor edges to sinkMBB.
12172 sinkMBB->splice(sinkMBB->begin(), BB,
12173 llvm::next(MachineBasicBlock::iterator(MI)),
12175 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12177 // Add the true and fallthrough blocks as its successors.
12178 BB->addSuccessor(copy0MBB);
12179 BB->addSuccessor(sinkMBB);
12181 // Create the conditional branch instruction.
12183 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12184 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12187 // %FalseValue = ...
12188 // # fallthrough to sinkMBB
12189 copy0MBB->addSuccessor(sinkMBB);
12192 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12194 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12195 TII->get(X86::PHI), MI->getOperand(0).getReg())
12196 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12197 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12199 MI->eraseFromParent(); // The pseudo instruction is gone now.
12203 MachineBasicBlock *
12204 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12205 bool Is64Bit) const {
12206 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12207 DebugLoc DL = MI->getDebugLoc();
12208 MachineFunction *MF = BB->getParent();
12209 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12211 assert(getTargetMachine().Options.EnableSegmentedStacks);
12213 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12214 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12217 // ... [Till the alloca]
12218 // If stacklet is not large enough, jump to mallocMBB
12221 // Allocate by subtracting from RSP
12222 // Jump to continueMBB
12225 // Allocate by call to runtime
12229 // [rest of original BB]
12232 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12233 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12234 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12236 MachineRegisterInfo &MRI = MF->getRegInfo();
12237 const TargetRegisterClass *AddrRegClass =
12238 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12240 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12241 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12242 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12243 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12244 sizeVReg = MI->getOperand(1).getReg(),
12245 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12247 MachineFunction::iterator MBBIter = BB;
12250 MF->insert(MBBIter, bumpMBB);
12251 MF->insert(MBBIter, mallocMBB);
12252 MF->insert(MBBIter, continueMBB);
12254 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12255 (MachineBasicBlock::iterator(MI)), BB->end());
12256 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12258 // Add code to the main basic block to check if the stack limit has been hit,
12259 // and if so, jump to mallocMBB otherwise to bumpMBB.
12260 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12261 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12262 .addReg(tmpSPVReg).addReg(sizeVReg);
12263 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12264 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12265 .addReg(SPLimitVReg);
12266 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12268 // bumpMBB simply decreases the stack pointer, since we know the current
12269 // stacklet has enough space.
12270 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12271 .addReg(SPLimitVReg);
12272 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12273 .addReg(SPLimitVReg);
12274 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12276 // Calls into a routine in libgcc to allocate more space from the heap.
12277 const uint32_t *RegMask =
12278 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12280 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12282 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12283 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12284 .addRegMask(RegMask)
12285 .addReg(X86::RAX, RegState::ImplicitDefine);
12287 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12289 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12290 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12291 .addExternalSymbol("__morestack_allocate_stack_space")
12292 .addRegMask(RegMask)
12293 .addReg(X86::EAX, RegState::ImplicitDefine);
12297 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12300 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12301 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12302 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12304 // Set up the CFG correctly.
12305 BB->addSuccessor(bumpMBB);
12306 BB->addSuccessor(mallocMBB);
12307 mallocMBB->addSuccessor(continueMBB);
12308 bumpMBB->addSuccessor(continueMBB);
12310 // Take care of the PHI nodes.
12311 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12312 MI->getOperand(0).getReg())
12313 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12314 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12316 // Delete the original pseudo instruction.
12317 MI->eraseFromParent();
12320 return continueMBB;
12323 MachineBasicBlock *
12324 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12325 MachineBasicBlock *BB) const {
12326 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12327 DebugLoc DL = MI->getDebugLoc();
12329 assert(!Subtarget->isTargetEnvMacho());
12331 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12332 // non-trivial part is impdef of ESP.
12334 if (Subtarget->isTargetWin64()) {
12335 if (Subtarget->isTargetCygMing()) {
12336 // ___chkstk(Mingw64):
12337 // Clobbers R10, R11, RAX and EFLAGS.
12339 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12340 .addExternalSymbol("___chkstk")
12341 .addReg(X86::RAX, RegState::Implicit)
12342 .addReg(X86::RSP, RegState::Implicit)
12343 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12344 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12345 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12347 // __chkstk(MSVCRT): does not update stack pointer.
12348 // Clobbers R10, R11 and EFLAGS.
12349 // FIXME: RAX(allocated size) might be reused and not killed.
12350 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12351 .addExternalSymbol("__chkstk")
12352 .addReg(X86::RAX, RegState::Implicit)
12353 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12354 // RAX has the offset to subtracted from RSP.
12355 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12360 const char *StackProbeSymbol =
12361 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12363 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12364 .addExternalSymbol(StackProbeSymbol)
12365 .addReg(X86::EAX, RegState::Implicit)
12366 .addReg(X86::ESP, RegState::Implicit)
12367 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12368 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12369 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12372 MI->eraseFromParent(); // The pseudo instruction is gone now.
12376 MachineBasicBlock *
12377 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12378 MachineBasicBlock *BB) const {
12379 // This is pretty easy. We're taking the value that we received from
12380 // our load from the relocation, sticking it in either RDI (x86-64)
12381 // or EAX and doing an indirect call. The return value will then
12382 // be in the normal return register.
12383 const X86InstrInfo *TII
12384 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12385 DebugLoc DL = MI->getDebugLoc();
12386 MachineFunction *F = BB->getParent();
12388 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12389 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12391 // Get a register mask for the lowered call.
12392 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12393 // proper register mask.
12394 const uint32_t *RegMask =
12395 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12396 if (Subtarget->is64Bit()) {
12397 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12398 TII->get(X86::MOV64rm), X86::RDI)
12400 .addImm(0).addReg(0)
12401 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12402 MI->getOperand(3).getTargetFlags())
12404 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12405 addDirectMem(MIB, X86::RDI);
12406 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12407 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12408 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12409 TII->get(X86::MOV32rm), X86::EAX)
12411 .addImm(0).addReg(0)
12412 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12413 MI->getOperand(3).getTargetFlags())
12415 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12416 addDirectMem(MIB, X86::EAX);
12417 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12419 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12420 TII->get(X86::MOV32rm), X86::EAX)
12421 .addReg(TII->getGlobalBaseReg(F))
12422 .addImm(0).addReg(0)
12423 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12424 MI->getOperand(3).getTargetFlags())
12426 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12427 addDirectMem(MIB, X86::EAX);
12428 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12431 MI->eraseFromParent(); // The pseudo instruction is gone now.
12435 MachineBasicBlock *
12436 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12437 MachineBasicBlock *BB) const {
12438 switch (MI->getOpcode()) {
12439 default: llvm_unreachable("Unexpected instr type to insert");
12440 case X86::TAILJMPd64:
12441 case X86::TAILJMPr64:
12442 case X86::TAILJMPm64:
12443 llvm_unreachable("TAILJMP64 would not be touched here.");
12444 case X86::TCRETURNdi64:
12445 case X86::TCRETURNri64:
12446 case X86::TCRETURNmi64:
12448 case X86::WIN_ALLOCA:
12449 return EmitLoweredWinAlloca(MI, BB);
12450 case X86::SEG_ALLOCA_32:
12451 return EmitLoweredSegAlloca(MI, BB, false);
12452 case X86::SEG_ALLOCA_64:
12453 return EmitLoweredSegAlloca(MI, BB, true);
12454 case X86::TLSCall_32:
12455 case X86::TLSCall_64:
12456 return EmitLoweredTLSCall(MI, BB);
12457 case X86::CMOV_GR8:
12458 case X86::CMOV_FR32:
12459 case X86::CMOV_FR64:
12460 case X86::CMOV_V4F32:
12461 case X86::CMOV_V2F64:
12462 case X86::CMOV_V2I64:
12463 case X86::CMOV_V8F32:
12464 case X86::CMOV_V4F64:
12465 case X86::CMOV_V4I64:
12466 case X86::CMOV_GR16:
12467 case X86::CMOV_GR32:
12468 case X86::CMOV_RFP32:
12469 case X86::CMOV_RFP64:
12470 case X86::CMOV_RFP80:
12471 return EmitLoweredSelect(MI, BB);
12473 case X86::FP32_TO_INT16_IN_MEM:
12474 case X86::FP32_TO_INT32_IN_MEM:
12475 case X86::FP32_TO_INT64_IN_MEM:
12476 case X86::FP64_TO_INT16_IN_MEM:
12477 case X86::FP64_TO_INT32_IN_MEM:
12478 case X86::FP64_TO_INT64_IN_MEM:
12479 case X86::FP80_TO_INT16_IN_MEM:
12480 case X86::FP80_TO_INT32_IN_MEM:
12481 case X86::FP80_TO_INT64_IN_MEM: {
12482 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12483 DebugLoc DL = MI->getDebugLoc();
12485 // Change the floating point control register to use "round towards zero"
12486 // mode when truncating to an integer value.
12487 MachineFunction *F = BB->getParent();
12488 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12489 addFrameReference(BuildMI(*BB, MI, DL,
12490 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12492 // Load the old value of the high byte of the control word...
12494 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12495 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12498 // Set the high part to be round to zero...
12499 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12502 // Reload the modified control word now...
12503 addFrameReference(BuildMI(*BB, MI, DL,
12504 TII->get(X86::FLDCW16m)), CWFrameIdx);
12506 // Restore the memory image of control word to original value
12507 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12510 // Get the X86 opcode to use.
12512 switch (MI->getOpcode()) {
12513 default: llvm_unreachable("illegal opcode!");
12514 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12515 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12516 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12517 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12518 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12519 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12520 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12521 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12522 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12526 MachineOperand &Op = MI->getOperand(0);
12528 AM.BaseType = X86AddressMode::RegBase;
12529 AM.Base.Reg = Op.getReg();
12531 AM.BaseType = X86AddressMode::FrameIndexBase;
12532 AM.Base.FrameIndex = Op.getIndex();
12534 Op = MI->getOperand(1);
12536 AM.Scale = Op.getImm();
12537 Op = MI->getOperand(2);
12539 AM.IndexReg = Op.getImm();
12540 Op = MI->getOperand(3);
12541 if (Op.isGlobal()) {
12542 AM.GV = Op.getGlobal();
12544 AM.Disp = Op.getImm();
12546 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12547 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12549 // Reload the original control word now.
12550 addFrameReference(BuildMI(*BB, MI, DL,
12551 TII->get(X86::FLDCW16m)), CWFrameIdx);
12553 MI->eraseFromParent(); // The pseudo instruction is gone now.
12556 // String/text processing lowering.
12557 case X86::PCMPISTRM128REG:
12558 case X86::VPCMPISTRM128REG:
12559 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12560 case X86::PCMPISTRM128MEM:
12561 case X86::VPCMPISTRM128MEM:
12562 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12563 case X86::PCMPESTRM128REG:
12564 case X86::VPCMPESTRM128REG:
12565 return EmitPCMP(MI, BB, 5, false /* in mem */);
12566 case X86::PCMPESTRM128MEM:
12567 case X86::VPCMPESTRM128MEM:
12568 return EmitPCMP(MI, BB, 5, true /* in mem */);
12570 // Thread synchronization.
12572 return EmitMonitor(MI, BB);
12574 return EmitMwait(MI, BB);
12576 // Atomic Lowering.
12577 case X86::ATOMAND32:
12578 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12579 X86::AND32ri, X86::MOV32rm,
12581 X86::NOT32r, X86::EAX,
12582 &X86::GR32RegClass);
12583 case X86::ATOMOR32:
12584 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12585 X86::OR32ri, X86::MOV32rm,
12587 X86::NOT32r, X86::EAX,
12588 &X86::GR32RegClass);
12589 case X86::ATOMXOR32:
12590 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12591 X86::XOR32ri, X86::MOV32rm,
12593 X86::NOT32r, X86::EAX,
12594 &X86::GR32RegClass);
12595 case X86::ATOMNAND32:
12596 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12597 X86::AND32ri, X86::MOV32rm,
12599 X86::NOT32r, X86::EAX,
12600 &X86::GR32RegClass, true);
12601 case X86::ATOMMIN32:
12602 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12603 case X86::ATOMMAX32:
12604 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12605 case X86::ATOMUMIN32:
12606 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12607 case X86::ATOMUMAX32:
12608 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12610 case X86::ATOMAND16:
12611 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12612 X86::AND16ri, X86::MOV16rm,
12614 X86::NOT16r, X86::AX,
12615 &X86::GR16RegClass);
12616 case X86::ATOMOR16:
12617 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12618 X86::OR16ri, X86::MOV16rm,
12620 X86::NOT16r, X86::AX,
12621 &X86::GR16RegClass);
12622 case X86::ATOMXOR16:
12623 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12624 X86::XOR16ri, X86::MOV16rm,
12626 X86::NOT16r, X86::AX,
12627 &X86::GR16RegClass);
12628 case X86::ATOMNAND16:
12629 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12630 X86::AND16ri, X86::MOV16rm,
12632 X86::NOT16r, X86::AX,
12633 &X86::GR16RegClass, true);
12634 case X86::ATOMMIN16:
12635 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12636 case X86::ATOMMAX16:
12637 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12638 case X86::ATOMUMIN16:
12639 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12640 case X86::ATOMUMAX16:
12641 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12643 case X86::ATOMAND8:
12644 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12645 X86::AND8ri, X86::MOV8rm,
12647 X86::NOT8r, X86::AL,
12648 &X86::GR8RegClass);
12650 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12651 X86::OR8ri, X86::MOV8rm,
12653 X86::NOT8r, X86::AL,
12654 &X86::GR8RegClass);
12655 case X86::ATOMXOR8:
12656 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12657 X86::XOR8ri, X86::MOV8rm,
12659 X86::NOT8r, X86::AL,
12660 &X86::GR8RegClass);
12661 case X86::ATOMNAND8:
12662 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12663 X86::AND8ri, X86::MOV8rm,
12665 X86::NOT8r, X86::AL,
12666 &X86::GR8RegClass, true);
12667 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12668 // This group is for 64-bit host.
12669 case X86::ATOMAND64:
12670 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12671 X86::AND64ri32, X86::MOV64rm,
12673 X86::NOT64r, X86::RAX,
12674 &X86::GR64RegClass);
12675 case X86::ATOMOR64:
12676 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12677 X86::OR64ri32, X86::MOV64rm,
12679 X86::NOT64r, X86::RAX,
12680 &X86::GR64RegClass);
12681 case X86::ATOMXOR64:
12682 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12683 X86::XOR64ri32, X86::MOV64rm,
12685 X86::NOT64r, X86::RAX,
12686 &X86::GR64RegClass);
12687 case X86::ATOMNAND64:
12688 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12689 X86::AND64ri32, X86::MOV64rm,
12691 X86::NOT64r, X86::RAX,
12692 &X86::GR64RegClass, true);
12693 case X86::ATOMMIN64:
12694 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12695 case X86::ATOMMAX64:
12696 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12697 case X86::ATOMUMIN64:
12698 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12699 case X86::ATOMUMAX64:
12700 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12702 // This group does 64-bit operations on a 32-bit host.
12703 case X86::ATOMAND6432:
12704 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12705 X86::AND32rr, X86::AND32rr,
12706 X86::AND32ri, X86::AND32ri,
12708 case X86::ATOMOR6432:
12709 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12710 X86::OR32rr, X86::OR32rr,
12711 X86::OR32ri, X86::OR32ri,
12713 case X86::ATOMXOR6432:
12714 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12715 X86::XOR32rr, X86::XOR32rr,
12716 X86::XOR32ri, X86::XOR32ri,
12718 case X86::ATOMNAND6432:
12719 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12720 X86::AND32rr, X86::AND32rr,
12721 X86::AND32ri, X86::AND32ri,
12723 case X86::ATOMADD6432:
12724 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12725 X86::ADD32rr, X86::ADC32rr,
12726 X86::ADD32ri, X86::ADC32ri,
12728 case X86::ATOMSUB6432:
12729 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12730 X86::SUB32rr, X86::SBB32rr,
12731 X86::SUB32ri, X86::SBB32ri,
12733 case X86::ATOMSWAP6432:
12734 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12735 X86::MOV32rr, X86::MOV32rr,
12736 X86::MOV32ri, X86::MOV32ri,
12738 case X86::VASTART_SAVE_XMM_REGS:
12739 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12741 case X86::VAARG_64:
12742 return EmitVAARG64WithCustomInserter(MI, BB);
12746 //===----------------------------------------------------------------------===//
12747 // X86 Optimization Hooks
12748 //===----------------------------------------------------------------------===//
12750 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12753 const SelectionDAG &DAG,
12754 unsigned Depth) const {
12755 unsigned BitWidth = KnownZero.getBitWidth();
12756 unsigned Opc = Op.getOpcode();
12757 assert((Opc >= ISD::BUILTIN_OP_END ||
12758 Opc == ISD::INTRINSIC_WO_CHAIN ||
12759 Opc == ISD::INTRINSIC_W_CHAIN ||
12760 Opc == ISD::INTRINSIC_VOID) &&
12761 "Should use MaskedValueIsZero if you don't know whether Op"
12762 " is a target node!");
12764 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12778 // These nodes' second result is a boolean.
12779 if (Op.getResNo() == 0)
12782 case X86ISD::SETCC:
12783 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12785 case ISD::INTRINSIC_WO_CHAIN: {
12786 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12787 unsigned NumLoBits = 0;
12790 case Intrinsic::x86_sse_movmsk_ps:
12791 case Intrinsic::x86_avx_movmsk_ps_256:
12792 case Intrinsic::x86_sse2_movmsk_pd:
12793 case Intrinsic::x86_avx_movmsk_pd_256:
12794 case Intrinsic::x86_mmx_pmovmskb:
12795 case Intrinsic::x86_sse2_pmovmskb_128:
12796 case Intrinsic::x86_avx2_pmovmskb: {
12797 // High bits of movmskp{s|d}, pmovmskb are known zero.
12799 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12800 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12801 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12802 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12803 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12804 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12805 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12806 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12808 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12817 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12818 unsigned Depth) const {
12819 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12820 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12821 return Op.getValueType().getScalarType().getSizeInBits();
12827 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12828 /// node is a GlobalAddress + offset.
12829 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12830 const GlobalValue* &GA,
12831 int64_t &Offset) const {
12832 if (N->getOpcode() == X86ISD::Wrapper) {
12833 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12834 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12835 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12839 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12842 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12843 /// same as extracting the high 128-bit part of 256-bit vector and then
12844 /// inserting the result into the low part of a new 256-bit vector
12845 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12846 EVT VT = SVOp->getValueType(0);
12847 int NumElems = VT.getVectorNumElements();
12849 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12850 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12851 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12852 SVOp->getMaskElt(j) >= 0)
12858 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12859 /// same as extracting the low 128-bit part of 256-bit vector and then
12860 /// inserting the result into the high part of a new 256-bit vector
12861 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12862 EVT VT = SVOp->getValueType(0);
12863 int NumElems = VT.getVectorNumElements();
12865 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12866 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12867 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12868 SVOp->getMaskElt(j) >= 0)
12874 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12875 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12876 TargetLowering::DAGCombinerInfo &DCI,
12877 const X86Subtarget* Subtarget) {
12878 DebugLoc dl = N->getDebugLoc();
12879 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12880 SDValue V1 = SVOp->getOperand(0);
12881 SDValue V2 = SVOp->getOperand(1);
12882 EVT VT = SVOp->getValueType(0);
12883 int NumElems = VT.getVectorNumElements();
12885 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12886 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12890 // V UNDEF BUILD_VECTOR UNDEF
12892 // CONCAT_VECTOR CONCAT_VECTOR
12895 // RESULT: V + zero extended
12897 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12898 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12899 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12902 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12905 // To match the shuffle mask, the first half of the mask should
12906 // be exactly the first vector, and all the rest a splat with the
12907 // first element of the second one.
12908 for (int i = 0; i < NumElems/2; ++i)
12909 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12910 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12913 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12914 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12915 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12916 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12918 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12920 Ld->getPointerInfo(),
12921 Ld->getAlignment(),
12922 false/*isVolatile*/, true/*ReadMem*/,
12923 false/*WriteMem*/);
12924 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12927 // Emit a zeroed vector and insert the desired subvector on its
12929 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12930 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
12931 return DCI.CombineTo(N, InsV);
12934 //===--------------------------------------------------------------------===//
12935 // Combine some shuffles into subvector extracts and inserts:
12938 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12939 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12940 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
12941 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
12942 return DCI.CombineTo(N, InsV);
12945 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12946 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12947 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
12948 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
12949 return DCI.CombineTo(N, InsV);
12955 /// PerformShuffleCombine - Performs several different shuffle combines.
12956 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12957 TargetLowering::DAGCombinerInfo &DCI,
12958 const X86Subtarget *Subtarget) {
12959 DebugLoc dl = N->getDebugLoc();
12960 EVT VT = N->getValueType(0);
12962 // Don't create instructions with illegal types after legalize types has run.
12963 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12964 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12967 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12968 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12969 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12970 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12972 // Only handle 128 wide vector from here on.
12973 if (VT.getSizeInBits() != 128)
12976 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12977 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12978 // consecutive, non-overlapping, and in the right order.
12979 SmallVector<SDValue, 16> Elts;
12980 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12981 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12983 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12987 /// PerformTruncateCombine - Converts truncate operation to
12988 /// a sequence of vector shuffle operations.
12989 /// It is possible when we truncate 256-bit vector to 128-bit vector
12991 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12992 DAGCombinerInfo &DCI) const {
12993 if (!DCI.isBeforeLegalizeOps())
12996 if (!Subtarget->hasAVX()) return SDValue();
12998 EVT VT = N->getValueType(0);
12999 SDValue Op = N->getOperand(0);
13000 EVT OpVT = Op.getValueType();
13001 DebugLoc dl = N->getDebugLoc();
13003 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13005 if (Subtarget->hasAVX2()) {
13006 // AVX2: v4i64 -> v4i32
13009 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13011 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13012 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13015 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13016 DAG.getIntPtrConstant(0));
13019 // AVX: v4i64 -> v4i32
13020 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13021 DAG.getIntPtrConstant(0));
13023 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13024 DAG.getIntPtrConstant(2));
13026 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13027 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13030 static const int ShufMask1[] = {0, 2, 0, 0};
13032 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13033 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13036 static const int ShufMask2[] = {0, 1, 4, 5};
13038 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13041 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13043 if (Subtarget->hasAVX2()) {
13044 // AVX2: v8i32 -> v8i16
13046 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13049 SmallVector<SDValue,32> pshufbMask;
13050 for (unsigned i = 0; i < 2; ++i) {
13051 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13052 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13053 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13054 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13055 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13056 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13057 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13058 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13059 for (unsigned j = 0; j < 8; ++j)
13060 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13062 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13063 &pshufbMask[0], 32);
13064 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13066 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13068 static const int ShufMask[] = {0, 2, -1, -1};
13069 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13072 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13073 DAG.getIntPtrConstant(0));
13075 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13078 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13079 DAG.getIntPtrConstant(0));
13081 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13082 DAG.getIntPtrConstant(4));
13084 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13085 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13088 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13089 -1, -1, -1, -1, -1, -1, -1, -1};
13091 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13093 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13096 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13097 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13100 static const int ShufMask2[] = {0, 1, 4, 5};
13102 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13103 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13109 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13110 /// specific shuffle of a load can be folded into a single element load.
13111 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13112 /// shuffles have been customed lowered so we need to handle those here.
13113 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13114 TargetLowering::DAGCombinerInfo &DCI) {
13115 if (DCI.isBeforeLegalizeOps())
13118 SDValue InVec = N->getOperand(0);
13119 SDValue EltNo = N->getOperand(1);
13121 if (!isa<ConstantSDNode>(EltNo))
13124 EVT VT = InVec.getValueType();
13126 bool HasShuffleIntoBitcast = false;
13127 if (InVec.getOpcode() == ISD::BITCAST) {
13128 // Don't duplicate a load with other uses.
13129 if (!InVec.hasOneUse())
13131 EVT BCVT = InVec.getOperand(0).getValueType();
13132 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13134 InVec = InVec.getOperand(0);
13135 HasShuffleIntoBitcast = true;
13138 if (!isTargetShuffle(InVec.getOpcode()))
13141 // Don't duplicate a load with other uses.
13142 if (!InVec.hasOneUse())
13145 SmallVector<int, 16> ShuffleMask;
13147 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13150 // Select the input vector, guarding against out of range extract vector.
13151 unsigned NumElems = VT.getVectorNumElements();
13152 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13153 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13154 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13155 : InVec.getOperand(1);
13157 // If inputs to shuffle are the same for both ops, then allow 2 uses
13158 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13160 if (LdNode.getOpcode() == ISD::BITCAST) {
13161 // Don't duplicate a load with other uses.
13162 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13165 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13166 LdNode = LdNode.getOperand(0);
13169 if (!ISD::isNormalLoad(LdNode.getNode()))
13172 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13174 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13177 if (HasShuffleIntoBitcast) {
13178 // If there's a bitcast before the shuffle, check if the load type and
13179 // alignment is valid.
13180 unsigned Align = LN0->getAlignment();
13181 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13182 unsigned NewAlign = TLI.getTargetData()->
13183 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13185 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13189 // All checks match so transform back to vector_shuffle so that DAG combiner
13190 // can finish the job
13191 DebugLoc dl = N->getDebugLoc();
13193 // Create shuffle node taking into account the case that its a unary shuffle
13194 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13195 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13196 InVec.getOperand(0), Shuffle,
13198 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13199 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13203 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13204 /// generation and convert it from being a bunch of shuffles and extracts
13205 /// to a simple store and scalar loads to extract the elements.
13206 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13207 TargetLowering::DAGCombinerInfo &DCI) {
13208 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13209 if (NewOp.getNode())
13212 SDValue InputVector = N->getOperand(0);
13214 // Only operate on vectors of 4 elements, where the alternative shuffling
13215 // gets to be more expensive.
13216 if (InputVector.getValueType() != MVT::v4i32)
13219 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13220 // single use which is a sign-extend or zero-extend, and all elements are
13222 SmallVector<SDNode *, 4> Uses;
13223 unsigned ExtractedElements = 0;
13224 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13225 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13226 if (UI.getUse().getResNo() != InputVector.getResNo())
13229 SDNode *Extract = *UI;
13230 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13233 if (Extract->getValueType(0) != MVT::i32)
13235 if (!Extract->hasOneUse())
13237 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13238 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13240 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13243 // Record which element was extracted.
13244 ExtractedElements |=
13245 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13247 Uses.push_back(Extract);
13250 // If not all the elements were used, this may not be worthwhile.
13251 if (ExtractedElements != 15)
13254 // Ok, we've now decided to do the transformation.
13255 DebugLoc dl = InputVector.getDebugLoc();
13257 // Store the value to a temporary stack slot.
13258 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13259 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13260 MachinePointerInfo(), false, false, 0);
13262 // Replace each use (extract) with a load of the appropriate element.
13263 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13264 UE = Uses.end(); UI != UE; ++UI) {
13265 SDNode *Extract = *UI;
13267 // cOMpute the element's address.
13268 SDValue Idx = Extract->getOperand(1);
13270 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13271 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13272 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13273 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13275 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13276 StackPtr, OffsetVal);
13278 // Load the scalar.
13279 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13280 ScalarAddr, MachinePointerInfo(),
13281 false, false, false, 0);
13283 // Replace the exact with the load.
13284 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13287 // The replacement was made in place; don't return anything.
13291 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13293 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13294 TargetLowering::DAGCombinerInfo &DCI,
13295 const X86Subtarget *Subtarget) {
13298 DebugLoc DL = N->getDebugLoc();
13299 SDValue Cond = N->getOperand(0);
13300 // Get the LHS/RHS of the select.
13301 SDValue LHS = N->getOperand(1);
13302 SDValue RHS = N->getOperand(2);
13303 EVT VT = LHS.getValueType();
13305 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13306 // instructions match the semantics of the common C idiom x<y?x:y but not
13307 // x<=y?x:y, because of how they handle negative zero (which can be
13308 // ignored in unsafe-math mode).
13309 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13310 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13311 (Subtarget->hasSSE2() ||
13312 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13313 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13315 unsigned Opcode = 0;
13316 // Check for x CC y ? x : y.
13317 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13318 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13322 // Converting this to a min would handle NaNs incorrectly, and swapping
13323 // the operands would cause it to handle comparisons between positive
13324 // and negative zero incorrectly.
13325 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13326 if (!DAG.getTarget().Options.UnsafeFPMath &&
13327 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13329 std::swap(LHS, RHS);
13331 Opcode = X86ISD::FMIN;
13334 // Converting this to a min would handle comparisons between positive
13335 // and negative zero incorrectly.
13336 if (!DAG.getTarget().Options.UnsafeFPMath &&
13337 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13339 Opcode = X86ISD::FMIN;
13342 // Converting this to a min would handle both negative zeros and NaNs
13343 // incorrectly, but we can swap the operands to fix both.
13344 std::swap(LHS, RHS);
13348 Opcode = X86ISD::FMIN;
13352 // Converting this to a max would handle comparisons between positive
13353 // and negative zero incorrectly.
13354 if (!DAG.getTarget().Options.UnsafeFPMath &&
13355 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13357 Opcode = X86ISD::FMAX;
13360 // Converting this to a max would handle NaNs incorrectly, and swapping
13361 // the operands would cause it to handle comparisons between positive
13362 // and negative zero incorrectly.
13363 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13364 if (!DAG.getTarget().Options.UnsafeFPMath &&
13365 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13367 std::swap(LHS, RHS);
13369 Opcode = X86ISD::FMAX;
13372 // Converting this to a max would handle both negative zeros and NaNs
13373 // incorrectly, but we can swap the operands to fix both.
13374 std::swap(LHS, RHS);
13378 Opcode = X86ISD::FMAX;
13381 // Check for x CC y ? y : x -- a min/max with reversed arms.
13382 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13383 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13387 // Converting this to a min would handle comparisons between positive
13388 // and negative zero incorrectly, and swapping the operands would
13389 // cause it to handle NaNs incorrectly.
13390 if (!DAG.getTarget().Options.UnsafeFPMath &&
13391 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13392 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13394 std::swap(LHS, RHS);
13396 Opcode = X86ISD::FMIN;
13399 // Converting this to a min would handle NaNs incorrectly.
13400 if (!DAG.getTarget().Options.UnsafeFPMath &&
13401 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13403 Opcode = X86ISD::FMIN;
13406 // Converting this to a min would handle both negative zeros and NaNs
13407 // incorrectly, but we can swap the operands to fix both.
13408 std::swap(LHS, RHS);
13412 Opcode = X86ISD::FMIN;
13416 // Converting this to a max would handle NaNs incorrectly.
13417 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13419 Opcode = X86ISD::FMAX;
13422 // Converting this to a max would handle comparisons between positive
13423 // and negative zero incorrectly, and swapping the operands would
13424 // cause it to handle NaNs incorrectly.
13425 if (!DAG.getTarget().Options.UnsafeFPMath &&
13426 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13427 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13429 std::swap(LHS, RHS);
13431 Opcode = X86ISD::FMAX;
13434 // Converting this to a max would handle both negative zeros and NaNs
13435 // incorrectly, but we can swap the operands to fix both.
13436 std::swap(LHS, RHS);
13440 Opcode = X86ISD::FMAX;
13446 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13449 // If this is a select between two integer constants, try to do some
13451 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13452 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13453 // Don't do this for crazy integer types.
13454 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13455 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13456 // so that TrueC (the true value) is larger than FalseC.
13457 bool NeedsCondInvert = false;
13459 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13460 // Efficiently invertible.
13461 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13462 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13463 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13464 NeedsCondInvert = true;
13465 std::swap(TrueC, FalseC);
13468 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13469 if (FalseC->getAPIntValue() == 0 &&
13470 TrueC->getAPIntValue().isPowerOf2()) {
13471 if (NeedsCondInvert) // Invert the condition if needed.
13472 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13473 DAG.getConstant(1, Cond.getValueType()));
13475 // Zero extend the condition if needed.
13476 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13478 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13479 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13480 DAG.getConstant(ShAmt, MVT::i8));
13483 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13484 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13485 if (NeedsCondInvert) // Invert the condition if needed.
13486 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13487 DAG.getConstant(1, Cond.getValueType()));
13489 // Zero extend the condition if needed.
13490 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13491 FalseC->getValueType(0), Cond);
13492 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13493 SDValue(FalseC, 0));
13496 // Optimize cases that will turn into an LEA instruction. This requires
13497 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13498 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13499 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13500 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13502 bool isFastMultiplier = false;
13504 switch ((unsigned char)Diff) {
13506 case 1: // result = add base, cond
13507 case 2: // result = lea base( , cond*2)
13508 case 3: // result = lea base(cond, cond*2)
13509 case 4: // result = lea base( , cond*4)
13510 case 5: // result = lea base(cond, cond*4)
13511 case 8: // result = lea base( , cond*8)
13512 case 9: // result = lea base(cond, cond*8)
13513 isFastMultiplier = true;
13518 if (isFastMultiplier) {
13519 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13520 if (NeedsCondInvert) // Invert the condition if needed.
13521 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13522 DAG.getConstant(1, Cond.getValueType()));
13524 // Zero extend the condition if needed.
13525 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13527 // Scale the condition by the difference.
13529 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13530 DAG.getConstant(Diff, Cond.getValueType()));
13532 // Add the base if non-zero.
13533 if (FalseC->getAPIntValue() != 0)
13534 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13535 SDValue(FalseC, 0));
13542 // Canonicalize max and min:
13543 // (x > y) ? x : y -> (x >= y) ? x : y
13544 // (x < y) ? x : y -> (x <= y) ? x : y
13545 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13546 // the need for an extra compare
13547 // against zero. e.g.
13548 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13550 // testl %edi, %edi
13552 // cmovgl %edi, %eax
13556 // cmovsl %eax, %edi
13557 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13558 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13559 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13560 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13565 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13566 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13567 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13568 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13573 // If we know that this node is legal then we know that it is going to be
13574 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13575 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13576 // to simplify previous instructions.
13577 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13578 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13579 !DCI.isBeforeLegalize() &&
13580 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13581 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13582 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13583 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13585 APInt KnownZero, KnownOne;
13586 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13587 DCI.isBeforeLegalizeOps());
13588 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13589 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13590 DCI.CommitTargetLoweringOpt(TLO);
13596 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13597 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13598 TargetLowering::DAGCombinerInfo &DCI) {
13599 DebugLoc DL = N->getDebugLoc();
13601 // If the flag operand isn't dead, don't touch this CMOV.
13602 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13605 SDValue FalseOp = N->getOperand(0);
13606 SDValue TrueOp = N->getOperand(1);
13607 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13608 SDValue Cond = N->getOperand(3);
13609 if (CC == X86::COND_E || CC == X86::COND_NE) {
13610 switch (Cond.getOpcode()) {
13614 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13615 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13616 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13620 // If this is a select between two integer constants, try to do some
13621 // optimizations. Note that the operands are ordered the opposite of SELECT
13623 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13624 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13625 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13626 // larger than FalseC (the false value).
13627 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13628 CC = X86::GetOppositeBranchCondition(CC);
13629 std::swap(TrueC, FalseC);
13632 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13633 // This is efficient for any integer data type (including i8/i16) and
13635 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13636 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13637 DAG.getConstant(CC, MVT::i8), Cond);
13639 // Zero extend the condition if needed.
13640 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13642 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13643 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13644 DAG.getConstant(ShAmt, MVT::i8));
13645 if (N->getNumValues() == 2) // Dead flag value?
13646 return DCI.CombineTo(N, Cond, SDValue());
13650 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13651 // for any integer data type, including i8/i16.
13652 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13653 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13654 DAG.getConstant(CC, MVT::i8), Cond);
13656 // Zero extend the condition if needed.
13657 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13658 FalseC->getValueType(0), Cond);
13659 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13660 SDValue(FalseC, 0));
13662 if (N->getNumValues() == 2) // Dead flag value?
13663 return DCI.CombineTo(N, Cond, SDValue());
13667 // Optimize cases that will turn into an LEA instruction. This requires
13668 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13669 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13670 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13671 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13673 bool isFastMultiplier = false;
13675 switch ((unsigned char)Diff) {
13677 case 1: // result = add base, cond
13678 case 2: // result = lea base( , cond*2)
13679 case 3: // result = lea base(cond, cond*2)
13680 case 4: // result = lea base( , cond*4)
13681 case 5: // result = lea base(cond, cond*4)
13682 case 8: // result = lea base( , cond*8)
13683 case 9: // result = lea base(cond, cond*8)
13684 isFastMultiplier = true;
13689 if (isFastMultiplier) {
13690 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13691 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13692 DAG.getConstant(CC, MVT::i8), Cond);
13693 // Zero extend the condition if needed.
13694 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13696 // Scale the condition by the difference.
13698 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13699 DAG.getConstant(Diff, Cond.getValueType()));
13701 // Add the base if non-zero.
13702 if (FalseC->getAPIntValue() != 0)
13703 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13704 SDValue(FalseC, 0));
13705 if (N->getNumValues() == 2) // Dead flag value?
13706 return DCI.CombineTo(N, Cond, SDValue());
13716 /// PerformMulCombine - Optimize a single multiply with constant into two
13717 /// in order to implement it with two cheaper instructions, e.g.
13718 /// LEA + SHL, LEA + LEA.
13719 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13720 TargetLowering::DAGCombinerInfo &DCI) {
13721 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13724 EVT VT = N->getValueType(0);
13725 if (VT != MVT::i64)
13728 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13731 uint64_t MulAmt = C->getZExtValue();
13732 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13735 uint64_t MulAmt1 = 0;
13736 uint64_t MulAmt2 = 0;
13737 if ((MulAmt % 9) == 0) {
13739 MulAmt2 = MulAmt / 9;
13740 } else if ((MulAmt % 5) == 0) {
13742 MulAmt2 = MulAmt / 5;
13743 } else if ((MulAmt % 3) == 0) {
13745 MulAmt2 = MulAmt / 3;
13748 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13749 DebugLoc DL = N->getDebugLoc();
13751 if (isPowerOf2_64(MulAmt2) &&
13752 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13753 // If second multiplifer is pow2, issue it first. We want the multiply by
13754 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13756 std::swap(MulAmt1, MulAmt2);
13759 if (isPowerOf2_64(MulAmt1))
13760 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13761 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13763 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13764 DAG.getConstant(MulAmt1, VT));
13766 if (isPowerOf2_64(MulAmt2))
13767 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13768 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13770 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13771 DAG.getConstant(MulAmt2, VT));
13773 // Do not add new nodes to DAG combiner worklist.
13774 DCI.CombineTo(N, NewMul, false);
13779 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13780 SDValue N0 = N->getOperand(0);
13781 SDValue N1 = N->getOperand(1);
13782 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13783 EVT VT = N0.getValueType();
13785 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13786 // since the result of setcc_c is all zero's or all ones.
13787 if (VT.isInteger() && !VT.isVector() &&
13788 N1C && N0.getOpcode() == ISD::AND &&
13789 N0.getOperand(1).getOpcode() == ISD::Constant) {
13790 SDValue N00 = N0.getOperand(0);
13791 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13792 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13793 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13794 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13795 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13796 APInt ShAmt = N1C->getAPIntValue();
13797 Mask = Mask.shl(ShAmt);
13799 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13800 N00, DAG.getConstant(Mask, VT));
13805 // Hardware support for vector shifts is sparse which makes us scalarize the
13806 // vector operations in many cases. Also, on sandybridge ADD is faster than
13808 // (shl V, 1) -> add V,V
13809 if (isSplatVector(N1.getNode())) {
13810 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13811 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13812 // We shift all of the values by one. In many cases we do not have
13813 // hardware support for this operation. This is better expressed as an ADD
13815 if (N1C && (1 == N1C->getZExtValue())) {
13816 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13823 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13825 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13826 TargetLowering::DAGCombinerInfo &DCI,
13827 const X86Subtarget *Subtarget) {
13828 EVT VT = N->getValueType(0);
13829 if (N->getOpcode() == ISD::SHL) {
13830 SDValue V = PerformSHLCombine(N, DAG);
13831 if (V.getNode()) return V;
13834 // On X86 with SSE2 support, we can transform this to a vector shift if
13835 // all elements are shifted by the same amount. We can't do this in legalize
13836 // because the a constant vector is typically transformed to a constant pool
13837 // so we have no knowledge of the shift amount.
13838 if (!Subtarget->hasSSE2())
13841 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13842 (!Subtarget->hasAVX2() ||
13843 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13846 SDValue ShAmtOp = N->getOperand(1);
13847 EVT EltVT = VT.getVectorElementType();
13848 DebugLoc DL = N->getDebugLoc();
13849 SDValue BaseShAmt = SDValue();
13850 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13851 unsigned NumElts = VT.getVectorNumElements();
13853 for (; i != NumElts; ++i) {
13854 SDValue Arg = ShAmtOp.getOperand(i);
13855 if (Arg.getOpcode() == ISD::UNDEF) continue;
13859 // Handle the case where the build_vector is all undef
13860 // FIXME: Should DAG allow this?
13864 for (; i != NumElts; ++i) {
13865 SDValue Arg = ShAmtOp.getOperand(i);
13866 if (Arg.getOpcode() == ISD::UNDEF) continue;
13867 if (Arg != BaseShAmt) {
13871 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13872 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13873 SDValue InVec = ShAmtOp.getOperand(0);
13874 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13875 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13877 for (; i != NumElts; ++i) {
13878 SDValue Arg = InVec.getOperand(i);
13879 if (Arg.getOpcode() == ISD::UNDEF) continue;
13883 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13885 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13886 if (C->getZExtValue() == SplatIdx)
13887 BaseShAmt = InVec.getOperand(1);
13890 if (BaseShAmt.getNode() == 0) {
13891 // Don't create instructions with illegal types after legalize
13893 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13894 !DCI.isBeforeLegalize())
13897 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13898 DAG.getIntPtrConstant(0));
13903 // The shift amount is an i32.
13904 if (EltVT.bitsGT(MVT::i32))
13905 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13906 else if (EltVT.bitsLT(MVT::i32))
13907 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13909 // The shift amount is identical so we can do a vector shift.
13910 SDValue ValOp = N->getOperand(0);
13911 switch (N->getOpcode()) {
13913 llvm_unreachable("Unknown shift opcode!");
13915 switch (VT.getSimpleVT().SimpleTy) {
13916 default: return SDValue();
13923 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13926 switch (VT.getSimpleVT().SimpleTy) {
13927 default: return SDValue();
13932 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13935 switch (VT.getSimpleVT().SimpleTy) {
13936 default: return SDValue();
13943 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13949 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13950 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13951 // and friends. Likewise for OR -> CMPNEQSS.
13952 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13953 TargetLowering::DAGCombinerInfo &DCI,
13954 const X86Subtarget *Subtarget) {
13957 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13958 // we're requiring SSE2 for both.
13959 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13960 SDValue N0 = N->getOperand(0);
13961 SDValue N1 = N->getOperand(1);
13962 SDValue CMP0 = N0->getOperand(1);
13963 SDValue CMP1 = N1->getOperand(1);
13964 DebugLoc DL = N->getDebugLoc();
13966 // The SETCCs should both refer to the same CMP.
13967 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13970 SDValue CMP00 = CMP0->getOperand(0);
13971 SDValue CMP01 = CMP0->getOperand(1);
13972 EVT VT = CMP00.getValueType();
13974 if (VT == MVT::f32 || VT == MVT::f64) {
13975 bool ExpectingFlags = false;
13976 // Check for any users that want flags:
13977 for (SDNode::use_iterator UI = N->use_begin(),
13979 !ExpectingFlags && UI != UE; ++UI)
13980 switch (UI->getOpcode()) {
13985 ExpectingFlags = true;
13987 case ISD::CopyToReg:
13988 case ISD::SIGN_EXTEND:
13989 case ISD::ZERO_EXTEND:
13990 case ISD::ANY_EXTEND:
13994 if (!ExpectingFlags) {
13995 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13996 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13998 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13999 X86::CondCode tmp = cc0;
14004 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14005 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14006 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14007 X86ISD::NodeType NTOperator = is64BitFP ?
14008 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14009 // FIXME: need symbolic constants for these magic numbers.
14010 // See X86ATTInstPrinter.cpp:printSSECC().
14011 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14012 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14013 DAG.getConstant(x86cc, MVT::i8));
14014 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14016 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14017 DAG.getConstant(1, MVT::i32));
14018 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14019 return OneBitOfTruth;
14027 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14028 /// so it can be folded inside ANDNP.
14029 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14030 EVT VT = N->getValueType(0);
14032 // Match direct AllOnes for 128 and 256-bit vectors
14033 if (ISD::isBuildVectorAllOnes(N))
14036 // Look through a bit convert.
14037 if (N->getOpcode() == ISD::BITCAST)
14038 N = N->getOperand(0).getNode();
14040 // Sometimes the operand may come from a insert_subvector building a 256-bit
14042 if (VT.getSizeInBits() == 256 &&
14043 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14044 SDValue V1 = N->getOperand(0);
14045 SDValue V2 = N->getOperand(1);
14047 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14048 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14049 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14050 ISD::isBuildVectorAllOnes(V2.getNode()))
14057 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14058 TargetLowering::DAGCombinerInfo &DCI,
14059 const X86Subtarget *Subtarget) {
14060 if (DCI.isBeforeLegalizeOps())
14063 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14067 EVT VT = N->getValueType(0);
14069 // Create ANDN, BLSI, and BLSR instructions
14070 // BLSI is X & (-X)
14071 // BLSR is X & (X-1)
14072 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14073 SDValue N0 = N->getOperand(0);
14074 SDValue N1 = N->getOperand(1);
14075 DebugLoc DL = N->getDebugLoc();
14077 // Check LHS for not
14078 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14079 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14080 // Check RHS for not
14081 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14082 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14084 // Check LHS for neg
14085 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14086 isZero(N0.getOperand(0)))
14087 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14089 // Check RHS for neg
14090 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14091 isZero(N1.getOperand(0)))
14092 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14094 // Check LHS for X-1
14095 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14096 isAllOnes(N0.getOperand(1)))
14097 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14099 // Check RHS for X-1
14100 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14101 isAllOnes(N1.getOperand(1)))
14102 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14107 // Want to form ANDNP nodes:
14108 // 1) In the hopes of then easily combining them with OR and AND nodes
14109 // to form PBLEND/PSIGN.
14110 // 2) To match ANDN packed intrinsics
14111 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14114 SDValue N0 = N->getOperand(0);
14115 SDValue N1 = N->getOperand(1);
14116 DebugLoc DL = N->getDebugLoc();
14118 // Check LHS for vnot
14119 if (N0.getOpcode() == ISD::XOR &&
14120 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14121 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14122 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14124 // Check RHS for vnot
14125 if (N1.getOpcode() == ISD::XOR &&
14126 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14127 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14128 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14133 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14134 TargetLowering::DAGCombinerInfo &DCI,
14135 const X86Subtarget *Subtarget) {
14136 if (DCI.isBeforeLegalizeOps())
14139 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14143 EVT VT = N->getValueType(0);
14145 SDValue N0 = N->getOperand(0);
14146 SDValue N1 = N->getOperand(1);
14148 // look for psign/blend
14149 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14150 if (!Subtarget->hasSSSE3() ||
14151 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14154 // Canonicalize pandn to RHS
14155 if (N0.getOpcode() == X86ISD::ANDNP)
14157 // or (and (m, y), (pandn m, x))
14158 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14159 SDValue Mask = N1.getOperand(0);
14160 SDValue X = N1.getOperand(1);
14162 if (N0.getOperand(0) == Mask)
14163 Y = N0.getOperand(1);
14164 if (N0.getOperand(1) == Mask)
14165 Y = N0.getOperand(0);
14167 // Check to see if the mask appeared in both the AND and ANDNP and
14171 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14172 // Look through mask bitcast.
14173 if (Mask.getOpcode() == ISD::BITCAST)
14174 Mask = Mask.getOperand(0);
14175 if (X.getOpcode() == ISD::BITCAST)
14176 X = X.getOperand(0);
14177 if (Y.getOpcode() == ISD::BITCAST)
14178 Y = Y.getOperand(0);
14180 EVT MaskVT = Mask.getValueType();
14182 // Validate that the Mask operand is a vector sra node.
14183 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14184 // there is no psrai.b
14185 if (Mask.getOpcode() != X86ISD::VSRAI)
14188 // Check that the SRA is all signbits.
14189 SDValue SraC = Mask.getOperand(1);
14190 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14191 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14192 if ((SraAmt + 1) != EltBits)
14195 DebugLoc DL = N->getDebugLoc();
14197 // Now we know we at least have a plendvb with the mask val. See if
14198 // we can form a psignb/w/d.
14199 // psign = x.type == y.type == mask.type && y = sub(0, x);
14200 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14201 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14202 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14203 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14204 "Unsupported VT for PSIGN");
14205 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14206 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14208 // PBLENDVB only available on SSE 4.1
14209 if (!Subtarget->hasSSE41())
14212 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14214 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14215 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14216 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14217 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14218 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14222 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14225 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14226 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14228 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14230 if (!N0.hasOneUse() || !N1.hasOneUse())
14233 SDValue ShAmt0 = N0.getOperand(1);
14234 if (ShAmt0.getValueType() != MVT::i8)
14236 SDValue ShAmt1 = N1.getOperand(1);
14237 if (ShAmt1.getValueType() != MVT::i8)
14239 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14240 ShAmt0 = ShAmt0.getOperand(0);
14241 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14242 ShAmt1 = ShAmt1.getOperand(0);
14244 DebugLoc DL = N->getDebugLoc();
14245 unsigned Opc = X86ISD::SHLD;
14246 SDValue Op0 = N0.getOperand(0);
14247 SDValue Op1 = N1.getOperand(0);
14248 if (ShAmt0.getOpcode() == ISD::SUB) {
14249 Opc = X86ISD::SHRD;
14250 std::swap(Op0, Op1);
14251 std::swap(ShAmt0, ShAmt1);
14254 unsigned Bits = VT.getSizeInBits();
14255 if (ShAmt1.getOpcode() == ISD::SUB) {
14256 SDValue Sum = ShAmt1.getOperand(0);
14257 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14258 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14259 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14260 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14261 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14262 return DAG.getNode(Opc, DL, VT,
14264 DAG.getNode(ISD::TRUNCATE, DL,
14267 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14268 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14270 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14271 return DAG.getNode(Opc, DL, VT,
14272 N0.getOperand(0), N1.getOperand(0),
14273 DAG.getNode(ISD::TRUNCATE, DL,
14280 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14281 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14282 TargetLowering::DAGCombinerInfo &DCI,
14283 const X86Subtarget *Subtarget) {
14284 if (DCI.isBeforeLegalizeOps())
14287 EVT VT = N->getValueType(0);
14289 if (VT != MVT::i32 && VT != MVT::i64)
14292 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14294 // Create BLSMSK instructions by finding X ^ (X-1)
14295 SDValue N0 = N->getOperand(0);
14296 SDValue N1 = N->getOperand(1);
14297 DebugLoc DL = N->getDebugLoc();
14299 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14300 isAllOnes(N0.getOperand(1)))
14301 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14303 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14304 isAllOnes(N1.getOperand(1)))
14305 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14310 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14311 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14312 const X86Subtarget *Subtarget) {
14313 LoadSDNode *Ld = cast<LoadSDNode>(N);
14314 EVT RegVT = Ld->getValueType(0);
14315 EVT MemVT = Ld->getMemoryVT();
14316 DebugLoc dl = Ld->getDebugLoc();
14317 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14319 ISD::LoadExtType Ext = Ld->getExtensionType();
14321 // If this is a vector EXT Load then attempt to optimize it using a
14322 // shuffle. We need SSE4 for the shuffles.
14323 // TODO: It is possible to support ZExt by zeroing the undef values
14324 // during the shuffle phase or after the shuffle.
14325 if (RegVT.isVector() && RegVT.isInteger() &&
14326 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14327 assert(MemVT != RegVT && "Cannot extend to the same type");
14328 assert(MemVT.isVector() && "Must load a vector from memory");
14330 unsigned NumElems = RegVT.getVectorNumElements();
14331 unsigned RegSz = RegVT.getSizeInBits();
14332 unsigned MemSz = MemVT.getSizeInBits();
14333 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14334 // All sizes must be a power of two
14335 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14337 // Attempt to load the original value using a single load op.
14338 // Find a scalar type which is equal to the loaded word size.
14339 MVT SclrLoadTy = MVT::i8;
14340 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14341 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14342 MVT Tp = (MVT::SimpleValueType)tp;
14343 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14349 // Proceed if a load word is found.
14350 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14352 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14353 RegSz/SclrLoadTy.getSizeInBits());
14355 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14356 RegSz/MemVT.getScalarType().getSizeInBits());
14357 // Can't shuffle using an illegal type.
14358 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14360 // Perform a single load.
14361 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14363 Ld->getPointerInfo(), Ld->isVolatile(),
14364 Ld->isNonTemporal(), Ld->isInvariant(),
14365 Ld->getAlignment());
14367 // Insert the word loaded into a vector.
14368 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14369 LoadUnitVecVT, ScalarLoad);
14371 // Bitcast the loaded value to a vector of the original element type, in
14372 // the size of the target vector type.
14373 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14375 unsigned SizeRatio = RegSz/MemSz;
14377 // Redistribute the loaded elements into the different locations.
14378 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14379 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14381 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14382 DAG.getUNDEF(WideVecVT),
14385 // Bitcast to the requested type.
14386 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14387 // Replace the original load with the new sequence
14388 // and return the new chain.
14389 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14390 return SDValue(ScalarLoad.getNode(), 1);
14396 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14397 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14398 const X86Subtarget *Subtarget) {
14399 StoreSDNode *St = cast<StoreSDNode>(N);
14400 EVT VT = St->getValue().getValueType();
14401 EVT StVT = St->getMemoryVT();
14402 DebugLoc dl = St->getDebugLoc();
14403 SDValue StoredVal = St->getOperand(1);
14404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14406 // If we are saving a concatenation of two XMM registers, perform two stores.
14407 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14408 // 128-bit ones. If in the future the cost becomes only one memory access the
14409 // first version would be better.
14410 if (VT.getSizeInBits() == 256 &&
14411 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14412 StoredVal.getNumOperands() == 2) {
14414 SDValue Value0 = StoredVal.getOperand(0);
14415 SDValue Value1 = StoredVal.getOperand(1);
14417 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14418 SDValue Ptr0 = St->getBasePtr();
14419 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14421 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14422 St->getPointerInfo(), St->isVolatile(),
14423 St->isNonTemporal(), St->getAlignment());
14424 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14425 St->getPointerInfo(), St->isVolatile(),
14426 St->isNonTemporal(), St->getAlignment());
14427 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14430 // Optimize trunc store (of multiple scalars) to shuffle and store.
14431 // First, pack all of the elements in one place. Next, store to memory
14432 // in fewer chunks.
14433 if (St->isTruncatingStore() && VT.isVector()) {
14434 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14435 unsigned NumElems = VT.getVectorNumElements();
14436 assert(StVT != VT && "Cannot truncate to the same type");
14437 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14438 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14440 // From, To sizes and ElemCount must be pow of two
14441 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14442 // We are going to use the original vector elt for storing.
14443 // Accumulated smaller vector elements must be a multiple of the store size.
14444 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14446 unsigned SizeRatio = FromSz / ToSz;
14448 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14450 // Create a type on which we perform the shuffle
14451 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14452 StVT.getScalarType(), NumElems*SizeRatio);
14454 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14456 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14457 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14458 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14460 // Can't shuffle using an illegal type
14461 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14463 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14464 DAG.getUNDEF(WideVecVT),
14466 // At this point all of the data is stored at the bottom of the
14467 // register. We now need to save it to mem.
14469 // Find the largest store unit
14470 MVT StoreType = MVT::i8;
14471 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14472 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14473 MVT Tp = (MVT::SimpleValueType)tp;
14474 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14478 // Bitcast the original vector into a vector of store-size units
14479 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14480 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14481 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14482 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14483 SmallVector<SDValue, 8> Chains;
14484 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14485 TLI.getPointerTy());
14486 SDValue Ptr = St->getBasePtr();
14488 // Perform one or more big stores into memory.
14489 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14490 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14491 StoreType, ShuffWide,
14492 DAG.getIntPtrConstant(i));
14493 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14494 St->getPointerInfo(), St->isVolatile(),
14495 St->isNonTemporal(), St->getAlignment());
14496 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14497 Chains.push_back(Ch);
14500 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14505 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14506 // the FP state in cases where an emms may be missing.
14507 // A preferable solution to the general problem is to figure out the right
14508 // places to insert EMMS. This qualifies as a quick hack.
14510 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14511 if (VT.getSizeInBits() != 64)
14514 const Function *F = DAG.getMachineFunction().getFunction();
14515 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14516 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14517 && Subtarget->hasSSE2();
14518 if ((VT.isVector() ||
14519 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14520 isa<LoadSDNode>(St->getValue()) &&
14521 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14522 St->getChain().hasOneUse() && !St->isVolatile()) {
14523 SDNode* LdVal = St->getValue().getNode();
14524 LoadSDNode *Ld = 0;
14525 int TokenFactorIndex = -1;
14526 SmallVector<SDValue, 8> Ops;
14527 SDNode* ChainVal = St->getChain().getNode();
14528 // Must be a store of a load. We currently handle two cases: the load
14529 // is a direct child, and it's under an intervening TokenFactor. It is
14530 // possible to dig deeper under nested TokenFactors.
14531 if (ChainVal == LdVal)
14532 Ld = cast<LoadSDNode>(St->getChain());
14533 else if (St->getValue().hasOneUse() &&
14534 ChainVal->getOpcode() == ISD::TokenFactor) {
14535 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14536 if (ChainVal->getOperand(i).getNode() == LdVal) {
14537 TokenFactorIndex = i;
14538 Ld = cast<LoadSDNode>(St->getValue());
14540 Ops.push_back(ChainVal->getOperand(i));
14544 if (!Ld || !ISD::isNormalLoad(Ld))
14547 // If this is not the MMX case, i.e. we are just turning i64 load/store
14548 // into f64 load/store, avoid the transformation if there are multiple
14549 // uses of the loaded value.
14550 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14553 DebugLoc LdDL = Ld->getDebugLoc();
14554 DebugLoc StDL = N->getDebugLoc();
14555 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14556 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14558 if (Subtarget->is64Bit() || F64IsLegal) {
14559 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14560 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14561 Ld->getPointerInfo(), Ld->isVolatile(),
14562 Ld->isNonTemporal(), Ld->isInvariant(),
14563 Ld->getAlignment());
14564 SDValue NewChain = NewLd.getValue(1);
14565 if (TokenFactorIndex != -1) {
14566 Ops.push_back(NewChain);
14567 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14570 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14571 St->getPointerInfo(),
14572 St->isVolatile(), St->isNonTemporal(),
14573 St->getAlignment());
14576 // Otherwise, lower to two pairs of 32-bit loads / stores.
14577 SDValue LoAddr = Ld->getBasePtr();
14578 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14579 DAG.getConstant(4, MVT::i32));
14581 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14582 Ld->getPointerInfo(),
14583 Ld->isVolatile(), Ld->isNonTemporal(),
14584 Ld->isInvariant(), Ld->getAlignment());
14585 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14586 Ld->getPointerInfo().getWithOffset(4),
14587 Ld->isVolatile(), Ld->isNonTemporal(),
14589 MinAlign(Ld->getAlignment(), 4));
14591 SDValue NewChain = LoLd.getValue(1);
14592 if (TokenFactorIndex != -1) {
14593 Ops.push_back(LoLd);
14594 Ops.push_back(HiLd);
14595 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14599 LoAddr = St->getBasePtr();
14600 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14601 DAG.getConstant(4, MVT::i32));
14603 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14604 St->getPointerInfo(),
14605 St->isVolatile(), St->isNonTemporal(),
14606 St->getAlignment());
14607 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14608 St->getPointerInfo().getWithOffset(4),
14610 St->isNonTemporal(),
14611 MinAlign(St->getAlignment(), 4));
14612 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14617 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14618 /// and return the operands for the horizontal operation in LHS and RHS. A
14619 /// horizontal operation performs the binary operation on successive elements
14620 /// of its first operand, then on successive elements of its second operand,
14621 /// returning the resulting values in a vector. For example, if
14622 /// A = < float a0, float a1, float a2, float a3 >
14624 /// B = < float b0, float b1, float b2, float b3 >
14625 /// then the result of doing a horizontal operation on A and B is
14626 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14627 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14628 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14629 /// set to A, RHS to B, and the routine returns 'true'.
14630 /// Note that the binary operation should have the property that if one of the
14631 /// operands is UNDEF then the result is UNDEF.
14632 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14633 // Look for the following pattern: if
14634 // A = < float a0, float a1, float a2, float a3 >
14635 // B = < float b0, float b1, float b2, float b3 >
14637 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14638 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14639 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14640 // which is A horizontal-op B.
14642 // At least one of the operands should be a vector shuffle.
14643 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14644 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14647 EVT VT = LHS.getValueType();
14649 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14650 "Unsupported vector type for horizontal add/sub");
14652 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14653 // operate independently on 128-bit lanes.
14654 unsigned NumElts = VT.getVectorNumElements();
14655 unsigned NumLanes = VT.getSizeInBits()/128;
14656 unsigned NumLaneElts = NumElts / NumLanes;
14657 assert((NumLaneElts % 2 == 0) &&
14658 "Vector type should have an even number of elements in each lane");
14659 unsigned HalfLaneElts = NumLaneElts/2;
14661 // View LHS in the form
14662 // LHS = VECTOR_SHUFFLE A, B, LMask
14663 // If LHS is not a shuffle then pretend it is the shuffle
14664 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14665 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14668 SmallVector<int, 16> LMask(NumElts);
14669 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14670 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14671 A = LHS.getOperand(0);
14672 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14673 B = LHS.getOperand(1);
14674 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14675 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14677 if (LHS.getOpcode() != ISD::UNDEF)
14679 for (unsigned i = 0; i != NumElts; ++i)
14683 // Likewise, view RHS in the form
14684 // RHS = VECTOR_SHUFFLE C, D, RMask
14686 SmallVector<int, 16> RMask(NumElts);
14687 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14688 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14689 C = RHS.getOperand(0);
14690 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14691 D = RHS.getOperand(1);
14692 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14693 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14695 if (RHS.getOpcode() != ISD::UNDEF)
14697 for (unsigned i = 0; i != NumElts; ++i)
14701 // Check that the shuffles are both shuffling the same vectors.
14702 if (!(A == C && B == D) && !(A == D && B == C))
14705 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14706 if (!A.getNode() && !B.getNode())
14709 // If A and B occur in reverse order in RHS, then "swap" them (which means
14710 // rewriting the mask).
14712 CommuteVectorShuffleMask(RMask, NumElts);
14714 // At this point LHS and RHS are equivalent to
14715 // LHS = VECTOR_SHUFFLE A, B, LMask
14716 // RHS = VECTOR_SHUFFLE A, B, RMask
14717 // Check that the masks correspond to performing a horizontal operation.
14718 for (unsigned i = 0; i != NumElts; ++i) {
14719 int LIdx = LMask[i], RIdx = RMask[i];
14721 // Ignore any UNDEF components.
14722 if (LIdx < 0 || RIdx < 0 ||
14723 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14724 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14727 // Check that successive elements are being operated on. If not, this is
14728 // not a horizontal operation.
14729 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14730 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14731 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14732 if (!(LIdx == Index && RIdx == Index + 1) &&
14733 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14737 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14738 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14742 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14743 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14744 const X86Subtarget *Subtarget) {
14745 EVT VT = N->getValueType(0);
14746 SDValue LHS = N->getOperand(0);
14747 SDValue RHS = N->getOperand(1);
14749 // Try to synthesize horizontal adds from adds of shuffles.
14750 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14751 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14752 isHorizontalBinOp(LHS, RHS, true))
14753 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14757 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14758 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14759 const X86Subtarget *Subtarget) {
14760 EVT VT = N->getValueType(0);
14761 SDValue LHS = N->getOperand(0);
14762 SDValue RHS = N->getOperand(1);
14764 // Try to synthesize horizontal subs from subs of shuffles.
14765 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14766 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14767 isHorizontalBinOp(LHS, RHS, false))
14768 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14772 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14773 /// X86ISD::FXOR nodes.
14774 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14775 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14776 // F[X]OR(0.0, x) -> x
14777 // F[X]OR(x, 0.0) -> x
14778 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14779 if (C->getValueAPF().isPosZero())
14780 return N->getOperand(1);
14781 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14782 if (C->getValueAPF().isPosZero())
14783 return N->getOperand(0);
14787 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14788 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14789 // FAND(0.0, x) -> 0.0
14790 // FAND(x, 0.0) -> 0.0
14791 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14792 if (C->getValueAPF().isPosZero())
14793 return N->getOperand(0);
14794 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14795 if (C->getValueAPF().isPosZero())
14796 return N->getOperand(1);
14800 static SDValue PerformBTCombine(SDNode *N,
14802 TargetLowering::DAGCombinerInfo &DCI) {
14803 // BT ignores high bits in the bit index operand.
14804 SDValue Op1 = N->getOperand(1);
14805 if (Op1.hasOneUse()) {
14806 unsigned BitWidth = Op1.getValueSizeInBits();
14807 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14808 APInt KnownZero, KnownOne;
14809 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14810 !DCI.isBeforeLegalizeOps());
14811 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14812 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14813 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14814 DCI.CommitTargetLoweringOpt(TLO);
14819 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14820 SDValue Op = N->getOperand(0);
14821 if (Op.getOpcode() == ISD::BITCAST)
14822 Op = Op.getOperand(0);
14823 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14824 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14825 VT.getVectorElementType().getSizeInBits() ==
14826 OpVT.getVectorElementType().getSizeInBits()) {
14827 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14832 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14833 TargetLowering::DAGCombinerInfo &DCI,
14834 const X86Subtarget *Subtarget) {
14835 if (!DCI.isBeforeLegalizeOps())
14838 if (!Subtarget->hasAVX())
14841 EVT VT = N->getValueType(0);
14842 SDValue Op = N->getOperand(0);
14843 EVT OpVT = Op.getValueType();
14844 DebugLoc dl = N->getDebugLoc();
14846 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14847 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14849 if (Subtarget->hasAVX2()) {
14850 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14853 // Optimize vectors in AVX mode
14854 // Sign extend v8i16 to v8i32 and
14857 // Divide input vector into two parts
14858 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14859 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14860 // concat the vectors to original VT
14862 unsigned NumElems = OpVT.getVectorNumElements();
14863 SmallVector<int,8> ShufMask1(NumElems, -1);
14864 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14866 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14869 SmallVector<int,8> ShufMask2(NumElems, -1);
14870 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14872 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14875 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14876 VT.getVectorNumElements()/2);
14878 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14879 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14881 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14886 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14887 const X86Subtarget *Subtarget) {
14888 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14889 // (and (i32 x86isd::setcc_carry), 1)
14890 // This eliminates the zext. This transformation is necessary because
14891 // ISD::SETCC is always legalized to i8.
14892 DebugLoc dl = N->getDebugLoc();
14893 SDValue N0 = N->getOperand(0);
14894 EVT VT = N->getValueType(0);
14895 EVT OpVT = N0.getValueType();
14897 if (N0.getOpcode() == ISD::AND &&
14899 N0.getOperand(0).hasOneUse()) {
14900 SDValue N00 = N0.getOperand(0);
14901 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14903 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14904 if (!C || C->getZExtValue() != 1)
14906 return DAG.getNode(ISD::AND, dl, VT,
14907 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14908 N00.getOperand(0), N00.getOperand(1)),
14909 DAG.getConstant(1, VT));
14912 // Optimize vectors in AVX mode:
14915 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14916 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14917 // Concat upper and lower parts.
14920 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14921 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14922 // Concat upper and lower parts.
14924 if (Subtarget->hasAVX()) {
14926 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14927 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14929 if (Subtarget->hasAVX2())
14930 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
14932 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14933 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec,
14935 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec,
14938 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14939 VT.getVectorNumElements()/2);
14941 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14942 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14944 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14951 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14952 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14953 unsigned X86CC = N->getConstantOperandVal(0);
14954 SDValue EFLAG = N->getOperand(1);
14955 DebugLoc DL = N->getDebugLoc();
14957 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14958 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14960 if (X86CC == X86::COND_B)
14961 return DAG.getNode(ISD::AND, DL, MVT::i8,
14962 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14963 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14964 DAG.getConstant(1, MVT::i8));
14969 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14970 const X86TargetLowering *XTLI) {
14971 SDValue Op0 = N->getOperand(0);
14972 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14973 // a 32-bit target where SSE doesn't support i64->FP operations.
14974 if (Op0.getOpcode() == ISD::LOAD) {
14975 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14976 EVT VT = Ld->getValueType(0);
14977 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14978 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14979 !XTLI->getSubtarget()->is64Bit() &&
14980 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14981 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14982 Ld->getChain(), Op0, DAG);
14983 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14990 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14991 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14992 X86TargetLowering::DAGCombinerInfo &DCI) {
14993 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14994 // the result is either zero or one (depending on the input carry bit).
14995 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14996 if (X86::isZeroNode(N->getOperand(0)) &&
14997 X86::isZeroNode(N->getOperand(1)) &&
14998 // We don't have a good way to replace an EFLAGS use, so only do this when
15000 SDValue(N, 1).use_empty()) {
15001 DebugLoc DL = N->getDebugLoc();
15002 EVT VT = N->getValueType(0);
15003 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15004 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15005 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15006 DAG.getConstant(X86::COND_B,MVT::i8),
15008 DAG.getConstant(1, VT));
15009 return DCI.CombineTo(N, Res1, CarryOut);
15015 // fold (add Y, (sete X, 0)) -> adc 0, Y
15016 // (add Y, (setne X, 0)) -> sbb -1, Y
15017 // (sub (sete X, 0), Y) -> sbb 0, Y
15018 // (sub (setne X, 0), Y) -> adc -1, Y
15019 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15020 DebugLoc DL = N->getDebugLoc();
15022 // Look through ZExts.
15023 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15024 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15027 SDValue SetCC = Ext.getOperand(0);
15028 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15031 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15032 if (CC != X86::COND_E && CC != X86::COND_NE)
15035 SDValue Cmp = SetCC.getOperand(1);
15036 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15037 !X86::isZeroNode(Cmp.getOperand(1)) ||
15038 !Cmp.getOperand(0).getValueType().isInteger())
15041 SDValue CmpOp0 = Cmp.getOperand(0);
15042 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15043 DAG.getConstant(1, CmpOp0.getValueType()));
15045 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15046 if (CC == X86::COND_NE)
15047 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15048 DL, OtherVal.getValueType(), OtherVal,
15049 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15050 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15051 DL, OtherVal.getValueType(), OtherVal,
15052 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15055 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15056 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15057 const X86Subtarget *Subtarget) {
15058 EVT VT = N->getValueType(0);
15059 SDValue Op0 = N->getOperand(0);
15060 SDValue Op1 = N->getOperand(1);
15062 // Try to synthesize horizontal adds from adds of shuffles.
15063 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15064 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15065 isHorizontalBinOp(Op0, Op1, true))
15066 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15068 return OptimizeConditionalInDecrement(N, DAG);
15071 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15072 const X86Subtarget *Subtarget) {
15073 SDValue Op0 = N->getOperand(0);
15074 SDValue Op1 = N->getOperand(1);
15076 // X86 can't encode an immediate LHS of a sub. See if we can push the
15077 // negation into a preceding instruction.
15078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15079 // If the RHS of the sub is a XOR with one use and a constant, invert the
15080 // immediate. Then add one to the LHS of the sub so we can turn
15081 // X-Y -> X+~Y+1, saving one register.
15082 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15083 isa<ConstantSDNode>(Op1.getOperand(1))) {
15084 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15085 EVT VT = Op0.getValueType();
15086 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15088 DAG.getConstant(~XorC, VT));
15089 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15090 DAG.getConstant(C->getAPIntValue()+1, VT));
15094 // Try to synthesize horizontal adds from adds of shuffles.
15095 EVT VT = N->getValueType(0);
15096 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15097 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15098 isHorizontalBinOp(Op0, Op1, true))
15099 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15101 return OptimizeConditionalInDecrement(N, DAG);
15104 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15105 DAGCombinerInfo &DCI) const {
15106 SelectionDAG &DAG = DCI.DAG;
15107 switch (N->getOpcode()) {
15109 case ISD::EXTRACT_VECTOR_ELT:
15110 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15112 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15113 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15114 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15115 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15116 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15117 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15120 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15121 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15122 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15123 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15124 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15125 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15126 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15127 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15128 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15130 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15131 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15132 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15133 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15134 case ISD::ANY_EXTEND:
15135 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
15136 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15137 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15138 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15139 case X86ISD::SHUFP: // Handle all target specific shuffles
15140 case X86ISD::PALIGN:
15141 case X86ISD::UNPCKH:
15142 case X86ISD::UNPCKL:
15143 case X86ISD::MOVHLPS:
15144 case X86ISD::MOVLHPS:
15145 case X86ISD::PSHUFD:
15146 case X86ISD::PSHUFHW:
15147 case X86ISD::PSHUFLW:
15148 case X86ISD::MOVSS:
15149 case X86ISD::MOVSD:
15150 case X86ISD::VPERMILP:
15151 case X86ISD::VPERM2X128:
15152 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15158 /// isTypeDesirableForOp - Return true if the target has native support for
15159 /// the specified value type and it is 'desirable' to use the type for the
15160 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15161 /// instruction encodings are longer and some i16 instructions are slow.
15162 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15163 if (!isTypeLegal(VT))
15165 if (VT != MVT::i16)
15172 case ISD::SIGN_EXTEND:
15173 case ISD::ZERO_EXTEND:
15174 case ISD::ANY_EXTEND:
15187 /// IsDesirableToPromoteOp - This method query the target whether it is
15188 /// beneficial for dag combiner to promote the specified node. If true, it
15189 /// should return the desired promotion type by reference.
15190 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15191 EVT VT = Op.getValueType();
15192 if (VT != MVT::i16)
15195 bool Promote = false;
15196 bool Commute = false;
15197 switch (Op.getOpcode()) {
15200 LoadSDNode *LD = cast<LoadSDNode>(Op);
15201 // If the non-extending load has a single use and it's not live out, then it
15202 // might be folded.
15203 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15204 Op.hasOneUse()*/) {
15205 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15206 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15207 // The only case where we'd want to promote LOAD (rather then it being
15208 // promoted as an operand is when it's only use is liveout.
15209 if (UI->getOpcode() != ISD::CopyToReg)
15216 case ISD::SIGN_EXTEND:
15217 case ISD::ZERO_EXTEND:
15218 case ISD::ANY_EXTEND:
15223 SDValue N0 = Op.getOperand(0);
15224 // Look out for (store (shl (load), x)).
15225 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15238 SDValue N0 = Op.getOperand(0);
15239 SDValue N1 = Op.getOperand(1);
15240 if (!Commute && MayFoldLoad(N1))
15242 // Avoid disabling potential load folding opportunities.
15243 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15245 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15255 //===----------------------------------------------------------------------===//
15256 // X86 Inline Assembly Support
15257 //===----------------------------------------------------------------------===//
15260 // Helper to match a string separated by whitespace.
15261 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15262 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15264 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15265 StringRef piece(*args[i]);
15266 if (!s.startswith(piece)) // Check if the piece matches.
15269 s = s.substr(piece.size());
15270 StringRef::size_type pos = s.find_first_not_of(" \t");
15271 if (pos == 0) // We matched a prefix.
15279 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15282 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15283 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15285 std::string AsmStr = IA->getAsmString();
15287 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15288 if (!Ty || Ty->getBitWidth() % 16 != 0)
15291 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15292 SmallVector<StringRef, 4> AsmPieces;
15293 SplitString(AsmStr, AsmPieces, ";\n");
15295 switch (AsmPieces.size()) {
15296 default: return false;
15298 // FIXME: this should verify that we are targeting a 486 or better. If not,
15299 // we will turn this bswap into something that will be lowered to logical
15300 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15301 // lower so don't worry about this.
15303 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15304 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15305 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15306 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15307 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15308 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15309 // No need to check constraints, nothing other than the equivalent of
15310 // "=r,0" would be valid here.
15311 return IntrinsicLowering::LowerToByteSwap(CI);
15314 // rorw $$8, ${0:w} --> llvm.bswap.i16
15315 if (CI->getType()->isIntegerTy(16) &&
15316 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15317 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15318 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15320 const std::string &ConstraintsStr = IA->getConstraintString();
15321 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15322 std::sort(AsmPieces.begin(), AsmPieces.end());
15323 if (AsmPieces.size() == 4 &&
15324 AsmPieces[0] == "~{cc}" &&
15325 AsmPieces[1] == "~{dirflag}" &&
15326 AsmPieces[2] == "~{flags}" &&
15327 AsmPieces[3] == "~{fpsr}")
15328 return IntrinsicLowering::LowerToByteSwap(CI);
15332 if (CI->getType()->isIntegerTy(32) &&
15333 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15334 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15335 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15336 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15338 const std::string &ConstraintsStr = IA->getConstraintString();
15339 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15340 std::sort(AsmPieces.begin(), AsmPieces.end());
15341 if (AsmPieces.size() == 4 &&
15342 AsmPieces[0] == "~{cc}" &&
15343 AsmPieces[1] == "~{dirflag}" &&
15344 AsmPieces[2] == "~{flags}" &&
15345 AsmPieces[3] == "~{fpsr}")
15346 return IntrinsicLowering::LowerToByteSwap(CI);
15349 if (CI->getType()->isIntegerTy(64)) {
15350 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15351 if (Constraints.size() >= 2 &&
15352 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15353 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15354 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15355 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15356 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15357 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15358 return IntrinsicLowering::LowerToByteSwap(CI);
15368 /// getConstraintType - Given a constraint letter, return the type of
15369 /// constraint it is for this target.
15370 X86TargetLowering::ConstraintType
15371 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15372 if (Constraint.size() == 1) {
15373 switch (Constraint[0]) {
15384 return C_RegisterClass;
15408 return TargetLowering::getConstraintType(Constraint);
15411 /// Examine constraint type and operand type and determine a weight value.
15412 /// This object must already have been set up with the operand type
15413 /// and the current alternative constraint selected.
15414 TargetLowering::ConstraintWeight
15415 X86TargetLowering::getSingleConstraintMatchWeight(
15416 AsmOperandInfo &info, const char *constraint) const {
15417 ConstraintWeight weight = CW_Invalid;
15418 Value *CallOperandVal = info.CallOperandVal;
15419 // If we don't have a value, we can't do a match,
15420 // but allow it at the lowest weight.
15421 if (CallOperandVal == NULL)
15423 Type *type = CallOperandVal->getType();
15424 // Look at the constraint type.
15425 switch (*constraint) {
15427 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15438 if (CallOperandVal->getType()->isIntegerTy())
15439 weight = CW_SpecificReg;
15444 if (type->isFloatingPointTy())
15445 weight = CW_SpecificReg;
15448 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15449 weight = CW_SpecificReg;
15453 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15454 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15455 weight = CW_Register;
15458 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15459 if (C->getZExtValue() <= 31)
15460 weight = CW_Constant;
15464 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15465 if (C->getZExtValue() <= 63)
15466 weight = CW_Constant;
15470 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15471 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15472 weight = CW_Constant;
15476 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15477 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15478 weight = CW_Constant;
15482 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15483 if (C->getZExtValue() <= 3)
15484 weight = CW_Constant;
15488 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15489 if (C->getZExtValue() <= 0xff)
15490 weight = CW_Constant;
15495 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15496 weight = CW_Constant;
15500 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15501 if ((C->getSExtValue() >= -0x80000000LL) &&
15502 (C->getSExtValue() <= 0x7fffffffLL))
15503 weight = CW_Constant;
15507 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15508 if (C->getZExtValue() <= 0xffffffff)
15509 weight = CW_Constant;
15516 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15517 /// with another that has more specific requirements based on the type of the
15518 /// corresponding operand.
15519 const char *X86TargetLowering::
15520 LowerXConstraint(EVT ConstraintVT) const {
15521 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15522 // 'f' like normal targets.
15523 if (ConstraintVT.isFloatingPoint()) {
15524 if (Subtarget->hasSSE2())
15526 if (Subtarget->hasSSE1())
15530 return TargetLowering::LowerXConstraint(ConstraintVT);
15533 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15534 /// vector. If it is invalid, don't add anything to Ops.
15535 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15536 std::string &Constraint,
15537 std::vector<SDValue>&Ops,
15538 SelectionDAG &DAG) const {
15539 SDValue Result(0, 0);
15541 // Only support length 1 constraints for now.
15542 if (Constraint.length() > 1) return;
15544 char ConstraintLetter = Constraint[0];
15545 switch (ConstraintLetter) {
15548 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15549 if (C->getZExtValue() <= 31) {
15550 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15556 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15557 if (C->getZExtValue() <= 63) {
15558 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15565 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15566 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15572 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15573 if (C->getZExtValue() <= 255) {
15574 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15580 // 32-bit signed value
15581 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15582 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15583 C->getSExtValue())) {
15584 // Widen to 64 bits here to get it sign extended.
15585 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15588 // FIXME gcc accepts some relocatable values here too, but only in certain
15589 // memory models; it's complicated.
15594 // 32-bit unsigned value
15595 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15596 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15597 C->getZExtValue())) {
15598 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15602 // FIXME gcc accepts some relocatable values here too, but only in certain
15603 // memory models; it's complicated.
15607 // Literal immediates are always ok.
15608 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15609 // Widen to 64 bits here to get it sign extended.
15610 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15614 // In any sort of PIC mode addresses need to be computed at runtime by
15615 // adding in a register or some sort of table lookup. These can't
15616 // be used as immediates.
15617 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15620 // If we are in non-pic codegen mode, we allow the address of a global (with
15621 // an optional displacement) to be used with 'i'.
15622 GlobalAddressSDNode *GA = 0;
15623 int64_t Offset = 0;
15625 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15627 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15628 Offset += GA->getOffset();
15630 } else if (Op.getOpcode() == ISD::ADD) {
15631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15632 Offset += C->getZExtValue();
15633 Op = Op.getOperand(0);
15636 } else if (Op.getOpcode() == ISD::SUB) {
15637 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15638 Offset += -C->getZExtValue();
15639 Op = Op.getOperand(0);
15644 // Otherwise, this isn't something we can handle, reject it.
15648 const GlobalValue *GV = GA->getGlobal();
15649 // If we require an extra load to get this address, as in PIC mode, we
15650 // can't accept it.
15651 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15652 getTargetMachine())))
15655 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15656 GA->getValueType(0), Offset);
15661 if (Result.getNode()) {
15662 Ops.push_back(Result);
15665 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15668 std::pair<unsigned, const TargetRegisterClass*>
15669 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15671 // First, see if this is a constraint that directly corresponds to an LLVM
15673 if (Constraint.size() == 1) {
15674 // GCC Constraint Letters
15675 switch (Constraint[0]) {
15677 // TODO: Slight differences here in allocation order and leaving
15678 // RIP in the class. Do they matter any more here than they do
15679 // in the normal allocation?
15680 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15681 if (Subtarget->is64Bit()) {
15682 if (VT == MVT::i32 || VT == MVT::f32)
15683 return std::make_pair(0U, &X86::GR32RegClass);
15684 if (VT == MVT::i16)
15685 return std::make_pair(0U, &X86::GR16RegClass);
15686 if (VT == MVT::i8 || VT == MVT::i1)
15687 return std::make_pair(0U, &X86::GR8RegClass);
15688 if (VT == MVT::i64 || VT == MVT::f64)
15689 return std::make_pair(0U, &X86::GR64RegClass);
15692 // 32-bit fallthrough
15693 case 'Q': // Q_REGS
15694 if (VT == MVT::i32 || VT == MVT::f32)
15695 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15696 if (VT == MVT::i16)
15697 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15698 if (VT == MVT::i8 || VT == MVT::i1)
15699 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15700 if (VT == MVT::i64)
15701 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15703 case 'r': // GENERAL_REGS
15704 case 'l': // INDEX_REGS
15705 if (VT == MVT::i8 || VT == MVT::i1)
15706 return std::make_pair(0U, &X86::GR8RegClass);
15707 if (VT == MVT::i16)
15708 return std::make_pair(0U, &X86::GR16RegClass);
15709 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15710 return std::make_pair(0U, &X86::GR32RegClass);
15711 return std::make_pair(0U, &X86::GR64RegClass);
15712 case 'R': // LEGACY_REGS
15713 if (VT == MVT::i8 || VT == MVT::i1)
15714 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15715 if (VT == MVT::i16)
15716 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15717 if (VT == MVT::i32 || !Subtarget->is64Bit())
15718 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15719 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15720 case 'f': // FP Stack registers.
15721 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15722 // value to the correct fpstack register class.
15723 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15724 return std::make_pair(0U, &X86::RFP32RegClass);
15725 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15726 return std::make_pair(0U, &X86::RFP64RegClass);
15727 return std::make_pair(0U, &X86::RFP80RegClass);
15728 case 'y': // MMX_REGS if MMX allowed.
15729 if (!Subtarget->hasMMX()) break;
15730 return std::make_pair(0U, &X86::VR64RegClass);
15731 case 'Y': // SSE_REGS if SSE2 allowed
15732 if (!Subtarget->hasSSE2()) break;
15734 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15735 if (!Subtarget->hasSSE1()) break;
15737 switch (VT.getSimpleVT().SimpleTy) {
15739 // Scalar SSE types.
15742 return std::make_pair(0U, &X86::FR32RegClass);
15745 return std::make_pair(0U, &X86::FR64RegClass);
15753 return std::make_pair(0U, &X86::VR128RegClass);
15761 return std::make_pair(0U, &X86::VR256RegClass);
15767 // Use the default implementation in TargetLowering to convert the register
15768 // constraint into a member of a register class.
15769 std::pair<unsigned, const TargetRegisterClass*> Res;
15770 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15772 // Not found as a standard register?
15773 if (Res.second == 0) {
15774 // Map st(0) -> st(7) -> ST0
15775 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15776 tolower(Constraint[1]) == 's' &&
15777 tolower(Constraint[2]) == 't' &&
15778 Constraint[3] == '(' &&
15779 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15780 Constraint[5] == ')' &&
15781 Constraint[6] == '}') {
15783 Res.first = X86::ST0+Constraint[4]-'0';
15784 Res.second = &X86::RFP80RegClass;
15788 // GCC allows "st(0)" to be called just plain "st".
15789 if (StringRef("{st}").equals_lower(Constraint)) {
15790 Res.first = X86::ST0;
15791 Res.second = &X86::RFP80RegClass;
15796 if (StringRef("{flags}").equals_lower(Constraint)) {
15797 Res.first = X86::EFLAGS;
15798 Res.second = &X86::CCRRegClass;
15802 // 'A' means EAX + EDX.
15803 if (Constraint == "A") {
15804 Res.first = X86::EAX;
15805 Res.second = &X86::GR32_ADRegClass;
15811 // Otherwise, check to see if this is a register class of the wrong value
15812 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15813 // turn into {ax},{dx}.
15814 if (Res.second->hasType(VT))
15815 return Res; // Correct type already, nothing to do.
15817 // All of the single-register GCC register classes map their values onto
15818 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15819 // really want an 8-bit or 32-bit register, map to the appropriate register
15820 // class and return the appropriate register.
15821 if (Res.second == &X86::GR16RegClass) {
15822 if (VT == MVT::i8) {
15823 unsigned DestReg = 0;
15824 switch (Res.first) {
15826 case X86::AX: DestReg = X86::AL; break;
15827 case X86::DX: DestReg = X86::DL; break;
15828 case X86::CX: DestReg = X86::CL; break;
15829 case X86::BX: DestReg = X86::BL; break;
15832 Res.first = DestReg;
15833 Res.second = &X86::GR8RegClass;
15835 } else if (VT == MVT::i32) {
15836 unsigned DestReg = 0;
15837 switch (Res.first) {
15839 case X86::AX: DestReg = X86::EAX; break;
15840 case X86::DX: DestReg = X86::EDX; break;
15841 case X86::CX: DestReg = X86::ECX; break;
15842 case X86::BX: DestReg = X86::EBX; break;
15843 case X86::SI: DestReg = X86::ESI; break;
15844 case X86::DI: DestReg = X86::EDI; break;
15845 case X86::BP: DestReg = X86::EBP; break;
15846 case X86::SP: DestReg = X86::ESP; break;
15849 Res.first = DestReg;
15850 Res.second = &X86::GR32RegClass;
15852 } else if (VT == MVT::i64) {
15853 unsigned DestReg = 0;
15854 switch (Res.first) {
15856 case X86::AX: DestReg = X86::RAX; break;
15857 case X86::DX: DestReg = X86::RDX; break;
15858 case X86::CX: DestReg = X86::RCX; break;
15859 case X86::BX: DestReg = X86::RBX; break;
15860 case X86::SI: DestReg = X86::RSI; break;
15861 case X86::DI: DestReg = X86::RDI; break;
15862 case X86::BP: DestReg = X86::RBP; break;
15863 case X86::SP: DestReg = X86::RSP; break;
15866 Res.first = DestReg;
15867 Res.second = &X86::GR64RegClass;
15870 } else if (Res.second == &X86::FR32RegClass ||
15871 Res.second == &X86::FR64RegClass ||
15872 Res.second == &X86::VR128RegClass) {
15873 // Handle references to XMM physical registers that got mapped into the
15874 // wrong class. This can happen with constraints like {xmm0} where the
15875 // target independent register mapper will just pick the first match it can
15876 // find, ignoring the required type.
15877 if (VT == MVT::f32)
15878 Res.second = &X86::FR32RegClass;
15879 else if (VT == MVT::f64)
15880 Res.second = &X86::FR64RegClass;
15881 else if (X86::VR128RegClass.hasType(VT))
15882 Res.second = &X86::VR128RegClass;