1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/ADT/VectorExtras.h"
26 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/SSARegMap.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/ADT/StringExtras.h"
39 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
40 cl::desc("Enable fastcc on X86"));
41 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
42 : TargetLowering(TM) {
43 Subtarget = &TM.getSubtarget<X86Subtarget>();
44 X86ScalarSSE = Subtarget->hasSSE2();
45 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
47 // Set up the TargetLowering object.
49 // X86 is weird, it always uses i8 for shift amounts and setcc results.
50 setShiftAmountType(MVT::i8);
51 setSetCCResultType(MVT::i8);
52 setSetCCResultContents(ZeroOrOneSetCCResult);
53 setSchedulingPreference(SchedulingForRegPressure);
54 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
55 setStackPointerRegisterToSaveRestore(X86StackPtr);
57 if (Subtarget->isTargetDarwin()) {
58 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
59 setUseUnderscoreSetJmp(false);
60 setUseUnderscoreLongJmp(false);
61 } else if (Subtarget->isTargetMingw()) {
62 // MS runtime is weird: it exports _setjmp, but longjmp!
63 setUseUnderscoreSetJmp(true);
64 setUseUnderscoreLongJmp(false);
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
70 // Add legal addressing mode scale values.
71 addLegalAddressScale(8);
72 addLegalAddressScale(4);
73 addLegalAddressScale(2);
74 // Enter the ones which require both scale + index last. These are more
76 addLegalAddressScale(9);
77 addLegalAddressScale(5);
78 addLegalAddressScale(3);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
89 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
91 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
92 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
93 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
95 if (Subtarget->is64Bit()) {
96 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
97 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
100 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
101 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
103 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
106 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
108 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
109 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
110 // SSE has no i16 to fp conversion, only i32
112 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
114 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
115 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
118 if (!Subtarget->is64Bit()) {
119 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
120 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
124 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
126 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
127 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
130 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
132 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
133 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
136 // Handle FP_TO_UINT by promoting the destination to a larger signed
138 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
139 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
140 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
144 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
146 if (X86ScalarSSE && !Subtarget->hasSSE3())
147 // Expand FP_TO_UINT into a select.
148 // FIXME: We would like to use a Custom expander here eventually to do
149 // the optimal thing for SSE vs. the default expansion in the legalizer.
150 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
152 // With SSE3 we can use fisttpll to convert to a signed i64.
153 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
156 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
158 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
159 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
162 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
163 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
164 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
165 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
166 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
167 if (Subtarget->is64Bit())
168 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
172 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
173 setOperationAction(ISD::FREM , MVT::f64 , Expand);
175 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
176 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
177 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
178 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
179 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
180 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
181 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
182 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
183 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
184 if (Subtarget->is64Bit()) {
185 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
186 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
187 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
190 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
191 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
193 // These should be promoted to a larger select which is supported.
194 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
195 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
196 // X86 wants to expand cmov itself.
197 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
198 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
199 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
200 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
201 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
202 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
203 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
204 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
205 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
206 if (Subtarget->is64Bit()) {
207 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
208 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
210 // X86 ret instruction may pop stack.
211 setOperationAction(ISD::RET , MVT::Other, Custom);
213 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
214 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
215 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
216 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
217 if (Subtarget->is64Bit()) {
218 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
219 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
220 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
221 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
223 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
224 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
225 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
226 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
227 // X86 wants to expand memset / memcpy itself.
228 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
229 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
231 // We don't have line number support yet.
232 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
233 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
234 // FIXME - use subtarget debug flags
235 if (!Subtarget->isTargetDarwin() &&
236 !Subtarget->isTargetELF() &&
237 !Subtarget->isTargetCygMing())
238 setOperationAction(ISD::LABEL, MVT::Other, Expand);
240 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
241 setOperationAction(ISD::VASTART , MVT::Other, Custom);
243 // Use the default implementation.
244 setOperationAction(ISD::VAARG , MVT::Other, Expand);
245 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
246 setOperationAction(ISD::VAEND , MVT::Other, Expand);
247 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
248 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
249 if (Subtarget->is64Bit())
250 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
251 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
254 // Set up the FP register classes.
255 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
256 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
258 // Use ANDPD to simulate FABS.
259 setOperationAction(ISD::FABS , MVT::f64, Custom);
260 setOperationAction(ISD::FABS , MVT::f32, Custom);
262 // Use XORP to simulate FNEG.
263 setOperationAction(ISD::FNEG , MVT::f64, Custom);
264 setOperationAction(ISD::FNEG , MVT::f32, Custom);
266 // Use ANDPD and ORPD to simulate FCOPYSIGN.
267 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
268 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
270 // We don't support sin/cos/fmod
271 setOperationAction(ISD::FSIN , MVT::f64, Expand);
272 setOperationAction(ISD::FCOS , MVT::f64, Expand);
273 setOperationAction(ISD::FREM , MVT::f64, Expand);
274 setOperationAction(ISD::FSIN , MVT::f32, Expand);
275 setOperationAction(ISD::FCOS , MVT::f32, Expand);
276 setOperationAction(ISD::FREM , MVT::f32, Expand);
278 // Expand FP immediates into loads from the stack, except for the special
280 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
281 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
282 addLegalFPImmediate(+0.0); // xorps / xorpd
284 // Set up the FP register classes.
285 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
287 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
288 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
289 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
292 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
293 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
296 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
297 addLegalFPImmediate(+0.0); // FLD0
298 addLegalFPImmediate(+1.0); // FLD1
299 addLegalFPImmediate(-0.0); // FLD0/FCHS
300 addLegalFPImmediate(-1.0); // FLD1/FCHS
303 // First set operation action for all vector types to expand. Then we
304 // will selectively turn on ones that can be effectively codegen'd.
305 for (unsigned VT = (unsigned)MVT::Vector + 1;
306 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
307 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
308 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
309 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
310 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
311 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
312 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
313 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
314 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
315 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
316 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
317 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
318 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
319 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
320 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
321 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
324 if (Subtarget->hasMMX()) {
325 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
326 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
327 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
329 // FIXME: add MMX packed arithmetics
330 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
331 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
332 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
335 if (Subtarget->hasSSE1()) {
336 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
338 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
339 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
340 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
341 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
342 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
343 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
344 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
346 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
349 if (Subtarget->hasSSE2()) {
350 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
351 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
352 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
353 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
354 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
356 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
357 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
358 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
359 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
360 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
361 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
362 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
363 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
364 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
365 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
366 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
368 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
369 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
370 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
371 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
372 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
373 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
375 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
376 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
377 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
378 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
379 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
381 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
382 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
383 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
384 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
385 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
388 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
389 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
390 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
391 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
392 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
393 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
394 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
395 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
396 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
397 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
398 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
399 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
402 // Custom lower v2i64 and v2f64 selects.
403 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
404 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
405 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
406 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
409 // We want to custom lower some of our intrinsics.
410 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
412 // We have target-specific dag combine patterns for the following nodes:
413 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
414 setTargetDAGCombine(ISD::SELECT);
416 computeRegisterProperties();
418 // FIXME: These should be based on subtarget info. Plus, the values should
419 // be smaller when we are in optimizing for size mode.
420 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
421 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
422 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
423 allowUnalignedMemoryAccesses = true; // x86 supports it!
426 //===----------------------------------------------------------------------===//
427 // C & StdCall Calling Convention implementation
428 //===----------------------------------------------------------------------===//
429 // StdCall calling convention seems to be standard for many Windows' API
430 // routines and around. It differs from C calling convention just a little:
431 // callee should clean up the stack, not caller. Symbols should be also
432 // decorated in some fancy way :) It doesn't support any vector arguments.
434 /// AddLiveIn - This helper function adds the specified physical register to the
435 /// MachineFunction as a live in value. It also creates a corresponding virtual
437 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
438 const TargetRegisterClass *RC) {
439 assert(RC->contains(PReg) && "Not the correct regclass!");
440 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
441 MF.addLiveIn(PReg, VReg);
445 /// HowToPassArgument - Returns how an formal argument of the specified type
446 /// should be passed. If it is through stack, returns the size of the stack
447 /// slot; if it is through integer or XMM register, returns the number of
448 /// integer or XMM registers are needed.
450 HowToPassCallArgument(MVT::ValueType ObjectVT,
452 unsigned NumIntRegs, unsigned NumXMMRegs,
453 unsigned MaxNumIntRegs,
454 unsigned &ObjSize, unsigned &ObjIntRegs,
455 unsigned &ObjXMMRegs,
456 bool AllowVectors = true) {
461 if (MaxNumIntRegs>3) {
462 // We don't have too much registers on ia32! :)
467 default: assert(0 && "Unhandled argument type!");
469 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
475 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
481 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
487 if (ArgInReg && (NumIntRegs+2 <= MaxNumIntRegs)) {
489 } else if (ArgInReg && (NumIntRegs+1 <= MaxNumIntRegs)) {
513 assert(0 && "Unhandled argument type [vector]!");
517 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
519 unsigned NumArgs = Op.Val->getNumValues() - 1;
520 MachineFunction &MF = DAG.getMachineFunction();
521 MachineFrameInfo *MFI = MF.getFrameInfo();
522 SDOperand Root = Op.getOperand(0);
523 std::vector<SDOperand> ArgValues;
524 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
526 // Add DAG nodes to load the arguments... On entry to a function on the X86,
527 // the stack frame looks like this:
529 // [ESP] -- return address
530 // [ESP + 4] -- first argument (leftmost lexically)
531 // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size
534 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
535 unsigned NumSRetBytes= 0; // How much bytes on stack used for struct return
536 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
537 unsigned NumIntRegs = 0; // Integer regs used for parameter passing
539 static const unsigned XMMArgRegs[] = {
540 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
542 static const unsigned GPRArgRegs[][3] = {
543 { X86::AL, X86::DL, X86::CL },
544 { X86::AX, X86::DX, X86::CX },
545 { X86::EAX, X86::EDX, X86::ECX }
547 static const TargetRegisterClass* GPRClasses[3] = {
548 X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
551 // Handle regparm attribute
552 std::vector<bool> ArgInRegs(NumArgs, false);
553 std::vector<bool> SRetArgs(NumArgs, false);
555 for (unsigned i = 0; i<NumArgs; ++i) {
556 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
557 ArgInRegs[i] = (Flags >> 1) & 1;
558 SRetArgs[i] = (Flags >> 2) & 1;
562 for (unsigned i = 0; i < NumArgs; ++i) {
563 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
564 unsigned ArgIncrement = 4;
565 unsigned ObjSize = 0;
566 unsigned ObjXMMRegs = 0;
567 unsigned ObjIntRegs = 0;
571 HowToPassCallArgument(ObjectVT,
573 NumIntRegs, NumXMMRegs, 3,
574 ObjSize, ObjIntRegs, ObjXMMRegs,
578 ArgIncrement = ObjSize;
580 if (ObjIntRegs || ObjXMMRegs) {
582 default: assert(0 && "Unhandled argument type!");
586 unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
587 Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
588 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
597 assert(!isStdCall && "Unhandled argument type!");
598 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
599 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
602 NumIntRegs += ObjIntRegs;
603 NumXMMRegs += ObjXMMRegs;
606 // XMM arguments have to be aligned on 16-byte boundary.
608 ArgOffset = ((ArgOffset + 15) / 16) * 16;
609 // Create the SelectionDAG nodes corresponding to a load from this
611 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
612 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
613 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
615 ArgOffset += ArgIncrement; // Move on to the next argument.
617 NumSRetBytes += ArgIncrement;
620 ArgValues.push_back(ArgValue);
623 ArgValues.push_back(Root);
625 // If the function takes variable number of arguments, make a frame index for
626 // the start of the first vararg value... for expansion of llvm.va_start.
628 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
630 if (isStdCall && !isVarArg) {
631 BytesToPopOnReturn = ArgOffset; // Callee pops everything..
632 BytesCallerReserves = 0;
634 BytesToPopOnReturn = NumSRetBytes; // Callee pops hidden struct pointer.
635 BytesCallerReserves = ArgOffset;
638 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
639 ReturnAddrIndex = 0; // No return address slot generated yet.
642 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
644 // Return the new list of results.
645 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
646 Op.Val->value_end());
647 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
650 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
652 SDOperand Chain = Op.getOperand(0);
653 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
654 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
655 SDOperand Callee = Op.getOperand(4);
656 MVT::ValueType RetVT= Op.Val->getValueType(0);
657 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
659 static const unsigned XMMArgRegs[] = {
660 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
662 static const unsigned GPR32ArgRegs[] = {
663 X86::EAX, X86::EDX, X86::ECX
666 // Count how many bytes are to be pushed on the stack.
667 unsigned NumBytes = 0;
668 // Keep track of the number of integer regs passed so far.
669 unsigned NumIntRegs = 0;
670 // Keep track of the number of XMM regs passed so far.
671 unsigned NumXMMRegs = 0;
672 // How much bytes on stack used for struct return
673 unsigned NumSRetBytes= 0;
675 // Handle regparm attribute
676 std::vector<bool> ArgInRegs(NumOps, false);
677 std::vector<bool> SRetArgs(NumOps, false);
678 for (unsigned i = 0; i<NumOps; ++i) {
680 dyn_cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
681 ArgInRegs[i] = (Flags >> 1) & 1;
682 SRetArgs[i] = (Flags >> 2) & 1;
685 // Calculate stack frame size
686 for (unsigned i = 0; i != NumOps; ++i) {
687 SDOperand Arg = Op.getOperand(5+2*i);
688 unsigned ArgIncrement = 4;
689 unsigned ObjSize = 0;
690 unsigned ObjIntRegs = 0;
691 unsigned ObjXMMRegs = 0;
693 HowToPassCallArgument(Arg.getValueType(),
695 NumIntRegs, NumXMMRegs, 3,
696 ObjSize, ObjIntRegs, ObjXMMRegs,
699 ArgIncrement = ObjSize;
701 NumIntRegs += ObjIntRegs;
702 NumXMMRegs += ObjXMMRegs;
704 // XMM arguments have to be aligned on 16-byte boundary.
706 NumBytes = ((NumBytes + 15) / 16) * 16;
707 NumBytes += ArgIncrement;
711 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
713 // Arguments go on the stack in reverse order, as specified by the ABI.
714 unsigned ArgOffset = 0;
717 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
718 std::vector<SDOperand> MemOpChains;
719 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
720 for (unsigned i = 0; i != NumOps; ++i) {
721 SDOperand Arg = Op.getOperand(5+2*i);
722 unsigned ArgIncrement = 4;
723 unsigned ObjSize = 0;
724 unsigned ObjIntRegs = 0;
725 unsigned ObjXMMRegs = 0;
727 HowToPassCallArgument(Arg.getValueType(),
729 NumIntRegs, NumXMMRegs, 3,
730 ObjSize, ObjIntRegs, ObjXMMRegs,
734 ArgIncrement = ObjSize;
736 if (Arg.getValueType() == MVT::i8 || Arg.getValueType() == MVT::i16) {
737 // Promote the integer to 32 bits. If the input type is signed use a
738 // sign extend, otherwise use a zero extend.
739 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
741 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
742 Arg = DAG.getNode(ExtOp, MVT::i32, Arg);
745 if (ObjIntRegs || ObjXMMRegs) {
746 switch (Arg.getValueType()) {
747 default: assert(0 && "Unhandled argument type!");
749 RegsToPass.push_back(std::make_pair(GPR32ArgRegs[NumIntRegs], Arg));
757 assert(!isStdCall && "Unhandled argument type!");
758 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
762 NumIntRegs += ObjIntRegs;
763 NumXMMRegs += ObjXMMRegs;
766 // XMM arguments have to be aligned on 16-byte boundary.
768 ArgOffset = ((ArgOffset + 15) / 16) * 16;
770 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
771 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
772 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
774 ArgOffset += ArgIncrement; // Move on to the next argument.
776 NumSRetBytes += ArgIncrement;
780 if (!MemOpChains.empty())
781 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
782 &MemOpChains[0], MemOpChains.size());
784 // Build a sequence of copy-to-reg nodes chained together with token chain
785 // and flag operands which copy the outgoing args into registers.
787 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
788 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
790 InFlag = Chain.getValue(1);
793 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
794 Subtarget->isPICStyleGOT()) {
795 Chain = DAG.getCopyToReg(Chain, X86::EBX,
796 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
798 InFlag = Chain.getValue(1);
801 // If the callee is a GlobalAddress node (quite common, every direct call is)
802 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
803 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
804 // We should use extra load for direct calls to dllimported functions in
806 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
807 getTargetMachine(), true))
808 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
809 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
810 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
812 std::vector<MVT::ValueType> NodeTys;
813 NodeTys.push_back(MVT::Other); // Returns a chain
814 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
815 std::vector<SDOperand> Ops;
816 Ops.push_back(Chain);
817 Ops.push_back(Callee);
819 // Add argument registers to the end of the list so that they are known live
821 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
822 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
823 RegsToPass[i].second.getValueType()));
826 Ops.push_back(InFlag);
828 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
829 NodeTys, &Ops[0], Ops.size());
830 InFlag = Chain.getValue(1);
832 // Create the CALLSEQ_END node.
833 unsigned NumBytesForCalleeToPush = 0;
837 NumBytesForCalleeToPush = NumSRetBytes;
839 NumBytesForCalleeToPush = NumBytes;
842 // If this is is a call to a struct-return function, the callee
843 // pops the hidden struct pointer, so we have to push it back.
844 // This is common for Darwin/X86, Linux & Mingw32 targets.
845 NumBytesForCalleeToPush = NumSRetBytes;
849 NodeTys.push_back(MVT::Other); // Returns a chain
850 if (RetVT != MVT::Other)
851 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
853 Ops.push_back(Chain);
854 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
855 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
856 Ops.push_back(InFlag);
857 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
858 if (RetVT != MVT::Other)
859 InFlag = Chain.getValue(1);
861 std::vector<SDOperand> ResultVals;
864 default: assert(0 && "Unknown value type to return!");
865 case MVT::Other: break;
867 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
868 ResultVals.push_back(Chain.getValue(0));
869 NodeTys.push_back(MVT::i8);
872 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
873 ResultVals.push_back(Chain.getValue(0));
874 NodeTys.push_back(MVT::i16);
877 if (Op.Val->getValueType(1) == MVT::i32) {
878 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
879 ResultVals.push_back(Chain.getValue(0));
880 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32,
881 Chain.getValue(2)).getValue(1);
882 ResultVals.push_back(Chain.getValue(0));
883 NodeTys.push_back(MVT::i32);
885 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
886 ResultVals.push_back(Chain.getValue(0));
888 NodeTys.push_back(MVT::i32);
896 assert(!isStdCall && "Unknown value type to return!");
897 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
898 ResultVals.push_back(Chain.getValue(0));
899 NodeTys.push_back(RetVT);
903 std::vector<MVT::ValueType> Tys;
904 Tys.push_back(MVT::f64);
905 Tys.push_back(MVT::Other);
906 Tys.push_back(MVT::Flag);
907 std::vector<SDOperand> Ops;
908 Ops.push_back(Chain);
909 Ops.push_back(InFlag);
910 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys,
911 &Ops[0], Ops.size());
912 Chain = RetVal.getValue(1);
913 InFlag = RetVal.getValue(2);
915 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
916 // shouldn't be necessary except that RFP cannot be live across
917 // multiple blocks. When stackifier is fixed, they can be uncoupled.
918 MachineFunction &MF = DAG.getMachineFunction();
919 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
920 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
922 Tys.push_back(MVT::Other);
924 Ops.push_back(Chain);
925 Ops.push_back(RetVal);
926 Ops.push_back(StackSlot);
927 Ops.push_back(DAG.getValueType(RetVT));
928 Ops.push_back(InFlag);
929 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
930 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
931 Chain = RetVal.getValue(1);
934 if (RetVT == MVT::f32 && !X86ScalarSSE)
935 // FIXME: we would really like to remember that this FP_ROUND
936 // operation is okay to eliminate if we allow excess FP precision.
937 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
938 ResultVals.push_back(RetVal);
939 NodeTys.push_back(RetVT);
944 // If the function returns void, just return the chain.
945 if (ResultVals.empty())
948 // Otherwise, merge everything together with a MERGE_VALUES node.
949 NodeTys.push_back(MVT::Other);
950 ResultVals.push_back(Chain);
951 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
952 &ResultVals[0], ResultVals.size());
953 return Res.getValue(Op.ResNo);
957 //===----------------------------------------------------------------------===//
958 // X86-64 C Calling Convention implementation
959 //===----------------------------------------------------------------------===//
961 /// HowToPassX86_64CCCArgument - Returns how an formal argument of the specified
962 /// type should be passed. If it is through stack, returns the size of the stack
963 /// slot; if it is through integer or XMM register, returns the number of
964 /// integer or XMM registers are needed.
966 HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT,
967 unsigned NumIntRegs, unsigned NumXMMRegs,
968 unsigned &ObjSize, unsigned &ObjIntRegs,
969 unsigned &ObjXMMRegs) {
975 default: assert(0 && "Unhandled argument type!");
985 case MVT::i8: ObjSize = 1; break;
986 case MVT::i16: ObjSize = 2; break;
987 case MVT::i32: ObjSize = 4; break;
988 case MVT::i64: ObjSize = 8; break;
1005 case MVT::f32: ObjSize = 4; break;
1006 case MVT::f64: ObjSize = 8; break;
1012 case MVT::v2f64: ObjSize = 16; break;
1020 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1021 unsigned NumArgs = Op.Val->getNumValues() - 1;
1022 MachineFunction &MF = DAG.getMachineFunction();
1023 MachineFrameInfo *MFI = MF.getFrameInfo();
1024 SDOperand Root = Op.getOperand(0);
1025 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1026 std::vector<SDOperand> ArgValues;
1028 // Add DAG nodes to load the arguments... On entry to a function on the X86,
1029 // the stack frame looks like this:
1031 // [RSP] -- return address
1032 // [RSP + 8] -- first nonreg argument (leftmost lexically)
1033 // [RSP +16] -- second nonreg argument, if 1st argument is <= 8 bytes in size
1036 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
1037 unsigned NumIntRegs = 0; // Int regs used for parameter passing.
1038 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1040 static const unsigned GPR8ArgRegs[] = {
1041 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B
1043 static const unsigned GPR16ArgRegs[] = {
1044 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W
1046 static const unsigned GPR32ArgRegs[] = {
1047 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1049 static const unsigned GPR64ArgRegs[] = {
1050 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1052 static const unsigned XMMArgRegs[] = {
1053 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1054 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1057 for (unsigned i = 0; i < NumArgs; ++i) {
1058 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
1059 unsigned ArgIncrement = 8;
1060 unsigned ObjSize = 0;
1061 unsigned ObjIntRegs = 0;
1062 unsigned ObjXMMRegs = 0;
1064 // FIXME: __int128 and long double support?
1065 HowToPassX86_64CCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
1066 ObjSize, ObjIntRegs, ObjXMMRegs);
1068 ArgIncrement = ObjSize;
1072 if (ObjIntRegs || ObjXMMRegs) {
1074 default: assert(0 && "Unhandled argument type!");
1079 TargetRegisterClass *RC = NULL;
1083 RC = X86::GR8RegisterClass;
1084 Reg = GPR8ArgRegs[NumIntRegs];
1087 RC = X86::GR16RegisterClass;
1088 Reg = GPR16ArgRegs[NumIntRegs];
1091 RC = X86::GR32RegisterClass;
1092 Reg = GPR32ArgRegs[NumIntRegs];
1095 RC = X86::GR64RegisterClass;
1096 Reg = GPR64ArgRegs[NumIntRegs];
1099 Reg = AddLiveIn(MF, Reg, RC);
1100 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1111 TargetRegisterClass *RC= (ObjectVT == MVT::f32) ?
1112 X86::FR32RegisterClass : ((ObjectVT == MVT::f64) ?
1113 X86::FR64RegisterClass : X86::VR128RegisterClass);
1114 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], RC);
1115 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1119 NumIntRegs += ObjIntRegs;
1120 NumXMMRegs += ObjXMMRegs;
1121 } else if (ObjSize) {
1122 // XMM arguments have to be aligned on 16-byte boundary.
1124 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1125 // Create the SelectionDAG nodes corresponding to a load from this
1127 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1128 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1129 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
1130 ArgOffset += ArgIncrement; // Move on to the next argument.
1133 ArgValues.push_back(ArgValue);
1136 // If the function takes variable number of arguments, make a frame index for
1137 // the start of the first vararg value... for expansion of llvm.va_start.
1139 // For X86-64, if there are vararg parameters that are passed via
1140 // registers, then we must store them to their spots on the stack so they
1141 // may be loaded by deferencing the result of va_next.
1142 VarArgsGPOffset = NumIntRegs * 8;
1143 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1144 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
1145 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1147 // Store the integer parameter registers.
1148 std::vector<SDOperand> MemOps;
1149 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1150 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1151 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1152 for (; NumIntRegs != 6; ++NumIntRegs) {
1153 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1154 X86::GR64RegisterClass);
1155 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1156 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1157 MemOps.push_back(Store);
1158 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1159 DAG.getConstant(8, getPointerTy()));
1162 // Now store the XMM (fp + vector) parameter registers.
1163 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1164 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1165 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1166 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1167 X86::VR128RegisterClass);
1168 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1169 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1170 MemOps.push_back(Store);
1171 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1172 DAG.getConstant(16, getPointerTy()));
1174 if (!MemOps.empty())
1175 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1176 &MemOps[0], MemOps.size());
1179 ArgValues.push_back(Root);
1181 ReturnAddrIndex = 0; // No return address slot generated yet.
1182 BytesToPopOnReturn = 0; // Callee pops nothing.
1183 BytesCallerReserves = ArgOffset;
1185 // Return the new list of results.
1186 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
1187 Op.Val->value_end());
1188 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
1192 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG) {
1193 SDOperand Chain = Op.getOperand(0);
1194 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1195 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1196 SDOperand Callee = Op.getOperand(4);
1197 MVT::ValueType RetVT= Op.Val->getValueType(0);
1198 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1200 // Count how many bytes are to be pushed on the stack.
1201 unsigned NumBytes = 0;
1202 unsigned NumIntRegs = 0; // Int regs used for parameter passing.
1203 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1205 static const unsigned GPR8ArgRegs[] = {
1206 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B
1208 static const unsigned GPR16ArgRegs[] = {
1209 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W
1211 static const unsigned GPR32ArgRegs[] = {
1212 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1214 static const unsigned GPR64ArgRegs[] = {
1215 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1217 static const unsigned XMMArgRegs[] = {
1218 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1219 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1222 for (unsigned i = 0; i != NumOps; ++i) {
1223 SDOperand Arg = Op.getOperand(5+2*i);
1224 MVT::ValueType ArgVT = Arg.getValueType();
1227 default: assert(0 && "Unknown value type!");
1247 else if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
1250 // XMM arguments have to be aligned on 16-byte boundary.
1251 NumBytes = ((NumBytes + 15) / 16) * 16;
1258 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1260 // Arguments go on the stack in reverse order, as specified by the ABI.
1261 unsigned ArgOffset = 0;
1264 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1265 std::vector<SDOperand> MemOpChains;
1266 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1267 for (unsigned i = 0; i != NumOps; ++i) {
1268 SDOperand Arg = Op.getOperand(5+2*i);
1269 MVT::ValueType ArgVT = Arg.getValueType();
1272 default: assert(0 && "Unexpected ValueType for argument!");
1277 if (NumIntRegs < 6) {
1281 case MVT::i8: Reg = GPR8ArgRegs[NumIntRegs]; break;
1282 case MVT::i16: Reg = GPR16ArgRegs[NumIntRegs]; break;
1283 case MVT::i32: Reg = GPR32ArgRegs[NumIntRegs]; break;
1284 case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break;
1286 RegsToPass.push_back(std::make_pair(Reg, Arg));
1289 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1290 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1291 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1303 if (NumXMMRegs < 8) {
1304 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
1307 if (ArgVT != MVT::f32 && ArgVT != MVT::f64) {
1308 // XMM arguments have to be aligned on 16-byte boundary.
1309 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1311 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1312 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1313 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1314 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
1322 if (!MemOpChains.empty())
1323 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1324 &MemOpChains[0], MemOpChains.size());
1326 // Build a sequence of copy-to-reg nodes chained together with token chain
1327 // and flag operands which copy the outgoing args into registers.
1329 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1330 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1332 InFlag = Chain.getValue(1);
1336 // From AMD64 ABI document:
1337 // For calls that may call functions that use varargs or stdargs
1338 // (prototype-less calls or calls to functions containing ellipsis (...) in
1339 // the declaration) %al is used as hidden argument to specify the number
1340 // of SSE registers used. The contents of %al do not need to match exactly
1341 // the number of registers, but must be an ubound on the number of SSE
1342 // registers used and is in the range 0 - 8 inclusive.
1343 Chain = DAG.getCopyToReg(Chain, X86::AL,
1344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1345 InFlag = Chain.getValue(1);
1348 // If the callee is a GlobalAddress node (quite common, every direct call is)
1349 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1350 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1351 // We should use extra load for direct calls to dllimported functions in
1353 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1354 getTargetMachine(), true))
1355 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1356 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1357 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1359 std::vector<MVT::ValueType> NodeTys;
1360 NodeTys.push_back(MVT::Other); // Returns a chain
1361 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1362 std::vector<SDOperand> Ops;
1363 Ops.push_back(Chain);
1364 Ops.push_back(Callee);
1366 // Add argument registers to the end of the list so that they are known live
1368 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1369 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1370 RegsToPass[i].second.getValueType()));
1373 Ops.push_back(InFlag);
1375 // FIXME: Do not generate X86ISD::TAILCALL for now.
1376 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1377 NodeTys, &Ops[0], Ops.size());
1378 InFlag = Chain.getValue(1);
1381 NodeTys.push_back(MVT::Other); // Returns a chain
1382 if (RetVT != MVT::Other)
1383 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1385 Ops.push_back(Chain);
1386 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1387 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1388 Ops.push_back(InFlag);
1389 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1390 if (RetVT != MVT::Other)
1391 InFlag = Chain.getValue(1);
1393 std::vector<SDOperand> ResultVals;
1396 default: assert(0 && "Unknown value type to return!");
1397 case MVT::Other: break;
1399 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
1400 ResultVals.push_back(Chain.getValue(0));
1401 NodeTys.push_back(MVT::i8);
1404 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
1405 ResultVals.push_back(Chain.getValue(0));
1406 NodeTys.push_back(MVT::i16);
1409 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
1410 ResultVals.push_back(Chain.getValue(0));
1411 NodeTys.push_back(MVT::i32);
1414 if (Op.Val->getValueType(1) == MVT::i64) {
1415 // FIXME: __int128 support?
1416 Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1);
1417 ResultVals.push_back(Chain.getValue(0));
1418 Chain = DAG.getCopyFromReg(Chain, X86::RDX, MVT::i64,
1419 Chain.getValue(2)).getValue(1);
1420 ResultVals.push_back(Chain.getValue(0));
1421 NodeTys.push_back(MVT::i64);
1423 Chain = DAG.getCopyFromReg(Chain, X86::RAX, MVT::i64, InFlag).getValue(1);
1424 ResultVals.push_back(Chain.getValue(0));
1426 NodeTys.push_back(MVT::i64);
1436 // FIXME: long double support?
1437 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
1438 ResultVals.push_back(Chain.getValue(0));
1439 NodeTys.push_back(RetVT);
1443 // If the function returns void, just return the chain.
1444 if (ResultVals.empty())
1447 // Otherwise, merge everything together with a MERGE_VALUES node.
1448 NodeTys.push_back(MVT::Other);
1449 ResultVals.push_back(Chain);
1450 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1451 &ResultVals[0], ResultVals.size());
1452 return Res.getValue(Op.ResNo);
1455 //===----------------------------------------------------------------------===//
1456 // Fast & FastCall Calling Convention implementation
1457 //===----------------------------------------------------------------------===//
1459 // The X86 'fast' calling convention passes up to two integer arguments in
1460 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
1461 // and requires that the callee pop its arguments off the stack (allowing proper
1462 // tail calls), and has the same return value conventions as C calling convs.
1464 // This calling convention always arranges for the callee pop value to be 8n+4
1465 // bytes, which is needed for tail recursion elimination and stack alignment
1468 // Note that this can be enhanced in the future to pass fp vals in registers
1469 // (when we have a global fp allocator) and do other tricks.
1471 //===----------------------------------------------------------------------===//
1472 // The X86 'fastcall' calling convention passes up to two integer arguments in
1473 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
1474 // and requires that the callee pop its arguments off the stack (allowing proper
1475 // tail calls), and has the same return value conventions as C calling convs.
1477 // This calling convention always arranges for the callee pop value to be 8n+4
1478 // bytes, which is needed for tail recursion elimination and stack alignment
1483 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
1485 unsigned NumArgs = Op.Val->getNumValues()-1;
1486 MachineFunction &MF = DAG.getMachineFunction();
1487 MachineFrameInfo *MFI = MF.getFrameInfo();
1488 SDOperand Root = Op.getOperand(0);
1489 std::vector<SDOperand> ArgValues;
1491 // Add DAG nodes to load the arguments... On entry to a function the stack
1492 // frame looks like this:
1494 // [ESP] -- return address
1495 // [ESP + 4] -- first nonreg argument (leftmost lexically)
1496 // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
1498 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
1500 // Keep track of the number of integer regs passed so far. This can be either
1501 // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
1503 unsigned NumIntRegs = 0;
1504 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1506 static const unsigned XMMArgRegs[] = {
1507 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1510 static const unsigned GPRArgRegs[][2][2] = {
1511 {{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
1512 {{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
1513 {{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
1516 static const TargetRegisterClass* GPRClasses[3] = {
1517 X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
1520 unsigned GPRInd = (isFastCall ? 1 : 0);
1521 for (unsigned i = 0; i < NumArgs; ++i) {
1522 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
1523 unsigned ArgIncrement = 4;
1524 unsigned ObjSize = 0;
1525 unsigned ObjXMMRegs = 0;
1526 unsigned ObjIntRegs = 0;
1530 HowToPassCallArgument(ObjectVT,
1531 true, // Use as much registers as possible
1532 NumIntRegs, NumXMMRegs,
1533 (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS),
1534 ObjSize, ObjIntRegs, ObjXMMRegs,
1538 ArgIncrement = ObjSize;
1540 if (ObjIntRegs || ObjXMMRegs) {
1542 default: assert(0 && "Unhandled argument type!");
1546 unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs];
1547 Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
1548 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1556 assert(!isFastCall && "Unhandled argument type!");
1557 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
1558 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1562 NumIntRegs += ObjIntRegs;
1563 NumXMMRegs += ObjXMMRegs;
1566 // XMM arguments have to be aligned on 16-byte boundary.
1568 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1569 // Create the SelectionDAG nodes corresponding to a load from this
1571 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1572 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1573 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
1575 ArgOffset += ArgIncrement; // Move on to the next argument.
1578 ArgValues.push_back(ArgValue);
1581 ArgValues.push_back(Root);
1583 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1584 // arguments and the arguments after the retaddr has been pushed are aligned.
1585 if ((ArgOffset & 7) == 0)
1588 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1589 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
1590 ReturnAddrIndex = 0; // No return address slot generated yet.
1591 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
1592 BytesCallerReserves = 0;
1594 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
1596 // Finally, inform the code generator which regs we return values in.
1597 switch (getValueType(MF.getFunction()->getReturnType())) {
1598 default: assert(0 && "Unknown type!");
1599 case MVT::isVoid: break;
1604 MF.addLiveOut(X86::EAX);
1607 MF.addLiveOut(X86::EAX);
1608 MF.addLiveOut(X86::EDX);
1612 MF.addLiveOut(X86::ST0);
1620 assert(!isFastCall && "Unknown result type");
1621 MF.addLiveOut(X86::XMM0);
1625 // Return the new list of results.
1626 std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
1627 Op.Val->value_end());
1628 return DAG.getNode(ISD::MERGE_VALUES, RetVTs, &ArgValues[0],ArgValues.size());
1631 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1633 SDOperand Chain = Op.getOperand(0);
1634 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1635 SDOperand Callee = Op.getOperand(4);
1636 MVT::ValueType RetVT= Op.Val->getValueType(0);
1637 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1639 // Count how many bytes are to be pushed on the stack.
1640 unsigned NumBytes = 0;
1642 // Keep track of the number of integer regs passed so far. This can be either
1643 // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
1645 unsigned NumIntRegs = 0;
1646 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1648 static const unsigned GPRArgRegs[][2][2] = {
1649 {{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
1650 {{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
1651 {{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
1653 static const unsigned XMMArgRegs[] = {
1654 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1657 unsigned GPRInd = (isFastCall ? 1 : 0);
1658 for (unsigned i = 0; i != NumOps; ++i) {
1659 SDOperand Arg = Op.getOperand(5+2*i);
1661 switch (Arg.getValueType()) {
1662 default: assert(0 && "Unknown value type!");
1666 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
1667 if (NumIntRegs < MaxNumIntRegs) {
1684 assert(!isFastCall && "Unknown value type!");
1688 // XMM arguments have to be aligned on 16-byte boundary.
1689 NumBytes = ((NumBytes + 15) / 16) * 16;
1696 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1697 // arguments and the arguments after the retaddr has been pushed are aligned.
1698 if ((NumBytes & 7) == 0)
1701 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1703 // Arguments go on the stack in reverse order, as specified by the ABI.
1704 unsigned ArgOffset = 0;
1706 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1707 std::vector<SDOperand> MemOpChains;
1708 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1709 for (unsigned i = 0; i != NumOps; ++i) {
1710 SDOperand Arg = Op.getOperand(5+2*i);
1712 switch (Arg.getValueType()) {
1713 default: assert(0 && "Unexpected ValueType for argument!");
1717 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
1718 if (NumIntRegs < MaxNumIntRegs) {
1720 GPRArgRegs[Arg.getValueType()-MVT::i8][GPRInd][NumIntRegs];
1721 RegsToPass.push_back(std::make_pair(RegToUse, Arg));
1727 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1728 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1729 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1734 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1735 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1736 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1746 assert(!isFastCall && "Unexpected ValueType for argument!");
1747 if (NumXMMRegs < 4) {
1748 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
1751 // XMM arguments have to be aligned on 16-byte boundary.
1752 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1753 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1754 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1755 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1762 if (!MemOpChains.empty())
1763 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1764 &MemOpChains[0], MemOpChains.size());
1766 // Build a sequence of copy-to-reg nodes chained together with token chain
1767 // and flag operands which copy the outgoing args into registers.
1769 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1770 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1772 InFlag = Chain.getValue(1);
1775 // If the callee is a GlobalAddress node (quite common, every direct call is)
1776 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1777 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1778 // We should use extra load for direct calls to dllimported functions in
1780 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1781 getTargetMachine(), true))
1782 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1783 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1784 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1786 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1787 Subtarget->isPICStyleGOT()) {
1788 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1789 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1791 InFlag = Chain.getValue(1);
1794 std::vector<MVT::ValueType> NodeTys;
1795 NodeTys.push_back(MVT::Other); // Returns a chain
1796 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1797 std::vector<SDOperand> Ops;
1798 Ops.push_back(Chain);
1799 Ops.push_back(Callee);
1801 // Add argument registers to the end of the list so that they are known live
1803 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1804 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1805 RegsToPass[i].second.getValueType()));
1808 Ops.push_back(InFlag);
1810 // FIXME: Do not generate X86ISD::TAILCALL for now.
1811 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1812 NodeTys, &Ops[0], Ops.size());
1813 InFlag = Chain.getValue(1);
1816 NodeTys.push_back(MVT::Other); // Returns a chain
1817 if (RetVT != MVT::Other)
1818 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1820 Ops.push_back(Chain);
1821 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1822 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1823 Ops.push_back(InFlag);
1824 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1825 if (RetVT != MVT::Other)
1826 InFlag = Chain.getValue(1);
1828 std::vector<SDOperand> ResultVals;
1831 default: assert(0 && "Unknown value type to return!");
1832 case MVT::Other: break;
1834 Chain = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag).getValue(1);
1835 ResultVals.push_back(Chain.getValue(0));
1836 NodeTys.push_back(MVT::i8);
1839 Chain = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag).getValue(1);
1840 ResultVals.push_back(Chain.getValue(0));
1841 NodeTys.push_back(MVT::i16);
1844 if (Op.Val->getValueType(1) == MVT::i32) {
1845 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
1846 ResultVals.push_back(Chain.getValue(0));
1847 Chain = DAG.getCopyFromReg(Chain, X86::EDX, MVT::i32,
1848 Chain.getValue(2)).getValue(1);
1849 ResultVals.push_back(Chain.getValue(0));
1850 NodeTys.push_back(MVT::i32);
1852 Chain = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag).getValue(1);
1853 ResultVals.push_back(Chain.getValue(0));
1855 NodeTys.push_back(MVT::i32);
1864 assert(0 && "Unknown value type to return!");
1866 Chain = DAG.getCopyFromReg(Chain, X86::XMM0, RetVT, InFlag).getValue(1);
1867 ResultVals.push_back(Chain.getValue(0));
1868 NodeTys.push_back(RetVT);
1873 std::vector<MVT::ValueType> Tys;
1874 Tys.push_back(MVT::f64);
1875 Tys.push_back(MVT::Other);
1876 Tys.push_back(MVT::Flag);
1877 std::vector<SDOperand> Ops;
1878 Ops.push_back(Chain);
1879 Ops.push_back(InFlag);
1880 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys,
1881 &Ops[0], Ops.size());
1882 Chain = RetVal.getValue(1);
1883 InFlag = RetVal.getValue(2);
1885 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
1886 // shouldn't be necessary except that RFP cannot be live across
1887 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1888 MachineFunction &MF = DAG.getMachineFunction();
1889 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1890 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1892 Tys.push_back(MVT::Other);
1894 Ops.push_back(Chain);
1895 Ops.push_back(RetVal);
1896 Ops.push_back(StackSlot);
1897 Ops.push_back(DAG.getValueType(RetVT));
1898 Ops.push_back(InFlag);
1899 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
1900 RetVal = DAG.getLoad(RetVT, Chain, StackSlot, NULL, 0);
1901 Chain = RetVal.getValue(1);
1904 if (RetVT == MVT::f32 && !X86ScalarSSE)
1905 // FIXME: we would really like to remember that this FP_ROUND
1906 // operation is okay to eliminate if we allow excess FP precision.
1907 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1908 ResultVals.push_back(RetVal);
1909 NodeTys.push_back(RetVT);
1915 // If the function returns void, just return the chain.
1916 if (ResultVals.empty())
1919 // Otherwise, merge everything together with a MERGE_VALUES node.
1920 NodeTys.push_back(MVT::Other);
1921 ResultVals.push_back(Chain);
1922 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1923 &ResultVals[0], ResultVals.size());
1924 return Res.getValue(Op.ResNo);
1927 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1928 if (ReturnAddrIndex == 0) {
1929 // Set up a frame object for the return address.
1930 MachineFunction &MF = DAG.getMachineFunction();
1931 if (Subtarget->is64Bit())
1932 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1934 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1937 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1942 std::pair<SDOperand, SDOperand> X86TargetLowering::
1943 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1944 SelectionDAG &DAG) {
1946 if (Depth) // Depths > 0 not supported yet!
1947 Result = DAG.getConstant(0, getPointerTy());
1949 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1950 if (!isFrameAddress)
1951 // Just load the return address
1952 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI,
1955 Result = DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
1956 DAG.getConstant(4, getPointerTy()));
1958 return std::make_pair(Result, Chain);
1961 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1962 /// specific condition code. It returns a false if it cannot do a direct
1963 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1965 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1966 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1967 SelectionDAG &DAG) {
1968 X86CC = X86::COND_INVALID;
1970 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1971 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1972 // X > -1 -> X == 0, jump !sign.
1973 RHS = DAG.getConstant(0, RHS.getValueType());
1974 X86CC = X86::COND_NS;
1976 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1977 // X < 0 -> X == 0, jump on sign.
1978 X86CC = X86::COND_S;
1983 switch (SetCCOpcode) {
1985 case ISD::SETEQ: X86CC = X86::COND_E; break;
1986 case ISD::SETGT: X86CC = X86::COND_G; break;
1987 case ISD::SETGE: X86CC = X86::COND_GE; break;
1988 case ISD::SETLT: X86CC = X86::COND_L; break;
1989 case ISD::SETLE: X86CC = X86::COND_LE; break;
1990 case ISD::SETNE: X86CC = X86::COND_NE; break;
1991 case ISD::SETULT: X86CC = X86::COND_B; break;
1992 case ISD::SETUGT: X86CC = X86::COND_A; break;
1993 case ISD::SETULE: X86CC = X86::COND_BE; break;
1994 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1997 // On a floating point condition, the flags are set as follows:
1999 // 0 | 0 | 0 | X > Y
2000 // 0 | 0 | 1 | X < Y
2001 // 1 | 0 | 0 | X == Y
2002 // 1 | 1 | 1 | unordered
2004 switch (SetCCOpcode) {
2007 case ISD::SETEQ: X86CC = X86::COND_E; break;
2008 case ISD::SETOLT: Flip = true; // Fallthrough
2010 case ISD::SETGT: X86CC = X86::COND_A; break;
2011 case ISD::SETOLE: Flip = true; // Fallthrough
2013 case ISD::SETGE: X86CC = X86::COND_AE; break;
2014 case ISD::SETUGT: Flip = true; // Fallthrough
2016 case ISD::SETLT: X86CC = X86::COND_B; break;
2017 case ISD::SETUGE: Flip = true; // Fallthrough
2019 case ISD::SETLE: X86CC = X86::COND_BE; break;
2021 case ISD::SETNE: X86CC = X86::COND_NE; break;
2022 case ISD::SETUO: X86CC = X86::COND_P; break;
2023 case ISD::SETO: X86CC = X86::COND_NP; break;
2026 std::swap(LHS, RHS);
2029 return X86CC != X86::COND_INVALID;
2032 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2033 /// code. Current x86 isa includes the following FP cmov instructions:
2034 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2035 static bool hasFPCMov(unsigned X86CC) {
2051 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2052 /// true if Op is undef or if its value falls within the specified range (L, H].
2053 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
2054 if (Op.getOpcode() == ISD::UNDEF)
2057 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
2058 return (Val >= Low && Val < Hi);
2061 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2062 /// true if Op is undef or if its value equal to the specified value.
2063 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
2064 if (Op.getOpcode() == ISD::UNDEF)
2066 return cast<ConstantSDNode>(Op)->getValue() == Val;
2069 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2070 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2071 bool X86::isPSHUFDMask(SDNode *N) {
2072 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2074 if (N->getNumOperands() != 4)
2077 // Check if the value doesn't reference the second vector.
2078 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2079 SDOperand Arg = N->getOperand(i);
2080 if (Arg.getOpcode() == ISD::UNDEF) continue;
2081 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2082 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
2089 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2090 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2091 bool X86::isPSHUFHWMask(SDNode *N) {
2092 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2094 if (N->getNumOperands() != 8)
2097 // Lower quadword copied in order.
2098 for (unsigned i = 0; i != 4; ++i) {
2099 SDOperand Arg = N->getOperand(i);
2100 if (Arg.getOpcode() == ISD::UNDEF) continue;
2101 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2102 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2106 // Upper quadword shuffled.
2107 for (unsigned i = 4; i != 8; ++i) {
2108 SDOperand Arg = N->getOperand(i);
2109 if (Arg.getOpcode() == ISD::UNDEF) continue;
2110 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2111 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2112 if (Val < 4 || Val > 7)
2119 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2120 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2121 bool X86::isPSHUFLWMask(SDNode *N) {
2122 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2124 if (N->getNumOperands() != 8)
2127 // Upper quadword copied in order.
2128 for (unsigned i = 4; i != 8; ++i)
2129 if (!isUndefOrEqual(N->getOperand(i), i))
2132 // Lower quadword shuffled.
2133 for (unsigned i = 0; i != 4; ++i)
2134 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2140 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2141 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2142 static bool isSHUFPMask(std::vector<SDOperand> &N) {
2143 unsigned NumElems = N.size();
2144 if (NumElems != 2 && NumElems != 4) return false;
2146 unsigned Half = NumElems / 2;
2147 for (unsigned i = 0; i < Half; ++i)
2148 if (!isUndefOrInRange(N[i], 0, NumElems))
2150 for (unsigned i = Half; i < NumElems; ++i)
2151 if (!isUndefOrInRange(N[i], NumElems, NumElems*2))
2157 bool X86::isSHUFPMask(SDNode *N) {
2158 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2159 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2160 return ::isSHUFPMask(Ops);
2163 /// isCommutedSHUFP - Returns true if the shuffle mask is except
2164 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2165 /// half elements to come from vector 1 (which would equal the dest.) and
2166 /// the upper half to come from vector 2.
2167 static bool isCommutedSHUFP(std::vector<SDOperand> &Ops) {
2168 unsigned NumElems = Ops.size();
2169 if (NumElems != 2 && NumElems != 4) return false;
2171 unsigned Half = NumElems / 2;
2172 for (unsigned i = 0; i < Half; ++i)
2173 if (!isUndefOrInRange(Ops[i], NumElems, NumElems*2))
2175 for (unsigned i = Half; i < NumElems; ++i)
2176 if (!isUndefOrInRange(Ops[i], 0, NumElems))
2181 static bool isCommutedSHUFP(SDNode *N) {
2182 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2183 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2184 return isCommutedSHUFP(Ops);
2187 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2188 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2189 bool X86::isMOVHLPSMask(SDNode *N) {
2190 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2192 if (N->getNumOperands() != 4)
2195 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2196 return isUndefOrEqual(N->getOperand(0), 6) &&
2197 isUndefOrEqual(N->getOperand(1), 7) &&
2198 isUndefOrEqual(N->getOperand(2), 2) &&
2199 isUndefOrEqual(N->getOperand(3), 3);
2202 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2203 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2205 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2206 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2208 if (N->getNumOperands() != 4)
2211 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2212 return isUndefOrEqual(N->getOperand(0), 2) &&
2213 isUndefOrEqual(N->getOperand(1), 3) &&
2214 isUndefOrEqual(N->getOperand(2), 2) &&
2215 isUndefOrEqual(N->getOperand(3), 3);
2218 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2219 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2220 bool X86::isMOVLPMask(SDNode *N) {
2221 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2223 unsigned NumElems = N->getNumOperands();
2224 if (NumElems != 2 && NumElems != 4)
2227 for (unsigned i = 0; i < NumElems/2; ++i)
2228 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2231 for (unsigned i = NumElems/2; i < NumElems; ++i)
2232 if (!isUndefOrEqual(N->getOperand(i), i))
2238 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2239 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2241 bool X86::isMOVHPMask(SDNode *N) {
2242 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2244 unsigned NumElems = N->getNumOperands();
2245 if (NumElems != 2 && NumElems != 4)
2248 for (unsigned i = 0; i < NumElems/2; ++i)
2249 if (!isUndefOrEqual(N->getOperand(i), i))
2252 for (unsigned i = 0; i < NumElems/2; ++i) {
2253 SDOperand Arg = N->getOperand(i + NumElems/2);
2254 if (!isUndefOrEqual(Arg, i + NumElems))
2261 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2262 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2263 bool static isUNPCKLMask(std::vector<SDOperand> &N, bool V2IsSplat = false) {
2264 unsigned NumElems = N.size();
2265 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2268 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2269 SDOperand BitI = N[i];
2270 SDOperand BitI1 = N[i+1];
2271 if (!isUndefOrEqual(BitI, j))
2274 if (isUndefOrEqual(BitI1, NumElems))
2277 if (!isUndefOrEqual(BitI1, j + NumElems))
2285 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2286 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2287 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2288 return ::isUNPCKLMask(Ops, V2IsSplat);
2291 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2292 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2293 bool static isUNPCKHMask(std::vector<SDOperand> &N, bool V2IsSplat = false) {
2294 unsigned NumElems = N.size();
2295 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2298 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2299 SDOperand BitI = N[i];
2300 SDOperand BitI1 = N[i+1];
2301 if (!isUndefOrEqual(BitI, j + NumElems/2))
2304 if (isUndefOrEqual(BitI1, NumElems))
2307 if (!isUndefOrEqual(BitI1, j + NumElems/2 + NumElems))
2315 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2316 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2317 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2318 return ::isUNPCKHMask(Ops, V2IsSplat);
2321 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2322 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2324 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2325 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2327 unsigned NumElems = N->getNumOperands();
2328 if (NumElems != 4 && NumElems != 8 && NumElems != 16)
2331 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2332 SDOperand BitI = N->getOperand(i);
2333 SDOperand BitI1 = N->getOperand(i+1);
2335 if (!isUndefOrEqual(BitI, j))
2337 if (!isUndefOrEqual(BitI1, j))
2344 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2345 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2346 /// MOVSD, and MOVD, i.e. setting the lowest element.
2347 static bool isMOVLMask(std::vector<SDOperand> &N) {
2348 unsigned NumElems = N.size();
2349 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2352 if (!isUndefOrEqual(N[0], NumElems))
2355 for (unsigned i = 1; i < NumElems; ++i) {
2356 SDOperand Arg = N[i];
2357 if (!isUndefOrEqual(Arg, i))
2364 bool X86::isMOVLMask(SDNode *N) {
2365 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2366 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2367 return ::isMOVLMask(Ops);
2370 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2371 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2372 /// element of vector 2 and the other elements to come from vector 1 in order.
2373 static bool isCommutedMOVL(std::vector<SDOperand> &Ops, bool V2IsSplat = false,
2374 bool V2IsUndef = false) {
2375 unsigned NumElems = Ops.size();
2376 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2379 if (!isUndefOrEqual(Ops[0], 0))
2382 for (unsigned i = 1; i < NumElems; ++i) {
2383 SDOperand Arg = Ops[i];
2384 if (!(isUndefOrEqual(Arg, i+NumElems) ||
2385 (V2IsUndef && isUndefOrInRange(Arg, NumElems, NumElems*2)) ||
2386 (V2IsSplat && isUndefOrEqual(Arg, NumElems))))
2393 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2394 bool V2IsUndef = false) {
2395 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2396 std::vector<SDOperand> Ops(N->op_begin(), N->op_end());
2397 return isCommutedMOVL(Ops, V2IsSplat, V2IsUndef);
2400 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2401 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2402 bool X86::isMOVSHDUPMask(SDNode *N) {
2403 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2405 if (N->getNumOperands() != 4)
2408 // Expect 1, 1, 3, 3
2409 for (unsigned i = 0; i < 2; ++i) {
2410 SDOperand Arg = N->getOperand(i);
2411 if (Arg.getOpcode() == ISD::UNDEF) continue;
2412 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2413 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2414 if (Val != 1) return false;
2418 for (unsigned i = 2; i < 4; ++i) {
2419 SDOperand Arg = N->getOperand(i);
2420 if (Arg.getOpcode() == ISD::UNDEF) continue;
2421 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2422 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2423 if (Val != 3) return false;
2427 // Don't use movshdup if it can be done with a shufps.
2431 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2432 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2433 bool X86::isMOVSLDUPMask(SDNode *N) {
2434 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2436 if (N->getNumOperands() != 4)
2439 // Expect 0, 0, 2, 2
2440 for (unsigned i = 0; i < 2; ++i) {
2441 SDOperand Arg = N->getOperand(i);
2442 if (Arg.getOpcode() == ISD::UNDEF) continue;
2443 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2444 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2445 if (Val != 0) return false;
2449 for (unsigned i = 2; i < 4; ++i) {
2450 SDOperand Arg = N->getOperand(i);
2451 if (Arg.getOpcode() == ISD::UNDEF) continue;
2452 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2453 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2454 if (Val != 2) return false;
2458 // Don't use movshdup if it can be done with a shufps.
2462 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2463 /// a splat of a single element.
2464 static bool isSplatMask(SDNode *N) {
2465 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2467 // This is a splat operation if each element of the permute is the same, and
2468 // if the value doesn't reference the second vector.
2469 unsigned NumElems = N->getNumOperands();
2470 SDOperand ElementBase;
2472 for (; i != NumElems; ++i) {
2473 SDOperand Elt = N->getOperand(i);
2474 if (isa<ConstantSDNode>(Elt)) {
2480 if (!ElementBase.Val)
2483 for (; i != NumElems; ++i) {
2484 SDOperand Arg = N->getOperand(i);
2485 if (Arg.getOpcode() == ISD::UNDEF) continue;
2486 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2487 if (Arg != ElementBase) return false;
2490 // Make sure it is a splat of the first vector operand.
2491 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2494 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2495 /// a splat of a single element and it's a 2 or 4 element mask.
2496 bool X86::isSplatMask(SDNode *N) {
2497 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2499 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2500 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2502 return ::isSplatMask(N);
2505 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2506 /// specifies a splat of zero element.
2507 bool X86::isSplatLoMask(SDNode *N) {
2508 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2510 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2511 if (!isUndefOrEqual(N->getOperand(i), 0))
2516 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2517 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2519 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2520 unsigned NumOperands = N->getNumOperands();
2521 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2523 for (unsigned i = 0; i < NumOperands; ++i) {
2525 SDOperand Arg = N->getOperand(NumOperands-i-1);
2526 if (Arg.getOpcode() != ISD::UNDEF)
2527 Val = cast<ConstantSDNode>(Arg)->getValue();
2528 if (Val >= NumOperands) Val -= NumOperands;
2530 if (i != NumOperands - 1)
2537 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2538 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2540 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2542 // 8 nodes, but we only care about the last 4.
2543 for (unsigned i = 7; i >= 4; --i) {
2545 SDOperand Arg = N->getOperand(i);
2546 if (Arg.getOpcode() != ISD::UNDEF)
2547 Val = cast<ConstantSDNode>(Arg)->getValue();
2556 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2557 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2559 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2561 // 8 nodes, but we only care about the first 4.
2562 for (int i = 3; i >= 0; --i) {
2564 SDOperand Arg = N->getOperand(i);
2565 if (Arg.getOpcode() != ISD::UNDEF)
2566 Val = cast<ConstantSDNode>(Arg)->getValue();
2575 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2576 /// specifies a 8 element shuffle that can be broken into a pair of
2577 /// PSHUFHW and PSHUFLW.
2578 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2579 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2581 if (N->getNumOperands() != 8)
2584 // Lower quadword shuffled.
2585 for (unsigned i = 0; i != 4; ++i) {
2586 SDOperand Arg = N->getOperand(i);
2587 if (Arg.getOpcode() == ISD::UNDEF) continue;
2588 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2589 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2594 // Upper quadword shuffled.
2595 for (unsigned i = 4; i != 8; ++i) {
2596 SDOperand Arg = N->getOperand(i);
2597 if (Arg.getOpcode() == ISD::UNDEF) continue;
2598 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2599 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2600 if (Val < 4 || Val > 7)
2607 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2608 /// values in ther permute mask.
2609 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2610 SDOperand &V2, SDOperand &Mask,
2611 SelectionDAG &DAG) {
2612 MVT::ValueType VT = Op.getValueType();
2613 MVT::ValueType MaskVT = Mask.getValueType();
2614 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
2615 unsigned NumElems = Mask.getNumOperands();
2616 std::vector<SDOperand> MaskVec;
2618 for (unsigned i = 0; i != NumElems; ++i) {
2619 SDOperand Arg = Mask.getOperand(i);
2620 if (Arg.getOpcode() == ISD::UNDEF) {
2621 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2624 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2625 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2627 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2629 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2633 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2634 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2637 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2638 /// match movhlps. The lower half elements should come from upper half of
2639 /// V1 (and in order), and the upper half elements should come from the upper
2640 /// half of V2 (and in order).
2641 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2642 unsigned NumElems = Mask->getNumOperands();
2645 for (unsigned i = 0, e = 2; i != e; ++i)
2646 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2648 for (unsigned i = 2; i != 4; ++i)
2649 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2654 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2655 /// is promoted to a vector.
2656 static inline bool isScalarLoadToVector(SDNode *N) {
2657 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2658 N = N->getOperand(0).Val;
2659 return ISD::isNON_EXTLoad(N);
2664 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2665 /// match movlp{s|d}. The lower half elements should come from lower half of
2666 /// V1 (and in order), and the upper half elements should come from the upper
2667 /// half of V2 (and in order). And since V1 will become the source of the
2668 /// MOVLP, it must be either a vector load or a scalar load to vector.
2669 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2670 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2672 // Is V2 is a vector load, don't do this transformation. We will try to use
2673 // load folding shufps op.
2674 if (ISD::isNON_EXTLoad(V2))
2677 unsigned NumElems = Mask->getNumOperands();
2678 if (NumElems != 2 && NumElems != 4)
2680 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2681 if (!isUndefOrEqual(Mask->getOperand(i), i))
2683 for (unsigned i = NumElems/2; i != NumElems; ++i)
2684 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2689 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2691 static bool isSplatVector(SDNode *N) {
2692 if (N->getOpcode() != ISD::BUILD_VECTOR)
2695 SDOperand SplatValue = N->getOperand(0);
2696 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2697 if (N->getOperand(i) != SplatValue)
2702 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2704 static bool isUndefShuffle(SDNode *N) {
2705 if (N->getOpcode() != ISD::BUILD_VECTOR)
2708 SDOperand V1 = N->getOperand(0);
2709 SDOperand V2 = N->getOperand(1);
2710 SDOperand Mask = N->getOperand(2);
2711 unsigned NumElems = Mask.getNumOperands();
2712 for (unsigned i = 0; i != NumElems; ++i) {
2713 SDOperand Arg = Mask.getOperand(i);
2714 if (Arg.getOpcode() != ISD::UNDEF) {
2715 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2716 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2718 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2725 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2726 /// that point to V2 points to its first element.
2727 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2728 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2730 bool Changed = false;
2731 std::vector<SDOperand> MaskVec;
2732 unsigned NumElems = Mask.getNumOperands();
2733 for (unsigned i = 0; i != NumElems; ++i) {
2734 SDOperand Arg = Mask.getOperand(i);
2735 if (Arg.getOpcode() != ISD::UNDEF) {
2736 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2737 if (Val > NumElems) {
2738 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2742 MaskVec.push_back(Arg);
2746 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2747 &MaskVec[0], MaskVec.size());
2751 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2752 /// operation of specified width.
2753 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2754 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2755 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2757 std::vector<SDOperand> MaskVec;
2758 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2759 for (unsigned i = 1; i != NumElems; ++i)
2760 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2761 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2764 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2765 /// of specified width.
2766 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2767 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2768 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2769 std::vector<SDOperand> MaskVec;
2770 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2771 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2772 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2774 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2777 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2778 /// of specified width.
2779 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2780 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2781 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2782 unsigned Half = NumElems/2;
2783 std::vector<SDOperand> MaskVec;
2784 for (unsigned i = 0; i != Half; ++i) {
2785 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2786 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2788 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2791 /// getZeroVector - Returns a vector of specified type with all zero elements.
2793 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2794 assert(MVT::isVector(VT) && "Expected a vector type");
2795 unsigned NumElems = getVectorNumElements(VT);
2796 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2797 bool isFP = MVT::isFloatingPoint(EVT);
2798 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2799 std::vector<SDOperand> ZeroVec(NumElems, Zero);
2800 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2803 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2805 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2806 SDOperand V1 = Op.getOperand(0);
2807 SDOperand Mask = Op.getOperand(2);
2808 MVT::ValueType VT = Op.getValueType();
2809 unsigned NumElems = Mask.getNumOperands();
2810 Mask = getUnpacklMask(NumElems, DAG);
2811 while (NumElems != 4) {
2812 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2815 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2817 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2818 Mask = getZeroVector(MaskVT, DAG);
2819 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2820 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2821 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2824 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2826 static inline bool isZeroNode(SDOperand Elt) {
2827 return ((isa<ConstantSDNode>(Elt) &&
2828 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2829 (isa<ConstantFPSDNode>(Elt) &&
2830 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2833 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2834 /// vector and zero or undef vector.
2835 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2836 unsigned NumElems, unsigned Idx,
2837 bool isZero, SelectionDAG &DAG) {
2838 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2839 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2840 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2841 SDOperand Zero = DAG.getConstant(0, EVT);
2842 std::vector<SDOperand> MaskVec(NumElems, Zero);
2843 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2844 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2845 &MaskVec[0], MaskVec.size());
2846 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2849 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2851 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2852 unsigned NumNonZero, unsigned NumZero,
2853 SelectionDAG &DAG, TargetLowering &TLI) {
2859 for (unsigned i = 0; i < 16; ++i) {
2860 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2861 if (ThisIsNonZero && First) {
2863 V = getZeroVector(MVT::v8i16, DAG);
2865 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2870 SDOperand ThisElt(0, 0), LastElt(0, 0);
2871 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2872 if (LastIsNonZero) {
2873 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2875 if (ThisIsNonZero) {
2876 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2877 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2878 ThisElt, DAG.getConstant(8, MVT::i8));
2880 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2885 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2886 DAG.getConstant(i/2, TLI.getPointerTy()));
2890 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2893 /// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
2895 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2896 unsigned NumNonZero, unsigned NumZero,
2897 SelectionDAG &DAG, TargetLowering &TLI) {
2903 for (unsigned i = 0; i < 8; ++i) {
2904 bool isNonZero = (NonZeros & (1 << i)) != 0;
2908 V = getZeroVector(MVT::v8i16, DAG);
2910 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2913 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2914 DAG.getConstant(i, TLI.getPointerTy()));
2922 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2923 // All zero's are handled with pxor.
2924 if (ISD::isBuildVectorAllZeros(Op.Val))
2927 // All one's are handled with pcmpeqd.
2928 if (ISD::isBuildVectorAllOnes(Op.Val))
2931 MVT::ValueType VT = Op.getValueType();
2932 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2933 unsigned EVTBits = MVT::getSizeInBits(EVT);
2935 unsigned NumElems = Op.getNumOperands();
2936 unsigned NumZero = 0;
2937 unsigned NumNonZero = 0;
2938 unsigned NonZeros = 0;
2939 std::set<SDOperand> Values;
2940 for (unsigned i = 0; i < NumElems; ++i) {
2941 SDOperand Elt = Op.getOperand(i);
2942 if (Elt.getOpcode() != ISD::UNDEF) {
2944 if (isZeroNode(Elt))
2947 NonZeros |= (1 << i);
2953 if (NumNonZero == 0)
2954 // Must be a mix of zero and undef. Return a zero vector.
2955 return getZeroVector(VT, DAG);
2957 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2958 if (Values.size() == 1)
2961 // Special case for single non-zero element.
2962 if (NumNonZero == 1) {
2963 unsigned Idx = CountTrailingZeros_32(NonZeros);
2964 SDOperand Item = Op.getOperand(Idx);
2965 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2967 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2968 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2971 if (EVTBits == 32) {
2972 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2973 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2975 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2976 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2977 std::vector<SDOperand> MaskVec;
2978 for (unsigned i = 0; i < NumElems; i++)
2979 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2980 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2981 &MaskVec[0], MaskVec.size());
2982 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2983 DAG.getNode(ISD::UNDEF, VT), Mask);
2987 // Let legalizer expand 2-wide build_vector's.
2991 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2993 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2995 if (V.Val) return V;
2998 if (EVTBits == 16) {
2999 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3001 if (V.Val) return V;
3004 // If element VT is == 32 bits, turn it into a number of shuffles.
3005 std::vector<SDOperand> V(NumElems);
3006 if (NumElems == 4 && NumZero > 0) {
3007 for (unsigned i = 0; i < 4; ++i) {
3008 bool isZero = !(NonZeros & (1 << i));
3010 V[i] = getZeroVector(VT, DAG);
3012 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3015 for (unsigned i = 0; i < 2; ++i) {
3016 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3019 V[i] = V[i*2]; // Must be a zero vector.
3022 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3023 getMOVLMask(NumElems, DAG));
3026 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3027 getMOVLMask(NumElems, DAG));
3030 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3031 getUnpacklMask(NumElems, DAG));
3036 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
3037 // clears the upper bits.
3038 // FIXME: we can do the same for v4f32 case when we know both parts of
3039 // the lower half come from scalar_to_vector (loadf32). We should do
3040 // that in post legalizer dag combiner with target specific hooks.
3041 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
3043 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3044 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
3045 std::vector<SDOperand> MaskVec;
3046 bool Reverse = (NonZeros & 0x3) == 2;
3047 for (unsigned i = 0; i < 2; ++i)
3049 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3051 MaskVec.push_back(DAG.getConstant(i, EVT));
3052 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3053 for (unsigned i = 0; i < 2; ++i)
3055 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3057 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3058 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3059 &MaskVec[0], MaskVec.size());
3060 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3063 if (Values.size() > 2) {
3064 // Expand into a number of unpckl*.
3066 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3067 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3068 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3069 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
3070 for (unsigned i = 0; i < NumElems; ++i)
3071 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3073 while (NumElems != 0) {
3074 for (unsigned i = 0; i < NumElems; ++i)
3075 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3086 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3087 SDOperand V1 = Op.getOperand(0);
3088 SDOperand V2 = Op.getOperand(1);
3089 SDOperand PermMask = Op.getOperand(2);
3090 MVT::ValueType VT = Op.getValueType();
3091 unsigned NumElems = PermMask.getNumOperands();
3092 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3093 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3094 bool V1IsSplat = false;
3095 bool V2IsSplat = false;
3097 if (isUndefShuffle(Op.Val))
3098 return DAG.getNode(ISD::UNDEF, VT);
3100 if (isSplatMask(PermMask.Val)) {
3101 if (NumElems <= 4) return Op;
3102 // Promote it to a v4i32 splat.
3103 return PromoteSplat(Op, DAG);
3106 if (X86::isMOVLMask(PermMask.Val))
3107 return (V1IsUndef) ? V2 : Op;
3109 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3110 X86::isMOVSLDUPMask(PermMask.Val) ||
3111 X86::isMOVHLPSMask(PermMask.Val) ||
3112 X86::isMOVHPMask(PermMask.Val) ||
3113 X86::isMOVLPMask(PermMask.Val))
3116 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3117 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3118 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3120 bool Commuted = false;
3121 V1IsSplat = isSplatVector(V1.Val);
3122 V2IsSplat = isSplatVector(V2.Val);
3123 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3124 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3125 std::swap(V1IsSplat, V2IsSplat);
3126 std::swap(V1IsUndef, V2IsUndef);
3130 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3131 if (V2IsUndef) return V1;
3132 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3134 // V2 is a splat, so the mask may be malformed. That is, it may point
3135 // to any V2 element. The instruction selectior won't like this. Get
3136 // a corrected mask and commute to form a proper MOVS{S|D}.
3137 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3138 if (NewMask.Val != PermMask.Val)
3139 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3144 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3145 X86::isUNPCKLMask(PermMask.Val) ||
3146 X86::isUNPCKHMask(PermMask.Val))
3150 // Normalize mask so all entries that point to V2 points to its first
3151 // element then try to match unpck{h|l} again. If match, return a
3152 // new vector_shuffle with the corrected mask.
3153 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3154 if (NewMask.Val != PermMask.Val) {
3155 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3156 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3157 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3158 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3159 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3160 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3165 // Normalize the node to match x86 shuffle ops if needed
3166 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3167 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3170 // Commute is back and try unpck* again.
3171 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3172 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3173 X86::isUNPCKLMask(PermMask.Val) ||
3174 X86::isUNPCKHMask(PermMask.Val))
3178 // If VT is integer, try PSHUF* first, then SHUFP*.
3179 if (MVT::isInteger(VT)) {
3180 if (X86::isPSHUFDMask(PermMask.Val) ||
3181 X86::isPSHUFHWMask(PermMask.Val) ||
3182 X86::isPSHUFLWMask(PermMask.Val)) {
3183 if (V2.getOpcode() != ISD::UNDEF)
3184 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3185 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3189 if (X86::isSHUFPMask(PermMask.Val))
3192 // Handle v8i16 shuffle high / low shuffle node pair.
3193 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
3194 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3195 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3196 std::vector<SDOperand> MaskVec;
3197 for (unsigned i = 0; i != 4; ++i)
3198 MaskVec.push_back(PermMask.getOperand(i));
3199 for (unsigned i = 4; i != 8; ++i)
3200 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3201 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3202 &MaskVec[0], MaskVec.size());
3203 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3205 for (unsigned i = 0; i != 4; ++i)
3206 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3207 for (unsigned i = 4; i != 8; ++i)
3208 MaskVec.push_back(PermMask.getOperand(i));
3209 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
3210 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3213 // Floating point cases in the other order.
3214 if (X86::isSHUFPMask(PermMask.Val))
3216 if (X86::isPSHUFDMask(PermMask.Val) ||
3217 X86::isPSHUFHWMask(PermMask.Val) ||
3218 X86::isPSHUFLWMask(PermMask.Val)) {
3219 if (V2.getOpcode() != ISD::UNDEF)
3220 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3221 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3226 if (NumElems == 4) {
3227 MVT::ValueType MaskVT = PermMask.getValueType();
3228 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
3229 std::vector<std::pair<int, int> > Locs;
3230 Locs.reserve(NumElems);
3231 std::vector<SDOperand> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3232 std::vector<SDOperand> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3235 // If no more than two elements come from either vector. This can be
3236 // implemented with two shuffles. First shuffle gather the elements.
3237 // The second shuffle, which takes the first shuffle as both of its
3238 // vector operands, put the elements into the right order.
3239 for (unsigned i = 0; i != NumElems; ++i) {
3240 SDOperand Elt = PermMask.getOperand(i);
3241 if (Elt.getOpcode() == ISD::UNDEF) {
3242 Locs[i] = std::make_pair(-1, -1);
3244 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3245 if (Val < NumElems) {
3246 Locs[i] = std::make_pair(0, NumLo);
3250 Locs[i] = std::make_pair(1, NumHi);
3251 if (2+NumHi < NumElems)
3252 Mask1[2+NumHi] = Elt;
3257 if (NumLo <= 2 && NumHi <= 2) {
3258 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3259 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3260 &Mask1[0], Mask1.size()));
3261 for (unsigned i = 0; i != NumElems; ++i) {
3262 if (Locs[i].first == -1)
3265 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3266 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3267 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3271 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3272 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3273 &Mask2[0], Mask2.size()));
3276 // Break it into (shuffle shuffle_hi, shuffle_lo).
3278 std::vector<SDOperand> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3279 std::vector<SDOperand> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3280 std::vector<SDOperand> *MaskPtr = &LoMask;
3281 unsigned MaskIdx = 0;
3283 unsigned HiIdx = NumElems/2;
3284 for (unsigned i = 0; i != NumElems; ++i) {
3285 if (i == NumElems/2) {
3291 SDOperand Elt = PermMask.getOperand(i);
3292 if (Elt.getOpcode() == ISD::UNDEF) {
3293 Locs[i] = std::make_pair(-1, -1);
3294 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3295 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3296 (*MaskPtr)[LoIdx] = Elt;
3299 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3300 (*MaskPtr)[HiIdx] = Elt;
3305 SDOperand LoShuffle =
3306 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3307 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3308 &LoMask[0], LoMask.size()));
3309 SDOperand HiShuffle =
3310 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3311 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3312 &HiMask[0], HiMask.size()));
3313 std::vector<SDOperand> MaskOps;
3314 for (unsigned i = 0; i != NumElems; ++i) {
3315 if (Locs[i].first == -1) {
3316 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3318 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3319 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3322 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3323 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3324 &MaskOps[0], MaskOps.size()));
3331 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3332 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3335 MVT::ValueType VT = Op.getValueType();
3336 // TODO: handle v16i8.
3337 if (MVT::getSizeInBits(VT) == 16) {
3338 // Transform it so it match pextrw which produces a 32-bit result.
3339 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3340 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3341 Op.getOperand(0), Op.getOperand(1));
3342 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3343 DAG.getValueType(VT));
3344 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3345 } else if (MVT::getSizeInBits(VT) == 32) {
3346 SDOperand Vec = Op.getOperand(0);
3347 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3350 // SHUFPS the element to the lowest double word, then movss.
3351 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3352 std::vector<SDOperand> IdxVec;
3353 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
3354 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3355 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3356 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3357 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3358 &IdxVec[0], IdxVec.size());
3359 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3360 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3361 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3362 DAG.getConstant(0, getPointerTy()));
3363 } else if (MVT::getSizeInBits(VT) == 64) {
3364 SDOperand Vec = Op.getOperand(0);
3365 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3369 // UNPCKHPD the element to the lowest double word, then movsd.
3370 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3371 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3372 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3373 std::vector<SDOperand> IdxVec;
3374 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
3375 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3376 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3377 &IdxVec[0], IdxVec.size());
3378 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3379 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3380 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3381 DAG.getConstant(0, getPointerTy()));
3388 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3389 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3390 // as its second argument.
3391 MVT::ValueType VT = Op.getValueType();
3392 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
3393 SDOperand N0 = Op.getOperand(0);
3394 SDOperand N1 = Op.getOperand(1);
3395 SDOperand N2 = Op.getOperand(2);
3396 if (MVT::getSizeInBits(BaseVT) == 16) {
3397 if (N1.getValueType() != MVT::i32)
3398 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3399 if (N2.getValueType() != MVT::i32)
3400 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
3401 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3402 } else if (MVT::getSizeInBits(BaseVT) == 32) {
3403 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
3406 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
3407 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3408 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3409 std::vector<SDOperand> MaskVec;
3410 MaskVec.push_back(DAG.getConstant(4, BaseVT));
3411 for (unsigned i = 1; i <= 3; ++i)
3412 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3413 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
3414 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3415 &MaskVec[0], MaskVec.size()));
3417 // Use two pinsrw instructions to insert a 32 bit value.
3419 if (MVT::isFloatingPoint(N1.getValueType())) {
3420 if (ISD::isNON_EXTLoad(N1.Val)) {
3421 // Just load directly from f32mem to GR32.
3422 LoadSDNode *LD = cast<LoadSDNode>(N1);
3423 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
3424 LD->getSrcValue(), LD->getSrcValueOffset());
3426 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
3427 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
3428 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
3429 DAG.getConstant(0, getPointerTy()));
3432 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
3433 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3434 DAG.getConstant(Idx, getPointerTy()));
3435 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
3436 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3437 DAG.getConstant(Idx+1, getPointerTy()));
3438 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3446 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3447 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3448 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3451 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3452 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3453 // one of the above mentioned nodes. It has to be wrapped because otherwise
3454 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3455 // be used to form addressing mode. These wrapped nodes will be selected
3458 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3459 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3460 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3462 CP->getAlignment());
3463 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3464 // With PIC, the address is actually $g + Offset.
3465 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3466 !Subtarget->isPICStyleRIPRel()) {
3467 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3468 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3476 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3477 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3478 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3479 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3480 // With PIC, the address is actually $g + Offset.
3481 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3482 !Subtarget->isPICStyleRIPRel()) {
3483 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3484 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3488 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3489 // load the value at address GV, not the value of GV itself. This means that
3490 // the GlobalAddress must be in the base or index register of the address, not
3491 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3492 // The same applies for external symbols during PIC codegen
3493 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3494 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3500 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3501 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3502 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3503 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3504 // With PIC, the address is actually $g + Offset.
3505 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3506 !Subtarget->isPICStyleRIPRel()) {
3507 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3508 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3515 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3516 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3517 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3518 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3519 // With PIC, the address is actually $g + Offset.
3520 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3521 !Subtarget->isPICStyleRIPRel()) {
3522 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3523 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3530 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3531 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3532 "Not an i64 shift!");
3533 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3534 SDOperand ShOpLo = Op.getOperand(0);
3535 SDOperand ShOpHi = Op.getOperand(1);
3536 SDOperand ShAmt = Op.getOperand(2);
3537 SDOperand Tmp1 = isSRA ?
3538 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3539 DAG.getConstant(0, MVT::i32);
3541 SDOperand Tmp2, Tmp3;
3542 if (Op.getOpcode() == ISD::SHL_PARTS) {
3543 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3544 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3546 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3547 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3550 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3551 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3552 DAG.getConstant(32, MVT::i8));
3553 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3554 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3557 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3559 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3560 SmallVector<SDOperand, 4> Ops;
3561 if (Op.getOpcode() == ISD::SHL_PARTS) {
3562 Ops.push_back(Tmp2);
3563 Ops.push_back(Tmp3);
3565 Ops.push_back(InFlag);
3566 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3567 InFlag = Hi.getValue(1);
3570 Ops.push_back(Tmp3);
3571 Ops.push_back(Tmp1);
3573 Ops.push_back(InFlag);
3574 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3576 Ops.push_back(Tmp2);
3577 Ops.push_back(Tmp3);
3579 Ops.push_back(InFlag);
3580 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3581 InFlag = Lo.getValue(1);
3584 Ops.push_back(Tmp3);
3585 Ops.push_back(Tmp1);
3587 Ops.push_back(InFlag);
3588 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3591 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3595 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3598 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3599 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3600 Op.getOperand(0).getValueType() >= MVT::i16 &&
3601 "Unknown SINT_TO_FP to lower!");
3604 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3605 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3606 MachineFunction &MF = DAG.getMachineFunction();
3607 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3608 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3609 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3610 StackSlot, NULL, 0);
3613 std::vector<MVT::ValueType> Tys;
3614 Tys.push_back(MVT::f64);
3615 Tys.push_back(MVT::Other);
3616 if (X86ScalarSSE) Tys.push_back(MVT::Flag);
3617 std::vector<SDOperand> Ops;
3618 Ops.push_back(Chain);
3619 Ops.push_back(StackSlot);
3620 Ops.push_back(DAG.getValueType(SrcVT));
3621 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3622 Tys, &Ops[0], Ops.size());
3625 Chain = Result.getValue(1);
3626 SDOperand InFlag = Result.getValue(2);
3628 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3629 // shouldn't be necessary except that RFP cannot be live across
3630 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3631 MachineFunction &MF = DAG.getMachineFunction();
3632 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3633 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3634 std::vector<MVT::ValueType> Tys;
3635 Tys.push_back(MVT::Other);
3636 std::vector<SDOperand> Ops;
3637 Ops.push_back(Chain);
3638 Ops.push_back(Result);
3639 Ops.push_back(StackSlot);
3640 Ops.push_back(DAG.getValueType(Op.getValueType()));
3641 Ops.push_back(InFlag);
3642 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3643 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3649 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3650 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3651 "Unknown FP_TO_SINT to lower!");
3652 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3654 MachineFunction &MF = DAG.getMachineFunction();
3655 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3656 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3657 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3660 switch (Op.getValueType()) {
3661 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3662 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3663 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3664 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3667 SDOperand Chain = DAG.getEntryNode();
3668 SDOperand Value = Op.getOperand(0);
3670 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3671 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3672 std::vector<MVT::ValueType> Tys;
3673 Tys.push_back(MVT::f64);
3674 Tys.push_back(MVT::Other);
3675 std::vector<SDOperand> Ops;
3676 Ops.push_back(Chain);
3677 Ops.push_back(StackSlot);
3678 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType()));
3679 Value = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size());
3680 Chain = Value.getValue(1);
3681 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3682 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3685 // Build the FP_TO_INT*_IN_MEM
3686 std::vector<SDOperand> Ops;
3687 Ops.push_back(Chain);
3688 Ops.push_back(Value);
3689 Ops.push_back(StackSlot);
3690 SDOperand FIST = DAG.getNode(Opc, MVT::Other, &Ops[0], Ops.size());
3693 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3696 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3697 MVT::ValueType VT = Op.getValueType();
3698 const Type *OpNTy = MVT::getTypeForValueType(VT);
3699 std::vector<Constant*> CV;
3700 if (VT == MVT::f64) {
3701 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3702 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3704 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3705 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3706 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3707 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3709 Constant *CS = ConstantStruct::get(CV);
3710 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3711 std::vector<MVT::ValueType> Tys;
3713 Tys.push_back(MVT::Other);
3714 SmallVector<SDOperand, 3> Ops;
3715 Ops.push_back(DAG.getEntryNode());
3716 Ops.push_back(CPIdx);
3717 Ops.push_back(DAG.getSrcValue(NULL));
3718 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3719 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3722 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3723 MVT::ValueType VT = Op.getValueType();
3724 const Type *OpNTy = MVT::getTypeForValueType(VT);
3725 std::vector<Constant*> CV;
3726 if (VT == MVT::f64) {
3727 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3728 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3730 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3731 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3732 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3733 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3735 Constant *CS = ConstantStruct::get(CV);
3736 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3737 std::vector<MVT::ValueType> Tys;
3739 Tys.push_back(MVT::Other);
3740 SmallVector<SDOperand, 3> Ops;
3741 Ops.push_back(DAG.getEntryNode());
3742 Ops.push_back(CPIdx);
3743 Ops.push_back(DAG.getSrcValue(NULL));
3744 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3745 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3748 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3749 SDOperand Op0 = Op.getOperand(0);
3750 SDOperand Op1 = Op.getOperand(1);
3751 MVT::ValueType VT = Op.getValueType();
3752 MVT::ValueType SrcVT = Op1.getValueType();
3753 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3755 // If second operand is smaller, extend it first.
3756 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3757 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3761 // First get the sign bit of second operand.
3762 std::vector<Constant*> CV;
3763 if (SrcVT == MVT::f64) {
3764 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63)));
3765 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3767 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31)));
3768 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3769 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3770 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3772 Constant *CS = ConstantStruct::get(CV);
3773 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3774 std::vector<MVT::ValueType> Tys;
3775 Tys.push_back(SrcVT);
3776 Tys.push_back(MVT::Other);
3777 SmallVector<SDOperand, 3> Ops;
3778 Ops.push_back(DAG.getEntryNode());
3779 Ops.push_back(CPIdx);
3780 Ops.push_back(DAG.getSrcValue(NULL));
3781 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3782 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3784 // Shift sign bit right or left if the two operands have different types.
3785 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3786 // Op0 is MVT::f32, Op1 is MVT::f64.
3787 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3788 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3789 DAG.getConstant(32, MVT::i32));
3790 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3791 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3792 DAG.getConstant(0, getPointerTy()));
3795 // Clear first operand sign bit.
3797 if (VT == MVT::f64) {
3798 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63))));
3799 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3801 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31))));
3802 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3803 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3804 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3806 CS = ConstantStruct::get(CV);
3807 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3810 Tys.push_back(MVT::Other);
3812 Ops.push_back(DAG.getEntryNode());
3813 Ops.push_back(CPIdx);
3814 Ops.push_back(DAG.getSrcValue(NULL));
3815 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3816 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3818 // Or the value with the sign bit.
3819 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3822 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3824 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3826 SDOperand Op0 = Op.getOperand(0);
3827 SDOperand Op1 = Op.getOperand(1);
3828 SDOperand CC = Op.getOperand(2);
3829 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3830 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3831 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3832 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3835 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3837 SDOperand Ops1[] = { Chain, Op0, Op1 };
3838 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3839 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3840 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3843 assert(isFP && "Illegal integer SetCC!");
3845 SDOperand COps[] = { Chain, Op0, Op1 };
3846 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3848 switch (SetCCOpcode) {
3849 default: assert(false && "Illegal floating point SetCC!");
3850 case ISD::SETOEQ: { // !PF & ZF
3851 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3852 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3853 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3855 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3856 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3858 case ISD::SETUNE: { // PF | !ZF
3859 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3860 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3861 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3863 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3864 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3869 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3870 bool addTest = true;
3871 SDOperand Chain = DAG.getEntryNode();
3872 SDOperand Cond = Op.getOperand(0);
3874 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3876 if (Cond.getOpcode() == ISD::SETCC)
3877 Cond = LowerSETCC(Cond, DAG, Chain);
3879 if (Cond.getOpcode() == X86ISD::SETCC) {
3880 CC = Cond.getOperand(0);
3882 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3883 // (since flag operand cannot be shared). Use it as the condition setting
3884 // operand in place of the X86ISD::SETCC.
3885 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3886 // to use a test instead of duplicating the X86ISD::CMP (for register
3887 // pressure reason)?
3888 SDOperand Cmp = Cond.getOperand(1);
3889 unsigned Opc = Cmp.getOpcode();
3890 bool IllegalFPCMov = !X86ScalarSSE &&
3891 MVT::isFloatingPoint(Op.getValueType()) &&
3892 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3893 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3895 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3896 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3902 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3903 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3904 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3907 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3908 SmallVector<SDOperand, 4> Ops;
3909 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3910 // condition is true.
3911 Ops.push_back(Op.getOperand(2));
3912 Ops.push_back(Op.getOperand(1));
3914 Ops.push_back(Cond.getValue(1));
3915 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3918 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3919 bool addTest = true;
3920 SDOperand Chain = Op.getOperand(0);
3921 SDOperand Cond = Op.getOperand(1);
3922 SDOperand Dest = Op.getOperand(2);
3924 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3926 if (Cond.getOpcode() == ISD::SETCC)
3927 Cond = LowerSETCC(Cond, DAG, Chain);
3929 if (Cond.getOpcode() == X86ISD::SETCC) {
3930 CC = Cond.getOperand(0);
3932 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3933 // (since flag operand cannot be shared). Use it as the condition setting
3934 // operand in place of the X86ISD::SETCC.
3935 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3936 // to use a test instead of duplicating the X86ISD::CMP (for register
3937 // pressure reason)?
3938 SDOperand Cmp = Cond.getOperand(1);
3939 unsigned Opc = Cmp.getOpcode();
3940 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3941 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3942 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3948 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3949 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3950 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3952 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3953 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3956 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3957 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3959 if (Subtarget->is64Bit())
3960 return LowerX86_64CCCCallTo(Op, DAG);
3962 switch (CallingConv) {
3964 assert(0 && "Unsupported calling convention");
3965 case CallingConv::Fast:
3967 return LowerFastCCCallTo(Op, DAG);
3970 case CallingConv::C:
3971 return LowerCCCCallTo(Op, DAG);
3972 case CallingConv::X86_StdCall:
3973 return LowerCCCCallTo(Op, DAG, true);
3974 case CallingConv::X86_FastCall:
3975 return LowerFastCCCallTo(Op, DAG, true);
3979 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
3982 switch(Op.getNumOperands()) {
3984 assert(0 && "Do not know how to return this many arguments!");
3986 case 1: // ret void.
3987 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
3988 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
3990 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
3992 if (MVT::isVector(ArgVT) ||
3993 (Subtarget->is64Bit() && MVT::isFloatingPoint(ArgVT))) {
3994 // Integer or FP vector result -> XMM0.
3995 if (DAG.getMachineFunction().liveout_empty())
3996 DAG.getMachineFunction().addLiveOut(X86::XMM0);
3997 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::XMM0, Op.getOperand(1),
3999 } else if (MVT::isInteger(ArgVT)) {
4000 // Integer result -> EAX / RAX.
4001 // The C calling convention guarantees the return value has been
4002 // promoted to at least MVT::i32. The X86-64 ABI doesn't require the
4003 // value to be promoted MVT::i64. So we don't have to extend it to
4004 // 64-bit. Return the value in EAX, but mark RAX as liveout.
4005 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
4006 if (DAG.getMachineFunction().liveout_empty())
4007 DAG.getMachineFunction().addLiveOut(Reg);
4009 Reg = (ArgVT == MVT::i64) ? X86::RAX : X86::EAX;
4010 Copy = DAG.getCopyToReg(Op.getOperand(0), Reg, Op.getOperand(1),
4012 } else if (!X86ScalarSSE) {
4013 // FP return with fp-stack value.
4014 if (DAG.getMachineFunction().liveout_empty())
4015 DAG.getMachineFunction().addLiveOut(X86::ST0);
4017 std::vector<MVT::ValueType> Tys;
4018 Tys.push_back(MVT::Other);
4019 Tys.push_back(MVT::Flag);
4020 std::vector<SDOperand> Ops;
4021 Ops.push_back(Op.getOperand(0));
4022 Ops.push_back(Op.getOperand(1));
4023 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size());
4025 // FP return with ScalarSSE (return on fp-stack).
4026 if (DAG.getMachineFunction().liveout_empty())
4027 DAG.getMachineFunction().addLiveOut(X86::ST0);
4030 SDOperand Chain = Op.getOperand(0);
4031 SDOperand Value = Op.getOperand(1);
4033 if (ISD::isNON_EXTLoad(Value.Val) &&
4034 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
4035 Chain = Value.getOperand(0);
4036 MemLoc = Value.getOperand(1);
4038 // Spill the value to memory and reload it into top of stack.
4039 unsigned Size = MVT::getSizeInBits(ArgVT)/8;
4040 MachineFunction &MF = DAG.getMachineFunction();
4041 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4042 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
4043 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
4045 std::vector<MVT::ValueType> Tys;
4046 Tys.push_back(MVT::f64);
4047 Tys.push_back(MVT::Other);
4048 std::vector<SDOperand> Ops;
4049 Ops.push_back(Chain);
4050 Ops.push_back(MemLoc);
4051 Ops.push_back(DAG.getValueType(ArgVT));
4052 Copy = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size());
4054 Tys.push_back(MVT::Other);
4055 Tys.push_back(MVT::Flag);
4057 Ops.push_back(Copy.getValue(1));
4058 Ops.push_back(Copy);
4059 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size());
4064 unsigned Reg1 = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
4065 unsigned Reg2 = Subtarget->is64Bit() ? X86::RDX : X86::EDX;
4066 if (DAG.getMachineFunction().liveout_empty()) {
4067 DAG.getMachineFunction().addLiveOut(Reg1);
4068 DAG.getMachineFunction().addLiveOut(Reg2);
4071 Copy = DAG.getCopyToReg(Op.getOperand(0), Reg2, Op.getOperand(3),
4073 Copy = DAG.getCopyToReg(Copy, Reg1, Op.getOperand(1), Copy.getValue(1));
4077 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
4078 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
4083 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
4084 MachineFunction &MF = DAG.getMachineFunction();
4085 const Function* Fn = MF.getFunction();
4086 if (Fn->hasExternalLinkage() &&
4087 Subtarget->isTargetCygMing() &&
4088 Fn->getName() == "main")
4089 MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true);
4091 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4092 if (Subtarget->is64Bit())
4093 return LowerX86_64CCCArguments(Op, DAG);
4097 assert(0 && "Unsupported calling convention");
4098 case CallingConv::Fast:
4100 return LowerFastCCArguments(Op, DAG);
4103 case CallingConv::C:
4104 return LowerCCCArguments(Op, DAG);
4105 case CallingConv::X86_StdCall:
4106 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(StdCall);
4107 return LowerCCCArguments(Op, DAG, true);
4108 case CallingConv::X86_FastCall:
4109 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall);
4110 return LowerFastCCArguments(Op, DAG, true);
4114 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4115 SDOperand InFlag(0, 0);
4116 SDOperand Chain = Op.getOperand(0);
4118 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4119 if (Align == 0) Align = 1;
4121 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4122 // If not DWORD aligned, call memset if size is less than the threshold.
4123 // It knows how to align to the right boundary first.
4124 if ((Align & 3) != 0 ||
4125 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
4126 MVT::ValueType IntPtr = getPointerTy();
4127 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4128 TargetLowering::ArgListTy Args;
4129 TargetLowering::ArgListEntry Entry;
4130 Entry.Node = Op.getOperand(1);
4131 Entry.Ty = IntPtrTy;
4132 Entry.isSigned = false;
4133 Entry.isInReg = false;
4134 Entry.isSRet = false;
4135 Args.push_back(Entry);
4136 // Extend the unsigned i8 argument to be an int value for the call.
4137 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4138 Entry.Ty = IntPtrTy;
4139 Entry.isSigned = false;
4140 Entry.isInReg = false;
4141 Entry.isSRet = false;
4142 Args.push_back(Entry);
4143 Entry.Node = Op.getOperand(3);
4144 Args.push_back(Entry);
4145 std::pair<SDOperand,SDOperand> CallResult =
4146 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4147 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
4148 return CallResult.second;
4153 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4154 unsigned BytesLeft = 0;
4155 bool TwoRepStos = false;
4158 uint64_t Val = ValC->getValue() & 255;
4160 // If the value is a constant, then we can potentially use larger sets.
4161 switch (Align & 3) {
4162 case 2: // WORD aligned
4165 Val = (Val << 8) | Val;
4167 case 0: // DWORD aligned
4170 Val = (Val << 8) | Val;
4171 Val = (Val << 16) | Val;
4172 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4175 Val = (Val << 32) | Val;
4178 default: // Byte aligned
4181 Count = Op.getOperand(3);
4185 if (AVT > MVT::i8) {
4187 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4188 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4189 BytesLeft = I->getValue() % UBytes;
4191 assert(AVT >= MVT::i32 &&
4192 "Do not use rep;stos if not at least DWORD aligned");
4193 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4194 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4199 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4201 InFlag = Chain.getValue(1);
4204 Count = Op.getOperand(3);
4205 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4206 InFlag = Chain.getValue(1);
4209 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4211 InFlag = Chain.getValue(1);
4212 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4213 Op.getOperand(1), InFlag);
4214 InFlag = Chain.getValue(1);
4216 std::vector<MVT::ValueType> Tys;
4217 Tys.push_back(MVT::Other);
4218 Tys.push_back(MVT::Flag);
4219 std::vector<SDOperand> Ops;
4220 Ops.push_back(Chain);
4221 Ops.push_back(DAG.getValueType(AVT));
4222 Ops.push_back(InFlag);
4223 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4226 InFlag = Chain.getValue(1);
4227 Count = Op.getOperand(3);
4228 MVT::ValueType CVT = Count.getValueType();
4229 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4230 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4231 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4233 InFlag = Chain.getValue(1);
4235 Tys.push_back(MVT::Other);
4236 Tys.push_back(MVT::Flag);
4238 Ops.push_back(Chain);
4239 Ops.push_back(DAG.getValueType(MVT::i8));
4240 Ops.push_back(InFlag);
4241 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4242 } else if (BytesLeft) {
4243 // Issue stores for the last 1 - 7 bytes.
4245 unsigned Val = ValC->getValue() & 255;
4246 unsigned Offset = I->getValue() - BytesLeft;
4247 SDOperand DstAddr = Op.getOperand(1);
4248 MVT::ValueType AddrVT = DstAddr.getValueType();
4249 if (BytesLeft >= 4) {
4250 Val = (Val << 8) | Val;
4251 Val = (Val << 16) | Val;
4252 Value = DAG.getConstant(Val, MVT::i32);
4253 Chain = DAG.getStore(Chain, Value,
4254 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4255 DAG.getConstant(Offset, AddrVT)),
4260 if (BytesLeft >= 2) {
4261 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4262 Chain = DAG.getStore(Chain, Value,
4263 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4264 DAG.getConstant(Offset, AddrVT)),
4269 if (BytesLeft == 1) {
4270 Value = DAG.getConstant(Val, MVT::i8);
4271 Chain = DAG.getStore(Chain, Value,
4272 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4273 DAG.getConstant(Offset, AddrVT)),
4281 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
4282 SDOperand Chain = Op.getOperand(0);
4284 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4285 if (Align == 0) Align = 1;
4287 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4288 // If not DWORD aligned, call memcpy if size is less than the threshold.
4289 // It knows how to align to the right boundary first.
4290 if ((Align & 3) != 0 ||
4291 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
4292 MVT::ValueType IntPtr = getPointerTy();
4293 TargetLowering::ArgListTy Args;
4294 TargetLowering::ArgListEntry Entry;
4295 Entry.Ty = getTargetData()->getIntPtrType();
4296 Entry.isSigned = false;
4297 Entry.isInReg = false;
4298 Entry.isSRet = false;
4299 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
4300 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
4301 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
4302 std::pair<SDOperand,SDOperand> CallResult =
4303 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4304 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
4305 return CallResult.second;
4310 unsigned BytesLeft = 0;
4311 bool TwoRepMovs = false;
4312 switch (Align & 3) {
4313 case 2: // WORD aligned
4316 case 0: // DWORD aligned
4318 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4321 default: // Byte aligned
4323 Count = Op.getOperand(3);
4327 if (AVT > MVT::i8) {
4329 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4330 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4331 BytesLeft = I->getValue() % UBytes;
4333 assert(AVT >= MVT::i32 &&
4334 "Do not use rep;movs if not at least DWORD aligned");
4335 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4336 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4341 SDOperand InFlag(0, 0);
4342 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4344 InFlag = Chain.getValue(1);
4345 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4346 Op.getOperand(1), InFlag);
4347 InFlag = Chain.getValue(1);
4348 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4349 Op.getOperand(2), InFlag);
4350 InFlag = Chain.getValue(1);
4352 std::vector<MVT::ValueType> Tys;
4353 Tys.push_back(MVT::Other);
4354 Tys.push_back(MVT::Flag);
4355 std::vector<SDOperand> Ops;
4356 Ops.push_back(Chain);
4357 Ops.push_back(DAG.getValueType(AVT));
4358 Ops.push_back(InFlag);
4359 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4362 InFlag = Chain.getValue(1);
4363 Count = Op.getOperand(3);
4364 MVT::ValueType CVT = Count.getValueType();
4365 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4366 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4367 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4369 InFlag = Chain.getValue(1);
4371 Tys.push_back(MVT::Other);
4372 Tys.push_back(MVT::Flag);
4374 Ops.push_back(Chain);
4375 Ops.push_back(DAG.getValueType(MVT::i8));
4376 Ops.push_back(InFlag);
4377 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4378 } else if (BytesLeft) {
4379 // Issue loads and stores for the last 1 - 7 bytes.
4380 unsigned Offset = I->getValue() - BytesLeft;
4381 SDOperand DstAddr = Op.getOperand(1);
4382 MVT::ValueType DstVT = DstAddr.getValueType();
4383 SDOperand SrcAddr = Op.getOperand(2);
4384 MVT::ValueType SrcVT = SrcAddr.getValueType();
4386 if (BytesLeft >= 4) {
4387 Value = DAG.getLoad(MVT::i32, Chain,
4388 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4389 DAG.getConstant(Offset, SrcVT)),
4391 Chain = Value.getValue(1);
4392 Chain = DAG.getStore(Chain, Value,
4393 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4394 DAG.getConstant(Offset, DstVT)),
4399 if (BytesLeft >= 2) {
4400 Value = DAG.getLoad(MVT::i16, Chain,
4401 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4402 DAG.getConstant(Offset, SrcVT)),
4404 Chain = Value.getValue(1);
4405 Chain = DAG.getStore(Chain, Value,
4406 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4407 DAG.getConstant(Offset, DstVT)),
4413 if (BytesLeft == 1) {
4414 Value = DAG.getLoad(MVT::i8, Chain,
4415 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4416 DAG.getConstant(Offset, SrcVT)),
4418 Chain = Value.getValue(1);
4419 Chain = DAG.getStore(Chain, Value,
4420 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4421 DAG.getConstant(Offset, DstVT)),
4430 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
4431 std::vector<MVT::ValueType> Tys;
4432 Tys.push_back(MVT::Other);
4433 Tys.push_back(MVT::Flag);
4434 std::vector<SDOperand> Ops;
4435 Ops.push_back(Op.getOperand(0));
4436 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &Ops[0], Ops.size());
4438 if (Subtarget->is64Bit()) {
4439 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4440 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
4441 MVT::i64, Copy1.getValue(2));
4442 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
4443 DAG.getConstant(32, MVT::i8));
4444 Ops.push_back(DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp));
4445 Ops.push_back(Copy2.getValue(1));
4447 Tys[1] = MVT::Other;
4449 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4450 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
4451 MVT::i32, Copy1.getValue(2));
4452 Ops.push_back(Copy1);
4453 Ops.push_back(Copy2);
4454 Ops.push_back(Copy2.getValue(1));
4455 Tys[0] = Tys[1] = MVT::i32;
4456 Tys.push_back(MVT::Other);
4458 return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size());
4461 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4462 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4464 if (!Subtarget->is64Bit()) {
4465 // vastart just stores the address of the VarArgsFrameIndex slot into the
4466 // memory location argument.
4467 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4468 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4473 // gp_offset (0 - 6 * 8)
4474 // fp_offset (48 - 48 + 8 * 16)
4475 // overflow_arg_area (point to parameters coming in memory).
4477 std::vector<SDOperand> MemOps;
4478 SDOperand FIN = Op.getOperand(1);
4480 SDOperand Store = DAG.getStore(Op.getOperand(0),
4481 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4482 FIN, SV->getValue(), SV->getOffset());
4483 MemOps.push_back(Store);
4486 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4487 DAG.getConstant(4, getPointerTy()));
4488 Store = DAG.getStore(Op.getOperand(0),
4489 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4490 FIN, SV->getValue(), SV->getOffset());
4491 MemOps.push_back(Store);
4493 // Store ptr to overflow_arg_area
4494 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4495 DAG.getConstant(4, getPointerTy()));
4496 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4497 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4499 MemOps.push_back(Store);
4501 // Store ptr to reg_save_area.
4502 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4503 DAG.getConstant(8, getPointerTy()));
4504 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4505 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4507 MemOps.push_back(Store);
4508 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4512 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4513 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4515 default: return SDOperand(); // Don't custom lower most intrinsics.
4516 // Comparison intrinsics.
4517 case Intrinsic::x86_sse_comieq_ss:
4518 case Intrinsic::x86_sse_comilt_ss:
4519 case Intrinsic::x86_sse_comile_ss:
4520 case Intrinsic::x86_sse_comigt_ss:
4521 case Intrinsic::x86_sse_comige_ss:
4522 case Intrinsic::x86_sse_comineq_ss:
4523 case Intrinsic::x86_sse_ucomieq_ss:
4524 case Intrinsic::x86_sse_ucomilt_ss:
4525 case Intrinsic::x86_sse_ucomile_ss:
4526 case Intrinsic::x86_sse_ucomigt_ss:
4527 case Intrinsic::x86_sse_ucomige_ss:
4528 case Intrinsic::x86_sse_ucomineq_ss:
4529 case Intrinsic::x86_sse2_comieq_sd:
4530 case Intrinsic::x86_sse2_comilt_sd:
4531 case Intrinsic::x86_sse2_comile_sd:
4532 case Intrinsic::x86_sse2_comigt_sd:
4533 case Intrinsic::x86_sse2_comige_sd:
4534 case Intrinsic::x86_sse2_comineq_sd:
4535 case Intrinsic::x86_sse2_ucomieq_sd:
4536 case Intrinsic::x86_sse2_ucomilt_sd:
4537 case Intrinsic::x86_sse2_ucomile_sd:
4538 case Intrinsic::x86_sse2_ucomigt_sd:
4539 case Intrinsic::x86_sse2_ucomige_sd:
4540 case Intrinsic::x86_sse2_ucomineq_sd: {
4542 ISD::CondCode CC = ISD::SETCC_INVALID;
4545 case Intrinsic::x86_sse_comieq_ss:
4546 case Intrinsic::x86_sse2_comieq_sd:
4550 case Intrinsic::x86_sse_comilt_ss:
4551 case Intrinsic::x86_sse2_comilt_sd:
4555 case Intrinsic::x86_sse_comile_ss:
4556 case Intrinsic::x86_sse2_comile_sd:
4560 case Intrinsic::x86_sse_comigt_ss:
4561 case Intrinsic::x86_sse2_comigt_sd:
4565 case Intrinsic::x86_sse_comige_ss:
4566 case Intrinsic::x86_sse2_comige_sd:
4570 case Intrinsic::x86_sse_comineq_ss:
4571 case Intrinsic::x86_sse2_comineq_sd:
4575 case Intrinsic::x86_sse_ucomieq_ss:
4576 case Intrinsic::x86_sse2_ucomieq_sd:
4577 Opc = X86ISD::UCOMI;
4580 case Intrinsic::x86_sse_ucomilt_ss:
4581 case Intrinsic::x86_sse2_ucomilt_sd:
4582 Opc = X86ISD::UCOMI;
4585 case Intrinsic::x86_sse_ucomile_ss:
4586 case Intrinsic::x86_sse2_ucomile_sd:
4587 Opc = X86ISD::UCOMI;
4590 case Intrinsic::x86_sse_ucomigt_ss:
4591 case Intrinsic::x86_sse2_ucomigt_sd:
4592 Opc = X86ISD::UCOMI;
4595 case Intrinsic::x86_sse_ucomige_ss:
4596 case Intrinsic::x86_sse2_ucomige_sd:
4597 Opc = X86ISD::UCOMI;
4600 case Intrinsic::x86_sse_ucomineq_ss:
4601 case Intrinsic::x86_sse2_ucomineq_sd:
4602 Opc = X86ISD::UCOMI;
4608 SDOperand LHS = Op.getOperand(1);
4609 SDOperand RHS = Op.getOperand(2);
4610 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4612 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4613 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4614 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4615 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4616 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4617 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4618 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4623 /// LowerOperation - Provide custom lowering hooks for some operations.
4625 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4626 switch (Op.getOpcode()) {
4627 default: assert(0 && "Should not custom lower this!");
4628 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4629 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4630 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4631 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4632 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4633 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4634 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4635 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4636 case ISD::SHL_PARTS:
4637 case ISD::SRA_PARTS:
4638 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4639 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4640 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4641 case ISD::FABS: return LowerFABS(Op, DAG);
4642 case ISD::FNEG: return LowerFNEG(Op, DAG);
4643 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4644 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4645 case ISD::SELECT: return LowerSELECT(Op, DAG);
4646 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4647 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4648 case ISD::CALL: return LowerCALL(Op, DAG);
4649 case ISD::RET: return LowerRET(Op, DAG);
4650 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4651 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4652 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4653 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4654 case ISD::VASTART: return LowerVASTART(Op, DAG);
4655 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4659 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4661 default: return NULL;
4662 case X86ISD::SHLD: return "X86ISD::SHLD";
4663 case X86ISD::SHRD: return "X86ISD::SHRD";
4664 case X86ISD::FAND: return "X86ISD::FAND";
4665 case X86ISD::FOR: return "X86ISD::FOR";
4666 case X86ISD::FXOR: return "X86ISD::FXOR";
4667 case X86ISD::FSRL: return "X86ISD::FSRL";
4668 case X86ISD::FILD: return "X86ISD::FILD";
4669 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4670 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4671 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4672 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4673 case X86ISD::FLD: return "X86ISD::FLD";
4674 case X86ISD::FST: return "X86ISD::FST";
4675 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4676 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4677 case X86ISD::CALL: return "X86ISD::CALL";
4678 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4679 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4680 case X86ISD::CMP: return "X86ISD::CMP";
4681 case X86ISD::COMI: return "X86ISD::COMI";
4682 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4683 case X86ISD::SETCC: return "X86ISD::SETCC";
4684 case X86ISD::CMOV: return "X86ISD::CMOV";
4685 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4686 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4687 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4688 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4689 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4690 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4691 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4692 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4693 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4694 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4695 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4696 case X86ISD::FMAX: return "X86ISD::FMAX";
4697 case X86ISD::FMIN: return "X86ISD::FMIN";
4701 /// isLegalAddressImmediate - Return true if the integer value or
4702 /// GlobalValue can be used as the offset of the target addressing mode.
4703 bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
4704 // X86 allows a sign-extended 32-bit immediate field.
4705 return (V > -(1LL << 32) && V < (1LL << 32)-1);
4708 bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
4709 // In 64-bit mode, GV is 64-bit so it won't fit in the 32-bit displacement
4710 // field unless we are in small code model.
4711 if (Subtarget->is64Bit() &&
4712 getTargetMachine().getCodeModel() != CodeModel::Small)
4715 return (!Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false));
4718 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4719 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4720 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4721 /// are assumed to be legal.
4723 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4724 // Only do shuffles on 128-bit vector types for now.
4725 if (MVT::getSizeInBits(VT) == 64) return false;
4726 return (Mask.Val->getNumOperands() <= 4 ||
4727 isSplatMask(Mask.Val) ||
4728 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4729 X86::isUNPCKLMask(Mask.Val) ||
4730 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4731 X86::isUNPCKHMask(Mask.Val));
4734 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4736 SelectionDAG &DAG) const {
4737 unsigned NumElts = BVOps.size();
4738 // Only do shuffles on 128-bit vector types for now.
4739 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4740 if (NumElts == 2) return true;
4742 return (isMOVLMask(BVOps) || isCommutedMOVL(BVOps, true) ||
4743 isSHUFPMask(BVOps) || isCommutedSHUFP(BVOps));
4748 //===----------------------------------------------------------------------===//
4749 // X86 Scheduler Hooks
4750 //===----------------------------------------------------------------------===//
4753 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4754 MachineBasicBlock *BB) {
4755 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4756 switch (MI->getOpcode()) {
4757 default: assert(false && "Unexpected instr type to insert");
4758 case X86::CMOV_FR32:
4759 case X86::CMOV_FR64:
4760 case X86::CMOV_V4F32:
4761 case X86::CMOV_V2F64:
4762 case X86::CMOV_V2I64: {
4763 // To "insert" a SELECT_CC instruction, we actually have to insert the
4764 // diamond control-flow pattern. The incoming instruction knows the
4765 // destination vreg to set, the condition code register to branch on, the
4766 // true/false values to select between, and a branch opcode to use.
4767 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4768 ilist<MachineBasicBlock>::iterator It = BB;
4774 // cmpTY ccX, r1, r2
4776 // fallthrough --> copy0MBB
4777 MachineBasicBlock *thisMBB = BB;
4778 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4779 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4781 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4782 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4783 MachineFunction *F = BB->getParent();
4784 F->getBasicBlockList().insert(It, copy0MBB);
4785 F->getBasicBlockList().insert(It, sinkMBB);
4786 // Update machine-CFG edges by first adding all successors of the current
4787 // block to the new block which will contain the Phi node for the select.
4788 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4789 e = BB->succ_end(); i != e; ++i)
4790 sinkMBB->addSuccessor(*i);
4791 // Next, remove all successors of the current block, and add the true
4792 // and fallthrough blocks as its successors.
4793 while(!BB->succ_empty())
4794 BB->removeSuccessor(BB->succ_begin());
4795 BB->addSuccessor(copy0MBB);
4796 BB->addSuccessor(sinkMBB);
4799 // %FalseValue = ...
4800 // # fallthrough to sinkMBB
4803 // Update machine-CFG edges
4804 BB->addSuccessor(sinkMBB);
4807 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4810 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4811 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4812 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4814 delete MI; // The pseudo instruction is gone now.
4818 case X86::FP_TO_INT16_IN_MEM:
4819 case X86::FP_TO_INT32_IN_MEM:
4820 case X86::FP_TO_INT64_IN_MEM: {
4821 // Change the floating point control register to use "round towards zero"
4822 // mode when truncating to an integer value.
4823 MachineFunction *F = BB->getParent();
4824 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4825 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4827 // Load the old value of the high byte of the control word...
4829 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4830 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4832 // Set the high part to be round to zero...
4833 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4836 // Reload the modified control word now...
4837 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4839 // Restore the memory image of control word to original value
4840 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4843 // Get the X86 opcode to use.
4845 switch (MI->getOpcode()) {
4846 default: assert(0 && "illegal opcode!");
4847 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
4848 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
4849 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
4853 MachineOperand &Op = MI->getOperand(0);
4854 if (Op.isRegister()) {
4855 AM.BaseType = X86AddressMode::RegBase;
4856 AM.Base.Reg = Op.getReg();
4858 AM.BaseType = X86AddressMode::FrameIndexBase;
4859 AM.Base.FrameIndex = Op.getFrameIndex();
4861 Op = MI->getOperand(1);
4862 if (Op.isImmediate())
4863 AM.Scale = Op.getImm();
4864 Op = MI->getOperand(2);
4865 if (Op.isImmediate())
4866 AM.IndexReg = Op.getImm();
4867 Op = MI->getOperand(3);
4868 if (Op.isGlobalAddress()) {
4869 AM.GV = Op.getGlobal();
4871 AM.Disp = Op.getImm();
4873 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4874 .addReg(MI->getOperand(4).getReg());
4876 // Reload the original control word now.
4877 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4879 delete MI; // The pseudo instruction is gone now.
4885 //===----------------------------------------------------------------------===//
4886 // X86 Optimization Hooks
4887 //===----------------------------------------------------------------------===//
4889 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4891 uint64_t &KnownZero,
4893 unsigned Depth) const {
4894 unsigned Opc = Op.getOpcode();
4895 assert((Opc >= ISD::BUILTIN_OP_END ||
4896 Opc == ISD::INTRINSIC_WO_CHAIN ||
4897 Opc == ISD::INTRINSIC_W_CHAIN ||
4898 Opc == ISD::INTRINSIC_VOID) &&
4899 "Should use MaskedValueIsZero if you don't know whether Op"
4900 " is a target node!");
4902 KnownZero = KnownOne = 0; // Don't know anything.
4906 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4911 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4912 /// element of the result of the vector shuffle.
4913 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4914 MVT::ValueType VT = N->getValueType(0);
4915 SDOperand PermMask = N->getOperand(2);
4916 unsigned NumElems = PermMask.getNumOperands();
4917 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4919 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4921 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4922 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4923 SDOperand Idx = PermMask.getOperand(i);
4924 if (Idx.getOpcode() == ISD::UNDEF)
4925 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4926 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4931 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4932 /// node is a GlobalAddress + an offset.
4933 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4934 unsigned Opc = N->getOpcode();
4935 if (Opc == X86ISD::Wrapper) {
4936 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4937 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4940 } else if (Opc == ISD::ADD) {
4941 SDOperand N1 = N->getOperand(0);
4942 SDOperand N2 = N->getOperand(1);
4943 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4944 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4946 Offset += V->getSignExtended();
4949 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4950 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4952 Offset += V->getSignExtended();
4960 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4962 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4963 MachineFrameInfo *MFI) {
4964 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4967 SDOperand Loc = N->getOperand(1);
4968 SDOperand BaseLoc = Base->getOperand(1);
4969 if (Loc.getOpcode() == ISD::FrameIndex) {
4970 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4972 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
4973 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4974 int FS = MFI->getObjectSize(FI);
4975 int BFS = MFI->getObjectSize(BFI);
4976 if (FS != BFS || FS != Size) return false;
4977 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4979 GlobalValue *GV1 = NULL;
4980 GlobalValue *GV2 = NULL;
4981 int64_t Offset1 = 0;
4982 int64_t Offset2 = 0;
4983 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4984 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4985 if (isGA1 && isGA2 && GV1 == GV2)
4986 return Offset1 == (Offset2 + Dist*Size);
4992 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4993 const X86Subtarget *Subtarget) {
4996 if (isGAPlusOffset(Base, GV, Offset))
4997 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4999 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
5000 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
5002 // Fixed objects do not specify alignment, however the offsets are known.
5003 return ((Subtarget->getStackAlignment() % 16) == 0 &&
5004 (MFI->getObjectOffset(BFI) % 16) == 0);
5006 return MFI->getObjectAlignment(BFI) >= 16;
5012 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5013 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5014 /// if the load addresses are consecutive, non-overlapping, and in the right
5016 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5017 const X86Subtarget *Subtarget) {
5018 MachineFunction &MF = DAG.getMachineFunction();
5019 MachineFrameInfo *MFI = MF.getFrameInfo();
5020 MVT::ValueType VT = N->getValueType(0);
5021 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
5022 SDOperand PermMask = N->getOperand(2);
5023 int NumElems = (int)PermMask.getNumOperands();
5024 SDNode *Base = NULL;
5025 for (int i = 0; i < NumElems; ++i) {
5026 SDOperand Idx = PermMask.getOperand(i);
5027 if (Idx.getOpcode() == ISD::UNDEF) {
5028 if (!Base) return SDOperand();
5031 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
5032 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
5036 else if (!isConsecutiveLoad(Arg.Val, Base,
5037 i, MVT::getSizeInBits(EVT)/8,MFI))
5042 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
5044 LoadSDNode *LD = cast<LoadSDNode>(Base);
5045 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5046 LD->getSrcValueOffset());
5048 // Just use movups, it's shorter.
5049 std::vector<MVT::ValueType> Tys;
5050 Tys.push_back(MVT::v4f32);
5051 Tys.push_back(MVT::Other);
5052 SmallVector<SDOperand, 3> Ops;
5053 Ops.push_back(Base->getOperand(0));
5054 Ops.push_back(Base->getOperand(1));
5055 Ops.push_back(Base->getOperand(2));
5056 return DAG.getNode(ISD::BIT_CONVERT, VT,
5057 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
5061 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
5062 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
5063 const X86Subtarget *Subtarget) {
5064 SDOperand Cond = N->getOperand(0);
5066 // If we have SSE[12] support, try to form min/max nodes.
5067 if (Subtarget->hasSSE2() &&
5068 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
5069 if (Cond.getOpcode() == ISD::SETCC) {
5070 // Get the LHS/RHS of the select.
5071 SDOperand LHS = N->getOperand(1);
5072 SDOperand RHS = N->getOperand(2);
5073 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
5075 unsigned Opcode = 0;
5076 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
5079 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
5082 if (!UnsafeFPMath) break;
5084 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
5086 Opcode = X86ISD::FMIN;
5089 case ISD::SETOGT: // (X > Y) ? X : Y -> max
5092 if (!UnsafeFPMath) break;
5094 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
5096 Opcode = X86ISD::FMAX;
5099 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
5102 case ISD::SETOGT: // (X > Y) ? Y : X -> min
5105 if (!UnsafeFPMath) break;
5107 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
5109 Opcode = X86ISD::FMIN;
5112 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
5115 if (!UnsafeFPMath) break;
5117 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
5119 Opcode = X86ISD::FMAX;
5125 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
5134 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
5135 DAGCombinerInfo &DCI) const {
5136 SelectionDAG &DAG = DCI.DAG;
5137 switch (N->getOpcode()) {
5139 case ISD::VECTOR_SHUFFLE:
5140 return PerformShuffleCombine(N, DAG, Subtarget);
5142 return PerformSELECTCombine(N, DAG, Subtarget);
5148 //===----------------------------------------------------------------------===//
5149 // X86 Inline Assembly Support
5150 //===----------------------------------------------------------------------===//
5152 /// getConstraintType - Given a constraint letter, return the type of
5153 /// constraint it is for this target.
5154 X86TargetLowering::ConstraintType
5155 X86TargetLowering::getConstraintType(char ConstraintLetter) const {
5156 switch (ConstraintLetter) {
5165 return C_RegisterClass;
5166 default: return TargetLowering::getConstraintType(ConstraintLetter);
5170 /// isOperandValidForConstraint - Return the specified operand (possibly
5171 /// modified) if the specified SDOperand is valid for the specified target
5172 /// constraint letter, otherwise return null.
5173 SDOperand X86TargetLowering::
5174 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
5175 switch (Constraint) {
5178 // Literal immediates are always ok.
5179 if (isa<ConstantSDNode>(Op)) return Op;
5181 // If we are in non-pic codegen mode, we allow the address of a global to
5182 // be used with 'i'.
5183 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
5184 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
5185 return SDOperand(0, 0);
5187 if (GA->getOpcode() != ISD::TargetGlobalAddress)
5188 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5193 // Otherwise, not valid for this mode.
5194 return SDOperand(0, 0);
5196 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
5200 std::vector<unsigned> X86TargetLowering::
5201 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5202 MVT::ValueType VT) const {
5203 if (Constraint.size() == 1) {
5204 // FIXME: not handling fp-stack yet!
5205 // FIXME: not handling MMX registers yet ('y' constraint).
5206 switch (Constraint[0]) { // GCC X86 Constraint Letters
5207 default: break; // Unknown constraint letter
5208 case 'A': // EAX/EDX
5209 if (VT == MVT::i32 || VT == MVT::i64)
5210 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5212 case 'r': // GENERAL_REGS
5213 case 'R': // LEGACY_REGS
5214 if (VT == MVT::i64 && Subtarget->is64Bit())
5215 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
5216 X86::RSI, X86::RDI, X86::RBP, X86::RSP,
5217 X86::R8, X86::R9, X86::R10, X86::R11,
5218 X86::R12, X86::R13, X86::R14, X86::R15, 0);
5220 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
5221 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
5222 else if (VT == MVT::i16)
5223 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
5224 X86::SI, X86::DI, X86::BP, X86::SP, 0);
5225 else if (VT == MVT::i8)
5226 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5228 case 'l': // INDEX_REGS
5230 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
5231 X86::ESI, X86::EDI, X86::EBP, 0);
5232 else if (VT == MVT::i16)
5233 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
5234 X86::SI, X86::DI, X86::BP, 0);
5235 else if (VT == MVT::i8)
5236 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5238 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5241 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5242 else if (VT == MVT::i16)
5243 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5244 else if (VT == MVT::i8)
5245 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5247 case 'x': // SSE_REGS if SSE1 allowed
5248 if (Subtarget->hasSSE1())
5249 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
5250 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
5252 return std::vector<unsigned>();
5253 case 'Y': // SSE_REGS if SSE2 allowed
5254 if (Subtarget->hasSSE2())
5255 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
5256 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
5258 return std::vector<unsigned>();
5262 return std::vector<unsigned>();
5265 std::pair<unsigned, const TargetRegisterClass*>
5266 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5267 MVT::ValueType VT) const {
5268 // Use the default implementation in TargetLowering to convert the register
5269 // constraint into a member of a register class.
5270 std::pair<unsigned, const TargetRegisterClass*> Res;
5271 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5273 // Not found as a standard register?
5274 if (Res.second == 0) {
5275 // GCC calls "st(0)" just plain "st".
5276 if (StringsEqualNoCase("{st}", Constraint)) {
5277 Res.first = X86::ST0;
5278 Res.second = X86::RSTRegisterClass;
5284 // Otherwise, check to see if this is a register class of the wrong value
5285 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5286 // turn into {ax},{dx}.
5287 if (Res.second->hasType(VT))
5288 return Res; // Correct type already, nothing to do.
5290 // All of the single-register GCC register classes map their values onto
5291 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5292 // really want an 8-bit or 32-bit register, map to the appropriate register
5293 // class and return the appropriate register.
5294 if (Res.second != X86::GR16RegisterClass)
5297 if (VT == MVT::i8) {
5298 unsigned DestReg = 0;
5299 switch (Res.first) {
5301 case X86::AX: DestReg = X86::AL; break;
5302 case X86::DX: DestReg = X86::DL; break;
5303 case X86::CX: DestReg = X86::CL; break;
5304 case X86::BX: DestReg = X86::BL; break;
5307 Res.first = DestReg;
5308 Res.second = Res.second = X86::GR8RegisterClass;
5310 } else if (VT == MVT::i32) {
5311 unsigned DestReg = 0;
5312 switch (Res.first) {
5314 case X86::AX: DestReg = X86::EAX; break;
5315 case X86::DX: DestReg = X86::EDX; break;
5316 case X86::CX: DestReg = X86::ECX; break;
5317 case X86::BX: DestReg = X86::EBX; break;
5318 case X86::SI: DestReg = X86::ESI; break;
5319 case X86::DI: DestReg = X86::EDI; break;
5320 case X86::BP: DestReg = X86::EBP; break;
5321 case X86::SP: DestReg = X86::ESP; break;
5324 Res.first = DestReg;
5325 Res.second = Res.second = X86::GR32RegisterClass;
5327 } else if (VT == MVT::i64) {
5328 unsigned DestReg = 0;
5329 switch (Res.first) {
5331 case X86::AX: DestReg = X86::RAX; break;
5332 case X86::DX: DestReg = X86::RDX; break;
5333 case X86::CX: DestReg = X86::RCX; break;
5334 case X86::BX: DestReg = X86::RBX; break;
5335 case X86::SI: DestReg = X86::RSI; break;
5336 case X86::DI: DestReg = X86::RDI; break;
5337 case X86::BP: DestReg = X86::RBP; break;
5338 case X86::SP: DestReg = X86::RSP; break;
5341 Res.first = DestReg;
5342 Res.second = Res.second = X86::GR64RegisterClass;