1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<bool> ExperimentalVectorShuffleLegality(
75 "x86-experimental-vector-shuffle-legality", cl::init(false),
76 cl::desc("Enable experimental shuffle legality based on the experimental "
77 "shuffle lowering. Should only be used with the experimental "
81 static cl::opt<int> ReciprocalEstimateRefinementSteps(
82 "x86-recip-refinement-steps", cl::init(1),
83 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
84 "result of the hardware reciprocal estimate instruction."),
87 // Forward declarations.
88 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
91 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
92 SelectionDAG &DAG, SDLoc dl,
93 unsigned vectorWidth) {
94 assert((vectorWidth == 128 || vectorWidth == 256) &&
95 "Unsupported vector width");
96 EVT VT = Vec.getValueType();
97 EVT ElVT = VT.getVectorElementType();
98 unsigned Factor = VT.getSizeInBits()/vectorWidth;
99 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
100 VT.getVectorNumElements()/Factor);
102 // Extract from UNDEF is UNDEF.
103 if (Vec.getOpcode() == ISD::UNDEF)
104 return DAG.getUNDEF(ResultVT);
106 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
107 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
109 // This is the index of the first element of the vectorWidth-bit chunk
111 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
114 // If the input is a buildvector just emit a smaller one.
115 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
116 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
117 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
120 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
121 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
124 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
125 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
126 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
127 /// instructions or a simple subregister reference. Idx is an index in the
128 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
129 /// lowering EXTRACT_VECTOR_ELT operations easier.
130 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
131 SelectionDAG &DAG, SDLoc dl) {
132 assert((Vec.getValueType().is256BitVector() ||
133 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
137 /// Generate a DAG to grab 256-bits from a 512-bit vector.
138 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
139 SelectionDAG &DAG, SDLoc dl) {
140 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
141 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
144 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
145 unsigned IdxVal, SelectionDAG &DAG,
146 SDLoc dl, unsigned vectorWidth) {
147 assert((vectorWidth == 128 || vectorWidth == 256) &&
148 "Unsupported vector width");
149 // Inserting UNDEF is Result
150 if (Vec.getOpcode() == ISD::UNDEF)
152 EVT VT = Vec.getValueType();
153 EVT ElVT = VT.getVectorElementType();
154 EVT ResultVT = Result.getValueType();
156 // Insert the relevant vectorWidth bits.
157 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
159 // This is the index of the first element of the vectorWidth-bit chunk
161 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
164 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
165 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
168 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
169 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
170 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
171 /// simple superregister reference. Idx is an index in the 128 bits
172 /// we want. It need not be aligned to a 128-bit boundary. That makes
173 /// lowering INSERT_VECTOR_ELT operations easier.
174 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
175 SelectionDAG &DAG,SDLoc dl) {
176 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
177 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
180 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
181 SelectionDAG &DAG, SDLoc dl) {
182 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
183 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
186 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
187 /// instructions. This is used because creating CONCAT_VECTOR nodes of
188 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
189 /// large BUILD_VECTORS.
190 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
197 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
198 unsigned NumElems, SelectionDAG &DAG,
200 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
201 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
204 // FIXME: This should stop caching the target machine as soon as
205 // we can remove resetOperationActions et al.
206 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
207 : TargetLowering(TM) {
208 Subtarget = &TM.getSubtarget<X86Subtarget>();
209 X86ScalarSSEf64 = Subtarget->hasSSE2();
210 X86ScalarSSEf32 = Subtarget->hasSSE1();
211 TD = getDataLayout();
213 resetOperationActions();
216 void X86TargetLowering::resetOperationActions() {
217 const TargetMachine &TM = getTargetMachine();
218 static bool FirstTimeThrough = true;
220 // If none of the target options have changed, then we don't need to reset the
221 // operation actions.
222 if (!FirstTimeThrough && TO == TM.Options) return;
224 if (!FirstTimeThrough) {
225 // Reinitialize the actions.
227 FirstTimeThrough = false;
232 // Set up the TargetLowering object.
233 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
235 // X86 is weird. It always uses i8 for shift amounts and setcc results.
236 setBooleanContents(ZeroOrOneBooleanContent);
237 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
238 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
240 // For 64-bit, since we have so many registers, use the ILP scheduler.
241 // For 32-bit, use the register pressure specific scheduling.
242 // For Atom, always use ILP scheduling.
243 if (Subtarget->isAtom())
244 setSchedulingPreference(Sched::ILP);
245 else if (Subtarget->is64Bit())
246 setSchedulingPreference(Sched::ILP);
248 setSchedulingPreference(Sched::RegPressure);
249 const X86RegisterInfo *RegInfo =
250 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
251 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
253 // Bypass expensive divides on Atom when compiling with O2.
254 if (TM.getOptLevel() >= CodeGenOpt::Default) {
255 if (Subtarget->hasSlowDivide32())
256 addBypassSlowDiv(32, 8);
257 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
258 addBypassSlowDiv(64, 16);
261 if (Subtarget->isTargetKnownWindowsMSVC()) {
262 // Setup Windows compiler runtime calls.
263 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
264 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
265 setLibcallName(RTLIB::SREM_I64, "_allrem");
266 setLibcallName(RTLIB::UREM_I64, "_aullrem");
267 setLibcallName(RTLIB::MUL_I64, "_allmul");
268 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
271 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
272 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
274 // The _ftol2 runtime function has an unusual calling conv, which
275 // is modeled by a special pseudo-instruction.
276 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
278 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
279 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
282 if (Subtarget->isTargetDarwin()) {
283 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
284 setUseUnderscoreSetJmp(false);
285 setUseUnderscoreLongJmp(false);
286 } else if (Subtarget->isTargetWindowsGNU()) {
287 // MS runtime is weird: it exports _setjmp, but longjmp!
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(false);
291 setUseUnderscoreSetJmp(true);
292 setUseUnderscoreLongJmp(true);
295 // Set up the register classes.
296 addRegisterClass(MVT::i8, &X86::GR8RegClass);
297 addRegisterClass(MVT::i16, &X86::GR16RegClass);
298 addRegisterClass(MVT::i32, &X86::GR32RegClass);
299 if (Subtarget->is64Bit())
300 addRegisterClass(MVT::i64, &X86::GR64RegClass);
302 for (MVT VT : MVT::integer_valuetypes())
303 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
305 // We don't accept any truncstore of integer registers.
306 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
307 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
308 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
309 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
310 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
311 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
313 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
315 // SETOEQ and SETUNE require checking two conditions.
316 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
319 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
320 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
321 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
323 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
325 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
326 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
329 if (Subtarget->is64Bit()) {
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 } else if (!TM.Options.UseSoftFloat) {
333 // We have an algorithm for SSE2->double, and we turn this into a
334 // 64-bit FILD followed by conditional FADD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 // We have an algorithm for SSE2, and we turn this into a 64-bit
337 // FILD for other targets.
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
341 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
343 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
346 if (!TM.Options.UseSoftFloat) {
347 // SSE has no i16 to fp conversion, only i32
348 if (X86ScalarSSEf32) {
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 // f32 and f64 cases are Legal, f80 case is not
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
361 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
362 // are Legal, f80 is custom lowered.
363 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
364 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
366 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
368 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
371 if (X86ScalarSSEf32) {
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
373 // f32 and f64 cases are Legal, f80 case is not
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 // Handle FP_TO_UINT by promoting the destination to a larger signed
382 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
383 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
386 if (Subtarget->is64Bit()) {
387 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
389 } else if (!TM.Options.UseSoftFloat) {
390 // Since AVX is a superset of SSE3, only check for SSE here.
391 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
392 // Expand FP_TO_UINT into a select.
393 // FIXME: We would like to use a Custom expander here eventually to do
394 // the optimal thing for SSE vs. the default expansion in the legalizer.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
397 // With SSE3 we can use fisttpll to convert to a signed i64; without
398 // SSE, we're stuck with a fistpll.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
402 if (isTargetFTOL()) {
403 // Use the _ftol2 runtime function, which has a pseudo-instruction
404 // to handle its weird calling convention.
405 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
408 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
409 if (!X86ScalarSSEf64) {
410 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
411 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
412 if (Subtarget->is64Bit()) {
413 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
414 // Without SSE, i64->f64 goes through memory.
415 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
419 // Scalar integer divide and remainder are lowered to use operations that
420 // produce two results, to match the available instructions. This exposes
421 // the two-result form to trivial CSE, which is able to combine x/y and x%y
422 // into a single instruction.
424 // Scalar integer multiply-high is also lowered to use two-result
425 // operations, to match the available instructions. However, plain multiply
426 // (low) operations are left as Legal, as there are single-result
427 // instructions for this in x86. Using the two-result multiply instructions
428 // when both high and low results are needed must be arranged by dagcombine.
429 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
431 setOperationAction(ISD::MULHS, VT, Expand);
432 setOperationAction(ISD::MULHU, VT, Expand);
433 setOperationAction(ISD::SDIV, VT, Expand);
434 setOperationAction(ISD::UDIV, VT, Expand);
435 setOperationAction(ISD::SREM, VT, Expand);
436 setOperationAction(ISD::UREM, VT, Expand);
438 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
439 setOperationAction(ISD::ADDC, VT, Custom);
440 setOperationAction(ISD::ADDE, VT, Custom);
441 setOperationAction(ISD::SUBC, VT, Custom);
442 setOperationAction(ISD::SUBE, VT, Custom);
445 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
446 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
447 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
448 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
449 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
451 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
452 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
453 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
461 if (Subtarget->is64Bit())
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
463 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
466 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
467 setOperationAction(ISD::FREM , MVT::f32 , Expand);
468 setOperationAction(ISD::FREM , MVT::f64 , Expand);
469 setOperationAction(ISD::FREM , MVT::f80 , Expand);
470 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
472 // Promote the i8 variants and force them on up to i32 which has a shorter
474 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
478 if (Subtarget->hasBMI()) {
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
484 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
486 if (Subtarget->is64Bit())
487 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
490 if (Subtarget->hasLZCNT()) {
491 // When promoting the i8 variants, force them to i32 for a shorter
493 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
494 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
496 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
499 if (Subtarget->is64Bit())
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
502 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
508 if (Subtarget->is64Bit()) {
509 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
514 // Special handling for half-precision floating point conversions.
515 // If we don't have F16C support, then lower half float conversions
516 // into library calls.
517 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
518 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
519 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
522 // There's never any support for operations beyond MVT::f32.
523 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
524 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
525 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
526 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
528 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
529 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
530 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
531 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
532 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
535 if (Subtarget->hasPOPCNT()) {
536 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
538 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
539 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
540 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
541 if (Subtarget->is64Bit())
542 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
545 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
547 if (!Subtarget->hasMOVBE())
548 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
550 // These should be promoted to a larger select which is supported.
551 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
552 // X86 wants to expand cmov itself.
553 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
554 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
555 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
556 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
557 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
559 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
562 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
563 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
565 if (Subtarget->is64Bit()) {
566 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
569 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
570 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
571 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
572 // support continuation, user-level threading, and etc.. As a result, no
573 // other SjLj exception interfaces are implemented and please don't build
574 // your own exception handling based on them.
575 // LLVM/Clang supports zero-cost DWARF exception handling.
576 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
577 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
580 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
581 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
582 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
583 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
584 if (Subtarget->is64Bit())
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
586 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
588 if (Subtarget->is64Bit()) {
589 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
590 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
591 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
592 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
595 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
596 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
597 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
598 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
599 if (Subtarget->is64Bit()) {
600 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
601 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
602 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
605 if (Subtarget->hasSSE1())
606 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
608 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
610 // Expand certain atomics
611 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
614 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
615 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
618 if (Subtarget->hasCmpxchg16b()) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
622 // FIXME - use subtarget debug flags
623 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
624 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
625 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
628 if (Subtarget->is64Bit()) {
629 setExceptionPointerRegister(X86::RAX);
630 setExceptionSelectorRegister(X86::RDX);
632 setExceptionPointerRegister(X86::EAX);
633 setExceptionSelectorRegister(X86::EDX);
635 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
636 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
638 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
639 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::TRAP, MVT::Other, Legal);
642 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
644 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
645 setOperationAction(ISD::VASTART , MVT::Other, Custom);
646 setOperationAction(ISD::VAEND , MVT::Other, Expand);
647 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
648 // TargetInfo::X86_64ABIBuiltinVaList
649 setOperationAction(ISD::VAARG , MVT::Other, Custom);
650 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
652 // TargetInfo::CharPtrBuiltinVaList
653 setOperationAction(ISD::VAARG , MVT::Other, Expand);
654 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
657 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
658 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
660 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
662 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
663 // f32 and f64 use SSE.
664 // Set up the FP register classes.
665 addRegisterClass(MVT::f32, &X86::FR32RegClass);
666 addRegisterClass(MVT::f64, &X86::FR64RegClass);
668 // Use ANDPD to simulate FABS.
669 setOperationAction(ISD::FABS , MVT::f64, Custom);
670 setOperationAction(ISD::FABS , MVT::f32, Custom);
672 // Use XORP to simulate FNEG.
673 setOperationAction(ISD::FNEG , MVT::f64, Custom);
674 setOperationAction(ISD::FNEG , MVT::f32, Custom);
676 // Use ANDPD and ORPD to simulate FCOPYSIGN.
677 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
678 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
680 // Lower this to FGETSIGNx86 plus an AND.
681 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
682 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
684 // We don't support sin/cos/fmod
685 setOperationAction(ISD::FSIN , MVT::f64, Expand);
686 setOperationAction(ISD::FCOS , MVT::f64, Expand);
687 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
688 setOperationAction(ISD::FSIN , MVT::f32, Expand);
689 setOperationAction(ISD::FCOS , MVT::f32, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
692 // Expand FP immediates into loads from the stack, except for the special
694 addLegalFPImmediate(APFloat(+0.0)); // xorpd
695 addLegalFPImmediate(APFloat(+0.0f)); // xorps
696 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
697 // Use SSE for f32, x87 for f64.
698 // Set up the FP register classes.
699 addRegisterClass(MVT::f32, &X86::FR32RegClass);
700 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
702 // Use ANDPS to simulate FABS.
703 setOperationAction(ISD::FABS , MVT::f32, Custom);
705 // Use XORP to simulate FNEG.
706 setOperationAction(ISD::FNEG , MVT::f32, Custom);
708 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
710 // Use ANDPS and ORPS to simulate FCOPYSIGN.
711 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
712 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
714 // We don't support sin/cos/fmod
715 setOperationAction(ISD::FSIN , MVT::f32, Expand);
716 setOperationAction(ISD::FCOS , MVT::f32, Expand);
717 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
719 // Special cases we handle for FP constants.
720 addLegalFPImmediate(APFloat(+0.0f)); // xorps
721 addLegalFPImmediate(APFloat(+0.0)); // FLD0
722 addLegalFPImmediate(APFloat(+1.0)); // FLD1
723 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
724 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f64, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
731 } else if (!TM.Options.UseSoftFloat) {
732 // f32 and f64 in x87.
733 // Set up the FP register classes.
734 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
735 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
737 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
738 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
739 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
740 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
742 if (!TM.Options.UnsafeFPMath) {
743 setOperationAction(ISD::FSIN , MVT::f64, Expand);
744 setOperationAction(ISD::FSIN , MVT::f32, Expand);
745 setOperationAction(ISD::FCOS , MVT::f64, Expand);
746 setOperationAction(ISD::FCOS , MVT::f32, Expand);
747 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
748 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
750 addLegalFPImmediate(APFloat(+0.0)); // FLD0
751 addLegalFPImmediate(APFloat(+1.0)); // FLD1
752 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
753 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
754 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
755 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
756 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
757 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
760 // We don't support FMA.
761 setOperationAction(ISD::FMA, MVT::f64, Expand);
762 setOperationAction(ISD::FMA, MVT::f32, Expand);
764 // Long double always uses X87.
765 if (!TM.Options.UseSoftFloat) {
766 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
767 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
768 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
770 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
771 addLegalFPImmediate(TmpFlt); // FLD0
773 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
776 APFloat TmpFlt2(+1.0);
777 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
779 addLegalFPImmediate(TmpFlt2); // FLD1
780 TmpFlt2.changeSign();
781 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
784 if (!TM.Options.UnsafeFPMath) {
785 setOperationAction(ISD::FSIN , MVT::f80, Expand);
786 setOperationAction(ISD::FCOS , MVT::f80, Expand);
787 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
790 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
791 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
792 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
793 setOperationAction(ISD::FRINT, MVT::f80, Expand);
794 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
795 setOperationAction(ISD::FMA, MVT::f80, Expand);
798 // Always use a library call for pow.
799 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
800 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
801 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
803 setOperationAction(ISD::FLOG, MVT::f80, Expand);
804 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
805 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
806 setOperationAction(ISD::FEXP, MVT::f80, Expand);
807 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
808 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
809 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
811 // First set operation action for all vector types to either promote
812 // (for widening) or expand (for scalarization). Then we will selectively
813 // turn on ones that can be effectively codegen'd.
814 for (MVT VT : MVT::vector_valuetypes()) {
815 setOperationAction(ISD::ADD , VT, Expand);
816 setOperationAction(ISD::SUB , VT, Expand);
817 setOperationAction(ISD::FADD, VT, Expand);
818 setOperationAction(ISD::FNEG, VT, Expand);
819 setOperationAction(ISD::FSUB, VT, Expand);
820 setOperationAction(ISD::MUL , VT, Expand);
821 setOperationAction(ISD::FMUL, VT, Expand);
822 setOperationAction(ISD::SDIV, VT, Expand);
823 setOperationAction(ISD::UDIV, VT, Expand);
824 setOperationAction(ISD::FDIV, VT, Expand);
825 setOperationAction(ISD::SREM, VT, Expand);
826 setOperationAction(ISD::UREM, VT, Expand);
827 setOperationAction(ISD::LOAD, VT, Expand);
828 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
830 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
831 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
832 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
833 setOperationAction(ISD::FABS, VT, Expand);
834 setOperationAction(ISD::FSIN, VT, Expand);
835 setOperationAction(ISD::FSINCOS, VT, Expand);
836 setOperationAction(ISD::FCOS, VT, Expand);
837 setOperationAction(ISD::FSINCOS, VT, Expand);
838 setOperationAction(ISD::FREM, VT, Expand);
839 setOperationAction(ISD::FMA, VT, Expand);
840 setOperationAction(ISD::FPOWI, VT, Expand);
841 setOperationAction(ISD::FSQRT, VT, Expand);
842 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
843 setOperationAction(ISD::FFLOOR, VT, Expand);
844 setOperationAction(ISD::FCEIL, VT, Expand);
845 setOperationAction(ISD::FTRUNC, VT, Expand);
846 setOperationAction(ISD::FRINT, VT, Expand);
847 setOperationAction(ISD::FNEARBYINT, VT, Expand);
848 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
849 setOperationAction(ISD::MULHS, VT, Expand);
850 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
851 setOperationAction(ISD::MULHU, VT, Expand);
852 setOperationAction(ISD::SDIVREM, VT, Expand);
853 setOperationAction(ISD::UDIVREM, VT, Expand);
854 setOperationAction(ISD::FPOW, VT, Expand);
855 setOperationAction(ISD::CTPOP, VT, Expand);
856 setOperationAction(ISD::CTTZ, VT, Expand);
857 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
858 setOperationAction(ISD::CTLZ, VT, Expand);
859 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
860 setOperationAction(ISD::SHL, VT, Expand);
861 setOperationAction(ISD::SRA, VT, Expand);
862 setOperationAction(ISD::SRL, VT, Expand);
863 setOperationAction(ISD::ROTL, VT, Expand);
864 setOperationAction(ISD::ROTR, VT, Expand);
865 setOperationAction(ISD::BSWAP, VT, Expand);
866 setOperationAction(ISD::SETCC, VT, Expand);
867 setOperationAction(ISD::FLOG, VT, Expand);
868 setOperationAction(ISD::FLOG2, VT, Expand);
869 setOperationAction(ISD::FLOG10, VT, Expand);
870 setOperationAction(ISD::FEXP, VT, Expand);
871 setOperationAction(ISD::FEXP2, VT, Expand);
872 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
873 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
874 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
875 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
876 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
877 setOperationAction(ISD::TRUNCATE, VT, Expand);
878 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
879 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
880 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
881 setOperationAction(ISD::VSELECT, VT, Expand);
882 setOperationAction(ISD::SELECT_CC, VT, Expand);
883 for (MVT InnerVT : MVT::vector_valuetypes()) {
884 setTruncStoreAction(InnerVT, VT, Expand);
886 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
887 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
889 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
890 // types, we have to deal with them whether we ask for Expansion or not.
891 // Setting Expand causes its own optimisation problems though, so leave
893 if (VT.getVectorElementType() == MVT::i1)
894 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
898 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
899 // with -msoft-float, disable use of MMX as well.
900 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
901 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
902 // No operations on x86mmx supported, everything uses intrinsics.
905 // MMX-sized vectors (other than x86mmx) are expected to be expanded
906 // into smaller operations.
907 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
908 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
909 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
910 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
911 setOperationAction(ISD::AND, MVT::v8i8, Expand);
912 setOperationAction(ISD::AND, MVT::v4i16, Expand);
913 setOperationAction(ISD::AND, MVT::v2i32, Expand);
914 setOperationAction(ISD::AND, MVT::v1i64, Expand);
915 setOperationAction(ISD::OR, MVT::v8i8, Expand);
916 setOperationAction(ISD::OR, MVT::v4i16, Expand);
917 setOperationAction(ISD::OR, MVT::v2i32, Expand);
918 setOperationAction(ISD::OR, MVT::v1i64, Expand);
919 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
927 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
928 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
929 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
930 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
931 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
932 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
933 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
937 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
938 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
940 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
941 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
942 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
943 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
944 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
945 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
946 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
947 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
948 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
949 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
951 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
952 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
955 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
956 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
959 // registers cannot be used even for integer operations.
960 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
961 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
962 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
963 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
966 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
967 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
968 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
969 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
970 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
971 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
972 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
974 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
975 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
976 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
977 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
978 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
979 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
980 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
981 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
982 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
983 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
984 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
985 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
986 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
990 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
991 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 // Only provide customized ctpop vector bit twiddling for vector types we
1000 // know to perform better than using the popcnt instructions on each vector
1001 // element. If popcnt isn't supported, always provide the custom version.
1002 if (!Subtarget->hasPOPCNT()) {
1003 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
1004 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
1007 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1008 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1009 MVT VT = (MVT::SimpleValueType)i;
1010 // Do not attempt to custom lower non-power-of-2 vectors
1011 if (!isPowerOf2_32(VT.getVectorNumElements()))
1013 // Do not attempt to custom lower non-128-bit vectors
1014 if (!VT.is128BitVector())
1016 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1017 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1018 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1021 // We support custom legalizing of sext and anyext loads for specific
1022 // memory vector types which we can load as a scalar (or sequence of
1023 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1024 // loads these must work with a single scalar load.
1025 for (MVT VT : MVT::integer_vector_valuetypes()) {
1026 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
1027 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
1028 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
1030 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
1031 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
1032 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
1033 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
1037 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1038 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1039 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1040 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1042 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1044 if (Subtarget->is64Bit()) {
1045 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1046 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1049 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1050 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1051 MVT VT = (MVT::SimpleValueType)i;
1053 // Do not attempt to promote non-128-bit vectors
1054 if (!VT.is128BitVector())
1057 setOperationAction(ISD::AND, VT, Promote);
1058 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1059 setOperationAction(ISD::OR, VT, Promote);
1060 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1061 setOperationAction(ISD::XOR, VT, Promote);
1062 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1063 setOperationAction(ISD::LOAD, VT, Promote);
1064 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1065 setOperationAction(ISD::SELECT, VT, Promote);
1066 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1069 // Custom lower v2i64 and v2f64 selects.
1070 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1071 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1072 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1073 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1075 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1076 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1078 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1079 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1080 // As there is no 64-bit GPR available, we need build a special custom
1081 // sequence to convert from v2i32 to v2f32.
1082 if (!Subtarget->is64Bit())
1083 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1085 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1086 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1088 for (MVT VT : MVT::fp_vector_valuetypes())
1089 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
1091 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1092 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1093 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1096 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1097 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1100 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1102 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1103 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1104 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1105 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1106 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1108 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1109 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1110 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1111 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1112 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1113 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1114 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1115 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1116 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1117 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1119 // FIXME: Do we need to handle scalar-to-vector here?
1120 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1122 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1123 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1124 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1125 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1126 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1127 // There is no BLENDI for byte vectors. We don't need to custom lower
1128 // some vselects for now.
1129 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1131 // SSE41 brings specific instructions for doing vector sign extend even in
1132 // cases where we don't have SRA.
1133 for (MVT VT : MVT::integer_vector_valuetypes()) {
1134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
1135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
1136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
1139 // i8 and i16 vectors are custom because the source register and source
1140 // source memory operand types are not the same width. f32 vectors are
1141 // custom since the immediate controlling the insert encodes additional
1143 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1144 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1145 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1150 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1153 // FIXME: these should be Legal, but that's only for the case where
1154 // the index is constant. For now custom expand to deal with that.
1155 if (Subtarget->is64Bit()) {
1156 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1157 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1161 if (Subtarget->hasSSE2()) {
1162 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1163 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1165 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1166 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1168 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1169 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1171 // In the customized shift lowering, the legal cases in AVX2 will be
1173 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1174 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1176 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1177 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1179 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1182 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1183 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1184 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1185 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1186 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1187 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1188 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1190 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1191 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1192 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1194 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1197 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1198 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1199 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1200 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1201 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1202 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1204 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1205 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1207 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1210 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1211 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1212 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1213 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1214 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1215 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1216 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1217 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1218 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1220 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1221 // even though v8i16 is a legal type.
1222 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1223 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1224 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1226 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1227 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1228 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1230 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1231 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1233 for (MVT VT : MVT::fp_vector_valuetypes())
1234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1236 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1240 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1242 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1243 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1245 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1246 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1247 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1251 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1254 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1255 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1256 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1257 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1259 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1260 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1261 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1262 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1263 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1264 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1265 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1266 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1267 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1268 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1269 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1270 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1272 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1273 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1274 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1275 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1276 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1277 setOperationAction(ISD::FMA, MVT::f32, Legal);
1278 setOperationAction(ISD::FMA, MVT::f64, Legal);
1281 if (Subtarget->hasInt256()) {
1282 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1283 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1284 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1285 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1287 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1288 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1289 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1290 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1292 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1293 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1294 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1295 // Don't lower v32i8 because there is no 128-bit byte mul
1297 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1299 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1300 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1302 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1303 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1305 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1306 // when we have a 256bit-wide blend with immediate.
1307 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1309 // Only provide customized ctpop vector bit twiddling for vector types we
1310 // know to perform better than using the popcnt instructions on each
1311 // vector element. If popcnt isn't supported, always provide the custom
1313 if (!Subtarget->hasPOPCNT())
1314 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1316 // Custom CTPOP always performs better on natively supported v8i32
1317 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1319 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1320 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1321 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1322 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1324 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1325 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1326 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1327 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1329 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1330 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1331 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1332 // Don't lower v32i8 because there is no 128-bit byte mul
1335 // In the customized shift lowering, the legal cases in AVX2 will be
1337 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1338 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1340 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1341 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1343 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1345 // Custom lower several nodes for 256-bit types.
1346 for (MVT VT : MVT::vector_valuetypes()) {
1347 if (VT.getScalarSizeInBits() >= 32) {
1348 setOperationAction(ISD::MLOAD, VT, Legal);
1349 setOperationAction(ISD::MSTORE, VT, Legal);
1351 // Extract subvector is special because the value type
1352 // (result) is 128-bit but the source is 256-bit wide.
1353 if (VT.is128BitVector()) {
1354 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1356 // Do not attempt to custom lower other non-256-bit vectors
1357 if (!VT.is256BitVector())
1360 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1361 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1362 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1363 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1364 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1365 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1366 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1369 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1370 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1371 MVT VT = (MVT::SimpleValueType)i;
1373 // Do not attempt to promote non-256-bit vectors
1374 if (!VT.is256BitVector())
1377 setOperationAction(ISD::AND, VT, Promote);
1378 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1379 setOperationAction(ISD::OR, VT, Promote);
1380 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1381 setOperationAction(ISD::XOR, VT, Promote);
1382 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1383 setOperationAction(ISD::LOAD, VT, Promote);
1384 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1385 setOperationAction(ISD::SELECT, VT, Promote);
1386 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1390 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1391 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1392 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1393 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1394 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1396 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1397 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1398 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1400 for (MVT VT : MVT::fp_vector_valuetypes())
1401 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1403 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1404 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1405 setOperationAction(ISD::XOR, MVT::i1, Legal);
1406 setOperationAction(ISD::OR, MVT::i1, Legal);
1407 setOperationAction(ISD::AND, MVT::i1, Legal);
1408 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1409 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1410 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1411 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1412 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1414 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1415 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1417 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1418 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1419 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1421 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1422 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1423 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1424 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1425 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1426 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1427 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1428 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1430 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1431 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1432 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1433 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1434 if (Subtarget->is64Bit()) {
1435 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1436 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1438 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1440 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1441 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1442 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1443 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1444 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1445 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1446 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1447 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1448 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1449 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1450 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1451 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1452 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1453 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1455 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1456 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1457 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1458 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1459 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1460 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1461 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1462 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1463 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1464 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1465 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1466 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1467 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1473 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1474 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1476 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1477 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1479 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1481 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1482 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1483 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1484 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1485 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1486 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1488 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1491 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1492 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1494 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1495 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1497 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1499 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1500 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1502 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1503 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1505 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1506 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1508 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1509 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1510 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1511 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1512 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1513 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1515 if (Subtarget->hasCDI()) {
1516 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1517 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1520 // Custom lower several nodes.
1521 for (MVT VT : MVT::vector_valuetypes()) {
1522 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1523 // Extract subvector is special because the value type
1524 // (result) is 256/128-bit but the source is 512-bit wide.
1525 if (VT.is128BitVector() || VT.is256BitVector()) {
1526 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1528 if (VT.getVectorElementType() == MVT::i1)
1529 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1531 // Do not attempt to custom lower other non-512-bit vectors
1532 if (!VT.is512BitVector())
1535 if ( EltSize >= 32) {
1536 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1537 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1538 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1539 setOperationAction(ISD::VSELECT, VT, Legal);
1540 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1541 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1542 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1543 setOperationAction(ISD::MLOAD, VT, Legal);
1544 setOperationAction(ISD::MSTORE, VT, Legal);
1547 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1548 MVT VT = (MVT::SimpleValueType)i;
1550 // Do not attempt to promote non-512-bit vectors.
1551 if (!VT.is512BitVector())
1554 setOperationAction(ISD::SELECT, VT, Promote);
1555 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1559 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1560 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1561 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1563 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1564 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1566 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1567 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1568 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1569 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1570 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1571 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1572 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1573 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1574 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 const MVT VT = (MVT::SimpleValueType)i;
1579 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1581 // Do not attempt to promote non-512-bit vectors.
1582 if (!VT.is512BitVector())
1586 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1587 setOperationAction(ISD::VSELECT, VT, Legal);
1592 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1593 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1594 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1596 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1597 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1598 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1600 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1601 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1602 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1603 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1604 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1605 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1608 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1609 // of this type with custom code.
1610 for (MVT VT : MVT::vector_valuetypes())
1611 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
1613 // We want to custom lower some of our intrinsics.
1614 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1615 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1616 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1617 if (!Subtarget->is64Bit())
1618 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1620 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1621 // handle type legalization for these operations here.
1623 // FIXME: We really should do custom legalization for addition and
1624 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1625 // than generic legalization for 64-bit multiplication-with-overflow, though.
1626 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1627 // Add/Sub/Mul with overflow operations are custom lowered.
1629 setOperationAction(ISD::SADDO, VT, Custom);
1630 setOperationAction(ISD::UADDO, VT, Custom);
1631 setOperationAction(ISD::SSUBO, VT, Custom);
1632 setOperationAction(ISD::USUBO, VT, Custom);
1633 setOperationAction(ISD::SMULO, VT, Custom);
1634 setOperationAction(ISD::UMULO, VT, Custom);
1638 if (!Subtarget->is64Bit()) {
1639 // These libcalls are not available in 32-bit.
1640 setLibcallName(RTLIB::SHL_I128, nullptr);
1641 setLibcallName(RTLIB::SRL_I128, nullptr);
1642 setLibcallName(RTLIB::SRA_I128, nullptr);
1645 // Combine sin / cos into one node or libcall if possible.
1646 if (Subtarget->hasSinCos()) {
1647 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1648 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1649 if (Subtarget->isTargetDarwin()) {
1650 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1651 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1652 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1653 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1657 if (Subtarget->isTargetWin64()) {
1658 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1659 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1660 setOperationAction(ISD::SREM, MVT::i128, Custom);
1661 setOperationAction(ISD::UREM, MVT::i128, Custom);
1662 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1663 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1666 // We have target-specific dag combine patterns for the following nodes:
1667 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1668 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1669 setTargetDAGCombine(ISD::VSELECT);
1670 setTargetDAGCombine(ISD::SELECT);
1671 setTargetDAGCombine(ISD::SHL);
1672 setTargetDAGCombine(ISD::SRA);
1673 setTargetDAGCombine(ISD::SRL);
1674 setTargetDAGCombine(ISD::OR);
1675 setTargetDAGCombine(ISD::AND);
1676 setTargetDAGCombine(ISD::ADD);
1677 setTargetDAGCombine(ISD::FADD);
1678 setTargetDAGCombine(ISD::FSUB);
1679 setTargetDAGCombine(ISD::FMA);
1680 setTargetDAGCombine(ISD::SUB);
1681 setTargetDAGCombine(ISD::LOAD);
1682 setTargetDAGCombine(ISD::STORE);
1683 setTargetDAGCombine(ISD::ZERO_EXTEND);
1684 setTargetDAGCombine(ISD::ANY_EXTEND);
1685 setTargetDAGCombine(ISD::SIGN_EXTEND);
1686 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1687 setTargetDAGCombine(ISD::TRUNCATE);
1688 setTargetDAGCombine(ISD::SINT_TO_FP);
1689 setTargetDAGCombine(ISD::SETCC);
1690 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1691 setTargetDAGCombine(ISD::BUILD_VECTOR);
1692 if (Subtarget->is64Bit())
1693 setTargetDAGCombine(ISD::MUL);
1694 setTargetDAGCombine(ISD::XOR);
1696 computeRegisterProperties();
1698 // On Darwin, -Os means optimize for size without hurting performance,
1699 // do not reduce the limit.
1700 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1701 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1702 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1703 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1704 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1705 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1706 setPrefLoopAlignment(4); // 2^4 bytes.
1708 // Predictable cmov don't hurt on atom because it's in-order.
1709 PredictableSelectIsExpensive = !Subtarget->isAtom();
1710 EnableExtLdPromotion = true;
1711 setPrefFunctionAlignment(4); // 2^4 bytes.
1713 verifyIntrinsicTables();
1716 // This has so far only been implemented for 64-bit MachO.
1717 bool X86TargetLowering::useLoadStackGuardNode() const {
1718 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1721 TargetLoweringBase::LegalizeTypeAction
1722 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1723 if (ExperimentalVectorWideningLegalization &&
1724 VT.getVectorNumElements() != 1 &&
1725 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1726 return TypeWidenVector;
1728 return TargetLoweringBase::getPreferredVectorAction(VT);
1731 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1733 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1735 const unsigned NumElts = VT.getVectorNumElements();
1736 const EVT EltVT = VT.getVectorElementType();
1737 if (VT.is512BitVector()) {
1738 if (Subtarget->hasAVX512())
1739 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1740 EltVT == MVT::f32 || EltVT == MVT::f64)
1742 case 8: return MVT::v8i1;
1743 case 16: return MVT::v16i1;
1745 if (Subtarget->hasBWI())
1746 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1748 case 32: return MVT::v32i1;
1749 case 64: return MVT::v64i1;
1753 if (VT.is256BitVector() || VT.is128BitVector()) {
1754 if (Subtarget->hasVLX())
1755 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1756 EltVT == MVT::f32 || EltVT == MVT::f64)
1758 case 2: return MVT::v2i1;
1759 case 4: return MVT::v4i1;
1760 case 8: return MVT::v8i1;
1762 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1763 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1765 case 8: return MVT::v8i1;
1766 case 16: return MVT::v16i1;
1767 case 32: return MVT::v32i1;
1771 return VT.changeVectorElementTypeToInteger();
1774 /// Helper for getByValTypeAlignment to determine
1775 /// the desired ByVal argument alignment.
1776 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1779 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1780 if (VTy->getBitWidth() == 128)
1782 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1783 unsigned EltAlign = 0;
1784 getMaxByValAlign(ATy->getElementType(), EltAlign);
1785 if (EltAlign > MaxAlign)
1786 MaxAlign = EltAlign;
1787 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1788 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1789 unsigned EltAlign = 0;
1790 getMaxByValAlign(STy->getElementType(i), EltAlign);
1791 if (EltAlign > MaxAlign)
1792 MaxAlign = EltAlign;
1799 /// Return the desired alignment for ByVal aggregate
1800 /// function arguments in the caller parameter area. For X86, aggregates
1801 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1802 /// are at 4-byte boundaries.
1803 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1804 if (Subtarget->is64Bit()) {
1805 // Max of 8 and alignment of type.
1806 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1813 if (Subtarget->hasSSE1())
1814 getMaxByValAlign(Ty, Align);
1818 /// Returns the target specific optimal type for load
1819 /// and store operations as a result of memset, memcpy, and memmove
1820 /// lowering. If DstAlign is zero that means it's safe to destination
1821 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1822 /// means there isn't a need to check it against alignment requirement,
1823 /// probably because the source does not need to be loaded. If 'IsMemset' is
1824 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1825 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1826 /// source is constant so it does not need to be loaded.
1827 /// It returns EVT::Other if the type should be determined using generic
1828 /// target-independent logic.
1830 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1831 unsigned DstAlign, unsigned SrcAlign,
1832 bool IsMemset, bool ZeroMemset,
1834 MachineFunction &MF) const {
1835 const Function *F = MF.getFunction();
1836 if ((!IsMemset || ZeroMemset) &&
1837 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1838 Attribute::NoImplicitFloat)) {
1840 (Subtarget->isUnalignedMemAccessFast() ||
1841 ((DstAlign == 0 || DstAlign >= 16) &&
1842 (SrcAlign == 0 || SrcAlign >= 16)))) {
1844 if (Subtarget->hasInt256())
1846 if (Subtarget->hasFp256())
1849 if (Subtarget->hasSSE2())
1851 if (Subtarget->hasSSE1())
1853 } else if (!MemcpyStrSrc && Size >= 8 &&
1854 !Subtarget->is64Bit() &&
1855 Subtarget->hasSSE2()) {
1856 // Do not use f64 to lower memcpy if source is string constant. It's
1857 // better to use i32 to avoid the loads.
1861 if (Subtarget->is64Bit() && Size >= 8)
1866 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1868 return X86ScalarSSEf32;
1869 else if (VT == MVT::f64)
1870 return X86ScalarSSEf64;
1875 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1880 *Fast = Subtarget->isUnalignedMemAccessFast();
1884 /// Return the entry encoding for a jump table in the
1885 /// current function. The returned value is a member of the
1886 /// MachineJumpTableInfo::JTEntryKind enum.
1887 unsigned X86TargetLowering::getJumpTableEncoding() const {
1888 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1890 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1891 Subtarget->isPICStyleGOT())
1892 return MachineJumpTableInfo::EK_Custom32;
1894 // Otherwise, use the normal jump table encoding heuristics.
1895 return TargetLowering::getJumpTableEncoding();
1899 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1900 const MachineBasicBlock *MBB,
1901 unsigned uid,MCContext &Ctx) const{
1902 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1903 Subtarget->isPICStyleGOT());
1904 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1906 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1907 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1910 /// Returns relocation base for the given PIC jumptable.
1911 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1912 SelectionDAG &DAG) const {
1913 if (!Subtarget->is64Bit())
1914 // This doesn't have SDLoc associated with it, but is not really the
1915 // same as a Register.
1916 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1920 /// This returns the relocation base for the given PIC jumptable,
1921 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1922 const MCExpr *X86TargetLowering::
1923 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1924 MCContext &Ctx) const {
1925 // X86-64 uses RIP relative addressing based on the jump table label.
1926 if (Subtarget->isPICStyleRIPRel())
1927 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1929 // Otherwise, the reference is relative to the PIC base.
1930 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1933 // FIXME: Why this routine is here? Move to RegInfo!
1934 std::pair<const TargetRegisterClass*, uint8_t>
1935 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1936 const TargetRegisterClass *RRC = nullptr;
1938 switch (VT.SimpleTy) {
1940 return TargetLowering::findRepresentativeClass(VT);
1941 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1942 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1945 RRC = &X86::VR64RegClass;
1947 case MVT::f32: case MVT::f64:
1948 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1949 case MVT::v4f32: case MVT::v2f64:
1950 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1952 RRC = &X86::VR128RegClass;
1955 return std::make_pair(RRC, Cost);
1958 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1959 unsigned &Offset) const {
1960 if (!Subtarget->isTargetLinux())
1963 if (Subtarget->is64Bit()) {
1964 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1966 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1978 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1979 unsigned DestAS) const {
1980 assert(SrcAS != DestAS && "Expected different address spaces!");
1982 return SrcAS < 256 && DestAS < 256;
1985 //===----------------------------------------------------------------------===//
1986 // Return Value Calling Convention Implementation
1987 //===----------------------------------------------------------------------===//
1989 #include "X86GenCallingConv.inc"
1992 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1993 MachineFunction &MF, bool isVarArg,
1994 const SmallVectorImpl<ISD::OutputArg> &Outs,
1995 LLVMContext &Context) const {
1996 SmallVector<CCValAssign, 16> RVLocs;
1997 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1998 return CCInfo.CheckReturn(Outs, RetCC_X86);
2001 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2002 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2007 X86TargetLowering::LowerReturn(SDValue Chain,
2008 CallingConv::ID CallConv, bool isVarArg,
2009 const SmallVectorImpl<ISD::OutputArg> &Outs,
2010 const SmallVectorImpl<SDValue> &OutVals,
2011 SDLoc dl, SelectionDAG &DAG) const {
2012 MachineFunction &MF = DAG.getMachineFunction();
2013 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2015 SmallVector<CCValAssign, 16> RVLocs;
2016 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2017 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2020 SmallVector<SDValue, 6> RetOps;
2021 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2022 // Operand #1 = Bytes To Pop
2023 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2026 // Copy the result values into the output registers.
2027 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2028 CCValAssign &VA = RVLocs[i];
2029 assert(VA.isRegLoc() && "Can only return in registers!");
2030 SDValue ValToCopy = OutVals[i];
2031 EVT ValVT = ValToCopy.getValueType();
2033 // Promote values to the appropriate types.
2034 if (VA.getLocInfo() == CCValAssign::SExt)
2035 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2036 else if (VA.getLocInfo() == CCValAssign::ZExt)
2037 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2038 else if (VA.getLocInfo() == CCValAssign::AExt)
2039 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2040 else if (VA.getLocInfo() == CCValAssign::BCvt)
2041 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2043 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2044 "Unexpected FP-extend for return value.");
2046 // If this is x86-64, and we disabled SSE, we can't return FP values,
2047 // or SSE or MMX vectors.
2048 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2049 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2050 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2051 report_fatal_error("SSE register return with SSE disabled");
2053 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2054 // llvm-gcc has never done it right and no one has noticed, so this
2055 // should be OK for now.
2056 if (ValVT == MVT::f64 &&
2057 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2058 report_fatal_error("SSE2 register return with SSE2 disabled");
2060 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2061 // the RET instruction and handled by the FP Stackifier.
2062 if (VA.getLocReg() == X86::FP0 ||
2063 VA.getLocReg() == X86::FP1) {
2064 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2065 // change the value to the FP stack register class.
2066 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2067 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2068 RetOps.push_back(ValToCopy);
2069 // Don't emit a copytoreg.
2073 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2074 // which is returned in RAX / RDX.
2075 if (Subtarget->is64Bit()) {
2076 if (ValVT == MVT::x86mmx) {
2077 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2078 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2079 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2081 // If we don't have SSE2 available, convert to v4f32 so the generated
2082 // register is legal.
2083 if (!Subtarget->hasSSE2())
2084 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2089 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2090 Flag = Chain.getValue(1);
2091 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2094 // The x86-64 ABIs require that for returning structs by value we copy
2095 // the sret argument into %rax/%eax (depending on ABI) for the return.
2096 // Win32 requires us to put the sret argument to %eax as well.
2097 // We saved the argument into a virtual register in the entry block,
2098 // so now we copy the value out and into %rax/%eax.
2099 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2100 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2101 MachineFunction &MF = DAG.getMachineFunction();
2102 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2103 unsigned Reg = FuncInfo->getSRetReturnReg();
2105 "SRetReturnReg should have been set in LowerFormalArguments().");
2106 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2109 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2110 X86::RAX : X86::EAX;
2111 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2112 Flag = Chain.getValue(1);
2114 // RAX/EAX now acts like a return value.
2115 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2118 RetOps[0] = Chain; // Update chain.
2120 // Add the flag if we have it.
2122 RetOps.push_back(Flag);
2124 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2127 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2128 if (N->getNumValues() != 1)
2130 if (!N->hasNUsesOfValue(1, 0))
2133 SDValue TCChain = Chain;
2134 SDNode *Copy = *N->use_begin();
2135 if (Copy->getOpcode() == ISD::CopyToReg) {
2136 // If the copy has a glue operand, we conservatively assume it isn't safe to
2137 // perform a tail call.
2138 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2140 TCChain = Copy->getOperand(0);
2141 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2144 bool HasRet = false;
2145 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2147 if (UI->getOpcode() != X86ISD::RET_FLAG)
2149 // If we are returning more than one value, we can definitely
2150 // not make a tail call see PR19530
2151 if (UI->getNumOperands() > 4)
2153 if (UI->getNumOperands() == 4 &&
2154 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2167 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2168 ISD::NodeType ExtendKind) const {
2170 // TODO: Is this also valid on 32-bit?
2171 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2172 ReturnMVT = MVT::i8;
2174 ReturnMVT = MVT::i32;
2176 EVT MinVT = getRegisterType(Context, ReturnMVT);
2177 return VT.bitsLT(MinVT) ? MinVT : VT;
2180 /// Lower the result values of a call into the
2181 /// appropriate copies out of appropriate physical registers.
2184 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2185 CallingConv::ID CallConv, bool isVarArg,
2186 const SmallVectorImpl<ISD::InputArg> &Ins,
2187 SDLoc dl, SelectionDAG &DAG,
2188 SmallVectorImpl<SDValue> &InVals) const {
2190 // Assign locations to each value returned by this call.
2191 SmallVector<CCValAssign, 16> RVLocs;
2192 bool Is64Bit = Subtarget->is64Bit();
2193 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2195 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2197 // Copy all of the result registers out of their specified physreg.
2198 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2199 CCValAssign &VA = RVLocs[i];
2200 EVT CopyVT = VA.getValVT();
2202 // If this is x86-64, and we disabled SSE, we can't return FP values
2203 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2204 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2205 report_fatal_error("SSE register return with SSE disabled");
2208 // If we prefer to use the value in xmm registers, copy it out as f80 and
2209 // use a truncate to move it from fp stack reg to xmm reg.
2210 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2211 isScalarFPTypeInSSEReg(VA.getValVT()))
2214 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2215 CopyVT, InFlag).getValue(1);
2216 SDValue Val = Chain.getValue(0);
2218 if (CopyVT != VA.getValVT())
2219 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2220 // This truncation won't change the value.
2221 DAG.getIntPtrConstant(1));
2223 InFlag = Chain.getValue(2);
2224 InVals.push_back(Val);
2230 //===----------------------------------------------------------------------===//
2231 // C & StdCall & Fast Calling Convention implementation
2232 //===----------------------------------------------------------------------===//
2233 // StdCall calling convention seems to be standard for many Windows' API
2234 // routines and around. It differs from C calling convention just a little:
2235 // callee should clean up the stack, not caller. Symbols should be also
2236 // decorated in some fancy way :) It doesn't support any vector arguments.
2237 // For info on fast calling convention see Fast Calling Convention (tail call)
2238 // implementation LowerX86_32FastCCCallTo.
2240 /// CallIsStructReturn - Determines whether a call uses struct return
2242 enum StructReturnType {
2247 static StructReturnType
2248 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2250 return NotStructReturn;
2252 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2253 if (!Flags.isSRet())
2254 return NotStructReturn;
2255 if (Flags.isInReg())
2256 return RegStructReturn;
2257 return StackStructReturn;
2260 /// Determines whether a function uses struct return semantics.
2261 static StructReturnType
2262 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2264 return NotStructReturn;
2266 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2267 if (!Flags.isSRet())
2268 return NotStructReturn;
2269 if (Flags.isInReg())
2270 return RegStructReturn;
2271 return StackStructReturn;
2274 /// Make a copy of an aggregate at address specified by "Src" to address
2275 /// "Dst" with size and alignment information specified by the specific
2276 /// parameter attribute. The copy will be passed as a byval function parameter.
2278 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2279 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2281 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2283 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2284 /*isVolatile*/false, /*AlwaysInline=*/true,
2285 MachinePointerInfo(), MachinePointerInfo());
2288 /// Return true if the calling convention is one that
2289 /// supports tail call optimization.
2290 static bool IsTailCallConvention(CallingConv::ID CC) {
2291 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2292 CC == CallingConv::HiPE);
2295 /// \brief Return true if the calling convention is a C calling convention.
2296 static bool IsCCallConvention(CallingConv::ID CC) {
2297 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2298 CC == CallingConv::X86_64_SysV);
2301 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2302 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2306 CallingConv::ID CalleeCC = CS.getCallingConv();
2307 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2313 /// Return true if the function is being made into
2314 /// a tailcall target by changing its ABI.
2315 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2316 bool GuaranteedTailCallOpt) {
2317 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2321 X86TargetLowering::LowerMemArgument(SDValue Chain,
2322 CallingConv::ID CallConv,
2323 const SmallVectorImpl<ISD::InputArg> &Ins,
2324 SDLoc dl, SelectionDAG &DAG,
2325 const CCValAssign &VA,
2326 MachineFrameInfo *MFI,
2328 // Create the nodes corresponding to a load from this parameter slot.
2329 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2330 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2331 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2332 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2335 // If value is passed by pointer we have address passed instead of the value
2337 if (VA.getLocInfo() == CCValAssign::Indirect)
2338 ValVT = VA.getLocVT();
2340 ValVT = VA.getValVT();
2342 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2343 // changed with more analysis.
2344 // In case of tail call optimization mark all arguments mutable. Since they
2345 // could be overwritten by lowering of arguments in case of a tail call.
2346 if (Flags.isByVal()) {
2347 unsigned Bytes = Flags.getByValSize();
2348 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2349 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2350 return DAG.getFrameIndex(FI, getPointerTy());
2352 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2353 VA.getLocMemOffset(), isImmutable);
2354 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2355 return DAG.getLoad(ValVT, dl, Chain, FIN,
2356 MachinePointerInfo::getFixedStack(FI),
2357 false, false, false, 0);
2361 // FIXME: Get this from tablegen.
2362 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2363 const X86Subtarget *Subtarget) {
2364 assert(Subtarget->is64Bit());
2366 if (Subtarget->isCallingConvWin64(CallConv)) {
2367 static const MCPhysReg GPR64ArgRegsWin64[] = {
2368 X86::RCX, X86::RDX, X86::R8, X86::R9
2370 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2373 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2374 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2376 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2379 // FIXME: Get this from tablegen.
2380 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2381 CallingConv::ID CallConv,
2382 const X86Subtarget *Subtarget) {
2383 assert(Subtarget->is64Bit());
2384 if (Subtarget->isCallingConvWin64(CallConv)) {
2385 // The XMM registers which might contain var arg parameters are shadowed
2386 // in their paired GPR. So we only need to save the GPR to their home
2388 // TODO: __vectorcall will change this.
2392 const Function *Fn = MF.getFunction();
2393 bool NoImplicitFloatOps = Fn->getAttributes().
2394 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2395 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2396 "SSE register cannot be used when SSE is disabled!");
2397 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2398 !Subtarget->hasSSE1())
2399 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2403 static const MCPhysReg XMMArgRegs64Bit[] = {
2404 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2405 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2407 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2411 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2412 CallingConv::ID CallConv,
2414 const SmallVectorImpl<ISD::InputArg> &Ins,
2417 SmallVectorImpl<SDValue> &InVals)
2419 MachineFunction &MF = DAG.getMachineFunction();
2420 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2422 const Function* Fn = MF.getFunction();
2423 if (Fn->hasExternalLinkage() &&
2424 Subtarget->isTargetCygMing() &&
2425 Fn->getName() == "main")
2426 FuncInfo->setForceFramePointer(true);
2428 MachineFrameInfo *MFI = MF.getFrameInfo();
2429 bool Is64Bit = Subtarget->is64Bit();
2430 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2432 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2433 "Var args not supported with calling convention fastcc, ghc or hipe");
2435 // Assign locations to all of the incoming arguments.
2436 SmallVector<CCValAssign, 16> ArgLocs;
2437 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2439 // Allocate shadow area for Win64
2441 CCInfo.AllocateStack(32, 8);
2443 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2445 unsigned LastVal = ~0U;
2447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2448 CCValAssign &VA = ArgLocs[i];
2449 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2451 assert(VA.getValNo() != LastVal &&
2452 "Don't support value assigned to multiple locs yet");
2454 LastVal = VA.getValNo();
2456 if (VA.isRegLoc()) {
2457 EVT RegVT = VA.getLocVT();
2458 const TargetRegisterClass *RC;
2459 if (RegVT == MVT::i32)
2460 RC = &X86::GR32RegClass;
2461 else if (Is64Bit && RegVT == MVT::i64)
2462 RC = &X86::GR64RegClass;
2463 else if (RegVT == MVT::f32)
2464 RC = &X86::FR32RegClass;
2465 else if (RegVT == MVT::f64)
2466 RC = &X86::FR64RegClass;
2467 else if (RegVT.is512BitVector())
2468 RC = &X86::VR512RegClass;
2469 else if (RegVT.is256BitVector())
2470 RC = &X86::VR256RegClass;
2471 else if (RegVT.is128BitVector())
2472 RC = &X86::VR128RegClass;
2473 else if (RegVT == MVT::x86mmx)
2474 RC = &X86::VR64RegClass;
2475 else if (RegVT == MVT::i1)
2476 RC = &X86::VK1RegClass;
2477 else if (RegVT == MVT::v8i1)
2478 RC = &X86::VK8RegClass;
2479 else if (RegVT == MVT::v16i1)
2480 RC = &X86::VK16RegClass;
2481 else if (RegVT == MVT::v32i1)
2482 RC = &X86::VK32RegClass;
2483 else if (RegVT == MVT::v64i1)
2484 RC = &X86::VK64RegClass;
2486 llvm_unreachable("Unknown argument type!");
2488 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2489 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2491 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2492 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2494 if (VA.getLocInfo() == CCValAssign::SExt)
2495 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2496 DAG.getValueType(VA.getValVT()));
2497 else if (VA.getLocInfo() == CCValAssign::ZExt)
2498 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2499 DAG.getValueType(VA.getValVT()));
2500 else if (VA.getLocInfo() == CCValAssign::BCvt)
2501 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2503 if (VA.isExtInLoc()) {
2504 // Handle MMX values passed in XMM regs.
2505 if (RegVT.isVector())
2506 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2508 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2511 assert(VA.isMemLoc());
2512 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2515 // If value is passed via pointer - do a load.
2516 if (VA.getLocInfo() == CCValAssign::Indirect)
2517 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2518 MachinePointerInfo(), false, false, false, 0);
2520 InVals.push_back(ArgValue);
2523 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2524 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2525 // The x86-64 ABIs require that for returning structs by value we copy
2526 // the sret argument into %rax/%eax (depending on ABI) for the return.
2527 // Win32 requires us to put the sret argument to %eax as well.
2528 // Save the argument into a virtual register so that we can access it
2529 // from the return points.
2530 if (Ins[i].Flags.isSRet()) {
2531 unsigned Reg = FuncInfo->getSRetReturnReg();
2533 MVT PtrTy = getPointerTy();
2534 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2535 FuncInfo->setSRetReturnReg(Reg);
2537 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2544 unsigned StackSize = CCInfo.getNextStackOffset();
2545 // Align stack specially for tail calls.
2546 if (FuncIsMadeTailCallSafe(CallConv,
2547 MF.getTarget().Options.GuaranteedTailCallOpt))
2548 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2550 // If the function takes variable number of arguments, make a frame index for
2551 // the start of the first vararg value... for expansion of llvm.va_start. We
2552 // can skip this if there are no va_start calls.
2553 if (MFI->hasVAStart() &&
2554 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2555 CallConv != CallingConv::X86_ThisCall))) {
2556 FuncInfo->setVarArgsFrameIndex(
2557 MFI->CreateFixedObject(1, StackSize, true));
2560 // Figure out if XMM registers are in use.
2561 assert(!(MF.getTarget().Options.UseSoftFloat &&
2562 Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2563 Attribute::NoImplicitFloat)) &&
2564 "SSE register cannot be used when SSE is disabled!");
2566 // 64-bit calling conventions support varargs and register parameters, so we
2567 // have to do extra work to spill them in the prologue.
2568 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2569 // Find the first unallocated argument registers.
2570 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2571 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2572 unsigned NumIntRegs =
2573 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2574 unsigned NumXMMRegs =
2575 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2576 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2577 "SSE register cannot be used when SSE is disabled!");
2579 // Gather all the live in physical registers.
2580 SmallVector<SDValue, 6> LiveGPRs;
2581 SmallVector<SDValue, 8> LiveXMMRegs;
2583 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2584 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2586 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2588 if (!ArgXMMs.empty()) {
2589 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2590 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2591 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2592 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2593 LiveXMMRegs.push_back(
2594 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2599 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2600 // Get to the caller-allocated home save location. Add 8 to account
2601 // for the return address.
2602 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2603 FuncInfo->setRegSaveFrameIndex(
2604 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2605 // Fixup to set vararg frame on shadow area (4 x i64).
2607 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2609 // For X86-64, if there are vararg parameters that are passed via
2610 // registers, then we must store them to their spots on the stack so
2611 // they may be loaded by deferencing the result of va_next.
2612 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2613 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2614 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2615 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2618 // Store the integer parameter registers.
2619 SmallVector<SDValue, 8> MemOps;
2620 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2622 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2623 for (SDValue Val : LiveGPRs) {
2624 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2625 DAG.getIntPtrConstant(Offset));
2627 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2628 MachinePointerInfo::getFixedStack(
2629 FuncInfo->getRegSaveFrameIndex(), Offset),
2631 MemOps.push_back(Store);
2635 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2636 // Now store the XMM (fp + vector) parameter registers.
2637 SmallVector<SDValue, 12> SaveXMMOps;
2638 SaveXMMOps.push_back(Chain);
2639 SaveXMMOps.push_back(ALVal);
2640 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2641 FuncInfo->getRegSaveFrameIndex()));
2642 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2643 FuncInfo->getVarArgsFPOffset()));
2644 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2646 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2647 MVT::Other, SaveXMMOps));
2650 if (!MemOps.empty())
2651 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2654 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2655 // Find the largest legal vector type.
2656 MVT VecVT = MVT::Other;
2657 // FIXME: Only some x86_32 calling conventions support AVX512.
2658 if (Subtarget->hasAVX512() &&
2659 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2660 CallConv == CallingConv::Intel_OCL_BI)))
2661 VecVT = MVT::v16f32;
2662 else if (Subtarget->hasAVX())
2664 else if (Subtarget->hasSSE2())
2667 // We forward some GPRs and some vector types.
2668 SmallVector<MVT, 2> RegParmTypes;
2669 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2670 RegParmTypes.push_back(IntVT);
2671 if (VecVT != MVT::Other)
2672 RegParmTypes.push_back(VecVT);
2674 // Compute the set of forwarded registers. The rest are scratch.
2675 SmallVectorImpl<ForwardedRegister> &Forwards =
2676 FuncInfo->getForwardedMustTailRegParms();
2677 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2679 // Conservatively forward AL on x86_64, since it might be used for varargs.
2680 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2681 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2682 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2685 // Copy all forwards from physical to virtual registers.
2686 for (ForwardedRegister &F : Forwards) {
2687 // FIXME: Can we use a less constrained schedule?
2688 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2689 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2690 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2694 // Some CCs need callee pop.
2695 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2696 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2697 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2699 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2700 // If this is an sret function, the return should pop the hidden pointer.
2701 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2702 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2703 argsAreStructReturn(Ins) == StackStructReturn)
2704 FuncInfo->setBytesToPopOnReturn(4);
2708 // RegSaveFrameIndex is X86-64 only.
2709 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2710 if (CallConv == CallingConv::X86_FastCall ||
2711 CallConv == CallingConv::X86_ThisCall)
2712 // fastcc functions can't have varargs.
2713 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2716 FuncInfo->setArgumentStackSize(StackSize);
2722 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2723 SDValue StackPtr, SDValue Arg,
2724 SDLoc dl, SelectionDAG &DAG,
2725 const CCValAssign &VA,
2726 ISD::ArgFlagsTy Flags) const {
2727 unsigned LocMemOffset = VA.getLocMemOffset();
2728 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2729 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2730 if (Flags.isByVal())
2731 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2733 return DAG.getStore(Chain, dl, Arg, PtrOff,
2734 MachinePointerInfo::getStack(LocMemOffset),
2738 /// Emit a load of return address if tail call
2739 /// optimization is performed and it is required.
2741 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2742 SDValue &OutRetAddr, SDValue Chain,
2743 bool IsTailCall, bool Is64Bit,
2744 int FPDiff, SDLoc dl) const {
2745 // Adjust the Return address stack slot.
2746 EVT VT = getPointerTy();
2747 OutRetAddr = getReturnAddressFrameIndex(DAG);
2749 // Load the "old" Return address.
2750 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2751 false, false, false, 0);
2752 return SDValue(OutRetAddr.getNode(), 1);
2755 /// Emit a store of the return address if tail call
2756 /// optimization is performed and it is required (FPDiff!=0).
2757 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2758 SDValue Chain, SDValue RetAddrFrIdx,
2759 EVT PtrVT, unsigned SlotSize,
2760 int FPDiff, SDLoc dl) {
2761 // Store the return address to the appropriate stack slot.
2762 if (!FPDiff) return Chain;
2763 // Calculate the new stack slot for the return address.
2764 int NewReturnAddrFI =
2765 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2767 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2768 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2769 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2775 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2776 SmallVectorImpl<SDValue> &InVals) const {
2777 SelectionDAG &DAG = CLI.DAG;
2779 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2780 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2781 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2782 SDValue Chain = CLI.Chain;
2783 SDValue Callee = CLI.Callee;
2784 CallingConv::ID CallConv = CLI.CallConv;
2785 bool &isTailCall = CLI.IsTailCall;
2786 bool isVarArg = CLI.IsVarArg;
2788 MachineFunction &MF = DAG.getMachineFunction();
2789 bool Is64Bit = Subtarget->is64Bit();
2790 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2791 StructReturnType SR = callIsStructReturn(Outs);
2792 bool IsSibcall = false;
2793 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2795 if (MF.getTarget().Options.DisableTailCalls)
2798 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2800 // Force this to be a tail call. The verifier rules are enough to ensure
2801 // that we can lower this successfully without moving the return address
2804 } else if (isTailCall) {
2805 // Check if it's really possible to do a tail call.
2806 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2807 isVarArg, SR != NotStructReturn,
2808 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2809 Outs, OutVals, Ins, DAG);
2811 // Sibcalls are automatically detected tailcalls which do not require
2813 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2820 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2821 "Var args not supported with calling convention fastcc, ghc or hipe");
2823 // Analyze operands of the call, assigning locations to each operand.
2824 SmallVector<CCValAssign, 16> ArgLocs;
2825 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2827 // Allocate shadow area for Win64
2829 CCInfo.AllocateStack(32, 8);
2831 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2833 // Get a count of how many bytes are to be pushed on the stack.
2834 unsigned NumBytes = CCInfo.getNextStackOffset();
2836 // This is a sibcall. The memory operands are available in caller's
2837 // own caller's stack.
2839 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2840 IsTailCallConvention(CallConv))
2841 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2844 if (isTailCall && !IsSibcall && !IsMustTail) {
2845 // Lower arguments at fp - stackoffset + fpdiff.
2846 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2848 FPDiff = NumBytesCallerPushed - NumBytes;
2850 // Set the delta of movement of the returnaddr stackslot.
2851 // But only set if delta is greater than previous delta.
2852 if (FPDiff < X86Info->getTCReturnAddrDelta())
2853 X86Info->setTCReturnAddrDelta(FPDiff);
2856 unsigned NumBytesToPush = NumBytes;
2857 unsigned NumBytesToPop = NumBytes;
2859 // If we have an inalloca argument, all stack space has already been allocated
2860 // for us and be right at the top of the stack. We don't support multiple
2861 // arguments passed in memory when using inalloca.
2862 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2864 if (!ArgLocs.back().isMemLoc())
2865 report_fatal_error("cannot use inalloca attribute on a register "
2867 if (ArgLocs.back().getLocMemOffset() != 0)
2868 report_fatal_error("any parameter with the inalloca attribute must be "
2869 "the only memory argument");
2873 Chain = DAG.getCALLSEQ_START(
2874 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2876 SDValue RetAddrFrIdx;
2877 // Load return address for tail calls.
2878 if (isTailCall && FPDiff)
2879 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2880 Is64Bit, FPDiff, dl);
2882 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2883 SmallVector<SDValue, 8> MemOpChains;
2886 // Walk the register/memloc assignments, inserting copies/loads. In the case
2887 // of tail call optimization arguments are handle later.
2888 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2889 DAG.getSubtarget().getRegisterInfo());
2890 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2891 // Skip inalloca arguments, they have already been written.
2892 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2893 if (Flags.isInAlloca())
2896 CCValAssign &VA = ArgLocs[i];
2897 EVT RegVT = VA.getLocVT();
2898 SDValue Arg = OutVals[i];
2899 bool isByVal = Flags.isByVal();
2901 // Promote the value if needed.
2902 switch (VA.getLocInfo()) {
2903 default: llvm_unreachable("Unknown loc info!");
2904 case CCValAssign::Full: break;
2905 case CCValAssign::SExt:
2906 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2908 case CCValAssign::ZExt:
2909 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2911 case CCValAssign::AExt:
2912 if (RegVT.is128BitVector()) {
2913 // Special case: passing MMX values in XMM registers.
2914 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2915 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2916 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2918 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2920 case CCValAssign::BCvt:
2921 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2923 case CCValAssign::Indirect: {
2924 // Store the argument.
2925 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2926 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2927 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2928 MachinePointerInfo::getFixedStack(FI),
2935 if (VA.isRegLoc()) {
2936 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2937 if (isVarArg && IsWin64) {
2938 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2939 // shadow reg if callee is a varargs function.
2940 unsigned ShadowReg = 0;
2941 switch (VA.getLocReg()) {
2942 case X86::XMM0: ShadowReg = X86::RCX; break;
2943 case X86::XMM1: ShadowReg = X86::RDX; break;
2944 case X86::XMM2: ShadowReg = X86::R8; break;
2945 case X86::XMM3: ShadowReg = X86::R9; break;
2948 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2950 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2951 assert(VA.isMemLoc());
2952 if (!StackPtr.getNode())
2953 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2955 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2956 dl, DAG, VA, Flags));
2960 if (!MemOpChains.empty())
2961 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2963 if (Subtarget->isPICStyleGOT()) {
2964 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2967 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2968 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2970 // If we are tail calling and generating PIC/GOT style code load the
2971 // address of the callee into ECX. The value in ecx is used as target of
2972 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2973 // for tail calls on PIC/GOT architectures. Normally we would just put the
2974 // address of GOT into ebx and then call target@PLT. But for tail calls
2975 // ebx would be restored (since ebx is callee saved) before jumping to the
2978 // Note: The actual moving to ECX is done further down.
2979 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2980 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2981 !G->getGlobal()->hasProtectedVisibility())
2982 Callee = LowerGlobalAddress(Callee, DAG);
2983 else if (isa<ExternalSymbolSDNode>(Callee))
2984 Callee = LowerExternalSymbol(Callee, DAG);
2988 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2989 // From AMD64 ABI document:
2990 // For calls that may call functions that use varargs or stdargs
2991 // (prototype-less calls or calls to functions containing ellipsis (...) in
2992 // the declaration) %al is used as hidden argument to specify the number
2993 // of SSE registers used. The contents of %al do not need to match exactly
2994 // the number of registers, but must be an ubound on the number of SSE
2995 // registers used and is in the range 0 - 8 inclusive.
2997 // Count the number of XMM registers allocated.
2998 static const MCPhysReg XMMArgRegs[] = {
2999 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3000 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3002 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
3003 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3004 && "SSE registers cannot be used when SSE is disabled");
3006 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3007 DAG.getConstant(NumXMMRegs, MVT::i8)));
3010 if (isVarArg && IsMustTail) {
3011 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3012 for (const auto &F : Forwards) {
3013 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3014 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3018 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3019 // don't need this because the eligibility check rejects calls that require
3020 // shuffling arguments passed in memory.
3021 if (!IsSibcall && isTailCall) {
3022 // Force all the incoming stack arguments to be loaded from the stack
3023 // before any new outgoing arguments are stored to the stack, because the
3024 // outgoing stack slots may alias the incoming argument stack slots, and
3025 // the alias isn't otherwise explicit. This is slightly more conservative
3026 // than necessary, because it means that each store effectively depends
3027 // on every argument instead of just those arguments it would clobber.
3028 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3030 SmallVector<SDValue, 8> MemOpChains2;
3033 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3034 CCValAssign &VA = ArgLocs[i];
3037 assert(VA.isMemLoc());
3038 SDValue Arg = OutVals[i];
3039 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3040 // Skip inalloca arguments. They don't require any work.
3041 if (Flags.isInAlloca())
3043 // Create frame index.
3044 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3045 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3046 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3047 FIN = DAG.getFrameIndex(FI, getPointerTy());
3049 if (Flags.isByVal()) {
3050 // Copy relative to framepointer.
3051 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3052 if (!StackPtr.getNode())
3053 StackPtr = DAG.getCopyFromReg(Chain, dl,
3054 RegInfo->getStackRegister(),
3056 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3058 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3062 // Store relative to framepointer.
3063 MemOpChains2.push_back(
3064 DAG.getStore(ArgChain, dl, Arg, FIN,
3065 MachinePointerInfo::getFixedStack(FI),
3070 if (!MemOpChains2.empty())
3071 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3073 // Store the return address to the appropriate stack slot.
3074 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3075 getPointerTy(), RegInfo->getSlotSize(),
3079 // Build a sequence of copy-to-reg nodes chained together with token chain
3080 // and flag operands which copy the outgoing args into registers.
3082 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3083 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3084 RegsToPass[i].second, InFlag);
3085 InFlag = Chain.getValue(1);
3088 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3089 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3090 // In the 64-bit large code model, we have to make all calls
3091 // through a register, since the call instruction's 32-bit
3092 // pc-relative offset may not be large enough to hold the whole
3094 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3095 // If the callee is a GlobalAddress node (quite common, every direct call
3096 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3098 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3100 // We should use extra load for direct calls to dllimported functions in
3102 const GlobalValue *GV = G->getGlobal();
3103 if (!GV->hasDLLImportStorageClass()) {
3104 unsigned char OpFlags = 0;
3105 bool ExtraLoad = false;
3106 unsigned WrapperKind = ISD::DELETED_NODE;
3108 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3109 // external symbols most go through the PLT in PIC mode. If the symbol
3110 // has hidden or protected visibility, or if it is static or local, then
3111 // we don't need to use the PLT - we can directly call it.
3112 if (Subtarget->isTargetELF() &&
3113 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3114 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3115 OpFlags = X86II::MO_PLT;
3116 } else if (Subtarget->isPICStyleStubAny() &&
3117 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3118 (!Subtarget->getTargetTriple().isMacOSX() ||
3119 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3120 // PC-relative references to external symbols should go through $stub,
3121 // unless we're building with the leopard linker or later, which
3122 // automatically synthesizes these stubs.
3123 OpFlags = X86II::MO_DARWIN_STUB;
3124 } else if (Subtarget->isPICStyleRIPRel() &&
3125 isa<Function>(GV) &&
3126 cast<Function>(GV)->getAttributes().
3127 hasAttribute(AttributeSet::FunctionIndex,
3128 Attribute::NonLazyBind)) {
3129 // If the function is marked as non-lazy, generate an indirect call
3130 // which loads from the GOT directly. This avoids runtime overhead
3131 // at the cost of eager binding (and one extra byte of encoding).
3132 OpFlags = X86II::MO_GOTPCREL;
3133 WrapperKind = X86ISD::WrapperRIP;
3137 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3138 G->getOffset(), OpFlags);
3140 // Add a wrapper if needed.
3141 if (WrapperKind != ISD::DELETED_NODE)
3142 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3143 // Add extra indirection if needed.
3145 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3146 MachinePointerInfo::getGOT(),
3147 false, false, false, 0);
3149 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3150 unsigned char OpFlags = 0;
3152 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3153 // external symbols should go through the PLT.
3154 if (Subtarget->isTargetELF() &&
3155 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3156 OpFlags = X86II::MO_PLT;
3157 } else if (Subtarget->isPICStyleStubAny() &&
3158 (!Subtarget->getTargetTriple().isMacOSX() ||
3159 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3160 // PC-relative references to external symbols should go through $stub,
3161 // unless we're building with the leopard linker or later, which
3162 // automatically synthesizes these stubs.
3163 OpFlags = X86II::MO_DARWIN_STUB;
3166 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3168 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3169 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3170 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3173 // Returns a chain & a flag for retval copy to use.
3174 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3175 SmallVector<SDValue, 8> Ops;
3177 if (!IsSibcall && isTailCall) {
3178 Chain = DAG.getCALLSEQ_END(Chain,
3179 DAG.getIntPtrConstant(NumBytesToPop, true),
3180 DAG.getIntPtrConstant(0, true), InFlag, dl);
3181 InFlag = Chain.getValue(1);
3184 Ops.push_back(Chain);
3185 Ops.push_back(Callee);
3188 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3190 // Add argument registers to the end of the list so that they are known live
3192 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3193 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3194 RegsToPass[i].second.getValueType()));
3196 // Add a register mask operand representing the call-preserved registers.
3197 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3198 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3199 assert(Mask && "Missing call preserved mask for calling convention");
3200 Ops.push_back(DAG.getRegisterMask(Mask));
3202 if (InFlag.getNode())
3203 Ops.push_back(InFlag);
3207 //// If this is the first return lowered for this function, add the regs
3208 //// to the liveout set for the function.
3209 // This isn't right, although it's probably harmless on x86; liveouts
3210 // should be computed from returns not tail calls. Consider a void
3211 // function making a tail call to a function returning int.
3212 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3215 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3216 InFlag = Chain.getValue(1);
3218 // Create the CALLSEQ_END node.
3219 unsigned NumBytesForCalleeToPop;
3220 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3221 DAG.getTarget().Options.GuaranteedTailCallOpt))
3222 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3223 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3224 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3225 SR == StackStructReturn)
3226 // If this is a call to a struct-return function, the callee
3227 // pops the hidden struct pointer, so we have to push it back.
3228 // This is common for Darwin/X86, Linux & Mingw32 targets.
3229 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3230 NumBytesForCalleeToPop = 4;
3232 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3234 // Returns a flag for retval copy to use.
3236 Chain = DAG.getCALLSEQ_END(Chain,
3237 DAG.getIntPtrConstant(NumBytesToPop, true),
3238 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3241 InFlag = Chain.getValue(1);
3244 // Handle result values, copying them out of physregs into vregs that we
3246 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3247 Ins, dl, DAG, InVals);
3250 //===----------------------------------------------------------------------===//
3251 // Fast Calling Convention (tail call) implementation
3252 //===----------------------------------------------------------------------===//
3254 // Like std call, callee cleans arguments, convention except that ECX is
3255 // reserved for storing the tail called function address. Only 2 registers are
3256 // free for argument passing (inreg). Tail call optimization is performed
3258 // * tailcallopt is enabled
3259 // * caller/callee are fastcc
3260 // On X86_64 architecture with GOT-style position independent code only local
3261 // (within module) calls are supported at the moment.
3262 // To keep the stack aligned according to platform abi the function
3263 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3264 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3265 // If a tail called function callee has more arguments than the caller the
3266 // caller needs to make sure that there is room to move the RETADDR to. This is
3267 // achieved by reserving an area the size of the argument delta right after the
3268 // original RETADDR, but before the saved framepointer or the spilled registers
3269 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3281 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3282 /// for a 16 byte align requirement.
3284 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3285 SelectionDAG& DAG) const {
3286 MachineFunction &MF = DAG.getMachineFunction();
3287 const TargetMachine &TM = MF.getTarget();
3288 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3289 TM.getSubtargetImpl()->getRegisterInfo());
3290 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3291 unsigned StackAlignment = TFI.getStackAlignment();
3292 uint64_t AlignMask = StackAlignment - 1;
3293 int64_t Offset = StackSize;
3294 unsigned SlotSize = RegInfo->getSlotSize();
3295 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3296 // Number smaller than 12 so just add the difference.
3297 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3299 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3300 Offset = ((~AlignMask) & Offset) + StackAlignment +
3301 (StackAlignment-SlotSize);
3306 /// MatchingStackOffset - Return true if the given stack call argument is
3307 /// already available in the same position (relatively) of the caller's
3308 /// incoming argument stack.
3310 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3311 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3312 const X86InstrInfo *TII) {
3313 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3315 if (Arg.getOpcode() == ISD::CopyFromReg) {
3316 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3317 if (!TargetRegisterInfo::isVirtualRegister(VR))
3319 MachineInstr *Def = MRI->getVRegDef(VR);
3322 if (!Flags.isByVal()) {
3323 if (!TII->isLoadFromStackSlot(Def, FI))
3326 unsigned Opcode = Def->getOpcode();
3327 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3328 Def->getOperand(1).isFI()) {
3329 FI = Def->getOperand(1).getIndex();
3330 Bytes = Flags.getByValSize();
3334 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3335 if (Flags.isByVal())
3336 // ByVal argument is passed in as a pointer but it's now being
3337 // dereferenced. e.g.
3338 // define @foo(%struct.X* %A) {
3339 // tail call @bar(%struct.X* byval %A)
3342 SDValue Ptr = Ld->getBasePtr();
3343 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3346 FI = FINode->getIndex();
3347 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3348 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3349 FI = FINode->getIndex();
3350 Bytes = Flags.getByValSize();
3354 assert(FI != INT_MAX);
3355 if (!MFI->isFixedObjectIndex(FI))
3357 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3360 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3361 /// for tail call optimization. Targets which want to do tail call
3362 /// optimization should implement this function.
3364 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3365 CallingConv::ID CalleeCC,
3367 bool isCalleeStructRet,
3368 bool isCallerStructRet,
3370 const SmallVectorImpl<ISD::OutputArg> &Outs,
3371 const SmallVectorImpl<SDValue> &OutVals,
3372 const SmallVectorImpl<ISD::InputArg> &Ins,
3373 SelectionDAG &DAG) const {
3374 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3377 // If -tailcallopt is specified, make fastcc functions tail-callable.
3378 const MachineFunction &MF = DAG.getMachineFunction();
3379 const Function *CallerF = MF.getFunction();
3381 // If the function return type is x86_fp80 and the callee return type is not,
3382 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3383 // perform a tailcall optimization here.
3384 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3387 CallingConv::ID CallerCC = CallerF->getCallingConv();
3388 bool CCMatch = CallerCC == CalleeCC;
3389 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3390 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3392 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3393 if (IsTailCallConvention(CalleeCC) && CCMatch)
3398 // Look for obvious safe cases to perform tail call optimization that do not
3399 // require ABI changes. This is what gcc calls sibcall.
3401 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3402 // emit a special epilogue.
3403 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3404 DAG.getSubtarget().getRegisterInfo());
3405 if (RegInfo->needsStackRealignment(MF))
3408 // Also avoid sibcall optimization if either caller or callee uses struct
3409 // return semantics.
3410 if (isCalleeStructRet || isCallerStructRet)
3413 // An stdcall/thiscall caller is expected to clean up its arguments; the
3414 // callee isn't going to do that.
3415 // FIXME: this is more restrictive than needed. We could produce a tailcall
3416 // when the stack adjustment matches. For example, with a thiscall that takes
3417 // only one argument.
3418 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3419 CallerCC == CallingConv::X86_ThisCall))
3422 // Do not sibcall optimize vararg calls unless all arguments are passed via
3424 if (isVarArg && !Outs.empty()) {
3426 // Optimizing for varargs on Win64 is unlikely to be safe without
3427 // additional testing.
3428 if (IsCalleeWin64 || IsCallerWin64)
3431 SmallVector<CCValAssign, 16> ArgLocs;
3432 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3435 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3436 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3437 if (!ArgLocs[i].isRegLoc())
3441 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3442 // stack. Therefore, if it's not used by the call it is not safe to optimize
3443 // this into a sibcall.
3444 bool Unused = false;
3445 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3452 SmallVector<CCValAssign, 16> RVLocs;
3453 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3455 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3456 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3457 CCValAssign &VA = RVLocs[i];
3458 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3463 // If the calling conventions do not match, then we'd better make sure the
3464 // results are returned in the same way as what the caller expects.
3466 SmallVector<CCValAssign, 16> RVLocs1;
3467 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3469 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3471 SmallVector<CCValAssign, 16> RVLocs2;
3472 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3474 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3476 if (RVLocs1.size() != RVLocs2.size())
3478 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3479 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3481 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3483 if (RVLocs1[i].isRegLoc()) {
3484 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3487 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3493 // If the callee takes no arguments then go on to check the results of the
3495 if (!Outs.empty()) {
3496 // Check if stack adjustment is needed. For now, do not do this if any
3497 // argument is passed on the stack.
3498 SmallVector<CCValAssign, 16> ArgLocs;
3499 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3502 // Allocate shadow area for Win64
3504 CCInfo.AllocateStack(32, 8);
3506 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3507 if (CCInfo.getNextStackOffset()) {
3508 MachineFunction &MF = DAG.getMachineFunction();
3509 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3512 // Check if the arguments are already laid out in the right way as
3513 // the caller's fixed stack objects.
3514 MachineFrameInfo *MFI = MF.getFrameInfo();
3515 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3516 const X86InstrInfo *TII =
3517 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3518 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3519 CCValAssign &VA = ArgLocs[i];
3520 SDValue Arg = OutVals[i];
3521 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3522 if (VA.getLocInfo() == CCValAssign::Indirect)
3524 if (!VA.isRegLoc()) {
3525 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3532 // If the tailcall address may be in a register, then make sure it's
3533 // possible to register allocate for it. In 32-bit, the call address can
3534 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3535 // callee-saved registers are restored. These happen to be the same
3536 // registers used to pass 'inreg' arguments so watch out for those.
3537 if (!Subtarget->is64Bit() &&
3538 ((!isa<GlobalAddressSDNode>(Callee) &&
3539 !isa<ExternalSymbolSDNode>(Callee)) ||
3540 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3541 unsigned NumInRegs = 0;
3542 // In PIC we need an extra register to formulate the address computation
3544 unsigned MaxInRegs =
3545 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3547 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3548 CCValAssign &VA = ArgLocs[i];
3551 unsigned Reg = VA.getLocReg();
3554 case X86::EAX: case X86::EDX: case X86::ECX:
3555 if (++NumInRegs == MaxInRegs)
3567 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3568 const TargetLibraryInfo *libInfo) const {
3569 return X86::createFastISel(funcInfo, libInfo);
3572 //===----------------------------------------------------------------------===//
3573 // Other Lowering Hooks
3574 //===----------------------------------------------------------------------===//
3576 static bool MayFoldLoad(SDValue Op) {
3577 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3580 static bool MayFoldIntoStore(SDValue Op) {
3581 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3584 static bool isTargetShuffle(unsigned Opcode) {
3586 default: return false;
3587 case X86ISD::BLENDI:
3588 case X86ISD::PSHUFB:
3589 case X86ISD::PSHUFD:
3590 case X86ISD::PSHUFHW:
3591 case X86ISD::PSHUFLW:
3593 case X86ISD::PALIGNR:
3594 case X86ISD::MOVLHPS:
3595 case X86ISD::MOVLHPD:
3596 case X86ISD::MOVHLPS:
3597 case X86ISD::MOVLPS:
3598 case X86ISD::MOVLPD:
3599 case X86ISD::MOVSHDUP:
3600 case X86ISD::MOVSLDUP:
3601 case X86ISD::MOVDDUP:
3604 case X86ISD::UNPCKL:
3605 case X86ISD::UNPCKH:
3606 case X86ISD::VPERMILPI:
3607 case X86ISD::VPERM2X128:
3608 case X86ISD::VPERMI:
3613 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3614 SDValue V1, SelectionDAG &DAG) {
3616 default: llvm_unreachable("Unknown x86 shuffle node");
3617 case X86ISD::MOVSHDUP:
3618 case X86ISD::MOVSLDUP:
3619 case X86ISD::MOVDDUP:
3620 return DAG.getNode(Opc, dl, VT, V1);
3624 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3625 SDValue V1, unsigned TargetMask,
3626 SelectionDAG &DAG) {
3628 default: llvm_unreachable("Unknown x86 shuffle node");
3629 case X86ISD::PSHUFD:
3630 case X86ISD::PSHUFHW:
3631 case X86ISD::PSHUFLW:
3632 case X86ISD::VPERMILPI:
3633 case X86ISD::VPERMI:
3634 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3638 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3639 SDValue V1, SDValue V2, unsigned TargetMask,
3640 SelectionDAG &DAG) {
3642 default: llvm_unreachable("Unknown x86 shuffle node");
3643 case X86ISD::PALIGNR:
3644 case X86ISD::VALIGN:
3646 case X86ISD::VPERM2X128:
3647 return DAG.getNode(Opc, dl, VT, V1, V2,
3648 DAG.getConstant(TargetMask, MVT::i8));
3652 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3653 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3655 default: llvm_unreachable("Unknown x86 shuffle node");
3656 case X86ISD::MOVLHPS:
3657 case X86ISD::MOVLHPD:
3658 case X86ISD::MOVHLPS:
3659 case X86ISD::MOVLPS:
3660 case X86ISD::MOVLPD:
3663 case X86ISD::UNPCKL:
3664 case X86ISD::UNPCKH:
3665 return DAG.getNode(Opc, dl, VT, V1, V2);
3669 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3670 MachineFunction &MF = DAG.getMachineFunction();
3671 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3672 DAG.getSubtarget().getRegisterInfo());
3673 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3674 int ReturnAddrIndex = FuncInfo->getRAIndex();
3676 if (ReturnAddrIndex == 0) {
3677 // Set up a frame object for the return address.
3678 unsigned SlotSize = RegInfo->getSlotSize();
3679 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3682 FuncInfo->setRAIndex(ReturnAddrIndex);
3685 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3688 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3689 bool hasSymbolicDisplacement) {
3690 // Offset should fit into 32 bit immediate field.
3691 if (!isInt<32>(Offset))
3694 // If we don't have a symbolic displacement - we don't have any extra
3696 if (!hasSymbolicDisplacement)
3699 // FIXME: Some tweaks might be needed for medium code model.
3700 if (M != CodeModel::Small && M != CodeModel::Kernel)
3703 // For small code model we assume that latest object is 16MB before end of 31
3704 // bits boundary. We may also accept pretty large negative constants knowing
3705 // that all objects are in the positive half of address space.
3706 if (M == CodeModel::Small && Offset < 16*1024*1024)
3709 // For kernel code model we know that all object resist in the negative half
3710 // of 32bits address space. We may not accept negative offsets, since they may
3711 // be just off and we may accept pretty large positive ones.
3712 if (M == CodeModel::Kernel && Offset >= 0)
3718 /// isCalleePop - Determines whether the callee is required to pop its
3719 /// own arguments. Callee pop is necessary to support tail calls.
3720 bool X86::isCalleePop(CallingConv::ID CallingConv,
3721 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3722 switch (CallingConv) {
3725 case CallingConv::X86_StdCall:
3726 case CallingConv::X86_FastCall:
3727 case CallingConv::X86_ThisCall:
3729 case CallingConv::Fast:
3730 case CallingConv::GHC:
3731 case CallingConv::HiPE:
3738 /// \brief Return true if the condition is an unsigned comparison operation.
3739 static bool isX86CCUnsigned(unsigned X86CC) {
3741 default: llvm_unreachable("Invalid integer condition!");
3742 case X86::COND_E: return true;
3743 case X86::COND_G: return false;
3744 case X86::COND_GE: return false;
3745 case X86::COND_L: return false;
3746 case X86::COND_LE: return false;
3747 case X86::COND_NE: return true;
3748 case X86::COND_B: return true;
3749 case X86::COND_A: return true;
3750 case X86::COND_BE: return true;
3751 case X86::COND_AE: return true;
3753 llvm_unreachable("covered switch fell through?!");
3756 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3757 /// specific condition code, returning the condition code and the LHS/RHS of the
3758 /// comparison to make.
3759 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3760 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3762 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3763 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3764 // X > -1 -> X == 0, jump !sign.
3765 RHS = DAG.getConstant(0, RHS.getValueType());
3766 return X86::COND_NS;
3768 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3769 // X < 0 -> X == 0, jump on sign.
3772 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3774 RHS = DAG.getConstant(0, RHS.getValueType());
3775 return X86::COND_LE;
3779 switch (SetCCOpcode) {
3780 default: llvm_unreachable("Invalid integer condition!");
3781 case ISD::SETEQ: return X86::COND_E;
3782 case ISD::SETGT: return X86::COND_G;
3783 case ISD::SETGE: return X86::COND_GE;
3784 case ISD::SETLT: return X86::COND_L;
3785 case ISD::SETLE: return X86::COND_LE;
3786 case ISD::SETNE: return X86::COND_NE;
3787 case ISD::SETULT: return X86::COND_B;
3788 case ISD::SETUGT: return X86::COND_A;
3789 case ISD::SETULE: return X86::COND_BE;
3790 case ISD::SETUGE: return X86::COND_AE;
3794 // First determine if it is required or is profitable to flip the operands.
3796 // If LHS is a foldable load, but RHS is not, flip the condition.
3797 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3798 !ISD::isNON_EXTLoad(RHS.getNode())) {
3799 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3800 std::swap(LHS, RHS);
3803 switch (SetCCOpcode) {
3809 std::swap(LHS, RHS);
3813 // On a floating point condition, the flags are set as follows:
3815 // 0 | 0 | 0 | X > Y
3816 // 0 | 0 | 1 | X < Y
3817 // 1 | 0 | 0 | X == Y
3818 // 1 | 1 | 1 | unordered
3819 switch (SetCCOpcode) {
3820 default: llvm_unreachable("Condcode should be pre-legalized away");
3822 case ISD::SETEQ: return X86::COND_E;
3823 case ISD::SETOLT: // flipped
3825 case ISD::SETGT: return X86::COND_A;
3826 case ISD::SETOLE: // flipped
3828 case ISD::SETGE: return X86::COND_AE;
3829 case ISD::SETUGT: // flipped
3831 case ISD::SETLT: return X86::COND_B;
3832 case ISD::SETUGE: // flipped
3834 case ISD::SETLE: return X86::COND_BE;
3836 case ISD::SETNE: return X86::COND_NE;
3837 case ISD::SETUO: return X86::COND_P;
3838 case ISD::SETO: return X86::COND_NP;
3840 case ISD::SETUNE: return X86::COND_INVALID;
3844 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3845 /// code. Current x86 isa includes the following FP cmov instructions:
3846 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3847 static bool hasFPCMov(unsigned X86CC) {
3863 /// isFPImmLegal - Returns true if the target can instruction select the
3864 /// specified FP immediate natively. If false, the legalizer will
3865 /// materialize the FP immediate as a load from a constant pool.
3866 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3867 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3868 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3874 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3875 ISD::LoadExtType ExtTy,
3877 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3878 // relocation target a movq or addq instruction: don't let the load shrink.
3879 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3880 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3881 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3882 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3886 /// \brief Returns true if it is beneficial to convert a load of a constant
3887 /// to just the constant itself.
3888 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3890 assert(Ty->isIntegerTy());
3892 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3893 if (BitSize == 0 || BitSize > 64)
3898 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3899 unsigned Index) const {
3900 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3903 return (Index == 0 || Index == ResVT.getVectorNumElements());
3906 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3907 // Speculate cttz only if we can directly use TZCNT.
3908 return Subtarget->hasBMI();
3911 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3912 // Speculate ctlz only if we can directly use LZCNT.
3913 return Subtarget->hasLZCNT();
3916 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3917 /// the specified range (L, H].
3918 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3919 return (Val < 0) || (Val >= Low && Val < Hi);
3922 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3923 /// specified value.
3924 static bool isUndefOrEqual(int Val, int CmpVal) {
3925 return (Val < 0 || Val == CmpVal);
3928 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3929 /// from position Pos and ending in Pos+Size, falls within the specified
3930 /// sequential range (Low, Low+Size]. or is undef.
3931 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3932 unsigned Pos, unsigned Size, int Low) {
3933 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3934 if (!isUndefOrEqual(Mask[i], Low))
3939 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3940 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3941 /// operand - by default will match for first operand.
3942 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3943 bool TestSecondOperand = false) {
3944 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3945 VT != MVT::v2f64 && VT != MVT::v2i64)
3948 unsigned NumElems = VT.getVectorNumElements();
3949 unsigned Lo = TestSecondOperand ? NumElems : 0;
3950 unsigned Hi = Lo + NumElems;
3952 for (unsigned i = 0; i < NumElems; ++i)
3953 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3959 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3960 /// is suitable for input to PSHUFHW.
3961 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3962 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3965 // Lower quadword copied in order or undef.
3966 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3969 // Upper quadword shuffled.
3970 for (unsigned i = 4; i != 8; ++i)
3971 if (!isUndefOrInRange(Mask[i], 4, 8))
3974 if (VT == MVT::v16i16) {
3975 // Lower quadword copied in order or undef.
3976 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3979 // Upper quadword shuffled.
3980 for (unsigned i = 12; i != 16; ++i)
3981 if (!isUndefOrInRange(Mask[i], 12, 16))
3988 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3989 /// is suitable for input to PSHUFLW.
3990 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3991 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3994 // Upper quadword copied in order.
3995 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3998 // Lower quadword shuffled.
3999 for (unsigned i = 0; i != 4; ++i)
4000 if (!isUndefOrInRange(Mask[i], 0, 4))
4003 if (VT == MVT::v16i16) {
4004 // Upper quadword copied in order.
4005 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
4008 // Lower quadword shuffled.
4009 for (unsigned i = 8; i != 12; ++i)
4010 if (!isUndefOrInRange(Mask[i], 8, 12))
4017 /// \brief Return true if the mask specifies a shuffle of elements that is
4018 /// suitable for input to intralane (palignr) or interlane (valign) vector
4020 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
4021 unsigned NumElts = VT.getVectorNumElements();
4022 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
4023 unsigned NumLaneElts = NumElts/NumLanes;
4025 // Do not handle 64-bit element shuffles with palignr.
4026 if (NumLaneElts == 2)
4029 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4031 for (i = 0; i != NumLaneElts; ++i) {
4036 // Lane is all undef, go to next lane
4037 if (i == NumLaneElts)
4040 int Start = Mask[i+l];
4042 // Make sure its in this lane in one of the sources
4043 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4044 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4047 // If not lane 0, then we must match lane 0
4048 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4051 // Correct second source to be contiguous with first source
4052 if (Start >= (int)NumElts)
4053 Start -= NumElts - NumLaneElts;
4055 // Make sure we're shifting in the right direction.
4056 if (Start <= (int)(i+l))
4061 // Check the rest of the elements to see if they are consecutive.
4062 for (++i; i != NumLaneElts; ++i) {
4063 int Idx = Mask[i+l];
4065 // Make sure its in this lane
4066 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4067 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4070 // If not lane 0, then we must match lane 0
4071 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4074 if (Idx >= (int)NumElts)
4075 Idx -= NumElts - NumLaneElts;
4077 if (!isUndefOrEqual(Idx, Start+i))
4086 /// \brief Return true if the node specifies a shuffle of elements that is
4087 /// suitable for input to PALIGNR.
4088 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4089 const X86Subtarget *Subtarget) {
4090 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4091 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4092 VT.is512BitVector())
4093 // FIXME: Add AVX512BW.
4096 return isAlignrMask(Mask, VT, false);
4099 /// \brief Return true if the node specifies a shuffle of elements that is
4100 /// suitable for input to VALIGN.
4101 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4102 const X86Subtarget *Subtarget) {
4103 // FIXME: Add AVX512VL.
4104 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4106 return isAlignrMask(Mask, VT, true);
4109 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4110 /// the two vector operands have swapped position.
4111 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4112 unsigned NumElems) {
4113 for (unsigned i = 0; i != NumElems; ++i) {
4117 else if (idx < (int)NumElems)
4118 Mask[i] = idx + NumElems;
4120 Mask[i] = idx - NumElems;
4124 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4125 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4126 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4127 /// reverse of what x86 shuffles want.
4128 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4130 unsigned NumElems = VT.getVectorNumElements();
4131 unsigned NumLanes = VT.getSizeInBits()/128;
4132 unsigned NumLaneElems = NumElems/NumLanes;
4134 if (NumLaneElems != 2 && NumLaneElems != 4)
4137 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4138 bool symetricMaskRequired =
4139 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4141 // VSHUFPSY divides the resulting vector into 4 chunks.
4142 // The sources are also splitted into 4 chunks, and each destination
4143 // chunk must come from a different source chunk.
4145 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4146 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4148 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4149 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4151 // VSHUFPDY divides the resulting vector into 4 chunks.
4152 // The sources are also splitted into 4 chunks, and each destination
4153 // chunk must come from a different source chunk.
4155 // SRC1 => X3 X2 X1 X0
4156 // SRC2 => Y3 Y2 Y1 Y0
4158 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4160 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4161 unsigned HalfLaneElems = NumLaneElems/2;
4162 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4163 for (unsigned i = 0; i != NumLaneElems; ++i) {
4164 int Idx = Mask[i+l];
4165 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4166 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4168 // For VSHUFPSY, the mask of the second half must be the same as the
4169 // first but with the appropriate offsets. This works in the same way as
4170 // VPERMILPS works with masks.
4171 if (!symetricMaskRequired || Idx < 0)
4173 if (MaskVal[i] < 0) {
4174 MaskVal[i] = Idx - l;
4177 if ((signed)(Idx - l) != MaskVal[i])
4185 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4186 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4187 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4188 if (!VT.is128BitVector())
4191 unsigned NumElems = VT.getVectorNumElements();
4196 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4197 return isUndefOrEqual(Mask[0], 6) &&
4198 isUndefOrEqual(Mask[1], 7) &&
4199 isUndefOrEqual(Mask[2], 2) &&
4200 isUndefOrEqual(Mask[3], 3);
4203 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4204 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4206 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4207 if (!VT.is128BitVector())
4210 unsigned NumElems = VT.getVectorNumElements();
4215 return isUndefOrEqual(Mask[0], 2) &&
4216 isUndefOrEqual(Mask[1], 3) &&
4217 isUndefOrEqual(Mask[2], 2) &&
4218 isUndefOrEqual(Mask[3], 3);
4221 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4222 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4223 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4224 if (!VT.is128BitVector())
4227 unsigned NumElems = VT.getVectorNumElements();
4229 if (NumElems != 2 && NumElems != 4)
4232 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4233 if (!isUndefOrEqual(Mask[i], i + NumElems))
4236 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4237 if (!isUndefOrEqual(Mask[i], i))
4243 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4244 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4245 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4246 if (!VT.is128BitVector())
4249 unsigned NumElems = VT.getVectorNumElements();
4251 if (NumElems != 2 && NumElems != 4)
4254 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4255 if (!isUndefOrEqual(Mask[i], i))
4258 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4259 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4265 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4266 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4267 /// i. e: If all but one element come from the same vector.
4268 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4269 // TODO: Deal with AVX's VINSERTPS
4270 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4273 unsigned CorrectPosV1 = 0;
4274 unsigned CorrectPosV2 = 0;
4275 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4276 if (Mask[i] == -1) {
4284 else if (Mask[i] == i + 4)
4288 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4289 // We have 3 elements (undefs count as elements from any vector) from one
4290 // vector, and one from another.
4297 // Some special combinations that can be optimized.
4300 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4301 SelectionDAG &DAG) {
4302 MVT VT = SVOp->getSimpleValueType(0);
4305 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4308 ArrayRef<int> Mask = SVOp->getMask();
4310 // These are the special masks that may be optimized.
4311 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4312 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4313 bool MatchEvenMask = true;
4314 bool MatchOddMask = true;
4315 for (int i=0; i<8; ++i) {
4316 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4317 MatchEvenMask = false;
4318 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4319 MatchOddMask = false;
4322 if (!MatchEvenMask && !MatchOddMask)
4325 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4327 SDValue Op0 = SVOp->getOperand(0);
4328 SDValue Op1 = SVOp->getOperand(1);
4330 if (MatchEvenMask) {
4331 // Shift the second operand right to 32 bits.
4332 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4333 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4335 // Shift the first operand left to 32 bits.
4336 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4337 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4339 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4340 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4343 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4344 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4345 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4346 bool HasInt256, bool V2IsSplat = false) {
4348 assert(VT.getSizeInBits() >= 128 &&
4349 "Unsupported vector type for unpckl");
4351 unsigned NumElts = VT.getVectorNumElements();
4352 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4353 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4356 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4357 "Unsupported vector type for unpckh");
4359 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4367 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, NumElts))
4373 if (!isUndefOrEqual(BitI1, j + NumElts))
4382 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4383 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4384 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4385 bool HasInt256, bool V2IsSplat = false) {
4386 assert(VT.getSizeInBits() >= 128 &&
4387 "Unsupported vector type for unpckh");
4389 unsigned NumElts = VT.getVectorNumElements();
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4395 "Unsupported vector type for unpckh");
4397 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4398 unsigned NumLanes = VT.getSizeInBits()/128;
4399 unsigned NumLaneElts = NumElts/NumLanes;
4401 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4402 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4403 int BitI = Mask[l+i];
4404 int BitI1 = Mask[l+i+1];
4405 if (!isUndefOrEqual(BitI, j))
4408 if (isUndefOrEqual(BitI1, NumElts))
4411 if (!isUndefOrEqual(BitI1, j+NumElts))
4419 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4420 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4422 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4423 unsigned NumElts = VT.getVectorNumElements();
4424 bool Is256BitVec = VT.is256BitVector();
4426 if (VT.is512BitVector())
4428 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4429 "Unsupported vector type for unpckh");
4431 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4432 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4435 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4436 // FIXME: Need a better way to get rid of this, there's no latency difference
4437 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4438 // the former later. We should also remove the "_undef" special mask.
4439 if (NumElts == 4 && Is256BitVec)
4442 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4443 // independently on 128-bit lanes.
4444 unsigned NumLanes = VT.getSizeInBits()/128;
4445 unsigned NumLaneElts = NumElts/NumLanes;
4447 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4448 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4449 int BitI = Mask[l+i];
4450 int BitI1 = Mask[l+i+1];
4452 if (!isUndefOrEqual(BitI, j))
4454 if (!isUndefOrEqual(BitI1, j))
4462 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4463 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4465 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4466 unsigned NumElts = VT.getVectorNumElements();
4468 if (VT.is512BitVector())
4471 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4472 "Unsupported vector type for unpckh");
4474 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4475 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4478 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4479 // independently on 128-bit lanes.
4480 unsigned NumLanes = VT.getSizeInBits()/128;
4481 unsigned NumLaneElts = NumElts/NumLanes;
4483 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4484 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4485 int BitI = Mask[l+i];
4486 int BitI1 = Mask[l+i+1];
4487 if (!isUndefOrEqual(BitI, j))
4489 if (!isUndefOrEqual(BitI1, j))
4496 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4497 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4498 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4499 if (!VT.is512BitVector())
4502 unsigned NumElts = VT.getVectorNumElements();
4503 unsigned HalfSize = NumElts/2;
4504 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4505 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4510 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4511 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4519 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4520 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4521 /// MOVSD, and MOVD, i.e. setting the lowest element.
4522 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4523 if (VT.getVectorElementType().getSizeInBits() < 32)
4525 if (!VT.is128BitVector())
4528 unsigned NumElts = VT.getVectorNumElements();
4530 if (!isUndefOrEqual(Mask[0], NumElts))
4533 for (unsigned i = 1; i != NumElts; ++i)
4534 if (!isUndefOrEqual(Mask[i], i))
4540 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4541 /// as permutations between 128-bit chunks or halves. As an example: this
4543 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4544 /// The first half comes from the second half of V1 and the second half from the
4545 /// the second half of V2.
4546 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4547 if (!HasFp256 || !VT.is256BitVector())
4550 // The shuffle result is divided into half A and half B. In total the two
4551 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4552 // B must come from C, D, E or F.
4553 unsigned HalfSize = VT.getVectorNumElements()/2;
4554 bool MatchA = false, MatchB = false;
4556 // Check if A comes from one of C, D, E, F.
4557 for (unsigned Half = 0; Half != 4; ++Half) {
4558 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4564 // Check if B comes from one of C, D, E, F.
4565 for (unsigned Half = 0; Half != 4; ++Half) {
4566 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4572 return MatchA && MatchB;
4575 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4576 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4577 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4578 MVT VT = SVOp->getSimpleValueType(0);
4580 unsigned HalfSize = VT.getVectorNumElements()/2;
4582 unsigned FstHalf = 0, SndHalf = 0;
4583 for (unsigned i = 0; i < HalfSize; ++i) {
4584 if (SVOp->getMaskElt(i) > 0) {
4585 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4589 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4590 if (SVOp->getMaskElt(i) > 0) {
4591 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4596 return (FstHalf | (SndHalf << 4));
4599 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4600 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4601 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4605 unsigned NumElts = VT.getVectorNumElements();
4607 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4608 for (unsigned i = 0; i != NumElts; ++i) {
4611 Imm8 |= Mask[i] << (i*2);
4616 unsigned LaneSize = 4;
4617 SmallVector<int, 4> MaskVal(LaneSize, -1);
4619 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4620 for (unsigned i = 0; i != LaneSize; ++i) {
4621 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4625 if (MaskVal[i] < 0) {
4626 MaskVal[i] = Mask[i+l] - l;
4627 Imm8 |= MaskVal[i] << (i*2);
4630 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4637 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4639 /// Note that VPERMIL mask matching is different depending whether theunderlying
4640 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4641 /// to the same elements of the low, but to the higher half of the source.
4642 /// In VPERMILPD the two lanes could be shuffled independently of each other
4643 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4644 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4645 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4646 if (VT.getSizeInBits() < 256 || EltSize < 32)
4648 bool symetricMaskRequired = (EltSize == 32);
4649 unsigned NumElts = VT.getVectorNumElements();
4651 unsigned NumLanes = VT.getSizeInBits()/128;
4652 unsigned LaneSize = NumElts/NumLanes;
4653 // 2 or 4 elements in one lane
4655 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4656 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4657 for (unsigned i = 0; i != LaneSize; ++i) {
4658 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4660 if (symetricMaskRequired) {
4661 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4662 ExpectedMaskVal[i] = Mask[i+l] - l;
4665 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4673 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4674 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4675 /// element of vector 2 and the other elements to come from vector 1 in order.
4676 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4677 bool V2IsSplat = false, bool V2IsUndef = false) {
4678 if (!VT.is128BitVector())
4681 unsigned NumOps = VT.getVectorNumElements();
4682 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4685 if (!isUndefOrEqual(Mask[0], 0))
4688 for (unsigned i = 1; i != NumOps; ++i)
4689 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4690 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4691 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4697 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4698 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4699 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4700 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4701 const X86Subtarget *Subtarget) {
4702 if (!Subtarget->hasSSE3())
4705 unsigned NumElems = VT.getVectorNumElements();
4707 if ((VT.is128BitVector() && NumElems != 4) ||
4708 (VT.is256BitVector() && NumElems != 8) ||
4709 (VT.is512BitVector() && NumElems != 16))
4712 // "i+1" is the value the indexed mask element must have
4713 for (unsigned i = 0; i != NumElems; i += 2)
4714 if (!isUndefOrEqual(Mask[i], i+1) ||
4715 !isUndefOrEqual(Mask[i+1], i+1))
4721 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4722 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4723 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4724 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4725 const X86Subtarget *Subtarget) {
4726 if (!Subtarget->hasSSE3())
4729 unsigned NumElems = VT.getVectorNumElements();
4731 if ((VT.is128BitVector() && NumElems != 4) ||
4732 (VT.is256BitVector() && NumElems != 8) ||
4733 (VT.is512BitVector() && NumElems != 16))
4736 // "i" is the value the indexed mask element must have
4737 for (unsigned i = 0; i != NumElems; i += 2)
4738 if (!isUndefOrEqual(Mask[i], i) ||
4739 !isUndefOrEqual(Mask[i+1], i))
4745 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4746 /// specifies a shuffle of elements that is suitable for input to 256-bit
4747 /// version of MOVDDUP.
4748 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4749 if (!HasFp256 || !VT.is256BitVector())
4752 unsigned NumElts = VT.getVectorNumElements();
4756 for (unsigned i = 0; i != NumElts/2; ++i)
4757 if (!isUndefOrEqual(Mask[i], 0))
4759 for (unsigned i = NumElts/2; i != NumElts; ++i)
4760 if (!isUndefOrEqual(Mask[i], NumElts/2))
4765 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4766 /// specifies a shuffle of elements that is suitable for input to 128-bit
4767 /// version of MOVDDUP.
4768 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4769 if (!VT.is128BitVector())
4772 unsigned e = VT.getVectorNumElements() / 2;
4773 for (unsigned i = 0; i != e; ++i)
4774 if (!isUndefOrEqual(Mask[i], i))
4776 for (unsigned i = 0; i != e; ++i)
4777 if (!isUndefOrEqual(Mask[e+i], i))
4782 /// isVEXTRACTIndex - Return true if the specified
4783 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4784 /// suitable for instruction that extract 128 or 256 bit vectors
4785 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4786 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4787 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4790 // The index should be aligned on a vecWidth-bit boundary.
4792 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4794 MVT VT = N->getSimpleValueType(0);
4795 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4796 bool Result = (Index * ElSize) % vecWidth == 0;
4801 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4802 /// operand specifies a subvector insert that is suitable for input to
4803 /// insertion of 128 or 256-bit subvectors
4804 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4805 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4806 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4808 // The index should be aligned on a vecWidth-bit boundary.
4810 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4812 MVT VT = N->getSimpleValueType(0);
4813 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4814 bool Result = (Index * ElSize) % vecWidth == 0;
4819 bool X86::isVINSERT128Index(SDNode *N) {
4820 return isVINSERTIndex(N, 128);
4823 bool X86::isVINSERT256Index(SDNode *N) {
4824 return isVINSERTIndex(N, 256);
4827 bool X86::isVEXTRACT128Index(SDNode *N) {
4828 return isVEXTRACTIndex(N, 128);
4831 bool X86::isVEXTRACT256Index(SDNode *N) {
4832 return isVEXTRACTIndex(N, 256);
4835 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4836 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4837 /// Handles 128-bit and 256-bit.
4838 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4839 MVT VT = N->getSimpleValueType(0);
4841 assert((VT.getSizeInBits() >= 128) &&
4842 "Unsupported vector type for PSHUF/SHUFP");
4844 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4845 // independently on 128-bit lanes.
4846 unsigned NumElts = VT.getVectorNumElements();
4847 unsigned NumLanes = VT.getSizeInBits()/128;
4848 unsigned NumLaneElts = NumElts/NumLanes;
4850 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4851 "Only supports 2, 4 or 8 elements per lane");
4853 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4855 for (unsigned i = 0; i != NumElts; ++i) {
4856 int Elt = N->getMaskElt(i);
4857 if (Elt < 0) continue;
4858 Elt &= NumLaneElts - 1;
4859 unsigned ShAmt = (i << Shift) % 8;
4860 Mask |= Elt << ShAmt;
4866 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4867 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4868 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4869 MVT VT = N->getSimpleValueType(0);
4871 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4872 "Unsupported vector type for PSHUFHW");
4874 unsigned NumElts = VT.getVectorNumElements();
4877 for (unsigned l = 0; l != NumElts; l += 8) {
4878 // 8 nodes per lane, but we only care about the last 4.
4879 for (unsigned i = 0; i < 4; ++i) {
4880 int Elt = N->getMaskElt(l+i+4);
4881 if (Elt < 0) continue;
4882 Elt &= 0x3; // only 2-bits.
4883 Mask |= Elt << (i * 2);
4890 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4891 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4892 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4893 MVT VT = N->getSimpleValueType(0);
4895 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4896 "Unsupported vector type for PSHUFHW");
4898 unsigned NumElts = VT.getVectorNumElements();
4901 for (unsigned l = 0; l != NumElts; l += 8) {
4902 // 8 nodes per lane, but we only care about the first 4.
4903 for (unsigned i = 0; i < 4; ++i) {
4904 int Elt = N->getMaskElt(l+i);
4905 if (Elt < 0) continue;
4906 Elt &= 0x3; // only 2-bits
4907 Mask |= Elt << (i * 2);
4914 /// \brief Return the appropriate immediate to shuffle the specified
4915 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4916 /// VALIGN (if Interlane is true) instructions.
4917 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4919 MVT VT = SVOp->getSimpleValueType(0);
4920 unsigned EltSize = InterLane ? 1 :
4921 VT.getVectorElementType().getSizeInBits() >> 3;
4923 unsigned NumElts = VT.getVectorNumElements();
4924 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4925 unsigned NumLaneElts = NumElts/NumLanes;
4929 for (i = 0; i != NumElts; ++i) {
4930 Val = SVOp->getMaskElt(i);
4934 if (Val >= (int)NumElts)
4935 Val -= NumElts - NumLaneElts;
4937 assert(Val - i > 0 && "PALIGNR imm should be positive");
4938 return (Val - i) * EltSize;
4941 /// \brief Return the appropriate immediate to shuffle the specified
4942 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4943 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4944 return getShuffleAlignrImmediate(SVOp, false);
4947 /// \brief Return the appropriate immediate to shuffle the specified
4948 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4949 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4950 return getShuffleAlignrImmediate(SVOp, true);
4954 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4955 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4956 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4957 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4960 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4962 MVT VecVT = N->getOperand(0).getSimpleValueType();
4963 MVT ElVT = VecVT.getVectorElementType();
4965 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4966 return Index / NumElemsPerChunk;
4969 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4970 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4971 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4972 llvm_unreachable("Illegal insert subvector for VINSERT");
4975 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4977 MVT VecVT = N->getSimpleValueType(0);
4978 MVT ElVT = VecVT.getVectorElementType();
4980 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4981 return Index / NumElemsPerChunk;
4984 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4985 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4986 /// and VINSERTI128 instructions.
4987 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4988 return getExtractVEXTRACTImmediate(N, 128);
4991 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4992 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4993 /// and VINSERTI64x4 instructions.
4994 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4995 return getExtractVEXTRACTImmediate(N, 256);
4998 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4999 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
5000 /// and VINSERTI128 instructions.
5001 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
5002 return getInsertVINSERTImmediate(N, 128);
5005 /// getInsertVINSERT256Immediate - Return the appropriate immediate
5006 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
5007 /// and VINSERTI64x4 instructions.
5008 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
5009 return getInsertVINSERTImmediate(N, 256);
5012 /// isZero - Returns true if Elt is a constant integer zero
5013 static bool isZero(SDValue V) {
5014 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
5015 return C && C->isNullValue();
5018 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
5020 bool X86::isZeroNode(SDValue Elt) {
5023 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
5024 return CFP->getValueAPF().isPosZero();
5028 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5029 /// match movhlps. The lower half elements should come from upper half of
5030 /// V1 (and in order), and the upper half elements should come from the upper
5031 /// half of V2 (and in order).
5032 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5033 if (!VT.is128BitVector())
5035 if (VT.getVectorNumElements() != 4)
5037 for (unsigned i = 0, e = 2; i != e; ++i)
5038 if (!isUndefOrEqual(Mask[i], i+2))
5040 for (unsigned i = 2; i != 4; ++i)
5041 if (!isUndefOrEqual(Mask[i], i+4))
5046 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5047 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5049 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5050 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5052 N = N->getOperand(0).getNode();
5053 if (!ISD::isNON_EXTLoad(N))
5056 *LD = cast<LoadSDNode>(N);
5060 // Test whether the given value is a vector value which will be legalized
5062 static bool WillBeConstantPoolLoad(SDNode *N) {
5063 if (N->getOpcode() != ISD::BUILD_VECTOR)
5066 // Check for any non-constant elements.
5067 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5068 switch (N->getOperand(i).getNode()->getOpcode()) {
5070 case ISD::ConstantFP:
5077 // Vectors of all-zeros and all-ones are materialized with special
5078 // instructions rather than being loaded.
5079 return !ISD::isBuildVectorAllZeros(N) &&
5080 !ISD::isBuildVectorAllOnes(N);
5083 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5084 /// match movlp{s|d}. The lower half elements should come from lower half of
5085 /// V1 (and in order), and the upper half elements should come from the upper
5086 /// half of V2 (and in order). And since V1 will become the source of the
5087 /// MOVLP, it must be either a vector load or a scalar load to vector.
5088 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5089 ArrayRef<int> Mask, MVT VT) {
5090 if (!VT.is128BitVector())
5093 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5095 // Is V2 is a vector load, don't do this transformation. We will try to use
5096 // load folding shufps op.
5097 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5100 unsigned NumElems = VT.getVectorNumElements();
5102 if (NumElems != 2 && NumElems != 4)
5104 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5105 if (!isUndefOrEqual(Mask[i], i))
5107 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5108 if (!isUndefOrEqual(Mask[i], i+NumElems))
5113 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5114 /// to an zero vector.
5115 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5116 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5117 SDValue V1 = N->getOperand(0);
5118 SDValue V2 = N->getOperand(1);
5119 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5120 for (unsigned i = 0; i != NumElems; ++i) {
5121 int Idx = N->getMaskElt(i);
5122 if (Idx >= (int)NumElems) {
5123 unsigned Opc = V2.getOpcode();
5124 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5126 if (Opc != ISD::BUILD_VECTOR ||
5127 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5129 } else if (Idx >= 0) {
5130 unsigned Opc = V1.getOpcode();
5131 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5133 if (Opc != ISD::BUILD_VECTOR ||
5134 !X86::isZeroNode(V1.getOperand(Idx)))
5141 /// getZeroVector - Returns a vector of specified type with all zero elements.
5143 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5144 SelectionDAG &DAG, SDLoc dl) {
5145 assert(VT.isVector() && "Expected a vector type");
5147 // Always build SSE zero vectors as <4 x i32> bitcasted
5148 // to their dest type. This ensures they get CSE'd.
5150 if (VT.is128BitVector()) { // SSE
5151 if (Subtarget->hasSSE2()) { // SSE2
5152 SDValue Cst = DAG.getConstant(0, MVT::i32);
5153 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5155 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5158 } else if (VT.is256BitVector()) { // AVX
5159 if (Subtarget->hasInt256()) { // AVX2
5160 SDValue Cst = DAG.getConstant(0, MVT::i32);
5161 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5162 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5164 // 256-bit logic and arithmetic instructions in AVX are all
5165 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5166 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5167 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5168 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5170 } else if (VT.is512BitVector()) { // AVX-512
5171 SDValue Cst = DAG.getConstant(0, MVT::i32);
5172 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5173 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5175 } else if (VT.getScalarType() == MVT::i1) {
5176 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5177 SDValue Cst = DAG.getConstant(0, MVT::i1);
5178 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5179 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5181 llvm_unreachable("Unexpected vector type");
5183 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5186 /// getOnesVector - Returns a vector of specified type with all bits set.
5187 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5188 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5189 /// Then bitcast to their original type, ensuring they get CSE'd.
5190 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5192 assert(VT.isVector() && "Expected a vector type");
5194 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5196 if (VT.is256BitVector()) {
5197 if (HasInt256) { // AVX2
5198 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5199 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5201 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5202 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5204 } else if (VT.is128BitVector()) {
5205 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5207 llvm_unreachable("Unexpected vector type");
5209 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5212 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5213 /// that point to V2 points to its first element.
5214 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5215 for (unsigned i = 0; i != NumElems; ++i) {
5216 if (Mask[i] > (int)NumElems) {
5222 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5223 /// operation of specified width.
5224 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5226 unsigned NumElems = VT.getVectorNumElements();
5227 SmallVector<int, 8> Mask;
5228 Mask.push_back(NumElems);
5229 for (unsigned i = 1; i != NumElems; ++i)
5231 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5234 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5235 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5237 unsigned NumElems = VT.getVectorNumElements();
5238 SmallVector<int, 8> Mask;
5239 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5241 Mask.push_back(i + NumElems);
5243 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5246 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5247 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5249 unsigned NumElems = VT.getVectorNumElements();
5250 SmallVector<int, 8> Mask;
5251 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5252 Mask.push_back(i + Half);
5253 Mask.push_back(i + NumElems + Half);
5255 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5258 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5259 // a generic shuffle instruction because the target has no such instructions.
5260 // Generate shuffles which repeat i16 and i8 several times until they can be
5261 // represented by v4f32 and then be manipulated by target suported shuffles.
5262 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5263 MVT VT = V.getSimpleValueType();
5264 int NumElems = VT.getVectorNumElements();
5267 while (NumElems > 4) {
5268 if (EltNo < NumElems/2) {
5269 V = getUnpackl(DAG, dl, VT, V, V);
5271 V = getUnpackh(DAG, dl, VT, V, V);
5272 EltNo -= NumElems/2;
5279 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5280 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5281 MVT VT = V.getSimpleValueType();
5284 if (VT.is128BitVector()) {
5285 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5286 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5287 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5289 } else if (VT.is256BitVector()) {
5290 // To use VPERMILPS to splat scalars, the second half of indicies must
5291 // refer to the higher part, which is a duplication of the lower one,
5292 // because VPERMILPS can only handle in-lane permutations.
5293 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5294 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5296 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5297 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5300 llvm_unreachable("Vector size not supported");
5302 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5305 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5306 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5307 MVT SrcVT = SV->getSimpleValueType(0);
5308 SDValue V1 = SV->getOperand(0);
5311 int EltNo = SV->getSplatIndex();
5312 int NumElems = SrcVT.getVectorNumElements();
5313 bool Is256BitVec = SrcVT.is256BitVector();
5315 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5316 "Unknown how to promote splat for type");
5318 // Extract the 128-bit part containing the splat element and update
5319 // the splat element index when it refers to the higher register.
5321 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5322 if (EltNo >= NumElems/2)
5323 EltNo -= NumElems/2;
5326 // All i16 and i8 vector types can't be used directly by a generic shuffle
5327 // instruction because the target has no such instruction. Generate shuffles
5328 // which repeat i16 and i8 several times until they fit in i32, and then can
5329 // be manipulated by target suported shuffles.
5330 MVT EltVT = SrcVT.getVectorElementType();
5331 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5332 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5334 // Recreate the 256-bit vector and place the same 128-bit vector
5335 // into the low and high part. This is necessary because we want
5336 // to use VPERM* to shuffle the vectors
5338 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5341 return getLegalSplat(DAG, V1, EltNo);
5344 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5345 /// vector of zero or undef vector. This produces a shuffle where the low
5346 /// element of V2 is swizzled into the zero/undef vector, landing at element
5347 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5348 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5350 const X86Subtarget *Subtarget,
5351 SelectionDAG &DAG) {
5352 MVT VT = V2.getSimpleValueType();
5354 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5355 unsigned NumElems = VT.getVectorNumElements();
5356 SmallVector<int, 16> MaskVec;
5357 for (unsigned i = 0; i != NumElems; ++i)
5358 // If this is the insertion idx, put the low elt of V2 here.
5359 MaskVec.push_back(i == Idx ? NumElems : i);
5360 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5363 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5364 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5365 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5366 /// shuffles which use a single input multiple times, and in those cases it will
5367 /// adjust the mask to only have indices within that single input.
5368 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5369 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5370 unsigned NumElems = VT.getVectorNumElements();
5374 bool IsFakeUnary = false;
5375 switch(N->getOpcode()) {
5376 case X86ISD::BLENDI:
5377 ImmN = N->getOperand(N->getNumOperands()-1);
5378 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5381 ImmN = N->getOperand(N->getNumOperands()-1);
5382 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5383 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5385 case X86ISD::UNPCKH:
5386 DecodeUNPCKHMask(VT, Mask);
5387 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5389 case X86ISD::UNPCKL:
5390 DecodeUNPCKLMask(VT, Mask);
5391 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5393 case X86ISD::MOVHLPS:
5394 DecodeMOVHLPSMask(NumElems, Mask);
5395 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5397 case X86ISD::MOVLHPS:
5398 DecodeMOVLHPSMask(NumElems, Mask);
5399 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5401 case X86ISD::PALIGNR:
5402 ImmN = N->getOperand(N->getNumOperands()-1);
5403 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5405 case X86ISD::PSHUFD:
5406 case X86ISD::VPERMILPI:
5407 ImmN = N->getOperand(N->getNumOperands()-1);
5408 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5411 case X86ISD::PSHUFHW:
5412 ImmN = N->getOperand(N->getNumOperands()-1);
5413 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5416 case X86ISD::PSHUFLW:
5417 ImmN = N->getOperand(N->getNumOperands()-1);
5418 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5421 case X86ISD::PSHUFB: {
5423 SDValue MaskNode = N->getOperand(1);
5424 while (MaskNode->getOpcode() == ISD::BITCAST)
5425 MaskNode = MaskNode->getOperand(0);
5427 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5428 // If we have a build-vector, then things are easy.
5429 EVT VT = MaskNode.getValueType();
5430 assert(VT.isVector() &&
5431 "Can't produce a non-vector with a build_vector!");
5432 if (!VT.isInteger())
5435 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5437 SmallVector<uint64_t, 32> RawMask;
5438 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5439 SDValue Op = MaskNode->getOperand(i);
5440 if (Op->getOpcode() == ISD::UNDEF) {
5441 RawMask.push_back((uint64_t)SM_SentinelUndef);
5444 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5447 APInt MaskElement = CN->getAPIntValue();
5449 // We now have to decode the element which could be any integer size and
5450 // extract each byte of it.
5451 for (int j = 0; j < NumBytesPerElement; ++j) {
5452 // Note that this is x86 and so always little endian: the low byte is
5453 // the first byte of the mask.
5454 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5455 MaskElement = MaskElement.lshr(8);
5458 DecodePSHUFBMask(RawMask, Mask);
5462 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5466 SDValue Ptr = MaskLoad->getBasePtr();
5467 if (Ptr->getOpcode() == X86ISD::Wrapper)
5468 Ptr = Ptr->getOperand(0);
5470 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5471 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5474 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5475 // FIXME: Support AVX-512 here.
5476 Type *Ty = C->getType();
5477 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5478 Ty->getVectorNumElements() != 32))
5481 DecodePSHUFBMask(C, Mask);
5487 case X86ISD::VPERMI:
5488 ImmN = N->getOperand(N->getNumOperands()-1);
5489 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5493 case X86ISD::MOVSD: {
5494 // The index 0 always comes from the first element of the second source,
5495 // this is why MOVSS and MOVSD are used in the first place. The other
5496 // elements come from the other positions of the first source vector
5497 Mask.push_back(NumElems);
5498 for (unsigned i = 1; i != NumElems; ++i) {
5503 case X86ISD::VPERM2X128:
5504 ImmN = N->getOperand(N->getNumOperands()-1);
5505 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5506 if (Mask.empty()) return false;
5508 case X86ISD::MOVSLDUP:
5509 DecodeMOVSLDUPMask(VT, Mask);
5511 case X86ISD::MOVSHDUP:
5512 DecodeMOVSHDUPMask(VT, Mask);
5514 case X86ISD::MOVDDUP:
5515 case X86ISD::MOVLHPD:
5516 case X86ISD::MOVLPD:
5517 case X86ISD::MOVLPS:
5518 // Not yet implemented
5520 default: llvm_unreachable("unknown target shuffle node");
5523 // If we have a fake unary shuffle, the shuffle mask is spread across two
5524 // inputs that are actually the same node. Re-map the mask to always point
5525 // into the first input.
5528 if (M >= (int)Mask.size())
5534 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5535 /// element of the result of the vector shuffle.
5536 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5539 return SDValue(); // Limit search depth.
5541 SDValue V = SDValue(N, 0);
5542 EVT VT = V.getValueType();
5543 unsigned Opcode = V.getOpcode();
5545 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5546 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5547 int Elt = SV->getMaskElt(Index);
5550 return DAG.getUNDEF(VT.getVectorElementType());
5552 unsigned NumElems = VT.getVectorNumElements();
5553 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5554 : SV->getOperand(1);
5555 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5558 // Recurse into target specific vector shuffles to find scalars.
5559 if (isTargetShuffle(Opcode)) {
5560 MVT ShufVT = V.getSimpleValueType();
5561 unsigned NumElems = ShufVT.getVectorNumElements();
5562 SmallVector<int, 16> ShuffleMask;
5565 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5568 int Elt = ShuffleMask[Index];
5570 return DAG.getUNDEF(ShufVT.getVectorElementType());
5572 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5574 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5578 // Actual nodes that may contain scalar elements
5579 if (Opcode == ISD::BITCAST) {
5580 V = V.getOperand(0);
5581 EVT SrcVT = V.getValueType();
5582 unsigned NumElems = VT.getVectorNumElements();
5584 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5588 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5589 return (Index == 0) ? V.getOperand(0)
5590 : DAG.getUNDEF(VT.getVectorElementType());
5592 if (V.getOpcode() == ISD::BUILD_VECTOR)
5593 return V.getOperand(Index);
5598 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5599 /// shuffle operation which come from a consecutively from a zero. The
5600 /// search can start in two different directions, from left or right.
5601 /// We count undefs as zeros until PreferredNum is reached.
5602 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5603 unsigned NumElems, bool ZerosFromLeft,
5605 unsigned PreferredNum = -1U) {
5606 unsigned NumZeros = 0;
5607 for (unsigned i = 0; i != NumElems; ++i) {
5608 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5609 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5613 if (X86::isZeroNode(Elt))
5615 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5616 NumZeros = std::min(NumZeros + 1, PreferredNum);
5624 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5625 /// correspond consecutively to elements from one of the vector operands,
5626 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5628 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5629 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5630 unsigned NumElems, unsigned &OpNum) {
5631 bool SeenV1 = false;
5632 bool SeenV2 = false;
5634 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5635 int Idx = SVOp->getMaskElt(i);
5636 // Ignore undef indicies
5640 if (Idx < (int)NumElems)
5645 // Only accept consecutive elements from the same vector
5646 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5650 OpNum = SeenV1 ? 0 : 1;
5654 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5655 /// logical left shift of a vector.
5656 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5657 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5659 SVOp->getSimpleValueType(0).getVectorNumElements();
5660 unsigned NumZeros = getNumOfConsecutiveZeros(
5661 SVOp, NumElems, false /* check zeros from right */, DAG,
5662 SVOp->getMaskElt(0));
5668 // Considering the elements in the mask that are not consecutive zeros,
5669 // check if they consecutively come from only one of the source vectors.
5671 // V1 = {X, A, B, C} 0
5673 // vector_shuffle V1, V2 <1, 2, 3, X>
5675 if (!isShuffleMaskConsecutive(SVOp,
5676 0, // Mask Start Index
5677 NumElems-NumZeros, // Mask End Index(exclusive)
5678 NumZeros, // Where to start looking in the src vector
5679 NumElems, // Number of elements in vector
5680 OpSrc)) // Which source operand ?
5685 ShVal = SVOp->getOperand(OpSrc);
5689 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5690 /// logical left shift of a vector.
5691 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5692 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5694 SVOp->getSimpleValueType(0).getVectorNumElements();
5695 unsigned NumZeros = getNumOfConsecutiveZeros(
5696 SVOp, NumElems, true /* check zeros from left */, DAG,
5697 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5703 // Considering the elements in the mask that are not consecutive zeros,
5704 // check if they consecutively come from only one of the source vectors.
5706 // 0 { A, B, X, X } = V2
5708 // vector_shuffle V1, V2 <X, X, 4, 5>
5710 if (!isShuffleMaskConsecutive(SVOp,
5711 NumZeros, // Mask Start Index
5712 NumElems, // Mask End Index(exclusive)
5713 0, // Where to start looking in the src vector
5714 NumElems, // Number of elements in vector
5715 OpSrc)) // Which source operand ?
5720 ShVal = SVOp->getOperand(OpSrc);
5724 /// isVectorShift - Returns true if the shuffle can be implemented as a
5725 /// logical left or right shift of a vector.
5726 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5727 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5728 // Although the logic below support any bitwidth size, there are no
5729 // shift instructions which handle more than 128-bit vectors.
5730 if (!SVOp->getSimpleValueType(0).is128BitVector())
5733 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5734 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5740 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5742 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5743 unsigned NumNonZero, unsigned NumZero,
5745 const X86Subtarget* Subtarget,
5746 const TargetLowering &TLI) {
5753 for (unsigned i = 0; i < 16; ++i) {
5754 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5755 if (ThisIsNonZero && First) {
5757 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5759 V = DAG.getUNDEF(MVT::v8i16);
5764 SDValue ThisElt, LastElt;
5765 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5766 if (LastIsNonZero) {
5767 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5768 MVT::i16, Op.getOperand(i-1));
5770 if (ThisIsNonZero) {
5771 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5772 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5773 ThisElt, DAG.getConstant(8, MVT::i8));
5775 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5779 if (ThisElt.getNode())
5780 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5781 DAG.getIntPtrConstant(i/2));
5785 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5788 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5790 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5791 unsigned NumNonZero, unsigned NumZero,
5793 const X86Subtarget* Subtarget,
5794 const TargetLowering &TLI) {
5801 for (unsigned i = 0; i < 8; ++i) {
5802 bool isNonZero = (NonZeros & (1 << i)) != 0;
5806 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5808 V = DAG.getUNDEF(MVT::v8i16);
5811 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5812 MVT::v8i16, V, Op.getOperand(i),
5813 DAG.getIntPtrConstant(i));
5820 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5821 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5822 const X86Subtarget *Subtarget,
5823 const TargetLowering &TLI) {
5824 // Find all zeroable elements.
5826 for (int i=0; i < 4; ++i) {
5827 SDValue Elt = Op->getOperand(i);
5828 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5830 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5831 [](bool M) { return !M; }) > 1 &&
5832 "We expect at least two non-zero elements!");
5834 // We only know how to deal with build_vector nodes where elements are either
5835 // zeroable or extract_vector_elt with constant index.
5836 SDValue FirstNonZero;
5837 unsigned FirstNonZeroIdx;
5838 for (unsigned i=0; i < 4; ++i) {
5841 SDValue Elt = Op->getOperand(i);
5842 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5843 !isa<ConstantSDNode>(Elt.getOperand(1)))
5845 // Make sure that this node is extracting from a 128-bit vector.
5846 MVT VT = Elt.getOperand(0).getSimpleValueType();
5847 if (!VT.is128BitVector())
5849 if (!FirstNonZero.getNode()) {
5851 FirstNonZeroIdx = i;
5855 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5856 SDValue V1 = FirstNonZero.getOperand(0);
5857 MVT VT = V1.getSimpleValueType();
5859 // See if this build_vector can be lowered as a blend with zero.
5861 unsigned EltMaskIdx, EltIdx;
5863 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5864 if (Zeroable[EltIdx]) {
5865 // The zero vector will be on the right hand side.
5866 Mask[EltIdx] = EltIdx+4;
5870 Elt = Op->getOperand(EltIdx);
5871 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5872 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5873 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5875 Mask[EltIdx] = EltIdx;
5879 // Let the shuffle legalizer deal with blend operations.
5880 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5881 if (V1.getSimpleValueType() != VT)
5882 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5883 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5886 // See if we can lower this build_vector to a INSERTPS.
5887 if (!Subtarget->hasSSE41())
5890 SDValue V2 = Elt.getOperand(0);
5891 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5894 bool CanFold = true;
5895 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5899 SDValue Current = Op->getOperand(i);
5900 SDValue SrcVector = Current->getOperand(0);
5903 CanFold = SrcVector == V1 &&
5904 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5910 assert(V1.getNode() && "Expected at least two non-zero elements!");
5911 if (V1.getSimpleValueType() != MVT::v4f32)
5912 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5913 if (V2.getSimpleValueType() != MVT::v4f32)
5914 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5916 // Ok, we can emit an INSERTPS instruction.
5918 for (int i = 0; i < 4; ++i)
5922 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5923 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5924 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5925 DAG.getIntPtrConstant(InsertPSMask));
5926 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5929 /// getVShift - Return a vector logical shift node.
5931 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5932 unsigned NumBits, SelectionDAG &DAG,
5933 const TargetLowering &TLI, SDLoc dl) {
5934 assert(VT.is128BitVector() && "Unknown type for VShift");
5935 EVT ShVT = MVT::v2i64;
5936 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5937 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5938 return DAG.getNode(ISD::BITCAST, dl, VT,
5939 DAG.getNode(Opc, dl, ShVT, SrcOp,
5940 DAG.getConstant(NumBits,
5941 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5945 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5947 // Check if the scalar load can be widened into a vector load. And if
5948 // the address is "base + cst" see if the cst can be "absorbed" into
5949 // the shuffle mask.
5950 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5951 SDValue Ptr = LD->getBasePtr();
5952 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5954 EVT PVT = LD->getValueType(0);
5955 if (PVT != MVT::i32 && PVT != MVT::f32)
5960 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5961 FI = FINode->getIndex();
5963 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5964 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5965 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5966 Offset = Ptr.getConstantOperandVal(1);
5967 Ptr = Ptr.getOperand(0);
5972 // FIXME: 256-bit vector instructions don't require a strict alignment,
5973 // improve this code to support it better.
5974 unsigned RequiredAlign = VT.getSizeInBits()/8;
5975 SDValue Chain = LD->getChain();
5976 // Make sure the stack object alignment is at least 16 or 32.
5977 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5978 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5979 if (MFI->isFixedObjectIndex(FI)) {
5980 // Can't change the alignment. FIXME: It's possible to compute
5981 // the exact stack offset and reference FI + adjust offset instead.
5982 // If someone *really* cares about this. That's the way to implement it.
5985 MFI->setObjectAlignment(FI, RequiredAlign);
5989 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5990 // Ptr + (Offset & ~15).
5993 if ((Offset % RequiredAlign) & 3)
5995 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5997 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5998 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
6000 int EltNo = (Offset - StartOffset) >> 2;
6001 unsigned NumElems = VT.getVectorNumElements();
6003 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
6004 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
6005 LD->getPointerInfo().getWithOffset(StartOffset),
6006 false, false, false, 0);
6008 SmallVector<int, 8> Mask;
6009 for (unsigned i = 0; i != NumElems; ++i)
6010 Mask.push_back(EltNo);
6012 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
6018 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
6019 /// vector of type 'VT', see if the elements can be replaced by a single large
6020 /// load which has the same value as a build_vector whose operands are 'elts'.
6022 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
6024 /// FIXME: we'd also like to handle the case where the last elements are zero
6025 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
6026 /// There's even a handy isZeroNode for that purpose.
6027 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6028 SDLoc &DL, SelectionDAG &DAG,
6029 bool isAfterLegalize) {
6030 EVT EltVT = VT.getVectorElementType();
6031 unsigned NumElems = Elts.size();
6033 LoadSDNode *LDBase = nullptr;
6034 unsigned LastLoadedElt = -1U;
6036 // For each element in the initializer, see if we've found a load or an undef.
6037 // If we don't find an initial load element, or later load elements are
6038 // non-consecutive, bail out.
6039 for (unsigned i = 0; i < NumElems; ++i) {
6040 SDValue Elt = Elts[i];
6042 if (!Elt.getNode() ||
6043 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6046 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6048 LDBase = cast<LoadSDNode>(Elt.getNode());
6052 if (Elt.getOpcode() == ISD::UNDEF)
6055 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6056 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6061 // If we have found an entire vector of loads and undefs, then return a large
6062 // load of the entire vector width starting at the base pointer. If we found
6063 // consecutive loads for the low half, generate a vzext_load node.
6064 if (LastLoadedElt == NumElems - 1) {
6066 if (isAfterLegalize &&
6067 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6070 SDValue NewLd = SDValue();
6072 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6073 LDBase->getPointerInfo(), LDBase->isVolatile(),
6074 LDBase->isNonTemporal(), LDBase->isInvariant(),
6075 LDBase->getAlignment());
6077 if (LDBase->hasAnyUseOfValue(1)) {
6078 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6080 SDValue(NewLd.getNode(), 1));
6081 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6082 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6083 SDValue(NewLd.getNode(), 1));
6089 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6090 //of a v4i32 / v4f32. It's probably worth generalizing.
6091 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6092 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6093 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6094 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6096 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6097 LDBase->getPointerInfo(),
6098 LDBase->getAlignment(),
6099 false/*isVolatile*/, true/*ReadMem*/,
6102 // Make sure the newly-created LOAD is in the same position as LDBase in
6103 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6104 // update uses of LDBase's output chain to use the TokenFactor.
6105 if (LDBase->hasAnyUseOfValue(1)) {
6106 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6107 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6108 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6109 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6110 SDValue(ResNode.getNode(), 1));
6113 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6118 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6119 /// to generate a splat value for the following cases:
6120 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6121 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6122 /// a scalar load, or a constant.
6123 /// The VBROADCAST node is returned when a pattern is found,
6124 /// or SDValue() otherwise.
6125 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6126 SelectionDAG &DAG) {
6127 // VBROADCAST requires AVX.
6128 // TODO: Splats could be generated for non-AVX CPUs using SSE
6129 // instructions, but there's less potential gain for only 128-bit vectors.
6130 if (!Subtarget->hasAVX())
6133 MVT VT = Op.getSimpleValueType();
6136 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6137 "Unsupported vector type for broadcast.");
6142 switch (Op.getOpcode()) {
6144 // Unknown pattern found.
6147 case ISD::BUILD_VECTOR: {
6148 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6149 BitVector UndefElements;
6150 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6152 // We need a splat of a single value to use broadcast, and it doesn't
6153 // make any sense if the value is only in one element of the vector.
6154 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6158 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6159 Ld.getOpcode() == ISD::ConstantFP);
6161 // Make sure that all of the users of a non-constant load are from the
6162 // BUILD_VECTOR node.
6163 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6168 case ISD::VECTOR_SHUFFLE: {
6169 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6171 // Shuffles must have a splat mask where the first element is
6173 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6176 SDValue Sc = Op.getOperand(0);
6177 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6178 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6180 if (!Subtarget->hasInt256())
6183 // Use the register form of the broadcast instruction available on AVX2.
6184 if (VT.getSizeInBits() >= 256)
6185 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6186 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6189 Ld = Sc.getOperand(0);
6190 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6191 Ld.getOpcode() == ISD::ConstantFP);
6193 // The scalar_to_vector node and the suspected
6194 // load node must have exactly one user.
6195 // Constants may have multiple users.
6197 // AVX-512 has register version of the broadcast
6198 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6199 Ld.getValueType().getSizeInBits() >= 32;
6200 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6207 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6208 bool IsGE256 = (VT.getSizeInBits() >= 256);
6210 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6211 // instruction to save 8 or more bytes of constant pool data.
6212 // TODO: If multiple splats are generated to load the same constant,
6213 // it may be detrimental to overall size. There needs to be a way to detect
6214 // that condition to know if this is truly a size win.
6215 const Function *F = DAG.getMachineFunction().getFunction();
6216 bool OptForSize = F->getAttributes().
6217 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6219 // Handle broadcasting a single constant scalar from the constant pool
6221 // On Sandybridge (no AVX2), it is still better to load a constant vector
6222 // from the constant pool and not to broadcast it from a scalar.
6223 // But override that restriction when optimizing for size.
6224 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6225 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6226 EVT CVT = Ld.getValueType();
6227 assert(!CVT.isVector() && "Must not broadcast a vector type");
6229 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6230 // For size optimization, also splat v2f64 and v2i64, and for size opt
6231 // with AVX2, also splat i8 and i16.
6232 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6233 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6234 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6235 const Constant *C = nullptr;
6236 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6237 C = CI->getConstantIntValue();
6238 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6239 C = CF->getConstantFPValue();
6241 assert(C && "Invalid constant type");
6243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6244 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6245 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6246 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6247 MachinePointerInfo::getConstantPool(),
6248 false, false, false, Alignment);
6250 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6254 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6256 // Handle AVX2 in-register broadcasts.
6257 if (!IsLoad && Subtarget->hasInt256() &&
6258 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6259 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6261 // The scalar source must be a normal load.
6265 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6266 (Subtarget->hasVLX() && ScalarSize == 64))
6267 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6269 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6270 // double since there is no vbroadcastsd xmm
6271 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6272 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6273 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6276 // Unsupported broadcast.
6280 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6281 /// underlying vector and index.
6283 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6285 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6287 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6288 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6291 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6293 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6295 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6296 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6299 // In this case the vector is the extract_subvector expression and the index
6300 // is 2, as specified by the shuffle.
6301 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6302 SDValue ShuffleVec = SVOp->getOperand(0);
6303 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6304 assert(ShuffleVecVT.getVectorElementType() ==
6305 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6307 int ShuffleIdx = SVOp->getMaskElt(Idx);
6308 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6309 ExtractedFromVec = ShuffleVec;
6315 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6316 MVT VT = Op.getSimpleValueType();
6318 // Skip if insert_vec_elt is not supported.
6319 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6320 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6324 unsigned NumElems = Op.getNumOperands();
6328 SmallVector<unsigned, 4> InsertIndices;
6329 SmallVector<int, 8> Mask(NumElems, -1);
6331 for (unsigned i = 0; i != NumElems; ++i) {
6332 unsigned Opc = Op.getOperand(i).getOpcode();
6334 if (Opc == ISD::UNDEF)
6337 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6338 // Quit if more than 1 elements need inserting.
6339 if (InsertIndices.size() > 1)
6342 InsertIndices.push_back(i);
6346 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6347 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6348 // Quit if non-constant index.
6349 if (!isa<ConstantSDNode>(ExtIdx))
6351 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6353 // Quit if extracted from vector of different type.
6354 if (ExtractedFromVec.getValueType() != VT)
6357 if (!VecIn1.getNode())
6358 VecIn1 = ExtractedFromVec;
6359 else if (VecIn1 != ExtractedFromVec) {
6360 if (!VecIn2.getNode())
6361 VecIn2 = ExtractedFromVec;
6362 else if (VecIn2 != ExtractedFromVec)
6363 // Quit if more than 2 vectors to shuffle
6367 if (ExtractedFromVec == VecIn1)
6369 else if (ExtractedFromVec == VecIn2)
6370 Mask[i] = Idx + NumElems;
6373 if (!VecIn1.getNode())
6376 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6377 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6378 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6379 unsigned Idx = InsertIndices[i];
6380 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6381 DAG.getIntPtrConstant(Idx));
6387 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6389 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6391 MVT VT = Op.getSimpleValueType();
6392 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6393 "Unexpected type in LowerBUILD_VECTORvXi1!");
6396 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6397 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6398 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6399 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6402 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6403 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6404 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6405 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6408 bool AllContants = true;
6409 uint64_t Immediate = 0;
6410 int NonConstIdx = -1;
6411 bool IsSplat = true;
6412 unsigned NumNonConsts = 0;
6413 unsigned NumConsts = 0;
6414 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6415 SDValue In = Op.getOperand(idx);
6416 if (In.getOpcode() == ISD::UNDEF)
6418 if (!isa<ConstantSDNode>(In)) {
6419 AllContants = false;
6424 if (cast<ConstantSDNode>(In)->getZExtValue())
6425 Immediate |= (1ULL << idx);
6427 if (In != Op.getOperand(0))
6432 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6433 DAG.getConstant(Immediate, MVT::i16));
6434 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6435 DAG.getIntPtrConstant(0));
6438 if (NumNonConsts == 1 && NonConstIdx != 0) {
6441 SDValue VecAsImm = DAG.getConstant(Immediate,
6442 MVT::getIntegerVT(VT.getSizeInBits()));
6443 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6446 DstVec = DAG.getUNDEF(VT);
6447 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6448 Op.getOperand(NonConstIdx),
6449 DAG.getIntPtrConstant(NonConstIdx));
6451 if (!IsSplat && (NonConstIdx != 0))
6452 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6453 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6456 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6457 DAG.getConstant(-1, SelectVT),
6458 DAG.getConstant(0, SelectVT));
6460 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6461 DAG.getConstant((Immediate | 1), SelectVT),
6462 DAG.getConstant(Immediate, SelectVT));
6463 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6466 /// \brief Return true if \p N implements a horizontal binop and return the
6467 /// operands for the horizontal binop into V0 and V1.
6469 /// This is a helper function of PerformBUILD_VECTORCombine.
6470 /// This function checks that the build_vector \p N in input implements a
6471 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6472 /// operation to match.
6473 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6474 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6475 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6478 /// This function only analyzes elements of \p N whose indices are
6479 /// in range [BaseIdx, LastIdx).
6480 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6482 unsigned BaseIdx, unsigned LastIdx,
6483 SDValue &V0, SDValue &V1) {
6484 EVT VT = N->getValueType(0);
6486 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6487 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6488 "Invalid Vector in input!");
6490 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6491 bool CanFold = true;
6492 unsigned ExpectedVExtractIdx = BaseIdx;
6493 unsigned NumElts = LastIdx - BaseIdx;
6494 V0 = DAG.getUNDEF(VT);
6495 V1 = DAG.getUNDEF(VT);
6497 // Check if N implements a horizontal binop.
6498 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6499 SDValue Op = N->getOperand(i + BaseIdx);
6502 if (Op->getOpcode() == ISD::UNDEF) {
6503 // Update the expected vector extract index.
6504 if (i * 2 == NumElts)
6505 ExpectedVExtractIdx = BaseIdx;
6506 ExpectedVExtractIdx += 2;
6510 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6515 SDValue Op0 = Op.getOperand(0);
6516 SDValue Op1 = Op.getOperand(1);
6518 // Try to match the following pattern:
6519 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6520 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6521 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6522 Op0.getOperand(0) == Op1.getOperand(0) &&
6523 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6524 isa<ConstantSDNode>(Op1.getOperand(1)));
6528 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6529 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6531 if (i * 2 < NumElts) {
6532 if (V0.getOpcode() == ISD::UNDEF)
6533 V0 = Op0.getOperand(0);
6535 if (V1.getOpcode() == ISD::UNDEF)
6536 V1 = Op0.getOperand(0);
6537 if (i * 2 == NumElts)
6538 ExpectedVExtractIdx = BaseIdx;
6541 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6542 if (I0 == ExpectedVExtractIdx)
6543 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6544 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6545 // Try to match the following dag sequence:
6546 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6547 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6551 ExpectedVExtractIdx += 2;
6557 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6558 /// a concat_vector.
6560 /// This is a helper function of PerformBUILD_VECTORCombine.
6561 /// This function expects two 256-bit vectors called V0 and V1.
6562 /// At first, each vector is split into two separate 128-bit vectors.
6563 /// Then, the resulting 128-bit vectors are used to implement two
6564 /// horizontal binary operations.
6566 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6568 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6569 /// the two new horizontal binop.
6570 /// When Mode is set, the first horizontal binop dag node would take as input
6571 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6572 /// horizontal binop dag node would take as input the lower 128-bit of V1
6573 /// and the upper 128-bit of V1.
6575 /// HADD V0_LO, V0_HI
6576 /// HADD V1_LO, V1_HI
6578 /// Otherwise, the first horizontal binop dag node takes as input the lower
6579 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6580 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6582 /// HADD V0_LO, V1_LO
6583 /// HADD V0_HI, V1_HI
6585 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6586 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6587 /// the upper 128-bits of the result.
6588 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6589 SDLoc DL, SelectionDAG &DAG,
6590 unsigned X86Opcode, bool Mode,
6591 bool isUndefLO, bool isUndefHI) {
6592 EVT VT = V0.getValueType();
6593 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6594 "Invalid nodes in input!");
6596 unsigned NumElts = VT.getVectorNumElements();
6597 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6598 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6599 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6600 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6601 EVT NewVT = V0_LO.getValueType();
6603 SDValue LO = DAG.getUNDEF(NewVT);
6604 SDValue HI = DAG.getUNDEF(NewVT);
6607 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6608 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6609 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6610 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6611 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6613 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6614 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6615 V1_LO->getOpcode() != ISD::UNDEF))
6616 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6618 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6619 V1_HI->getOpcode() != ISD::UNDEF))
6620 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6623 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6626 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6627 /// sequence of 'vadd + vsub + blendi'.
6628 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6629 const X86Subtarget *Subtarget) {
6631 EVT VT = BV->getValueType(0);
6632 unsigned NumElts = VT.getVectorNumElements();
6633 SDValue InVec0 = DAG.getUNDEF(VT);
6634 SDValue InVec1 = DAG.getUNDEF(VT);
6636 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6637 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6639 // Odd-numbered elements in the input build vector are obtained from
6640 // adding two integer/float elements.
6641 // Even-numbered elements in the input build vector are obtained from
6642 // subtracting two integer/float elements.
6643 unsigned ExpectedOpcode = ISD::FSUB;
6644 unsigned NextExpectedOpcode = ISD::FADD;
6645 bool AddFound = false;
6646 bool SubFound = false;
6648 for (unsigned i = 0, e = NumElts; i != e; i++) {
6649 SDValue Op = BV->getOperand(i);
6651 // Skip 'undef' values.
6652 unsigned Opcode = Op.getOpcode();
6653 if (Opcode == ISD::UNDEF) {
6654 std::swap(ExpectedOpcode, NextExpectedOpcode);
6658 // Early exit if we found an unexpected opcode.
6659 if (Opcode != ExpectedOpcode)
6662 SDValue Op0 = Op.getOperand(0);
6663 SDValue Op1 = Op.getOperand(1);
6665 // Try to match the following pattern:
6666 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6667 // Early exit if we cannot match that sequence.
6668 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6669 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6670 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6671 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6672 Op0.getOperand(1) != Op1.getOperand(1))
6675 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6679 // We found a valid add/sub node. Update the information accordingly.
6685 // Update InVec0 and InVec1.
6686 if (InVec0.getOpcode() == ISD::UNDEF)
6687 InVec0 = Op0.getOperand(0);
6688 if (InVec1.getOpcode() == ISD::UNDEF)
6689 InVec1 = Op1.getOperand(0);
6691 // Make sure that operands in input to each add/sub node always
6692 // come from a same pair of vectors.
6693 if (InVec0 != Op0.getOperand(0)) {
6694 if (ExpectedOpcode == ISD::FSUB)
6697 // FADD is commutable. Try to commute the operands
6698 // and then test again.
6699 std::swap(Op0, Op1);
6700 if (InVec0 != Op0.getOperand(0))
6704 if (InVec1 != Op1.getOperand(0))
6707 // Update the pair of expected opcodes.
6708 std::swap(ExpectedOpcode, NextExpectedOpcode);
6711 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6712 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6713 InVec1.getOpcode() != ISD::UNDEF)
6714 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6719 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6720 const X86Subtarget *Subtarget) {
6722 EVT VT = N->getValueType(0);
6723 unsigned NumElts = VT.getVectorNumElements();
6724 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6725 SDValue InVec0, InVec1;
6727 // Try to match an ADDSUB.
6728 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6729 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6730 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6731 if (Value.getNode())
6735 // Try to match horizontal ADD/SUB.
6736 unsigned NumUndefsLO = 0;
6737 unsigned NumUndefsHI = 0;
6738 unsigned Half = NumElts/2;
6740 // Count the number of UNDEF operands in the build_vector in input.
6741 for (unsigned i = 0, e = Half; i != e; ++i)
6742 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6745 for (unsigned i = Half, e = NumElts; i != e; ++i)
6746 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6749 // Early exit if this is either a build_vector of all UNDEFs or all the
6750 // operands but one are UNDEF.
6751 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6754 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6755 // Try to match an SSE3 float HADD/HSUB.
6756 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6757 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6759 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6760 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6761 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6762 // Try to match an SSSE3 integer HADD/HSUB.
6763 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6764 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6766 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6767 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6770 if (!Subtarget->hasAVX())
6773 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6774 // Try to match an AVX horizontal add/sub of packed single/double
6775 // precision floating point values from 256-bit vectors.
6776 SDValue InVec2, InVec3;
6777 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6778 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6779 ((InVec0.getOpcode() == ISD::UNDEF ||
6780 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6781 ((InVec1.getOpcode() == ISD::UNDEF ||
6782 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6783 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6785 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6786 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6787 ((InVec0.getOpcode() == ISD::UNDEF ||
6788 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6789 ((InVec1.getOpcode() == ISD::UNDEF ||
6790 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6791 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6792 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6793 // Try to match an AVX2 horizontal add/sub of signed integers.
6794 SDValue InVec2, InVec3;
6796 bool CanFold = true;
6798 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6799 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6800 ((InVec0.getOpcode() == ISD::UNDEF ||
6801 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6802 ((InVec1.getOpcode() == ISD::UNDEF ||
6803 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6804 X86Opcode = X86ISD::HADD;
6805 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6806 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6807 ((InVec0.getOpcode() == ISD::UNDEF ||
6808 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6809 ((InVec1.getOpcode() == ISD::UNDEF ||
6810 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6811 X86Opcode = X86ISD::HSUB;
6816 // Fold this build_vector into a single horizontal add/sub.
6817 // Do this only if the target has AVX2.
6818 if (Subtarget->hasAVX2())
6819 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6821 // Do not try to expand this build_vector into a pair of horizontal
6822 // add/sub if we can emit a pair of scalar add/sub.
6823 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6826 // Convert this build_vector into a pair of horizontal binop followed by
6828 bool isUndefLO = NumUndefsLO == Half;
6829 bool isUndefHI = NumUndefsHI == Half;
6830 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6831 isUndefLO, isUndefHI);
6835 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6836 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6838 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6839 X86Opcode = X86ISD::HADD;
6840 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6841 X86Opcode = X86ISD::HSUB;
6842 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6843 X86Opcode = X86ISD::FHADD;
6844 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6845 X86Opcode = X86ISD::FHSUB;
6849 // Don't try to expand this build_vector into a pair of horizontal add/sub
6850 // if we can simply emit a pair of scalar add/sub.
6851 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6854 // Convert this build_vector into two horizontal add/sub followed by
6856 bool isUndefLO = NumUndefsLO == Half;
6857 bool isUndefHI = NumUndefsHI == Half;
6858 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6859 isUndefLO, isUndefHI);
6866 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6869 MVT VT = Op.getSimpleValueType();
6870 MVT ExtVT = VT.getVectorElementType();
6871 unsigned NumElems = Op.getNumOperands();
6873 // Generate vectors for predicate vectors.
6874 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6875 return LowerBUILD_VECTORvXi1(Op, DAG);
6877 // Vectors containing all zeros can be matched by pxor and xorps later
6878 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6879 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6880 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6881 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6884 return getZeroVector(VT, Subtarget, DAG, dl);
6887 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6888 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6889 // vpcmpeqd on 256-bit vectors.
6890 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6891 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6894 if (!VT.is512BitVector())
6895 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6898 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6899 if (Broadcast.getNode())
6902 unsigned EVTBits = ExtVT.getSizeInBits();
6904 unsigned NumZero = 0;
6905 unsigned NumNonZero = 0;
6906 unsigned NonZeros = 0;
6907 bool IsAllConstants = true;
6908 SmallSet<SDValue, 8> Values;
6909 for (unsigned i = 0; i < NumElems; ++i) {
6910 SDValue Elt = Op.getOperand(i);
6911 if (Elt.getOpcode() == ISD::UNDEF)
6914 if (Elt.getOpcode() != ISD::Constant &&
6915 Elt.getOpcode() != ISD::ConstantFP)
6916 IsAllConstants = false;
6917 if (X86::isZeroNode(Elt))
6920 NonZeros |= (1 << i);
6925 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6926 if (NumNonZero == 0)
6927 return DAG.getUNDEF(VT);
6929 // Special case for single non-zero, non-undef, element.
6930 if (NumNonZero == 1) {
6931 unsigned Idx = countTrailingZeros(NonZeros);
6932 SDValue Item = Op.getOperand(Idx);
6934 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6935 // the value are obviously zero, truncate the value to i32 and do the
6936 // insertion that way. Only do this if the value is non-constant or if the
6937 // value is a constant being inserted into element 0. It is cheaper to do
6938 // a constant pool load than it is to do a movd + shuffle.
6939 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6940 (!IsAllConstants || Idx == 0)) {
6941 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6943 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6944 EVT VecVT = MVT::v4i32;
6945 unsigned VecElts = 4;
6947 // Truncate the value (which may itself be a constant) to i32, and
6948 // convert it to a vector with movd (S2V+shuffle to zero extend).
6949 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6950 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6952 // If using the new shuffle lowering, just directly insert this.
6953 if (ExperimentalVectorShuffleLowering)
6955 ISD::BITCAST, dl, VT,
6956 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6958 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6960 // Now we have our 32-bit value zero extended in the low element of
6961 // a vector. If Idx != 0, swizzle it into place.
6963 SmallVector<int, 4> Mask;
6964 Mask.push_back(Idx);
6965 for (unsigned i = 1; i != VecElts; ++i)
6967 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6970 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6974 // If we have a constant or non-constant insertion into the low element of
6975 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6976 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6977 // depending on what the source datatype is.
6980 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6982 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6983 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6984 if (VT.is256BitVector() || VT.is512BitVector()) {
6985 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6986 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6987 Item, DAG.getIntPtrConstant(0));
6989 assert(VT.is128BitVector() && "Expected an SSE value type!");
6990 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6991 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6992 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6995 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6996 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6997 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6998 if (VT.is256BitVector()) {
6999 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
7000 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
7002 assert(VT.is128BitVector() && "Expected an SSE value type!");
7003 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
7005 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
7009 // Is it a vector logical left shift?
7010 if (NumElems == 2 && Idx == 1 &&
7011 X86::isZeroNode(Op.getOperand(0)) &&
7012 !X86::isZeroNode(Op.getOperand(1))) {
7013 unsigned NumBits = VT.getSizeInBits();
7014 return getVShift(true, VT,
7015 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7016 VT, Op.getOperand(1)),
7017 NumBits/2, DAG, *this, dl);
7020 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7023 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7024 // is a non-constant being inserted into an element other than the low one,
7025 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7026 // movd/movss) to move this into the low element, then shuffle it into
7028 if (EVTBits == 32) {
7029 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7031 // If using the new shuffle lowering, just directly insert this.
7032 if (ExperimentalVectorShuffleLowering)
7033 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7035 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7036 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7037 SmallVector<int, 8> MaskVec;
7038 for (unsigned i = 0; i != NumElems; ++i)
7039 MaskVec.push_back(i == Idx ? 0 : 1);
7040 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7044 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7045 if (Values.size() == 1) {
7046 if (EVTBits == 32) {
7047 // Instead of a shuffle like this:
7048 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7049 // Check if it's possible to issue this instead.
7050 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7051 unsigned Idx = countTrailingZeros(NonZeros);
7052 SDValue Item = Op.getOperand(Idx);
7053 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7054 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7059 // A vector full of immediates; various special cases are already
7060 // handled, so this is best done with a single constant-pool load.
7064 // For AVX-length vectors, see if we can use a vector load to get all of the
7065 // elements, otherwise build the individual 128-bit pieces and use
7066 // shuffles to put them in place.
7067 if (VT.is256BitVector() || VT.is512BitVector()) {
7068 SmallVector<SDValue, 64> V;
7069 for (unsigned i = 0; i != NumElems; ++i)
7070 V.push_back(Op.getOperand(i));
7072 // Check for a build vector of consecutive loads.
7073 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7076 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7078 // Build both the lower and upper subvector.
7079 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7080 makeArrayRef(&V[0], NumElems/2));
7081 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7082 makeArrayRef(&V[NumElems / 2], NumElems/2));
7084 // Recreate the wider vector with the lower and upper part.
7085 if (VT.is256BitVector())
7086 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7087 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7090 // Let legalizer expand 2-wide build_vectors.
7091 if (EVTBits == 64) {
7092 if (NumNonZero == 1) {
7093 // One half is zero or undef.
7094 unsigned Idx = countTrailingZeros(NonZeros);
7095 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7096 Op.getOperand(Idx));
7097 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7102 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7103 if (EVTBits == 8 && NumElems == 16) {
7104 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7106 if (V.getNode()) return V;
7109 if (EVTBits == 16 && NumElems == 8) {
7110 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7112 if (V.getNode()) return V;
7115 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7116 if (EVTBits == 32 && NumElems == 4) {
7117 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7122 // If element VT is == 32 bits, turn it into a number of shuffles.
7123 SmallVector<SDValue, 8> V(NumElems);
7124 if (NumElems == 4 && NumZero > 0) {
7125 for (unsigned i = 0; i < 4; ++i) {
7126 bool isZero = !(NonZeros & (1 << i));
7128 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7130 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7133 for (unsigned i = 0; i < 2; ++i) {
7134 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7137 V[i] = V[i*2]; // Must be a zero vector.
7140 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7143 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7146 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7151 bool Reverse1 = (NonZeros & 0x3) == 2;
7152 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7156 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7157 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7159 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7162 if (Values.size() > 1 && VT.is128BitVector()) {
7163 // Check for a build vector of consecutive loads.
7164 for (unsigned i = 0; i < NumElems; ++i)
7165 V[i] = Op.getOperand(i);
7167 // Check for elements which are consecutive loads.
7168 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7172 // Check for a build vector from mostly shuffle plus few inserting.
7173 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7177 // For SSE 4.1, use insertps to put the high elements into the low element.
7178 if (getSubtarget()->hasSSE41()) {
7180 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7181 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7183 Result = DAG.getUNDEF(VT);
7185 for (unsigned i = 1; i < NumElems; ++i) {
7186 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7187 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7188 Op.getOperand(i), DAG.getIntPtrConstant(i));
7193 // Otherwise, expand into a number of unpckl*, start by extending each of
7194 // our (non-undef) elements to the full vector width with the element in the
7195 // bottom slot of the vector (which generates no code for SSE).
7196 for (unsigned i = 0; i < NumElems; ++i) {
7197 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7198 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7200 V[i] = DAG.getUNDEF(VT);
7203 // Next, we iteratively mix elements, e.g. for v4f32:
7204 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7205 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7206 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7207 unsigned EltStride = NumElems >> 1;
7208 while (EltStride != 0) {
7209 for (unsigned i = 0; i < EltStride; ++i) {
7210 // If V[i+EltStride] is undef and this is the first round of mixing,
7211 // then it is safe to just drop this shuffle: V[i] is already in the
7212 // right place, the one element (since it's the first round) being
7213 // inserted as undef can be dropped. This isn't safe for successive
7214 // rounds because they will permute elements within both vectors.
7215 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7216 EltStride == NumElems/2)
7219 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7228 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7229 // to create 256-bit vectors from two other 128-bit ones.
7230 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7232 MVT ResVT = Op.getSimpleValueType();
7234 assert((ResVT.is256BitVector() ||
7235 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7237 SDValue V1 = Op.getOperand(0);
7238 SDValue V2 = Op.getOperand(1);
7239 unsigned NumElems = ResVT.getVectorNumElements();
7240 if(ResVT.is256BitVector())
7241 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7243 if (Op.getNumOperands() == 4) {
7244 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7245 ResVT.getVectorNumElements()/2);
7246 SDValue V3 = Op.getOperand(2);
7247 SDValue V4 = Op.getOperand(3);
7248 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7249 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7251 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7254 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7255 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7256 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7257 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7258 Op.getNumOperands() == 4)));
7260 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7261 // from two other 128-bit ones.
7263 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7264 return LowerAVXCONCAT_VECTORS(Op, DAG);
7268 //===----------------------------------------------------------------------===//
7269 // Vector shuffle lowering
7271 // This is an experimental code path for lowering vector shuffles on x86. It is
7272 // designed to handle arbitrary vector shuffles and blends, gracefully
7273 // degrading performance as necessary. It works hard to recognize idiomatic
7274 // shuffles and lower them to optimal instruction patterns without leaving
7275 // a framework that allows reasonably efficient handling of all vector shuffle
7277 //===----------------------------------------------------------------------===//
7279 /// \brief Tiny helper function to identify a no-op mask.
7281 /// This is a somewhat boring predicate function. It checks whether the mask
7282 /// array input, which is assumed to be a single-input shuffle mask of the kind
7283 /// used by the X86 shuffle instructions (not a fully general
7284 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7285 /// in-place shuffle are 'no-op's.
7286 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7287 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7288 if (Mask[i] != -1 && Mask[i] != i)
7293 /// \brief Helper function to classify a mask as a single-input mask.
7295 /// This isn't a generic single-input test because in the vector shuffle
7296 /// lowering we canonicalize single inputs to be the first input operand. This
7297 /// means we can more quickly test for a single input by only checking whether
7298 /// an input from the second operand exists. We also assume that the size of
7299 /// mask corresponds to the size of the input vectors which isn't true in the
7300 /// fully general case.
7301 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7303 if (M >= (int)Mask.size())
7308 /// \brief Test whether there are elements crossing 128-bit lanes in this
7311 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7312 /// and we routinely test for these.
7313 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7314 int LaneSize = 128 / VT.getScalarSizeInBits();
7315 int Size = Mask.size();
7316 for (int i = 0; i < Size; ++i)
7317 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7322 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7324 /// This checks a shuffle mask to see if it is performing the same
7325 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7326 /// that it is also not lane-crossing. It may however involve a blend from the
7327 /// same lane of a second vector.
7329 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7330 /// non-trivial to compute in the face of undef lanes. The representation is
7331 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7332 /// entries from both V1 and V2 inputs to the wider mask.
7334 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7335 SmallVectorImpl<int> &RepeatedMask) {
7336 int LaneSize = 128 / VT.getScalarSizeInBits();
7337 RepeatedMask.resize(LaneSize, -1);
7338 int Size = Mask.size();
7339 for (int i = 0; i < Size; ++i) {
7342 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7343 // This entry crosses lanes, so there is no way to model this shuffle.
7346 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7347 if (RepeatedMask[i % LaneSize] == -1)
7348 // This is the first non-undef entry in this slot of a 128-bit lane.
7349 RepeatedMask[i % LaneSize] =
7350 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7351 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7352 // Found a mismatch with the repeated mask.
7358 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7359 // 2013 will allow us to use it as a non-type template parameter.
7362 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7364 /// See its documentation for details.
7365 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7366 if (Mask.size() != Args.size())
7368 for (int i = 0, e = Mask.size(); i < e; ++i) {
7369 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7370 if (Mask[i] != -1 && Mask[i] != *Args[i])
7378 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7381 /// This is a fast way to test a shuffle mask against a fixed pattern:
7383 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7385 /// It returns true if the mask is exactly as wide as the argument list, and
7386 /// each element of the mask is either -1 (signifying undef) or the value given
7387 /// in the argument.
7388 static const VariadicFunction1<
7389 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7391 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7393 /// This helper function produces an 8-bit shuffle immediate corresponding to
7394 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7395 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7398 /// NB: We rely heavily on "undef" masks preserving the input lane.
7399 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7400 SelectionDAG &DAG) {
7401 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7402 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7403 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7404 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7405 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7408 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7409 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7410 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7411 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7412 return DAG.getConstant(Imm, MVT::i8);
7415 /// \brief Try to emit a blend instruction for a shuffle.
7417 /// This doesn't do any checks for the availability of instructions for blending
7418 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7419 /// be matched in the backend with the type given. What it does check for is
7420 /// that the shuffle mask is in fact a blend.
7421 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7422 SDValue V2, ArrayRef<int> Mask,
7423 const X86Subtarget *Subtarget,
7424 SelectionDAG &DAG) {
7426 unsigned BlendMask = 0;
7427 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7428 if (Mask[i] >= Size) {
7429 if (Mask[i] != i + Size)
7430 return SDValue(); // Shuffled V2 input!
7431 BlendMask |= 1u << i;
7434 if (Mask[i] >= 0 && Mask[i] != i)
7435 return SDValue(); // Shuffled V1 input!
7437 switch (VT.SimpleTy) {
7442 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7443 DAG.getConstant(BlendMask, MVT::i8));
7447 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7451 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7452 // that instruction.
7453 if (Subtarget->hasAVX2()) {
7454 // Scale the blend by the number of 32-bit dwords per element.
7455 int Scale = VT.getScalarSizeInBits() / 32;
7457 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7458 if (Mask[i] >= Size)
7459 for (int j = 0; j < Scale; ++j)
7460 BlendMask |= 1u << (i * Scale + j);
7462 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7463 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7464 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7465 return DAG.getNode(ISD::BITCAST, DL, VT,
7466 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7467 DAG.getConstant(BlendMask, MVT::i8)));
7471 // For integer shuffles we need to expand the mask and cast the inputs to
7472 // v8i16s prior to blending.
7473 int Scale = 8 / VT.getVectorNumElements();
7475 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7476 if (Mask[i] >= Size)
7477 for (int j = 0; j < Scale; ++j)
7478 BlendMask |= 1u << (i * Scale + j);
7480 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7481 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7482 return DAG.getNode(ISD::BITCAST, DL, VT,
7483 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7484 DAG.getConstant(BlendMask, MVT::i8)));
7488 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7489 SmallVector<int, 8> RepeatedMask;
7490 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7491 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7492 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7494 for (int i = 0; i < 8; ++i)
7495 if (RepeatedMask[i] >= 16)
7496 BlendMask |= 1u << i;
7497 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7498 DAG.getConstant(BlendMask, MVT::i8));
7503 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7504 // Scale the blend by the number of bytes per element.
7505 int Scale = VT.getScalarSizeInBits() / 8;
7506 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7508 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7509 // mix of LLVM's code generator and the x86 backend. We tell the code
7510 // generator that boolean values in the elements of an x86 vector register
7511 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7512 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7513 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7514 // of the element (the remaining are ignored) and 0 in that high bit would
7515 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7516 // the LLVM model for boolean values in vector elements gets the relevant
7517 // bit set, it is set backwards and over constrained relative to x86's
7519 SDValue VSELECTMask[32];
7520 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7521 for (int j = 0; j < Scale; ++j)
7522 VSELECTMask[Scale * i + j] =
7523 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7524 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7526 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7527 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7529 ISD::BITCAST, DL, VT,
7530 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7531 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7536 llvm_unreachable("Not a supported integer vector type!");
7540 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7541 /// unblended shuffles followed by an unshuffled blend.
7543 /// This matches the extremely common pattern for handling combined
7544 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7546 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7550 SelectionDAG &DAG) {
7551 // Shuffle the input elements into the desired positions in V1 and V2 and
7552 // blend them together.
7553 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7554 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7555 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7556 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7557 if (Mask[i] >= 0 && Mask[i] < Size) {
7558 V1Mask[i] = Mask[i];
7560 } else if (Mask[i] >= Size) {
7561 V2Mask[i] = Mask[i] - Size;
7562 BlendMask[i] = i + Size;
7565 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7566 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7567 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7570 /// \brief Try to lower a vector shuffle as a byte rotation.
7572 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7573 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7574 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7575 /// try to generically lower a vector shuffle through such an pattern. It
7576 /// does not check for the profitability of lowering either as PALIGNR or
7577 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7578 /// This matches shuffle vectors that look like:
7580 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7582 /// Essentially it concatenates V1 and V2, shifts right by some number of
7583 /// elements, and takes the low elements as the result. Note that while this is
7584 /// specified as a *right shift* because x86 is little-endian, it is a *left
7585 /// rotate* of the vector lanes.
7587 /// Note that this only handles 128-bit vector widths currently.
7588 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7591 const X86Subtarget *Subtarget,
7592 SelectionDAG &DAG) {
7593 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7595 // We need to detect various ways of spelling a rotation:
7596 // [11, 12, 13, 14, 15, 0, 1, 2]
7597 // [-1, 12, 13, 14, -1, -1, 1, -1]
7598 // [-1, -1, -1, -1, -1, -1, 1, 2]
7599 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7600 // [-1, 4, 5, 6, -1, -1, 9, -1]
7601 // [-1, 4, 5, 6, -1, -1, -1, -1]
7604 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7607 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7609 // Based on the mod-Size value of this mask element determine where
7610 // a rotated vector would have started.
7611 int StartIdx = i - (Mask[i] % Size);
7613 // The identity rotation isn't interesting, stop.
7616 // If we found the tail of a vector the rotation must be the missing
7617 // front. If we found the head of a vector, it must be how much of the head.
7618 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7621 Rotation = CandidateRotation;
7622 else if (Rotation != CandidateRotation)
7623 // The rotations don't match, so we can't match this mask.
7626 // Compute which value this mask is pointing at.
7627 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7629 // Compute which of the two target values this index should be assigned to.
7630 // This reflects whether the high elements are remaining or the low elements
7632 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7634 // Either set up this value if we've not encountered it before, or check
7635 // that it remains consistent.
7638 else if (TargetV != MaskV)
7639 // This may be a rotation, but it pulls from the inputs in some
7640 // unsupported interleaving.
7644 // Check that we successfully analyzed the mask, and normalize the results.
7645 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7646 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7652 assert(VT.getSizeInBits() == 128 &&
7653 "Rotate-based lowering only supports 128-bit lowering!");
7654 assert(Mask.size() <= 16 &&
7655 "Can shuffle at most 16 bytes in a 128-bit vector!");
7657 // The actual rotate instruction rotates bytes, so we need to scale the
7658 // rotation based on how many bytes are in the vector.
7659 int Scale = 16 / Mask.size();
7661 // SSSE3 targets can use the palignr instruction
7662 if (Subtarget->hasSSSE3()) {
7663 // Cast the inputs to v16i8 to match PALIGNR.
7664 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7665 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7667 return DAG.getNode(ISD::BITCAST, DL, VT,
7668 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7669 DAG.getConstant(Rotation * Scale, MVT::i8)));
7672 // Default SSE2 implementation
7673 int LoByteShift = 16 - Rotation * Scale;
7674 int HiByteShift = Rotation * Scale;
7676 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7677 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7678 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7680 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7681 DAG.getConstant(8 * LoByteShift, MVT::i8));
7682 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7683 DAG.getConstant(8 * HiByteShift, MVT::i8));
7684 return DAG.getNode(ISD::BITCAST, DL, VT,
7685 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7688 /// \brief Compute whether each element of a shuffle is zeroable.
7690 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7691 /// Either it is an undef element in the shuffle mask, the element of the input
7692 /// referenced is undef, or the element of the input referenced is known to be
7693 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7694 /// as many lanes with this technique as possible to simplify the remaining
7696 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7697 SDValue V1, SDValue V2) {
7698 SmallBitVector Zeroable(Mask.size(), false);
7700 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7701 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7703 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7705 // Handle the easy cases.
7706 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7711 // If this is an index into a build_vector node, dig out the input value and
7713 SDValue V = M < Size ? V1 : V2;
7714 if (V.getOpcode() != ISD::BUILD_VECTOR)
7717 SDValue Input = V.getOperand(M % Size);
7718 // The UNDEF opcode check really should be dead code here, but not quite
7719 // worth asserting on (it isn't invalid, just unexpected).
7720 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7727 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7729 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7730 /// byte-shift instructions. The mask must consist of a shifted sequential
7731 /// shuffle from one of the input vectors and zeroable elements for the
7732 /// remaining 'shifted in' elements.
7734 /// Note that this only handles 128-bit vector widths currently.
7735 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7736 SDValue V2, ArrayRef<int> Mask,
7737 SelectionDAG &DAG) {
7738 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7740 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7742 int Size = Mask.size();
7743 int Scale = 16 / Size;
7745 for (int Shift = 1; Shift < Size; Shift++) {
7746 int ByteShift = Shift * Scale;
7748 // PSRLDQ : (little-endian) right byte shift
7749 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7750 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7751 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7752 bool ZeroableRight = true;
7753 for (int i = Size - Shift; i < Size; i++) {
7754 ZeroableRight &= Zeroable[i];
7757 if (ZeroableRight) {
7758 bool ValidShiftRight1 =
7759 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Shift);
7760 bool ValidShiftRight2 =
7761 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Size + Shift);
7763 if (ValidShiftRight1 || ValidShiftRight2) {
7764 // Cast the inputs to v2i64 to match PSRLDQ.
7765 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7766 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7767 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7768 DAG.getConstant(ByteShift * 8, MVT::i8));
7769 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7773 // PSLLDQ : (little-endian) left byte shift
7774 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7775 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7776 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7777 bool ZeroableLeft = true;
7778 for (int i = 0; i < Shift; i++) {
7779 ZeroableLeft &= Zeroable[i];
7783 bool ValidShiftLeft1 =
7784 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, 0);
7785 bool ValidShiftLeft2 =
7786 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, Size);
7788 if (ValidShiftLeft1 || ValidShiftLeft2) {
7789 // Cast the inputs to v2i64 to match PSLLDQ.
7790 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7791 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7792 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7793 DAG.getConstant(ByteShift * 8, MVT::i8));
7794 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7802 /// \brief Lower a vector shuffle as a zero or any extension.
7804 /// Given a specific number of elements, element bit width, and extension
7805 /// stride, produce either a zero or any extension based on the available
7806 /// features of the subtarget.
7807 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7808 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7809 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7810 assert(Scale > 1 && "Need a scale to extend.");
7811 int EltBits = VT.getSizeInBits() / NumElements;
7812 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7813 "Only 8, 16, and 32 bit elements can be extended.");
7814 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7816 // Found a valid zext mask! Try various lowering strategies based on the
7817 // input type and available ISA extensions.
7818 if (Subtarget->hasSSE41()) {
7819 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7820 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7821 NumElements / Scale);
7822 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7823 return DAG.getNode(ISD::BITCAST, DL, VT,
7824 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7827 // For any extends we can cheat for larger element sizes and use shuffle
7828 // instructions that can fold with a load and/or copy.
7829 if (AnyExt && EltBits == 32) {
7830 int PSHUFDMask[4] = {0, -1, 1, -1};
7832 ISD::BITCAST, DL, VT,
7833 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7834 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7835 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7837 if (AnyExt && EltBits == 16 && Scale > 2) {
7838 int PSHUFDMask[4] = {0, -1, 0, -1};
7839 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7840 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7841 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7842 int PSHUFHWMask[4] = {1, -1, -1, -1};
7844 ISD::BITCAST, DL, VT,
7845 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7846 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7847 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7850 // If this would require more than 2 unpack instructions to expand, use
7851 // pshufb when available. We can only use more than 2 unpack instructions
7852 // when zero extending i8 elements which also makes it easier to use pshufb.
7853 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7854 assert(NumElements == 16 && "Unexpected byte vector width!");
7855 SDValue PSHUFBMask[16];
7856 for (int i = 0; i < 16; ++i)
7858 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7859 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7860 return DAG.getNode(ISD::BITCAST, DL, VT,
7861 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7862 DAG.getNode(ISD::BUILD_VECTOR, DL,
7863 MVT::v16i8, PSHUFBMask)));
7866 // Otherwise emit a sequence of unpacks.
7868 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7869 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7870 : getZeroVector(InputVT, Subtarget, DAG, DL);
7871 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7872 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7876 } while (Scale > 1);
7877 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7880 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7882 /// This routine will try to do everything in its power to cleverly lower
7883 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7884 /// check for the profitability of this lowering, it tries to aggressively
7885 /// match this pattern. It will use all of the micro-architectural details it
7886 /// can to emit an efficient lowering. It handles both blends with all-zero
7887 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7888 /// masking out later).
7890 /// The reason we have dedicated lowering for zext-style shuffles is that they
7891 /// are both incredibly common and often quite performance sensitive.
7892 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7893 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7894 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7895 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7897 int Bits = VT.getSizeInBits();
7898 int NumElements = Mask.size();
7900 // Define a helper function to check a particular ext-scale and lower to it if
7902 auto Lower = [&](int Scale) -> SDValue {
7905 for (int i = 0; i < NumElements; ++i) {
7907 continue; // Valid anywhere but doesn't tell us anything.
7908 if (i % Scale != 0) {
7909 // Each of the extend elements needs to be zeroable.
7913 // We no lorger are in the anyext case.
7918 // Each of the base elements needs to be consecutive indices into the
7919 // same input vector.
7920 SDValue V = Mask[i] < NumElements ? V1 : V2;
7923 else if (InputV != V)
7924 return SDValue(); // Flip-flopping inputs.
7926 if (Mask[i] % NumElements != i / Scale)
7927 return SDValue(); // Non-consecutive strided elemenst.
7930 // If we fail to find an input, we have a zero-shuffle which should always
7931 // have already been handled.
7932 // FIXME: Maybe handle this here in case during blending we end up with one?
7936 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7937 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7940 // The widest scale possible for extending is to a 64-bit integer.
7941 assert(Bits % 64 == 0 &&
7942 "The number of bits in a vector must be divisible by 64 on x86!");
7943 int NumExtElements = Bits / 64;
7945 // Each iteration, try extending the elements half as much, but into twice as
7947 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7948 assert(NumElements % NumExtElements == 0 &&
7949 "The input vector size must be divisble by the extended size.");
7950 if (SDValue V = Lower(NumElements / NumExtElements))
7954 // No viable ext lowering found.
7958 /// \brief Try to get a scalar value for a specific element of a vector.
7960 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7961 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7962 SelectionDAG &DAG) {
7963 MVT VT = V.getSimpleValueType();
7964 MVT EltVT = VT.getVectorElementType();
7965 while (V.getOpcode() == ISD::BITCAST)
7966 V = V.getOperand(0);
7967 // If the bitcasts shift the element size, we can't extract an equivalent
7969 MVT NewVT = V.getSimpleValueType();
7970 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7973 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7974 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7975 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7980 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7982 /// This is particularly important because the set of instructions varies
7983 /// significantly based on whether the operand is a load or not.
7984 static bool isShuffleFoldableLoad(SDValue V) {
7985 while (V.getOpcode() == ISD::BITCAST)
7986 V = V.getOperand(0);
7988 return ISD::isNON_EXTLoad(V.getNode());
7991 /// \brief Try to lower insertion of a single element into a zero vector.
7993 /// This is a common pattern that we have especially efficient patterns to lower
7994 /// across all subtarget feature sets.
7995 static SDValue lowerVectorShuffleAsElementInsertion(
7996 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7997 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7998 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8000 MVT EltVT = VT.getVectorElementType();
8002 int V2Index = std::find_if(Mask.begin(), Mask.end(),
8003 [&Mask](int M) { return M >= (int)Mask.size(); }) -
8005 bool IsV1Zeroable = true;
8006 for (int i = 0, Size = Mask.size(); i < Size; ++i)
8007 if (i != V2Index && !Zeroable[i]) {
8008 IsV1Zeroable = false;
8012 // Check for a single input from a SCALAR_TO_VECTOR node.
8013 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
8014 // all the smarts here sunk into that routine. However, the current
8015 // lowering of BUILD_VECTOR makes that nearly impossible until the old
8016 // vector shuffle lowering is dead.
8017 if (SDValue V2S = getScalarValueForVectorElement(
8018 V2, Mask[V2Index] - Mask.size(), DAG)) {
8019 // We need to zext the scalar if it is smaller than an i32.
8020 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8021 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8022 // Using zext to expand a narrow element won't work for non-zero
8027 // Zero-extend directly to i32.
8029 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8031 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8032 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8033 EltVT == MVT::i16) {
8034 // Either not inserting from the low element of the input or the input
8035 // element size is too small to use VZEXT_MOVL to clear the high bits.
8039 if (!IsV1Zeroable) {
8040 // If V1 can't be treated as a zero vector we have fewer options to lower
8041 // this. We can't support integer vectors or non-zero targets cheaply, and
8042 // the V1 elements can't be permuted in any way.
8043 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8044 if (!VT.isFloatingPoint() || V2Index != 0)
8046 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8047 V1Mask[V2Index] = -1;
8048 if (!isNoopShuffleMask(V1Mask))
8050 // This is essentially a special case blend operation, but if we have
8051 // general purpose blend operations, they are always faster. Bail and let
8052 // the rest of the lowering handle these as blends.
8053 if (Subtarget->hasSSE41())
8056 // Otherwise, use MOVSD or MOVSS.
8057 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8058 "Only two types of floating point element types to handle!");
8059 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8063 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8065 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8068 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8069 // the desired position. Otherwise it is more efficient to do a vector
8070 // shift left. We know that we can do a vector shift left because all
8071 // the inputs are zero.
8072 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8073 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8074 V2Shuffle[V2Index] = 0;
8075 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8077 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8079 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8081 V2Index * EltVT.getSizeInBits(),
8082 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8083 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8089 /// \brief Try to lower broadcast of a single element.
8091 /// For convenience, this code also bundles all of the subtarget feature set
8092 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8093 /// a convenient way to factor it out.
8094 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8096 const X86Subtarget *Subtarget,
8097 SelectionDAG &DAG) {
8098 if (!Subtarget->hasAVX())
8100 if (VT.isInteger() && !Subtarget->hasAVX2())
8103 // Check that the mask is a broadcast.
8104 int BroadcastIdx = -1;
8106 if (M >= 0 && BroadcastIdx == -1)
8108 else if (M >= 0 && M != BroadcastIdx)
8111 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8112 "a sorted mask where the broadcast "
8115 // Go up the chain of (vector) values to try and find a scalar load that
8116 // we can combine with the broadcast.
8118 switch (V.getOpcode()) {
8119 case ISD::CONCAT_VECTORS: {
8120 int OperandSize = Mask.size() / V.getNumOperands();
8121 V = V.getOperand(BroadcastIdx / OperandSize);
8122 BroadcastIdx %= OperandSize;
8126 case ISD::INSERT_SUBVECTOR: {
8127 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8128 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8132 int BeginIdx = (int)ConstantIdx->getZExtValue();
8134 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8135 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8136 BroadcastIdx -= BeginIdx;
8147 // Check if this is a broadcast of a scalar. We special case lowering
8148 // for scalars so that we can more effectively fold with loads.
8149 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8150 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8151 V = V.getOperand(BroadcastIdx);
8153 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8155 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8157 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8158 // We can't broadcast from a vector register w/o AVX2, and we can only
8159 // broadcast from the zero-element of a vector register.
8163 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8166 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8168 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8169 /// support for floating point shuffles but not integer shuffles. These
8170 /// instructions will incur a domain crossing penalty on some chips though so
8171 /// it is better to avoid lowering through this for integer vectors where
8173 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8174 const X86Subtarget *Subtarget,
8175 SelectionDAG &DAG) {
8177 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8178 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8179 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8181 ArrayRef<int> Mask = SVOp->getMask();
8182 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8184 if (isSingleInputShuffleMask(Mask)) {
8185 // Straight shuffle of a single input vector. Simulate this by using the
8186 // single input as both of the "inputs" to this instruction..
8187 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8189 if (Subtarget->hasAVX()) {
8190 // If we have AVX, we can use VPERMILPS which will allow folding a load
8191 // into the shuffle.
8192 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8193 DAG.getConstant(SHUFPDMask, MVT::i8));
8196 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8197 DAG.getConstant(SHUFPDMask, MVT::i8));
8199 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8200 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8202 // Use dedicated unpack instructions for masks that match their pattern.
8203 if (isShuffleEquivalent(Mask, 0, 2))
8204 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8205 if (isShuffleEquivalent(Mask, 1, 3))
8206 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8208 // If we have a single input, insert that into V1 if we can do so cheaply.
8209 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8210 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8211 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8213 // Try inverting the insertion since for v2 masks it is easy to do and we
8214 // can't reliably sort the mask one way or the other.
8215 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8216 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8217 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8218 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8222 // Try to use one of the special instruction patterns to handle two common
8223 // blend patterns if a zero-blend above didn't work.
8224 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8225 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8226 // We can either use a special instruction to load over the low double or
8227 // to move just the low double.
8229 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8231 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8233 if (Subtarget->hasSSE41())
8234 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8238 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8239 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8240 DAG.getConstant(SHUFPDMask, MVT::i8));
8243 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8245 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8246 /// the integer unit to minimize domain crossing penalties. However, for blends
8247 /// it falls back to the floating point shuffle operation with appropriate bit
8249 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8250 const X86Subtarget *Subtarget,
8251 SelectionDAG &DAG) {
8253 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8254 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8255 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8256 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8257 ArrayRef<int> Mask = SVOp->getMask();
8258 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8260 if (isSingleInputShuffleMask(Mask)) {
8261 // Check for being able to broadcast a single element.
8262 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8263 Mask, Subtarget, DAG))
8266 // Straight shuffle of a single input vector. For everything from SSE2
8267 // onward this has a single fast instruction with no scary immediates.
8268 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8269 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8270 int WidenedMask[4] = {
8271 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8272 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8274 ISD::BITCAST, DL, MVT::v2i64,
8275 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8276 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8279 // Try to use byte shift instructions.
8280 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8281 DL, MVT::v2i64, V1, V2, Mask, DAG))
8284 // If we have a single input from V2 insert that into V1 if we can do so
8286 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8287 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8288 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8290 // Try inverting the insertion since for v2 masks it is easy to do and we
8291 // can't reliably sort the mask one way or the other.
8292 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8293 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8294 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8295 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8299 // Use dedicated unpack instructions for masks that match their pattern.
8300 if (isShuffleEquivalent(Mask, 0, 2))
8301 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8302 if (isShuffleEquivalent(Mask, 1, 3))
8303 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8305 if (Subtarget->hasSSE41())
8306 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8310 // Try to use byte rotation instructions.
8311 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8312 if (Subtarget->hasSSSE3())
8313 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8314 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8317 // We implement this with SHUFPD which is pretty lame because it will likely
8318 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8319 // However, all the alternatives are still more cycles and newer chips don't
8320 // have this problem. It would be really nice if x86 had better shuffles here.
8321 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8322 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8323 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8324 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8327 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8329 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8330 /// It makes no assumptions about whether this is the *best* lowering, it simply
8332 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8333 ArrayRef<int> Mask, SDValue V1,
8334 SDValue V2, SelectionDAG &DAG) {
8335 SDValue LowV = V1, HighV = V2;
8336 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8339 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8341 if (NumV2Elements == 1) {
8343 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8346 // Compute the index adjacent to V2Index and in the same half by toggling
8348 int V2AdjIndex = V2Index ^ 1;
8350 if (Mask[V2AdjIndex] == -1) {
8351 // Handles all the cases where we have a single V2 element and an undef.
8352 // This will only ever happen in the high lanes because we commute the
8353 // vector otherwise.
8355 std::swap(LowV, HighV);
8356 NewMask[V2Index] -= 4;
8358 // Handle the case where the V2 element ends up adjacent to a V1 element.
8359 // To make this work, blend them together as the first step.
8360 int V1Index = V2AdjIndex;
8361 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8362 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8363 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8365 // Now proceed to reconstruct the final blend as we have the necessary
8366 // high or low half formed.
8373 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8374 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8376 } else if (NumV2Elements == 2) {
8377 if (Mask[0] < 4 && Mask[1] < 4) {
8378 // Handle the easy case where we have V1 in the low lanes and V2 in the
8382 } else if (Mask[2] < 4 && Mask[3] < 4) {
8383 // We also handle the reversed case because this utility may get called
8384 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8385 // arrange things in the right direction.
8391 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8392 // trying to place elements directly, just blend them and set up the final
8393 // shuffle to place them.
8395 // The first two blend mask elements are for V1, the second two are for
8397 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8398 Mask[2] < 4 ? Mask[2] : Mask[3],
8399 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8400 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8401 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8402 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8404 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8407 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8408 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8409 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8410 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8413 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8414 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8417 /// \brief Lower 4-lane 32-bit floating point shuffles.
8419 /// Uses instructions exclusively from the floating point unit to minimize
8420 /// domain crossing penalties, as these are sufficient to implement all v4f32
8422 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8423 const X86Subtarget *Subtarget,
8424 SelectionDAG &DAG) {
8426 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8427 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8428 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8429 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8430 ArrayRef<int> Mask = SVOp->getMask();
8431 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8434 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8436 if (NumV2Elements == 0) {
8437 // Check for being able to broadcast a single element.
8438 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8439 Mask, Subtarget, DAG))
8442 if (Subtarget->hasAVX()) {
8443 // If we have AVX, we can use VPERMILPS which will allow folding a load
8444 // into the shuffle.
8445 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8446 getV4X86ShuffleImm8ForMask(Mask, DAG));
8449 // Otherwise, use a straight shuffle of a single input vector. We pass the
8450 // input vector to both operands to simulate this with a SHUFPS.
8451 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8452 getV4X86ShuffleImm8ForMask(Mask, DAG));
8455 // Use dedicated unpack instructions for masks that match their pattern.
8456 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8457 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8458 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8459 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8461 // There are special ways we can lower some single-element blends. However, we
8462 // have custom ways we can lower more complex single-element blends below that
8463 // we defer to if both this and BLENDPS fail to match, so restrict this to
8464 // when the V2 input is targeting element 0 of the mask -- that is the fast
8466 if (NumV2Elements == 1 && Mask[0] >= 4)
8467 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8468 Mask, Subtarget, DAG))
8471 if (Subtarget->hasSSE41())
8472 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8476 // Check for whether we can use INSERTPS to perform the blend. We only use
8477 // INSERTPS when the V1 elements are already in the correct locations
8478 // because otherwise we can just always use two SHUFPS instructions which
8479 // are much smaller to encode than a SHUFPS and an INSERTPS.
8480 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8482 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8485 // When using INSERTPS we can zero any lane of the destination. Collect
8486 // the zero inputs into a mask and drop them from the lanes of V1 which
8487 // actually need to be present as inputs to the INSERTPS.
8488 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8490 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8491 bool InsertNeedsShuffle = false;
8493 for (int i = 0; i < 4; ++i)
8497 } else if (Mask[i] != i) {
8498 InsertNeedsShuffle = true;
8503 // We don't want to use INSERTPS or other insertion techniques if it will
8504 // require shuffling anyways.
8505 if (!InsertNeedsShuffle) {
8506 // If all of V1 is zeroable, replace it with undef.
8507 if ((ZMask | 1 << V2Index) == 0xF)
8508 V1 = DAG.getUNDEF(MVT::v4f32);
8510 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8511 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8513 // Insert the V2 element into the desired position.
8514 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8515 DAG.getConstant(InsertPSMask, MVT::i8));
8519 // Otherwise fall back to a SHUFPS lowering strategy.
8520 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8523 /// \brief Lower 4-lane i32 vector shuffles.
8525 /// We try to handle these with integer-domain shuffles where we can, but for
8526 /// blends we use the floating point domain blend instructions.
8527 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8528 const X86Subtarget *Subtarget,
8529 SelectionDAG &DAG) {
8531 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8532 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8533 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8534 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8535 ArrayRef<int> Mask = SVOp->getMask();
8536 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8538 // Whenever we can lower this as a zext, that instruction is strictly faster
8539 // than any alternative. It also allows us to fold memory operands into the
8540 // shuffle in many cases.
8541 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8542 Mask, Subtarget, DAG))
8546 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8548 if (NumV2Elements == 0) {
8549 // Check for being able to broadcast a single element.
8550 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8551 Mask, Subtarget, DAG))
8554 // Straight shuffle of a single input vector. For everything from SSE2
8555 // onward this has a single fast instruction with no scary immediates.
8556 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8557 // but we aren't actually going to use the UNPCK instruction because doing
8558 // so prevents folding a load into this instruction or making a copy.
8559 const int UnpackLoMask[] = {0, 0, 1, 1};
8560 const int UnpackHiMask[] = {2, 2, 3, 3};
8561 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8562 Mask = UnpackLoMask;
8563 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8564 Mask = UnpackHiMask;
8566 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8567 getV4X86ShuffleImm8ForMask(Mask, DAG));
8570 // Try to use byte shift instructions.
8571 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8572 DL, MVT::v4i32, V1, V2, Mask, DAG))
8575 // There are special ways we can lower some single-element blends.
8576 if (NumV2Elements == 1)
8577 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8578 Mask, Subtarget, DAG))
8581 // Use dedicated unpack instructions for masks that match their pattern.
8582 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8583 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8584 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8585 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8587 if (Subtarget->hasSSE41())
8588 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8592 // Try to use byte rotation instructions.
8593 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8594 if (Subtarget->hasSSSE3())
8595 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8596 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8599 // We implement this with SHUFPS because it can blend from two vectors.
8600 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8601 // up the inputs, bypassing domain shift penalties that we would encur if we
8602 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8604 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8605 DAG.getVectorShuffle(
8607 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8608 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8611 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8612 /// shuffle lowering, and the most complex part.
8614 /// The lowering strategy is to try to form pairs of input lanes which are
8615 /// targeted at the same half of the final vector, and then use a dword shuffle
8616 /// to place them onto the right half, and finally unpack the paired lanes into
8617 /// their final position.
8619 /// The exact breakdown of how to form these dword pairs and align them on the
8620 /// correct sides is really tricky. See the comments within the function for
8621 /// more of the details.
8622 static SDValue lowerV8I16SingleInputVectorShuffle(
8623 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8624 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8625 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8626 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8627 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8629 SmallVector<int, 4> LoInputs;
8630 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8631 [](int M) { return M >= 0; });
8632 std::sort(LoInputs.begin(), LoInputs.end());
8633 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8634 SmallVector<int, 4> HiInputs;
8635 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8636 [](int M) { return M >= 0; });
8637 std::sort(HiInputs.begin(), HiInputs.end());
8638 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8640 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8641 int NumHToL = LoInputs.size() - NumLToL;
8643 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8644 int NumHToH = HiInputs.size() - NumLToH;
8645 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8646 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8647 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8648 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8650 // Check for being able to broadcast a single element.
8651 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8652 Mask, Subtarget, DAG))
8655 // Try to use byte shift instructions.
8656 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8657 DL, MVT::v8i16, V, V, Mask, DAG))
8660 // Use dedicated unpack instructions for masks that match their pattern.
8661 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8662 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8663 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8664 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8666 // Try to use byte rotation instructions.
8667 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8668 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8671 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8672 // such inputs we can swap two of the dwords across the half mark and end up
8673 // with <=2 inputs to each half in each half. Once there, we can fall through
8674 // to the generic code below. For example:
8676 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8677 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8679 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8680 // and an existing 2-into-2 on the other half. In this case we may have to
8681 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8682 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8683 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8684 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8685 // half than the one we target for fixing) will be fixed when we re-enter this
8686 // path. We will also combine away any sequence of PSHUFD instructions that
8687 // result into a single instruction. Here is an example of the tricky case:
8689 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8690 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8692 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8694 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8695 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8697 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8698 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8700 // The result is fine to be handled by the generic logic.
8701 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8702 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8703 int AOffset, int BOffset) {
8704 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8705 "Must call this with A having 3 or 1 inputs from the A half.");
8706 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8707 "Must call this with B having 1 or 3 inputs from the B half.");
8708 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8709 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8711 // Compute the index of dword with only one word among the three inputs in
8712 // a half by taking the sum of the half with three inputs and subtracting
8713 // the sum of the actual three inputs. The difference is the remaining
8716 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8717 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8718 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8719 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8720 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8721 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8722 int TripleNonInputIdx =
8723 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8724 TripleDWord = TripleNonInputIdx / 2;
8726 // We use xor with one to compute the adjacent DWord to whichever one the
8728 OneInputDWord = (OneInput / 2) ^ 1;
8730 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8731 // and BToA inputs. If there is also such a problem with the BToB and AToB
8732 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8733 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8734 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8735 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8736 // Compute how many inputs will be flipped by swapping these DWords. We
8738 // to balance this to ensure we don't form a 3-1 shuffle in the other
8740 int NumFlippedAToBInputs =
8741 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8742 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8743 int NumFlippedBToBInputs =
8744 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8745 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8746 if ((NumFlippedAToBInputs == 1 &&
8747 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8748 (NumFlippedBToBInputs == 1 &&
8749 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8750 // We choose whether to fix the A half or B half based on whether that
8751 // half has zero flipped inputs. At zero, we may not be able to fix it
8752 // with that half. We also bias towards fixing the B half because that
8753 // will more commonly be the high half, and we have to bias one way.
8754 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8755 ArrayRef<int> Inputs) {
8756 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8757 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8758 PinnedIdx ^ 1) != Inputs.end();
8759 // Determine whether the free index is in the flipped dword or the
8760 // unflipped dword based on where the pinned index is. We use this bit
8761 // in an xor to conditionally select the adjacent dword.
8762 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8763 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8764 FixFreeIdx) != Inputs.end();
8765 if (IsFixIdxInput == IsFixFreeIdxInput)
8767 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8768 FixFreeIdx) != Inputs.end();
8769 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8770 "We need to be changing the number of flipped inputs!");
8771 int PSHUFHalfMask[] = {0, 1, 2, 3};
8772 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8773 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8775 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8778 if (M != -1 && M == FixIdx)
8780 else if (M != -1 && M == FixFreeIdx)
8783 if (NumFlippedBToBInputs != 0) {
8785 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8786 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8788 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8790 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8791 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8796 int PSHUFDMask[] = {0, 1, 2, 3};
8797 PSHUFDMask[ADWord] = BDWord;
8798 PSHUFDMask[BDWord] = ADWord;
8799 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8800 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8801 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8802 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8804 // Adjust the mask to match the new locations of A and B.
8806 if (M != -1 && M/2 == ADWord)
8807 M = 2 * BDWord + M % 2;
8808 else if (M != -1 && M/2 == BDWord)
8809 M = 2 * ADWord + M % 2;
8811 // Recurse back into this routine to re-compute state now that this isn't
8812 // a 3 and 1 problem.
8813 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8816 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8817 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8818 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8819 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8821 // At this point there are at most two inputs to the low and high halves from
8822 // each half. That means the inputs can always be grouped into dwords and
8823 // those dwords can then be moved to the correct half with a dword shuffle.
8824 // We use at most one low and one high word shuffle to collect these paired
8825 // inputs into dwords, and finally a dword shuffle to place them.
8826 int PSHUFLMask[4] = {-1, -1, -1, -1};
8827 int PSHUFHMask[4] = {-1, -1, -1, -1};
8828 int PSHUFDMask[4] = {-1, -1, -1, -1};
8830 // First fix the masks for all the inputs that are staying in their
8831 // original halves. This will then dictate the targets of the cross-half
8833 auto fixInPlaceInputs =
8834 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8835 MutableArrayRef<int> SourceHalfMask,
8836 MutableArrayRef<int> HalfMask, int HalfOffset) {
8837 if (InPlaceInputs.empty())
8839 if (InPlaceInputs.size() == 1) {
8840 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8841 InPlaceInputs[0] - HalfOffset;
8842 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8845 if (IncomingInputs.empty()) {
8846 // Just fix all of the in place inputs.
8847 for (int Input : InPlaceInputs) {
8848 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8849 PSHUFDMask[Input / 2] = Input / 2;
8854 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8855 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8856 InPlaceInputs[0] - HalfOffset;
8857 // Put the second input next to the first so that they are packed into
8858 // a dword. We find the adjacent index by toggling the low bit.
8859 int AdjIndex = InPlaceInputs[0] ^ 1;
8860 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8861 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8862 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8864 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8865 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8867 // Now gather the cross-half inputs and place them into a free dword of
8868 // their target half.
8869 // FIXME: This operation could almost certainly be simplified dramatically to
8870 // look more like the 3-1 fixing operation.
8871 auto moveInputsToRightHalf = [&PSHUFDMask](
8872 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8873 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8874 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8876 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8877 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8879 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8881 int LowWord = Word & ~1;
8882 int HighWord = Word | 1;
8883 return isWordClobbered(SourceHalfMask, LowWord) ||
8884 isWordClobbered(SourceHalfMask, HighWord);
8887 if (IncomingInputs.empty())
8890 if (ExistingInputs.empty()) {
8891 // Map any dwords with inputs from them into the right half.
8892 for (int Input : IncomingInputs) {
8893 // If the source half mask maps over the inputs, turn those into
8894 // swaps and use the swapped lane.
8895 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8896 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8897 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8898 Input - SourceOffset;
8899 // We have to swap the uses in our half mask in one sweep.
8900 for (int &M : HalfMask)
8901 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8903 else if (M == Input)
8904 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8906 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8907 Input - SourceOffset &&
8908 "Previous placement doesn't match!");
8910 // Note that this correctly re-maps both when we do a swap and when
8911 // we observe the other side of the swap above. We rely on that to
8912 // avoid swapping the members of the input list directly.
8913 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8916 // Map the input's dword into the correct half.
8917 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8918 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8920 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8922 "Previous placement doesn't match!");
8925 // And just directly shift any other-half mask elements to be same-half
8926 // as we will have mirrored the dword containing the element into the
8927 // same position within that half.
8928 for (int &M : HalfMask)
8929 if (M >= SourceOffset && M < SourceOffset + 4) {
8930 M = M - SourceOffset + DestOffset;
8931 assert(M >= 0 && "This should never wrap below zero!");
8936 // Ensure we have the input in a viable dword of its current half. This
8937 // is particularly tricky because the original position may be clobbered
8938 // by inputs being moved and *staying* in that half.
8939 if (IncomingInputs.size() == 1) {
8940 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8941 int InputFixed = std::find(std::begin(SourceHalfMask),
8942 std::end(SourceHalfMask), -1) -
8943 std::begin(SourceHalfMask) + SourceOffset;
8944 SourceHalfMask[InputFixed - SourceOffset] =
8945 IncomingInputs[0] - SourceOffset;
8946 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8948 IncomingInputs[0] = InputFixed;
8950 } else if (IncomingInputs.size() == 2) {
8951 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8952 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8953 // We have two non-adjacent or clobbered inputs we need to extract from
8954 // the source half. To do this, we need to map them into some adjacent
8955 // dword slot in the source mask.
8956 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8957 IncomingInputs[1] - SourceOffset};
8959 // If there is a free slot in the source half mask adjacent to one of
8960 // the inputs, place the other input in it. We use (Index XOR 1) to
8961 // compute an adjacent index.
8962 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8963 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8964 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8965 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8966 InputsFixed[1] = InputsFixed[0] ^ 1;
8967 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8968 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8969 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8970 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8971 InputsFixed[0] = InputsFixed[1] ^ 1;
8972 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8973 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8974 // The two inputs are in the same DWord but it is clobbered and the
8975 // adjacent DWord isn't used at all. Move both inputs to the free
8977 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8978 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8979 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8980 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8982 // The only way we hit this point is if there is no clobbering
8983 // (because there are no off-half inputs to this half) and there is no
8984 // free slot adjacent to one of the inputs. In this case, we have to
8985 // swap an input with a non-input.
8986 for (int i = 0; i < 4; ++i)
8987 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8988 "We can't handle any clobbers here!");
8989 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8990 "Cannot have adjacent inputs here!");
8992 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8993 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8995 // We also have to update the final source mask in this case because
8996 // it may need to undo the above swap.
8997 for (int &M : FinalSourceHalfMask)
8998 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8999 M = InputsFixed[1] + SourceOffset;
9000 else if (M == InputsFixed[1] + SourceOffset)
9001 M = (InputsFixed[0] ^ 1) + SourceOffset;
9003 InputsFixed[1] = InputsFixed[0] ^ 1;
9006 // Point everything at the fixed inputs.
9007 for (int &M : HalfMask)
9008 if (M == IncomingInputs[0])
9009 M = InputsFixed[0] + SourceOffset;
9010 else if (M == IncomingInputs[1])
9011 M = InputsFixed[1] + SourceOffset;
9013 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9014 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9017 llvm_unreachable("Unhandled input size!");
9020 // Now hoist the DWord down to the right half.
9021 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9022 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9023 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9024 for (int &M : HalfMask)
9025 for (int Input : IncomingInputs)
9027 M = FreeDWord * 2 + Input % 2;
9029 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9030 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9031 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9032 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9034 // Now enact all the shuffles we've computed to move the inputs into their
9036 if (!isNoopShuffleMask(PSHUFLMask))
9037 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9038 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9039 if (!isNoopShuffleMask(PSHUFHMask))
9040 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9041 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9042 if (!isNoopShuffleMask(PSHUFDMask))
9043 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9044 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9045 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9046 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9048 // At this point, each half should contain all its inputs, and we can then
9049 // just shuffle them into their final position.
9050 assert(std::count_if(LoMask.begin(), LoMask.end(),
9051 [](int M) { return M >= 4; }) == 0 &&
9052 "Failed to lift all the high half inputs to the low mask!");
9053 assert(std::count_if(HiMask.begin(), HiMask.end(),
9054 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9055 "Failed to lift all the low half inputs to the high mask!");
9057 // Do a half shuffle for the low mask.
9058 if (!isNoopShuffleMask(LoMask))
9059 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9060 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9062 // Do a half shuffle with the high mask after shifting its values down.
9063 for (int &M : HiMask)
9066 if (!isNoopShuffleMask(HiMask))
9067 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9068 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9073 /// \brief Detect whether the mask pattern should be lowered through
9076 /// This essentially tests whether viewing the mask as an interleaving of two
9077 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9078 /// lowering it through interleaving is a significantly better strategy.
9079 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9080 int NumEvenInputs[2] = {0, 0};
9081 int NumOddInputs[2] = {0, 0};
9082 int NumLoInputs[2] = {0, 0};
9083 int NumHiInputs[2] = {0, 0};
9084 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9088 int InputIdx = Mask[i] >= Size;
9091 ++NumLoInputs[InputIdx];
9093 ++NumHiInputs[InputIdx];
9096 ++NumEvenInputs[InputIdx];
9098 ++NumOddInputs[InputIdx];
9101 // The minimum number of cross-input results for both the interleaved and
9102 // split cases. If interleaving results in fewer cross-input results, return
9104 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9105 NumEvenInputs[0] + NumOddInputs[1]);
9106 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9107 NumLoInputs[0] + NumHiInputs[1]);
9108 return InterleavedCrosses < SplitCrosses;
9111 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9113 /// This strategy only works when the inputs from each vector fit into a single
9114 /// half of that vector, and generally there are not so many inputs as to leave
9115 /// the in-place shuffles required highly constrained (and thus expensive). It
9116 /// shifts all the inputs into a single side of both input vectors and then
9117 /// uses an unpack to interleave these inputs in a single vector. At that
9118 /// point, we will fall back on the generic single input shuffle lowering.
9119 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9121 MutableArrayRef<int> Mask,
9122 const X86Subtarget *Subtarget,
9123 SelectionDAG &DAG) {
9124 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9125 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9126 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9127 for (int i = 0; i < 8; ++i)
9128 if (Mask[i] >= 0 && Mask[i] < 4)
9129 LoV1Inputs.push_back(i);
9130 else if (Mask[i] >= 4 && Mask[i] < 8)
9131 HiV1Inputs.push_back(i);
9132 else if (Mask[i] >= 8 && Mask[i] < 12)
9133 LoV2Inputs.push_back(i);
9134 else if (Mask[i] >= 12)
9135 HiV2Inputs.push_back(i);
9137 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9138 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9141 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9142 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9143 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9145 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9146 HiV1Inputs.size() + HiV2Inputs.size();
9148 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9149 ArrayRef<int> HiInputs, bool MoveToLo,
9151 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9152 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9153 if (BadInputs.empty())
9156 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9157 int MoveOffset = MoveToLo ? 0 : 4;
9159 if (GoodInputs.empty()) {
9160 for (int BadInput : BadInputs) {
9161 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9162 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9165 if (GoodInputs.size() == 2) {
9166 // If the low inputs are spread across two dwords, pack them into
9168 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9169 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9170 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9171 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9173 // Otherwise pin the good inputs.
9174 for (int GoodInput : GoodInputs)
9175 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9178 if (BadInputs.size() == 2) {
9179 // If we have two bad inputs then there may be either one or two good
9180 // inputs fixed in place. Find a fixed input, and then find the *other*
9181 // two adjacent indices by using modular arithmetic.
9183 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9184 [](int M) { return M >= 0; }) -
9185 std::begin(MoveMask);
9187 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9188 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9189 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9190 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9191 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9192 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9193 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9195 assert(BadInputs.size() == 1 && "All sizes handled");
9196 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9197 std::end(MoveMask), -1) -
9198 std::begin(MoveMask);
9199 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9200 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9204 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9207 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9209 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9212 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9213 // cross-half traffic in the final shuffle.
9215 // Munge the mask to be a single-input mask after the unpack merges the
9219 M = 2 * (M % 4) + (M / 8);
9221 return DAG.getVectorShuffle(
9222 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9223 DL, MVT::v8i16, V1, V2),
9224 DAG.getUNDEF(MVT::v8i16), Mask);
9227 /// \brief Generic lowering of 8-lane i16 shuffles.
9229 /// This handles both single-input shuffles and combined shuffle/blends with
9230 /// two inputs. The single input shuffles are immediately delegated to
9231 /// a dedicated lowering routine.
9233 /// The blends are lowered in one of three fundamental ways. If there are few
9234 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9235 /// of the input is significantly cheaper when lowered as an interleaving of
9236 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9237 /// halves of the inputs separately (making them have relatively few inputs)
9238 /// and then concatenate them.
9239 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9240 const X86Subtarget *Subtarget,
9241 SelectionDAG &DAG) {
9243 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9244 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9245 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9247 ArrayRef<int> OrigMask = SVOp->getMask();
9248 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9249 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9250 MutableArrayRef<int> Mask(MaskStorage);
9252 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9254 // Whenever we can lower this as a zext, that instruction is strictly faster
9255 // than any alternative.
9256 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9257 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9260 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9261 auto isV2 = [](int M) { return M >= 8; };
9263 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9264 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9266 if (NumV2Inputs == 0)
9267 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9269 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9270 "to be V1-input shuffles.");
9272 // Try to use byte shift instructions.
9273 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9274 DL, MVT::v8i16, V1, V2, Mask, DAG))
9277 // There are special ways we can lower some single-element blends.
9278 if (NumV2Inputs == 1)
9279 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9280 Mask, Subtarget, DAG))
9283 // Use dedicated unpack instructions for masks that match their pattern.
9284 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9285 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9286 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9287 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9289 if (Subtarget->hasSSE41())
9290 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9294 // Try to use byte rotation instructions.
9295 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9296 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9299 if (NumV1Inputs + NumV2Inputs <= 4)
9300 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9302 // Check whether an interleaving lowering is likely to be more efficient.
9303 // This isn't perfect but it is a strong heuristic that tends to work well on
9304 // the kinds of shuffles that show up in practice.
9306 // FIXME: Handle 1x, 2x, and 4x interleaving.
9307 if (shouldLowerAsInterleaving(Mask)) {
9308 // FIXME: Figure out whether we should pack these into the low or high
9311 int EMask[8], OMask[8];
9312 for (int i = 0; i < 4; ++i) {
9313 EMask[i] = Mask[2*i];
9314 OMask[i] = Mask[2*i + 1];
9319 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9320 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9322 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9325 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9326 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9328 for (int i = 0; i < 4; ++i) {
9329 LoBlendMask[i] = Mask[i];
9330 HiBlendMask[i] = Mask[i + 4];
9333 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9334 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9335 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9336 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9338 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9339 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9342 /// \brief Check whether a compaction lowering can be done by dropping even
9343 /// elements and compute how many times even elements must be dropped.
9345 /// This handles shuffles which take every Nth element where N is a power of
9346 /// two. Example shuffle masks:
9348 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9349 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9350 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9351 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9352 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9353 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9355 /// Any of these lanes can of course be undef.
9357 /// This routine only supports N <= 3.
9358 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9361 /// \returns N above, or the number of times even elements must be dropped if
9362 /// there is such a number. Otherwise returns zero.
9363 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9364 // Figure out whether we're looping over two inputs or just one.
9365 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9367 // The modulus for the shuffle vector entries is based on whether this is
9368 // a single input or not.
9369 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9370 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9371 "We should only be called with masks with a power-of-2 size!");
9373 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9375 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9376 // and 2^3 simultaneously. This is because we may have ambiguity with
9377 // partially undef inputs.
9378 bool ViableForN[3] = {true, true, true};
9380 for (int i = 0, e = Mask.size(); i < e; ++i) {
9381 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9386 bool IsAnyViable = false;
9387 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9388 if (ViableForN[j]) {
9391 // The shuffle mask must be equal to (i * 2^N) % M.
9392 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9395 ViableForN[j] = false;
9397 // Early exit if we exhaust the possible powers of two.
9402 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9406 // Return 0 as there is no viable power of two.
9410 /// \brief Generic lowering of v16i8 shuffles.
9412 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9413 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9414 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9415 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9417 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9418 const X86Subtarget *Subtarget,
9419 SelectionDAG &DAG) {
9421 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9422 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9423 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9424 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9425 ArrayRef<int> OrigMask = SVOp->getMask();
9426 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9428 // Try to use byte shift instructions.
9429 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9430 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9433 // Try to use byte rotation instructions.
9434 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9435 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9438 // Try to use a zext lowering.
9439 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9440 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9443 int MaskStorage[16] = {
9444 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9445 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9446 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9447 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9448 MutableArrayRef<int> Mask(MaskStorage);
9449 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9450 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9453 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9455 // For single-input shuffles, there are some nicer lowering tricks we can use.
9456 if (NumV2Elements == 0) {
9457 // Check for being able to broadcast a single element.
9458 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9459 Mask, Subtarget, DAG))
9462 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9463 // Notably, this handles splat and partial-splat shuffles more efficiently.
9464 // However, it only makes sense if the pre-duplication shuffle simplifies
9465 // things significantly. Currently, this means we need to be able to
9466 // express the pre-duplication shuffle as an i16 shuffle.
9468 // FIXME: We should check for other patterns which can be widened into an
9469 // i16 shuffle as well.
9470 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9471 for (int i = 0; i < 16; i += 2)
9472 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9477 auto tryToWidenViaDuplication = [&]() -> SDValue {
9478 if (!canWidenViaDuplication(Mask))
9480 SmallVector<int, 4> LoInputs;
9481 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9482 [](int M) { return M >= 0 && M < 8; });
9483 std::sort(LoInputs.begin(), LoInputs.end());
9484 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9486 SmallVector<int, 4> HiInputs;
9487 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9488 [](int M) { return M >= 8; });
9489 std::sort(HiInputs.begin(), HiInputs.end());
9490 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9493 bool TargetLo = LoInputs.size() >= HiInputs.size();
9494 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9495 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9497 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9498 SmallDenseMap<int, int, 8> LaneMap;
9499 for (int I : InPlaceInputs) {
9500 PreDupI16Shuffle[I/2] = I/2;
9503 int j = TargetLo ? 0 : 4, je = j + 4;
9504 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9505 // Check if j is already a shuffle of this input. This happens when
9506 // there are two adjacent bytes after we move the low one.
9507 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9508 // If we haven't yet mapped the input, search for a slot into which
9510 while (j < je && PreDupI16Shuffle[j] != -1)
9514 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9517 // Map this input with the i16 shuffle.
9518 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9521 // Update the lane map based on the mapping we ended up with.
9522 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9525 ISD::BITCAST, DL, MVT::v16i8,
9526 DAG.getVectorShuffle(MVT::v8i16, DL,
9527 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9528 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9530 // Unpack the bytes to form the i16s that will be shuffled into place.
9531 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9532 MVT::v16i8, V1, V1);
9534 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9535 for (int i = 0; i < 16; ++i)
9536 if (Mask[i] != -1) {
9537 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9538 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9539 if (PostDupI16Shuffle[i / 2] == -1)
9540 PostDupI16Shuffle[i / 2] = MappedMask;
9542 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9543 "Conflicting entrties in the original shuffle!");
9546 ISD::BITCAST, DL, MVT::v16i8,
9547 DAG.getVectorShuffle(MVT::v8i16, DL,
9548 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9549 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9551 if (SDValue V = tryToWidenViaDuplication())
9555 // Check whether an interleaving lowering is likely to be more efficient.
9556 // This isn't perfect but it is a strong heuristic that tends to work well on
9557 // the kinds of shuffles that show up in practice.
9559 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9560 if (shouldLowerAsInterleaving(Mask)) {
9561 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9562 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9564 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9565 return (M >= 8 && M < 16) || M >= 24;
9567 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9568 -1, -1, -1, -1, -1, -1, -1, -1};
9569 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9570 -1, -1, -1, -1, -1, -1, -1, -1};
9571 bool UnpackLo = NumLoHalf >= NumHiHalf;
9572 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9573 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9574 for (int i = 0; i < 8; ++i) {
9575 TargetEMask[i] = Mask[2 * i];
9576 TargetOMask[i] = Mask[2 * i + 1];
9579 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9580 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9582 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9583 MVT::v16i8, Evens, Odds);
9586 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9587 // with PSHUFB. It is important to do this before we attempt to generate any
9588 // blends but after all of the single-input lowerings. If the single input
9589 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9590 // want to preserve that and we can DAG combine any longer sequences into
9591 // a PSHUFB in the end. But once we start blending from multiple inputs,
9592 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9593 // and there are *very* few patterns that would actually be faster than the
9594 // PSHUFB approach because of its ability to zero lanes.
9596 // FIXME: The only exceptions to the above are blends which are exact
9597 // interleavings with direct instructions supporting them. We currently don't
9598 // handle those well here.
9599 if (Subtarget->hasSSSE3()) {
9602 bool V1InUse = false;
9603 bool V2InUse = false;
9604 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9606 for (int i = 0; i < 16; ++i) {
9607 if (Mask[i] == -1) {
9608 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9610 const int ZeroMask = 0x80;
9611 int V1Idx = (Mask[i] < 16 ? Mask[i] : ZeroMask);
9612 int V2Idx = (Mask[i] < 16 ? ZeroMask : Mask[i] - 16);
9614 V1Idx = V2Idx = ZeroMask;
9615 V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
9616 V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
9617 V1InUse |= (ZeroMask != V1Idx);
9618 V2InUse |= (ZeroMask != V2Idx);
9621 assert((V1InUse || V2InUse) && "Shuffling to a zeroable vector");
9624 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9625 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9627 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9628 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9630 // If we need shuffled inputs from both, blend the two.
9631 if (V1InUse && V2InUse)
9632 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9634 return V1; // Single inputs are easy.
9636 return V2; // Single inputs are easy.
9639 // There are special ways we can lower some single-element blends.
9640 if (NumV2Elements == 1)
9641 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9642 Mask, Subtarget, DAG))
9645 // Check whether a compaction lowering can be done. This handles shuffles
9646 // which take every Nth element for some even N. See the helper function for
9649 // We special case these as they can be particularly efficiently handled with
9650 // the PACKUSB instruction on x86 and they show up in common patterns of
9651 // rearranging bytes to truncate wide elements.
9652 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9653 // NumEvenDrops is the power of two stride of the elements. Another way of
9654 // thinking about it is that we need to drop the even elements this many
9655 // times to get the original input.
9656 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9658 // First we need to zero all the dropped bytes.
9659 assert(NumEvenDrops <= 3 &&
9660 "No support for dropping even elements more than 3 times.");
9661 // We use the mask type to pick which bytes are preserved based on how many
9662 // elements are dropped.
9663 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9664 SDValue ByteClearMask =
9665 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9666 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9667 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9669 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9671 // Now pack things back together.
9672 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9673 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9674 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9675 for (int i = 1; i < NumEvenDrops; ++i) {
9676 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9677 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9683 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9684 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9685 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9686 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9688 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9689 MutableArrayRef<int> V1HalfBlendMask,
9690 MutableArrayRef<int> V2HalfBlendMask) {
9691 for (int i = 0; i < 8; ++i)
9692 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9693 V1HalfBlendMask[i] = HalfMask[i];
9695 } else if (HalfMask[i] >= 16) {
9696 V2HalfBlendMask[i] = HalfMask[i] - 16;
9697 HalfMask[i] = i + 8;
9700 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9701 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9703 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9705 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9706 MutableArrayRef<int> HiBlendMask) {
9708 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9709 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9711 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9712 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9713 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9714 [](int M) { return M >= 0 && M % 2 == 1; })) {
9715 // Use a mask to drop the high bytes.
9716 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9717 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9718 DAG.getConstant(0x00FF, MVT::v8i16));
9720 // This will be a single vector shuffle instead of a blend so nuke V2.
9721 V2 = DAG.getUNDEF(MVT::v8i16);
9723 // Squash the masks to point directly into V1.
9724 for (int &M : LoBlendMask)
9727 for (int &M : HiBlendMask)
9731 // Otherwise just unpack the low half of V into V1 and the high half into
9732 // V2 so that we can blend them as i16s.
9733 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9734 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9735 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9736 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9739 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9740 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9741 return std::make_pair(BlendedLo, BlendedHi);
9743 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9744 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9745 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9747 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9748 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9750 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9753 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9755 /// This routine breaks down the specific type of 128-bit shuffle and
9756 /// dispatches to the lowering routines accordingly.
9757 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9758 MVT VT, const X86Subtarget *Subtarget,
9759 SelectionDAG &DAG) {
9760 switch (VT.SimpleTy) {
9762 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9764 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9766 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9768 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9770 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9772 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9775 llvm_unreachable("Unimplemented!");
9779 /// \brief Helper function to test whether a shuffle mask could be
9780 /// simplified by widening the elements being shuffled.
9782 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9783 /// leaves it in an unspecified state.
9785 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9786 /// shuffle masks. The latter have the special property of a '-2' representing
9787 /// a zero-ed lane of a vector.
9788 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9789 SmallVectorImpl<int> &WidenedMask) {
9790 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9791 // If both elements are undef, its trivial.
9792 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9793 WidenedMask.push_back(SM_SentinelUndef);
9797 // Check for an undef mask and a mask value properly aligned to fit with
9798 // a pair of values. If we find such a case, use the non-undef mask's value.
9799 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9800 WidenedMask.push_back(Mask[i + 1] / 2);
9803 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9804 WidenedMask.push_back(Mask[i] / 2);
9808 // When zeroing, we need to spread the zeroing across both lanes to widen.
9809 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9810 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9811 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9812 WidenedMask.push_back(SM_SentinelZero);
9818 // Finally check if the two mask values are adjacent and aligned with
9820 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9821 WidenedMask.push_back(Mask[i] / 2);
9825 // Otherwise we can't safely widen the elements used in this shuffle.
9828 assert(WidenedMask.size() == Mask.size() / 2 &&
9829 "Incorrect size of mask after widening the elements!");
9834 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9836 /// This routine just extracts two subvectors, shuffles them independently, and
9837 /// then concatenates them back together. This should work effectively with all
9838 /// AVX vector shuffle types.
9839 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9840 SDValue V2, ArrayRef<int> Mask,
9841 SelectionDAG &DAG) {
9842 assert(VT.getSizeInBits() >= 256 &&
9843 "Only for 256-bit or wider vector shuffles!");
9844 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9845 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9847 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9848 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9850 int NumElements = VT.getVectorNumElements();
9851 int SplitNumElements = NumElements / 2;
9852 MVT ScalarVT = VT.getScalarType();
9853 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9855 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9856 DAG.getIntPtrConstant(0));
9857 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9858 DAG.getIntPtrConstant(SplitNumElements));
9859 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9860 DAG.getIntPtrConstant(0));
9861 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9862 DAG.getIntPtrConstant(SplitNumElements));
9864 // Now create two 4-way blends of these half-width vectors.
9865 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9866 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9867 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9868 for (int i = 0; i < SplitNumElements; ++i) {
9869 int M = HalfMask[i];
9870 if (M >= NumElements) {
9871 if (M >= NumElements + SplitNumElements)
9875 V2BlendMask.push_back(M - NumElements);
9876 V1BlendMask.push_back(-1);
9877 BlendMask.push_back(SplitNumElements + i);
9878 } else if (M >= 0) {
9879 if (M >= SplitNumElements)
9883 V2BlendMask.push_back(-1);
9884 V1BlendMask.push_back(M);
9885 BlendMask.push_back(i);
9887 V2BlendMask.push_back(-1);
9888 V1BlendMask.push_back(-1);
9889 BlendMask.push_back(-1);
9893 // Because the lowering happens after all combining takes place, we need to
9894 // manually combine these blend masks as much as possible so that we create
9895 // a minimal number of high-level vector shuffle nodes.
9897 // First try just blending the halves of V1 or V2.
9898 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9899 return DAG.getUNDEF(SplitVT);
9900 if (!UseLoV2 && !UseHiV2)
9901 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9902 if (!UseLoV1 && !UseHiV1)
9903 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9905 SDValue V1Blend, V2Blend;
9906 if (UseLoV1 && UseHiV1) {
9908 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9910 // We only use half of V1 so map the usage down into the final blend mask.
9911 V1Blend = UseLoV1 ? LoV1 : HiV1;
9912 for (int i = 0; i < SplitNumElements; ++i)
9913 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9914 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9916 if (UseLoV2 && UseHiV2) {
9918 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9920 // We only use half of V2 so map the usage down into the final blend mask.
9921 V2Blend = UseLoV2 ? LoV2 : HiV2;
9922 for (int i = 0; i < SplitNumElements; ++i)
9923 if (BlendMask[i] >= SplitNumElements)
9924 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9926 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9928 SDValue Lo = HalfBlend(LoMask);
9929 SDValue Hi = HalfBlend(HiMask);
9930 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9933 /// \brief Either split a vector in halves or decompose the shuffles and the
9936 /// This is provided as a good fallback for many lowerings of non-single-input
9937 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9938 /// between splitting the shuffle into 128-bit components and stitching those
9939 /// back together vs. extracting the single-input shuffles and blending those
9941 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9942 SDValue V2, ArrayRef<int> Mask,
9943 SelectionDAG &DAG) {
9944 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9945 "lower single-input shuffles as it "
9946 "could then recurse on itself.");
9947 int Size = Mask.size();
9949 // If this can be modeled as a broadcast of two elements followed by a blend,
9950 // prefer that lowering. This is especially important because broadcasts can
9951 // often fold with memory operands.
9952 auto DoBothBroadcast = [&] {
9953 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9956 if (V2BroadcastIdx == -1)
9957 V2BroadcastIdx = M - Size;
9958 else if (M - Size != V2BroadcastIdx)
9960 } else if (M >= 0) {
9961 if (V1BroadcastIdx == -1)
9963 else if (M != V1BroadcastIdx)
9968 if (DoBothBroadcast())
9969 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9972 // If the inputs all stem from a single 128-bit lane of each input, then we
9973 // split them rather than blending because the split will decompose to
9974 // unusually few instructions.
9975 int LaneCount = VT.getSizeInBits() / 128;
9976 int LaneSize = Size / LaneCount;
9977 SmallBitVector LaneInputs[2];
9978 LaneInputs[0].resize(LaneCount, false);
9979 LaneInputs[1].resize(LaneCount, false);
9980 for (int i = 0; i < Size; ++i)
9982 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9983 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9984 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9986 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9987 // that the decomposed single-input shuffles don't end up here.
9988 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9991 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9992 /// a permutation and blend of those lanes.
9994 /// This essentially blends the out-of-lane inputs to each lane into the lane
9995 /// from a permuted copy of the vector. This lowering strategy results in four
9996 /// instructions in the worst case for a single-input cross lane shuffle which
9997 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9998 /// of. Special cases for each particular shuffle pattern should be handled
9999 /// prior to trying this lowering.
10000 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10001 SDValue V1, SDValue V2,
10002 ArrayRef<int> Mask,
10003 SelectionDAG &DAG) {
10004 // FIXME: This should probably be generalized for 512-bit vectors as well.
10005 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
10006 int LaneSize = Mask.size() / 2;
10008 // If there are only inputs from one 128-bit lane, splitting will in fact be
10009 // less expensive. The flags track wether the given lane contains an element
10010 // that crosses to another lane.
10011 bool LaneCrossing[2] = {false, false};
10012 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10013 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10014 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10015 if (!LaneCrossing[0] || !LaneCrossing[1])
10016 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10018 if (isSingleInputShuffleMask(Mask)) {
10019 SmallVector<int, 32> FlippedBlendMask;
10020 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10021 FlippedBlendMask.push_back(
10022 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10024 : Mask[i] % LaneSize +
10025 (i / LaneSize) * LaneSize + Size));
10027 // Flip the vector, and blend the results which should now be in-lane. The
10028 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10029 // 5 for the high source. The value 3 selects the high half of source 2 and
10030 // the value 2 selects the low half of source 2. We only use source 2 to
10031 // allow folding it into a memory operand.
10032 unsigned PERMMask = 3 | 2 << 4;
10033 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10034 V1, DAG.getConstant(PERMMask, MVT::i8));
10035 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10038 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10039 // will be handled by the above logic and a blend of the results, much like
10040 // other patterns in AVX.
10041 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10044 /// \brief Handle lowering 2-lane 128-bit shuffles.
10045 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10046 SDValue V2, ArrayRef<int> Mask,
10047 const X86Subtarget *Subtarget,
10048 SelectionDAG &DAG) {
10049 // Blends are faster and handle all the non-lane-crossing cases.
10050 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10054 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10055 VT.getVectorNumElements() / 2);
10056 // Check for patterns which can be matched with a single insert of a 128-bit
10058 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10059 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10060 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10061 DAG.getIntPtrConstant(0));
10062 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10063 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10064 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10066 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10067 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10068 DAG.getIntPtrConstant(0));
10069 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10070 DAG.getIntPtrConstant(2));
10071 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10074 // Otherwise form a 128-bit permutation.
10075 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10076 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10077 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10078 DAG.getConstant(PermMask, MVT::i8));
10081 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10082 /// shuffling each lane.
10084 /// This will only succeed when the result of fixing the 128-bit lanes results
10085 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10086 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10087 /// the lane crosses early and then use simpler shuffles within each lane.
10089 /// FIXME: It might be worthwhile at some point to support this without
10090 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10091 /// in x86 only floating point has interesting non-repeating shuffles, and even
10092 /// those are still *marginally* more expensive.
10093 static SDValue lowerVectorShuffleByMerging128BitLanes(
10094 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10095 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10096 assert(!isSingleInputShuffleMask(Mask) &&
10097 "This is only useful with multiple inputs.");
10099 int Size = Mask.size();
10100 int LaneSize = 128 / VT.getScalarSizeInBits();
10101 int NumLanes = Size / LaneSize;
10102 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10104 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10105 // check whether the in-128-bit lane shuffles share a repeating pattern.
10106 SmallVector<int, 4> Lanes;
10107 Lanes.resize(NumLanes, -1);
10108 SmallVector<int, 4> InLaneMask;
10109 InLaneMask.resize(LaneSize, -1);
10110 for (int i = 0; i < Size; ++i) {
10114 int j = i / LaneSize;
10116 if (Lanes[j] < 0) {
10117 // First entry we've seen for this lane.
10118 Lanes[j] = Mask[i] / LaneSize;
10119 } else if (Lanes[j] != Mask[i] / LaneSize) {
10120 // This doesn't match the lane selected previously!
10124 // Check that within each lane we have a consistent shuffle mask.
10125 int k = i % LaneSize;
10126 if (InLaneMask[k] < 0) {
10127 InLaneMask[k] = Mask[i] % LaneSize;
10128 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10129 // This doesn't fit a repeating in-lane mask.
10134 // First shuffle the lanes into place.
10135 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10136 VT.getSizeInBits() / 64);
10137 SmallVector<int, 8> LaneMask;
10138 LaneMask.resize(NumLanes * 2, -1);
10139 for (int i = 0; i < NumLanes; ++i)
10140 if (Lanes[i] >= 0) {
10141 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10142 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10145 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10146 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10147 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10149 // Cast it back to the type we actually want.
10150 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10152 // Now do a simple shuffle that isn't lane crossing.
10153 SmallVector<int, 8> NewMask;
10154 NewMask.resize(Size, -1);
10155 for (int i = 0; i < Size; ++i)
10157 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10158 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10159 "Must not introduce lane crosses at this point!");
10161 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10164 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10167 /// This returns true if the elements from a particular input are already in the
10168 /// slot required by the given mask and require no permutation.
10169 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10170 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10171 int Size = Mask.size();
10172 for (int i = 0; i < Size; ++i)
10173 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10179 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10181 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10182 /// isn't available.
10183 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10184 const X86Subtarget *Subtarget,
10185 SelectionDAG &DAG) {
10187 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10188 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10189 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10190 ArrayRef<int> Mask = SVOp->getMask();
10191 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10193 SmallVector<int, 4> WidenedMask;
10194 if (canWidenShuffleElements(Mask, WidenedMask))
10195 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10198 if (isSingleInputShuffleMask(Mask)) {
10199 // Check for being able to broadcast a single element.
10200 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10201 Mask, Subtarget, DAG))
10204 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10205 // Non-half-crossing single input shuffles can be lowerid with an
10206 // interleaved permutation.
10207 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10208 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10209 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10210 DAG.getConstant(VPERMILPMask, MVT::i8));
10213 // With AVX2 we have direct support for this permutation.
10214 if (Subtarget->hasAVX2())
10215 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10216 getV4X86ShuffleImm8ForMask(Mask, DAG));
10218 // Otherwise, fall back.
10219 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10223 // X86 has dedicated unpack instructions that can handle specific blend
10224 // operations: UNPCKH and UNPCKL.
10225 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10226 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10227 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10228 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10230 // If we have a single input to the zero element, insert that into V1 if we
10231 // can do so cheaply.
10232 int NumV2Elements =
10233 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10234 if (NumV2Elements == 1 && Mask[0] >= 4)
10235 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10236 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10239 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10243 // Check if the blend happens to exactly fit that of SHUFPD.
10244 if ((Mask[0] == -1 || Mask[0] < 2) &&
10245 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10246 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10247 (Mask[3] == -1 || Mask[3] >= 6)) {
10248 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10249 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10250 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10251 DAG.getConstant(SHUFPDMask, MVT::i8));
10253 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10254 (Mask[1] == -1 || Mask[1] < 2) &&
10255 (Mask[2] == -1 || Mask[2] >= 6) &&
10256 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10257 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10258 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10259 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10260 DAG.getConstant(SHUFPDMask, MVT::i8));
10263 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10264 // shuffle. However, if we have AVX2 and either inputs are already in place,
10265 // we will be able to shuffle even across lanes the other input in a single
10266 // instruction so skip this pattern.
10267 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10268 isShuffleMaskInputInPlace(1, Mask))))
10269 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10270 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10273 // If we have AVX2 then we always want to lower with a blend because an v4 we
10274 // can fully permute the elements.
10275 if (Subtarget->hasAVX2())
10276 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10279 // Otherwise fall back on generic lowering.
10280 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10283 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10285 /// This routine is only called when we have AVX2 and thus a reasonable
10286 /// instruction set for v4i64 shuffling..
10287 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10288 const X86Subtarget *Subtarget,
10289 SelectionDAG &DAG) {
10291 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10292 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10293 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10294 ArrayRef<int> Mask = SVOp->getMask();
10295 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10296 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10298 SmallVector<int, 4> WidenedMask;
10299 if (canWidenShuffleElements(Mask, WidenedMask))
10300 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10303 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10307 // Check for being able to broadcast a single element.
10308 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10309 Mask, Subtarget, DAG))
10312 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10313 // use lower latency instructions that will operate on both 128-bit lanes.
10314 SmallVector<int, 2> RepeatedMask;
10315 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10316 if (isSingleInputShuffleMask(Mask)) {
10317 int PSHUFDMask[] = {-1, -1, -1, -1};
10318 for (int i = 0; i < 2; ++i)
10319 if (RepeatedMask[i] >= 0) {
10320 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10321 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10323 return DAG.getNode(
10324 ISD::BITCAST, DL, MVT::v4i64,
10325 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10326 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10327 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10330 // Use dedicated unpack instructions for masks that match their pattern.
10331 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10332 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10333 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10334 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10337 // AVX2 provides a direct instruction for permuting a single input across
10339 if (isSingleInputShuffleMask(Mask))
10340 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10341 getV4X86ShuffleImm8ForMask(Mask, DAG));
10343 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10344 // shuffle. However, if we have AVX2 and either inputs are already in place,
10345 // we will be able to shuffle even across lanes the other input in a single
10346 // instruction so skip this pattern.
10347 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10348 isShuffleMaskInputInPlace(1, Mask))))
10349 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10350 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10353 // Otherwise fall back on generic blend lowering.
10354 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10358 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10360 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10361 /// isn't available.
10362 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10363 const X86Subtarget *Subtarget,
10364 SelectionDAG &DAG) {
10366 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10367 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10369 ArrayRef<int> Mask = SVOp->getMask();
10370 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10372 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10376 // Check for being able to broadcast a single element.
10377 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10378 Mask, Subtarget, DAG))
10381 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10382 // options to efficiently lower the shuffle.
10383 SmallVector<int, 4> RepeatedMask;
10384 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10385 assert(RepeatedMask.size() == 4 &&
10386 "Repeated masks must be half the mask width!");
10387 if (isSingleInputShuffleMask(Mask))
10388 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10389 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10391 // Use dedicated unpack instructions for masks that match their pattern.
10392 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10393 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10394 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10395 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10397 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10398 // have already handled any direct blends. We also need to squash the
10399 // repeated mask into a simulated v4f32 mask.
10400 for (int i = 0; i < 4; ++i)
10401 if (RepeatedMask[i] >= 8)
10402 RepeatedMask[i] -= 4;
10403 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10406 // If we have a single input shuffle with different shuffle patterns in the
10407 // two 128-bit lanes use the variable mask to VPERMILPS.
10408 if (isSingleInputShuffleMask(Mask)) {
10409 SDValue VPermMask[8];
10410 for (int i = 0; i < 8; ++i)
10411 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10412 : DAG.getConstant(Mask[i], MVT::i32);
10413 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10414 return DAG.getNode(
10415 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10416 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10418 if (Subtarget->hasAVX2())
10419 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10420 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10421 DAG.getNode(ISD::BUILD_VECTOR, DL,
10422 MVT::v8i32, VPermMask)),
10425 // Otherwise, fall back.
10426 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10430 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10432 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10433 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10436 // If we have AVX2 then we always want to lower with a blend because at v8 we
10437 // can fully permute the elements.
10438 if (Subtarget->hasAVX2())
10439 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10442 // Otherwise fall back on generic lowering.
10443 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10446 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10448 /// This routine is only called when we have AVX2 and thus a reasonable
10449 /// instruction set for v8i32 shuffling..
10450 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10451 const X86Subtarget *Subtarget,
10452 SelectionDAG &DAG) {
10454 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10455 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10456 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10457 ArrayRef<int> Mask = SVOp->getMask();
10458 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10459 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10461 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10465 // Check for being able to broadcast a single element.
10466 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10467 Mask, Subtarget, DAG))
10470 // If the shuffle mask is repeated in each 128-bit lane we can use more
10471 // efficient instructions that mirror the shuffles across the two 128-bit
10473 SmallVector<int, 4> RepeatedMask;
10474 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10475 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10476 if (isSingleInputShuffleMask(Mask))
10477 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10478 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10480 // Use dedicated unpack instructions for masks that match their pattern.
10481 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10482 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10483 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10484 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10487 // If the shuffle patterns aren't repeated but it is a single input, directly
10488 // generate a cross-lane VPERMD instruction.
10489 if (isSingleInputShuffleMask(Mask)) {
10490 SDValue VPermMask[8];
10491 for (int i = 0; i < 8; ++i)
10492 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10493 : DAG.getConstant(Mask[i], MVT::i32);
10494 return DAG.getNode(
10495 X86ISD::VPERMV, DL, MVT::v8i32,
10496 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10499 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10501 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10502 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10505 // Otherwise fall back on generic blend lowering.
10506 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10510 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10512 /// This routine is only called when we have AVX2 and thus a reasonable
10513 /// instruction set for v16i16 shuffling..
10514 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10515 const X86Subtarget *Subtarget,
10516 SelectionDAG &DAG) {
10518 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10519 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10520 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10521 ArrayRef<int> Mask = SVOp->getMask();
10522 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10523 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10525 // Check for being able to broadcast a single element.
10526 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10527 Mask, Subtarget, DAG))
10530 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10534 // Use dedicated unpack instructions for masks that match their pattern.
10535 if (isShuffleEquivalent(Mask,
10536 // First 128-bit lane:
10537 0, 16, 1, 17, 2, 18, 3, 19,
10538 // Second 128-bit lane:
10539 8, 24, 9, 25, 10, 26, 11, 27))
10540 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10541 if (isShuffleEquivalent(Mask,
10542 // First 128-bit lane:
10543 4, 20, 5, 21, 6, 22, 7, 23,
10544 // Second 128-bit lane:
10545 12, 28, 13, 29, 14, 30, 15, 31))
10546 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10548 if (isSingleInputShuffleMask(Mask)) {
10549 // There are no generalized cross-lane shuffle operations available on i16
10551 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10552 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10555 SDValue PSHUFBMask[32];
10556 for (int i = 0; i < 16; ++i) {
10557 if (Mask[i] == -1) {
10558 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10562 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10563 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10564 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10565 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10567 return DAG.getNode(
10568 ISD::BITCAST, DL, MVT::v16i16,
10570 X86ISD::PSHUFB, DL, MVT::v32i8,
10571 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10572 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10575 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10577 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10578 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10581 // Otherwise fall back on generic lowering.
10582 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10585 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10587 /// This routine is only called when we have AVX2 and thus a reasonable
10588 /// instruction set for v32i8 shuffling..
10589 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10590 const X86Subtarget *Subtarget,
10591 SelectionDAG &DAG) {
10593 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10594 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10595 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10596 ArrayRef<int> Mask = SVOp->getMask();
10597 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10598 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10600 // Check for being able to broadcast a single element.
10601 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10602 Mask, Subtarget, DAG))
10605 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10609 // Use dedicated unpack instructions for masks that match their pattern.
10610 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10612 if (isShuffleEquivalent(
10614 // First 128-bit lane:
10615 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10616 // Second 128-bit lane:
10617 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10618 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10619 if (isShuffleEquivalent(
10621 // First 128-bit lane:
10622 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10623 // Second 128-bit lane:
10624 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10625 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10627 if (isSingleInputShuffleMask(Mask)) {
10628 // There are no generalized cross-lane shuffle operations available on i8
10630 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10631 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10634 SDValue PSHUFBMask[32];
10635 for (int i = 0; i < 32; ++i)
10638 ? DAG.getUNDEF(MVT::i8)
10639 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10641 return DAG.getNode(
10642 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10643 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10646 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10648 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10649 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10652 // Otherwise fall back on generic lowering.
10653 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10656 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10658 /// This routine either breaks down the specific type of a 256-bit x86 vector
10659 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10660 /// together based on the available instructions.
10661 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10662 MVT VT, const X86Subtarget *Subtarget,
10663 SelectionDAG &DAG) {
10665 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10666 ArrayRef<int> Mask = SVOp->getMask();
10668 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10669 // check for those subtargets here and avoid much of the subtarget querying in
10670 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10671 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10672 // floating point types there eventually, just immediately cast everything to
10673 // a float and operate entirely in that domain.
10674 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10675 int ElementBits = VT.getScalarSizeInBits();
10676 if (ElementBits < 32)
10677 // No floating point type available, decompose into 128-bit vectors.
10678 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10680 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10681 VT.getVectorNumElements());
10682 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10683 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10684 return DAG.getNode(ISD::BITCAST, DL, VT,
10685 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10688 switch (VT.SimpleTy) {
10690 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10692 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10694 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10696 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10698 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10700 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10703 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10707 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10708 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10709 const X86Subtarget *Subtarget,
10710 SelectionDAG &DAG) {
10712 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10713 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10714 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10715 ArrayRef<int> Mask = SVOp->getMask();
10716 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10718 // FIXME: Implement direct support for this type!
10719 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10722 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10723 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10724 const X86Subtarget *Subtarget,
10725 SelectionDAG &DAG) {
10727 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10728 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10729 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10730 ArrayRef<int> Mask = SVOp->getMask();
10731 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10733 // FIXME: Implement direct support for this type!
10734 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10737 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10738 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10739 const X86Subtarget *Subtarget,
10740 SelectionDAG &DAG) {
10742 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10743 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10745 ArrayRef<int> Mask = SVOp->getMask();
10746 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10748 // FIXME: Implement direct support for this type!
10749 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10752 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10753 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10754 const X86Subtarget *Subtarget,
10755 SelectionDAG &DAG) {
10757 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10758 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10759 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10760 ArrayRef<int> Mask = SVOp->getMask();
10761 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10763 // FIXME: Implement direct support for this type!
10764 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10767 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10768 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10769 const X86Subtarget *Subtarget,
10770 SelectionDAG &DAG) {
10772 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10773 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10774 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10775 ArrayRef<int> Mask = SVOp->getMask();
10776 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10777 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10779 // FIXME: Implement direct support for this type!
10780 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10783 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10784 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10785 const X86Subtarget *Subtarget,
10786 SelectionDAG &DAG) {
10788 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10789 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10790 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10791 ArrayRef<int> Mask = SVOp->getMask();
10792 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10793 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10795 // FIXME: Implement direct support for this type!
10796 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10799 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10801 /// This routine either breaks down the specific type of a 512-bit x86 vector
10802 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10803 /// together based on the available instructions.
10804 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10805 MVT VT, const X86Subtarget *Subtarget,
10806 SelectionDAG &DAG) {
10808 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10809 ArrayRef<int> Mask = SVOp->getMask();
10810 assert(Subtarget->hasAVX512() &&
10811 "Cannot lower 512-bit vectors w/ basic ISA!");
10813 // Check for being able to broadcast a single element.
10814 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10815 Mask, Subtarget, DAG))
10818 // Dispatch to each element type for lowering. If we don't have supprot for
10819 // specific element type shuffles at 512 bits, immediately split them and
10820 // lower them. Each lowering routine of a given type is allowed to assume that
10821 // the requisite ISA extensions for that element type are available.
10822 switch (VT.SimpleTy) {
10824 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10826 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10828 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10830 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10832 if (Subtarget->hasBWI())
10833 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10836 if (Subtarget->hasBWI())
10837 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10841 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10844 // Otherwise fall back on splitting.
10845 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10848 /// \brief Top-level lowering for x86 vector shuffles.
10850 /// This handles decomposition, canonicalization, and lowering of all x86
10851 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10852 /// above in helper routines. The canonicalization attempts to widen shuffles
10853 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10854 /// s.t. only one of the two inputs needs to be tested, etc.
10855 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10856 SelectionDAG &DAG) {
10857 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10858 ArrayRef<int> Mask = SVOp->getMask();
10859 SDValue V1 = Op.getOperand(0);
10860 SDValue V2 = Op.getOperand(1);
10861 MVT VT = Op.getSimpleValueType();
10862 int NumElements = VT.getVectorNumElements();
10865 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10867 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10868 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10869 if (V1IsUndef && V2IsUndef)
10870 return DAG.getUNDEF(VT);
10872 // When we create a shuffle node we put the UNDEF node to second operand,
10873 // but in some cases the first operand may be transformed to UNDEF.
10874 // In this case we should just commute the node.
10876 return DAG.getCommutedVectorShuffle(*SVOp);
10878 // Check for non-undef masks pointing at an undef vector and make the masks
10879 // undef as well. This makes it easier to match the shuffle based solely on
10883 if (M >= NumElements) {
10884 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10885 for (int &M : NewMask)
10886 if (M >= NumElements)
10888 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10891 // Try to collapse shuffles into using a vector type with fewer elements but
10892 // wider element types. We cap this to not form integers or floating point
10893 // elements wider than 64 bits, but it might be interesting to form i128
10894 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10895 SmallVector<int, 16> WidenedMask;
10896 if (VT.getScalarSizeInBits() < 64 &&
10897 canWidenShuffleElements(Mask, WidenedMask)) {
10898 MVT NewEltVT = VT.isFloatingPoint()
10899 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10900 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10901 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10902 // Make sure that the new vector type is legal. For example, v2f64 isn't
10904 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10905 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10906 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10907 return DAG.getNode(ISD::BITCAST, dl, VT,
10908 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10912 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10913 for (int M : SVOp->getMask())
10915 ++NumUndefElements;
10916 else if (M < NumElements)
10921 // Commute the shuffle as needed such that more elements come from V1 than
10922 // V2. This allows us to match the shuffle pattern strictly on how many
10923 // elements come from V1 without handling the symmetric cases.
10924 if (NumV2Elements > NumV1Elements)
10925 return DAG.getCommutedVectorShuffle(*SVOp);
10927 // When the number of V1 and V2 elements are the same, try to minimize the
10928 // number of uses of V2 in the low half of the vector. When that is tied,
10929 // ensure that the sum of indices for V1 is equal to or lower than the sum
10930 // indices for V2. When those are equal, try to ensure that the number of odd
10931 // indices for V1 is lower than the number of odd indices for V2.
10932 if (NumV1Elements == NumV2Elements) {
10933 int LowV1Elements = 0, LowV2Elements = 0;
10934 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10935 if (M >= NumElements)
10939 if (LowV2Elements > LowV1Elements) {
10940 return DAG.getCommutedVectorShuffle(*SVOp);
10941 } else if (LowV2Elements == LowV1Elements) {
10942 int SumV1Indices = 0, SumV2Indices = 0;
10943 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10944 if (SVOp->getMask()[i] >= NumElements)
10946 else if (SVOp->getMask()[i] >= 0)
10948 if (SumV2Indices < SumV1Indices) {
10949 return DAG.getCommutedVectorShuffle(*SVOp);
10950 } else if (SumV2Indices == SumV1Indices) {
10951 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10952 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10953 if (SVOp->getMask()[i] >= NumElements)
10954 NumV2OddIndices += i % 2;
10955 else if (SVOp->getMask()[i] >= 0)
10956 NumV1OddIndices += i % 2;
10957 if (NumV2OddIndices < NumV1OddIndices)
10958 return DAG.getCommutedVectorShuffle(*SVOp);
10963 // For each vector width, delegate to a specialized lowering routine.
10964 if (VT.getSizeInBits() == 128)
10965 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10967 if (VT.getSizeInBits() == 256)
10968 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10970 // Force AVX-512 vectors to be scalarized for now.
10971 // FIXME: Implement AVX-512 support!
10972 if (VT.getSizeInBits() == 512)
10973 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10975 llvm_unreachable("Unimplemented!");
10979 //===----------------------------------------------------------------------===//
10980 // Legacy vector shuffle lowering
10982 // This code is the legacy code handling vector shuffles until the above
10983 // replaces its functionality and performance.
10984 //===----------------------------------------------------------------------===//
10986 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10987 bool hasInt256, unsigned *MaskOut = nullptr) {
10988 MVT EltVT = VT.getVectorElementType();
10990 // There is no blend with immediate in AVX-512.
10991 if (VT.is512BitVector())
10994 if (!hasSSE41 || EltVT == MVT::i8)
10996 if (!hasInt256 && VT == MVT::v16i16)
10999 unsigned MaskValue = 0;
11000 unsigned NumElems = VT.getVectorNumElements();
11001 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11002 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11003 unsigned NumElemsInLane = NumElems / NumLanes;
11005 // Blend for v16i16 should be symetric for the both lanes.
11006 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11008 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
11009 int EltIdx = MaskVals[i];
11011 if ((EltIdx < 0 || EltIdx == (int)i) &&
11012 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
11015 if (((unsigned)EltIdx == (i + NumElems)) &&
11016 (SndLaneEltIdx < 0 ||
11017 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
11018 MaskValue |= (1 << i);
11024 *MaskOut = MaskValue;
11028 // Try to lower a shuffle node into a simple blend instruction.
11029 // This function assumes isBlendMask returns true for this
11030 // SuffleVectorSDNode
11031 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
11032 unsigned MaskValue,
11033 const X86Subtarget *Subtarget,
11034 SelectionDAG &DAG) {
11035 MVT VT = SVOp->getSimpleValueType(0);
11036 MVT EltVT = VT.getVectorElementType();
11037 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
11038 Subtarget->hasInt256() && "Trying to lower a "
11039 "VECTOR_SHUFFLE to a Blend but "
11040 "with the wrong mask"));
11041 SDValue V1 = SVOp->getOperand(0);
11042 SDValue V2 = SVOp->getOperand(1);
11044 unsigned NumElems = VT.getVectorNumElements();
11046 // Convert i32 vectors to floating point if it is not AVX2.
11047 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11049 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11050 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11052 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11053 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11056 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11057 DAG.getConstant(MaskValue, MVT::i32));
11058 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11061 /// In vector type \p VT, return true if the element at index \p InputIdx
11062 /// falls on a different 128-bit lane than \p OutputIdx.
11063 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11064 unsigned OutputIdx) {
11065 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11066 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11069 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11070 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11071 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11072 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11074 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11075 SelectionDAG &DAG) {
11076 MVT VT = V1.getSimpleValueType();
11077 assert(VT.is128BitVector() || VT.is256BitVector());
11079 MVT EltVT = VT.getVectorElementType();
11080 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11081 unsigned NumElts = VT.getVectorNumElements();
11083 SmallVector<SDValue, 32> PshufbMask;
11084 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11085 int InputIdx = MaskVals[OutputIdx];
11086 unsigned InputByteIdx;
11088 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11089 InputByteIdx = 0x80;
11091 // Cross lane is not allowed.
11092 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11094 InputByteIdx = InputIdx * EltSizeInBytes;
11095 // Index is an byte offset within the 128-bit lane.
11096 InputByteIdx &= 0xf;
11099 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11100 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11101 if (InputByteIdx != 0x80)
11106 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11108 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11109 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11110 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11113 // v8i16 shuffles - Prefer shuffles in the following order:
11114 // 1. [all] pshuflw, pshufhw, optional move
11115 // 2. [ssse3] 1 x pshufb
11116 // 3. [ssse3] 2 x pshufb + 1 x por
11117 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11119 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11120 SelectionDAG &DAG) {
11121 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11122 SDValue V1 = SVOp->getOperand(0);
11123 SDValue V2 = SVOp->getOperand(1);
11125 SmallVector<int, 8> MaskVals;
11127 // Determine if more than 1 of the words in each of the low and high quadwords
11128 // of the result come from the same quadword of one of the two inputs. Undef
11129 // mask values count as coming from any quadword, for better codegen.
11131 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11132 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11133 unsigned LoQuad[] = { 0, 0, 0, 0 };
11134 unsigned HiQuad[] = { 0, 0, 0, 0 };
11135 // Indices of quads used.
11136 std::bitset<4> InputQuads;
11137 for (unsigned i = 0; i < 8; ++i) {
11138 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11139 int EltIdx = SVOp->getMaskElt(i);
11140 MaskVals.push_back(EltIdx);
11148 ++Quad[EltIdx / 4];
11149 InputQuads.set(EltIdx / 4);
11152 int BestLoQuad = -1;
11153 unsigned MaxQuad = 1;
11154 for (unsigned i = 0; i < 4; ++i) {
11155 if (LoQuad[i] > MaxQuad) {
11157 MaxQuad = LoQuad[i];
11161 int BestHiQuad = -1;
11163 for (unsigned i = 0; i < 4; ++i) {
11164 if (HiQuad[i] > MaxQuad) {
11166 MaxQuad = HiQuad[i];
11170 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11171 // of the two input vectors, shuffle them into one input vector so only a
11172 // single pshufb instruction is necessary. If there are more than 2 input
11173 // quads, disable the next transformation since it does not help SSSE3.
11174 bool V1Used = InputQuads[0] || InputQuads[1];
11175 bool V2Used = InputQuads[2] || InputQuads[3];
11176 if (Subtarget->hasSSSE3()) {
11177 if (InputQuads.count() == 2 && V1Used && V2Used) {
11178 BestLoQuad = InputQuads[0] ? 0 : 1;
11179 BestHiQuad = InputQuads[2] ? 2 : 3;
11181 if (InputQuads.count() > 2) {
11187 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11188 // the shuffle mask. If a quad is scored as -1, that means that it contains
11189 // words from all 4 input quadwords.
11191 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11193 BestLoQuad < 0 ? 0 : BestLoQuad,
11194 BestHiQuad < 0 ? 1 : BestHiQuad
11196 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11197 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11198 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11199 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11201 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11202 // source words for the shuffle, to aid later transformations.
11203 bool AllWordsInNewV = true;
11204 bool InOrder[2] = { true, true };
11205 for (unsigned i = 0; i != 8; ++i) {
11206 int idx = MaskVals[i];
11208 InOrder[i/4] = false;
11209 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11211 AllWordsInNewV = false;
11215 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11216 if (AllWordsInNewV) {
11217 for (int i = 0; i != 8; ++i) {
11218 int idx = MaskVals[i];
11221 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11222 if ((idx != i) && idx < 4)
11224 if ((idx != i) && idx > 3)
11233 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11234 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11235 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11236 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11237 unsigned TargetMask = 0;
11238 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11239 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11240 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11241 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11242 getShufflePSHUFLWImmediate(SVOp);
11243 V1 = NewV.getOperand(0);
11244 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11248 // Promote splats to a larger type which usually leads to more efficient code.
11249 // FIXME: Is this true if pshufb is available?
11250 if (SVOp->isSplat())
11251 return PromoteSplat(SVOp, DAG);
11253 // If we have SSSE3, and all words of the result are from 1 input vector,
11254 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11255 // is present, fall back to case 4.
11256 if (Subtarget->hasSSSE3()) {
11257 SmallVector<SDValue,16> pshufbMask;
11259 // If we have elements from both input vectors, set the high bit of the
11260 // shuffle mask element to zero out elements that come from V2 in the V1
11261 // mask, and elements that come from V1 in the V2 mask, so that the two
11262 // results can be OR'd together.
11263 bool TwoInputs = V1Used && V2Used;
11264 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11266 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11268 // Calculate the shuffle mask for the second input, shuffle it, and
11269 // OR it with the first shuffled input.
11270 CommuteVectorShuffleMask(MaskVals, 8);
11271 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11272 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11273 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11276 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11277 // and update MaskVals with new element order.
11278 std::bitset<8> InOrder;
11279 if (BestLoQuad >= 0) {
11280 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11281 for (int i = 0; i != 4; ++i) {
11282 int idx = MaskVals[i];
11285 } else if ((idx / 4) == BestLoQuad) {
11286 MaskV[i] = idx & 3;
11290 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11293 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11294 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11295 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11296 NewV.getOperand(0),
11297 getShufflePSHUFLWImmediate(SVOp), DAG);
11301 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11302 // and update MaskVals with the new element order.
11303 if (BestHiQuad >= 0) {
11304 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11305 for (unsigned i = 4; i != 8; ++i) {
11306 int idx = MaskVals[i];
11309 } else if ((idx / 4) == BestHiQuad) {
11310 MaskV[i] = (idx & 3) + 4;
11314 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11317 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11318 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11319 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11320 NewV.getOperand(0),
11321 getShufflePSHUFHWImmediate(SVOp), DAG);
11325 // In case BestHi & BestLo were both -1, which means each quadword has a word
11326 // from each of the four input quadwords, calculate the InOrder bitvector now
11327 // before falling through to the insert/extract cleanup.
11328 if (BestLoQuad == -1 && BestHiQuad == -1) {
11330 for (int i = 0; i != 8; ++i)
11331 if (MaskVals[i] < 0 || MaskVals[i] == i)
11335 // The other elements are put in the right place using pextrw and pinsrw.
11336 for (unsigned i = 0; i != 8; ++i) {
11339 int EltIdx = MaskVals[i];
11342 SDValue ExtOp = (EltIdx < 8) ?
11343 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11344 DAG.getIntPtrConstant(EltIdx)) :
11345 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11346 DAG.getIntPtrConstant(EltIdx - 8));
11347 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11348 DAG.getIntPtrConstant(i));
11353 /// \brief v16i16 shuffles
11355 /// FIXME: We only support generation of a single pshufb currently. We can
11356 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11357 /// well (e.g 2 x pshufb + 1 x por).
11359 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11360 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11361 SDValue V1 = SVOp->getOperand(0);
11362 SDValue V2 = SVOp->getOperand(1);
11365 if (V2.getOpcode() != ISD::UNDEF)
11368 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11369 return getPSHUFB(MaskVals, V1, dl, DAG);
11372 // v16i8 shuffles - Prefer shuffles in the following order:
11373 // 1. [ssse3] 1 x pshufb
11374 // 2. [ssse3] 2 x pshufb + 1 x por
11375 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11376 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11377 const X86Subtarget* Subtarget,
11378 SelectionDAG &DAG) {
11379 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11380 SDValue V1 = SVOp->getOperand(0);
11381 SDValue V2 = SVOp->getOperand(1);
11383 ArrayRef<int> MaskVals = SVOp->getMask();
11385 // Promote splats to a larger type which usually leads to more efficient code.
11386 // FIXME: Is this true if pshufb is available?
11387 if (SVOp->isSplat())
11388 return PromoteSplat(SVOp, DAG);
11390 // If we have SSSE3, case 1 is generated when all result bytes come from
11391 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11392 // present, fall back to case 3.
11394 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11395 if (Subtarget->hasSSSE3()) {
11396 SmallVector<SDValue,16> pshufbMask;
11398 // If all result elements are from one input vector, then only translate
11399 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11401 // Otherwise, we have elements from both input vectors, and must zero out
11402 // elements that come from V2 in the first mask, and V1 in the second mask
11403 // so that we can OR them together.
11404 for (unsigned i = 0; i != 16; ++i) {
11405 int EltIdx = MaskVals[i];
11406 if (EltIdx < 0 || EltIdx >= 16)
11408 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11410 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11411 DAG.getNode(ISD::BUILD_VECTOR, dl,
11412 MVT::v16i8, pshufbMask));
11414 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11415 // the 2nd operand if it's undefined or zero.
11416 if (V2.getOpcode() == ISD::UNDEF ||
11417 ISD::isBuildVectorAllZeros(V2.getNode()))
11420 // Calculate the shuffle mask for the second input, shuffle it, and
11421 // OR it with the first shuffled input.
11422 pshufbMask.clear();
11423 for (unsigned i = 0; i != 16; ++i) {
11424 int EltIdx = MaskVals[i];
11425 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11426 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11428 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11429 DAG.getNode(ISD::BUILD_VECTOR, dl,
11430 MVT::v16i8, pshufbMask));
11431 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11434 // No SSSE3 - Calculate in place words and then fix all out of place words
11435 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11436 // the 16 different words that comprise the two doublequadword input vectors.
11437 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11438 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11440 for (int i = 0; i != 8; ++i) {
11441 int Elt0 = MaskVals[i*2];
11442 int Elt1 = MaskVals[i*2+1];
11444 // This word of the result is all undef, skip it.
11445 if (Elt0 < 0 && Elt1 < 0)
11448 // This word of the result is already in the correct place, skip it.
11449 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11452 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11453 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11456 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11457 // using a single extract together, load it and store it.
11458 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11459 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11460 DAG.getIntPtrConstant(Elt1 / 2));
11461 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11462 DAG.getIntPtrConstant(i));
11466 // If Elt1 is defined, extract it from the appropriate source. If the
11467 // source byte is not also odd, shift the extracted word left 8 bits
11468 // otherwise clear the bottom 8 bits if we need to do an or.
11470 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11471 DAG.getIntPtrConstant(Elt1 / 2));
11472 if ((Elt1 & 1) == 0)
11473 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11475 TLI.getShiftAmountTy(InsElt.getValueType())));
11476 else if (Elt0 >= 0)
11477 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11478 DAG.getConstant(0xFF00, MVT::i16));
11480 // If Elt0 is defined, extract it from the appropriate source. If the
11481 // source byte is not also even, shift the extracted word right 8 bits. If
11482 // Elt1 was also defined, OR the extracted values together before
11483 // inserting them in the result.
11485 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11486 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11487 if ((Elt0 & 1) != 0)
11488 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11490 TLI.getShiftAmountTy(InsElt0.getValueType())));
11491 else if (Elt1 >= 0)
11492 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11493 DAG.getConstant(0x00FF, MVT::i16));
11494 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11497 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11498 DAG.getIntPtrConstant(i));
11500 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11503 // v32i8 shuffles - Translate to VPSHUFB if possible.
11505 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11506 const X86Subtarget *Subtarget,
11507 SelectionDAG &DAG) {
11508 MVT VT = SVOp->getSimpleValueType(0);
11509 SDValue V1 = SVOp->getOperand(0);
11510 SDValue V2 = SVOp->getOperand(1);
11512 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11514 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11515 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11516 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11518 // VPSHUFB may be generated if
11519 // (1) one of input vector is undefined or zeroinitializer.
11520 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11521 // And (2) the mask indexes don't cross the 128-bit lane.
11522 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11523 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11526 if (V1IsAllZero && !V2IsAllZero) {
11527 CommuteVectorShuffleMask(MaskVals, 32);
11530 return getPSHUFB(MaskVals, V1, dl, DAG);
11533 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11534 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11535 /// done when every pair / quad of shuffle mask elements point to elements in
11536 /// the right sequence. e.g.
11537 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11539 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11540 SelectionDAG &DAG) {
11541 MVT VT = SVOp->getSimpleValueType(0);
11543 unsigned NumElems = VT.getVectorNumElements();
11546 switch (VT.SimpleTy) {
11547 default: llvm_unreachable("Unexpected!");
11550 return SDValue(SVOp, 0);
11551 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11552 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11553 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11554 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11555 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11556 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11559 SmallVector<int, 8> MaskVec;
11560 for (unsigned i = 0; i != NumElems; i += Scale) {
11562 for (unsigned j = 0; j != Scale; ++j) {
11563 int EltIdx = SVOp->getMaskElt(i+j);
11567 StartIdx = (EltIdx / Scale);
11568 if (EltIdx != (int)(StartIdx*Scale + j))
11571 MaskVec.push_back(StartIdx);
11574 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11575 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11576 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11579 /// getVZextMovL - Return a zero-extending vector move low node.
11581 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11582 SDValue SrcOp, SelectionDAG &DAG,
11583 const X86Subtarget *Subtarget, SDLoc dl) {
11584 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11585 LoadSDNode *LD = nullptr;
11586 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11587 LD = dyn_cast<LoadSDNode>(SrcOp);
11589 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11591 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11592 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11593 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11594 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11595 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11597 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11598 return DAG.getNode(ISD::BITCAST, dl, VT,
11599 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11600 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11602 SrcOp.getOperand(0)
11608 return DAG.getNode(ISD::BITCAST, dl, VT,
11609 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11610 DAG.getNode(ISD::BITCAST, dl,
11614 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11615 /// which could not be matched by any known target speficic shuffle
11617 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11619 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11620 if (NewOp.getNode())
11623 MVT VT = SVOp->getSimpleValueType(0);
11625 unsigned NumElems = VT.getVectorNumElements();
11626 unsigned NumLaneElems = NumElems / 2;
11629 MVT EltVT = VT.getVectorElementType();
11630 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11633 SmallVector<int, 16> Mask;
11634 for (unsigned l = 0; l < 2; ++l) {
11635 // Build a shuffle mask for the output, discovering on the fly which
11636 // input vectors to use as shuffle operands (recorded in InputUsed).
11637 // If building a suitable shuffle vector proves too hard, then bail
11638 // out with UseBuildVector set.
11639 bool UseBuildVector = false;
11640 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11641 unsigned LaneStart = l * NumLaneElems;
11642 for (unsigned i = 0; i != NumLaneElems; ++i) {
11643 // The mask element. This indexes into the input.
11644 int Idx = SVOp->getMaskElt(i+LaneStart);
11646 // the mask element does not index into any input vector.
11647 Mask.push_back(-1);
11651 // The input vector this mask element indexes into.
11652 int Input = Idx / NumLaneElems;
11654 // Turn the index into an offset from the start of the input vector.
11655 Idx -= Input * NumLaneElems;
11657 // Find or create a shuffle vector operand to hold this input.
11659 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11660 if (InputUsed[OpNo] == Input)
11661 // This input vector is already an operand.
11663 if (InputUsed[OpNo] < 0) {
11664 // Create a new operand for this input vector.
11665 InputUsed[OpNo] = Input;
11670 if (OpNo >= array_lengthof(InputUsed)) {
11671 // More than two input vectors used! Give up on trying to create a
11672 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11673 UseBuildVector = true;
11677 // Add the mask index for the new shuffle vector.
11678 Mask.push_back(Idx + OpNo * NumLaneElems);
11681 if (UseBuildVector) {
11682 SmallVector<SDValue, 16> SVOps;
11683 for (unsigned i = 0; i != NumLaneElems; ++i) {
11684 // The mask element. This indexes into the input.
11685 int Idx = SVOp->getMaskElt(i+LaneStart);
11687 SVOps.push_back(DAG.getUNDEF(EltVT));
11691 // The input vector this mask element indexes into.
11692 int Input = Idx / NumElems;
11694 // Turn the index into an offset from the start of the input vector.
11695 Idx -= Input * NumElems;
11697 // Extract the vector element by hand.
11698 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11699 SVOp->getOperand(Input),
11700 DAG.getIntPtrConstant(Idx)));
11703 // Construct the output using a BUILD_VECTOR.
11704 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11705 } else if (InputUsed[0] < 0) {
11706 // No input vectors were used! The result is undefined.
11707 Output[l] = DAG.getUNDEF(NVT);
11709 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11710 (InputUsed[0] % 2) * NumLaneElems,
11712 // If only one input was used, use an undefined vector for the other.
11713 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11714 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11715 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11716 // At least one input vector was used. Create a new shuffle vector.
11717 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11723 // Concatenate the result back
11724 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11727 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11728 /// 4 elements, and match them with several different shuffle types.
11730 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11731 SDValue V1 = SVOp->getOperand(0);
11732 SDValue V2 = SVOp->getOperand(1);
11734 MVT VT = SVOp->getSimpleValueType(0);
11736 assert(VT.is128BitVector() && "Unsupported vector size");
11738 std::pair<int, int> Locs[4];
11739 int Mask1[] = { -1, -1, -1, -1 };
11740 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11742 unsigned NumHi = 0;
11743 unsigned NumLo = 0;
11744 for (unsigned i = 0; i != 4; ++i) {
11745 int Idx = PermMask[i];
11747 Locs[i] = std::make_pair(-1, -1);
11749 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11751 Locs[i] = std::make_pair(0, NumLo);
11752 Mask1[NumLo] = Idx;
11755 Locs[i] = std::make_pair(1, NumHi);
11757 Mask1[2+NumHi] = Idx;
11763 if (NumLo <= 2 && NumHi <= 2) {
11764 // If no more than two elements come from either vector. This can be
11765 // implemented with two shuffles. First shuffle gather the elements.
11766 // The second shuffle, which takes the first shuffle as both of its
11767 // vector operands, put the elements into the right order.
11768 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11770 int Mask2[] = { -1, -1, -1, -1 };
11772 for (unsigned i = 0; i != 4; ++i)
11773 if (Locs[i].first != -1) {
11774 unsigned Idx = (i < 2) ? 0 : 4;
11775 Idx += Locs[i].first * 2 + Locs[i].second;
11779 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11782 if (NumLo == 3 || NumHi == 3) {
11783 // Otherwise, we must have three elements from one vector, call it X, and
11784 // one element from the other, call it Y. First, use a shufps to build an
11785 // intermediate vector with the one element from Y and the element from X
11786 // that will be in the same half in the final destination (the indexes don't
11787 // matter). Then, use a shufps to build the final vector, taking the half
11788 // containing the element from Y from the intermediate, and the other half
11791 // Normalize it so the 3 elements come from V1.
11792 CommuteVectorShuffleMask(PermMask, 4);
11796 // Find the element from V2.
11798 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11799 int Val = PermMask[HiIndex];
11806 Mask1[0] = PermMask[HiIndex];
11808 Mask1[2] = PermMask[HiIndex^1];
11810 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11812 if (HiIndex >= 2) {
11813 Mask1[0] = PermMask[0];
11814 Mask1[1] = PermMask[1];
11815 Mask1[2] = HiIndex & 1 ? 6 : 4;
11816 Mask1[3] = HiIndex & 1 ? 4 : 6;
11817 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11820 Mask1[0] = HiIndex & 1 ? 2 : 0;
11821 Mask1[1] = HiIndex & 1 ? 0 : 2;
11822 Mask1[2] = PermMask[2];
11823 Mask1[3] = PermMask[3];
11828 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11831 // Break it into (shuffle shuffle_hi, shuffle_lo).
11832 int LoMask[] = { -1, -1, -1, -1 };
11833 int HiMask[] = { -1, -1, -1, -1 };
11835 int *MaskPtr = LoMask;
11836 unsigned MaskIdx = 0;
11837 unsigned LoIdx = 0;
11838 unsigned HiIdx = 2;
11839 for (unsigned i = 0; i != 4; ++i) {
11846 int Idx = PermMask[i];
11848 Locs[i] = std::make_pair(-1, -1);
11849 } else if (Idx < 4) {
11850 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11851 MaskPtr[LoIdx] = Idx;
11854 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11855 MaskPtr[HiIdx] = Idx;
11860 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11861 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11862 int MaskOps[] = { -1, -1, -1, -1 };
11863 for (unsigned i = 0; i != 4; ++i)
11864 if (Locs[i].first != -1)
11865 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11866 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11869 static bool MayFoldVectorLoad(SDValue V) {
11870 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11871 V = V.getOperand(0);
11873 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11874 V = V.getOperand(0);
11875 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11876 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11877 // BUILD_VECTOR (load), undef
11878 V = V.getOperand(0);
11880 return MayFoldLoad(V);
11884 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11885 MVT VT = Op.getSimpleValueType();
11887 // Canonizalize to v2f64.
11888 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11889 return DAG.getNode(ISD::BITCAST, dl, VT,
11890 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11895 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11897 SDValue V1 = Op.getOperand(0);
11898 SDValue V2 = Op.getOperand(1);
11899 MVT VT = Op.getSimpleValueType();
11901 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11903 if (HasSSE2 && VT == MVT::v2f64)
11904 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11906 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11907 return DAG.getNode(ISD::BITCAST, dl, VT,
11908 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11909 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11910 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11914 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11915 SDValue V1 = Op.getOperand(0);
11916 SDValue V2 = Op.getOperand(1);
11917 MVT VT = Op.getSimpleValueType();
11919 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11920 "unsupported shuffle type");
11922 if (V2.getOpcode() == ISD::UNDEF)
11926 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11930 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11931 SDValue V1 = Op.getOperand(0);
11932 SDValue V2 = Op.getOperand(1);
11933 MVT VT = Op.getSimpleValueType();
11934 unsigned NumElems = VT.getVectorNumElements();
11936 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11937 // operand of these instructions is only memory, so check if there's a
11938 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11940 bool CanFoldLoad = false;
11942 // Trivial case, when V2 comes from a load.
11943 if (MayFoldVectorLoad(V2))
11944 CanFoldLoad = true;
11946 // When V1 is a load, it can be folded later into a store in isel, example:
11947 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11949 // (MOVLPSmr addr:$src1, VR128:$src2)
11950 // So, recognize this potential and also use MOVLPS or MOVLPD
11951 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11952 CanFoldLoad = true;
11954 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11956 if (HasSSE2 && NumElems == 2)
11957 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11960 // If we don't care about the second element, proceed to use movss.
11961 if (SVOp->getMaskElt(1) != -1)
11962 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11965 // movl and movlp will both match v2i64, but v2i64 is never matched by
11966 // movl earlier because we make it strict to avoid messing with the movlp load
11967 // folding logic (see the code above getMOVLP call). Match it here then,
11968 // this is horrible, but will stay like this until we move all shuffle
11969 // matching to x86 specific nodes. Note that for the 1st condition all
11970 // types are matched with movsd.
11972 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11973 // as to remove this logic from here, as much as possible
11974 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11975 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11976 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11979 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11981 // Invert the operand order and use SHUFPS to match it.
11982 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11983 getShuffleSHUFImmediate(SVOp), DAG);
11986 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11987 SelectionDAG &DAG) {
11989 MVT VT = Load->getSimpleValueType(0);
11990 MVT EVT = VT.getVectorElementType();
11991 SDValue Addr = Load->getOperand(1);
11992 SDValue NewAddr = DAG.getNode(
11993 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11994 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11997 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11998 DAG.getMachineFunction().getMachineMemOperand(
11999 Load->getMemOperand(), 0, EVT.getStoreSize()));
12003 // It is only safe to call this function if isINSERTPSMask is true for
12004 // this shufflevector mask.
12005 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
12006 SelectionDAG &DAG) {
12007 // Generate an insertps instruction when inserting an f32 from memory onto a
12008 // v4f32 or when copying a member from one v4f32 to another.
12009 // We also use it for transferring i32 from one register to another,
12010 // since it simply copies the same bits.
12011 // If we're transferring an i32 from memory to a specific element in a
12012 // register, we output a generic DAG that will match the PINSRD
12014 MVT VT = SVOp->getSimpleValueType(0);
12015 MVT EVT = VT.getVectorElementType();
12016 SDValue V1 = SVOp->getOperand(0);
12017 SDValue V2 = SVOp->getOperand(1);
12018 auto Mask = SVOp->getMask();
12019 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
12020 "unsupported vector type for insertps/pinsrd");
12022 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
12023 auto FromV2Predicate = [](const int &i) { return i >= 4; };
12024 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
12028 unsigned DestIndex;
12032 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
12035 // If we have 1 element from each vector, we have to check if we're
12036 // changing V1's element's place. If so, we're done. Otherwise, we
12037 // should assume we're changing V2's element's place and behave
12039 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12040 assert(DestIndex <= INT32_MAX && "truncated destination index");
12041 if (FromV1 == FromV2 &&
12042 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12046 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12049 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12050 "More than one element from V1 and from V2, or no elements from one "
12051 "of the vectors. This case should not have returned true from "
12056 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12059 // Get an index into the source vector in the range [0,4) (the mask is
12060 // in the range [0,8) because it can address V1 and V2)
12061 unsigned SrcIndex = Mask[DestIndex] % 4;
12062 if (MayFoldLoad(From)) {
12063 // Trivial case, when From comes from a load and is only used by the
12064 // shuffle. Make it use insertps from the vector that we need from that
12067 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12068 if (!NewLoad.getNode())
12071 if (EVT == MVT::f32) {
12072 // Create this as a scalar to vector to match the instruction pattern.
12073 SDValue LoadScalarToVector =
12074 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12075 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12076 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12078 } else { // EVT == MVT::i32
12079 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12080 // instruction, to match the PINSRD instruction, which loads an i32 to a
12081 // certain vector element.
12082 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12083 DAG.getConstant(DestIndex, MVT::i32));
12087 // Vector-element-to-vector
12088 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12089 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12092 // Reduce a vector shuffle to zext.
12093 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12094 SelectionDAG &DAG) {
12095 // PMOVZX is only available from SSE41.
12096 if (!Subtarget->hasSSE41())
12099 MVT VT = Op.getSimpleValueType();
12101 // Only AVX2 support 256-bit vector integer extending.
12102 if (!Subtarget->hasInt256() && VT.is256BitVector())
12105 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12107 SDValue V1 = Op.getOperand(0);
12108 SDValue V2 = Op.getOperand(1);
12109 unsigned NumElems = VT.getVectorNumElements();
12111 // Extending is an unary operation and the element type of the source vector
12112 // won't be equal to or larger than i64.
12113 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12114 VT.getVectorElementType() == MVT::i64)
12117 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12118 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12119 while ((1U << Shift) < NumElems) {
12120 if (SVOp->getMaskElt(1U << Shift) == 1)
12123 // The maximal ratio is 8, i.e. from i8 to i64.
12128 // Check the shuffle mask.
12129 unsigned Mask = (1U << Shift) - 1;
12130 for (unsigned i = 0; i != NumElems; ++i) {
12131 int EltIdx = SVOp->getMaskElt(i);
12132 if ((i & Mask) != 0 && EltIdx != -1)
12134 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12138 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12139 MVT NeVT = MVT::getIntegerVT(NBits);
12140 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12142 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12145 return DAG.getNode(ISD::BITCAST, DL, VT,
12146 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12149 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12150 SelectionDAG &DAG) {
12151 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12152 MVT VT = Op.getSimpleValueType();
12154 SDValue V1 = Op.getOperand(0);
12155 SDValue V2 = Op.getOperand(1);
12157 if (isZeroShuffle(SVOp))
12158 return getZeroVector(VT, Subtarget, DAG, dl);
12160 // Handle splat operations
12161 if (SVOp->isSplat()) {
12162 // Use vbroadcast whenever the splat comes from a foldable load
12163 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12164 if (Broadcast.getNode())
12168 // Check integer expanding shuffles.
12169 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12170 if (NewOp.getNode())
12173 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12175 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12176 VT == MVT::v32i8) {
12177 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12178 if (NewOp.getNode())
12179 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12180 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12181 // FIXME: Figure out a cleaner way to do this.
12182 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12183 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12184 if (NewOp.getNode()) {
12185 MVT NewVT = NewOp.getSimpleValueType();
12186 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12187 NewVT, true, false))
12188 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12191 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12192 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12193 if (NewOp.getNode()) {
12194 MVT NewVT = NewOp.getSimpleValueType();
12195 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12196 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12205 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12206 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12207 SDValue V1 = Op.getOperand(0);
12208 SDValue V2 = Op.getOperand(1);
12209 MVT VT = Op.getSimpleValueType();
12211 unsigned NumElems = VT.getVectorNumElements();
12212 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12213 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12214 bool V1IsSplat = false;
12215 bool V2IsSplat = false;
12216 bool HasSSE2 = Subtarget->hasSSE2();
12217 bool HasFp256 = Subtarget->hasFp256();
12218 bool HasInt256 = Subtarget->hasInt256();
12219 MachineFunction &MF = DAG.getMachineFunction();
12220 bool OptForSize = MF.getFunction()->getAttributes().
12221 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12223 // Check if we should use the experimental vector shuffle lowering. If so,
12224 // delegate completely to that code path.
12225 if (ExperimentalVectorShuffleLowering)
12226 return lowerVectorShuffle(Op, Subtarget, DAG);
12228 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12230 if (V1IsUndef && V2IsUndef)
12231 return DAG.getUNDEF(VT);
12233 // When we create a shuffle node we put the UNDEF node to second operand,
12234 // but in some cases the first operand may be transformed to UNDEF.
12235 // In this case we should just commute the node.
12237 return DAG.getCommutedVectorShuffle(*SVOp);
12239 // Vector shuffle lowering takes 3 steps:
12241 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12242 // narrowing and commutation of operands should be handled.
12243 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12245 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12246 // so the shuffle can be broken into other shuffles and the legalizer can
12247 // try the lowering again.
12249 // The general idea is that no vector_shuffle operation should be left to
12250 // be matched during isel, all of them must be converted to a target specific
12253 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12254 // narrowing and commutation of operands should be handled. The actual code
12255 // doesn't include all of those, work in progress...
12256 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12257 if (NewOp.getNode())
12260 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12262 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12263 // unpckh_undef). Only use pshufd if speed is more important than size.
12264 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12265 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12266 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12267 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12269 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12270 V2IsUndef && MayFoldVectorLoad(V1))
12271 return getMOVDDup(Op, dl, V1, DAG);
12273 if (isMOVHLPS_v_undef_Mask(M, VT))
12274 return getMOVHighToLow(Op, dl, DAG);
12276 // Use to match splats
12277 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12278 (VT == MVT::v2f64 || VT == MVT::v2i64))
12279 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12281 if (isPSHUFDMask(M, VT)) {
12282 // The actual implementation will match the mask in the if above and then
12283 // during isel it can match several different instructions, not only pshufd
12284 // as its name says, sad but true, emulate the behavior for now...
12285 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12286 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12288 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12290 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12291 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12293 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12294 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12297 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12301 if (isPALIGNRMask(M, VT, Subtarget))
12302 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12303 getShufflePALIGNRImmediate(SVOp),
12306 if (isVALIGNMask(M, VT, Subtarget))
12307 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12308 getShuffleVALIGNImmediate(SVOp),
12311 // Check if this can be converted into a logical shift.
12312 bool isLeft = false;
12313 unsigned ShAmt = 0;
12315 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12316 if (isShift && ShVal.hasOneUse()) {
12317 // If the shifted value has multiple uses, it may be cheaper to use
12318 // v_set0 + movlhps or movhlps, etc.
12319 MVT EltVT = VT.getVectorElementType();
12320 ShAmt *= EltVT.getSizeInBits();
12321 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12324 if (isMOVLMask(M, VT)) {
12325 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12326 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12327 if (!isMOVLPMask(M, VT)) {
12328 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12329 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12331 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12332 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12336 // FIXME: fold these into legal mask.
12337 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12338 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12340 if (isMOVHLPSMask(M, VT))
12341 return getMOVHighToLow(Op, dl, DAG);
12343 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12344 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12346 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12347 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12349 if (isMOVLPMask(M, VT))
12350 return getMOVLP(Op, dl, DAG, HasSSE2);
12352 if (ShouldXformToMOVHLPS(M, VT) ||
12353 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12354 return DAG.getCommutedVectorShuffle(*SVOp);
12357 // No better options. Use a vshldq / vsrldq.
12358 MVT EltVT = VT.getVectorElementType();
12359 ShAmt *= EltVT.getSizeInBits();
12360 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12363 bool Commuted = false;
12364 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12365 // 1,1,1,1 -> v8i16 though.
12366 BitVector UndefElements;
12367 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12368 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12370 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12371 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12374 // Canonicalize the splat or undef, if present, to be on the RHS.
12375 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12376 CommuteVectorShuffleMask(M, NumElems);
12378 std::swap(V1IsSplat, V2IsSplat);
12382 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12383 // Shuffling low element of v1 into undef, just return v1.
12386 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12387 // the instruction selector will not match, so get a canonical MOVL with
12388 // swapped operands to undo the commute.
12389 return getMOVL(DAG, dl, VT, V2, V1);
12392 if (isUNPCKLMask(M, VT, HasInt256))
12393 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12395 if (isUNPCKHMask(M, VT, HasInt256))
12396 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12399 // Normalize mask so all entries that point to V2 points to its first
12400 // element then try to match unpck{h|l} again. If match, return a
12401 // new vector_shuffle with the corrected mask.p
12402 SmallVector<int, 8> NewMask(M.begin(), M.end());
12403 NormalizeMask(NewMask, NumElems);
12404 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12405 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12406 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12407 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12411 // Commute is back and try unpck* again.
12412 // FIXME: this seems wrong.
12413 CommuteVectorShuffleMask(M, NumElems);
12415 std::swap(V1IsSplat, V2IsSplat);
12417 if (isUNPCKLMask(M, VT, HasInt256))
12418 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12420 if (isUNPCKHMask(M, VT, HasInt256))
12421 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12424 // Normalize the node to match x86 shuffle ops if needed
12425 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12426 return DAG.getCommutedVectorShuffle(*SVOp);
12428 // The checks below are all present in isShuffleMaskLegal, but they are
12429 // inlined here right now to enable us to directly emit target specific
12430 // nodes, and remove one by one until they don't return Op anymore.
12432 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12433 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12434 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12435 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12438 if (isPSHUFHWMask(M, VT, HasInt256))
12439 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12440 getShufflePSHUFHWImmediate(SVOp),
12443 if (isPSHUFLWMask(M, VT, HasInt256))
12444 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12445 getShufflePSHUFLWImmediate(SVOp),
12448 unsigned MaskValue;
12449 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12451 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12453 if (isSHUFPMask(M, VT))
12454 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12455 getShuffleSHUFImmediate(SVOp), DAG);
12457 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12458 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12459 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12460 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12462 //===--------------------------------------------------------------------===//
12463 // Generate target specific nodes for 128 or 256-bit shuffles only
12464 // supported in the AVX instruction set.
12467 // Handle VMOVDDUPY permutations
12468 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12469 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12471 // Handle VPERMILPS/D* permutations
12472 if (isVPERMILPMask(M, VT)) {
12473 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12474 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12475 getShuffleSHUFImmediate(SVOp), DAG);
12476 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12477 getShuffleSHUFImmediate(SVOp), DAG);
12481 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12482 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12483 Idx*(NumElems/2), DAG, dl);
12485 // Handle VPERM2F128/VPERM2I128 permutations
12486 if (isVPERM2X128Mask(M, VT, HasFp256))
12487 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12488 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12490 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12491 return getINSERTPS(SVOp, dl, DAG);
12494 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12495 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12497 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12498 VT.is512BitVector()) {
12499 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12500 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12501 SmallVector<SDValue, 16> permclMask;
12502 for (unsigned i = 0; i != NumElems; ++i) {
12503 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12506 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12508 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12509 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12510 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12511 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12512 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12515 //===--------------------------------------------------------------------===//
12516 // Since no target specific shuffle was selected for this generic one,
12517 // lower it into other known shuffles. FIXME: this isn't true yet, but
12518 // this is the plan.
12521 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12522 if (VT == MVT::v8i16) {
12523 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12524 if (NewOp.getNode())
12528 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12529 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12530 if (NewOp.getNode())
12534 if (VT == MVT::v16i8) {
12535 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12536 if (NewOp.getNode())
12540 if (VT == MVT::v32i8) {
12541 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12542 if (NewOp.getNode())
12546 // Handle all 128-bit wide vectors with 4 elements, and match them with
12547 // several different shuffle types.
12548 if (NumElems == 4 && VT.is128BitVector())
12549 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12551 // Handle general 256-bit shuffles
12552 if (VT.is256BitVector())
12553 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12558 // This function assumes its argument is a BUILD_VECTOR of constants or
12559 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12561 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12562 unsigned &MaskValue) {
12564 unsigned NumElems = BuildVector->getNumOperands();
12565 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12566 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12567 unsigned NumElemsInLane = NumElems / NumLanes;
12569 // Blend for v16i16 should be symetric for the both lanes.
12570 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12571 SDValue EltCond = BuildVector->getOperand(i);
12572 SDValue SndLaneEltCond =
12573 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12575 int Lane1Cond = -1, Lane2Cond = -1;
12576 if (isa<ConstantSDNode>(EltCond))
12577 Lane1Cond = !isZero(EltCond);
12578 if (isa<ConstantSDNode>(SndLaneEltCond))
12579 Lane2Cond = !isZero(SndLaneEltCond);
12581 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12582 // Lane1Cond != 0, means we want the first argument.
12583 // Lane1Cond == 0, means we want the second argument.
12584 // The encoding of this argument is 0 for the first argument, 1
12585 // for the second. Therefore, invert the condition.
12586 MaskValue |= !Lane1Cond << i;
12587 else if (Lane1Cond < 0)
12588 MaskValue |= !Lane2Cond << i;
12595 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12597 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12598 SelectionDAG &DAG) {
12599 SDValue Cond = Op.getOperand(0);
12600 SDValue LHS = Op.getOperand(1);
12601 SDValue RHS = Op.getOperand(2);
12603 MVT VT = Op.getSimpleValueType();
12604 MVT EltVT = VT.getVectorElementType();
12605 unsigned NumElems = VT.getVectorNumElements();
12607 // There is no blend with immediate in AVX-512.
12608 if (VT.is512BitVector())
12611 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12613 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12616 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12619 // Check the mask for BLEND and build the value.
12620 unsigned MaskValue = 0;
12621 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12624 // Convert i32 vectors to floating point if it is not AVX2.
12625 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12627 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12628 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12630 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12631 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12634 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12635 DAG.getConstant(MaskValue, MVT::i32));
12636 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12639 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12640 // A vselect where all conditions and data are constants can be optimized into
12641 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12642 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12643 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12644 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12647 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12648 if (BlendOp.getNode())
12651 // Some types for vselect were previously set to Expand, not Legal or
12652 // Custom. Return an empty SDValue so we fall-through to Expand, after
12653 // the Custom lowering phase.
12654 MVT VT = Op.getSimpleValueType();
12655 switch (VT.SimpleTy) {
12660 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12665 // We couldn't create a "Blend with immediate" node.
12666 // This node should still be legal, but we'll have to emit a blendv*
12671 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12672 MVT VT = Op.getSimpleValueType();
12675 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12678 if (VT.getSizeInBits() == 8) {
12679 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12680 Op.getOperand(0), Op.getOperand(1));
12681 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12682 DAG.getValueType(VT));
12683 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12686 if (VT.getSizeInBits() == 16) {
12687 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12688 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12690 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12691 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12692 DAG.getNode(ISD::BITCAST, dl,
12695 Op.getOperand(1)));
12696 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12697 Op.getOperand(0), Op.getOperand(1));
12698 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12699 DAG.getValueType(VT));
12700 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12703 if (VT == MVT::f32) {
12704 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12705 // the result back to FR32 register. It's only worth matching if the
12706 // result has a single use which is a store or a bitcast to i32. And in
12707 // the case of a store, it's not worth it if the index is a constant 0,
12708 // because a MOVSSmr can be used instead, which is smaller and faster.
12709 if (!Op.hasOneUse())
12711 SDNode *User = *Op.getNode()->use_begin();
12712 if ((User->getOpcode() != ISD::STORE ||
12713 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12714 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12715 (User->getOpcode() != ISD::BITCAST ||
12716 User->getValueType(0) != MVT::i32))
12718 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12719 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12722 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12725 if (VT == MVT::i32 || VT == MVT::i64) {
12726 // ExtractPS/pextrq works with constant index.
12727 if (isa<ConstantSDNode>(Op.getOperand(1)))
12733 /// Extract one bit from mask vector, like v16i1 or v8i1.
12734 /// AVX-512 feature.
12736 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12737 SDValue Vec = Op.getOperand(0);
12739 MVT VecVT = Vec.getSimpleValueType();
12740 SDValue Idx = Op.getOperand(1);
12741 MVT EltVT = Op.getSimpleValueType();
12743 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12745 // variable index can't be handled in mask registers,
12746 // extend vector to VR512
12747 if (!isa<ConstantSDNode>(Idx)) {
12748 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12749 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12750 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12751 ExtVT.getVectorElementType(), Ext, Idx);
12752 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12755 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12756 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12757 unsigned MaxSift = rc->getSize()*8 - 1;
12758 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12759 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12760 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12761 DAG.getConstant(MaxSift, MVT::i8));
12762 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12763 DAG.getIntPtrConstant(0));
12767 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12768 SelectionDAG &DAG) const {
12770 SDValue Vec = Op.getOperand(0);
12771 MVT VecVT = Vec.getSimpleValueType();
12772 SDValue Idx = Op.getOperand(1);
12774 if (Op.getSimpleValueType() == MVT::i1)
12775 return ExtractBitFromMaskVector(Op, DAG);
12777 if (!isa<ConstantSDNode>(Idx)) {
12778 if (VecVT.is512BitVector() ||
12779 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12780 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12783 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12784 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12785 MaskEltVT.getSizeInBits());
12787 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12788 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12789 getZeroVector(MaskVT, Subtarget, DAG, dl),
12790 Idx, DAG.getConstant(0, getPointerTy()));
12791 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12792 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12793 Perm, DAG.getConstant(0, getPointerTy()));
12798 // If this is a 256-bit vector result, first extract the 128-bit vector and
12799 // then extract the element from the 128-bit vector.
12800 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12802 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12803 // Get the 128-bit vector.
12804 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12805 MVT EltVT = VecVT.getVectorElementType();
12807 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12809 //if (IdxVal >= NumElems/2)
12810 // IdxVal -= NumElems/2;
12811 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12812 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12813 DAG.getConstant(IdxVal, MVT::i32));
12816 assert(VecVT.is128BitVector() && "Unexpected vector length");
12818 if (Subtarget->hasSSE41()) {
12819 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12824 MVT VT = Op.getSimpleValueType();
12825 // TODO: handle v16i8.
12826 if (VT.getSizeInBits() == 16) {
12827 SDValue Vec = Op.getOperand(0);
12828 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12830 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12831 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12832 DAG.getNode(ISD::BITCAST, dl,
12834 Op.getOperand(1)));
12835 // Transform it so it match pextrw which produces a 32-bit result.
12836 MVT EltVT = MVT::i32;
12837 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12838 Op.getOperand(0), Op.getOperand(1));
12839 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12840 DAG.getValueType(VT));
12841 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12844 if (VT.getSizeInBits() == 32) {
12845 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12849 // SHUFPS the element to the lowest double word, then movss.
12850 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12851 MVT VVT = Op.getOperand(0).getSimpleValueType();
12852 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12853 DAG.getUNDEF(VVT), Mask);
12854 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12855 DAG.getIntPtrConstant(0));
12858 if (VT.getSizeInBits() == 64) {
12859 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12860 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12861 // to match extract_elt for f64.
12862 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12866 // UNPCKHPD the element to the lowest double word, then movsd.
12867 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12868 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12869 int Mask[2] = { 1, -1 };
12870 MVT VVT = Op.getOperand(0).getSimpleValueType();
12871 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12872 DAG.getUNDEF(VVT), Mask);
12873 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12874 DAG.getIntPtrConstant(0));
12880 /// Insert one bit to mask vector, like v16i1 or v8i1.
12881 /// AVX-512 feature.
12883 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12885 SDValue Vec = Op.getOperand(0);
12886 SDValue Elt = Op.getOperand(1);
12887 SDValue Idx = Op.getOperand(2);
12888 MVT VecVT = Vec.getSimpleValueType();
12890 if (!isa<ConstantSDNode>(Idx)) {
12891 // Non constant index. Extend source and destination,
12892 // insert element and then truncate the result.
12893 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12894 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12895 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12896 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12897 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12898 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12901 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12902 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12903 if (Vec.getOpcode() == ISD::UNDEF)
12904 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12905 DAG.getConstant(IdxVal, MVT::i8));
12906 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12907 unsigned MaxSift = rc->getSize()*8 - 1;
12908 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12909 DAG.getConstant(MaxSift, MVT::i8));
12910 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12911 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12912 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12915 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12916 SelectionDAG &DAG) const {
12917 MVT VT = Op.getSimpleValueType();
12918 MVT EltVT = VT.getVectorElementType();
12920 if (EltVT == MVT::i1)
12921 return InsertBitToMaskVector(Op, DAG);
12924 SDValue N0 = Op.getOperand(0);
12925 SDValue N1 = Op.getOperand(1);
12926 SDValue N2 = Op.getOperand(2);
12927 if (!isa<ConstantSDNode>(N2))
12929 auto *N2C = cast<ConstantSDNode>(N2);
12930 unsigned IdxVal = N2C->getZExtValue();
12932 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12933 // into that, and then insert the subvector back into the result.
12934 if (VT.is256BitVector() || VT.is512BitVector()) {
12935 // Get the desired 128-bit vector half.
12936 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12938 // Insert the element into the desired half.
12939 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12940 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12942 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12943 DAG.getConstant(IdxIn128, MVT::i32));
12945 // Insert the changed part back to the 256-bit vector
12946 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12948 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12950 if (Subtarget->hasSSE41()) {
12951 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12953 if (VT == MVT::v8i16) {
12954 Opc = X86ISD::PINSRW;
12956 assert(VT == MVT::v16i8);
12957 Opc = X86ISD::PINSRB;
12960 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12962 if (N1.getValueType() != MVT::i32)
12963 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12964 if (N2.getValueType() != MVT::i32)
12965 N2 = DAG.getIntPtrConstant(IdxVal);
12966 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12969 if (EltVT == MVT::f32) {
12970 // Bits [7:6] of the constant are the source select. This will always be
12971 // zero here. The DAG Combiner may combine an extract_elt index into
12973 // bits. For example (insert (extract, 3), 2) could be matched by
12975 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12976 // Bits [5:4] of the constant are the destination select. This is the
12977 // value of the incoming immediate.
12978 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12979 // combine either bitwise AND or insert of float 0.0 to set these bits.
12980 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12981 // Create this as a scalar to vector..
12982 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12983 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12986 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12987 // PINSR* works with constant index.
12992 if (EltVT == MVT::i8)
12995 if (EltVT.getSizeInBits() == 16) {
12996 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12997 // as its second argument.
12998 if (N1.getValueType() != MVT::i32)
12999 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
13000 if (N2.getValueType() != MVT::i32)
13001 N2 = DAG.getIntPtrConstant(IdxVal);
13002 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
13007 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
13009 MVT OpVT = Op.getSimpleValueType();
13011 // If this is a 256-bit vector result, first insert into a 128-bit
13012 // vector and then insert into the 256-bit vector.
13013 if (!OpVT.is128BitVector()) {
13014 // Insert into a 128-bit vector.
13015 unsigned SizeFactor = OpVT.getSizeInBits()/128;
13016 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
13017 OpVT.getVectorNumElements() / SizeFactor);
13019 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
13021 // Insert the 128-bit vector.
13022 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
13025 if (OpVT == MVT::v1i64 &&
13026 Op.getOperand(0).getValueType() == MVT::i64)
13027 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
13029 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
13030 assert(OpVT.is128BitVector() && "Expected an SSE type!");
13031 return DAG.getNode(ISD::BITCAST, dl, OpVT,
13032 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
13035 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
13036 // a simple subregister reference or explicit instructions to grab
13037 // upper bits of a vector.
13038 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13039 SelectionDAG &DAG) {
13041 SDValue In = Op.getOperand(0);
13042 SDValue Idx = Op.getOperand(1);
13043 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13044 MVT ResVT = Op.getSimpleValueType();
13045 MVT InVT = In.getSimpleValueType();
13047 if (Subtarget->hasFp256()) {
13048 if (ResVT.is128BitVector() &&
13049 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13050 isa<ConstantSDNode>(Idx)) {
13051 return Extract128BitVector(In, IdxVal, DAG, dl);
13053 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13054 isa<ConstantSDNode>(Idx)) {
13055 return Extract256BitVector(In, IdxVal, DAG, dl);
13061 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13062 // simple superregister reference or explicit instructions to insert
13063 // the upper bits of a vector.
13064 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13065 SelectionDAG &DAG) {
13066 if (Subtarget->hasFp256()) {
13067 SDLoc dl(Op.getNode());
13068 SDValue Vec = Op.getNode()->getOperand(0);
13069 SDValue SubVec = Op.getNode()->getOperand(1);
13070 SDValue Idx = Op.getNode()->getOperand(2);
13072 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13073 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13074 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13075 isa<ConstantSDNode>(Idx)) {
13076 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13077 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13080 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13081 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13082 isa<ConstantSDNode>(Idx)) {
13083 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13084 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13090 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13091 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13092 // one of the above mentioned nodes. It has to be wrapped because otherwise
13093 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13094 // be used to form addressing mode. These wrapped nodes will be selected
13097 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13098 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13100 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13101 // global base reg.
13102 unsigned char OpFlag = 0;
13103 unsigned WrapperKind = X86ISD::Wrapper;
13104 CodeModel::Model M = DAG.getTarget().getCodeModel();
13106 if (Subtarget->isPICStyleRIPRel() &&
13107 (M == CodeModel::Small || M == CodeModel::Kernel))
13108 WrapperKind = X86ISD::WrapperRIP;
13109 else if (Subtarget->isPICStyleGOT())
13110 OpFlag = X86II::MO_GOTOFF;
13111 else if (Subtarget->isPICStyleStubPIC())
13112 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13114 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13115 CP->getAlignment(),
13116 CP->getOffset(), OpFlag);
13118 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13119 // With PIC, the address is actually $g + Offset.
13121 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13122 DAG.getNode(X86ISD::GlobalBaseReg,
13123 SDLoc(), getPointerTy()),
13130 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13131 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13133 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13134 // global base reg.
13135 unsigned char OpFlag = 0;
13136 unsigned WrapperKind = X86ISD::Wrapper;
13137 CodeModel::Model M = DAG.getTarget().getCodeModel();
13139 if (Subtarget->isPICStyleRIPRel() &&
13140 (M == CodeModel::Small || M == CodeModel::Kernel))
13141 WrapperKind = X86ISD::WrapperRIP;
13142 else if (Subtarget->isPICStyleGOT())
13143 OpFlag = X86II::MO_GOTOFF;
13144 else if (Subtarget->isPICStyleStubPIC())
13145 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13147 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13150 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13152 // With PIC, the address is actually $g + Offset.
13154 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13155 DAG.getNode(X86ISD::GlobalBaseReg,
13156 SDLoc(), getPointerTy()),
13163 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13164 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13166 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13167 // global base reg.
13168 unsigned char OpFlag = 0;
13169 unsigned WrapperKind = X86ISD::Wrapper;
13170 CodeModel::Model M = DAG.getTarget().getCodeModel();
13172 if (Subtarget->isPICStyleRIPRel() &&
13173 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13174 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13175 OpFlag = X86II::MO_GOTPCREL;
13176 WrapperKind = X86ISD::WrapperRIP;
13177 } else if (Subtarget->isPICStyleGOT()) {
13178 OpFlag = X86II::MO_GOT;
13179 } else if (Subtarget->isPICStyleStubPIC()) {
13180 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13181 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13182 OpFlag = X86II::MO_DARWIN_NONLAZY;
13185 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13188 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13190 // With PIC, the address is actually $g + Offset.
13191 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13192 !Subtarget->is64Bit()) {
13193 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13194 DAG.getNode(X86ISD::GlobalBaseReg,
13195 SDLoc(), getPointerTy()),
13199 // For symbols that require a load from a stub to get the address, emit the
13201 if (isGlobalStubReference(OpFlag))
13202 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13203 MachinePointerInfo::getGOT(), false, false, false, 0);
13209 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13210 // Create the TargetBlockAddressAddress node.
13211 unsigned char OpFlags =
13212 Subtarget->ClassifyBlockAddressReference();
13213 CodeModel::Model M = DAG.getTarget().getCodeModel();
13214 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13215 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13217 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13220 if (Subtarget->isPICStyleRIPRel() &&
13221 (M == CodeModel::Small || M == CodeModel::Kernel))
13222 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13224 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13226 // With PIC, the address is actually $g + Offset.
13227 if (isGlobalRelativeToPICBase(OpFlags)) {
13228 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13229 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13237 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13238 int64_t Offset, SelectionDAG &DAG) const {
13239 // Create the TargetGlobalAddress node, folding in the constant
13240 // offset if it is legal.
13241 unsigned char OpFlags =
13242 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13243 CodeModel::Model M = DAG.getTarget().getCodeModel();
13245 if (OpFlags == X86II::MO_NO_FLAG &&
13246 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13247 // A direct static reference to a global.
13248 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13251 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13254 if (Subtarget->isPICStyleRIPRel() &&
13255 (M == CodeModel::Small || M == CodeModel::Kernel))
13256 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13258 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13260 // With PIC, the address is actually $g + Offset.
13261 if (isGlobalRelativeToPICBase(OpFlags)) {
13262 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13263 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13267 // For globals that require a load from a stub to get the address, emit the
13269 if (isGlobalStubReference(OpFlags))
13270 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13271 MachinePointerInfo::getGOT(), false, false, false, 0);
13273 // If there was a non-zero offset that we didn't fold, create an explicit
13274 // addition for it.
13276 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13277 DAG.getConstant(Offset, getPointerTy()));
13283 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13284 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13285 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13286 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13290 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13291 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13292 unsigned char OperandFlags, bool LocalDynamic = false) {
13293 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13294 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13296 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13297 GA->getValueType(0),
13301 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13305 SDValue Ops[] = { Chain, TGA, *InFlag };
13306 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13308 SDValue Ops[] = { Chain, TGA };
13309 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13312 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13313 MFI->setAdjustsStack(true);
13314 MFI->setHasCalls(true);
13316 SDValue Flag = Chain.getValue(1);
13317 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13320 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13322 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13325 SDLoc dl(GA); // ? function entry point might be better
13326 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13327 DAG.getNode(X86ISD::GlobalBaseReg,
13328 SDLoc(), PtrVT), InFlag);
13329 InFlag = Chain.getValue(1);
13331 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13334 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13336 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13338 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13339 X86::RAX, X86II::MO_TLSGD);
13342 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13348 // Get the start address of the TLS block for this module.
13349 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13350 .getInfo<X86MachineFunctionInfo>();
13351 MFI->incNumLocalDynamicTLSAccesses();
13355 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13356 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13359 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13360 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13361 InFlag = Chain.getValue(1);
13362 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13363 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13366 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13370 unsigned char OperandFlags = X86II::MO_DTPOFF;
13371 unsigned WrapperKind = X86ISD::Wrapper;
13372 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13373 GA->getValueType(0),
13374 GA->getOffset(), OperandFlags);
13375 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13377 // Add x@dtpoff with the base.
13378 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13381 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13382 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13383 const EVT PtrVT, TLSModel::Model model,
13384 bool is64Bit, bool isPIC) {
13387 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13388 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13389 is64Bit ? 257 : 256));
13391 SDValue ThreadPointer =
13392 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13393 MachinePointerInfo(Ptr), false, false, false, 0);
13395 unsigned char OperandFlags = 0;
13396 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13398 unsigned WrapperKind = X86ISD::Wrapper;
13399 if (model == TLSModel::LocalExec) {
13400 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13401 } else if (model == TLSModel::InitialExec) {
13403 OperandFlags = X86II::MO_GOTTPOFF;
13404 WrapperKind = X86ISD::WrapperRIP;
13406 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13409 llvm_unreachable("Unexpected model");
13412 // emit "addl x@ntpoff,%eax" (local exec)
13413 // or "addl x@indntpoff,%eax" (initial exec)
13414 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13416 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13417 GA->getOffset(), OperandFlags);
13418 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13420 if (model == TLSModel::InitialExec) {
13421 if (isPIC && !is64Bit) {
13422 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13423 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13427 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13428 MachinePointerInfo::getGOT(), false, false, false, 0);
13431 // The address of the thread local variable is the add of the thread
13432 // pointer with the offset of the variable.
13433 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13437 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13439 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13440 const GlobalValue *GV = GA->getGlobal();
13442 if (Subtarget->isTargetELF()) {
13443 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13446 case TLSModel::GeneralDynamic:
13447 if (Subtarget->is64Bit())
13448 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13449 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13450 case TLSModel::LocalDynamic:
13451 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13452 Subtarget->is64Bit());
13453 case TLSModel::InitialExec:
13454 case TLSModel::LocalExec:
13455 return LowerToTLSExecModel(
13456 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13457 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13459 llvm_unreachable("Unknown TLS model.");
13462 if (Subtarget->isTargetDarwin()) {
13463 // Darwin only has one model of TLS. Lower to that.
13464 unsigned char OpFlag = 0;
13465 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13466 X86ISD::WrapperRIP : X86ISD::Wrapper;
13468 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13469 // global base reg.
13470 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13471 !Subtarget->is64Bit();
13473 OpFlag = X86II::MO_TLVP_PIC_BASE;
13475 OpFlag = X86II::MO_TLVP;
13477 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13478 GA->getValueType(0),
13479 GA->getOffset(), OpFlag);
13480 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13482 // With PIC32, the address is actually $g + Offset.
13484 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13485 DAG.getNode(X86ISD::GlobalBaseReg,
13486 SDLoc(), getPointerTy()),
13489 // Lowering the machine isd will make sure everything is in the right
13491 SDValue Chain = DAG.getEntryNode();
13492 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13493 SDValue Args[] = { Chain, Offset };
13494 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13496 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13497 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13498 MFI->setAdjustsStack(true);
13500 // And our return value (tls address) is in the standard call return value
13502 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13503 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13504 Chain.getValue(1));
13507 if (Subtarget->isTargetKnownWindowsMSVC() ||
13508 Subtarget->isTargetWindowsGNU()) {
13509 // Just use the implicit TLS architecture
13510 // Need to generate someting similar to:
13511 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13513 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13514 // mov rcx, qword [rdx+rcx*8]
13515 // mov eax, .tls$:tlsvar
13516 // [rax+rcx] contains the address
13517 // Windows 64bit: gs:0x58
13518 // Windows 32bit: fs:__tls_array
13521 SDValue Chain = DAG.getEntryNode();
13523 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13524 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13525 // use its literal value of 0x2C.
13526 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13527 ? Type::getInt8PtrTy(*DAG.getContext(),
13529 : Type::getInt32PtrTy(*DAG.getContext(),
13533 Subtarget->is64Bit()
13534 ? DAG.getIntPtrConstant(0x58)
13535 : (Subtarget->isTargetWindowsGNU()
13536 ? DAG.getIntPtrConstant(0x2C)
13537 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13539 SDValue ThreadPointer =
13540 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13541 MachinePointerInfo(Ptr), false, false, false, 0);
13543 // Load the _tls_index variable
13544 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13545 if (Subtarget->is64Bit())
13546 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13547 IDX, MachinePointerInfo(), MVT::i32,
13548 false, false, false, 0);
13550 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13551 false, false, false, 0);
13553 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13555 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13557 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13558 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13559 false, false, false, 0);
13561 // Get the offset of start of .tls section
13562 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13563 GA->getValueType(0),
13564 GA->getOffset(), X86II::MO_SECREL);
13565 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13567 // The address of the thread local variable is the add of the thread
13568 // pointer with the offset of the variable.
13569 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13572 llvm_unreachable("TLS not implemented for this target.");
13575 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13576 /// and take a 2 x i32 value to shift plus a shift amount.
13577 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13578 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13579 MVT VT = Op.getSimpleValueType();
13580 unsigned VTBits = VT.getSizeInBits();
13582 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13583 SDValue ShOpLo = Op.getOperand(0);
13584 SDValue ShOpHi = Op.getOperand(1);
13585 SDValue ShAmt = Op.getOperand(2);
13586 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13587 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13589 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13590 DAG.getConstant(VTBits - 1, MVT::i8));
13591 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13592 DAG.getConstant(VTBits - 1, MVT::i8))
13593 : DAG.getConstant(0, VT);
13595 SDValue Tmp2, Tmp3;
13596 if (Op.getOpcode() == ISD::SHL_PARTS) {
13597 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13598 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13600 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13601 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13604 // If the shift amount is larger or equal than the width of a part we can't
13605 // rely on the results of shld/shrd. Insert a test and select the appropriate
13606 // values for large shift amounts.
13607 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13608 DAG.getConstant(VTBits, MVT::i8));
13609 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13610 AndNode, DAG.getConstant(0, MVT::i8));
13613 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13614 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13615 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13617 if (Op.getOpcode() == ISD::SHL_PARTS) {
13618 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13619 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13621 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13622 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13625 SDValue Ops[2] = { Lo, Hi };
13626 return DAG.getMergeValues(Ops, dl);
13629 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13630 SelectionDAG &DAG) const {
13631 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13634 if (SrcVT.isVector()) {
13635 if (SrcVT.getVectorElementType() == MVT::i1) {
13636 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13637 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13638 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13639 Op.getOperand(0)));
13644 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13645 "Unknown SINT_TO_FP to lower!");
13647 // These are really Legal; return the operand so the caller accepts it as
13649 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13651 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13652 Subtarget->is64Bit()) {
13656 unsigned Size = SrcVT.getSizeInBits()/8;
13657 MachineFunction &MF = DAG.getMachineFunction();
13658 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13659 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13660 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13662 MachinePointerInfo::getFixedStack(SSFI),
13664 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13667 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13669 SelectionDAG &DAG) const {
13673 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13675 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13677 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13679 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13681 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13682 MachineMemOperand *MMO;
13684 int SSFI = FI->getIndex();
13686 DAG.getMachineFunction()
13687 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13688 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13690 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13691 StackSlot = StackSlot.getOperand(1);
13693 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13694 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13696 Tys, Ops, SrcVT, MMO);
13699 Chain = Result.getValue(1);
13700 SDValue InFlag = Result.getValue(2);
13702 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13703 // shouldn't be necessary except that RFP cannot be live across
13704 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13705 MachineFunction &MF = DAG.getMachineFunction();
13706 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13707 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13708 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13709 Tys = DAG.getVTList(MVT::Other);
13711 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13713 MachineMemOperand *MMO =
13714 DAG.getMachineFunction()
13715 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13716 MachineMemOperand::MOStore, SSFISize, SSFISize);
13718 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13719 Ops, Op.getValueType(), MMO);
13720 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13721 MachinePointerInfo::getFixedStack(SSFI),
13722 false, false, false, 0);
13728 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13729 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13730 SelectionDAG &DAG) const {
13731 // This algorithm is not obvious. Here it is what we're trying to output:
13734 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13735 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13737 haddpd %xmm0, %xmm0
13739 pshufd $0x4e, %xmm0, %xmm1
13745 LLVMContext *Context = DAG.getContext();
13747 // Build some magic constants.
13748 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13749 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13750 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13752 SmallVector<Constant*,2> CV1;
13754 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13755 APInt(64, 0x4330000000000000ULL))));
13757 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13758 APInt(64, 0x4530000000000000ULL))));
13759 Constant *C1 = ConstantVector::get(CV1);
13760 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13762 // Load the 64-bit value into an XMM register.
13763 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13765 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13766 MachinePointerInfo::getConstantPool(),
13767 false, false, false, 16);
13768 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13769 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13772 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13773 MachinePointerInfo::getConstantPool(),
13774 false, false, false, 16);
13775 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13776 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13779 if (Subtarget->hasSSE3()) {
13780 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13781 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13783 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13784 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13786 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13787 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13791 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13792 DAG.getIntPtrConstant(0));
13795 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13796 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13797 SelectionDAG &DAG) const {
13799 // FP constant to bias correct the final result.
13800 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13803 // Load the 32-bit value into an XMM register.
13804 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13807 // Zero out the upper parts of the register.
13808 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13810 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13811 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13812 DAG.getIntPtrConstant(0));
13814 // Or the load with the bias.
13815 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13816 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13817 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13818 MVT::v2f64, Load)),
13819 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13820 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13821 MVT::v2f64, Bias)));
13822 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13823 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13824 DAG.getIntPtrConstant(0));
13826 // Subtract the bias.
13827 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13829 // Handle final rounding.
13830 EVT DestVT = Op.getValueType();
13832 if (DestVT.bitsLT(MVT::f64))
13833 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13834 DAG.getIntPtrConstant(0));
13835 if (DestVT.bitsGT(MVT::f64))
13836 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13838 // Handle final rounding.
13842 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13843 const X86Subtarget &Subtarget) {
13844 // The algorithm is the following:
13845 // #ifdef __SSE4_1__
13846 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13847 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13848 // (uint4) 0x53000000, 0xaa);
13850 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13851 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13853 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13854 // return (float4) lo + fhi;
13857 SDValue V = Op->getOperand(0);
13858 EVT VecIntVT = V.getValueType();
13859 bool Is128 = VecIntVT == MVT::v4i32;
13860 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13861 // If we convert to something else than the supported type, e.g., to v4f64,
13863 if (VecFloatVT != Op->getValueType(0))
13866 unsigned NumElts = VecIntVT.getVectorNumElements();
13867 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13868 "Unsupported custom type");
13869 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13871 // In the #idef/#else code, we have in common:
13872 // - The vector of constants:
13878 // Create the splat vector for 0x4b000000.
13879 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13880 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13881 CstLow, CstLow, CstLow, CstLow};
13882 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13883 makeArrayRef(&CstLowArray[0], NumElts));
13884 // Create the splat vector for 0x53000000.
13885 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13886 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13887 CstHigh, CstHigh, CstHigh, CstHigh};
13888 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13889 makeArrayRef(&CstHighArray[0], NumElts));
13891 // Create the right shift.
13892 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13893 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13894 CstShift, CstShift, CstShift, CstShift};
13895 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13896 makeArrayRef(&CstShiftArray[0], NumElts));
13897 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13900 if (Subtarget.hasSSE41()) {
13901 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13902 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13903 SDValue VecCstLowBitcast =
13904 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13905 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13906 // Low will be bitcasted right away, so do not bother bitcasting back to its
13908 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13909 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13910 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13911 // (uint4) 0x53000000, 0xaa);
13912 SDValue VecCstHighBitcast =
13913 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13914 SDValue VecShiftBitcast =
13915 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13916 // High will be bitcasted right away, so do not bother bitcasting back to
13917 // its original type.
13918 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13919 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13921 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13922 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13923 CstMask, CstMask, CstMask);
13924 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13925 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13926 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13928 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13929 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13932 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13933 SDValue CstFAdd = DAG.getConstantFP(
13934 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13935 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13936 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13937 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13938 makeArrayRef(&CstFAddArray[0], NumElts));
13940 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13941 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13943 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13944 // return (float4) lo + fhi;
13945 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13946 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13949 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13950 SelectionDAG &DAG) const {
13951 SDValue N0 = Op.getOperand(0);
13952 MVT SVT = N0.getSimpleValueType();
13955 switch (SVT.SimpleTy) {
13957 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13962 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13963 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13964 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13968 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13970 llvm_unreachable(nullptr);
13973 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13974 SelectionDAG &DAG) const {
13975 SDValue N0 = Op.getOperand(0);
13978 if (Op.getValueType().isVector())
13979 return lowerUINT_TO_FP_vec(Op, DAG);
13981 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13982 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13983 // the optimization here.
13984 if (DAG.SignBitIsZero(N0))
13985 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13987 MVT SrcVT = N0.getSimpleValueType();
13988 MVT DstVT = Op.getSimpleValueType();
13989 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13990 return LowerUINT_TO_FP_i64(Op, DAG);
13991 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13992 return LowerUINT_TO_FP_i32(Op, DAG);
13993 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13996 // Make a 64-bit buffer, and use it to build an FILD.
13997 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13998 if (SrcVT == MVT::i32) {
13999 SDValue WordOff = DAG.getConstant(4, getPointerTy());
14000 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
14001 getPointerTy(), StackSlot, WordOff);
14002 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
14003 StackSlot, MachinePointerInfo(),
14005 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
14006 OffsetSlot, MachinePointerInfo(),
14008 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
14012 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
14013 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
14014 StackSlot, MachinePointerInfo(),
14016 // For i64 source, we need to add the appropriate power of 2 if the input
14017 // was negative. This is the same as the optimization in
14018 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
14019 // we must be careful to do the computation in x87 extended precision, not
14020 // in SSE. (The generic code can't know it's OK to do this, or how to.)
14021 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
14022 MachineMemOperand *MMO =
14023 DAG.getMachineFunction()
14024 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14025 MachineMemOperand::MOLoad, 8, 8);
14027 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
14028 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
14029 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
14032 APInt FF(32, 0x5F800000ULL);
14034 // Check whether the sign bit is set.
14035 SDValue SignSet = DAG.getSetCC(dl,
14036 getSetCCResultType(*DAG.getContext(), MVT::i64),
14037 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14040 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14041 SDValue FudgePtr = DAG.getConstantPool(
14042 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14045 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14046 SDValue Zero = DAG.getIntPtrConstant(0);
14047 SDValue Four = DAG.getIntPtrConstant(4);
14048 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14050 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14052 // Load the value out, extending it from f32 to f80.
14053 // FIXME: Avoid the extend by constructing the right constant pool?
14054 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14055 FudgePtr, MachinePointerInfo::getConstantPool(),
14056 MVT::f32, false, false, false, 4);
14057 // Extend everything to 80 bits to force it to be done on x87.
14058 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14059 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14062 std::pair<SDValue,SDValue>
14063 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14064 bool IsSigned, bool IsReplace) const {
14067 EVT DstTy = Op.getValueType();
14069 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14070 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14074 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14075 DstTy.getSimpleVT() >= MVT::i16 &&
14076 "Unknown FP_TO_INT to lower!");
14078 // These are really Legal.
14079 if (DstTy == MVT::i32 &&
14080 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14081 return std::make_pair(SDValue(), SDValue());
14082 if (Subtarget->is64Bit() &&
14083 DstTy == MVT::i64 &&
14084 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14085 return std::make_pair(SDValue(), SDValue());
14087 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14088 // stack slot, or into the FTOL runtime function.
14089 MachineFunction &MF = DAG.getMachineFunction();
14090 unsigned MemSize = DstTy.getSizeInBits()/8;
14091 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14092 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14095 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14096 Opc = X86ISD::WIN_FTOL;
14098 switch (DstTy.getSimpleVT().SimpleTy) {
14099 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14100 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14101 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14102 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14105 SDValue Chain = DAG.getEntryNode();
14106 SDValue Value = Op.getOperand(0);
14107 EVT TheVT = Op.getOperand(0).getValueType();
14108 // FIXME This causes a redundant load/store if the SSE-class value is already
14109 // in memory, such as if it is on the callstack.
14110 if (isScalarFPTypeInSSEReg(TheVT)) {
14111 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14112 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14113 MachinePointerInfo::getFixedStack(SSFI),
14115 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14117 Chain, StackSlot, DAG.getValueType(TheVT)
14120 MachineMemOperand *MMO =
14121 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14122 MachineMemOperand::MOLoad, MemSize, MemSize);
14123 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14124 Chain = Value.getValue(1);
14125 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14126 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14129 MachineMemOperand *MMO =
14130 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14131 MachineMemOperand::MOStore, MemSize, MemSize);
14133 if (Opc != X86ISD::WIN_FTOL) {
14134 // Build the FP_TO_INT*_IN_MEM
14135 SDValue Ops[] = { Chain, Value, StackSlot };
14136 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14138 return std::make_pair(FIST, StackSlot);
14140 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14141 DAG.getVTList(MVT::Other, MVT::Glue),
14143 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14144 MVT::i32, ftol.getValue(1));
14145 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14146 MVT::i32, eax.getValue(2));
14147 SDValue Ops[] = { eax, edx };
14148 SDValue pair = IsReplace
14149 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14150 : DAG.getMergeValues(Ops, DL);
14151 return std::make_pair(pair, SDValue());
14155 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14156 const X86Subtarget *Subtarget) {
14157 MVT VT = Op->getSimpleValueType(0);
14158 SDValue In = Op->getOperand(0);
14159 MVT InVT = In.getSimpleValueType();
14162 // Optimize vectors in AVX mode:
14165 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14166 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14167 // Concat upper and lower parts.
14170 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14171 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14172 // Concat upper and lower parts.
14175 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14176 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14177 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14180 if (Subtarget->hasInt256())
14181 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14183 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14184 SDValue Undef = DAG.getUNDEF(InVT);
14185 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14186 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14187 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14189 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14190 VT.getVectorNumElements()/2);
14192 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14193 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14195 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14198 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14199 SelectionDAG &DAG) {
14200 MVT VT = Op->getSimpleValueType(0);
14201 SDValue In = Op->getOperand(0);
14202 MVT InVT = In.getSimpleValueType();
14204 unsigned int NumElts = VT.getVectorNumElements();
14205 if (NumElts != 8 && NumElts != 16)
14208 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14209 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14211 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14212 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14213 // Now we have only mask extension
14214 assert(InVT.getVectorElementType() == MVT::i1);
14215 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14216 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14217 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14218 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14219 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14220 MachinePointerInfo::getConstantPool(),
14221 false, false, false, Alignment);
14223 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14224 if (VT.is512BitVector())
14226 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14229 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14230 SelectionDAG &DAG) {
14231 if (Subtarget->hasFp256()) {
14232 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14240 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14241 SelectionDAG &DAG) {
14243 MVT VT = Op.getSimpleValueType();
14244 SDValue In = Op.getOperand(0);
14245 MVT SVT = In.getSimpleValueType();
14247 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14248 return LowerZERO_EXTEND_AVX512(Op, DAG);
14250 if (Subtarget->hasFp256()) {
14251 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14256 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14257 VT.getVectorNumElements() != SVT.getVectorNumElements());
14261 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14263 MVT VT = Op.getSimpleValueType();
14264 SDValue In = Op.getOperand(0);
14265 MVT InVT = In.getSimpleValueType();
14267 if (VT == MVT::i1) {
14268 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14269 "Invalid scalar TRUNCATE operation");
14270 if (InVT.getSizeInBits() >= 32)
14272 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14273 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14275 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14276 "Invalid TRUNCATE operation");
14278 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14279 if (VT.getVectorElementType().getSizeInBits() >=8)
14280 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14282 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14283 unsigned NumElts = InVT.getVectorNumElements();
14284 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14285 if (InVT.getSizeInBits() < 512) {
14286 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14287 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14291 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14292 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14293 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14294 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14295 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14296 MachinePointerInfo::getConstantPool(),
14297 false, false, false, Alignment);
14298 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14299 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14300 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14303 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14304 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14305 if (Subtarget->hasInt256()) {
14306 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14307 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14308 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14310 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14311 DAG.getIntPtrConstant(0));
14314 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14315 DAG.getIntPtrConstant(0));
14316 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14317 DAG.getIntPtrConstant(2));
14318 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14319 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14320 static const int ShufMask[] = {0, 2, 4, 6};
14321 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14324 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14325 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14326 if (Subtarget->hasInt256()) {
14327 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14329 SmallVector<SDValue,32> pshufbMask;
14330 for (unsigned i = 0; i < 2; ++i) {
14331 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14332 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14333 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14334 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14335 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14336 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14337 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14338 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14339 for (unsigned j = 0; j < 8; ++j)
14340 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14342 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14343 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14344 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14346 static const int ShufMask[] = {0, 2, -1, -1};
14347 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14349 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14350 DAG.getIntPtrConstant(0));
14351 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14354 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14355 DAG.getIntPtrConstant(0));
14357 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14358 DAG.getIntPtrConstant(4));
14360 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14361 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14363 // The PSHUFB mask:
14364 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14365 -1, -1, -1, -1, -1, -1, -1, -1};
14367 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14368 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14369 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14371 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14372 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14374 // The MOVLHPS Mask:
14375 static const int ShufMask2[] = {0, 1, 4, 5};
14376 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14377 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14380 // Handle truncation of V256 to V128 using shuffles.
14381 if (!VT.is128BitVector() || !InVT.is256BitVector())
14384 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14386 unsigned NumElems = VT.getVectorNumElements();
14387 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14389 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14390 // Prepare truncation shuffle mask
14391 for (unsigned i = 0; i != NumElems; ++i)
14392 MaskVec[i] = i * 2;
14393 SDValue V = DAG.getVectorShuffle(NVT, DL,
14394 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14395 DAG.getUNDEF(NVT), &MaskVec[0]);
14396 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14397 DAG.getIntPtrConstant(0));
14400 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14401 SelectionDAG &DAG) const {
14402 assert(!Op.getSimpleValueType().isVector());
14404 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14405 /*IsSigned=*/ true, /*IsReplace=*/ false);
14406 SDValue FIST = Vals.first, StackSlot = Vals.second;
14407 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14408 if (!FIST.getNode()) return Op;
14410 if (StackSlot.getNode())
14411 // Load the result.
14412 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14413 FIST, StackSlot, MachinePointerInfo(),
14414 false, false, false, 0);
14416 // The node is the result.
14420 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14421 SelectionDAG &DAG) const {
14422 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14423 /*IsSigned=*/ false, /*IsReplace=*/ false);
14424 SDValue FIST = Vals.first, StackSlot = Vals.second;
14425 assert(FIST.getNode() && "Unexpected failure");
14427 if (StackSlot.getNode())
14428 // Load the result.
14429 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14430 FIST, StackSlot, MachinePointerInfo(),
14431 false, false, false, 0);
14433 // The node is the result.
14437 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14439 MVT VT = Op.getSimpleValueType();
14440 SDValue In = Op.getOperand(0);
14441 MVT SVT = In.getSimpleValueType();
14443 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14445 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14446 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14447 In, DAG.getUNDEF(SVT)));
14450 /// The only differences between FABS and FNEG are the mask and the logic op.
14451 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14452 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14453 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14454 "Wrong opcode for lowering FABS or FNEG.");
14456 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14458 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14459 // into an FNABS. We'll lower the FABS after that if it is still in use.
14461 for (SDNode *User : Op->uses())
14462 if (User->getOpcode() == ISD::FNEG)
14465 SDValue Op0 = Op.getOperand(0);
14466 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14469 MVT VT = Op.getSimpleValueType();
14470 // Assume scalar op for initialization; update for vector if needed.
14471 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14472 // generate a 16-byte vector constant and logic op even for the scalar case.
14473 // Using a 16-byte mask allows folding the load of the mask with
14474 // the logic op, so it can save (~4 bytes) on code size.
14476 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14477 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14478 // decide if we should generate a 16-byte constant mask when we only need 4 or
14479 // 8 bytes for the scalar case.
14480 if (VT.isVector()) {
14481 EltVT = VT.getVectorElementType();
14482 NumElts = VT.getVectorNumElements();
14485 unsigned EltBits = EltVT.getSizeInBits();
14486 LLVMContext *Context = DAG.getContext();
14487 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14489 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14490 Constant *C = ConstantInt::get(*Context, MaskElt);
14491 C = ConstantVector::getSplat(NumElts, C);
14492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14493 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14494 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14495 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14496 MachinePointerInfo::getConstantPool(),
14497 false, false, false, Alignment);
14499 if (VT.isVector()) {
14500 // For a vector, cast operands to a vector type, perform the logic op,
14501 // and cast the result back to the original value type.
14502 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14503 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14504 SDValue Operand = IsFNABS ?
14505 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14506 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14507 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14508 return DAG.getNode(ISD::BITCAST, dl, VT,
14509 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14512 // If not vector, then scalar.
14513 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14514 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14515 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14518 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14520 LLVMContext *Context = DAG.getContext();
14521 SDValue Op0 = Op.getOperand(0);
14522 SDValue Op1 = Op.getOperand(1);
14524 MVT VT = Op.getSimpleValueType();
14525 MVT SrcVT = Op1.getSimpleValueType();
14527 // If second operand is smaller, extend it first.
14528 if (SrcVT.bitsLT(VT)) {
14529 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14532 // And if it is bigger, shrink it first.
14533 if (SrcVT.bitsGT(VT)) {
14534 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14538 // At this point the operands and the result should have the same
14539 // type, and that won't be f80 since that is not custom lowered.
14541 const fltSemantics &Sem =
14542 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14543 const unsigned SizeInBits = VT.getSizeInBits();
14545 SmallVector<Constant *, 4> CV(
14546 VT == MVT::f64 ? 2 : 4,
14547 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14549 // First, clear all bits but the sign bit from the second operand (sign).
14550 CV[0] = ConstantFP::get(*Context,
14551 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14552 Constant *C = ConstantVector::get(CV);
14553 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14554 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14555 MachinePointerInfo::getConstantPool(),
14556 false, false, false, 16);
14557 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14559 // Next, clear the sign bit from the first operand (magnitude).
14560 // If it's a constant, we can clear it here.
14561 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
14562 APFloat APF = Op0CN->getValueAPF();
14563 // If the magnitude is a positive zero, the sign bit alone is enough.
14564 if (APF.isPosZero())
14567 CV[0] = ConstantFP::get(*Context, APF);
14569 CV[0] = ConstantFP::get(
14571 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14573 C = ConstantVector::get(CV);
14574 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14575 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14576 MachinePointerInfo::getConstantPool(),
14577 false, false, false, 16);
14578 // If the magnitude operand wasn't a constant, we need to AND out the sign.
14579 if (!isa<ConstantFPSDNode>(Op0))
14580 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
14582 // OR the magnitude value with the sign bit.
14583 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14586 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14587 SDValue N0 = Op.getOperand(0);
14589 MVT VT = Op.getSimpleValueType();
14591 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14592 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14593 DAG.getConstant(1, VT));
14594 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14597 // Check whether an OR'd tree is PTEST-able.
14598 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14599 SelectionDAG &DAG) {
14600 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14602 if (!Subtarget->hasSSE41())
14605 if (!Op->hasOneUse())
14608 SDNode *N = Op.getNode();
14611 SmallVector<SDValue, 8> Opnds;
14612 DenseMap<SDValue, unsigned> VecInMap;
14613 SmallVector<SDValue, 8> VecIns;
14614 EVT VT = MVT::Other;
14616 // Recognize a special case where a vector is casted into wide integer to
14618 Opnds.push_back(N->getOperand(0));
14619 Opnds.push_back(N->getOperand(1));
14621 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14622 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14623 // BFS traverse all OR'd operands.
14624 if (I->getOpcode() == ISD::OR) {
14625 Opnds.push_back(I->getOperand(0));
14626 Opnds.push_back(I->getOperand(1));
14627 // Re-evaluate the number of nodes to be traversed.
14628 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14632 // Quit if a non-EXTRACT_VECTOR_ELT
14633 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14636 // Quit if without a constant index.
14637 SDValue Idx = I->getOperand(1);
14638 if (!isa<ConstantSDNode>(Idx))
14641 SDValue ExtractedFromVec = I->getOperand(0);
14642 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14643 if (M == VecInMap.end()) {
14644 VT = ExtractedFromVec.getValueType();
14645 // Quit if not 128/256-bit vector.
14646 if (!VT.is128BitVector() && !VT.is256BitVector())
14648 // Quit if not the same type.
14649 if (VecInMap.begin() != VecInMap.end() &&
14650 VT != VecInMap.begin()->first.getValueType())
14652 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14653 VecIns.push_back(ExtractedFromVec);
14655 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14658 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14659 "Not extracted from 128-/256-bit vector.");
14661 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14663 for (DenseMap<SDValue, unsigned>::const_iterator
14664 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14665 // Quit if not all elements are used.
14666 if (I->second != FullMask)
14670 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14672 // Cast all vectors into TestVT for PTEST.
14673 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14674 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14676 // If more than one full vectors are evaluated, OR them first before PTEST.
14677 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14678 // Each iteration will OR 2 nodes and append the result until there is only
14679 // 1 node left, i.e. the final OR'd value of all vectors.
14680 SDValue LHS = VecIns[Slot];
14681 SDValue RHS = VecIns[Slot + 1];
14682 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14685 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14686 VecIns.back(), VecIns.back());
14689 /// \brief return true if \c Op has a use that doesn't just read flags.
14690 static bool hasNonFlagsUse(SDValue Op) {
14691 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14693 SDNode *User = *UI;
14694 unsigned UOpNo = UI.getOperandNo();
14695 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14696 // Look pass truncate.
14697 UOpNo = User->use_begin().getOperandNo();
14698 User = *User->use_begin();
14701 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14702 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14708 /// Emit nodes that will be selected as "test Op0,Op0", or something
14710 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14711 SelectionDAG &DAG) const {
14712 if (Op.getValueType() == MVT::i1)
14713 // KORTEST instruction should be selected
14714 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14715 DAG.getConstant(0, Op.getValueType()));
14717 // CF and OF aren't always set the way we want. Determine which
14718 // of these we need.
14719 bool NeedCF = false;
14720 bool NeedOF = false;
14723 case X86::COND_A: case X86::COND_AE:
14724 case X86::COND_B: case X86::COND_BE:
14727 case X86::COND_G: case X86::COND_GE:
14728 case X86::COND_L: case X86::COND_LE:
14729 case X86::COND_O: case X86::COND_NO: {
14730 // Check if we really need to set the
14731 // Overflow flag. If NoSignedWrap is present
14732 // that is not actually needed.
14733 switch (Op->getOpcode()) {
14738 const BinaryWithFlagsSDNode *BinNode =
14739 cast<BinaryWithFlagsSDNode>(Op.getNode());
14740 if (BinNode->hasNoSignedWrap())
14750 // See if we can use the EFLAGS value from the operand instead of
14751 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14752 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14753 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14754 // Emit a CMP with 0, which is the TEST pattern.
14755 //if (Op.getValueType() == MVT::i1)
14756 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14757 // DAG.getConstant(0, MVT::i1));
14758 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14759 DAG.getConstant(0, Op.getValueType()));
14761 unsigned Opcode = 0;
14762 unsigned NumOperands = 0;
14764 // Truncate operations may prevent the merge of the SETCC instruction
14765 // and the arithmetic instruction before it. Attempt to truncate the operands
14766 // of the arithmetic instruction and use a reduced bit-width instruction.
14767 bool NeedTruncation = false;
14768 SDValue ArithOp = Op;
14769 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14770 SDValue Arith = Op->getOperand(0);
14771 // Both the trunc and the arithmetic op need to have one user each.
14772 if (Arith->hasOneUse())
14773 switch (Arith.getOpcode()) {
14780 NeedTruncation = true;
14786 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14787 // which may be the result of a CAST. We use the variable 'Op', which is the
14788 // non-casted variable when we check for possible users.
14789 switch (ArithOp.getOpcode()) {
14791 // Due to an isel shortcoming, be conservative if this add is likely to be
14792 // selected as part of a load-modify-store instruction. When the root node
14793 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14794 // uses of other nodes in the match, such as the ADD in this case. This
14795 // leads to the ADD being left around and reselected, with the result being
14796 // two adds in the output. Alas, even if none our users are stores, that
14797 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14798 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14799 // climbing the DAG back to the root, and it doesn't seem to be worth the
14801 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14802 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14803 if (UI->getOpcode() != ISD::CopyToReg &&
14804 UI->getOpcode() != ISD::SETCC &&
14805 UI->getOpcode() != ISD::STORE)
14808 if (ConstantSDNode *C =
14809 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14810 // An add of one will be selected as an INC.
14811 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14812 Opcode = X86ISD::INC;
14817 // An add of negative one (subtract of one) will be selected as a DEC.
14818 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14819 Opcode = X86ISD::DEC;
14825 // Otherwise use a regular EFLAGS-setting add.
14826 Opcode = X86ISD::ADD;
14831 // If we have a constant logical shift that's only used in a comparison
14832 // against zero turn it into an equivalent AND. This allows turning it into
14833 // a TEST instruction later.
14834 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14835 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14836 EVT VT = Op.getValueType();
14837 unsigned BitWidth = VT.getSizeInBits();
14838 unsigned ShAmt = Op->getConstantOperandVal(1);
14839 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14841 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14842 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14843 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14844 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14846 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14847 DAG.getConstant(Mask, VT));
14848 DAG.ReplaceAllUsesWith(Op, New);
14854 // If the primary and result isn't used, don't bother using X86ISD::AND,
14855 // because a TEST instruction will be better.
14856 if (!hasNonFlagsUse(Op))
14862 // Due to the ISEL shortcoming noted above, be conservative if this op is
14863 // likely to be selected as part of a load-modify-store instruction.
14864 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14865 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14866 if (UI->getOpcode() == ISD::STORE)
14869 // Otherwise use a regular EFLAGS-setting instruction.
14870 switch (ArithOp.getOpcode()) {
14871 default: llvm_unreachable("unexpected operator!");
14872 case ISD::SUB: Opcode = X86ISD::SUB; break;
14873 case ISD::XOR: Opcode = X86ISD::XOR; break;
14874 case ISD::AND: Opcode = X86ISD::AND; break;
14876 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14877 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14878 if (EFLAGS.getNode())
14881 Opcode = X86ISD::OR;
14895 return SDValue(Op.getNode(), 1);
14901 // If we found that truncation is beneficial, perform the truncation and
14903 if (NeedTruncation) {
14904 EVT VT = Op.getValueType();
14905 SDValue WideVal = Op->getOperand(0);
14906 EVT WideVT = WideVal.getValueType();
14907 unsigned ConvertedOp = 0;
14908 // Use a target machine opcode to prevent further DAGCombine
14909 // optimizations that may separate the arithmetic operations
14910 // from the setcc node.
14911 switch (WideVal.getOpcode()) {
14913 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14914 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14915 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14916 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14917 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14921 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14922 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14923 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14924 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14925 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14931 // Emit a CMP with 0, which is the TEST pattern.
14932 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14933 DAG.getConstant(0, Op.getValueType()));
14935 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14936 SmallVector<SDValue, 4> Ops;
14937 for (unsigned i = 0; i != NumOperands; ++i)
14938 Ops.push_back(Op.getOperand(i));
14940 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14941 DAG.ReplaceAllUsesWith(Op, New);
14942 return SDValue(New.getNode(), 1);
14945 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14947 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14948 SDLoc dl, SelectionDAG &DAG) const {
14949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14950 if (C->getAPIntValue() == 0)
14951 return EmitTest(Op0, X86CC, dl, DAG);
14953 if (Op0.getValueType() == MVT::i1)
14954 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14957 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14958 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14959 // Do the comparison at i32 if it's smaller, besides the Atom case.
14960 // This avoids subregister aliasing issues. Keep the smaller reference
14961 // if we're optimizing for size, however, as that'll allow better folding
14962 // of memory operations.
14963 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14964 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14965 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14966 !Subtarget->isAtom()) {
14967 unsigned ExtendOp =
14968 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14969 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14970 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14972 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14973 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14974 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14976 return SDValue(Sub.getNode(), 1);
14978 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14981 /// Convert a comparison if required by the subtarget.
14982 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14983 SelectionDAG &DAG) const {
14984 // If the subtarget does not support the FUCOMI instruction, floating-point
14985 // comparisons have to be converted.
14986 if (Subtarget->hasCMov() ||
14987 Cmp.getOpcode() != X86ISD::CMP ||
14988 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14989 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14992 // The instruction selector will select an FUCOM instruction instead of
14993 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14994 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14995 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14997 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14998 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14999 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
15000 DAG.getConstant(8, MVT::i8));
15001 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
15002 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
15005 /// The minimum architected relative accuracy is 2^-12. We need one
15006 /// Newton-Raphson step to have a good float result (24 bits of precision).
15007 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
15008 DAGCombinerInfo &DCI,
15009 unsigned &RefinementSteps,
15010 bool &UseOneConstNR) const {
15011 // FIXME: We should use instruction latency models to calculate the cost of
15012 // each potential sequence, but this is very hard to do reliably because
15013 // at least Intel's Core* chips have variable timing based on the number of
15014 // significant digits in the divisor and/or sqrt operand.
15015 if (!Subtarget->useSqrtEst())
15018 EVT VT = Op.getValueType();
15020 // SSE1 has rsqrtss and rsqrtps.
15021 // TODO: Add support for AVX512 (v16f32).
15022 // It is likely not profitable to do this for f64 because a double-precision
15023 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
15024 // instructions: convert to single, rsqrtss, convert back to double, refine
15025 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
15026 // along with FMA, this could be a throughput win.
15027 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15028 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15029 RefinementSteps = 1;
15030 UseOneConstNR = false;
15031 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
15036 /// The minimum architected relative accuracy is 2^-12. We need one
15037 /// Newton-Raphson step to have a good float result (24 bits of precision).
15038 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
15039 DAGCombinerInfo &DCI,
15040 unsigned &RefinementSteps) const {
15041 // FIXME: We should use instruction latency models to calculate the cost of
15042 // each potential sequence, but this is very hard to do reliably because
15043 // at least Intel's Core* chips have variable timing based on the number of
15044 // significant digits in the divisor.
15045 if (!Subtarget->useReciprocalEst())
15048 EVT VT = Op.getValueType();
15050 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
15051 // TODO: Add support for AVX512 (v16f32).
15052 // It is likely not profitable to do this for f64 because a double-precision
15053 // reciprocal estimate with refinement on x86 prior to FMA requires
15054 // 15 instructions: convert to single, rcpss, convert back to double, refine
15055 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15056 // along with FMA, this could be a throughput win.
15057 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15058 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15059 RefinementSteps = ReciprocalEstimateRefinementSteps;
15060 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15065 static bool isAllOnes(SDValue V) {
15066 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15067 return C && C->isAllOnesValue();
15070 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15071 /// if it's possible.
15072 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15073 SDLoc dl, SelectionDAG &DAG) const {
15074 SDValue Op0 = And.getOperand(0);
15075 SDValue Op1 = And.getOperand(1);
15076 if (Op0.getOpcode() == ISD::TRUNCATE)
15077 Op0 = Op0.getOperand(0);
15078 if (Op1.getOpcode() == ISD::TRUNCATE)
15079 Op1 = Op1.getOperand(0);
15082 if (Op1.getOpcode() == ISD::SHL)
15083 std::swap(Op0, Op1);
15084 if (Op0.getOpcode() == ISD::SHL) {
15085 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15086 if (And00C->getZExtValue() == 1) {
15087 // If we looked past a truncate, check that it's only truncating away
15089 unsigned BitWidth = Op0.getValueSizeInBits();
15090 unsigned AndBitWidth = And.getValueSizeInBits();
15091 if (BitWidth > AndBitWidth) {
15093 DAG.computeKnownBits(Op0, Zeros, Ones);
15094 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15098 RHS = Op0.getOperand(1);
15100 } else if (Op1.getOpcode() == ISD::Constant) {
15101 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15102 uint64_t AndRHSVal = AndRHS->getZExtValue();
15103 SDValue AndLHS = Op0;
15105 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15106 LHS = AndLHS.getOperand(0);
15107 RHS = AndLHS.getOperand(1);
15110 // Use BT if the immediate can't be encoded in a TEST instruction.
15111 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15113 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15117 if (LHS.getNode()) {
15118 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15119 // instruction. Since the shift amount is in-range-or-undefined, we know
15120 // that doing a bittest on the i32 value is ok. We extend to i32 because
15121 // the encoding for the i16 version is larger than the i32 version.
15122 // Also promote i16 to i32 for performance / code size reason.
15123 if (LHS.getValueType() == MVT::i8 ||
15124 LHS.getValueType() == MVT::i16)
15125 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15127 // If the operand types disagree, extend the shift amount to match. Since
15128 // BT ignores high bits (like shifts) we can use anyextend.
15129 if (LHS.getValueType() != RHS.getValueType())
15130 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15132 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15133 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15134 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15135 DAG.getConstant(Cond, MVT::i8), BT);
15141 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15143 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15148 // SSE Condition code mapping:
15157 switch (SetCCOpcode) {
15158 default: llvm_unreachable("Unexpected SETCC condition");
15160 case ISD::SETEQ: SSECC = 0; break;
15162 case ISD::SETGT: Swap = true; // Fallthrough
15164 case ISD::SETOLT: SSECC = 1; break;
15166 case ISD::SETGE: Swap = true; // Fallthrough
15168 case ISD::SETOLE: SSECC = 2; break;
15169 case ISD::SETUO: SSECC = 3; break;
15171 case ISD::SETNE: SSECC = 4; break;
15172 case ISD::SETULE: Swap = true; // Fallthrough
15173 case ISD::SETUGE: SSECC = 5; break;
15174 case ISD::SETULT: Swap = true; // Fallthrough
15175 case ISD::SETUGT: SSECC = 6; break;
15176 case ISD::SETO: SSECC = 7; break;
15178 case ISD::SETONE: SSECC = 8; break;
15181 std::swap(Op0, Op1);
15186 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15187 // ones, and then concatenate the result back.
15188 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15189 MVT VT = Op.getSimpleValueType();
15191 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15192 "Unsupported value type for operation");
15194 unsigned NumElems = VT.getVectorNumElements();
15196 SDValue CC = Op.getOperand(2);
15198 // Extract the LHS vectors
15199 SDValue LHS = Op.getOperand(0);
15200 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15201 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15203 // Extract the RHS vectors
15204 SDValue RHS = Op.getOperand(1);
15205 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15206 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15208 // Issue the operation on the smaller types and concatenate the result back
15209 MVT EltVT = VT.getVectorElementType();
15210 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15211 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15212 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15213 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15216 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15217 const X86Subtarget *Subtarget) {
15218 SDValue Op0 = Op.getOperand(0);
15219 SDValue Op1 = Op.getOperand(1);
15220 SDValue CC = Op.getOperand(2);
15221 MVT VT = Op.getSimpleValueType();
15224 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15225 Op.getValueType().getScalarType() == MVT::i1 &&
15226 "Cannot set masked compare for this operation");
15228 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15230 bool Unsigned = false;
15233 switch (SetCCOpcode) {
15234 default: llvm_unreachable("Unexpected SETCC condition");
15235 case ISD::SETNE: SSECC = 4; break;
15236 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15237 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15238 case ISD::SETLT: Swap = true; //fall-through
15239 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15240 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15241 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15242 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15243 case ISD::SETULE: Unsigned = true; //fall-through
15244 case ISD::SETLE: SSECC = 2; break;
15248 std::swap(Op0, Op1);
15250 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15251 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15252 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15253 DAG.getConstant(SSECC, MVT::i8));
15256 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15257 /// operand \p Op1. If non-trivial (for example because it's not constant)
15258 /// return an empty value.
15259 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15261 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15265 MVT VT = Op1.getSimpleValueType();
15266 MVT EVT = VT.getVectorElementType();
15267 unsigned n = VT.getVectorNumElements();
15268 SmallVector<SDValue, 8> ULTOp1;
15270 for (unsigned i = 0; i < n; ++i) {
15271 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15272 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15275 // Avoid underflow.
15276 APInt Val = Elt->getAPIntValue();
15280 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15283 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15286 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15287 SelectionDAG &DAG) {
15288 SDValue Op0 = Op.getOperand(0);
15289 SDValue Op1 = Op.getOperand(1);
15290 SDValue CC = Op.getOperand(2);
15291 MVT VT = Op.getSimpleValueType();
15292 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15293 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15298 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15299 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15302 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15303 unsigned Opc = X86ISD::CMPP;
15304 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15305 assert(VT.getVectorNumElements() <= 16);
15306 Opc = X86ISD::CMPM;
15308 // In the two special cases we can't handle, emit two comparisons.
15311 unsigned CombineOpc;
15312 if (SetCCOpcode == ISD::SETUEQ) {
15313 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15315 assert(SetCCOpcode == ISD::SETONE);
15316 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15319 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15320 DAG.getConstant(CC0, MVT::i8));
15321 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15322 DAG.getConstant(CC1, MVT::i8));
15323 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15325 // Handle all other FP comparisons here.
15326 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15327 DAG.getConstant(SSECC, MVT::i8));
15330 // Break 256-bit integer vector compare into smaller ones.
15331 if (VT.is256BitVector() && !Subtarget->hasInt256())
15332 return Lower256IntVSETCC(Op, DAG);
15334 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15335 EVT OpVT = Op1.getValueType();
15336 if (Subtarget->hasAVX512()) {
15337 if (Op1.getValueType().is512BitVector() ||
15338 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15339 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15340 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15342 // In AVX-512 architecture setcc returns mask with i1 elements,
15343 // But there is no compare instruction for i8 and i16 elements in KNL.
15344 // We are not talking about 512-bit operands in this case, these
15345 // types are illegal.
15347 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15348 OpVT.getVectorElementType().getSizeInBits() >= 8))
15349 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15350 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15353 // We are handling one of the integer comparisons here. Since SSE only has
15354 // GT and EQ comparisons for integer, swapping operands and multiple
15355 // operations may be required for some comparisons.
15357 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15358 bool Subus = false;
15360 switch (SetCCOpcode) {
15361 default: llvm_unreachable("Unexpected SETCC condition");
15362 case ISD::SETNE: Invert = true;
15363 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15364 case ISD::SETLT: Swap = true;
15365 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15366 case ISD::SETGE: Swap = true;
15367 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15368 Invert = true; break;
15369 case ISD::SETULT: Swap = true;
15370 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15371 FlipSigns = true; break;
15372 case ISD::SETUGE: Swap = true;
15373 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15374 FlipSigns = true; Invert = true; break;
15377 // Special case: Use min/max operations for SETULE/SETUGE
15378 MVT VET = VT.getVectorElementType();
15380 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15381 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15384 switch (SetCCOpcode) {
15386 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15387 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15390 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15393 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15394 if (!MinMax && hasSubus) {
15395 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15397 // t = psubus Op0, Op1
15398 // pcmpeq t, <0..0>
15399 switch (SetCCOpcode) {
15401 case ISD::SETULT: {
15402 // If the comparison is against a constant we can turn this into a
15403 // setule. With psubus, setule does not require a swap. This is
15404 // beneficial because the constant in the register is no longer
15405 // destructed as the destination so it can be hoisted out of a loop.
15406 // Only do this pre-AVX since vpcmp* is no longer destructive.
15407 if (Subtarget->hasAVX())
15409 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15410 if (ULEOp1.getNode()) {
15412 Subus = true; Invert = false; Swap = false;
15416 // Psubus is better than flip-sign because it requires no inversion.
15417 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15418 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15422 Opc = X86ISD::SUBUS;
15428 std::swap(Op0, Op1);
15430 // Check that the operation in question is available (most are plain SSE2,
15431 // but PCMPGTQ and PCMPEQQ have different requirements).
15432 if (VT == MVT::v2i64) {
15433 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15434 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15436 // First cast everything to the right type.
15437 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15438 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15440 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15441 // bits of the inputs before performing those operations. The lower
15442 // compare is always unsigned.
15445 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15447 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15448 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15449 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15450 Sign, Zero, Sign, Zero);
15452 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15453 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15455 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15456 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15457 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15459 // Create masks for only the low parts/high parts of the 64 bit integers.
15460 static const int MaskHi[] = { 1, 1, 3, 3 };
15461 static const int MaskLo[] = { 0, 0, 2, 2 };
15462 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15463 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15464 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15466 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15467 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15470 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15472 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15475 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15476 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15477 // pcmpeqd + pshufd + pand.
15478 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15480 // First cast everything to the right type.
15481 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15482 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15485 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15487 // Make sure the lower and upper halves are both all-ones.
15488 static const int Mask[] = { 1, 0, 3, 2 };
15489 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15490 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15493 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15495 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15499 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15500 // bits of the inputs before performing those operations.
15502 EVT EltVT = VT.getVectorElementType();
15503 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15504 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15505 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15508 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15510 // If the logical-not of the result is required, perform that now.
15512 Result = DAG.getNOT(dl, Result, VT);
15515 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15518 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15519 getZeroVector(VT, Subtarget, DAG, dl));
15524 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15526 MVT VT = Op.getSimpleValueType();
15528 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15530 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15531 && "SetCC type must be 8-bit or 1-bit integer");
15532 SDValue Op0 = Op.getOperand(0);
15533 SDValue Op1 = Op.getOperand(1);
15535 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15537 // Optimize to BT if possible.
15538 // Lower (X & (1 << N)) == 0 to BT(X, N).
15539 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15540 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15541 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15542 Op1.getOpcode() == ISD::Constant &&
15543 cast<ConstantSDNode>(Op1)->isNullValue() &&
15544 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15545 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15546 if (NewSetCC.getNode()) {
15548 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15553 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15555 if (Op1.getOpcode() == ISD::Constant &&
15556 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15557 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15558 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15560 // If the input is a setcc, then reuse the input setcc or use a new one with
15561 // the inverted condition.
15562 if (Op0.getOpcode() == X86ISD::SETCC) {
15563 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15564 bool Invert = (CC == ISD::SETNE) ^
15565 cast<ConstantSDNode>(Op1)->isNullValue();
15569 CCode = X86::GetOppositeBranchCondition(CCode);
15570 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15571 DAG.getConstant(CCode, MVT::i8),
15572 Op0.getOperand(1));
15574 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15578 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15579 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15580 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15582 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15583 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15586 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15587 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15588 if (X86CC == X86::COND_INVALID)
15591 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15592 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15593 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15594 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15596 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15600 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15601 static bool isX86LogicalCmp(SDValue Op) {
15602 unsigned Opc = Op.getNode()->getOpcode();
15603 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15604 Opc == X86ISD::SAHF)
15606 if (Op.getResNo() == 1 &&
15607 (Opc == X86ISD::ADD ||
15608 Opc == X86ISD::SUB ||
15609 Opc == X86ISD::ADC ||
15610 Opc == X86ISD::SBB ||
15611 Opc == X86ISD::SMUL ||
15612 Opc == X86ISD::UMUL ||
15613 Opc == X86ISD::INC ||
15614 Opc == X86ISD::DEC ||
15615 Opc == X86ISD::OR ||
15616 Opc == X86ISD::XOR ||
15617 Opc == X86ISD::AND))
15620 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15626 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15627 if (V.getOpcode() != ISD::TRUNCATE)
15630 SDValue VOp0 = V.getOperand(0);
15631 unsigned InBits = VOp0.getValueSizeInBits();
15632 unsigned Bits = V.getValueSizeInBits();
15633 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15636 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15637 bool addTest = true;
15638 SDValue Cond = Op.getOperand(0);
15639 SDValue Op1 = Op.getOperand(1);
15640 SDValue Op2 = Op.getOperand(2);
15642 EVT VT = Op1.getValueType();
15645 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15646 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15647 // sequence later on.
15648 if (Cond.getOpcode() == ISD::SETCC &&
15649 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15650 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15651 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15652 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15653 int SSECC = translateX86FSETCC(
15654 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15657 if (Subtarget->hasAVX512()) {
15658 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15659 DAG.getConstant(SSECC, MVT::i8));
15660 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15662 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15663 DAG.getConstant(SSECC, MVT::i8));
15664 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15665 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15666 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15670 if (Cond.getOpcode() == ISD::SETCC) {
15671 SDValue NewCond = LowerSETCC(Cond, DAG);
15672 if (NewCond.getNode())
15676 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15677 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15678 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15679 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15680 if (Cond.getOpcode() == X86ISD::SETCC &&
15681 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15682 isZero(Cond.getOperand(1).getOperand(1))) {
15683 SDValue Cmp = Cond.getOperand(1);
15685 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15687 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15688 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15689 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15691 SDValue CmpOp0 = Cmp.getOperand(0);
15692 // Apply further optimizations for special cases
15693 // (select (x != 0), -1, 0) -> neg & sbb
15694 // (select (x == 0), 0, -1) -> neg & sbb
15695 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15696 if (YC->isNullValue() &&
15697 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15698 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15699 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15700 DAG.getConstant(0, CmpOp0.getValueType()),
15702 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15703 DAG.getConstant(X86::COND_B, MVT::i8),
15704 SDValue(Neg.getNode(), 1));
15708 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15709 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15710 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15712 SDValue Res = // Res = 0 or -1.
15713 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15714 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15716 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15717 Res = DAG.getNOT(DL, Res, Res.getValueType());
15719 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15720 if (!N2C || !N2C->isNullValue())
15721 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15726 // Look past (and (setcc_carry (cmp ...)), 1).
15727 if (Cond.getOpcode() == ISD::AND &&
15728 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15729 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15730 if (C && C->getAPIntValue() == 1)
15731 Cond = Cond.getOperand(0);
15734 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15735 // setting operand in place of the X86ISD::SETCC.
15736 unsigned CondOpcode = Cond.getOpcode();
15737 if (CondOpcode == X86ISD::SETCC ||
15738 CondOpcode == X86ISD::SETCC_CARRY) {
15739 CC = Cond.getOperand(0);
15741 SDValue Cmp = Cond.getOperand(1);
15742 unsigned Opc = Cmp.getOpcode();
15743 MVT VT = Op.getSimpleValueType();
15745 bool IllegalFPCMov = false;
15746 if (VT.isFloatingPoint() && !VT.isVector() &&
15747 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15748 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15750 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15751 Opc == X86ISD::BT) { // FIXME
15755 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15756 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15757 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15758 Cond.getOperand(0).getValueType() != MVT::i8)) {
15759 SDValue LHS = Cond.getOperand(0);
15760 SDValue RHS = Cond.getOperand(1);
15761 unsigned X86Opcode;
15764 switch (CondOpcode) {
15765 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15766 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15767 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15768 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15769 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15770 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15771 default: llvm_unreachable("unexpected overflowing operator");
15773 if (CondOpcode == ISD::UMULO)
15774 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15777 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15779 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15781 if (CondOpcode == ISD::UMULO)
15782 Cond = X86Op.getValue(2);
15784 Cond = X86Op.getValue(1);
15786 CC = DAG.getConstant(X86Cond, MVT::i8);
15791 // Look pass the truncate if the high bits are known zero.
15792 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15793 Cond = Cond.getOperand(0);
15795 // We know the result of AND is compared against zero. Try to match
15797 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15798 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15799 if (NewSetCC.getNode()) {
15800 CC = NewSetCC.getOperand(0);
15801 Cond = NewSetCC.getOperand(1);
15808 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15809 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15812 // a < b ? -1 : 0 -> RES = ~setcc_carry
15813 // a < b ? 0 : -1 -> RES = setcc_carry
15814 // a >= b ? -1 : 0 -> RES = setcc_carry
15815 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15816 if (Cond.getOpcode() == X86ISD::SUB) {
15817 Cond = ConvertCmpIfNecessary(Cond, DAG);
15818 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15820 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15821 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15822 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15823 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15824 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15825 return DAG.getNOT(DL, Res, Res.getValueType());
15830 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15831 // widen the cmov and push the truncate through. This avoids introducing a new
15832 // branch during isel and doesn't add any extensions.
15833 if (Op.getValueType() == MVT::i8 &&
15834 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15835 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15836 if (T1.getValueType() == T2.getValueType() &&
15837 // Blacklist CopyFromReg to avoid partial register stalls.
15838 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15839 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15840 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15841 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15845 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15846 // condition is true.
15847 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15848 SDValue Ops[] = { Op2, Op1, CC, Cond };
15849 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15852 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15853 SelectionDAG &DAG) {
15854 MVT VT = Op->getSimpleValueType(0);
15855 SDValue In = Op->getOperand(0);
15856 MVT InVT = In.getSimpleValueType();
15857 MVT VTElt = VT.getVectorElementType();
15858 MVT InVTElt = InVT.getVectorElementType();
15862 if ((InVTElt == MVT::i1) &&
15863 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15864 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15866 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15867 VTElt.getSizeInBits() <= 16)) ||
15869 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15870 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15872 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15873 VTElt.getSizeInBits() >= 32))))
15874 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15876 unsigned int NumElts = VT.getVectorNumElements();
15878 if (NumElts != 8 && NumElts != 16)
15881 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15882 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15883 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15884 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15888 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15890 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15891 Constant *C = ConstantInt::get(*DAG.getContext(),
15892 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15894 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15895 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15896 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15897 MachinePointerInfo::getConstantPool(),
15898 false, false, false, Alignment);
15899 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15900 if (VT.is512BitVector())
15902 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15905 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15906 SelectionDAG &DAG) {
15907 MVT VT = Op->getSimpleValueType(0);
15908 SDValue In = Op->getOperand(0);
15909 MVT InVT = In.getSimpleValueType();
15912 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15913 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15915 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15916 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15917 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15920 if (Subtarget->hasInt256())
15921 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15923 // Optimize vectors in AVX mode
15924 // Sign extend v8i16 to v8i32 and
15927 // Divide input vector into two parts
15928 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15929 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15930 // concat the vectors to original VT
15932 unsigned NumElems = InVT.getVectorNumElements();
15933 SDValue Undef = DAG.getUNDEF(InVT);
15935 SmallVector<int,8> ShufMask1(NumElems, -1);
15936 for (unsigned i = 0; i != NumElems/2; ++i)
15939 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15941 SmallVector<int,8> ShufMask2(NumElems, -1);
15942 for (unsigned i = 0; i != NumElems/2; ++i)
15943 ShufMask2[i] = i + NumElems/2;
15945 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15947 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15948 VT.getVectorNumElements()/2);
15950 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15951 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15953 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15956 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15957 // may emit an illegal shuffle but the expansion is still better than scalar
15958 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15959 // we'll emit a shuffle and a arithmetic shift.
15960 // TODO: It is possible to support ZExt by zeroing the undef values during
15961 // the shuffle phase or after the shuffle.
15962 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15963 SelectionDAG &DAG) {
15964 MVT RegVT = Op.getSimpleValueType();
15965 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15966 assert(RegVT.isInteger() &&
15967 "We only custom lower integer vector sext loads.");
15969 // Nothing useful we can do without SSE2 shuffles.
15970 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15972 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15974 EVT MemVT = Ld->getMemoryVT();
15975 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15976 unsigned RegSz = RegVT.getSizeInBits();
15978 ISD::LoadExtType Ext = Ld->getExtensionType();
15980 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15981 && "Only anyext and sext are currently implemented.");
15982 assert(MemVT != RegVT && "Cannot extend to the same type");
15983 assert(MemVT.isVector() && "Must load a vector from memory");
15985 unsigned NumElems = RegVT.getVectorNumElements();
15986 unsigned MemSz = MemVT.getSizeInBits();
15987 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15989 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15990 // The only way in which we have a legal 256-bit vector result but not the
15991 // integer 256-bit operations needed to directly lower a sextload is if we
15992 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15993 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15994 // correctly legalized. We do this late to allow the canonical form of
15995 // sextload to persist throughout the rest of the DAG combiner -- it wants
15996 // to fold together any extensions it can, and so will fuse a sign_extend
15997 // of an sextload into a sextload targeting a wider value.
15999 if (MemSz == 128) {
16000 // Just switch this to a normal load.
16001 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
16002 "it must be a legal 128-bit vector "
16004 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
16005 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
16006 Ld->isInvariant(), Ld->getAlignment());
16008 assert(MemSz < 128 &&
16009 "Can't extend a type wider than 128 bits to a 256 bit vector!");
16010 // Do an sext load to a 128-bit vector type. We want to use the same
16011 // number of elements, but elements half as wide. This will end up being
16012 // recursively lowered by this routine, but will succeed as we definitely
16013 // have all the necessary features if we're using AVX1.
16015 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
16016 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
16018 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
16019 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
16020 Ld->isNonTemporal(), Ld->isInvariant(),
16021 Ld->getAlignment());
16024 // Replace chain users with the new chain.
16025 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
16026 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
16028 // Finally, do a normal sign-extend to the desired register.
16029 return DAG.getSExtOrTrunc(Load, dl, RegVT);
16032 // All sizes must be a power of two.
16033 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
16034 "Non-power-of-two elements are not custom lowered!");
16036 // Attempt to load the original value using scalar loads.
16037 // Find the largest scalar type that divides the total loaded size.
16038 MVT SclrLoadTy = MVT::i8;
16039 for (MVT Tp : MVT::integer_valuetypes()) {
16040 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16045 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16046 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16048 SclrLoadTy = MVT::f64;
16050 // Calculate the number of scalar loads that we need to perform
16051 // in order to load our vector from memory.
16052 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16054 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16055 "Can only lower sext loads with a single scalar load!");
16057 unsigned loadRegZize = RegSz;
16058 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16061 // Represent our vector as a sequence of elements which are the
16062 // largest scalar that we can load.
16063 EVT LoadUnitVecVT = EVT::getVectorVT(
16064 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16066 // Represent the data using the same element type that is stored in
16067 // memory. In practice, we ''widen'' MemVT.
16069 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16070 loadRegZize / MemVT.getScalarType().getSizeInBits());
16072 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16073 "Invalid vector type");
16075 // We can't shuffle using an illegal type.
16076 assert(TLI.isTypeLegal(WideVecVT) &&
16077 "We only lower types that form legal widened vector types");
16079 SmallVector<SDValue, 8> Chains;
16080 SDValue Ptr = Ld->getBasePtr();
16081 SDValue Increment =
16082 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16083 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16085 for (unsigned i = 0; i < NumLoads; ++i) {
16086 // Perform a single load.
16087 SDValue ScalarLoad =
16088 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16089 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16090 Ld->getAlignment());
16091 Chains.push_back(ScalarLoad.getValue(1));
16092 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16093 // another round of DAGCombining.
16095 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16097 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16098 ScalarLoad, DAG.getIntPtrConstant(i));
16100 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16103 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16105 // Bitcast the loaded value to a vector of the original element type, in
16106 // the size of the target vector type.
16107 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16108 unsigned SizeRatio = RegSz / MemSz;
16110 if (Ext == ISD::SEXTLOAD) {
16111 // If we have SSE4.1, we can directly emit a VSEXT node.
16112 if (Subtarget->hasSSE41()) {
16113 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16114 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16118 // Otherwise we'll shuffle the small elements in the high bits of the
16119 // larger type and perform an arithmetic shift. If the shift is not legal
16120 // it's better to scalarize.
16121 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16122 "We can't implement a sext load without an arithmetic right shift!");
16124 // Redistribute the loaded elements into the different locations.
16125 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16126 for (unsigned i = 0; i != NumElems; ++i)
16127 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16129 SDValue Shuff = DAG.getVectorShuffle(
16130 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16132 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16134 // Build the arithmetic shift.
16135 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16136 MemVT.getVectorElementType().getSizeInBits();
16138 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16140 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16144 // Redistribute the loaded elements into the different locations.
16145 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16146 for (unsigned i = 0; i != NumElems; ++i)
16147 ShuffleVec[i * SizeRatio] = i;
16149 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16150 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16152 // Bitcast to the requested type.
16153 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16154 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16158 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16159 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16160 // from the AND / OR.
16161 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16162 Opc = Op.getOpcode();
16163 if (Opc != ISD::OR && Opc != ISD::AND)
16165 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16166 Op.getOperand(0).hasOneUse() &&
16167 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16168 Op.getOperand(1).hasOneUse());
16171 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16172 // 1 and that the SETCC node has a single use.
16173 static bool isXor1OfSetCC(SDValue Op) {
16174 if (Op.getOpcode() != ISD::XOR)
16176 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16177 if (N1C && N1C->getAPIntValue() == 1) {
16178 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16179 Op.getOperand(0).hasOneUse();
16184 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16185 bool addTest = true;
16186 SDValue Chain = Op.getOperand(0);
16187 SDValue Cond = Op.getOperand(1);
16188 SDValue Dest = Op.getOperand(2);
16191 bool Inverted = false;
16193 if (Cond.getOpcode() == ISD::SETCC) {
16194 // Check for setcc([su]{add,sub,mul}o == 0).
16195 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16196 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16197 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16198 Cond.getOperand(0).getResNo() == 1 &&
16199 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16200 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16201 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16202 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16203 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16204 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16206 Cond = Cond.getOperand(0);
16208 SDValue NewCond = LowerSETCC(Cond, DAG);
16209 if (NewCond.getNode())
16214 // FIXME: LowerXALUO doesn't handle these!!
16215 else if (Cond.getOpcode() == X86ISD::ADD ||
16216 Cond.getOpcode() == X86ISD::SUB ||
16217 Cond.getOpcode() == X86ISD::SMUL ||
16218 Cond.getOpcode() == X86ISD::UMUL)
16219 Cond = LowerXALUO(Cond, DAG);
16222 // Look pass (and (setcc_carry (cmp ...)), 1).
16223 if (Cond.getOpcode() == ISD::AND &&
16224 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16225 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16226 if (C && C->getAPIntValue() == 1)
16227 Cond = Cond.getOperand(0);
16230 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16231 // setting operand in place of the X86ISD::SETCC.
16232 unsigned CondOpcode = Cond.getOpcode();
16233 if (CondOpcode == X86ISD::SETCC ||
16234 CondOpcode == X86ISD::SETCC_CARRY) {
16235 CC = Cond.getOperand(0);
16237 SDValue Cmp = Cond.getOperand(1);
16238 unsigned Opc = Cmp.getOpcode();
16239 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16240 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16244 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16248 // These can only come from an arithmetic instruction with overflow,
16249 // e.g. SADDO, UADDO.
16250 Cond = Cond.getNode()->getOperand(1);
16256 CondOpcode = Cond.getOpcode();
16257 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16258 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16259 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16260 Cond.getOperand(0).getValueType() != MVT::i8)) {
16261 SDValue LHS = Cond.getOperand(0);
16262 SDValue RHS = Cond.getOperand(1);
16263 unsigned X86Opcode;
16266 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16267 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16269 switch (CondOpcode) {
16270 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16272 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16274 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16277 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16278 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16280 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16282 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16285 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16286 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16287 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16288 default: llvm_unreachable("unexpected overflowing operator");
16291 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16292 if (CondOpcode == ISD::UMULO)
16293 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16296 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16298 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16300 if (CondOpcode == ISD::UMULO)
16301 Cond = X86Op.getValue(2);
16303 Cond = X86Op.getValue(1);
16305 CC = DAG.getConstant(X86Cond, MVT::i8);
16309 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16310 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16311 if (CondOpc == ISD::OR) {
16312 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16313 // two branches instead of an explicit OR instruction with a
16315 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16316 isX86LogicalCmp(Cmp)) {
16317 CC = Cond.getOperand(0).getOperand(0);
16318 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16319 Chain, Dest, CC, Cmp);
16320 CC = Cond.getOperand(1).getOperand(0);
16324 } else { // ISD::AND
16325 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16326 // two branches instead of an explicit AND instruction with a
16327 // separate test. However, we only do this if this block doesn't
16328 // have a fall-through edge, because this requires an explicit
16329 // jmp when the condition is false.
16330 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16331 isX86LogicalCmp(Cmp) &&
16332 Op.getNode()->hasOneUse()) {
16333 X86::CondCode CCode =
16334 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16335 CCode = X86::GetOppositeBranchCondition(CCode);
16336 CC = DAG.getConstant(CCode, MVT::i8);
16337 SDNode *User = *Op.getNode()->use_begin();
16338 // Look for an unconditional branch following this conditional branch.
16339 // We need this because we need to reverse the successors in order
16340 // to implement FCMP_OEQ.
16341 if (User->getOpcode() == ISD::BR) {
16342 SDValue FalseBB = User->getOperand(1);
16344 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16345 assert(NewBR == User);
16349 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16350 Chain, Dest, CC, Cmp);
16351 X86::CondCode CCode =
16352 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16353 CCode = X86::GetOppositeBranchCondition(CCode);
16354 CC = DAG.getConstant(CCode, MVT::i8);
16360 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16361 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16362 // It should be transformed during dag combiner except when the condition
16363 // is set by a arithmetics with overflow node.
16364 X86::CondCode CCode =
16365 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16366 CCode = X86::GetOppositeBranchCondition(CCode);
16367 CC = DAG.getConstant(CCode, MVT::i8);
16368 Cond = Cond.getOperand(0).getOperand(1);
16370 } else if (Cond.getOpcode() == ISD::SETCC &&
16371 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16372 // For FCMP_OEQ, we can emit
16373 // two branches instead of an explicit AND instruction with a
16374 // separate test. However, we only do this if this block doesn't
16375 // have a fall-through edge, because this requires an explicit
16376 // jmp when the condition is false.
16377 if (Op.getNode()->hasOneUse()) {
16378 SDNode *User = *Op.getNode()->use_begin();
16379 // Look for an unconditional branch following this conditional branch.
16380 // We need this because we need to reverse the successors in order
16381 // to implement FCMP_OEQ.
16382 if (User->getOpcode() == ISD::BR) {
16383 SDValue FalseBB = User->getOperand(1);
16385 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16386 assert(NewBR == User);
16390 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16391 Cond.getOperand(0), Cond.getOperand(1));
16392 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16393 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16394 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16395 Chain, Dest, CC, Cmp);
16396 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16401 } else if (Cond.getOpcode() == ISD::SETCC &&
16402 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16403 // For FCMP_UNE, we can emit
16404 // two branches instead of an explicit AND instruction with a
16405 // separate test. However, we only do this if this block doesn't
16406 // have a fall-through edge, because this requires an explicit
16407 // jmp when the condition is false.
16408 if (Op.getNode()->hasOneUse()) {
16409 SDNode *User = *Op.getNode()->use_begin();
16410 // Look for an unconditional branch following this conditional branch.
16411 // We need this because we need to reverse the successors in order
16412 // to implement FCMP_UNE.
16413 if (User->getOpcode() == ISD::BR) {
16414 SDValue FalseBB = User->getOperand(1);
16416 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16417 assert(NewBR == User);
16420 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16421 Cond.getOperand(0), Cond.getOperand(1));
16422 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16423 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16424 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16425 Chain, Dest, CC, Cmp);
16426 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16436 // Look pass the truncate if the high bits are known zero.
16437 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16438 Cond = Cond.getOperand(0);
16440 // We know the result of AND is compared against zero. Try to match
16442 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16443 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16444 if (NewSetCC.getNode()) {
16445 CC = NewSetCC.getOperand(0);
16446 Cond = NewSetCC.getOperand(1);
16453 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16454 CC = DAG.getConstant(X86Cond, MVT::i8);
16455 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16457 Cond = ConvertCmpIfNecessary(Cond, DAG);
16458 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16459 Chain, Dest, CC, Cond);
16462 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16463 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16464 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16465 // that the guard pages used by the OS virtual memory manager are allocated in
16466 // correct sequence.
16468 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16469 SelectionDAG &DAG) const {
16470 MachineFunction &MF = DAG.getMachineFunction();
16471 bool SplitStack = MF.shouldSplitStack();
16472 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16477 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16478 SDNode* Node = Op.getNode();
16480 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16481 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16482 " not tell us which reg is the stack pointer!");
16483 EVT VT = Node->getValueType(0);
16484 SDValue Tmp1 = SDValue(Node, 0);
16485 SDValue Tmp2 = SDValue(Node, 1);
16486 SDValue Tmp3 = Node->getOperand(2);
16487 SDValue Chain = Tmp1.getOperand(0);
16489 // Chain the dynamic stack allocation so that it doesn't modify the stack
16490 // pointer when other instructions are using the stack.
16491 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16494 SDValue Size = Tmp2.getOperand(1);
16495 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16496 Chain = SP.getValue(1);
16497 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16498 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16499 unsigned StackAlign = TFI.getStackAlignment();
16500 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16501 if (Align > StackAlign)
16502 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16503 DAG.getConstant(-(uint64_t)Align, VT));
16504 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16506 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16507 DAG.getIntPtrConstant(0, true), SDValue(),
16510 SDValue Ops[2] = { Tmp1, Tmp2 };
16511 return DAG.getMergeValues(Ops, dl);
16515 SDValue Chain = Op.getOperand(0);
16516 SDValue Size = Op.getOperand(1);
16517 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16518 EVT VT = Op.getNode()->getValueType(0);
16520 bool Is64Bit = Subtarget->is64Bit();
16521 EVT SPTy = getPointerTy();
16524 MachineRegisterInfo &MRI = MF.getRegInfo();
16527 // The 64 bit implementation of segmented stacks needs to clobber both r10
16528 // r11. This makes it impossible to use it along with nested parameters.
16529 const Function *F = MF.getFunction();
16531 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16533 if (I->hasNestAttr())
16534 report_fatal_error("Cannot use segmented stacks with functions that "
16535 "have nested arguments.");
16538 const TargetRegisterClass *AddrRegClass =
16539 getRegClassFor(getPointerTy());
16540 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16541 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16542 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16543 DAG.getRegister(Vreg, SPTy));
16544 SDValue Ops1[2] = { Value, Chain };
16545 return DAG.getMergeValues(Ops1, dl);
16548 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16550 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16551 Flag = Chain.getValue(1);
16552 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16554 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16556 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16557 DAG.getSubtarget().getRegisterInfo());
16558 unsigned SPReg = RegInfo->getStackRegister();
16559 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16560 Chain = SP.getValue(1);
16563 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16564 DAG.getConstant(-(uint64_t)Align, VT));
16565 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16568 SDValue Ops1[2] = { SP, Chain };
16569 return DAG.getMergeValues(Ops1, dl);
16573 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16574 MachineFunction &MF = DAG.getMachineFunction();
16575 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16577 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16580 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16581 // vastart just stores the address of the VarArgsFrameIndex slot into the
16582 // memory location argument.
16583 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16585 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16586 MachinePointerInfo(SV), false, false, 0);
16590 // gp_offset (0 - 6 * 8)
16591 // fp_offset (48 - 48 + 8 * 16)
16592 // overflow_arg_area (point to parameters coming in memory).
16594 SmallVector<SDValue, 8> MemOps;
16595 SDValue FIN = Op.getOperand(1);
16597 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16598 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16600 FIN, MachinePointerInfo(SV), false, false, 0);
16601 MemOps.push_back(Store);
16604 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16605 FIN, DAG.getIntPtrConstant(4));
16606 Store = DAG.getStore(Op.getOperand(0), DL,
16607 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16609 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16610 MemOps.push_back(Store);
16612 // Store ptr to overflow_arg_area
16613 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16614 FIN, DAG.getIntPtrConstant(4));
16615 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16617 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16618 MachinePointerInfo(SV, 8),
16620 MemOps.push_back(Store);
16622 // Store ptr to reg_save_area.
16623 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16624 FIN, DAG.getIntPtrConstant(8));
16625 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16627 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16628 MachinePointerInfo(SV, 16), false, false, 0);
16629 MemOps.push_back(Store);
16630 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16633 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16634 assert(Subtarget->is64Bit() &&
16635 "LowerVAARG only handles 64-bit va_arg!");
16636 assert((Subtarget->isTargetLinux() ||
16637 Subtarget->isTargetDarwin()) &&
16638 "Unhandled target in LowerVAARG");
16639 assert(Op.getNode()->getNumOperands() == 4);
16640 SDValue Chain = Op.getOperand(0);
16641 SDValue SrcPtr = Op.getOperand(1);
16642 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16643 unsigned Align = Op.getConstantOperandVal(3);
16646 EVT ArgVT = Op.getNode()->getValueType(0);
16647 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16648 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16651 // Decide which area this value should be read from.
16652 // TODO: Implement the AMD64 ABI in its entirety. This simple
16653 // selection mechanism works only for the basic types.
16654 if (ArgVT == MVT::f80) {
16655 llvm_unreachable("va_arg for f80 not yet implemented");
16656 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16657 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16658 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16659 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16661 llvm_unreachable("Unhandled argument type in LowerVAARG");
16664 if (ArgMode == 2) {
16665 // Sanity Check: Make sure using fp_offset makes sense.
16666 assert(!DAG.getTarget().Options.UseSoftFloat &&
16667 !(DAG.getMachineFunction()
16668 .getFunction()->getAttributes()
16669 .hasAttribute(AttributeSet::FunctionIndex,
16670 Attribute::NoImplicitFloat)) &&
16671 Subtarget->hasSSE1());
16674 // Insert VAARG_64 node into the DAG
16675 // VAARG_64 returns two values: Variable Argument Address, Chain
16676 SmallVector<SDValue, 11> InstOps;
16677 InstOps.push_back(Chain);
16678 InstOps.push_back(SrcPtr);
16679 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16680 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16681 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16682 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16683 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16684 VTs, InstOps, MVT::i64,
16685 MachinePointerInfo(SV),
16687 /*Volatile=*/false,
16689 /*WriteMem=*/true);
16690 Chain = VAARG.getValue(1);
16692 // Load the next argument and return it
16693 return DAG.getLoad(ArgVT, dl,
16696 MachinePointerInfo(),
16697 false, false, false, 0);
16700 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16701 SelectionDAG &DAG) {
16702 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16703 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16704 SDValue Chain = Op.getOperand(0);
16705 SDValue DstPtr = Op.getOperand(1);
16706 SDValue SrcPtr = Op.getOperand(2);
16707 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16708 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16711 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16712 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16714 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16717 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16718 // amount is a constant. Takes immediate version of shift as input.
16719 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16720 SDValue SrcOp, uint64_t ShiftAmt,
16721 SelectionDAG &DAG) {
16722 MVT ElementType = VT.getVectorElementType();
16724 // Fold this packed shift into its first operand if ShiftAmt is 0.
16728 // Check for ShiftAmt >= element width
16729 if (ShiftAmt >= ElementType.getSizeInBits()) {
16730 if (Opc == X86ISD::VSRAI)
16731 ShiftAmt = ElementType.getSizeInBits() - 1;
16733 return DAG.getConstant(0, VT);
16736 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16737 && "Unknown target vector shift-by-constant node");
16739 // Fold this packed vector shift into a build vector if SrcOp is a
16740 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16741 if (VT == SrcOp.getSimpleValueType() &&
16742 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16743 SmallVector<SDValue, 8> Elts;
16744 unsigned NumElts = SrcOp->getNumOperands();
16745 ConstantSDNode *ND;
16748 default: llvm_unreachable(nullptr);
16749 case X86ISD::VSHLI:
16750 for (unsigned i=0; i!=NumElts; ++i) {
16751 SDValue CurrentOp = SrcOp->getOperand(i);
16752 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16753 Elts.push_back(CurrentOp);
16756 ND = cast<ConstantSDNode>(CurrentOp);
16757 const APInt &C = ND->getAPIntValue();
16758 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16761 case X86ISD::VSRLI:
16762 for (unsigned i=0; i!=NumElts; ++i) {
16763 SDValue CurrentOp = SrcOp->getOperand(i);
16764 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16765 Elts.push_back(CurrentOp);
16768 ND = cast<ConstantSDNode>(CurrentOp);
16769 const APInt &C = ND->getAPIntValue();
16770 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16773 case X86ISD::VSRAI:
16774 for (unsigned i=0; i!=NumElts; ++i) {
16775 SDValue CurrentOp = SrcOp->getOperand(i);
16776 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16777 Elts.push_back(CurrentOp);
16780 ND = cast<ConstantSDNode>(CurrentOp);
16781 const APInt &C = ND->getAPIntValue();
16782 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16787 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16790 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16793 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16794 // may or may not be a constant. Takes immediate version of shift as input.
16795 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16796 SDValue SrcOp, SDValue ShAmt,
16797 SelectionDAG &DAG) {
16798 MVT SVT = ShAmt.getSimpleValueType();
16799 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16801 // Catch shift-by-constant.
16802 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16803 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16804 CShAmt->getZExtValue(), DAG);
16806 // Change opcode to non-immediate version
16808 default: llvm_unreachable("Unknown target vector shift node");
16809 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16810 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16811 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16814 const X86Subtarget &Subtarget =
16815 DAG.getTarget().getSubtarget<X86Subtarget>();
16816 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16817 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16818 // Let the shuffle legalizer expand this shift amount node.
16819 SDValue Op0 = ShAmt.getOperand(0);
16820 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16821 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16823 // Need to build a vector containing shift amount.
16824 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16825 SmallVector<SDValue, 4> ShOps;
16826 ShOps.push_back(ShAmt);
16827 if (SVT == MVT::i32) {
16828 ShOps.push_back(DAG.getConstant(0, SVT));
16829 ShOps.push_back(DAG.getUNDEF(SVT));
16831 ShOps.push_back(DAG.getUNDEF(SVT));
16833 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16834 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16837 // The return type has to be a 128-bit type with the same element
16838 // type as the input type.
16839 MVT EltVT = VT.getVectorElementType();
16840 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16842 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16843 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16846 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16847 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16848 /// necessary casting for \p Mask when lowering masking intrinsics.
16849 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16850 SDValue PreservedSrc,
16851 const X86Subtarget *Subtarget,
16852 SelectionDAG &DAG) {
16853 EVT VT = Op.getValueType();
16854 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16855 MVT::i1, VT.getVectorNumElements());
16856 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16857 Mask.getValueType().getSizeInBits());
16860 assert(MaskVT.isSimple() && "invalid mask type");
16862 if (isAllOnes(Mask))
16865 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16866 // are extracted by EXTRACT_SUBVECTOR.
16867 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16868 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16869 DAG.getIntPtrConstant(0));
16871 switch (Op.getOpcode()) {
16873 case X86ISD::PCMPEQM:
16874 case X86ISD::PCMPGTM:
16876 case X86ISD::CMPMU:
16877 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16879 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16880 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16881 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16884 /// \brief Creates an SDNode for a predicated scalar operation.
16885 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16886 /// The mask is comming as MVT::i8 and it should be truncated
16887 /// to MVT::i1 while lowering masking intrinsics.
16888 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16889 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16890 /// a scalar instruction.
16891 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16892 SDValue PreservedSrc,
16893 const X86Subtarget *Subtarget,
16894 SelectionDAG &DAG) {
16895 if (isAllOnes(Mask))
16898 EVT VT = Op.getValueType();
16900 // The mask should be of type MVT::i1
16901 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16903 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16904 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16905 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16908 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16910 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16911 case Intrinsic::x86_fma_vfmadd_ps:
16912 case Intrinsic::x86_fma_vfmadd_pd:
16913 case Intrinsic::x86_fma_vfmadd_ps_256:
16914 case Intrinsic::x86_fma_vfmadd_pd_256:
16915 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16916 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16917 return X86ISD::FMADD;
16918 case Intrinsic::x86_fma_vfmsub_ps:
16919 case Intrinsic::x86_fma_vfmsub_pd:
16920 case Intrinsic::x86_fma_vfmsub_ps_256:
16921 case Intrinsic::x86_fma_vfmsub_pd_256:
16922 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16923 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16924 return X86ISD::FMSUB;
16925 case Intrinsic::x86_fma_vfnmadd_ps:
16926 case Intrinsic::x86_fma_vfnmadd_pd:
16927 case Intrinsic::x86_fma_vfnmadd_ps_256:
16928 case Intrinsic::x86_fma_vfnmadd_pd_256:
16929 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16930 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16931 return X86ISD::FNMADD;
16932 case Intrinsic::x86_fma_vfnmsub_ps:
16933 case Intrinsic::x86_fma_vfnmsub_pd:
16934 case Intrinsic::x86_fma_vfnmsub_ps_256:
16935 case Intrinsic::x86_fma_vfnmsub_pd_256:
16936 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16937 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16938 return X86ISD::FNMSUB;
16939 case Intrinsic::x86_fma_vfmaddsub_ps:
16940 case Intrinsic::x86_fma_vfmaddsub_pd:
16941 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16942 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16943 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16944 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16945 return X86ISD::FMADDSUB;
16946 case Intrinsic::x86_fma_vfmsubadd_ps:
16947 case Intrinsic::x86_fma_vfmsubadd_pd:
16948 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16949 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16950 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16951 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16952 return X86ISD::FMSUBADD;
16956 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16957 SelectionDAG &DAG) {
16959 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16960 EVT VT = Op.getValueType();
16961 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16963 switch(IntrData->Type) {
16964 case INTR_TYPE_1OP:
16965 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16966 case INTR_TYPE_2OP:
16967 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16969 case INTR_TYPE_3OP:
16970 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16971 Op.getOperand(2), Op.getOperand(3));
16972 case INTR_TYPE_1OP_MASK_RM: {
16973 SDValue Src = Op.getOperand(1);
16974 SDValue Src0 = Op.getOperand(2);
16975 SDValue Mask = Op.getOperand(3);
16976 SDValue RoundingMode = Op.getOperand(4);
16977 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16979 Mask, Src0, Subtarget, DAG);
16981 case INTR_TYPE_SCALAR_MASK_RM: {
16982 SDValue Src1 = Op.getOperand(1);
16983 SDValue Src2 = Op.getOperand(2);
16984 SDValue Src0 = Op.getOperand(3);
16985 SDValue Mask = Op.getOperand(4);
16986 SDValue RoundingMode = Op.getOperand(5);
16987 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16989 Mask, Src0, Subtarget, DAG);
16991 case INTR_TYPE_2OP_MASK: {
16992 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16994 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16997 case CMP_MASK_CC: {
16998 // Comparison intrinsics with masks.
16999 // Example of transformation:
17000 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
17001 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
17003 // (v8i1 (insert_subvector undef,
17004 // (v2i1 (and (PCMPEQM %a, %b),
17005 // (extract_subvector
17006 // (v8i1 (bitcast %mask)), 0))), 0))))
17007 EVT VT = Op.getOperand(1).getValueType();
17008 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17009 VT.getVectorNumElements());
17010 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
17011 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17012 Mask.getValueType().getSizeInBits());
17014 if (IntrData->Type == CMP_MASK_CC) {
17015 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
17016 Op.getOperand(2), Op.getOperand(3));
17018 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
17019 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
17022 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
17023 DAG.getTargetConstant(0, MaskVT),
17025 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
17026 DAG.getUNDEF(BitcastVT), CmpMask,
17027 DAG.getIntPtrConstant(0));
17028 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
17030 case COMI: { // Comparison intrinsics
17031 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
17032 SDValue LHS = Op.getOperand(1);
17033 SDValue RHS = Op.getOperand(2);
17034 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
17035 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
17036 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
17037 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17038 DAG.getConstant(X86CC, MVT::i8), Cond);
17039 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17042 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
17043 Op.getOperand(1), Op.getOperand(2), DAG);
17045 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
17046 Op.getSimpleValueType(),
17048 Op.getOperand(2), DAG),
17049 Op.getOperand(4), Op.getOperand(3), Subtarget,
17051 case COMPRESS_EXPAND_IN_REG: {
17052 SDValue Mask = Op.getOperand(3);
17053 SDValue DataToCompress = Op.getOperand(1);
17054 SDValue PassThru = Op.getOperand(2);
17055 if (isAllOnes(Mask)) // return data as is
17056 return Op.getOperand(1);
17057 EVT VT = Op.getValueType();
17058 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17059 VT.getVectorNumElements());
17060 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17061 Mask.getValueType().getSizeInBits());
17063 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17064 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17065 DAG.getIntPtrConstant(0));
17067 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17071 SDValue Mask = Op.getOperand(3);
17072 EVT VT = Op.getValueType();
17073 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17074 VT.getVectorNumElements());
17075 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17076 Mask.getValueType().getSizeInBits());
17078 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17079 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17080 DAG.getIntPtrConstant(0));
17081 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17086 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17087 dl, Op.getValueType(),
17091 Op.getOperand(4), Op.getOperand(1),
17100 default: return SDValue(); // Don't custom lower most intrinsics.
17102 case Intrinsic::x86_avx512_mask_valign_q_512:
17103 case Intrinsic::x86_avx512_mask_valign_d_512:
17104 // Vector source operands are swapped.
17105 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17106 Op.getValueType(), Op.getOperand(2),
17109 Op.getOperand(5), Op.getOperand(4),
17112 // ptest and testp intrinsics. The intrinsic these come from are designed to
17113 // return an integer value, not just an instruction so lower it to the ptest
17114 // or testp pattern and a setcc for the result.
17115 case Intrinsic::x86_sse41_ptestz:
17116 case Intrinsic::x86_sse41_ptestc:
17117 case Intrinsic::x86_sse41_ptestnzc:
17118 case Intrinsic::x86_avx_ptestz_256:
17119 case Intrinsic::x86_avx_ptestc_256:
17120 case Intrinsic::x86_avx_ptestnzc_256:
17121 case Intrinsic::x86_avx_vtestz_ps:
17122 case Intrinsic::x86_avx_vtestc_ps:
17123 case Intrinsic::x86_avx_vtestnzc_ps:
17124 case Intrinsic::x86_avx_vtestz_pd:
17125 case Intrinsic::x86_avx_vtestc_pd:
17126 case Intrinsic::x86_avx_vtestnzc_pd:
17127 case Intrinsic::x86_avx_vtestz_ps_256:
17128 case Intrinsic::x86_avx_vtestc_ps_256:
17129 case Intrinsic::x86_avx_vtestnzc_ps_256:
17130 case Intrinsic::x86_avx_vtestz_pd_256:
17131 case Intrinsic::x86_avx_vtestc_pd_256:
17132 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17133 bool IsTestPacked = false;
17136 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17137 case Intrinsic::x86_avx_vtestz_ps:
17138 case Intrinsic::x86_avx_vtestz_pd:
17139 case Intrinsic::x86_avx_vtestz_ps_256:
17140 case Intrinsic::x86_avx_vtestz_pd_256:
17141 IsTestPacked = true; // Fallthrough
17142 case Intrinsic::x86_sse41_ptestz:
17143 case Intrinsic::x86_avx_ptestz_256:
17145 X86CC = X86::COND_E;
17147 case Intrinsic::x86_avx_vtestc_ps:
17148 case Intrinsic::x86_avx_vtestc_pd:
17149 case Intrinsic::x86_avx_vtestc_ps_256:
17150 case Intrinsic::x86_avx_vtestc_pd_256:
17151 IsTestPacked = true; // Fallthrough
17152 case Intrinsic::x86_sse41_ptestc:
17153 case Intrinsic::x86_avx_ptestc_256:
17155 X86CC = X86::COND_B;
17157 case Intrinsic::x86_avx_vtestnzc_ps:
17158 case Intrinsic::x86_avx_vtestnzc_pd:
17159 case Intrinsic::x86_avx_vtestnzc_ps_256:
17160 case Intrinsic::x86_avx_vtestnzc_pd_256:
17161 IsTestPacked = true; // Fallthrough
17162 case Intrinsic::x86_sse41_ptestnzc:
17163 case Intrinsic::x86_avx_ptestnzc_256:
17165 X86CC = X86::COND_A;
17169 SDValue LHS = Op.getOperand(1);
17170 SDValue RHS = Op.getOperand(2);
17171 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17172 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17173 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17174 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17175 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17177 case Intrinsic::x86_avx512_kortestz_w:
17178 case Intrinsic::x86_avx512_kortestc_w: {
17179 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17180 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17181 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17182 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17183 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17184 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17185 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17188 case Intrinsic::x86_sse42_pcmpistria128:
17189 case Intrinsic::x86_sse42_pcmpestria128:
17190 case Intrinsic::x86_sse42_pcmpistric128:
17191 case Intrinsic::x86_sse42_pcmpestric128:
17192 case Intrinsic::x86_sse42_pcmpistrio128:
17193 case Intrinsic::x86_sse42_pcmpestrio128:
17194 case Intrinsic::x86_sse42_pcmpistris128:
17195 case Intrinsic::x86_sse42_pcmpestris128:
17196 case Intrinsic::x86_sse42_pcmpistriz128:
17197 case Intrinsic::x86_sse42_pcmpestriz128: {
17201 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17202 case Intrinsic::x86_sse42_pcmpistria128:
17203 Opcode = X86ISD::PCMPISTRI;
17204 X86CC = X86::COND_A;
17206 case Intrinsic::x86_sse42_pcmpestria128:
17207 Opcode = X86ISD::PCMPESTRI;
17208 X86CC = X86::COND_A;
17210 case Intrinsic::x86_sse42_pcmpistric128:
17211 Opcode = X86ISD::PCMPISTRI;
17212 X86CC = X86::COND_B;
17214 case Intrinsic::x86_sse42_pcmpestric128:
17215 Opcode = X86ISD::PCMPESTRI;
17216 X86CC = X86::COND_B;
17218 case Intrinsic::x86_sse42_pcmpistrio128:
17219 Opcode = X86ISD::PCMPISTRI;
17220 X86CC = X86::COND_O;
17222 case Intrinsic::x86_sse42_pcmpestrio128:
17223 Opcode = X86ISD::PCMPESTRI;
17224 X86CC = X86::COND_O;
17226 case Intrinsic::x86_sse42_pcmpistris128:
17227 Opcode = X86ISD::PCMPISTRI;
17228 X86CC = X86::COND_S;
17230 case Intrinsic::x86_sse42_pcmpestris128:
17231 Opcode = X86ISD::PCMPESTRI;
17232 X86CC = X86::COND_S;
17234 case Intrinsic::x86_sse42_pcmpistriz128:
17235 Opcode = X86ISD::PCMPISTRI;
17236 X86CC = X86::COND_E;
17238 case Intrinsic::x86_sse42_pcmpestriz128:
17239 Opcode = X86ISD::PCMPESTRI;
17240 X86CC = X86::COND_E;
17243 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17244 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17245 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17246 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17247 DAG.getConstant(X86CC, MVT::i8),
17248 SDValue(PCMP.getNode(), 1));
17249 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17252 case Intrinsic::x86_sse42_pcmpistri128:
17253 case Intrinsic::x86_sse42_pcmpestri128: {
17255 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17256 Opcode = X86ISD::PCMPISTRI;
17258 Opcode = X86ISD::PCMPESTRI;
17260 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17261 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17262 return DAG.getNode(Opcode, dl, VTs, NewOps);
17265 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17266 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17267 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17268 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17269 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17270 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17271 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17272 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17273 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17274 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17275 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17276 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17277 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17278 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17279 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17280 dl, Op.getValueType(),
17284 Op.getOperand(4), Op.getOperand(1),
17290 case Intrinsic::x86_fma_vfmadd_ps:
17291 case Intrinsic::x86_fma_vfmadd_pd:
17292 case Intrinsic::x86_fma_vfmsub_ps:
17293 case Intrinsic::x86_fma_vfmsub_pd:
17294 case Intrinsic::x86_fma_vfnmadd_ps:
17295 case Intrinsic::x86_fma_vfnmadd_pd:
17296 case Intrinsic::x86_fma_vfnmsub_ps:
17297 case Intrinsic::x86_fma_vfnmsub_pd:
17298 case Intrinsic::x86_fma_vfmaddsub_ps:
17299 case Intrinsic::x86_fma_vfmaddsub_pd:
17300 case Intrinsic::x86_fma_vfmsubadd_ps:
17301 case Intrinsic::x86_fma_vfmsubadd_pd:
17302 case Intrinsic::x86_fma_vfmadd_ps_256:
17303 case Intrinsic::x86_fma_vfmadd_pd_256:
17304 case Intrinsic::x86_fma_vfmsub_ps_256:
17305 case Intrinsic::x86_fma_vfmsub_pd_256:
17306 case Intrinsic::x86_fma_vfnmadd_ps_256:
17307 case Intrinsic::x86_fma_vfnmadd_pd_256:
17308 case Intrinsic::x86_fma_vfnmsub_ps_256:
17309 case Intrinsic::x86_fma_vfnmsub_pd_256:
17310 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17311 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17312 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17313 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17314 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17315 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17319 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17320 SDValue Src, SDValue Mask, SDValue Base,
17321 SDValue Index, SDValue ScaleOp, SDValue Chain,
17322 const X86Subtarget * Subtarget) {
17324 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17325 assert(C && "Invalid scale type");
17326 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17327 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17328 Index.getSimpleValueType().getVectorNumElements());
17330 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17332 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17334 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17335 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17336 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17337 SDValue Segment = DAG.getRegister(0, MVT::i32);
17338 if (Src.getOpcode() == ISD::UNDEF)
17339 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17340 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17341 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17342 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17343 return DAG.getMergeValues(RetOps, dl);
17346 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17347 SDValue Src, SDValue Mask, SDValue Base,
17348 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17350 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17351 assert(C && "Invalid scale type");
17352 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17353 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17354 SDValue Segment = DAG.getRegister(0, MVT::i32);
17355 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17356 Index.getSimpleValueType().getVectorNumElements());
17358 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17360 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17362 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17363 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17364 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17365 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17366 return SDValue(Res, 1);
17369 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17370 SDValue Mask, SDValue Base, SDValue Index,
17371 SDValue ScaleOp, SDValue Chain) {
17373 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17374 assert(C && "Invalid scale type");
17375 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17376 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17377 SDValue Segment = DAG.getRegister(0, MVT::i32);
17379 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17381 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17383 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17385 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17386 //SDVTList VTs = DAG.getVTList(MVT::Other);
17387 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17388 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17389 return SDValue(Res, 0);
17392 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17393 // read performance monitor counters (x86_rdpmc).
17394 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17395 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17396 SmallVectorImpl<SDValue> &Results) {
17397 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17398 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17401 // The ECX register is used to select the index of the performance counter
17403 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17405 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17407 // Reads the content of a 64-bit performance counter and returns it in the
17408 // registers EDX:EAX.
17409 if (Subtarget->is64Bit()) {
17410 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17411 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17414 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17415 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17418 Chain = HI.getValue(1);
17420 if (Subtarget->is64Bit()) {
17421 // The EAX register is loaded with the low-order 32 bits. The EDX register
17422 // is loaded with the supported high-order bits of the counter.
17423 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17424 DAG.getConstant(32, MVT::i8));
17425 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17426 Results.push_back(Chain);
17430 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17431 SDValue Ops[] = { LO, HI };
17432 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17433 Results.push_back(Pair);
17434 Results.push_back(Chain);
17437 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17438 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17439 // also used to custom lower READCYCLECOUNTER nodes.
17440 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17441 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17442 SmallVectorImpl<SDValue> &Results) {
17443 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17444 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17447 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17448 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17449 // and the EAX register is loaded with the low-order 32 bits.
17450 if (Subtarget->is64Bit()) {
17451 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17452 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17455 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17456 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17459 SDValue Chain = HI.getValue(1);
17461 if (Opcode == X86ISD::RDTSCP_DAG) {
17462 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17464 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17465 // the ECX register. Add 'ecx' explicitly to the chain.
17466 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17468 // Explicitly store the content of ECX at the location passed in input
17469 // to the 'rdtscp' intrinsic.
17470 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17471 MachinePointerInfo(), false, false, 0);
17474 if (Subtarget->is64Bit()) {
17475 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17476 // the EAX register is loaded with the low-order 32 bits.
17477 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17478 DAG.getConstant(32, MVT::i8));
17479 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17480 Results.push_back(Chain);
17484 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17485 SDValue Ops[] = { LO, HI };
17486 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17487 Results.push_back(Pair);
17488 Results.push_back(Chain);
17491 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17492 SelectionDAG &DAG) {
17493 SmallVector<SDValue, 2> Results;
17495 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17497 return DAG.getMergeValues(Results, DL);
17501 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17502 SelectionDAG &DAG) {
17503 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17505 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17510 switch(IntrData->Type) {
17512 llvm_unreachable("Unknown Intrinsic Type");
17516 // Emit the node with the right value type.
17517 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17518 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17520 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17521 // Otherwise return the value from Rand, which is always 0, casted to i32.
17522 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17523 DAG.getConstant(1, Op->getValueType(1)),
17524 DAG.getConstant(X86::COND_B, MVT::i32),
17525 SDValue(Result.getNode(), 1) };
17526 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17527 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17530 // Return { result, isValid, chain }.
17531 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17532 SDValue(Result.getNode(), 2));
17535 //gather(v1, mask, index, base, scale);
17536 SDValue Chain = Op.getOperand(0);
17537 SDValue Src = Op.getOperand(2);
17538 SDValue Base = Op.getOperand(3);
17539 SDValue Index = Op.getOperand(4);
17540 SDValue Mask = Op.getOperand(5);
17541 SDValue Scale = Op.getOperand(6);
17542 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17546 //scatter(base, mask, index, v1, scale);
17547 SDValue Chain = Op.getOperand(0);
17548 SDValue Base = Op.getOperand(2);
17549 SDValue Mask = Op.getOperand(3);
17550 SDValue Index = Op.getOperand(4);
17551 SDValue Src = Op.getOperand(5);
17552 SDValue Scale = Op.getOperand(6);
17553 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17556 SDValue Hint = Op.getOperand(6);
17558 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17559 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17560 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17561 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17562 SDValue Chain = Op.getOperand(0);
17563 SDValue Mask = Op.getOperand(2);
17564 SDValue Index = Op.getOperand(3);
17565 SDValue Base = Op.getOperand(4);
17566 SDValue Scale = Op.getOperand(5);
17567 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17569 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17571 SmallVector<SDValue, 2> Results;
17572 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17573 return DAG.getMergeValues(Results, dl);
17575 // Read Performance Monitoring Counters.
17577 SmallVector<SDValue, 2> Results;
17578 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17579 return DAG.getMergeValues(Results, dl);
17581 // XTEST intrinsics.
17583 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17584 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17585 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17586 DAG.getConstant(X86::COND_NE, MVT::i8),
17588 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17589 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17590 Ret, SDValue(InTrans.getNode(), 1));
17594 SmallVector<SDValue, 2> Results;
17595 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17596 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17597 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17598 DAG.getConstant(-1, MVT::i8));
17599 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17600 Op.getOperand(4), GenCF.getValue(1));
17601 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17602 Op.getOperand(5), MachinePointerInfo(),
17604 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17605 DAG.getConstant(X86::COND_B, MVT::i8),
17607 Results.push_back(SetCC);
17608 Results.push_back(Store);
17609 return DAG.getMergeValues(Results, dl);
17611 case COMPRESS_TO_MEM: {
17613 SDValue Mask = Op.getOperand(4);
17614 SDValue DataToCompress = Op.getOperand(3);
17615 SDValue Addr = Op.getOperand(2);
17616 SDValue Chain = Op.getOperand(0);
17618 if (isAllOnes(Mask)) // return just a store
17619 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17620 MachinePointerInfo(), false, false, 0);
17622 EVT VT = DataToCompress.getValueType();
17623 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17624 VT.getVectorNumElements());
17625 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17626 Mask.getValueType().getSizeInBits());
17627 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17628 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17629 DAG.getIntPtrConstant(0));
17631 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17632 DataToCompress, DAG.getUNDEF(VT));
17633 return DAG.getStore(Chain, dl, Compressed, Addr,
17634 MachinePointerInfo(), false, false, 0);
17636 case EXPAND_FROM_MEM: {
17638 SDValue Mask = Op.getOperand(4);
17639 SDValue PathThru = Op.getOperand(3);
17640 SDValue Addr = Op.getOperand(2);
17641 SDValue Chain = Op.getOperand(0);
17642 EVT VT = Op.getValueType();
17644 if (isAllOnes(Mask)) // return just a load
17645 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17647 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17648 VT.getVectorNumElements());
17649 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17650 Mask.getValueType().getSizeInBits());
17651 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17652 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17653 DAG.getIntPtrConstant(0));
17655 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17656 false, false, false, 0);
17658 SmallVector<SDValue, 2> Results;
17659 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17661 Results.push_back(Chain);
17662 return DAG.getMergeValues(Results, dl);
17667 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17668 SelectionDAG &DAG) const {
17669 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17670 MFI->setReturnAddressIsTaken(true);
17672 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17675 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17677 EVT PtrVT = getPointerTy();
17680 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17681 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17682 DAG.getSubtarget().getRegisterInfo());
17683 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17684 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17685 DAG.getNode(ISD::ADD, dl, PtrVT,
17686 FrameAddr, Offset),
17687 MachinePointerInfo(), false, false, false, 0);
17690 // Just load the return address.
17691 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17692 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17693 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17696 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17697 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17698 MFI->setFrameAddressIsTaken(true);
17700 EVT VT = Op.getValueType();
17701 SDLoc dl(Op); // FIXME probably not meaningful
17702 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17703 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17704 DAG.getSubtarget().getRegisterInfo());
17705 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17706 DAG.getMachineFunction());
17707 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17708 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17709 "Invalid Frame Register!");
17710 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17712 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17713 MachinePointerInfo(),
17714 false, false, false, 0);
17718 // FIXME? Maybe this could be a TableGen attribute on some registers and
17719 // this table could be generated automatically from RegInfo.
17720 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17722 unsigned Reg = StringSwitch<unsigned>(RegName)
17723 .Case("esp", X86::ESP)
17724 .Case("rsp", X86::RSP)
17728 report_fatal_error("Invalid register name global variable");
17731 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17732 SelectionDAG &DAG) const {
17733 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17734 DAG.getSubtarget().getRegisterInfo());
17735 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17738 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17739 SDValue Chain = Op.getOperand(0);
17740 SDValue Offset = Op.getOperand(1);
17741 SDValue Handler = Op.getOperand(2);
17744 EVT PtrVT = getPointerTy();
17745 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17746 DAG.getSubtarget().getRegisterInfo());
17747 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17748 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17749 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17750 "Invalid Frame Register!");
17751 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17752 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17754 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17755 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17756 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17757 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17759 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17761 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17762 DAG.getRegister(StoreAddrReg, PtrVT));
17765 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17766 SelectionDAG &DAG) const {
17768 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17769 DAG.getVTList(MVT::i32, MVT::Other),
17770 Op.getOperand(0), Op.getOperand(1));
17773 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17774 SelectionDAG &DAG) const {
17776 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17777 Op.getOperand(0), Op.getOperand(1));
17780 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17781 return Op.getOperand(0);
17784 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17785 SelectionDAG &DAG) const {
17786 SDValue Root = Op.getOperand(0);
17787 SDValue Trmp = Op.getOperand(1); // trampoline
17788 SDValue FPtr = Op.getOperand(2); // nested function
17789 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17792 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17793 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17795 if (Subtarget->is64Bit()) {
17796 SDValue OutChains[6];
17798 // Large code-model.
17799 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17800 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17802 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17803 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17805 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17807 // Load the pointer to the nested function into R11.
17808 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17809 SDValue Addr = Trmp;
17810 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17811 Addr, MachinePointerInfo(TrmpAddr),
17814 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17815 DAG.getConstant(2, MVT::i64));
17816 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17817 MachinePointerInfo(TrmpAddr, 2),
17820 // Load the 'nest' parameter value into R10.
17821 // R10 is specified in X86CallingConv.td
17822 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17823 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17824 DAG.getConstant(10, MVT::i64));
17825 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17826 Addr, MachinePointerInfo(TrmpAddr, 10),
17829 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17830 DAG.getConstant(12, MVT::i64));
17831 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17832 MachinePointerInfo(TrmpAddr, 12),
17835 // Jump to the nested function.
17836 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17837 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17838 DAG.getConstant(20, MVT::i64));
17839 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17840 Addr, MachinePointerInfo(TrmpAddr, 20),
17843 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17844 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17845 DAG.getConstant(22, MVT::i64));
17846 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17847 MachinePointerInfo(TrmpAddr, 22),
17850 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17852 const Function *Func =
17853 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17854 CallingConv::ID CC = Func->getCallingConv();
17859 llvm_unreachable("Unsupported calling convention");
17860 case CallingConv::C:
17861 case CallingConv::X86_StdCall: {
17862 // Pass 'nest' parameter in ECX.
17863 // Must be kept in sync with X86CallingConv.td
17864 NestReg = X86::ECX;
17866 // Check that ECX wasn't needed by an 'inreg' parameter.
17867 FunctionType *FTy = Func->getFunctionType();
17868 const AttributeSet &Attrs = Func->getAttributes();
17870 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17871 unsigned InRegCount = 0;
17874 for (FunctionType::param_iterator I = FTy->param_begin(),
17875 E = FTy->param_end(); I != E; ++I, ++Idx)
17876 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17877 // FIXME: should only count parameters that are lowered to integers.
17878 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17880 if (InRegCount > 2) {
17881 report_fatal_error("Nest register in use - reduce number of inreg"
17887 case CallingConv::X86_FastCall:
17888 case CallingConv::X86_ThisCall:
17889 case CallingConv::Fast:
17890 // Pass 'nest' parameter in EAX.
17891 // Must be kept in sync with X86CallingConv.td
17892 NestReg = X86::EAX;
17896 SDValue OutChains[4];
17897 SDValue Addr, Disp;
17899 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17900 DAG.getConstant(10, MVT::i32));
17901 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17903 // This is storing the opcode for MOV32ri.
17904 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17905 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17906 OutChains[0] = DAG.getStore(Root, dl,
17907 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17908 Trmp, MachinePointerInfo(TrmpAddr),
17911 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17912 DAG.getConstant(1, MVT::i32));
17913 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17914 MachinePointerInfo(TrmpAddr, 1),
17917 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17918 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17919 DAG.getConstant(5, MVT::i32));
17920 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17921 MachinePointerInfo(TrmpAddr, 5),
17924 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17925 DAG.getConstant(6, MVT::i32));
17926 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17927 MachinePointerInfo(TrmpAddr, 6),
17930 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17934 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17935 SelectionDAG &DAG) const {
17937 The rounding mode is in bits 11:10 of FPSR, and has the following
17939 00 Round to nearest
17944 FLT_ROUNDS, on the other hand, expects the following:
17951 To perform the conversion, we do:
17952 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17955 MachineFunction &MF = DAG.getMachineFunction();
17956 const TargetMachine &TM = MF.getTarget();
17957 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17958 unsigned StackAlignment = TFI.getStackAlignment();
17959 MVT VT = Op.getSimpleValueType();
17962 // Save FP Control Word to stack slot
17963 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17964 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17966 MachineMemOperand *MMO =
17967 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17968 MachineMemOperand::MOStore, 2, 2);
17970 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17971 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17972 DAG.getVTList(MVT::Other),
17973 Ops, MVT::i16, MMO);
17975 // Load FP Control Word from stack slot
17976 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17977 MachinePointerInfo(), false, false, false, 0);
17979 // Transform as necessary
17981 DAG.getNode(ISD::SRL, DL, MVT::i16,
17982 DAG.getNode(ISD::AND, DL, MVT::i16,
17983 CWD, DAG.getConstant(0x800, MVT::i16)),
17984 DAG.getConstant(11, MVT::i8));
17986 DAG.getNode(ISD::SRL, DL, MVT::i16,
17987 DAG.getNode(ISD::AND, DL, MVT::i16,
17988 CWD, DAG.getConstant(0x400, MVT::i16)),
17989 DAG.getConstant(9, MVT::i8));
17992 DAG.getNode(ISD::AND, DL, MVT::i16,
17993 DAG.getNode(ISD::ADD, DL, MVT::i16,
17994 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17995 DAG.getConstant(1, MVT::i16)),
17996 DAG.getConstant(3, MVT::i16));
17998 return DAG.getNode((VT.getSizeInBits() < 16 ?
17999 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
18002 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
18003 MVT VT = Op.getSimpleValueType();
18005 unsigned NumBits = VT.getSizeInBits();
18008 Op = Op.getOperand(0);
18009 if (VT == MVT::i8) {
18010 // Zero extend to i32 since there is not an i8 bsr.
18012 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18015 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
18016 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18017 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18019 // If src is zero (i.e. bsr sets ZF), returns NumBits.
18022 DAG.getConstant(NumBits+NumBits-1, OpVT),
18023 DAG.getConstant(X86::COND_E, MVT::i8),
18026 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
18028 // Finally xor with NumBits-1.
18029 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18032 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18036 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
18037 MVT VT = Op.getSimpleValueType();
18039 unsigned NumBits = VT.getSizeInBits();
18042 Op = Op.getOperand(0);
18043 if (VT == MVT::i8) {
18044 // Zero extend to i32 since there is not an i8 bsr.
18046 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18049 // Issue a bsr (scan bits in reverse).
18050 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18051 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18053 // And xor with NumBits-1.
18054 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18057 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18061 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18062 MVT VT = Op.getSimpleValueType();
18063 unsigned NumBits = VT.getSizeInBits();
18065 Op = Op.getOperand(0);
18067 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18068 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18069 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18071 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18074 DAG.getConstant(NumBits, VT),
18075 DAG.getConstant(X86::COND_E, MVT::i8),
18078 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18081 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18082 // ones, and then concatenate the result back.
18083 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18084 MVT VT = Op.getSimpleValueType();
18086 assert(VT.is256BitVector() && VT.isInteger() &&
18087 "Unsupported value type for operation");
18089 unsigned NumElems = VT.getVectorNumElements();
18092 // Extract the LHS vectors
18093 SDValue LHS = Op.getOperand(0);
18094 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18095 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18097 // Extract the RHS vectors
18098 SDValue RHS = Op.getOperand(1);
18099 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18100 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18102 MVT EltVT = VT.getVectorElementType();
18103 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18105 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18106 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18107 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18110 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18111 assert(Op.getSimpleValueType().is256BitVector() &&
18112 Op.getSimpleValueType().isInteger() &&
18113 "Only handle AVX 256-bit vector integer operation");
18114 return Lower256IntArith(Op, DAG);
18117 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18118 assert(Op.getSimpleValueType().is256BitVector() &&
18119 Op.getSimpleValueType().isInteger() &&
18120 "Only handle AVX 256-bit vector integer operation");
18121 return Lower256IntArith(Op, DAG);
18124 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18125 SelectionDAG &DAG) {
18127 MVT VT = Op.getSimpleValueType();
18129 // Decompose 256-bit ops into smaller 128-bit ops.
18130 if (VT.is256BitVector() && !Subtarget->hasInt256())
18131 return Lower256IntArith(Op, DAG);
18133 SDValue A = Op.getOperand(0);
18134 SDValue B = Op.getOperand(1);
18136 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18137 if (VT == MVT::v4i32) {
18138 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18139 "Should not custom lower when pmuldq is available!");
18141 // Extract the odd parts.
18142 static const int UnpackMask[] = { 1, -1, 3, -1 };
18143 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18144 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18146 // Multiply the even parts.
18147 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18148 // Now multiply odd parts.
18149 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18151 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18152 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18154 // Merge the two vectors back together with a shuffle. This expands into 2
18156 static const int ShufMask[] = { 0, 4, 2, 6 };
18157 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18160 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18161 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18163 // Ahi = psrlqi(a, 32);
18164 // Bhi = psrlqi(b, 32);
18166 // AloBlo = pmuludq(a, b);
18167 // AloBhi = pmuludq(a, Bhi);
18168 // AhiBlo = pmuludq(Ahi, b);
18170 // AloBhi = psllqi(AloBhi, 32);
18171 // AhiBlo = psllqi(AhiBlo, 32);
18172 // return AloBlo + AloBhi + AhiBlo;
18174 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18175 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18177 // Bit cast to 32-bit vectors for MULUDQ
18178 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18179 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18180 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18181 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18182 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18183 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18185 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18186 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18187 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18189 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18190 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18192 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18193 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18196 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18197 assert(Subtarget->isTargetWin64() && "Unexpected target");
18198 EVT VT = Op.getValueType();
18199 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18200 "Unexpected return type for lowering");
18204 switch (Op->getOpcode()) {
18205 default: llvm_unreachable("Unexpected request for libcall!");
18206 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18207 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18208 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18209 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18210 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18211 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18215 SDValue InChain = DAG.getEntryNode();
18217 TargetLowering::ArgListTy Args;
18218 TargetLowering::ArgListEntry Entry;
18219 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18220 EVT ArgVT = Op->getOperand(i).getValueType();
18221 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18222 "Unexpected argument type for lowering");
18223 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18224 Entry.Node = StackPtr;
18225 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18227 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18228 Entry.Ty = PointerType::get(ArgTy,0);
18229 Entry.isSExt = false;
18230 Entry.isZExt = false;
18231 Args.push_back(Entry);
18234 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18237 TargetLowering::CallLoweringInfo CLI(DAG);
18238 CLI.setDebugLoc(dl).setChain(InChain)
18239 .setCallee(getLibcallCallingConv(LC),
18240 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18241 Callee, std::move(Args), 0)
18242 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18244 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18245 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18248 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18249 SelectionDAG &DAG) {
18250 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18251 EVT VT = Op0.getValueType();
18254 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18255 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18257 // PMULxD operations multiply each even value (starting at 0) of LHS with
18258 // the related value of RHS and produce a widen result.
18259 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18260 // => <2 x i64> <ae|cg>
18262 // In other word, to have all the results, we need to perform two PMULxD:
18263 // 1. one with the even values.
18264 // 2. one with the odd values.
18265 // To achieve #2, with need to place the odd values at an even position.
18267 // Place the odd value at an even position (basically, shift all values 1
18268 // step to the left):
18269 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18270 // <a|b|c|d> => <b|undef|d|undef>
18271 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18272 // <e|f|g|h> => <f|undef|h|undef>
18273 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18275 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18277 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18278 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18280 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18281 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18282 // => <2 x i64> <ae|cg>
18283 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18284 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18285 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18286 // => <2 x i64> <bf|dh>
18287 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18288 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18290 // Shuffle it back into the right order.
18291 SDValue Highs, Lows;
18292 if (VT == MVT::v8i32) {
18293 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18294 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18295 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18296 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18298 const int HighMask[] = {1, 5, 3, 7};
18299 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18300 const int LowMask[] = {0, 4, 2, 6};
18301 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18304 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18305 // unsigned multiply.
18306 if (IsSigned && !Subtarget->hasSSE41()) {
18308 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18309 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18310 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18311 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18312 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18314 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18315 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18318 // The first result of MUL_LOHI is actually the low value, followed by the
18320 SDValue Ops[] = {Lows, Highs};
18321 return DAG.getMergeValues(Ops, dl);
18324 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18325 const X86Subtarget *Subtarget) {
18326 MVT VT = Op.getSimpleValueType();
18328 SDValue R = Op.getOperand(0);
18329 SDValue Amt = Op.getOperand(1);
18331 // Optimize shl/srl/sra with constant shift amount.
18332 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18333 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18334 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18336 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18337 (Subtarget->hasInt256() &&
18338 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18339 (Subtarget->hasAVX512() &&
18340 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18341 if (Op.getOpcode() == ISD::SHL)
18342 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18344 if (Op.getOpcode() == ISD::SRL)
18345 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18347 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18348 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18352 if (VT == MVT::v16i8) {
18353 if (Op.getOpcode() == ISD::SHL) {
18354 // Make a large shift.
18355 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18356 MVT::v8i16, R, ShiftAmt,
18358 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18359 // Zero out the rightmost bits.
18360 SmallVector<SDValue, 16> V(16,
18361 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18363 return DAG.getNode(ISD::AND, dl, VT, SHL,
18364 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18366 if (Op.getOpcode() == ISD::SRL) {
18367 // Make a large shift.
18368 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18369 MVT::v8i16, R, ShiftAmt,
18371 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18372 // Zero out the leftmost bits.
18373 SmallVector<SDValue, 16> V(16,
18374 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18376 return DAG.getNode(ISD::AND, dl, VT, SRL,
18377 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18379 if (Op.getOpcode() == ISD::SRA) {
18380 if (ShiftAmt == 7) {
18381 // R s>> 7 === R s< 0
18382 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18383 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18386 // R s>> a === ((R u>> a) ^ m) - m
18387 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18388 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18390 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18391 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18392 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18395 llvm_unreachable("Unknown shift opcode.");
18398 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18399 if (Op.getOpcode() == ISD::SHL) {
18400 // Make a large shift.
18401 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18402 MVT::v16i16, R, ShiftAmt,
18404 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18405 // Zero out the rightmost bits.
18406 SmallVector<SDValue, 32> V(32,
18407 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18409 return DAG.getNode(ISD::AND, dl, VT, SHL,
18410 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18412 if (Op.getOpcode() == ISD::SRL) {
18413 // Make a large shift.
18414 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18415 MVT::v16i16, R, ShiftAmt,
18417 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18418 // Zero out the leftmost bits.
18419 SmallVector<SDValue, 32> V(32,
18420 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18422 return DAG.getNode(ISD::AND, dl, VT, SRL,
18423 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18425 if (Op.getOpcode() == ISD::SRA) {
18426 if (ShiftAmt == 7) {
18427 // R s>> 7 === R s< 0
18428 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18429 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18432 // R s>> a === ((R u>> a) ^ m) - m
18433 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18434 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18436 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18437 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18438 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18441 llvm_unreachable("Unknown shift opcode.");
18446 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18447 if (!Subtarget->is64Bit() &&
18448 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18449 Amt.getOpcode() == ISD::BITCAST &&
18450 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18451 Amt = Amt.getOperand(0);
18452 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18453 VT.getVectorNumElements();
18454 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18455 uint64_t ShiftAmt = 0;
18456 for (unsigned i = 0; i != Ratio; ++i) {
18457 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18461 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18463 // Check remaining shift amounts.
18464 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18465 uint64_t ShAmt = 0;
18466 for (unsigned j = 0; j != Ratio; ++j) {
18467 ConstantSDNode *C =
18468 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18472 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18474 if (ShAmt != ShiftAmt)
18477 switch (Op.getOpcode()) {
18479 llvm_unreachable("Unknown shift opcode!");
18481 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18484 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18487 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18495 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18496 const X86Subtarget* Subtarget) {
18497 MVT VT = Op.getSimpleValueType();
18499 SDValue R = Op.getOperand(0);
18500 SDValue Amt = Op.getOperand(1);
18502 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18503 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18504 (Subtarget->hasInt256() &&
18505 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18506 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18507 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18509 EVT EltVT = VT.getVectorElementType();
18511 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18512 // Check if this build_vector node is doing a splat.
18513 // If so, then set BaseShAmt equal to the splat value.
18514 BaseShAmt = BV->getSplatValue();
18515 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18516 BaseShAmt = SDValue();
18518 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18519 Amt = Amt.getOperand(0);
18521 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18522 if (SVN && SVN->isSplat()) {
18523 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18524 SDValue InVec = Amt.getOperand(0);
18525 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18526 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18527 "Unexpected shuffle index found!");
18528 BaseShAmt = InVec.getOperand(SplatIdx);
18529 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18530 if (ConstantSDNode *C =
18531 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18532 if (C->getZExtValue() == SplatIdx)
18533 BaseShAmt = InVec.getOperand(1);
18538 // Avoid introducing an extract element from a shuffle.
18539 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18540 DAG.getIntPtrConstant(SplatIdx));
18544 if (BaseShAmt.getNode()) {
18545 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18546 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18547 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18548 else if (EltVT.bitsLT(MVT::i32))
18549 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18551 switch (Op.getOpcode()) {
18553 llvm_unreachable("Unknown shift opcode!");
18555 switch (VT.SimpleTy) {
18556 default: return SDValue();
18565 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18568 switch (VT.SimpleTy) {
18569 default: return SDValue();
18576 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18579 switch (VT.SimpleTy) {
18580 default: return SDValue();
18589 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18595 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18596 if (!Subtarget->is64Bit() &&
18597 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18598 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18599 Amt.getOpcode() == ISD::BITCAST &&
18600 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18601 Amt = Amt.getOperand(0);
18602 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18603 VT.getVectorNumElements();
18604 std::vector<SDValue> Vals(Ratio);
18605 for (unsigned i = 0; i != Ratio; ++i)
18606 Vals[i] = Amt.getOperand(i);
18607 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18608 for (unsigned j = 0; j != Ratio; ++j)
18609 if (Vals[j] != Amt.getOperand(i + j))
18612 switch (Op.getOpcode()) {
18614 llvm_unreachable("Unknown shift opcode!");
18616 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18618 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18620 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18627 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18628 SelectionDAG &DAG) {
18629 MVT VT = Op.getSimpleValueType();
18631 SDValue R = Op.getOperand(0);
18632 SDValue Amt = Op.getOperand(1);
18635 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18636 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18638 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18642 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18646 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18648 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18649 if (Subtarget->hasInt256()) {
18650 if (Op.getOpcode() == ISD::SRL &&
18651 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18652 VT == MVT::v4i64 || VT == MVT::v8i32))
18654 if (Op.getOpcode() == ISD::SHL &&
18655 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18656 VT == MVT::v4i64 || VT == MVT::v8i32))
18658 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18662 // If possible, lower this packed shift into a vector multiply instead of
18663 // expanding it into a sequence of scalar shifts.
18664 // Do this only if the vector shift count is a constant build_vector.
18665 if (Op.getOpcode() == ISD::SHL &&
18666 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18667 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18668 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18669 SmallVector<SDValue, 8> Elts;
18670 EVT SVT = VT.getScalarType();
18671 unsigned SVTBits = SVT.getSizeInBits();
18672 const APInt &One = APInt(SVTBits, 1);
18673 unsigned NumElems = VT.getVectorNumElements();
18675 for (unsigned i=0; i !=NumElems; ++i) {
18676 SDValue Op = Amt->getOperand(i);
18677 if (Op->getOpcode() == ISD::UNDEF) {
18678 Elts.push_back(Op);
18682 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18683 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18684 uint64_t ShAmt = C.getZExtValue();
18685 if (ShAmt >= SVTBits) {
18686 Elts.push_back(DAG.getUNDEF(SVT));
18689 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18691 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18692 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18695 // Lower SHL with variable shift amount.
18696 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18697 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18699 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18700 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18701 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18702 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18705 // If possible, lower this shift as a sequence of two shifts by
18706 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18708 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18710 // Could be rewritten as:
18711 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18713 // The advantage is that the two shifts from the example would be
18714 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18715 // the vector shift into four scalar shifts plus four pairs of vector
18717 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18718 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18719 unsigned TargetOpcode = X86ISD::MOVSS;
18720 bool CanBeSimplified;
18721 // The splat value for the first packed shift (the 'X' from the example).
18722 SDValue Amt1 = Amt->getOperand(0);
18723 // The splat value for the second packed shift (the 'Y' from the example).
18724 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18725 Amt->getOperand(2);
18727 // See if it is possible to replace this node with a sequence of
18728 // two shifts followed by a MOVSS/MOVSD
18729 if (VT == MVT::v4i32) {
18730 // Check if it is legal to use a MOVSS.
18731 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18732 Amt2 == Amt->getOperand(3);
18733 if (!CanBeSimplified) {
18734 // Otherwise, check if we can still simplify this node using a MOVSD.
18735 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18736 Amt->getOperand(2) == Amt->getOperand(3);
18737 TargetOpcode = X86ISD::MOVSD;
18738 Amt2 = Amt->getOperand(2);
18741 // Do similar checks for the case where the machine value type
18743 CanBeSimplified = Amt1 == Amt->getOperand(1);
18744 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18745 CanBeSimplified = Amt2 == Amt->getOperand(i);
18747 if (!CanBeSimplified) {
18748 TargetOpcode = X86ISD::MOVSD;
18749 CanBeSimplified = true;
18750 Amt2 = Amt->getOperand(4);
18751 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18752 CanBeSimplified = Amt1 == Amt->getOperand(i);
18753 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18754 CanBeSimplified = Amt2 == Amt->getOperand(j);
18758 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18759 isa<ConstantSDNode>(Amt2)) {
18760 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18761 EVT CastVT = MVT::v4i32;
18763 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18764 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18766 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18767 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18768 if (TargetOpcode == X86ISD::MOVSD)
18769 CastVT = MVT::v2i64;
18770 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18771 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18772 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18774 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18778 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18779 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18782 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18783 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18785 // Turn 'a' into a mask suitable for VSELECT
18786 SDValue VSelM = DAG.getConstant(0x80, VT);
18787 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18788 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18790 SDValue CM1 = DAG.getConstant(0x0f, VT);
18791 SDValue CM2 = DAG.getConstant(0x3f, VT);
18793 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18794 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18795 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18796 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18797 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18800 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18801 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18802 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18804 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18805 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18806 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18807 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18808 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18811 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18812 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18813 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18815 // return VSELECT(r, r+r, a);
18816 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18817 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18821 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18822 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18823 // solution better.
18824 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18825 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18827 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18828 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18829 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18830 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18831 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18834 // Decompose 256-bit shifts into smaller 128-bit shifts.
18835 if (VT.is256BitVector()) {
18836 unsigned NumElems = VT.getVectorNumElements();
18837 MVT EltVT = VT.getVectorElementType();
18838 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18840 // Extract the two vectors
18841 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18842 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18844 // Recreate the shift amount vectors
18845 SDValue Amt1, Amt2;
18846 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18847 // Constant shift amount
18848 SmallVector<SDValue, 4> Amt1Csts;
18849 SmallVector<SDValue, 4> Amt2Csts;
18850 for (unsigned i = 0; i != NumElems/2; ++i)
18851 Amt1Csts.push_back(Amt->getOperand(i));
18852 for (unsigned i = NumElems/2; i != NumElems; ++i)
18853 Amt2Csts.push_back(Amt->getOperand(i));
18855 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18856 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18858 // Variable shift amount
18859 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18860 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18863 // Issue new vector shifts for the smaller types
18864 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18865 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18867 // Concatenate the result back
18868 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18874 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18875 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18876 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18877 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18878 // has only one use.
18879 SDNode *N = Op.getNode();
18880 SDValue LHS = N->getOperand(0);
18881 SDValue RHS = N->getOperand(1);
18882 unsigned BaseOp = 0;
18885 switch (Op.getOpcode()) {
18886 default: llvm_unreachable("Unknown ovf instruction!");
18888 // A subtract of one will be selected as a INC. Note that INC doesn't
18889 // set CF, so we can't do this for UADDO.
18890 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18892 BaseOp = X86ISD::INC;
18893 Cond = X86::COND_O;
18896 BaseOp = X86ISD::ADD;
18897 Cond = X86::COND_O;
18900 BaseOp = X86ISD::ADD;
18901 Cond = X86::COND_B;
18904 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18905 // set CF, so we can't do this for USUBO.
18906 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18908 BaseOp = X86ISD::DEC;
18909 Cond = X86::COND_O;
18912 BaseOp = X86ISD::SUB;
18913 Cond = X86::COND_O;
18916 BaseOp = X86ISD::SUB;
18917 Cond = X86::COND_B;
18920 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18921 Cond = X86::COND_O;
18923 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18924 if (N->getValueType(0) == MVT::i8) {
18925 BaseOp = X86ISD::UMUL8;
18926 Cond = X86::COND_O;
18929 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18931 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18934 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18935 DAG.getConstant(X86::COND_O, MVT::i32),
18936 SDValue(Sum.getNode(), 2));
18938 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18942 // Also sets EFLAGS.
18943 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18944 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18947 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18948 DAG.getConstant(Cond, MVT::i32),
18949 SDValue(Sum.getNode(), 1));
18951 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18954 // Sign extension of the low part of vector elements. This may be used either
18955 // when sign extend instructions are not available or if the vector element
18956 // sizes already match the sign-extended size. If the vector elements are in
18957 // their pre-extended size and sign extend instructions are available, that will
18958 // be handled by LowerSIGN_EXTEND.
18959 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18960 SelectionDAG &DAG) const {
18962 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18963 MVT VT = Op.getSimpleValueType();
18965 if (!Subtarget->hasSSE2() || !VT.isVector())
18968 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18969 ExtraVT.getScalarType().getSizeInBits();
18971 switch (VT.SimpleTy) {
18972 default: return SDValue();
18975 if (!Subtarget->hasFp256())
18977 if (!Subtarget->hasInt256()) {
18978 // needs to be split
18979 unsigned NumElems = VT.getVectorNumElements();
18981 // Extract the LHS vectors
18982 SDValue LHS = Op.getOperand(0);
18983 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18984 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18986 MVT EltVT = VT.getVectorElementType();
18987 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18989 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18990 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18991 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18993 SDValue Extra = DAG.getValueType(ExtraVT);
18995 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18996 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18998 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
19003 SDValue Op0 = Op.getOperand(0);
19005 // This is a sign extension of some low part of vector elements without
19006 // changing the size of the vector elements themselves:
19007 // Shift-Left + Shift-Right-Algebraic.
19008 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
19010 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
19016 /// Returns true if the operand type is exactly twice the native width, and
19017 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19018 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19019 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19020 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
19021 const X86Subtarget &Subtarget =
19022 getTargetMachine().getSubtarget<X86Subtarget>();
19023 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19026 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19027 else if (OpWidth == 128)
19028 return Subtarget.hasCmpxchg16b();
19033 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19034 return needsCmpXchgNb(SI->getValueOperand()->getType());
19037 // Note: this turns large loads into lock cmpxchg8b/16b.
19038 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19039 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19040 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19041 return needsCmpXchgNb(PTy->getElementType());
19044 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19045 const X86Subtarget &Subtarget =
19046 getTargetMachine().getSubtarget<X86Subtarget>();
19047 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19048 const Type *MemType = AI->getType();
19050 // If the operand is too big, we must see if cmpxchg8/16b is available
19051 // and default to library calls otherwise.
19052 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19053 return needsCmpXchgNb(MemType);
19055 AtomicRMWInst::BinOp Op = AI->getOperation();
19058 llvm_unreachable("Unknown atomic operation");
19059 case AtomicRMWInst::Xchg:
19060 case AtomicRMWInst::Add:
19061 case AtomicRMWInst::Sub:
19062 // It's better to use xadd, xsub or xchg for these in all cases.
19064 case AtomicRMWInst::Or:
19065 case AtomicRMWInst::And:
19066 case AtomicRMWInst::Xor:
19067 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19068 // prefix to a normal instruction for these operations.
19069 return !AI->use_empty();
19070 case AtomicRMWInst::Nand:
19071 case AtomicRMWInst::Max:
19072 case AtomicRMWInst::Min:
19073 case AtomicRMWInst::UMax:
19074 case AtomicRMWInst::UMin:
19075 // These always require a non-trivial set of data operations on x86. We must
19076 // use a cmpxchg loop.
19081 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19082 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19083 // no-sse2). There isn't any reason to disable it if the target processor
19085 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19089 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19090 const X86Subtarget &Subtarget =
19091 getTargetMachine().getSubtarget<X86Subtarget>();
19092 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19093 const Type *MemType = AI->getType();
19094 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19095 // there is no benefit in turning such RMWs into loads, and it is actually
19096 // harmful as it introduces a mfence.
19097 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19100 auto Builder = IRBuilder<>(AI);
19101 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19102 auto SynchScope = AI->getSynchScope();
19103 // We must restrict the ordering to avoid generating loads with Release or
19104 // ReleaseAcquire orderings.
19105 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19106 auto Ptr = AI->getPointerOperand();
19108 // Before the load we need a fence. Here is an example lifted from
19109 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19112 // x.store(1, relaxed);
19113 // r1 = y.fetch_add(0, release);
19115 // y.fetch_add(42, acquire);
19116 // r2 = x.load(relaxed);
19117 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19118 // lowered to just a load without a fence. A mfence flushes the store buffer,
19119 // making the optimization clearly correct.
19120 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19121 // otherwise, we might be able to be more agressive on relaxed idempotent
19122 // rmw. In practice, they do not look useful, so we don't try to be
19123 // especially clever.
19124 if (SynchScope == SingleThread) {
19125 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19126 // the IR level, so we must wrap it in an intrinsic.
19128 } else if (hasMFENCE(Subtarget)) {
19129 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19130 Intrinsic::x86_sse2_mfence);
19131 Builder.CreateCall(MFence);
19133 // FIXME: it might make sense to use a locked operation here but on a
19134 // different cache-line to prevent cache-line bouncing. In practice it
19135 // is probably a small win, and x86 processors without mfence are rare
19136 // enough that we do not bother.
19140 // Finally we can emit the atomic load.
19141 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19142 AI->getType()->getPrimitiveSizeInBits());
19143 Loaded->setAtomic(Order, SynchScope);
19144 AI->replaceAllUsesWith(Loaded);
19145 AI->eraseFromParent();
19149 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19150 SelectionDAG &DAG) {
19152 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19153 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19154 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19155 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19157 // The only fence that needs an instruction is a sequentially-consistent
19158 // cross-thread fence.
19159 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19160 if (hasMFENCE(*Subtarget))
19161 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19163 SDValue Chain = Op.getOperand(0);
19164 SDValue Zero = DAG.getConstant(0, MVT::i32);
19166 DAG.getRegister(X86::ESP, MVT::i32), // Base
19167 DAG.getTargetConstant(1, MVT::i8), // Scale
19168 DAG.getRegister(0, MVT::i32), // Index
19169 DAG.getTargetConstant(0, MVT::i32), // Disp
19170 DAG.getRegister(0, MVT::i32), // Segment.
19174 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19175 return SDValue(Res, 0);
19178 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19179 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19182 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19183 SelectionDAG &DAG) {
19184 MVT T = Op.getSimpleValueType();
19188 switch(T.SimpleTy) {
19189 default: llvm_unreachable("Invalid value type!");
19190 case MVT::i8: Reg = X86::AL; size = 1; break;
19191 case MVT::i16: Reg = X86::AX; size = 2; break;
19192 case MVT::i32: Reg = X86::EAX; size = 4; break;
19194 assert(Subtarget->is64Bit() && "Node not type legal!");
19195 Reg = X86::RAX; size = 8;
19198 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19199 Op.getOperand(2), SDValue());
19200 SDValue Ops[] = { cpIn.getValue(0),
19203 DAG.getTargetConstant(size, MVT::i8),
19204 cpIn.getValue(1) };
19205 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19206 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19207 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19211 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19212 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19213 MVT::i32, cpOut.getValue(2));
19214 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19215 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19217 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19218 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19219 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19223 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19224 SelectionDAG &DAG) {
19225 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19226 MVT DstVT = Op.getSimpleValueType();
19228 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19229 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19230 if (DstVT != MVT::f64)
19231 // This conversion needs to be expanded.
19234 SDValue InVec = Op->getOperand(0);
19236 unsigned NumElts = SrcVT.getVectorNumElements();
19237 EVT SVT = SrcVT.getVectorElementType();
19239 // Widen the vector in input in the case of MVT::v2i32.
19240 // Example: from MVT::v2i32 to MVT::v4i32.
19241 SmallVector<SDValue, 16> Elts;
19242 for (unsigned i = 0, e = NumElts; i != e; ++i)
19243 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19244 DAG.getIntPtrConstant(i)));
19246 // Explicitly mark the extra elements as Undef.
19247 SDValue Undef = DAG.getUNDEF(SVT);
19248 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19249 Elts.push_back(Undef);
19251 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19252 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19253 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19254 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19255 DAG.getIntPtrConstant(0));
19258 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19259 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19260 assert((DstVT == MVT::i64 ||
19261 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19262 "Unexpected custom BITCAST");
19263 // i64 <=> MMX conversions are Legal.
19264 if (SrcVT==MVT::i64 && DstVT.isVector())
19266 if (DstVT==MVT::i64 && SrcVT.isVector())
19268 // MMX <=> MMX conversions are Legal.
19269 if (SrcVT.isVector() && DstVT.isVector())
19271 // All other conversions need to be expanded.
19275 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19276 SelectionDAG &DAG) {
19277 SDNode *Node = Op.getNode();
19280 Op = Op.getOperand(0);
19281 EVT VT = Op.getValueType();
19282 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19283 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19285 unsigned NumElts = VT.getVectorNumElements();
19286 EVT EltVT = VT.getVectorElementType();
19287 unsigned Len = EltVT.getSizeInBits();
19289 // This is the vectorized version of the "best" algorithm from
19290 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19291 // with a minor tweak to use a series of adds + shifts instead of vector
19292 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19294 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19295 // v8i32 => Always profitable
19297 // FIXME: There a couple of possible improvements:
19299 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19300 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19302 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19303 "CTPOP not implemented for this vector element type.");
19305 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19306 // extra legalization.
19307 bool NeedsBitcast = EltVT == MVT::i32;
19308 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19310 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19311 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19312 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19314 // v = v - ((v >> 1) & 0x55555555...)
19315 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19316 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19317 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19319 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19321 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19322 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19324 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19326 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19327 if (VT != And.getValueType())
19328 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19329 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19331 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19332 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19333 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19334 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19335 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19337 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19338 if (NeedsBitcast) {
19339 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19340 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19341 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19344 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19345 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19346 if (VT != AndRHS.getValueType()) {
19347 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19348 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19350 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19352 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19353 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19354 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19355 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19356 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19358 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19359 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19360 if (NeedsBitcast) {
19361 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19362 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19364 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19365 if (VT != And.getValueType())
19366 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19368 // The algorithm mentioned above uses:
19369 // v = (v * 0x01010101...) >> (Len - 8)
19371 // Change it to use vector adds + vector shifts which yield faster results on
19372 // Haswell than using vector integer multiplication.
19374 // For i32 elements:
19375 // v = v + (v >> 8)
19376 // v = v + (v >> 16)
19378 // For i64 elements:
19379 // v = v + (v >> 8)
19380 // v = v + (v >> 16)
19381 // v = v + (v >> 32)
19384 SmallVector<SDValue, 8> Csts;
19385 for (unsigned i = 8; i <= Len/2; i *= 2) {
19386 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19387 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19388 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19389 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19393 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19394 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19395 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19396 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19397 if (NeedsBitcast) {
19398 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19399 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19401 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19402 if (VT != And.getValueType())
19403 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19408 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19409 SDNode *Node = Op.getNode();
19411 EVT T = Node->getValueType(0);
19412 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19413 DAG.getConstant(0, T), Node->getOperand(2));
19414 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19415 cast<AtomicSDNode>(Node)->getMemoryVT(),
19416 Node->getOperand(0),
19417 Node->getOperand(1), negOp,
19418 cast<AtomicSDNode>(Node)->getMemOperand(),
19419 cast<AtomicSDNode>(Node)->getOrdering(),
19420 cast<AtomicSDNode>(Node)->getSynchScope());
19423 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19424 SDNode *Node = Op.getNode();
19426 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19428 // Convert seq_cst store -> xchg
19429 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19430 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19431 // (The only way to get a 16-byte store is cmpxchg16b)
19432 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19433 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19434 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19435 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19436 cast<AtomicSDNode>(Node)->getMemoryVT(),
19437 Node->getOperand(0),
19438 Node->getOperand(1), Node->getOperand(2),
19439 cast<AtomicSDNode>(Node)->getMemOperand(),
19440 cast<AtomicSDNode>(Node)->getOrdering(),
19441 cast<AtomicSDNode>(Node)->getSynchScope());
19442 return Swap.getValue(1);
19444 // Other atomic stores have a simple pattern.
19448 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19449 EVT VT = Op.getNode()->getSimpleValueType(0);
19451 // Let legalize expand this if it isn't a legal type yet.
19452 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19455 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19458 bool ExtraOp = false;
19459 switch (Op.getOpcode()) {
19460 default: llvm_unreachable("Invalid code");
19461 case ISD::ADDC: Opc = X86ISD::ADD; break;
19462 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19463 case ISD::SUBC: Opc = X86ISD::SUB; break;
19464 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19468 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19470 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19471 Op.getOperand(1), Op.getOperand(2));
19474 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19475 SelectionDAG &DAG) {
19476 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19478 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19479 // which returns the values as { float, float } (in XMM0) or
19480 // { double, double } (which is returned in XMM0, XMM1).
19482 SDValue Arg = Op.getOperand(0);
19483 EVT ArgVT = Arg.getValueType();
19484 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19486 TargetLowering::ArgListTy Args;
19487 TargetLowering::ArgListEntry Entry;
19491 Entry.isSExt = false;
19492 Entry.isZExt = false;
19493 Args.push_back(Entry);
19495 bool isF64 = ArgVT == MVT::f64;
19496 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19497 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19498 // the results are returned via SRet in memory.
19499 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19500 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19501 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19503 Type *RetTy = isF64
19504 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19505 : (Type*)VectorType::get(ArgTy, 4);
19507 TargetLowering::CallLoweringInfo CLI(DAG);
19508 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19509 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19511 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19514 // Returned in xmm0 and xmm1.
19515 return CallResult.first;
19517 // Returned in bits 0:31 and 32:64 xmm0.
19518 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19519 CallResult.first, DAG.getIntPtrConstant(0));
19520 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19521 CallResult.first, DAG.getIntPtrConstant(1));
19522 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19523 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19526 /// LowerOperation - Provide custom lowering hooks for some operations.
19528 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19529 switch (Op.getOpcode()) {
19530 default: llvm_unreachable("Should not custom lower this!");
19531 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19532 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19533 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19534 return LowerCMP_SWAP(Op, Subtarget, DAG);
19535 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19536 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19537 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19538 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19539 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19540 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19541 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19542 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19543 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19544 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19545 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19546 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19547 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19548 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19549 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19550 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19551 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19552 case ISD::SHL_PARTS:
19553 case ISD::SRA_PARTS:
19554 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19555 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19556 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19557 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19558 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19559 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19560 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19561 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19562 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19563 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19564 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19566 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19567 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19568 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19569 case ISD::SETCC: return LowerSETCC(Op, DAG);
19570 case ISD::SELECT: return LowerSELECT(Op, DAG);
19571 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19572 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19573 case ISD::VASTART: return LowerVASTART(Op, DAG);
19574 case ISD::VAARG: return LowerVAARG(Op, DAG);
19575 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19576 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19577 case ISD::INTRINSIC_VOID:
19578 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19579 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19580 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19581 case ISD::FRAME_TO_ARGS_OFFSET:
19582 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19583 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19584 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19585 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19586 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19587 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19588 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19589 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19590 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19591 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19592 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19593 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19594 case ISD::UMUL_LOHI:
19595 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19598 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19604 case ISD::UMULO: return LowerXALUO(Op, DAG);
19605 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19606 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19610 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19611 case ISD::ADD: return LowerADD(Op, DAG);
19612 case ISD::SUB: return LowerSUB(Op, DAG);
19613 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19617 /// ReplaceNodeResults - Replace a node with an illegal result type
19618 /// with a new node built out of custom code.
19619 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19620 SmallVectorImpl<SDValue>&Results,
19621 SelectionDAG &DAG) const {
19623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19624 switch (N->getOpcode()) {
19626 llvm_unreachable("Do not know how to custom type legalize this operation!");
19627 case ISD::SIGN_EXTEND_INREG:
19632 // We don't want to expand or promote these.
19639 case ISD::UDIVREM: {
19640 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19641 Results.push_back(V);
19644 case ISD::FP_TO_SINT:
19645 case ISD::FP_TO_UINT: {
19646 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19648 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19651 std::pair<SDValue,SDValue> Vals =
19652 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19653 SDValue FIST = Vals.first, StackSlot = Vals.second;
19654 if (FIST.getNode()) {
19655 EVT VT = N->getValueType(0);
19656 // Return a load from the stack slot.
19657 if (StackSlot.getNode())
19658 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19659 MachinePointerInfo(),
19660 false, false, false, 0));
19662 Results.push_back(FIST);
19666 case ISD::UINT_TO_FP: {
19667 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19668 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19669 N->getValueType(0) != MVT::v2f32)
19671 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19673 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19675 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19676 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19677 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19678 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19679 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19680 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19683 case ISD::FP_ROUND: {
19684 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19686 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19687 Results.push_back(V);
19690 case ISD::INTRINSIC_W_CHAIN: {
19691 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19693 default : llvm_unreachable("Do not know how to custom type "
19694 "legalize this intrinsic operation!");
19695 case Intrinsic::x86_rdtsc:
19696 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19698 case Intrinsic::x86_rdtscp:
19699 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19701 case Intrinsic::x86_rdpmc:
19702 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19705 case ISD::READCYCLECOUNTER: {
19706 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19709 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19710 EVT T = N->getValueType(0);
19711 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19712 bool Regs64bit = T == MVT::i128;
19713 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19714 SDValue cpInL, cpInH;
19715 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19716 DAG.getConstant(0, HalfT));
19717 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19718 DAG.getConstant(1, HalfT));
19719 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19720 Regs64bit ? X86::RAX : X86::EAX,
19722 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19723 Regs64bit ? X86::RDX : X86::EDX,
19724 cpInH, cpInL.getValue(1));
19725 SDValue swapInL, swapInH;
19726 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19727 DAG.getConstant(0, HalfT));
19728 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19729 DAG.getConstant(1, HalfT));
19730 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19731 Regs64bit ? X86::RBX : X86::EBX,
19732 swapInL, cpInH.getValue(1));
19733 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19734 Regs64bit ? X86::RCX : X86::ECX,
19735 swapInH, swapInL.getValue(1));
19736 SDValue Ops[] = { swapInH.getValue(0),
19738 swapInH.getValue(1) };
19739 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19740 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19741 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19742 X86ISD::LCMPXCHG8_DAG;
19743 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19744 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19745 Regs64bit ? X86::RAX : X86::EAX,
19746 HalfT, Result.getValue(1));
19747 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19748 Regs64bit ? X86::RDX : X86::EDX,
19749 HalfT, cpOutL.getValue(2));
19750 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19752 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19753 MVT::i32, cpOutH.getValue(2));
19755 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19756 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19757 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19759 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19760 Results.push_back(Success);
19761 Results.push_back(EFLAGS.getValue(1));
19764 case ISD::ATOMIC_SWAP:
19765 case ISD::ATOMIC_LOAD_ADD:
19766 case ISD::ATOMIC_LOAD_SUB:
19767 case ISD::ATOMIC_LOAD_AND:
19768 case ISD::ATOMIC_LOAD_OR:
19769 case ISD::ATOMIC_LOAD_XOR:
19770 case ISD::ATOMIC_LOAD_NAND:
19771 case ISD::ATOMIC_LOAD_MIN:
19772 case ISD::ATOMIC_LOAD_MAX:
19773 case ISD::ATOMIC_LOAD_UMIN:
19774 case ISD::ATOMIC_LOAD_UMAX:
19775 case ISD::ATOMIC_LOAD: {
19776 // Delegate to generic TypeLegalization. Situations we can really handle
19777 // should have already been dealt with by AtomicExpandPass.cpp.
19780 case ISD::BITCAST: {
19781 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19782 EVT DstVT = N->getValueType(0);
19783 EVT SrcVT = N->getOperand(0)->getValueType(0);
19785 if (SrcVT != MVT::f64 ||
19786 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19789 unsigned NumElts = DstVT.getVectorNumElements();
19790 EVT SVT = DstVT.getVectorElementType();
19791 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19792 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19793 MVT::v2f64, N->getOperand(0));
19794 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19796 if (ExperimentalVectorWideningLegalization) {
19797 // If we are legalizing vectors by widening, we already have the desired
19798 // legal vector type, just return it.
19799 Results.push_back(ToVecInt);
19803 SmallVector<SDValue, 8> Elts;
19804 for (unsigned i = 0, e = NumElts; i != e; ++i)
19805 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19806 ToVecInt, DAG.getIntPtrConstant(i)));
19808 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19813 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19815 default: return nullptr;
19816 case X86ISD::BSF: return "X86ISD::BSF";
19817 case X86ISD::BSR: return "X86ISD::BSR";
19818 case X86ISD::SHLD: return "X86ISD::SHLD";
19819 case X86ISD::SHRD: return "X86ISD::SHRD";
19820 case X86ISD::FAND: return "X86ISD::FAND";
19821 case X86ISD::FANDN: return "X86ISD::FANDN";
19822 case X86ISD::FOR: return "X86ISD::FOR";
19823 case X86ISD::FXOR: return "X86ISD::FXOR";
19824 case X86ISD::FSRL: return "X86ISD::FSRL";
19825 case X86ISD::FILD: return "X86ISD::FILD";
19826 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19827 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19828 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19829 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19830 case X86ISD::FLD: return "X86ISD::FLD";
19831 case X86ISD::FST: return "X86ISD::FST";
19832 case X86ISD::CALL: return "X86ISD::CALL";
19833 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19834 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19835 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19836 case X86ISD::BT: return "X86ISD::BT";
19837 case X86ISD::CMP: return "X86ISD::CMP";
19838 case X86ISD::COMI: return "X86ISD::COMI";
19839 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19840 case X86ISD::CMPM: return "X86ISD::CMPM";
19841 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19842 case X86ISD::SETCC: return "X86ISD::SETCC";
19843 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19844 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19845 case X86ISD::CMOV: return "X86ISD::CMOV";
19846 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19847 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19848 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19849 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19850 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19851 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19852 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19853 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19854 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19855 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19856 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19857 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19858 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19859 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19860 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19861 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19862 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19863 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19864 case X86ISD::HADD: return "X86ISD::HADD";
19865 case X86ISD::HSUB: return "X86ISD::HSUB";
19866 case X86ISD::FHADD: return "X86ISD::FHADD";
19867 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19868 case X86ISD::UMAX: return "X86ISD::UMAX";
19869 case X86ISD::UMIN: return "X86ISD::UMIN";
19870 case X86ISD::SMAX: return "X86ISD::SMAX";
19871 case X86ISD::SMIN: return "X86ISD::SMIN";
19872 case X86ISD::FMAX: return "X86ISD::FMAX";
19873 case X86ISD::FMIN: return "X86ISD::FMIN";
19874 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19875 case X86ISD::FMINC: return "X86ISD::FMINC";
19876 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19877 case X86ISD::FRCP: return "X86ISD::FRCP";
19878 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19879 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19880 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19881 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19882 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19883 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19884 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19885 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19886 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19887 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19888 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19889 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19890 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19891 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19892 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19893 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19894 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19895 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19896 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19897 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19898 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19899 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19900 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19901 case X86ISD::VSHL: return "X86ISD::VSHL";
19902 case X86ISD::VSRL: return "X86ISD::VSRL";
19903 case X86ISD::VSRA: return "X86ISD::VSRA";
19904 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19905 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19906 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19907 case X86ISD::CMPP: return "X86ISD::CMPP";
19908 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19909 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19910 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19911 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19912 case X86ISD::ADD: return "X86ISD::ADD";
19913 case X86ISD::SUB: return "X86ISD::SUB";
19914 case X86ISD::ADC: return "X86ISD::ADC";
19915 case X86ISD::SBB: return "X86ISD::SBB";
19916 case X86ISD::SMUL: return "X86ISD::SMUL";
19917 case X86ISD::UMUL: return "X86ISD::UMUL";
19918 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19919 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19920 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19921 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19922 case X86ISD::INC: return "X86ISD::INC";
19923 case X86ISD::DEC: return "X86ISD::DEC";
19924 case X86ISD::OR: return "X86ISD::OR";
19925 case X86ISD::XOR: return "X86ISD::XOR";
19926 case X86ISD::AND: return "X86ISD::AND";
19927 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19928 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19929 case X86ISD::PTEST: return "X86ISD::PTEST";
19930 case X86ISD::TESTP: return "X86ISD::TESTP";
19931 case X86ISD::TESTM: return "X86ISD::TESTM";
19932 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19933 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19934 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19935 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19936 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19937 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19938 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19939 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19940 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19941 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19942 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19943 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19944 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19945 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19946 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19947 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19948 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19949 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19950 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19951 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19952 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19953 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19954 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19955 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19956 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19957 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19958 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19959 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19960 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19961 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19962 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19963 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19964 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19965 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19966 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19967 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19968 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19969 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19970 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19971 case X86ISD::SAHF: return "X86ISD::SAHF";
19972 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19973 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19974 case X86ISD::FMADD: return "X86ISD::FMADD";
19975 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19976 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19977 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19978 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19979 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19980 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19981 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19982 case X86ISD::XTEST: return "X86ISD::XTEST";
19983 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19984 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19985 case X86ISD::SELECT: return "X86ISD::SELECT";
19989 // isLegalAddressingMode - Return true if the addressing mode represented
19990 // by AM is legal for this target, for a load/store of the specified type.
19991 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19993 // X86 supports extremely general addressing modes.
19994 CodeModel::Model M = getTargetMachine().getCodeModel();
19995 Reloc::Model R = getTargetMachine().getRelocationModel();
19997 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19998 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20003 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20005 // If a reference to this global requires an extra load, we can't fold it.
20006 if (isGlobalStubReference(GVFlags))
20009 // If BaseGV requires a register for the PIC base, we cannot also have a
20010 // BaseReg specified.
20011 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20014 // If lower 4G is not available, then we must use rip-relative addressing.
20015 if ((M != CodeModel::Small || R != Reloc::Static) &&
20016 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20020 switch (AM.Scale) {
20026 // These scales always work.
20031 // These scales are formed with basereg+scalereg. Only accept if there is
20036 default: // Other stuff never works.
20043 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20044 unsigned Bits = Ty->getScalarSizeInBits();
20046 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20047 // particularly cheaper than those without.
20051 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20052 // variable shifts just as cheap as scalar ones.
20053 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20056 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20057 // fully general vector.
20061 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20062 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20064 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20065 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20066 return NumBits1 > NumBits2;
20069 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20070 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20073 if (!isTypeLegal(EVT::getEVT(Ty1)))
20076 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20078 // Assuming the caller doesn't have a zeroext or signext return parameter,
20079 // truncation all the way down to i1 is valid.
20083 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20084 return isInt<32>(Imm);
20087 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20088 // Can also use sub to handle negated immediates.
20089 return isInt<32>(Imm);
20092 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20093 if (!VT1.isInteger() || !VT2.isInteger())
20095 unsigned NumBits1 = VT1.getSizeInBits();
20096 unsigned NumBits2 = VT2.getSizeInBits();
20097 return NumBits1 > NumBits2;
20100 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20101 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20102 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20105 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20106 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20107 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20110 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20111 EVT VT1 = Val.getValueType();
20112 if (isZExtFree(VT1, VT2))
20115 if (Val.getOpcode() != ISD::LOAD)
20118 if (!VT1.isSimple() || !VT1.isInteger() ||
20119 !VT2.isSimple() || !VT2.isInteger())
20122 switch (VT1.getSimpleVT().SimpleTy) {
20127 // X86 has 8, 16, and 32-bit zero-extending loads.
20135 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20136 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20139 VT = VT.getScalarType();
20141 if (!VT.isSimple())
20144 switch (VT.getSimpleVT().SimpleTy) {
20155 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20156 // i16 instructions are longer (0x66 prefix) and potentially slower.
20157 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20160 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20161 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20162 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20163 /// are assumed to be legal.
20165 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20167 if (!VT.isSimple())
20170 MVT SVT = VT.getSimpleVT();
20172 // Very little shuffling can be done for 64-bit vectors right now.
20173 if (VT.getSizeInBits() == 64)
20176 // This is an experimental legality test that is tailored to match the
20177 // legality test of the experimental lowering more closely. They are gated
20178 // separately to ease testing of performance differences.
20179 if (ExperimentalVectorShuffleLegality)
20180 // We only care that the types being shuffled are legal. The lowering can
20181 // handle any possible shuffle mask that results.
20182 return isTypeLegal(SVT);
20184 // If this is a single-input shuffle with no 128 bit lane crossings we can
20185 // lower it into pshufb.
20186 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20187 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20188 bool isLegal = true;
20189 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20190 if (M[I] >= (int)SVT.getVectorNumElements() ||
20191 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20200 // FIXME: blends, shifts.
20201 return (SVT.getVectorNumElements() == 2 ||
20202 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20203 isMOVLMask(M, SVT) ||
20204 isCommutedMOVLMask(M, SVT) ||
20205 isMOVHLPSMask(M, SVT) ||
20206 isSHUFPMask(M, SVT) ||
20207 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20208 isPSHUFDMask(M, SVT) ||
20209 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20210 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20211 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20212 isPALIGNRMask(M, SVT, Subtarget) ||
20213 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20214 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20215 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20216 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20217 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20218 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20222 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20224 if (!VT.isSimple())
20227 MVT SVT = VT.getSimpleVT();
20229 // This is an experimental legality test that is tailored to match the
20230 // legality test of the experimental lowering more closely. They are gated
20231 // separately to ease testing of performance differences.
20232 if (ExperimentalVectorShuffleLegality)
20233 // The new vector shuffle lowering is very good at managing zero-inputs.
20234 return isShuffleMaskLegal(Mask, VT);
20236 unsigned NumElts = SVT.getVectorNumElements();
20237 // FIXME: This collection of masks seems suspect.
20240 if (NumElts == 4 && SVT.is128BitVector()) {
20241 return (isMOVLMask(Mask, SVT) ||
20242 isCommutedMOVLMask(Mask, SVT, true) ||
20243 isSHUFPMask(Mask, SVT) ||
20244 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20245 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20246 Subtarget->hasInt256()));
20251 //===----------------------------------------------------------------------===//
20252 // X86 Scheduler Hooks
20253 //===----------------------------------------------------------------------===//
20255 /// Utility function to emit xbegin specifying the start of an RTM region.
20256 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20257 const TargetInstrInfo *TII) {
20258 DebugLoc DL = MI->getDebugLoc();
20260 const BasicBlock *BB = MBB->getBasicBlock();
20261 MachineFunction::iterator I = MBB;
20264 // For the v = xbegin(), we generate
20275 MachineBasicBlock *thisMBB = MBB;
20276 MachineFunction *MF = MBB->getParent();
20277 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20278 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20279 MF->insert(I, mainMBB);
20280 MF->insert(I, sinkMBB);
20282 // Transfer the remainder of BB and its successor edges to sinkMBB.
20283 sinkMBB->splice(sinkMBB->begin(), MBB,
20284 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20285 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20289 // # fallthrough to mainMBB
20290 // # abortion to sinkMBB
20291 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20292 thisMBB->addSuccessor(mainMBB);
20293 thisMBB->addSuccessor(sinkMBB);
20297 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20298 mainMBB->addSuccessor(sinkMBB);
20301 // EAX is live into the sinkMBB
20302 sinkMBB->addLiveIn(X86::EAX);
20303 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20304 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20307 MI->eraseFromParent();
20311 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20312 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20313 // in the .td file.
20314 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20315 const TargetInstrInfo *TII) {
20317 switch (MI->getOpcode()) {
20318 default: llvm_unreachable("illegal opcode!");
20319 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20320 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20321 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20322 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20323 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20324 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20325 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20326 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20329 DebugLoc dl = MI->getDebugLoc();
20330 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20332 unsigned NumArgs = MI->getNumOperands();
20333 for (unsigned i = 1; i < NumArgs; ++i) {
20334 MachineOperand &Op = MI->getOperand(i);
20335 if (!(Op.isReg() && Op.isImplicit()))
20336 MIB.addOperand(Op);
20338 if (MI->hasOneMemOperand())
20339 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20341 BuildMI(*BB, MI, dl,
20342 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20343 .addReg(X86::XMM0);
20345 MI->eraseFromParent();
20349 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20350 // defs in an instruction pattern
20351 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20352 const TargetInstrInfo *TII) {
20354 switch (MI->getOpcode()) {
20355 default: llvm_unreachable("illegal opcode!");
20356 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20357 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20358 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20359 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20360 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20361 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20362 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20363 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20366 DebugLoc dl = MI->getDebugLoc();
20367 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20369 unsigned NumArgs = MI->getNumOperands(); // remove the results
20370 for (unsigned i = 1; i < NumArgs; ++i) {
20371 MachineOperand &Op = MI->getOperand(i);
20372 if (!(Op.isReg() && Op.isImplicit()))
20373 MIB.addOperand(Op);
20375 if (MI->hasOneMemOperand())
20376 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20378 BuildMI(*BB, MI, dl,
20379 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20382 MI->eraseFromParent();
20386 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20387 const TargetInstrInfo *TII,
20388 const X86Subtarget* Subtarget) {
20389 DebugLoc dl = MI->getDebugLoc();
20391 // Address into RAX/EAX, other two args into ECX, EDX.
20392 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20393 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20394 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20395 for (int i = 0; i < X86::AddrNumOperands; ++i)
20396 MIB.addOperand(MI->getOperand(i));
20398 unsigned ValOps = X86::AddrNumOperands;
20399 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20400 .addReg(MI->getOperand(ValOps).getReg());
20401 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20402 .addReg(MI->getOperand(ValOps+1).getReg());
20404 // The instruction doesn't actually take any operands though.
20405 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20407 MI->eraseFromParent(); // The pseudo is gone now.
20411 MachineBasicBlock *
20412 X86TargetLowering::EmitVAARG64WithCustomInserter(
20414 MachineBasicBlock *MBB) const {
20415 // Emit va_arg instruction on X86-64.
20417 // Operands to this pseudo-instruction:
20418 // 0 ) Output : destination address (reg)
20419 // 1-5) Input : va_list address (addr, i64mem)
20420 // 6 ) ArgSize : Size (in bytes) of vararg type
20421 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20422 // 8 ) Align : Alignment of type
20423 // 9 ) EFLAGS (implicit-def)
20425 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20426 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20428 unsigned DestReg = MI->getOperand(0).getReg();
20429 MachineOperand &Base = MI->getOperand(1);
20430 MachineOperand &Scale = MI->getOperand(2);
20431 MachineOperand &Index = MI->getOperand(3);
20432 MachineOperand &Disp = MI->getOperand(4);
20433 MachineOperand &Segment = MI->getOperand(5);
20434 unsigned ArgSize = MI->getOperand(6).getImm();
20435 unsigned ArgMode = MI->getOperand(7).getImm();
20436 unsigned Align = MI->getOperand(8).getImm();
20438 // Memory Reference
20439 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20440 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20441 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20443 // Machine Information
20444 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20445 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20446 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20447 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20448 DebugLoc DL = MI->getDebugLoc();
20450 // struct va_list {
20453 // i64 overflow_area (address)
20454 // i64 reg_save_area (address)
20456 // sizeof(va_list) = 24
20457 // alignment(va_list) = 8
20459 unsigned TotalNumIntRegs = 6;
20460 unsigned TotalNumXMMRegs = 8;
20461 bool UseGPOffset = (ArgMode == 1);
20462 bool UseFPOffset = (ArgMode == 2);
20463 unsigned MaxOffset = TotalNumIntRegs * 8 +
20464 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20466 /* Align ArgSize to a multiple of 8 */
20467 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20468 bool NeedsAlign = (Align > 8);
20470 MachineBasicBlock *thisMBB = MBB;
20471 MachineBasicBlock *overflowMBB;
20472 MachineBasicBlock *offsetMBB;
20473 MachineBasicBlock *endMBB;
20475 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20476 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20477 unsigned OffsetReg = 0;
20479 if (!UseGPOffset && !UseFPOffset) {
20480 // If we only pull from the overflow region, we don't create a branch.
20481 // We don't need to alter control flow.
20482 OffsetDestReg = 0; // unused
20483 OverflowDestReg = DestReg;
20485 offsetMBB = nullptr;
20486 overflowMBB = thisMBB;
20489 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20490 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20491 // If not, pull from overflow_area. (branch to overflowMBB)
20496 // offsetMBB overflowMBB
20501 // Registers for the PHI in endMBB
20502 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20503 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20505 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20506 MachineFunction *MF = MBB->getParent();
20507 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20508 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20509 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20511 MachineFunction::iterator MBBIter = MBB;
20514 // Insert the new basic blocks
20515 MF->insert(MBBIter, offsetMBB);
20516 MF->insert(MBBIter, overflowMBB);
20517 MF->insert(MBBIter, endMBB);
20519 // Transfer the remainder of MBB and its successor edges to endMBB.
20520 endMBB->splice(endMBB->begin(), thisMBB,
20521 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20522 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20524 // Make offsetMBB and overflowMBB successors of thisMBB
20525 thisMBB->addSuccessor(offsetMBB);
20526 thisMBB->addSuccessor(overflowMBB);
20528 // endMBB is a successor of both offsetMBB and overflowMBB
20529 offsetMBB->addSuccessor(endMBB);
20530 overflowMBB->addSuccessor(endMBB);
20532 // Load the offset value into a register
20533 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20534 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20538 .addDisp(Disp, UseFPOffset ? 4 : 0)
20539 .addOperand(Segment)
20540 .setMemRefs(MMOBegin, MMOEnd);
20542 // Check if there is enough room left to pull this argument.
20543 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20545 .addImm(MaxOffset + 8 - ArgSizeA8);
20547 // Branch to "overflowMBB" if offset >= max
20548 // Fall through to "offsetMBB" otherwise
20549 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20550 .addMBB(overflowMBB);
20553 // In offsetMBB, emit code to use the reg_save_area.
20555 assert(OffsetReg != 0);
20557 // Read the reg_save_area address.
20558 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20559 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20564 .addOperand(Segment)
20565 .setMemRefs(MMOBegin, MMOEnd);
20567 // Zero-extend the offset
20568 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20569 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20572 .addImm(X86::sub_32bit);
20574 // Add the offset to the reg_save_area to get the final address.
20575 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20576 .addReg(OffsetReg64)
20577 .addReg(RegSaveReg);
20579 // Compute the offset for the next argument
20580 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20581 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20583 .addImm(UseFPOffset ? 16 : 8);
20585 // Store it back into the va_list.
20586 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20590 .addDisp(Disp, UseFPOffset ? 4 : 0)
20591 .addOperand(Segment)
20592 .addReg(NextOffsetReg)
20593 .setMemRefs(MMOBegin, MMOEnd);
20596 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20601 // Emit code to use overflow area
20604 // Load the overflow_area address into a register.
20605 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20606 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20611 .addOperand(Segment)
20612 .setMemRefs(MMOBegin, MMOEnd);
20614 // If we need to align it, do so. Otherwise, just copy the address
20615 // to OverflowDestReg.
20617 // Align the overflow address
20618 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20619 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20621 // aligned_addr = (addr + (align-1)) & ~(align-1)
20622 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20623 .addReg(OverflowAddrReg)
20626 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20628 .addImm(~(uint64_t)(Align-1));
20630 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20631 .addReg(OverflowAddrReg);
20634 // Compute the next overflow address after this argument.
20635 // (the overflow address should be kept 8-byte aligned)
20636 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20637 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20638 .addReg(OverflowDestReg)
20639 .addImm(ArgSizeA8);
20641 // Store the new overflow address.
20642 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20647 .addOperand(Segment)
20648 .addReg(NextAddrReg)
20649 .setMemRefs(MMOBegin, MMOEnd);
20651 // If we branched, emit the PHI to the front of endMBB.
20653 BuildMI(*endMBB, endMBB->begin(), DL,
20654 TII->get(X86::PHI), DestReg)
20655 .addReg(OffsetDestReg).addMBB(offsetMBB)
20656 .addReg(OverflowDestReg).addMBB(overflowMBB);
20659 // Erase the pseudo instruction
20660 MI->eraseFromParent();
20665 MachineBasicBlock *
20666 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20668 MachineBasicBlock *MBB) const {
20669 // Emit code to save XMM registers to the stack. The ABI says that the
20670 // number of registers to save is given in %al, so it's theoretically
20671 // possible to do an indirect jump trick to avoid saving all of them,
20672 // however this code takes a simpler approach and just executes all
20673 // of the stores if %al is non-zero. It's less code, and it's probably
20674 // easier on the hardware branch predictor, and stores aren't all that
20675 // expensive anyway.
20677 // Create the new basic blocks. One block contains all the XMM stores,
20678 // and one block is the final destination regardless of whether any
20679 // stores were performed.
20680 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20681 MachineFunction *F = MBB->getParent();
20682 MachineFunction::iterator MBBIter = MBB;
20684 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20685 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20686 F->insert(MBBIter, XMMSaveMBB);
20687 F->insert(MBBIter, EndMBB);
20689 // Transfer the remainder of MBB and its successor edges to EndMBB.
20690 EndMBB->splice(EndMBB->begin(), MBB,
20691 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20692 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20694 // The original block will now fall through to the XMM save block.
20695 MBB->addSuccessor(XMMSaveMBB);
20696 // The XMMSaveMBB will fall through to the end block.
20697 XMMSaveMBB->addSuccessor(EndMBB);
20699 // Now add the instructions.
20700 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20701 DebugLoc DL = MI->getDebugLoc();
20703 unsigned CountReg = MI->getOperand(0).getReg();
20704 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20705 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20707 if (!Subtarget->isTargetWin64()) {
20708 // If %al is 0, branch around the XMM save block.
20709 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20710 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20711 MBB->addSuccessor(EndMBB);
20714 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20715 // that was just emitted, but clearly shouldn't be "saved".
20716 assert((MI->getNumOperands() <= 3 ||
20717 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20718 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20719 && "Expected last argument to be EFLAGS");
20720 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20721 // In the XMM save block, save all the XMM argument registers.
20722 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20723 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20724 MachineMemOperand *MMO =
20725 F->getMachineMemOperand(
20726 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20727 MachineMemOperand::MOStore,
20728 /*Size=*/16, /*Align=*/16);
20729 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20730 .addFrameIndex(RegSaveFrameIndex)
20731 .addImm(/*Scale=*/1)
20732 .addReg(/*IndexReg=*/0)
20733 .addImm(/*Disp=*/Offset)
20734 .addReg(/*Segment=*/0)
20735 .addReg(MI->getOperand(i).getReg())
20736 .addMemOperand(MMO);
20739 MI->eraseFromParent(); // The pseudo instruction is gone now.
20744 // The EFLAGS operand of SelectItr might be missing a kill marker
20745 // because there were multiple uses of EFLAGS, and ISel didn't know
20746 // which to mark. Figure out whether SelectItr should have had a
20747 // kill marker, and set it if it should. Returns the correct kill
20749 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20750 MachineBasicBlock* BB,
20751 const TargetRegisterInfo* TRI) {
20752 // Scan forward through BB for a use/def of EFLAGS.
20753 MachineBasicBlock::iterator miI(std::next(SelectItr));
20754 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20755 const MachineInstr& mi = *miI;
20756 if (mi.readsRegister(X86::EFLAGS))
20758 if (mi.definesRegister(X86::EFLAGS))
20759 break; // Should have kill-flag - update below.
20762 // If we hit the end of the block, check whether EFLAGS is live into a
20764 if (miI == BB->end()) {
20765 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20766 sEnd = BB->succ_end();
20767 sItr != sEnd; ++sItr) {
20768 MachineBasicBlock* succ = *sItr;
20769 if (succ->isLiveIn(X86::EFLAGS))
20774 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20775 // out. SelectMI should have a kill flag on EFLAGS.
20776 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20780 MachineBasicBlock *
20781 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20782 MachineBasicBlock *BB) const {
20783 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20784 DebugLoc DL = MI->getDebugLoc();
20786 // To "insert" a SELECT_CC instruction, we actually have to insert the
20787 // diamond control-flow pattern. The incoming instruction knows the
20788 // destination vreg to set, the condition code register to branch on, the
20789 // true/false values to select between, and a branch opcode to use.
20790 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20791 MachineFunction::iterator It = BB;
20797 // cmpTY ccX, r1, r2
20799 // fallthrough --> copy0MBB
20800 MachineBasicBlock *thisMBB = BB;
20801 MachineFunction *F = BB->getParent();
20802 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20803 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20804 F->insert(It, copy0MBB);
20805 F->insert(It, sinkMBB);
20807 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20808 // live into the sink and copy blocks.
20809 const TargetRegisterInfo *TRI =
20810 BB->getParent()->getSubtarget().getRegisterInfo();
20811 if (!MI->killsRegister(X86::EFLAGS) &&
20812 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20813 copy0MBB->addLiveIn(X86::EFLAGS);
20814 sinkMBB->addLiveIn(X86::EFLAGS);
20817 // Transfer the remainder of BB and its successor edges to sinkMBB.
20818 sinkMBB->splice(sinkMBB->begin(), BB,
20819 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20820 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20822 // Add the true and fallthrough blocks as its successors.
20823 BB->addSuccessor(copy0MBB);
20824 BB->addSuccessor(sinkMBB);
20826 // Create the conditional branch instruction.
20828 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20829 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20832 // %FalseValue = ...
20833 // # fallthrough to sinkMBB
20834 copy0MBB->addSuccessor(sinkMBB);
20837 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20839 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20840 TII->get(X86::PHI), MI->getOperand(0).getReg())
20841 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20842 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20844 MI->eraseFromParent(); // The pseudo instruction is gone now.
20848 MachineBasicBlock *
20849 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20850 MachineBasicBlock *BB) const {
20851 MachineFunction *MF = BB->getParent();
20852 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20853 DebugLoc DL = MI->getDebugLoc();
20854 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20856 assert(MF->shouldSplitStack());
20858 const bool Is64Bit = Subtarget->is64Bit();
20859 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20861 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20862 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20865 // ... [Till the alloca]
20866 // If stacklet is not large enough, jump to mallocMBB
20869 // Allocate by subtracting from RSP
20870 // Jump to continueMBB
20873 // Allocate by call to runtime
20877 // [rest of original BB]
20880 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20881 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20882 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20884 MachineRegisterInfo &MRI = MF->getRegInfo();
20885 const TargetRegisterClass *AddrRegClass =
20886 getRegClassFor(getPointerTy());
20888 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20889 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20890 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20891 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20892 sizeVReg = MI->getOperand(1).getReg(),
20893 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20895 MachineFunction::iterator MBBIter = BB;
20898 MF->insert(MBBIter, bumpMBB);
20899 MF->insert(MBBIter, mallocMBB);
20900 MF->insert(MBBIter, continueMBB);
20902 continueMBB->splice(continueMBB->begin(), BB,
20903 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20904 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20906 // Add code to the main basic block to check if the stack limit has been hit,
20907 // and if so, jump to mallocMBB otherwise to bumpMBB.
20908 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20909 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20910 .addReg(tmpSPVReg).addReg(sizeVReg);
20911 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20912 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20913 .addReg(SPLimitVReg);
20914 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20916 // bumpMBB simply decreases the stack pointer, since we know the current
20917 // stacklet has enough space.
20918 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20919 .addReg(SPLimitVReg);
20920 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20921 .addReg(SPLimitVReg);
20922 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20924 // Calls into a routine in libgcc to allocate more space from the heap.
20925 const uint32_t *RegMask = MF->getTarget()
20926 .getSubtargetImpl()
20927 ->getRegisterInfo()
20928 ->getCallPreservedMask(CallingConv::C);
20930 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20932 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20933 .addExternalSymbol("__morestack_allocate_stack_space")
20934 .addRegMask(RegMask)
20935 .addReg(X86::RDI, RegState::Implicit)
20936 .addReg(X86::RAX, RegState::ImplicitDefine);
20937 } else if (Is64Bit) {
20938 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20940 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20941 .addExternalSymbol("__morestack_allocate_stack_space")
20942 .addRegMask(RegMask)
20943 .addReg(X86::EDI, RegState::Implicit)
20944 .addReg(X86::EAX, RegState::ImplicitDefine);
20946 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20948 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20949 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20950 .addExternalSymbol("__morestack_allocate_stack_space")
20951 .addRegMask(RegMask)
20952 .addReg(X86::EAX, RegState::ImplicitDefine);
20956 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20959 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20960 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20961 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20963 // Set up the CFG correctly.
20964 BB->addSuccessor(bumpMBB);
20965 BB->addSuccessor(mallocMBB);
20966 mallocMBB->addSuccessor(continueMBB);
20967 bumpMBB->addSuccessor(continueMBB);
20969 // Take care of the PHI nodes.
20970 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20971 MI->getOperand(0).getReg())
20972 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20973 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20975 // Delete the original pseudo instruction.
20976 MI->eraseFromParent();
20979 return continueMBB;
20982 MachineBasicBlock *
20983 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20984 MachineBasicBlock *BB) const {
20985 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20986 DebugLoc DL = MI->getDebugLoc();
20988 assert(!Subtarget->isTargetMachO());
20990 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20991 // non-trivial part is impdef of ESP.
20993 if (Subtarget->isTargetWin64()) {
20994 if (Subtarget->isTargetCygMing()) {
20995 // ___chkstk(Mingw64):
20996 // Clobbers R10, R11, RAX and EFLAGS.
20998 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20999 .addExternalSymbol("___chkstk")
21000 .addReg(X86::RAX, RegState::Implicit)
21001 .addReg(X86::RSP, RegState::Implicit)
21002 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
21003 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
21004 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21006 // __chkstk(MSVCRT): does not update stack pointer.
21007 // Clobbers R10, R11 and EFLAGS.
21008 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
21009 .addExternalSymbol("__chkstk")
21010 .addReg(X86::RAX, RegState::Implicit)
21011 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21012 // RAX has the offset to be subtracted from RSP.
21013 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
21018 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
21019 Subtarget->isTargetWindowsItanium())
21023 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
21024 .addExternalSymbol(StackProbeSymbol)
21025 .addReg(X86::EAX, RegState::Implicit)
21026 .addReg(X86::ESP, RegState::Implicit)
21027 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
21028 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
21029 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
21032 MI->eraseFromParent(); // The pseudo instruction is gone now.
21036 MachineBasicBlock *
21037 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21038 MachineBasicBlock *BB) const {
21039 // This is pretty easy. We're taking the value that we received from
21040 // our load from the relocation, sticking it in either RDI (x86-64)
21041 // or EAX and doing an indirect call. The return value will then
21042 // be in the normal return register.
21043 MachineFunction *F = BB->getParent();
21044 const X86InstrInfo *TII =
21045 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
21046 DebugLoc DL = MI->getDebugLoc();
21048 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21049 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21051 // Get a register mask for the lowered call.
21052 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21053 // proper register mask.
21054 const uint32_t *RegMask = F->getTarget()
21055 .getSubtargetImpl()
21056 ->getRegisterInfo()
21057 ->getCallPreservedMask(CallingConv::C);
21058 if (Subtarget->is64Bit()) {
21059 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21060 TII->get(X86::MOV64rm), X86::RDI)
21062 .addImm(0).addReg(0)
21063 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21064 MI->getOperand(3).getTargetFlags())
21066 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21067 addDirectMem(MIB, X86::RDI);
21068 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21069 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21070 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21071 TII->get(X86::MOV32rm), X86::EAX)
21073 .addImm(0).addReg(0)
21074 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21075 MI->getOperand(3).getTargetFlags())
21077 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21078 addDirectMem(MIB, X86::EAX);
21079 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21081 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21082 TII->get(X86::MOV32rm), X86::EAX)
21083 .addReg(TII->getGlobalBaseReg(F))
21084 .addImm(0).addReg(0)
21085 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21086 MI->getOperand(3).getTargetFlags())
21088 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21089 addDirectMem(MIB, X86::EAX);
21090 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21093 MI->eraseFromParent(); // The pseudo instruction is gone now.
21097 MachineBasicBlock *
21098 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21099 MachineBasicBlock *MBB) const {
21100 DebugLoc DL = MI->getDebugLoc();
21101 MachineFunction *MF = MBB->getParent();
21102 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21103 MachineRegisterInfo &MRI = MF->getRegInfo();
21105 const BasicBlock *BB = MBB->getBasicBlock();
21106 MachineFunction::iterator I = MBB;
21109 // Memory Reference
21110 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21111 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21114 unsigned MemOpndSlot = 0;
21116 unsigned CurOp = 0;
21118 DstReg = MI->getOperand(CurOp++).getReg();
21119 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21120 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21121 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21122 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21124 MemOpndSlot = CurOp;
21126 MVT PVT = getPointerTy();
21127 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21128 "Invalid Pointer Size!");
21130 // For v = setjmp(buf), we generate
21133 // buf[LabelOffset] = restoreMBB
21134 // SjLjSetup restoreMBB
21140 // v = phi(main, restore)
21143 // if base pointer being used, load it from frame
21146 MachineBasicBlock *thisMBB = MBB;
21147 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21148 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21149 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21150 MF->insert(I, mainMBB);
21151 MF->insert(I, sinkMBB);
21152 MF->push_back(restoreMBB);
21154 MachineInstrBuilder MIB;
21156 // Transfer the remainder of BB and its successor edges to sinkMBB.
21157 sinkMBB->splice(sinkMBB->begin(), MBB,
21158 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21159 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21162 unsigned PtrStoreOpc = 0;
21163 unsigned LabelReg = 0;
21164 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21165 Reloc::Model RM = MF->getTarget().getRelocationModel();
21166 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21167 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21169 // Prepare IP either in reg or imm.
21170 if (!UseImmLabel) {
21171 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21172 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21173 LabelReg = MRI.createVirtualRegister(PtrRC);
21174 if (Subtarget->is64Bit()) {
21175 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21179 .addMBB(restoreMBB)
21182 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21183 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21184 .addReg(XII->getGlobalBaseReg(MF))
21187 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21191 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21193 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21194 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21195 if (i == X86::AddrDisp)
21196 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21198 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21201 MIB.addReg(LabelReg);
21203 MIB.addMBB(restoreMBB);
21204 MIB.setMemRefs(MMOBegin, MMOEnd);
21206 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21207 .addMBB(restoreMBB);
21209 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21210 MF->getSubtarget().getRegisterInfo());
21211 MIB.addRegMask(RegInfo->getNoPreservedMask());
21212 thisMBB->addSuccessor(mainMBB);
21213 thisMBB->addSuccessor(restoreMBB);
21217 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21218 mainMBB->addSuccessor(sinkMBB);
21221 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21222 TII->get(X86::PHI), DstReg)
21223 .addReg(mainDstReg).addMBB(mainMBB)
21224 .addReg(restoreDstReg).addMBB(restoreMBB);
21227 if (RegInfo->hasBasePointer(*MF)) {
21228 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21229 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21230 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21231 X86FI->setRestoreBasePointer(MF);
21232 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21233 unsigned BasePtr = RegInfo->getBaseRegister();
21234 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21235 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21236 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21237 .setMIFlag(MachineInstr::FrameSetup);
21239 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21240 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21241 restoreMBB->addSuccessor(sinkMBB);
21243 MI->eraseFromParent();
21247 MachineBasicBlock *
21248 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21249 MachineBasicBlock *MBB) const {
21250 DebugLoc DL = MI->getDebugLoc();
21251 MachineFunction *MF = MBB->getParent();
21252 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21253 MachineRegisterInfo &MRI = MF->getRegInfo();
21255 // Memory Reference
21256 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21257 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21259 MVT PVT = getPointerTy();
21260 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21261 "Invalid Pointer Size!");
21263 const TargetRegisterClass *RC =
21264 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21265 unsigned Tmp = MRI.createVirtualRegister(RC);
21266 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21267 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21268 MF->getSubtarget().getRegisterInfo());
21269 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21270 unsigned SP = RegInfo->getStackRegister();
21272 MachineInstrBuilder MIB;
21274 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21275 const int64_t SPOffset = 2 * PVT.getStoreSize();
21277 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21278 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21281 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21282 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21283 MIB.addOperand(MI->getOperand(i));
21284 MIB.setMemRefs(MMOBegin, MMOEnd);
21286 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21287 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21288 if (i == X86::AddrDisp)
21289 MIB.addDisp(MI->getOperand(i), LabelOffset);
21291 MIB.addOperand(MI->getOperand(i));
21293 MIB.setMemRefs(MMOBegin, MMOEnd);
21295 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21296 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21297 if (i == X86::AddrDisp)
21298 MIB.addDisp(MI->getOperand(i), SPOffset);
21300 MIB.addOperand(MI->getOperand(i));
21302 MIB.setMemRefs(MMOBegin, MMOEnd);
21304 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21306 MI->eraseFromParent();
21310 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21311 // accumulator loops. Writing back to the accumulator allows the coalescer
21312 // to remove extra copies in the loop.
21313 MachineBasicBlock *
21314 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21315 MachineBasicBlock *MBB) const {
21316 MachineOperand &AddendOp = MI->getOperand(3);
21318 // Bail out early if the addend isn't a register - we can't switch these.
21319 if (!AddendOp.isReg())
21322 MachineFunction &MF = *MBB->getParent();
21323 MachineRegisterInfo &MRI = MF.getRegInfo();
21325 // Check whether the addend is defined by a PHI:
21326 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21327 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21328 if (!AddendDef.isPHI())
21331 // Look for the following pattern:
21333 // %addend = phi [%entry, 0], [%loop, %result]
21335 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21339 // %addend = phi [%entry, 0], [%loop, %result]
21341 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21343 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21344 assert(AddendDef.getOperand(i).isReg());
21345 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21346 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21347 if (&PHISrcInst == MI) {
21348 // Found a matching instruction.
21349 unsigned NewFMAOpc = 0;
21350 switch (MI->getOpcode()) {
21351 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21352 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21353 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21354 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21355 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21356 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21357 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21358 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21359 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21360 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21361 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21362 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21363 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21364 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21365 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21366 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21367 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21368 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21369 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21370 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21372 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21373 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21374 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21375 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21376 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21377 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21378 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21379 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21380 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21381 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21382 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21383 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21384 default: llvm_unreachable("Unrecognized FMA variant.");
21387 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21388 MachineInstrBuilder MIB =
21389 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21390 .addOperand(MI->getOperand(0))
21391 .addOperand(MI->getOperand(3))
21392 .addOperand(MI->getOperand(2))
21393 .addOperand(MI->getOperand(1));
21394 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21395 MI->eraseFromParent();
21402 MachineBasicBlock *
21403 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21404 MachineBasicBlock *BB) const {
21405 switch (MI->getOpcode()) {
21406 default: llvm_unreachable("Unexpected instr type to insert");
21407 case X86::TAILJMPd64:
21408 case X86::TAILJMPr64:
21409 case X86::TAILJMPm64:
21410 llvm_unreachable("TAILJMP64 would not be touched here.");
21411 case X86::TCRETURNdi64:
21412 case X86::TCRETURNri64:
21413 case X86::TCRETURNmi64:
21415 case X86::WIN_ALLOCA:
21416 return EmitLoweredWinAlloca(MI, BB);
21417 case X86::SEG_ALLOCA_32:
21418 case X86::SEG_ALLOCA_64:
21419 return EmitLoweredSegAlloca(MI, BB);
21420 case X86::TLSCall_32:
21421 case X86::TLSCall_64:
21422 return EmitLoweredTLSCall(MI, BB);
21423 case X86::CMOV_GR8:
21424 case X86::CMOV_FR32:
21425 case X86::CMOV_FR64:
21426 case X86::CMOV_V4F32:
21427 case X86::CMOV_V2F64:
21428 case X86::CMOV_V2I64:
21429 case X86::CMOV_V8F32:
21430 case X86::CMOV_V4F64:
21431 case X86::CMOV_V4I64:
21432 case X86::CMOV_V16F32:
21433 case X86::CMOV_V8F64:
21434 case X86::CMOV_V8I64:
21435 case X86::CMOV_GR16:
21436 case X86::CMOV_GR32:
21437 case X86::CMOV_RFP32:
21438 case X86::CMOV_RFP64:
21439 case X86::CMOV_RFP80:
21440 return EmitLoweredSelect(MI, BB);
21442 case X86::FP32_TO_INT16_IN_MEM:
21443 case X86::FP32_TO_INT32_IN_MEM:
21444 case X86::FP32_TO_INT64_IN_MEM:
21445 case X86::FP64_TO_INT16_IN_MEM:
21446 case X86::FP64_TO_INT32_IN_MEM:
21447 case X86::FP64_TO_INT64_IN_MEM:
21448 case X86::FP80_TO_INT16_IN_MEM:
21449 case X86::FP80_TO_INT32_IN_MEM:
21450 case X86::FP80_TO_INT64_IN_MEM: {
21451 MachineFunction *F = BB->getParent();
21452 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21453 DebugLoc DL = MI->getDebugLoc();
21455 // Change the floating point control register to use "round towards zero"
21456 // mode when truncating to an integer value.
21457 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21458 addFrameReference(BuildMI(*BB, MI, DL,
21459 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21461 // Load the old value of the high byte of the control word...
21463 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21464 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21467 // Set the high part to be round to zero...
21468 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21471 // Reload the modified control word now...
21472 addFrameReference(BuildMI(*BB, MI, DL,
21473 TII->get(X86::FLDCW16m)), CWFrameIdx);
21475 // Restore the memory image of control word to original value
21476 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21479 // Get the X86 opcode to use.
21481 switch (MI->getOpcode()) {
21482 default: llvm_unreachable("illegal opcode!");
21483 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21484 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21485 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21486 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21487 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21488 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21489 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21490 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21491 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21495 MachineOperand &Op = MI->getOperand(0);
21497 AM.BaseType = X86AddressMode::RegBase;
21498 AM.Base.Reg = Op.getReg();
21500 AM.BaseType = X86AddressMode::FrameIndexBase;
21501 AM.Base.FrameIndex = Op.getIndex();
21503 Op = MI->getOperand(1);
21505 AM.Scale = Op.getImm();
21506 Op = MI->getOperand(2);
21508 AM.IndexReg = Op.getImm();
21509 Op = MI->getOperand(3);
21510 if (Op.isGlobal()) {
21511 AM.GV = Op.getGlobal();
21513 AM.Disp = Op.getImm();
21515 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21516 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21518 // Reload the original control word now.
21519 addFrameReference(BuildMI(*BB, MI, DL,
21520 TII->get(X86::FLDCW16m)), CWFrameIdx);
21522 MI->eraseFromParent(); // The pseudo instruction is gone now.
21525 // String/text processing lowering.
21526 case X86::PCMPISTRM128REG:
21527 case X86::VPCMPISTRM128REG:
21528 case X86::PCMPISTRM128MEM:
21529 case X86::VPCMPISTRM128MEM:
21530 case X86::PCMPESTRM128REG:
21531 case X86::VPCMPESTRM128REG:
21532 case X86::PCMPESTRM128MEM:
21533 case X86::VPCMPESTRM128MEM:
21534 assert(Subtarget->hasSSE42() &&
21535 "Target must have SSE4.2 or AVX features enabled");
21536 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21538 // String/text processing lowering.
21539 case X86::PCMPISTRIREG:
21540 case X86::VPCMPISTRIREG:
21541 case X86::PCMPISTRIMEM:
21542 case X86::VPCMPISTRIMEM:
21543 case X86::PCMPESTRIREG:
21544 case X86::VPCMPESTRIREG:
21545 case X86::PCMPESTRIMEM:
21546 case X86::VPCMPESTRIMEM:
21547 assert(Subtarget->hasSSE42() &&
21548 "Target must have SSE4.2 or AVX features enabled");
21549 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21551 // Thread synchronization.
21553 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21558 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21560 case X86::VASTART_SAVE_XMM_REGS:
21561 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21563 case X86::VAARG_64:
21564 return EmitVAARG64WithCustomInserter(MI, BB);
21566 case X86::EH_SjLj_SetJmp32:
21567 case X86::EH_SjLj_SetJmp64:
21568 return emitEHSjLjSetJmp(MI, BB);
21570 case X86::EH_SjLj_LongJmp32:
21571 case X86::EH_SjLj_LongJmp64:
21572 return emitEHSjLjLongJmp(MI, BB);
21574 case TargetOpcode::STATEPOINT:
21575 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21576 // this point in the process. We diverge later.
21577 return emitPatchPoint(MI, BB);
21579 case TargetOpcode::STACKMAP:
21580 case TargetOpcode::PATCHPOINT:
21581 return emitPatchPoint(MI, BB);
21583 case X86::VFMADDPDr213r:
21584 case X86::VFMADDPSr213r:
21585 case X86::VFMADDSDr213r:
21586 case X86::VFMADDSSr213r:
21587 case X86::VFMSUBPDr213r:
21588 case X86::VFMSUBPSr213r:
21589 case X86::VFMSUBSDr213r:
21590 case X86::VFMSUBSSr213r:
21591 case X86::VFNMADDPDr213r:
21592 case X86::VFNMADDPSr213r:
21593 case X86::VFNMADDSDr213r:
21594 case X86::VFNMADDSSr213r:
21595 case X86::VFNMSUBPDr213r:
21596 case X86::VFNMSUBPSr213r:
21597 case X86::VFNMSUBSDr213r:
21598 case X86::VFNMSUBSSr213r:
21599 case X86::VFMADDSUBPDr213r:
21600 case X86::VFMADDSUBPSr213r:
21601 case X86::VFMSUBADDPDr213r:
21602 case X86::VFMSUBADDPSr213r:
21603 case X86::VFMADDPDr213rY:
21604 case X86::VFMADDPSr213rY:
21605 case X86::VFMSUBPDr213rY:
21606 case X86::VFMSUBPSr213rY:
21607 case X86::VFNMADDPDr213rY:
21608 case X86::VFNMADDPSr213rY:
21609 case X86::VFNMSUBPDr213rY:
21610 case X86::VFNMSUBPSr213rY:
21611 case X86::VFMADDSUBPDr213rY:
21612 case X86::VFMADDSUBPSr213rY:
21613 case X86::VFMSUBADDPDr213rY:
21614 case X86::VFMSUBADDPSr213rY:
21615 return emitFMA3Instr(MI, BB);
21619 //===----------------------------------------------------------------------===//
21620 // X86 Optimization Hooks
21621 //===----------------------------------------------------------------------===//
21623 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21626 const SelectionDAG &DAG,
21627 unsigned Depth) const {
21628 unsigned BitWidth = KnownZero.getBitWidth();
21629 unsigned Opc = Op.getOpcode();
21630 assert((Opc >= ISD::BUILTIN_OP_END ||
21631 Opc == ISD::INTRINSIC_WO_CHAIN ||
21632 Opc == ISD::INTRINSIC_W_CHAIN ||
21633 Opc == ISD::INTRINSIC_VOID) &&
21634 "Should use MaskedValueIsZero if you don't know whether Op"
21635 " is a target node!");
21637 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21651 // These nodes' second result is a boolean.
21652 if (Op.getResNo() == 0)
21655 case X86ISD::SETCC:
21656 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21658 case ISD::INTRINSIC_WO_CHAIN: {
21659 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21660 unsigned NumLoBits = 0;
21663 case Intrinsic::x86_sse_movmsk_ps:
21664 case Intrinsic::x86_avx_movmsk_ps_256:
21665 case Intrinsic::x86_sse2_movmsk_pd:
21666 case Intrinsic::x86_avx_movmsk_pd_256:
21667 case Intrinsic::x86_mmx_pmovmskb:
21668 case Intrinsic::x86_sse2_pmovmskb_128:
21669 case Intrinsic::x86_avx2_pmovmskb: {
21670 // High bits of movmskp{s|d}, pmovmskb are known zero.
21672 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21673 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21674 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21675 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21676 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21677 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21678 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21679 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21681 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21690 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21692 const SelectionDAG &,
21693 unsigned Depth) const {
21694 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21695 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21696 return Op.getValueType().getScalarType().getSizeInBits();
21702 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21703 /// node is a GlobalAddress + offset.
21704 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21705 const GlobalValue* &GA,
21706 int64_t &Offset) const {
21707 if (N->getOpcode() == X86ISD::Wrapper) {
21708 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21709 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21710 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21714 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21717 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21718 /// same as extracting the high 128-bit part of 256-bit vector and then
21719 /// inserting the result into the low part of a new 256-bit vector
21720 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21721 EVT VT = SVOp->getValueType(0);
21722 unsigned NumElems = VT.getVectorNumElements();
21724 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21725 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21726 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21727 SVOp->getMaskElt(j) >= 0)
21733 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21734 /// same as extracting the low 128-bit part of 256-bit vector and then
21735 /// inserting the result into the high part of a new 256-bit vector
21736 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21737 EVT VT = SVOp->getValueType(0);
21738 unsigned NumElems = VT.getVectorNumElements();
21740 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21741 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21742 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21743 SVOp->getMaskElt(j) >= 0)
21749 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21750 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21751 TargetLowering::DAGCombinerInfo &DCI,
21752 const X86Subtarget* Subtarget) {
21754 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21755 SDValue V1 = SVOp->getOperand(0);
21756 SDValue V2 = SVOp->getOperand(1);
21757 EVT VT = SVOp->getValueType(0);
21758 unsigned NumElems = VT.getVectorNumElements();
21760 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21761 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21765 // V UNDEF BUILD_VECTOR UNDEF
21767 // CONCAT_VECTOR CONCAT_VECTOR
21770 // RESULT: V + zero extended
21772 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21773 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21774 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21777 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21780 // To match the shuffle mask, the first half of the mask should
21781 // be exactly the first vector, and all the rest a splat with the
21782 // first element of the second one.
21783 for (unsigned i = 0; i != NumElems/2; ++i)
21784 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21785 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21788 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21789 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21790 if (Ld->hasNUsesOfValue(1, 0)) {
21791 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21792 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21794 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21796 Ld->getPointerInfo(),
21797 Ld->getAlignment(),
21798 false/*isVolatile*/, true/*ReadMem*/,
21799 false/*WriteMem*/);
21801 // Make sure the newly-created LOAD is in the same position as Ld in
21802 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21803 // and update uses of Ld's output chain to use the TokenFactor.
21804 if (Ld->hasAnyUseOfValue(1)) {
21805 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21806 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21807 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21808 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21809 SDValue(ResNode.getNode(), 1));
21812 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21816 // Emit a zeroed vector and insert the desired subvector on its
21818 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21819 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21820 return DCI.CombineTo(N, InsV);
21823 //===--------------------------------------------------------------------===//
21824 // Combine some shuffles into subvector extracts and inserts:
21827 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21828 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21829 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21830 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21831 return DCI.CombineTo(N, InsV);
21834 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21835 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21836 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21837 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21838 return DCI.CombineTo(N, InsV);
21844 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21847 /// This is the leaf of the recursive combinine below. When we have found some
21848 /// chain of single-use x86 shuffle instructions and accumulated the combined
21849 /// shuffle mask represented by them, this will try to pattern match that mask
21850 /// into either a single instruction if there is a special purpose instruction
21851 /// for this operation, or into a PSHUFB instruction which is a fully general
21852 /// instruction but should only be used to replace chains over a certain depth.
21853 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21854 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21855 TargetLowering::DAGCombinerInfo &DCI,
21856 const X86Subtarget *Subtarget) {
21857 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21859 // Find the operand that enters the chain. Note that multiple uses are OK
21860 // here, we're not going to remove the operand we find.
21861 SDValue Input = Op.getOperand(0);
21862 while (Input.getOpcode() == ISD::BITCAST)
21863 Input = Input.getOperand(0);
21865 MVT VT = Input.getSimpleValueType();
21866 MVT RootVT = Root.getSimpleValueType();
21869 // Just remove no-op shuffle masks.
21870 if (Mask.size() == 1) {
21871 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21876 // Use the float domain if the operand type is a floating point type.
21877 bool FloatDomain = VT.isFloatingPoint();
21879 // For floating point shuffles, we don't have free copies in the shuffle
21880 // instructions or the ability to load as part of the instruction, so
21881 // canonicalize their shuffles to UNPCK or MOV variants.
21883 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21884 // vectors because it can have a load folded into it that UNPCK cannot. This
21885 // doesn't preclude something switching to the shorter encoding post-RA.
21887 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21888 bool Lo = Mask.equals(0, 0);
21891 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21892 // is no slower than UNPCKLPD but has the option to fold the input operand
21893 // into even an unaligned memory load.
21894 if (Lo && Subtarget->hasSSE3()) {
21895 Shuffle = X86ISD::MOVDDUP;
21896 ShuffleVT = MVT::v2f64;
21898 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21899 // than the UNPCK variants.
21900 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21901 ShuffleVT = MVT::v4f32;
21903 if (Depth == 1 && Root->getOpcode() == Shuffle)
21904 return false; // Nothing to do!
21905 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21906 DCI.AddToWorklist(Op.getNode());
21907 if (Shuffle == X86ISD::MOVDDUP)
21908 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21910 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21911 DCI.AddToWorklist(Op.getNode());
21912 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21916 if (Subtarget->hasSSE3() &&
21917 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21918 bool Lo = Mask.equals(0, 0, 2, 2);
21919 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21920 MVT ShuffleVT = MVT::v4f32;
21921 if (Depth == 1 && Root->getOpcode() == Shuffle)
21922 return false; // Nothing to do!
21923 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21924 DCI.AddToWorklist(Op.getNode());
21925 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21926 DCI.AddToWorklist(Op.getNode());
21927 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21931 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21932 bool Lo = Mask.equals(0, 0, 1, 1);
21933 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21934 MVT ShuffleVT = MVT::v4f32;
21935 if (Depth == 1 && Root->getOpcode() == Shuffle)
21936 return false; // Nothing to do!
21937 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21938 DCI.AddToWorklist(Op.getNode());
21939 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21940 DCI.AddToWorklist(Op.getNode());
21941 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21947 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21948 // variants as none of these have single-instruction variants that are
21949 // superior to the UNPCK formulation.
21950 if (!FloatDomain &&
21951 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21952 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21953 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21954 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21956 bool Lo = Mask[0] == 0;
21957 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21958 if (Depth == 1 && Root->getOpcode() == Shuffle)
21959 return false; // Nothing to do!
21961 switch (Mask.size()) {
21963 ShuffleVT = MVT::v8i16;
21966 ShuffleVT = MVT::v16i8;
21969 llvm_unreachable("Impossible mask size!");
21971 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21972 DCI.AddToWorklist(Op.getNode());
21973 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21974 DCI.AddToWorklist(Op.getNode());
21975 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21980 // Don't try to re-form single instruction chains under any circumstances now
21981 // that we've done encoding canonicalization for them.
21985 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21986 // can replace them with a single PSHUFB instruction profitably. Intel's
21987 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21988 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21989 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21990 SmallVector<SDValue, 16> PSHUFBMask;
21991 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21992 int Ratio = 16 / Mask.size();
21993 for (unsigned i = 0; i < 16; ++i) {
21994 if (Mask[i / Ratio] == SM_SentinelUndef) {
21995 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21998 int M = Mask[i / Ratio] != SM_SentinelZero
21999 ? Ratio * Mask[i / Ratio] + i % Ratio
22001 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
22003 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
22004 DCI.AddToWorklist(Op.getNode());
22005 SDValue PSHUFBMaskOp =
22006 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
22007 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22008 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
22009 DCI.AddToWorklist(Op.getNode());
22010 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
22015 // Failed to find any combines.
22019 /// \brief Fully generic combining of x86 shuffle instructions.
22021 /// This should be the last combine run over the x86 shuffle instructions. Once
22022 /// they have been fully optimized, this will recursively consider all chains
22023 /// of single-use shuffle instructions, build a generic model of the cumulative
22024 /// shuffle operation, and check for simpler instructions which implement this
22025 /// operation. We use this primarily for two purposes:
22027 /// 1) Collapse generic shuffles to specialized single instructions when
22028 /// equivalent. In most cases, this is just an encoding size win, but
22029 /// sometimes we will collapse multiple generic shuffles into a single
22030 /// special-purpose shuffle.
22031 /// 2) Look for sequences of shuffle instructions with 3 or more total
22032 /// instructions, and replace them with the slightly more expensive SSSE3
22033 /// PSHUFB instruction if available. We do this as the last combining step
22034 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22035 /// a suitable short sequence of other instructions. The PHUFB will either
22036 /// use a register or have to read from memory and so is slightly (but only
22037 /// slightly) more expensive than the other shuffle instructions.
22039 /// Because this is inherently a quadratic operation (for each shuffle in
22040 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22041 /// This should never be an issue in practice as the shuffle lowering doesn't
22042 /// produce sequences of more than 8 instructions.
22044 /// FIXME: We will currently miss some cases where the redundant shuffling
22045 /// would simplify under the threshold for PSHUFB formation because of
22046 /// combine-ordering. To fix this, we should do the redundant instruction
22047 /// combining in this recursive walk.
22048 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22049 ArrayRef<int> RootMask,
22050 int Depth, bool HasPSHUFB,
22052 TargetLowering::DAGCombinerInfo &DCI,
22053 const X86Subtarget *Subtarget) {
22054 // Bound the depth of our recursive combine because this is ultimately
22055 // quadratic in nature.
22059 // Directly rip through bitcasts to find the underlying operand.
22060 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22061 Op = Op.getOperand(0);
22063 MVT VT = Op.getSimpleValueType();
22064 if (!VT.isVector())
22065 return false; // Bail if we hit a non-vector.
22066 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
22067 // version should be added.
22068 if (VT.getSizeInBits() != 128)
22071 assert(Root.getSimpleValueType().isVector() &&
22072 "Shuffles operate on vector types!");
22073 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22074 "Can only combine shuffles of the same vector register size.");
22076 if (!isTargetShuffle(Op.getOpcode()))
22078 SmallVector<int, 16> OpMask;
22080 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22081 // We only can combine unary shuffles which we can decode the mask for.
22082 if (!HaveMask || !IsUnary)
22085 assert(VT.getVectorNumElements() == OpMask.size() &&
22086 "Different mask size from vector size!");
22087 assert(((RootMask.size() > OpMask.size() &&
22088 RootMask.size() % OpMask.size() == 0) ||
22089 (OpMask.size() > RootMask.size() &&
22090 OpMask.size() % RootMask.size() == 0) ||
22091 OpMask.size() == RootMask.size()) &&
22092 "The smaller number of elements must divide the larger.");
22093 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22094 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22095 assert(((RootRatio == 1 && OpRatio == 1) ||
22096 (RootRatio == 1) != (OpRatio == 1)) &&
22097 "Must not have a ratio for both incoming and op masks!");
22099 SmallVector<int, 16> Mask;
22100 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22102 // Merge this shuffle operation's mask into our accumulated mask. Note that
22103 // this shuffle's mask will be the first applied to the input, followed by the
22104 // root mask to get us all the way to the root value arrangement. The reason
22105 // for this order is that we are recursing up the operation chain.
22106 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22107 int RootIdx = i / RootRatio;
22108 if (RootMask[RootIdx] < 0) {
22109 // This is a zero or undef lane, we're done.
22110 Mask.push_back(RootMask[RootIdx]);
22114 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22115 int OpIdx = RootMaskedIdx / OpRatio;
22116 if (OpMask[OpIdx] < 0) {
22117 // The incoming lanes are zero or undef, it doesn't matter which ones we
22119 Mask.push_back(OpMask[OpIdx]);
22123 // Ok, we have non-zero lanes, map them through.
22124 Mask.push_back(OpMask[OpIdx] * OpRatio +
22125 RootMaskedIdx % OpRatio);
22128 // See if we can recurse into the operand to combine more things.
22129 switch (Op.getOpcode()) {
22130 case X86ISD::PSHUFB:
22132 case X86ISD::PSHUFD:
22133 case X86ISD::PSHUFHW:
22134 case X86ISD::PSHUFLW:
22135 if (Op.getOperand(0).hasOneUse() &&
22136 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22137 HasPSHUFB, DAG, DCI, Subtarget))
22141 case X86ISD::UNPCKL:
22142 case X86ISD::UNPCKH:
22143 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22144 // We can't check for single use, we have to check that this shuffle is the only user.
22145 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22146 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22147 HasPSHUFB, DAG, DCI, Subtarget))
22152 // Minor canonicalization of the accumulated shuffle mask to make it easier
22153 // to match below. All this does is detect masks with squential pairs of
22154 // elements, and shrink them to the half-width mask. It does this in a loop
22155 // so it will reduce the size of the mask to the minimal width mask which
22156 // performs an equivalent shuffle.
22157 SmallVector<int, 16> WidenedMask;
22158 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22159 Mask = std::move(WidenedMask);
22160 WidenedMask.clear();
22163 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22167 /// \brief Get the PSHUF-style mask from PSHUF node.
22169 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22170 /// PSHUF-style masks that can be reused with such instructions.
22171 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22172 SmallVector<int, 4> Mask;
22174 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22178 switch (N.getOpcode()) {
22179 case X86ISD::PSHUFD:
22181 case X86ISD::PSHUFLW:
22184 case X86ISD::PSHUFHW:
22185 Mask.erase(Mask.begin(), Mask.begin() + 4);
22186 for (int &M : Mask)
22190 llvm_unreachable("No valid shuffle instruction found!");
22194 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22196 /// We walk up the chain and look for a combinable shuffle, skipping over
22197 /// shuffles that we could hoist this shuffle's transformation past without
22198 /// altering anything.
22200 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22202 TargetLowering::DAGCombinerInfo &DCI) {
22203 assert(N.getOpcode() == X86ISD::PSHUFD &&
22204 "Called with something other than an x86 128-bit half shuffle!");
22207 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22208 // of the shuffles in the chain so that we can form a fresh chain to replace
22210 SmallVector<SDValue, 8> Chain;
22211 SDValue V = N.getOperand(0);
22212 for (; V.hasOneUse(); V = V.getOperand(0)) {
22213 switch (V.getOpcode()) {
22215 return SDValue(); // Nothing combined!
22218 // Skip bitcasts as we always know the type for the target specific
22222 case X86ISD::PSHUFD:
22223 // Found another dword shuffle.
22226 case X86ISD::PSHUFLW:
22227 // Check that the low words (being shuffled) are the identity in the
22228 // dword shuffle, and the high words are self-contained.
22229 if (Mask[0] != 0 || Mask[1] != 1 ||
22230 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22233 Chain.push_back(V);
22236 case X86ISD::PSHUFHW:
22237 // Check that the high words (being shuffled) are the identity in the
22238 // dword shuffle, and the low words are self-contained.
22239 if (Mask[2] != 2 || Mask[3] != 3 ||
22240 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22243 Chain.push_back(V);
22246 case X86ISD::UNPCKL:
22247 case X86ISD::UNPCKH:
22248 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22249 // shuffle into a preceding word shuffle.
22250 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22253 // Search for a half-shuffle which we can combine with.
22254 unsigned CombineOp =
22255 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22256 if (V.getOperand(0) != V.getOperand(1) ||
22257 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22259 Chain.push_back(V);
22260 V = V.getOperand(0);
22262 switch (V.getOpcode()) {
22264 return SDValue(); // Nothing to combine.
22266 case X86ISD::PSHUFLW:
22267 case X86ISD::PSHUFHW:
22268 if (V.getOpcode() == CombineOp)
22271 Chain.push_back(V);
22275 V = V.getOperand(0);
22279 } while (V.hasOneUse());
22282 // Break out of the loop if we break out of the switch.
22286 if (!V.hasOneUse())
22287 // We fell out of the loop without finding a viable combining instruction.
22290 // Merge this node's mask and our incoming mask.
22291 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22292 for (int &M : Mask)
22294 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22295 getV4X86ShuffleImm8ForMask(Mask, DAG));
22297 // Rebuild the chain around this new shuffle.
22298 while (!Chain.empty()) {
22299 SDValue W = Chain.pop_back_val();
22301 if (V.getValueType() != W.getOperand(0).getValueType())
22302 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22304 switch (W.getOpcode()) {
22306 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22308 case X86ISD::UNPCKL:
22309 case X86ISD::UNPCKH:
22310 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22313 case X86ISD::PSHUFD:
22314 case X86ISD::PSHUFLW:
22315 case X86ISD::PSHUFHW:
22316 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22320 if (V.getValueType() != N.getValueType())
22321 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22323 // Return the new chain to replace N.
22327 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22329 /// We walk up the chain, skipping shuffles of the other half and looking
22330 /// through shuffles which switch halves trying to find a shuffle of the same
22331 /// pair of dwords.
22332 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22334 TargetLowering::DAGCombinerInfo &DCI) {
22336 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22337 "Called with something other than an x86 128-bit half shuffle!");
22339 unsigned CombineOpcode = N.getOpcode();
22341 // Walk up a single-use chain looking for a combinable shuffle.
22342 SDValue V = N.getOperand(0);
22343 for (; V.hasOneUse(); V = V.getOperand(0)) {
22344 switch (V.getOpcode()) {
22346 return false; // Nothing combined!
22349 // Skip bitcasts as we always know the type for the target specific
22353 case X86ISD::PSHUFLW:
22354 case X86ISD::PSHUFHW:
22355 if (V.getOpcode() == CombineOpcode)
22358 // Other-half shuffles are no-ops.
22361 // Break out of the loop if we break out of the switch.
22365 if (!V.hasOneUse())
22366 // We fell out of the loop without finding a viable combining instruction.
22369 // Combine away the bottom node as its shuffle will be accumulated into
22370 // a preceding shuffle.
22371 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22373 // Record the old value.
22376 // Merge this node's mask and our incoming mask (adjusted to account for all
22377 // the pshufd instructions encountered).
22378 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22379 for (int &M : Mask)
22381 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22382 getV4X86ShuffleImm8ForMask(Mask, DAG));
22384 // Check that the shuffles didn't cancel each other out. If not, we need to
22385 // combine to the new one.
22387 // Replace the combinable shuffle with the combined one, updating all users
22388 // so that we re-evaluate the chain here.
22389 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22394 /// \brief Try to combine x86 target specific shuffles.
22395 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22396 TargetLowering::DAGCombinerInfo &DCI,
22397 const X86Subtarget *Subtarget) {
22399 MVT VT = N.getSimpleValueType();
22400 SmallVector<int, 4> Mask;
22402 switch (N.getOpcode()) {
22403 case X86ISD::PSHUFD:
22404 case X86ISD::PSHUFLW:
22405 case X86ISD::PSHUFHW:
22406 Mask = getPSHUFShuffleMask(N);
22407 assert(Mask.size() == 4);
22413 // Nuke no-op shuffles that show up after combining.
22414 if (isNoopShuffleMask(Mask))
22415 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22417 // Look for simplifications involving one or two shuffle instructions.
22418 SDValue V = N.getOperand(0);
22419 switch (N.getOpcode()) {
22422 case X86ISD::PSHUFLW:
22423 case X86ISD::PSHUFHW:
22424 assert(VT == MVT::v8i16);
22427 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22428 return SDValue(); // We combined away this shuffle, so we're done.
22430 // See if this reduces to a PSHUFD which is no more expensive and can
22431 // combine with more operations. Note that it has to at least flip the
22432 // dwords as otherwise it would have been removed as a no-op.
22433 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22434 int DMask[] = {0, 1, 2, 3};
22435 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22436 DMask[DOffset + 0] = DOffset + 1;
22437 DMask[DOffset + 1] = DOffset + 0;
22438 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22439 DCI.AddToWorklist(V.getNode());
22440 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22441 getV4X86ShuffleImm8ForMask(DMask, DAG));
22442 DCI.AddToWorklist(V.getNode());
22443 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22446 // Look for shuffle patterns which can be implemented as a single unpack.
22447 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22448 // only works when we have a PSHUFD followed by two half-shuffles.
22449 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22450 (V.getOpcode() == X86ISD::PSHUFLW ||
22451 V.getOpcode() == X86ISD::PSHUFHW) &&
22452 V.getOpcode() != N.getOpcode() &&
22454 SDValue D = V.getOperand(0);
22455 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22456 D = D.getOperand(0);
22457 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22458 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22459 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22460 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22461 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22463 for (int i = 0; i < 4; ++i) {
22464 WordMask[i + NOffset] = Mask[i] + NOffset;
22465 WordMask[i + VOffset] = VMask[i] + VOffset;
22467 // Map the word mask through the DWord mask.
22469 for (int i = 0; i < 8; ++i)
22470 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22471 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22472 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22473 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22474 std::begin(UnpackLoMask)) ||
22475 std::equal(std::begin(MappedMask), std::end(MappedMask),
22476 std::begin(UnpackHiMask))) {
22477 // We can replace all three shuffles with an unpack.
22478 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22479 DCI.AddToWorklist(V.getNode());
22480 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22482 DL, MVT::v8i16, V, V);
22489 case X86ISD::PSHUFD:
22490 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22499 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22501 /// We combine this directly on the abstract vector shuffle nodes so it is
22502 /// easier to generically match. We also insert dummy vector shuffle nodes for
22503 /// the operands which explicitly discard the lanes which are unused by this
22504 /// operation to try to flow through the rest of the combiner the fact that
22505 /// they're unused.
22506 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22508 EVT VT = N->getValueType(0);
22510 // We only handle target-independent shuffles.
22511 // FIXME: It would be easy and harmless to use the target shuffle mask
22512 // extraction tool to support more.
22513 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22516 auto *SVN = cast<ShuffleVectorSDNode>(N);
22517 ArrayRef<int> Mask = SVN->getMask();
22518 SDValue V1 = N->getOperand(0);
22519 SDValue V2 = N->getOperand(1);
22521 // We require the first shuffle operand to be the SUB node, and the second to
22522 // be the ADD node.
22523 // FIXME: We should support the commuted patterns.
22524 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22527 // If there are other uses of these operations we can't fold them.
22528 if (!V1->hasOneUse() || !V2->hasOneUse())
22531 // Ensure that both operations have the same operands. Note that we can
22532 // commute the FADD operands.
22533 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22534 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22535 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22538 // We're looking for blends between FADD and FSUB nodes. We insist on these
22539 // nodes being lined up in a specific expected pattern.
22540 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22541 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22542 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22545 // Only specific types are legal at this point, assert so we notice if and
22546 // when these change.
22547 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22548 VT == MVT::v4f64) &&
22549 "Unknown vector type encountered!");
22551 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22554 /// PerformShuffleCombine - Performs several different shuffle combines.
22555 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22556 TargetLowering::DAGCombinerInfo &DCI,
22557 const X86Subtarget *Subtarget) {
22559 SDValue N0 = N->getOperand(0);
22560 SDValue N1 = N->getOperand(1);
22561 EVT VT = N->getValueType(0);
22563 // Don't create instructions with illegal types after legalize types has run.
22564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22565 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22568 // If we have legalized the vector types, look for blends of FADD and FSUB
22569 // nodes that we can fuse into an ADDSUB node.
22570 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22571 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22574 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22575 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22576 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22577 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22579 // During Type Legalization, when promoting illegal vector types,
22580 // the backend might introduce new shuffle dag nodes and bitcasts.
22582 // This code performs the following transformation:
22583 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22584 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22586 // We do this only if both the bitcast and the BINOP dag nodes have
22587 // one use. Also, perform this transformation only if the new binary
22588 // operation is legal. This is to avoid introducing dag nodes that
22589 // potentially need to be further expanded (or custom lowered) into a
22590 // less optimal sequence of dag nodes.
22591 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22592 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22593 N0.getOpcode() == ISD::BITCAST) {
22594 SDValue BC0 = N0.getOperand(0);
22595 EVT SVT = BC0.getValueType();
22596 unsigned Opcode = BC0.getOpcode();
22597 unsigned NumElts = VT.getVectorNumElements();
22599 if (BC0.hasOneUse() && SVT.isVector() &&
22600 SVT.getVectorNumElements() * 2 == NumElts &&
22601 TLI.isOperationLegal(Opcode, VT)) {
22602 bool CanFold = false;
22614 unsigned SVTNumElts = SVT.getVectorNumElements();
22615 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22616 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22617 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22618 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22619 CanFold = SVOp->getMaskElt(i) < 0;
22622 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22623 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22624 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22625 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22630 // Only handle 128 wide vector from here on.
22631 if (!VT.is128BitVector())
22634 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22635 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22636 // consecutive, non-overlapping, and in the right order.
22637 SmallVector<SDValue, 16> Elts;
22638 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22639 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22641 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22645 if (isTargetShuffle(N->getOpcode())) {
22647 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22648 if (Shuffle.getNode())
22651 // Try recursively combining arbitrary sequences of x86 shuffle
22652 // instructions into higher-order shuffles. We do this after combining
22653 // specific PSHUF instruction sequences into their minimal form so that we
22654 // can evaluate how many specialized shuffle instructions are involved in
22655 // a particular chain.
22656 SmallVector<int, 1> NonceMask; // Just a placeholder.
22657 NonceMask.push_back(0);
22658 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22659 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22661 return SDValue(); // This routine will use CombineTo to replace N.
22667 /// PerformTruncateCombine - Converts truncate operation to
22668 /// a sequence of vector shuffle operations.
22669 /// It is possible when we truncate 256-bit vector to 128-bit vector
22670 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22671 TargetLowering::DAGCombinerInfo &DCI,
22672 const X86Subtarget *Subtarget) {
22676 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22677 /// specific shuffle of a load can be folded into a single element load.
22678 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22679 /// shuffles have been custom lowered so we need to handle those here.
22680 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22681 TargetLowering::DAGCombinerInfo &DCI) {
22682 if (DCI.isBeforeLegalizeOps())
22685 SDValue InVec = N->getOperand(0);
22686 SDValue EltNo = N->getOperand(1);
22688 if (!isa<ConstantSDNode>(EltNo))
22691 EVT OriginalVT = InVec.getValueType();
22693 if (InVec.getOpcode() == ISD::BITCAST) {
22694 // Don't duplicate a load with other uses.
22695 if (!InVec.hasOneUse())
22697 EVT BCVT = InVec.getOperand(0).getValueType();
22698 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22700 InVec = InVec.getOperand(0);
22703 EVT CurrentVT = InVec.getValueType();
22705 if (!isTargetShuffle(InVec.getOpcode()))
22708 // Don't duplicate a load with other uses.
22709 if (!InVec.hasOneUse())
22712 SmallVector<int, 16> ShuffleMask;
22714 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22715 ShuffleMask, UnaryShuffle))
22718 // Select the input vector, guarding against out of range extract vector.
22719 unsigned NumElems = CurrentVT.getVectorNumElements();
22720 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22721 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22722 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22723 : InVec.getOperand(1);
22725 // If inputs to shuffle are the same for both ops, then allow 2 uses
22726 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22728 if (LdNode.getOpcode() == ISD::BITCAST) {
22729 // Don't duplicate a load with other uses.
22730 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22733 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22734 LdNode = LdNode.getOperand(0);
22737 if (!ISD::isNormalLoad(LdNode.getNode()))
22740 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22742 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22745 EVT EltVT = N->getValueType(0);
22746 // If there's a bitcast before the shuffle, check if the load type and
22747 // alignment is valid.
22748 unsigned Align = LN0->getAlignment();
22749 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22750 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22751 EltVT.getTypeForEVT(*DAG.getContext()));
22753 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22756 // All checks match so transform back to vector_shuffle so that DAG combiner
22757 // can finish the job
22760 // Create shuffle node taking into account the case that its a unary shuffle
22761 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22762 : InVec.getOperand(1);
22763 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22764 InVec.getOperand(0), Shuffle,
22766 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22767 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22771 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22772 /// generation and convert it from being a bunch of shuffles and extracts
22773 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22774 /// storing the value and loading scalars back, while for x64 we should
22775 /// use 64-bit extracts and shifts.
22776 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22777 TargetLowering::DAGCombinerInfo &DCI) {
22778 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22779 if (NewOp.getNode())
22782 SDValue InputVector = N->getOperand(0);
22784 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22785 // from mmx to v2i32 has a single usage.
22786 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22787 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22788 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22789 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22790 N->getValueType(0),
22791 InputVector.getNode()->getOperand(0));
22793 // Only operate on vectors of 4 elements, where the alternative shuffling
22794 // gets to be more expensive.
22795 if (InputVector.getValueType() != MVT::v4i32)
22798 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22799 // single use which is a sign-extend or zero-extend, and all elements are
22801 SmallVector<SDNode *, 4> Uses;
22802 unsigned ExtractedElements = 0;
22803 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22804 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22805 if (UI.getUse().getResNo() != InputVector.getResNo())
22808 SDNode *Extract = *UI;
22809 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22812 if (Extract->getValueType(0) != MVT::i32)
22814 if (!Extract->hasOneUse())
22816 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22817 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22819 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22822 // Record which element was extracted.
22823 ExtractedElements |=
22824 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22826 Uses.push_back(Extract);
22829 // If not all the elements were used, this may not be worthwhile.
22830 if (ExtractedElements != 15)
22833 // Ok, we've now decided to do the transformation.
22834 // If 64-bit shifts are legal, use the extract-shift sequence,
22835 // otherwise bounce the vector off the cache.
22836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22838 SDLoc dl(InputVector);
22840 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22841 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22842 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22843 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22844 DAG.getConstant(0, VecIdxTy));
22845 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22846 DAG.getConstant(1, VecIdxTy));
22848 SDValue ShAmt = DAG.getConstant(32,
22849 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22850 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22851 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22852 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22853 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22854 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22855 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22857 // Store the value to a temporary stack slot.
22858 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22859 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22860 MachinePointerInfo(), false, false, 0);
22862 EVT ElementType = InputVector.getValueType().getVectorElementType();
22863 unsigned EltSize = ElementType.getSizeInBits() / 8;
22865 // Replace each use (extract) with a load of the appropriate element.
22866 for (unsigned i = 0; i < 4; ++i) {
22867 uint64_t Offset = EltSize * i;
22868 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22870 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22871 StackPtr, OffsetVal);
22873 // Load the scalar.
22874 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22875 ScalarAddr, MachinePointerInfo(),
22876 false, false, false, 0);
22881 // Replace the extracts
22882 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22883 UE = Uses.end(); UI != UE; ++UI) {
22884 SDNode *Extract = *UI;
22886 SDValue Idx = Extract->getOperand(1);
22887 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22888 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22891 // The replacement was made in place; don't return anything.
22895 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22896 static std::pair<unsigned, bool>
22897 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22898 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22899 if (!VT.isVector())
22900 return std::make_pair(0, false);
22902 bool NeedSplit = false;
22903 switch (VT.getSimpleVT().SimpleTy) {
22904 default: return std::make_pair(0, false);
22907 if (!Subtarget->hasVLX())
22908 return std::make_pair(0, false);
22912 if (!Subtarget->hasBWI())
22913 return std::make_pair(0, false);
22917 if (!Subtarget->hasAVX512())
22918 return std::make_pair(0, false);
22923 if (!Subtarget->hasAVX2())
22925 if (!Subtarget->hasAVX())
22926 return std::make_pair(0, false);
22931 if (!Subtarget->hasSSE2())
22932 return std::make_pair(0, false);
22935 // SSE2 has only a small subset of the operations.
22936 bool hasUnsigned = Subtarget->hasSSE41() ||
22937 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22938 bool hasSigned = Subtarget->hasSSE41() ||
22939 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22941 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22944 // Check for x CC y ? x : y.
22945 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22946 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22951 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22954 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22957 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22960 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22962 // Check for x CC y ? y : x -- a min/max with reversed arms.
22963 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22964 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22969 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22972 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22975 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22978 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22982 return std::make_pair(Opc, NeedSplit);
22986 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22987 const X86Subtarget *Subtarget) {
22989 SDValue Cond = N->getOperand(0);
22990 SDValue LHS = N->getOperand(1);
22991 SDValue RHS = N->getOperand(2);
22993 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22994 SDValue CondSrc = Cond->getOperand(0);
22995 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22996 Cond = CondSrc->getOperand(0);
22999 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23002 // A vselect where all conditions and data are constants can be optimized into
23003 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23004 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23005 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23008 unsigned MaskValue = 0;
23009 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23012 MVT VT = N->getSimpleValueType(0);
23013 unsigned NumElems = VT.getVectorNumElements();
23014 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23015 for (unsigned i = 0; i < NumElems; ++i) {
23016 // Be sure we emit undef where we can.
23017 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23018 ShuffleMask[i] = -1;
23020 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23023 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23024 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23026 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23029 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23031 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23032 TargetLowering::DAGCombinerInfo &DCI,
23033 const X86Subtarget *Subtarget) {
23035 SDValue Cond = N->getOperand(0);
23036 // Get the LHS/RHS of the select.
23037 SDValue LHS = N->getOperand(1);
23038 SDValue RHS = N->getOperand(2);
23039 EVT VT = LHS.getValueType();
23040 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23042 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23043 // instructions match the semantics of the common C idiom x<y?x:y but not
23044 // x<=y?x:y, because of how they handle negative zero (which can be
23045 // ignored in unsafe-math mode).
23046 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23047 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
23048 (Subtarget->hasSSE2() ||
23049 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23050 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23052 unsigned Opcode = 0;
23053 // Check for x CC y ? x : y.
23054 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23055 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23059 // Converting this to a min would handle NaNs incorrectly, and swapping
23060 // the operands would cause it to handle comparisons between positive
23061 // and negative zero incorrectly.
23062 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23063 if (!DAG.getTarget().Options.UnsafeFPMath &&
23064 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23066 std::swap(LHS, RHS);
23068 Opcode = X86ISD::FMIN;
23071 // Converting this to a min would handle comparisons between positive
23072 // and negative zero incorrectly.
23073 if (!DAG.getTarget().Options.UnsafeFPMath &&
23074 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23076 Opcode = X86ISD::FMIN;
23079 // Converting this to a min would handle both negative zeros and NaNs
23080 // incorrectly, but we can swap the operands to fix both.
23081 std::swap(LHS, RHS);
23085 Opcode = X86ISD::FMIN;
23089 // Converting this to a max would handle comparisons between positive
23090 // and negative zero incorrectly.
23091 if (!DAG.getTarget().Options.UnsafeFPMath &&
23092 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23094 Opcode = X86ISD::FMAX;
23097 // Converting this to a max would handle NaNs incorrectly, and swapping
23098 // the operands would cause it to handle comparisons between positive
23099 // and negative zero incorrectly.
23100 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23101 if (!DAG.getTarget().Options.UnsafeFPMath &&
23102 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23104 std::swap(LHS, RHS);
23106 Opcode = X86ISD::FMAX;
23109 // Converting this to a max would handle both negative zeros and NaNs
23110 // incorrectly, but we can swap the operands to fix both.
23111 std::swap(LHS, RHS);
23115 Opcode = X86ISD::FMAX;
23118 // Check for x CC y ? y : x -- a min/max with reversed arms.
23119 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23120 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23124 // Converting this to a min would handle comparisons between positive
23125 // and negative zero incorrectly, and swapping the operands would
23126 // cause it to handle NaNs incorrectly.
23127 if (!DAG.getTarget().Options.UnsafeFPMath &&
23128 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23129 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23131 std::swap(LHS, RHS);
23133 Opcode = X86ISD::FMIN;
23136 // Converting this to a min would handle NaNs incorrectly.
23137 if (!DAG.getTarget().Options.UnsafeFPMath &&
23138 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23140 Opcode = X86ISD::FMIN;
23143 // Converting this to a min would handle both negative zeros and NaNs
23144 // incorrectly, but we can swap the operands to fix both.
23145 std::swap(LHS, RHS);
23149 Opcode = X86ISD::FMIN;
23153 // Converting this to a max would handle NaNs incorrectly.
23154 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23156 Opcode = X86ISD::FMAX;
23159 // Converting this to a max would handle comparisons between positive
23160 // and negative zero incorrectly, and swapping the operands would
23161 // cause it to handle NaNs incorrectly.
23162 if (!DAG.getTarget().Options.UnsafeFPMath &&
23163 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23164 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23166 std::swap(LHS, RHS);
23168 Opcode = X86ISD::FMAX;
23171 // Converting this to a max would handle both negative zeros and NaNs
23172 // incorrectly, but we can swap the operands to fix both.
23173 std::swap(LHS, RHS);
23177 Opcode = X86ISD::FMAX;
23183 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23186 EVT CondVT = Cond.getValueType();
23187 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23188 CondVT.getVectorElementType() == MVT::i1) {
23189 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23190 // lowering on KNL. In this case we convert it to
23191 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23192 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23193 // Since SKX these selects have a proper lowering.
23194 EVT OpVT = LHS.getValueType();
23195 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23196 (OpVT.getVectorElementType() == MVT::i8 ||
23197 OpVT.getVectorElementType() == MVT::i16) &&
23198 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23199 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23200 DCI.AddToWorklist(Cond.getNode());
23201 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23204 // If this is a select between two integer constants, try to do some
23206 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23207 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23208 // Don't do this for crazy integer types.
23209 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23210 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23211 // so that TrueC (the true value) is larger than FalseC.
23212 bool NeedsCondInvert = false;
23214 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23215 // Efficiently invertible.
23216 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23217 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23218 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23219 NeedsCondInvert = true;
23220 std::swap(TrueC, FalseC);
23223 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23224 if (FalseC->getAPIntValue() == 0 &&
23225 TrueC->getAPIntValue().isPowerOf2()) {
23226 if (NeedsCondInvert) // Invert the condition if needed.
23227 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23228 DAG.getConstant(1, Cond.getValueType()));
23230 // Zero extend the condition if needed.
23231 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23233 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23234 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23235 DAG.getConstant(ShAmt, MVT::i8));
23238 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23239 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23240 if (NeedsCondInvert) // Invert the condition if needed.
23241 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23242 DAG.getConstant(1, Cond.getValueType()));
23244 // Zero extend the condition if needed.
23245 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23246 FalseC->getValueType(0), Cond);
23247 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23248 SDValue(FalseC, 0));
23251 // Optimize cases that will turn into an LEA instruction. This requires
23252 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23253 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23254 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23255 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23257 bool isFastMultiplier = false;
23259 switch ((unsigned char)Diff) {
23261 case 1: // result = add base, cond
23262 case 2: // result = lea base( , cond*2)
23263 case 3: // result = lea base(cond, cond*2)
23264 case 4: // result = lea base( , cond*4)
23265 case 5: // result = lea base(cond, cond*4)
23266 case 8: // result = lea base( , cond*8)
23267 case 9: // result = lea base(cond, cond*8)
23268 isFastMultiplier = true;
23273 if (isFastMultiplier) {
23274 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23275 if (NeedsCondInvert) // Invert the condition if needed.
23276 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23277 DAG.getConstant(1, Cond.getValueType()));
23279 // Zero extend the condition if needed.
23280 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23282 // Scale the condition by the difference.
23284 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23285 DAG.getConstant(Diff, Cond.getValueType()));
23287 // Add the base if non-zero.
23288 if (FalseC->getAPIntValue() != 0)
23289 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23290 SDValue(FalseC, 0));
23297 // Canonicalize max and min:
23298 // (x > y) ? x : y -> (x >= y) ? x : y
23299 // (x < y) ? x : y -> (x <= y) ? x : y
23300 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23301 // the need for an extra compare
23302 // against zero. e.g.
23303 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23305 // testl %edi, %edi
23307 // cmovgl %edi, %eax
23311 // cmovsl %eax, %edi
23312 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23313 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23314 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23315 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23320 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23321 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23322 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23323 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23328 // Early exit check
23329 if (!TLI.isTypeLegal(VT))
23332 // Match VSELECTs into subs with unsigned saturation.
23333 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23334 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23335 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23336 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23337 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23339 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23340 // left side invert the predicate to simplify logic below.
23342 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23344 CC = ISD::getSetCCInverse(CC, true);
23345 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23349 if (Other.getNode() && Other->getNumOperands() == 2 &&
23350 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23351 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23352 SDValue CondRHS = Cond->getOperand(1);
23354 // Look for a general sub with unsigned saturation first.
23355 // x >= y ? x-y : 0 --> subus x, y
23356 // x > y ? x-y : 0 --> subus x, y
23357 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23358 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23359 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23361 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23362 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23363 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23364 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23365 // If the RHS is a constant we have to reverse the const
23366 // canonicalization.
23367 // x > C-1 ? x+-C : 0 --> subus x, C
23368 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23369 CondRHSConst->getAPIntValue() ==
23370 (-OpRHSConst->getAPIntValue() - 1))
23371 return DAG.getNode(
23372 X86ISD::SUBUS, DL, VT, OpLHS,
23373 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23375 // Another special case: If C was a sign bit, the sub has been
23376 // canonicalized into a xor.
23377 // FIXME: Would it be better to use computeKnownBits to determine
23378 // whether it's safe to decanonicalize the xor?
23379 // x s< 0 ? x^C : 0 --> subus x, C
23380 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23381 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23382 OpRHSConst->getAPIntValue().isSignBit())
23383 // Note that we have to rebuild the RHS constant here to ensure we
23384 // don't rely on particular values of undef lanes.
23385 return DAG.getNode(
23386 X86ISD::SUBUS, DL, VT, OpLHS,
23387 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23392 // Try to match a min/max vector operation.
23393 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23394 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23395 unsigned Opc = ret.first;
23396 bool NeedSplit = ret.second;
23398 if (Opc && NeedSplit) {
23399 unsigned NumElems = VT.getVectorNumElements();
23400 // Extract the LHS vectors
23401 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23402 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23404 // Extract the RHS vectors
23405 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23406 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23408 // Create min/max for each subvector
23409 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23410 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23412 // Merge the result
23413 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23415 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23418 // Simplify vector selection if condition value type matches vselect
23420 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23421 assert(Cond.getValueType().isVector() &&
23422 "vector select expects a vector selector!");
23424 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23425 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23427 // Try invert the condition if true value is not all 1s and false value
23429 if (!TValIsAllOnes && !FValIsAllZeros &&
23430 // Check if the selector will be produced by CMPP*/PCMP*
23431 Cond.getOpcode() == ISD::SETCC &&
23432 // Check if SETCC has already been promoted
23433 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23434 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23435 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23437 if (TValIsAllZeros || FValIsAllOnes) {
23438 SDValue CC = Cond.getOperand(2);
23439 ISD::CondCode NewCC =
23440 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23441 Cond.getOperand(0).getValueType().isInteger());
23442 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23443 std::swap(LHS, RHS);
23444 TValIsAllOnes = FValIsAllOnes;
23445 FValIsAllZeros = TValIsAllZeros;
23449 if (TValIsAllOnes || FValIsAllZeros) {
23452 if (TValIsAllOnes && FValIsAllZeros)
23454 else if (TValIsAllOnes)
23455 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23456 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23457 else if (FValIsAllZeros)
23458 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23459 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23461 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23465 // If we know that this node is legal then we know that it is going to be
23466 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23467 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23468 // to simplify previous instructions.
23469 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23470 !DCI.isBeforeLegalize() &&
23471 // We explicitly check against v8i16 and v16i16 because, although
23472 // they're marked as Custom, they might only be legal when Cond is a
23473 // build_vector of constants. This will be taken care in a later
23475 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23476 VT != MVT::v8i16) &&
23477 // Don't optimize vector of constants. Those are handled by
23478 // the generic code and all the bits must be properly set for
23479 // the generic optimizer.
23480 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23481 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23483 // Don't optimize vector selects that map to mask-registers.
23487 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23488 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23490 APInt KnownZero, KnownOne;
23491 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23492 DCI.isBeforeLegalizeOps());
23493 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23494 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23496 // If we changed the computation somewhere in the DAG, this change
23497 // will affect all users of Cond.
23498 // Make sure it is fine and update all the nodes so that we do not
23499 // use the generic VSELECT anymore. Otherwise, we may perform
23500 // wrong optimizations as we messed up with the actual expectation
23501 // for the vector boolean values.
23502 if (Cond != TLO.Old) {
23503 // Check all uses of that condition operand to check whether it will be
23504 // consumed by non-BLEND instructions, which may depend on all bits are
23506 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23508 if (I->getOpcode() != ISD::VSELECT)
23509 // TODO: Add other opcodes eventually lowered into BLEND.
23512 // Update all the users of the condition, before committing the change,
23513 // so that the VSELECT optimizations that expect the correct vector
23514 // boolean value will not be triggered.
23515 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23517 DAG.ReplaceAllUsesOfValueWith(
23519 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23520 Cond, I->getOperand(1), I->getOperand(2)));
23521 DCI.CommitTargetLoweringOpt(TLO);
23524 // At this point, only Cond is changed. Change the condition
23525 // just for N to keep the opportunity to optimize all other
23526 // users their own way.
23527 DAG.ReplaceAllUsesOfValueWith(
23529 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23530 TLO.New, N->getOperand(1), N->getOperand(2)));
23535 // We should generate an X86ISD::BLENDI from a vselect if its argument
23536 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23537 // constants. This specific pattern gets generated when we split a
23538 // selector for a 512 bit vector in a machine without AVX512 (but with
23539 // 256-bit vectors), during legalization:
23541 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23543 // Iff we find this pattern and the build_vectors are built from
23544 // constants, we translate the vselect into a shuffle_vector that we
23545 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23546 if ((N->getOpcode() == ISD::VSELECT ||
23547 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23548 !DCI.isBeforeLegalize()) {
23549 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23550 if (Shuffle.getNode())
23557 // Check whether a boolean test is testing a boolean value generated by
23558 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23561 // Simplify the following patterns:
23562 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23563 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23564 // to (Op EFLAGS Cond)
23566 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23567 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23568 // to (Op EFLAGS !Cond)
23570 // where Op could be BRCOND or CMOV.
23572 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23573 // Quit if not CMP and SUB with its value result used.
23574 if (Cmp.getOpcode() != X86ISD::CMP &&
23575 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23578 // Quit if not used as a boolean value.
23579 if (CC != X86::COND_E && CC != X86::COND_NE)
23582 // Check CMP operands. One of them should be 0 or 1 and the other should be
23583 // an SetCC or extended from it.
23584 SDValue Op1 = Cmp.getOperand(0);
23585 SDValue Op2 = Cmp.getOperand(1);
23588 const ConstantSDNode* C = nullptr;
23589 bool needOppositeCond = (CC == X86::COND_E);
23590 bool checkAgainstTrue = false; // Is it a comparison against 1?
23592 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23594 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23596 else // Quit if all operands are not constants.
23599 if (C->getZExtValue() == 1) {
23600 needOppositeCond = !needOppositeCond;
23601 checkAgainstTrue = true;
23602 } else if (C->getZExtValue() != 0)
23603 // Quit if the constant is neither 0 or 1.
23606 bool truncatedToBoolWithAnd = false;
23607 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23608 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23609 SetCC.getOpcode() == ISD::TRUNCATE ||
23610 SetCC.getOpcode() == ISD::AND) {
23611 if (SetCC.getOpcode() == ISD::AND) {
23613 ConstantSDNode *CS;
23614 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23615 CS->getZExtValue() == 1)
23617 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23618 CS->getZExtValue() == 1)
23622 SetCC = SetCC.getOperand(OpIdx);
23623 truncatedToBoolWithAnd = true;
23625 SetCC = SetCC.getOperand(0);
23628 switch (SetCC.getOpcode()) {
23629 case X86ISD::SETCC_CARRY:
23630 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23631 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23632 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23633 // truncated to i1 using 'and'.
23634 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23636 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23637 "Invalid use of SETCC_CARRY!");
23639 case X86ISD::SETCC:
23640 // Set the condition code or opposite one if necessary.
23641 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23642 if (needOppositeCond)
23643 CC = X86::GetOppositeBranchCondition(CC);
23644 return SetCC.getOperand(1);
23645 case X86ISD::CMOV: {
23646 // Check whether false/true value has canonical one, i.e. 0 or 1.
23647 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23648 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23649 // Quit if true value is not a constant.
23652 // Quit if false value is not a constant.
23654 SDValue Op = SetCC.getOperand(0);
23655 // Skip 'zext' or 'trunc' node.
23656 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23657 Op.getOpcode() == ISD::TRUNCATE)
23658 Op = Op.getOperand(0);
23659 // A special case for rdrand/rdseed, where 0 is set if false cond is
23661 if ((Op.getOpcode() != X86ISD::RDRAND &&
23662 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23665 // Quit if false value is not the constant 0 or 1.
23666 bool FValIsFalse = true;
23667 if (FVal && FVal->getZExtValue() != 0) {
23668 if (FVal->getZExtValue() != 1)
23670 // If FVal is 1, opposite cond is needed.
23671 needOppositeCond = !needOppositeCond;
23672 FValIsFalse = false;
23674 // Quit if TVal is not the constant opposite of FVal.
23675 if (FValIsFalse && TVal->getZExtValue() != 1)
23677 if (!FValIsFalse && TVal->getZExtValue() != 0)
23679 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23680 if (needOppositeCond)
23681 CC = X86::GetOppositeBranchCondition(CC);
23682 return SetCC.getOperand(3);
23689 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23690 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23691 TargetLowering::DAGCombinerInfo &DCI,
23692 const X86Subtarget *Subtarget) {
23695 // If the flag operand isn't dead, don't touch this CMOV.
23696 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23699 SDValue FalseOp = N->getOperand(0);
23700 SDValue TrueOp = N->getOperand(1);
23701 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23702 SDValue Cond = N->getOperand(3);
23704 if (CC == X86::COND_E || CC == X86::COND_NE) {
23705 switch (Cond.getOpcode()) {
23709 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23710 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23711 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23717 Flags = checkBoolTestSetCCCombine(Cond, CC);
23718 if (Flags.getNode() &&
23719 // Extra check as FCMOV only supports a subset of X86 cond.
23720 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23721 SDValue Ops[] = { FalseOp, TrueOp,
23722 DAG.getConstant(CC, MVT::i8), Flags };
23723 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23726 // If this is a select between two integer constants, try to do some
23727 // optimizations. Note that the operands are ordered the opposite of SELECT
23729 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23730 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23731 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23732 // larger than FalseC (the false value).
23733 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23734 CC = X86::GetOppositeBranchCondition(CC);
23735 std::swap(TrueC, FalseC);
23736 std::swap(TrueOp, FalseOp);
23739 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23740 // This is efficient for any integer data type (including i8/i16) and
23742 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23743 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23744 DAG.getConstant(CC, MVT::i8), Cond);
23746 // Zero extend the condition if needed.
23747 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23749 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23750 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23751 DAG.getConstant(ShAmt, MVT::i8));
23752 if (N->getNumValues() == 2) // Dead flag value?
23753 return DCI.CombineTo(N, Cond, SDValue());
23757 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23758 // for any integer data type, including i8/i16.
23759 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23760 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23761 DAG.getConstant(CC, MVT::i8), Cond);
23763 // Zero extend the condition if needed.
23764 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23765 FalseC->getValueType(0), Cond);
23766 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23767 SDValue(FalseC, 0));
23769 if (N->getNumValues() == 2) // Dead flag value?
23770 return DCI.CombineTo(N, Cond, SDValue());
23774 // Optimize cases that will turn into an LEA instruction. This requires
23775 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23776 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23777 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23778 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23780 bool isFastMultiplier = false;
23782 switch ((unsigned char)Diff) {
23784 case 1: // result = add base, cond
23785 case 2: // result = lea base( , cond*2)
23786 case 3: // result = lea base(cond, cond*2)
23787 case 4: // result = lea base( , cond*4)
23788 case 5: // result = lea base(cond, cond*4)
23789 case 8: // result = lea base( , cond*8)
23790 case 9: // result = lea base(cond, cond*8)
23791 isFastMultiplier = true;
23796 if (isFastMultiplier) {
23797 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23798 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23799 DAG.getConstant(CC, MVT::i8), Cond);
23800 // Zero extend the condition if needed.
23801 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23803 // Scale the condition by the difference.
23805 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23806 DAG.getConstant(Diff, Cond.getValueType()));
23808 // Add the base if non-zero.
23809 if (FalseC->getAPIntValue() != 0)
23810 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23811 SDValue(FalseC, 0));
23812 if (N->getNumValues() == 2) // Dead flag value?
23813 return DCI.CombineTo(N, Cond, SDValue());
23820 // Handle these cases:
23821 // (select (x != c), e, c) -> select (x != c), e, x),
23822 // (select (x == c), c, e) -> select (x == c), x, e)
23823 // where the c is an integer constant, and the "select" is the combination
23824 // of CMOV and CMP.
23826 // The rationale for this change is that the conditional-move from a constant
23827 // needs two instructions, however, conditional-move from a register needs
23828 // only one instruction.
23830 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23831 // some instruction-combining opportunities. This opt needs to be
23832 // postponed as late as possible.
23834 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23835 // the DCI.xxxx conditions are provided to postpone the optimization as
23836 // late as possible.
23838 ConstantSDNode *CmpAgainst = nullptr;
23839 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23840 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23841 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23843 if (CC == X86::COND_NE &&
23844 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23845 CC = X86::GetOppositeBranchCondition(CC);
23846 std::swap(TrueOp, FalseOp);
23849 if (CC == X86::COND_E &&
23850 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23851 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23852 DAG.getConstant(CC, MVT::i8), Cond };
23853 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23861 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23862 const X86Subtarget *Subtarget) {
23863 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23865 default: return SDValue();
23866 // SSE/AVX/AVX2 blend intrinsics.
23867 case Intrinsic::x86_avx2_pblendvb:
23868 case Intrinsic::x86_avx2_pblendw:
23869 case Intrinsic::x86_avx2_pblendd_128:
23870 case Intrinsic::x86_avx2_pblendd_256:
23871 // Don't try to simplify this intrinsic if we don't have AVX2.
23872 if (!Subtarget->hasAVX2())
23875 case Intrinsic::x86_avx_blend_pd_256:
23876 case Intrinsic::x86_avx_blend_ps_256:
23877 case Intrinsic::x86_avx_blendv_pd_256:
23878 case Intrinsic::x86_avx_blendv_ps_256:
23879 // Don't try to simplify this intrinsic if we don't have AVX.
23880 if (!Subtarget->hasAVX())
23883 case Intrinsic::x86_sse41_pblendw:
23884 case Intrinsic::x86_sse41_blendpd:
23885 case Intrinsic::x86_sse41_blendps:
23886 case Intrinsic::x86_sse41_blendvps:
23887 case Intrinsic::x86_sse41_blendvpd:
23888 case Intrinsic::x86_sse41_pblendvb: {
23889 SDValue Op0 = N->getOperand(1);
23890 SDValue Op1 = N->getOperand(2);
23891 SDValue Mask = N->getOperand(3);
23893 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23894 if (!Subtarget->hasSSE41())
23897 // fold (blend A, A, Mask) -> A
23900 // fold (blend A, B, allZeros) -> A
23901 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23903 // fold (blend A, B, allOnes) -> B
23904 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23907 // Simplify the case where the mask is a constant i32 value.
23908 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23909 if (C->isNullValue())
23911 if (C->isAllOnesValue())
23918 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23919 case Intrinsic::x86_sse2_psrai_w:
23920 case Intrinsic::x86_sse2_psrai_d:
23921 case Intrinsic::x86_avx2_psrai_w:
23922 case Intrinsic::x86_avx2_psrai_d:
23923 case Intrinsic::x86_sse2_psra_w:
23924 case Intrinsic::x86_sse2_psra_d:
23925 case Intrinsic::x86_avx2_psra_w:
23926 case Intrinsic::x86_avx2_psra_d: {
23927 SDValue Op0 = N->getOperand(1);
23928 SDValue Op1 = N->getOperand(2);
23929 EVT VT = Op0.getValueType();
23930 assert(VT.isVector() && "Expected a vector type!");
23932 if (isa<BuildVectorSDNode>(Op1))
23933 Op1 = Op1.getOperand(0);
23935 if (!isa<ConstantSDNode>(Op1))
23938 EVT SVT = VT.getVectorElementType();
23939 unsigned SVTBits = SVT.getSizeInBits();
23941 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23942 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23943 uint64_t ShAmt = C.getZExtValue();
23945 // Don't try to convert this shift into a ISD::SRA if the shift
23946 // count is bigger than or equal to the element size.
23947 if (ShAmt >= SVTBits)
23950 // Trivial case: if the shift count is zero, then fold this
23951 // into the first operand.
23955 // Replace this packed shift intrinsic with a target independent
23957 SDValue Splat = DAG.getConstant(C, VT);
23958 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23963 /// PerformMulCombine - Optimize a single multiply with constant into two
23964 /// in order to implement it with two cheaper instructions, e.g.
23965 /// LEA + SHL, LEA + LEA.
23966 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23967 TargetLowering::DAGCombinerInfo &DCI) {
23968 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23971 EVT VT = N->getValueType(0);
23972 if (VT != MVT::i64)
23975 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23978 uint64_t MulAmt = C->getZExtValue();
23979 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23982 uint64_t MulAmt1 = 0;
23983 uint64_t MulAmt2 = 0;
23984 if ((MulAmt % 9) == 0) {
23986 MulAmt2 = MulAmt / 9;
23987 } else if ((MulAmt % 5) == 0) {
23989 MulAmt2 = MulAmt / 5;
23990 } else if ((MulAmt % 3) == 0) {
23992 MulAmt2 = MulAmt / 3;
23995 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23998 if (isPowerOf2_64(MulAmt2) &&
23999 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24000 // If second multiplifer is pow2, issue it first. We want the multiply by
24001 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24003 std::swap(MulAmt1, MulAmt2);
24006 if (isPowerOf2_64(MulAmt1))
24007 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24008 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
24010 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24011 DAG.getConstant(MulAmt1, VT));
24013 if (isPowerOf2_64(MulAmt2))
24014 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24015 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
24017 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24018 DAG.getConstant(MulAmt2, VT));
24020 // Do not add new nodes to DAG combiner worklist.
24021 DCI.CombineTo(N, NewMul, false);
24026 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24027 SDValue N0 = N->getOperand(0);
24028 SDValue N1 = N->getOperand(1);
24029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24030 EVT VT = N0.getValueType();
24032 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24033 // since the result of setcc_c is all zero's or all ones.
24034 if (VT.isInteger() && !VT.isVector() &&
24035 N1C && N0.getOpcode() == ISD::AND &&
24036 N0.getOperand(1).getOpcode() == ISD::Constant) {
24037 SDValue N00 = N0.getOperand(0);
24038 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
24039 ((N00.getOpcode() == ISD::ANY_EXTEND ||
24040 N00.getOpcode() == ISD::ZERO_EXTEND) &&
24041 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
24042 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24043 APInt ShAmt = N1C->getAPIntValue();
24044 Mask = Mask.shl(ShAmt);
24046 return DAG.getNode(ISD::AND, SDLoc(N), VT,
24047 N00, DAG.getConstant(Mask, VT));
24051 // Hardware support for vector shifts is sparse which makes us scalarize the
24052 // vector operations in many cases. Also, on sandybridge ADD is faster than
24054 // (shl V, 1) -> add V,V
24055 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24056 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24057 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24058 // We shift all of the values by one. In many cases we do not have
24059 // hardware support for this operation. This is better expressed as an ADD
24061 if (N1SplatC->getZExtValue() == 1)
24062 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24068 /// \brief Returns a vector of 0s if the node in input is a vector logical
24069 /// shift by a constant amount which is known to be bigger than or equal
24070 /// to the vector element size in bits.
24071 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24072 const X86Subtarget *Subtarget) {
24073 EVT VT = N->getValueType(0);
24075 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24076 (!Subtarget->hasInt256() ||
24077 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24080 SDValue Amt = N->getOperand(1);
24082 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24083 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24084 APInt ShiftAmt = AmtSplat->getAPIntValue();
24085 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24087 // SSE2/AVX2 logical shifts always return a vector of 0s
24088 // if the shift amount is bigger than or equal to
24089 // the element size. The constant shift amount will be
24090 // encoded as a 8-bit immediate.
24091 if (ShiftAmt.trunc(8).uge(MaxAmount))
24092 return getZeroVector(VT, Subtarget, DAG, DL);
24098 /// PerformShiftCombine - Combine shifts.
24099 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24100 TargetLowering::DAGCombinerInfo &DCI,
24101 const X86Subtarget *Subtarget) {
24102 if (N->getOpcode() == ISD::SHL) {
24103 SDValue V = PerformSHLCombine(N, DAG);
24104 if (V.getNode()) return V;
24107 if (N->getOpcode() != ISD::SRA) {
24108 // Try to fold this logical shift into a zero vector.
24109 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24110 if (V.getNode()) return V;
24116 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24117 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24118 // and friends. Likewise for OR -> CMPNEQSS.
24119 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24120 TargetLowering::DAGCombinerInfo &DCI,
24121 const X86Subtarget *Subtarget) {
24124 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24125 // we're requiring SSE2 for both.
24126 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24127 SDValue N0 = N->getOperand(0);
24128 SDValue N1 = N->getOperand(1);
24129 SDValue CMP0 = N0->getOperand(1);
24130 SDValue CMP1 = N1->getOperand(1);
24133 // The SETCCs should both refer to the same CMP.
24134 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24137 SDValue CMP00 = CMP0->getOperand(0);
24138 SDValue CMP01 = CMP0->getOperand(1);
24139 EVT VT = CMP00.getValueType();
24141 if (VT == MVT::f32 || VT == MVT::f64) {
24142 bool ExpectingFlags = false;
24143 // Check for any users that want flags:
24144 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24145 !ExpectingFlags && UI != UE; ++UI)
24146 switch (UI->getOpcode()) {
24151 ExpectingFlags = true;
24153 case ISD::CopyToReg:
24154 case ISD::SIGN_EXTEND:
24155 case ISD::ZERO_EXTEND:
24156 case ISD::ANY_EXTEND:
24160 if (!ExpectingFlags) {
24161 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24162 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24164 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24165 X86::CondCode tmp = cc0;
24170 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24171 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24172 // FIXME: need symbolic constants for these magic numbers.
24173 // See X86ATTInstPrinter.cpp:printSSECC().
24174 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24175 if (Subtarget->hasAVX512()) {
24176 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24177 CMP01, DAG.getConstant(x86cc, MVT::i8));
24178 if (N->getValueType(0) != MVT::i1)
24179 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24183 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24184 CMP00.getValueType(), CMP00, CMP01,
24185 DAG.getConstant(x86cc, MVT::i8));
24187 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24188 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24190 if (is64BitFP && !Subtarget->is64Bit()) {
24191 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24192 // 64-bit integer, since that's not a legal type. Since
24193 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24194 // bits, but can do this little dance to extract the lowest 32 bits
24195 // and work with those going forward.
24196 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24198 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24200 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24201 Vector32, DAG.getIntPtrConstant(0));
24205 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24206 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24207 DAG.getConstant(1, IntVT));
24208 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24209 return OneBitOfTruth;
24217 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24218 /// so it can be folded inside ANDNP.
24219 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24220 EVT VT = N->getValueType(0);
24222 // Match direct AllOnes for 128 and 256-bit vectors
24223 if (ISD::isBuildVectorAllOnes(N))
24226 // Look through a bit convert.
24227 if (N->getOpcode() == ISD::BITCAST)
24228 N = N->getOperand(0).getNode();
24230 // Sometimes the operand may come from a insert_subvector building a 256-bit
24232 if (VT.is256BitVector() &&
24233 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24234 SDValue V1 = N->getOperand(0);
24235 SDValue V2 = N->getOperand(1);
24237 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24238 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24239 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24240 ISD::isBuildVectorAllOnes(V2.getNode()))
24247 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24248 // register. In most cases we actually compare or select YMM-sized registers
24249 // and mixing the two types creates horrible code. This method optimizes
24250 // some of the transition sequences.
24251 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24252 TargetLowering::DAGCombinerInfo &DCI,
24253 const X86Subtarget *Subtarget) {
24254 EVT VT = N->getValueType(0);
24255 if (!VT.is256BitVector())
24258 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24259 N->getOpcode() == ISD::ZERO_EXTEND ||
24260 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24262 SDValue Narrow = N->getOperand(0);
24263 EVT NarrowVT = Narrow->getValueType(0);
24264 if (!NarrowVT.is128BitVector())
24267 if (Narrow->getOpcode() != ISD::XOR &&
24268 Narrow->getOpcode() != ISD::AND &&
24269 Narrow->getOpcode() != ISD::OR)
24272 SDValue N0 = Narrow->getOperand(0);
24273 SDValue N1 = Narrow->getOperand(1);
24276 // The Left side has to be a trunc.
24277 if (N0.getOpcode() != ISD::TRUNCATE)
24280 // The type of the truncated inputs.
24281 EVT WideVT = N0->getOperand(0)->getValueType(0);
24285 // The right side has to be a 'trunc' or a constant vector.
24286 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24287 ConstantSDNode *RHSConstSplat = nullptr;
24288 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24289 RHSConstSplat = RHSBV->getConstantSplatNode();
24290 if (!RHSTrunc && !RHSConstSplat)
24293 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24295 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24298 // Set N0 and N1 to hold the inputs to the new wide operation.
24299 N0 = N0->getOperand(0);
24300 if (RHSConstSplat) {
24301 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24302 SDValue(RHSConstSplat, 0));
24303 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24304 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24305 } else if (RHSTrunc) {
24306 N1 = N1->getOperand(0);
24309 // Generate the wide operation.
24310 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24311 unsigned Opcode = N->getOpcode();
24313 case ISD::ANY_EXTEND:
24315 case ISD::ZERO_EXTEND: {
24316 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24317 APInt Mask = APInt::getAllOnesValue(InBits);
24318 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24319 return DAG.getNode(ISD::AND, DL, VT,
24320 Op, DAG.getConstant(Mask, VT));
24322 case ISD::SIGN_EXTEND:
24323 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24324 Op, DAG.getValueType(NarrowVT));
24326 llvm_unreachable("Unexpected opcode");
24330 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24331 TargetLowering::DAGCombinerInfo &DCI,
24332 const X86Subtarget *Subtarget) {
24333 EVT VT = N->getValueType(0);
24334 if (DCI.isBeforeLegalizeOps())
24337 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24341 // Create BEXTR instructions
24342 // BEXTR is ((X >> imm) & (2**size-1))
24343 if (VT == MVT::i32 || VT == MVT::i64) {
24344 SDValue N0 = N->getOperand(0);
24345 SDValue N1 = N->getOperand(1);
24348 // Check for BEXTR.
24349 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24350 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24351 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24352 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24353 if (MaskNode && ShiftNode) {
24354 uint64_t Mask = MaskNode->getZExtValue();
24355 uint64_t Shift = ShiftNode->getZExtValue();
24356 if (isMask_64(Mask)) {
24357 uint64_t MaskSize = CountPopulation_64(Mask);
24358 if (Shift + MaskSize <= VT.getSizeInBits())
24359 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24360 DAG.getConstant(Shift | (MaskSize << 8), VT));
24368 // Want to form ANDNP nodes:
24369 // 1) In the hopes of then easily combining them with OR and AND nodes
24370 // to form PBLEND/PSIGN.
24371 // 2) To match ANDN packed intrinsics
24372 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24375 SDValue N0 = N->getOperand(0);
24376 SDValue N1 = N->getOperand(1);
24379 // Check LHS for vnot
24380 if (N0.getOpcode() == ISD::XOR &&
24381 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24382 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24383 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24385 // Check RHS for vnot
24386 if (N1.getOpcode() == ISD::XOR &&
24387 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24388 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24389 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24394 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24395 TargetLowering::DAGCombinerInfo &DCI,
24396 const X86Subtarget *Subtarget) {
24397 if (DCI.isBeforeLegalizeOps())
24400 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24404 SDValue N0 = N->getOperand(0);
24405 SDValue N1 = N->getOperand(1);
24406 EVT VT = N->getValueType(0);
24408 // look for psign/blend
24409 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24410 if (!Subtarget->hasSSSE3() ||
24411 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24414 // Canonicalize pandn to RHS
24415 if (N0.getOpcode() == X86ISD::ANDNP)
24417 // or (and (m, y), (pandn m, x))
24418 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24419 SDValue Mask = N1.getOperand(0);
24420 SDValue X = N1.getOperand(1);
24422 if (N0.getOperand(0) == Mask)
24423 Y = N0.getOperand(1);
24424 if (N0.getOperand(1) == Mask)
24425 Y = N0.getOperand(0);
24427 // Check to see if the mask appeared in both the AND and ANDNP and
24431 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24432 // Look through mask bitcast.
24433 if (Mask.getOpcode() == ISD::BITCAST)
24434 Mask = Mask.getOperand(0);
24435 if (X.getOpcode() == ISD::BITCAST)
24436 X = X.getOperand(0);
24437 if (Y.getOpcode() == ISD::BITCAST)
24438 Y = Y.getOperand(0);
24440 EVT MaskVT = Mask.getValueType();
24442 // Validate that the Mask operand is a vector sra node.
24443 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24444 // there is no psrai.b
24445 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24446 unsigned SraAmt = ~0;
24447 if (Mask.getOpcode() == ISD::SRA) {
24448 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24449 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24450 SraAmt = AmtConst->getZExtValue();
24451 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24452 SDValue SraC = Mask.getOperand(1);
24453 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24455 if ((SraAmt + 1) != EltBits)
24460 // Now we know we at least have a plendvb with the mask val. See if
24461 // we can form a psignb/w/d.
24462 // psign = x.type == y.type == mask.type && y = sub(0, x);
24463 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24464 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24465 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24466 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24467 "Unsupported VT for PSIGN");
24468 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24469 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24471 // PBLENDVB only available on SSE 4.1
24472 if (!Subtarget->hasSSE41())
24475 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24477 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24478 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24479 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24480 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24481 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24485 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24488 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24489 MachineFunction &MF = DAG.getMachineFunction();
24490 bool OptForSize = MF.getFunction()->getAttributes().
24491 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24493 // SHLD/SHRD instructions have lower register pressure, but on some
24494 // platforms they have higher latency than the equivalent
24495 // series of shifts/or that would otherwise be generated.
24496 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24497 // have higher latencies and we are not optimizing for size.
24498 if (!OptForSize && Subtarget->isSHLDSlow())
24501 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24503 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24505 if (!N0.hasOneUse() || !N1.hasOneUse())
24508 SDValue ShAmt0 = N0.getOperand(1);
24509 if (ShAmt0.getValueType() != MVT::i8)
24511 SDValue ShAmt1 = N1.getOperand(1);
24512 if (ShAmt1.getValueType() != MVT::i8)
24514 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24515 ShAmt0 = ShAmt0.getOperand(0);
24516 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24517 ShAmt1 = ShAmt1.getOperand(0);
24520 unsigned Opc = X86ISD::SHLD;
24521 SDValue Op0 = N0.getOperand(0);
24522 SDValue Op1 = N1.getOperand(0);
24523 if (ShAmt0.getOpcode() == ISD::SUB) {
24524 Opc = X86ISD::SHRD;
24525 std::swap(Op0, Op1);
24526 std::swap(ShAmt0, ShAmt1);
24529 unsigned Bits = VT.getSizeInBits();
24530 if (ShAmt1.getOpcode() == ISD::SUB) {
24531 SDValue Sum = ShAmt1.getOperand(0);
24532 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24533 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24534 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24535 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24536 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24537 return DAG.getNode(Opc, DL, VT,
24539 DAG.getNode(ISD::TRUNCATE, DL,
24542 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24543 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24545 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24546 return DAG.getNode(Opc, DL, VT,
24547 N0.getOperand(0), N1.getOperand(0),
24548 DAG.getNode(ISD::TRUNCATE, DL,
24555 // Generate NEG and CMOV for integer abs.
24556 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24557 EVT VT = N->getValueType(0);
24559 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24560 // 8-bit integer abs to NEG and CMOV.
24561 if (VT.isInteger() && VT.getSizeInBits() == 8)
24564 SDValue N0 = N->getOperand(0);
24565 SDValue N1 = N->getOperand(1);
24568 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24569 // and change it to SUB and CMOV.
24570 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24571 N0.getOpcode() == ISD::ADD &&
24572 N0.getOperand(1) == N1 &&
24573 N1.getOpcode() == ISD::SRA &&
24574 N1.getOperand(0) == N0.getOperand(0))
24575 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24576 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24577 // Generate SUB & CMOV.
24578 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24579 DAG.getConstant(0, VT), N0.getOperand(0));
24581 SDValue Ops[] = { N0.getOperand(0), Neg,
24582 DAG.getConstant(X86::COND_GE, MVT::i8),
24583 SDValue(Neg.getNode(), 1) };
24584 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24589 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24590 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24591 TargetLowering::DAGCombinerInfo &DCI,
24592 const X86Subtarget *Subtarget) {
24593 if (DCI.isBeforeLegalizeOps())
24596 if (Subtarget->hasCMov()) {
24597 SDValue RV = performIntegerAbsCombine(N, DAG);
24605 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24606 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24607 TargetLowering::DAGCombinerInfo &DCI,
24608 const X86Subtarget *Subtarget) {
24609 LoadSDNode *Ld = cast<LoadSDNode>(N);
24610 EVT RegVT = Ld->getValueType(0);
24611 EVT MemVT = Ld->getMemoryVT();
24613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24615 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24616 // into two 16-byte operations.
24617 ISD::LoadExtType Ext = Ld->getExtensionType();
24618 unsigned Alignment = Ld->getAlignment();
24619 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24620 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24621 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24622 unsigned NumElems = RegVT.getVectorNumElements();
24626 SDValue Ptr = Ld->getBasePtr();
24627 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24629 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24631 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24632 Ld->getPointerInfo(), Ld->isVolatile(),
24633 Ld->isNonTemporal(), Ld->isInvariant(),
24635 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24636 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24637 Ld->getPointerInfo(), Ld->isVolatile(),
24638 Ld->isNonTemporal(), Ld->isInvariant(),
24639 std::min(16U, Alignment));
24640 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24642 Load2.getValue(1));
24644 SDValue NewVec = DAG.getUNDEF(RegVT);
24645 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24646 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24647 return DCI.CombineTo(N, NewVec, TF, true);
24653 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24654 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24655 const X86Subtarget *Subtarget) {
24656 StoreSDNode *St = cast<StoreSDNode>(N);
24657 EVT VT = St->getValue().getValueType();
24658 EVT StVT = St->getMemoryVT();
24660 SDValue StoredVal = St->getOperand(1);
24661 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24663 // If we are saving a concatenation of two XMM registers and 32-byte stores
24664 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24665 unsigned Alignment = St->getAlignment();
24666 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24667 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24668 StVT == VT && !IsAligned) {
24669 unsigned NumElems = VT.getVectorNumElements();
24673 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24674 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24676 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24677 SDValue Ptr0 = St->getBasePtr();
24678 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24680 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24681 St->getPointerInfo(), St->isVolatile(),
24682 St->isNonTemporal(), Alignment);
24683 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24684 St->getPointerInfo(), St->isVolatile(),
24685 St->isNonTemporal(),
24686 std::min(16U, Alignment));
24687 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24690 // Optimize trunc store (of multiple scalars) to shuffle and store.
24691 // First, pack all of the elements in one place. Next, store to memory
24692 // in fewer chunks.
24693 if (St->isTruncatingStore() && VT.isVector()) {
24694 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24695 unsigned NumElems = VT.getVectorNumElements();
24696 assert(StVT != VT && "Cannot truncate to the same type");
24697 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24698 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24700 // From, To sizes and ElemCount must be pow of two
24701 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24702 // We are going to use the original vector elt for storing.
24703 // Accumulated smaller vector elements must be a multiple of the store size.
24704 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24706 unsigned SizeRatio = FromSz / ToSz;
24708 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24710 // Create a type on which we perform the shuffle
24711 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24712 StVT.getScalarType(), NumElems*SizeRatio);
24714 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24716 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24717 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24718 for (unsigned i = 0; i != NumElems; ++i)
24719 ShuffleVec[i] = i * SizeRatio;
24721 // Can't shuffle using an illegal type.
24722 if (!TLI.isTypeLegal(WideVecVT))
24725 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24726 DAG.getUNDEF(WideVecVT),
24728 // At this point all of the data is stored at the bottom of the
24729 // register. We now need to save it to mem.
24731 // Find the largest store unit
24732 MVT StoreType = MVT::i8;
24733 for (MVT Tp : MVT::integer_valuetypes()) {
24734 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24738 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24739 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24740 (64 <= NumElems * ToSz))
24741 StoreType = MVT::f64;
24743 // Bitcast the original vector into a vector of store-size units
24744 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24745 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24746 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24747 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24748 SmallVector<SDValue, 8> Chains;
24749 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24750 TLI.getPointerTy());
24751 SDValue Ptr = St->getBasePtr();
24753 // Perform one or more big stores into memory.
24754 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24755 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24756 StoreType, ShuffWide,
24757 DAG.getIntPtrConstant(i));
24758 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24759 St->getPointerInfo(), St->isVolatile(),
24760 St->isNonTemporal(), St->getAlignment());
24761 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24762 Chains.push_back(Ch);
24765 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24768 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24769 // the FP state in cases where an emms may be missing.
24770 // A preferable solution to the general problem is to figure out the right
24771 // places to insert EMMS. This qualifies as a quick hack.
24773 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24774 if (VT.getSizeInBits() != 64)
24777 const Function *F = DAG.getMachineFunction().getFunction();
24778 bool NoImplicitFloatOps = F->getAttributes().
24779 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24780 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24781 && Subtarget->hasSSE2();
24782 if ((VT.isVector() ||
24783 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24784 isa<LoadSDNode>(St->getValue()) &&
24785 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24786 St->getChain().hasOneUse() && !St->isVolatile()) {
24787 SDNode* LdVal = St->getValue().getNode();
24788 LoadSDNode *Ld = nullptr;
24789 int TokenFactorIndex = -1;
24790 SmallVector<SDValue, 8> Ops;
24791 SDNode* ChainVal = St->getChain().getNode();
24792 // Must be a store of a load. We currently handle two cases: the load
24793 // is a direct child, and it's under an intervening TokenFactor. It is
24794 // possible to dig deeper under nested TokenFactors.
24795 if (ChainVal == LdVal)
24796 Ld = cast<LoadSDNode>(St->getChain());
24797 else if (St->getValue().hasOneUse() &&
24798 ChainVal->getOpcode() == ISD::TokenFactor) {
24799 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24800 if (ChainVal->getOperand(i).getNode() == LdVal) {
24801 TokenFactorIndex = i;
24802 Ld = cast<LoadSDNode>(St->getValue());
24804 Ops.push_back(ChainVal->getOperand(i));
24808 if (!Ld || !ISD::isNormalLoad(Ld))
24811 // If this is not the MMX case, i.e. we are just turning i64 load/store
24812 // into f64 load/store, avoid the transformation if there are multiple
24813 // uses of the loaded value.
24814 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24819 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24820 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24822 if (Subtarget->is64Bit() || F64IsLegal) {
24823 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24824 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24825 Ld->getPointerInfo(), Ld->isVolatile(),
24826 Ld->isNonTemporal(), Ld->isInvariant(),
24827 Ld->getAlignment());
24828 SDValue NewChain = NewLd.getValue(1);
24829 if (TokenFactorIndex != -1) {
24830 Ops.push_back(NewChain);
24831 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24833 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24834 St->getPointerInfo(),
24835 St->isVolatile(), St->isNonTemporal(),
24836 St->getAlignment());
24839 // Otherwise, lower to two pairs of 32-bit loads / stores.
24840 SDValue LoAddr = Ld->getBasePtr();
24841 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24842 DAG.getConstant(4, MVT::i32));
24844 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24845 Ld->getPointerInfo(),
24846 Ld->isVolatile(), Ld->isNonTemporal(),
24847 Ld->isInvariant(), Ld->getAlignment());
24848 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24849 Ld->getPointerInfo().getWithOffset(4),
24850 Ld->isVolatile(), Ld->isNonTemporal(),
24852 MinAlign(Ld->getAlignment(), 4));
24854 SDValue NewChain = LoLd.getValue(1);
24855 if (TokenFactorIndex != -1) {
24856 Ops.push_back(LoLd);
24857 Ops.push_back(HiLd);
24858 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24861 LoAddr = St->getBasePtr();
24862 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24863 DAG.getConstant(4, MVT::i32));
24865 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24866 St->getPointerInfo(),
24867 St->isVolatile(), St->isNonTemporal(),
24868 St->getAlignment());
24869 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24870 St->getPointerInfo().getWithOffset(4),
24872 St->isNonTemporal(),
24873 MinAlign(St->getAlignment(), 4));
24874 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24879 /// Return 'true' if this vector operation is "horizontal"
24880 /// and return the operands for the horizontal operation in LHS and RHS. A
24881 /// horizontal operation performs the binary operation on successive elements
24882 /// of its first operand, then on successive elements of its second operand,
24883 /// returning the resulting values in a vector. For example, if
24884 /// A = < float a0, float a1, float a2, float a3 >
24886 /// B = < float b0, float b1, float b2, float b3 >
24887 /// then the result of doing a horizontal operation on A and B is
24888 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24889 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24890 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24891 /// set to A, RHS to B, and the routine returns 'true'.
24892 /// Note that the binary operation should have the property that if one of the
24893 /// operands is UNDEF then the result is UNDEF.
24894 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24895 // Look for the following pattern: if
24896 // A = < float a0, float a1, float a2, float a3 >
24897 // B = < float b0, float b1, float b2, float b3 >
24899 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24900 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24901 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24902 // which is A horizontal-op B.
24904 // At least one of the operands should be a vector shuffle.
24905 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24906 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24909 MVT VT = LHS.getSimpleValueType();
24911 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24912 "Unsupported vector type for horizontal add/sub");
24914 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24915 // operate independently on 128-bit lanes.
24916 unsigned NumElts = VT.getVectorNumElements();
24917 unsigned NumLanes = VT.getSizeInBits()/128;
24918 unsigned NumLaneElts = NumElts / NumLanes;
24919 assert((NumLaneElts % 2 == 0) &&
24920 "Vector type should have an even number of elements in each lane");
24921 unsigned HalfLaneElts = NumLaneElts/2;
24923 // View LHS in the form
24924 // LHS = VECTOR_SHUFFLE A, B, LMask
24925 // If LHS is not a shuffle then pretend it is the shuffle
24926 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24927 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24930 SmallVector<int, 16> LMask(NumElts);
24931 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24932 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24933 A = LHS.getOperand(0);
24934 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24935 B = LHS.getOperand(1);
24936 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24937 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24939 if (LHS.getOpcode() != ISD::UNDEF)
24941 for (unsigned i = 0; i != NumElts; ++i)
24945 // Likewise, view RHS in the form
24946 // RHS = VECTOR_SHUFFLE C, D, RMask
24948 SmallVector<int, 16> RMask(NumElts);
24949 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24950 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24951 C = RHS.getOperand(0);
24952 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24953 D = RHS.getOperand(1);
24954 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24955 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24957 if (RHS.getOpcode() != ISD::UNDEF)
24959 for (unsigned i = 0; i != NumElts; ++i)
24963 // Check that the shuffles are both shuffling the same vectors.
24964 if (!(A == C && B == D) && !(A == D && B == C))
24967 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24968 if (!A.getNode() && !B.getNode())
24971 // If A and B occur in reverse order in RHS, then "swap" them (which means
24972 // rewriting the mask).
24974 CommuteVectorShuffleMask(RMask, NumElts);
24976 // At this point LHS and RHS are equivalent to
24977 // LHS = VECTOR_SHUFFLE A, B, LMask
24978 // RHS = VECTOR_SHUFFLE A, B, RMask
24979 // Check that the masks correspond to performing a horizontal operation.
24980 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24981 for (unsigned i = 0; i != NumLaneElts; ++i) {
24982 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24984 // Ignore any UNDEF components.
24985 if (LIdx < 0 || RIdx < 0 ||
24986 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24987 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24990 // Check that successive elements are being operated on. If not, this is
24991 // not a horizontal operation.
24992 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24993 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24994 if (!(LIdx == Index && RIdx == Index + 1) &&
24995 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25000 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25001 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25005 /// Do target-specific dag combines on floating point adds.
25006 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25007 const X86Subtarget *Subtarget) {
25008 EVT VT = N->getValueType(0);
25009 SDValue LHS = N->getOperand(0);
25010 SDValue RHS = N->getOperand(1);
25012 // Try to synthesize horizontal adds from adds of shuffles.
25013 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25014 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25015 isHorizontalBinOp(LHS, RHS, true))
25016 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25020 /// Do target-specific dag combines on floating point subs.
25021 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25022 const X86Subtarget *Subtarget) {
25023 EVT VT = N->getValueType(0);
25024 SDValue LHS = N->getOperand(0);
25025 SDValue RHS = N->getOperand(1);
25027 // Try to synthesize horizontal subs from subs of shuffles.
25028 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25029 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25030 isHorizontalBinOp(LHS, RHS, false))
25031 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25035 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25036 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
25037 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25038 // F[X]OR(0.0, x) -> x
25039 // F[X]OR(x, 0.0) -> x
25040 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25041 if (C->getValueAPF().isPosZero())
25042 return N->getOperand(1);
25043 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25044 if (C->getValueAPF().isPosZero())
25045 return N->getOperand(0);
25049 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25050 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25051 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25053 // Only perform optimizations if UnsafeMath is used.
25054 if (!DAG.getTarget().Options.UnsafeFPMath)
25057 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25058 // into FMINC and FMAXC, which are Commutative operations.
25059 unsigned NewOp = 0;
25060 switch (N->getOpcode()) {
25061 default: llvm_unreachable("unknown opcode");
25062 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25063 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25066 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25067 N->getOperand(0), N->getOperand(1));
25070 /// Do target-specific dag combines on X86ISD::FAND nodes.
25071 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25072 // FAND(0.0, x) -> 0.0
25073 // FAND(x, 0.0) -> 0.0
25074 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25075 if (C->getValueAPF().isPosZero())
25076 return N->getOperand(0);
25077 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25078 if (C->getValueAPF().isPosZero())
25079 return N->getOperand(1);
25083 /// Do target-specific dag combines on X86ISD::FANDN nodes
25084 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25085 // FANDN(x, 0.0) -> 0.0
25086 // FANDN(0.0, x) -> x
25087 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25088 if (C->getValueAPF().isPosZero())
25089 return N->getOperand(1);
25090 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25091 if (C->getValueAPF().isPosZero())
25092 return N->getOperand(1);
25096 static SDValue PerformBTCombine(SDNode *N,
25098 TargetLowering::DAGCombinerInfo &DCI) {
25099 // BT ignores high bits in the bit index operand.
25100 SDValue Op1 = N->getOperand(1);
25101 if (Op1.hasOneUse()) {
25102 unsigned BitWidth = Op1.getValueSizeInBits();
25103 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25104 APInt KnownZero, KnownOne;
25105 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25106 !DCI.isBeforeLegalizeOps());
25107 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25108 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25109 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25110 DCI.CommitTargetLoweringOpt(TLO);
25115 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25116 SDValue Op = N->getOperand(0);
25117 if (Op.getOpcode() == ISD::BITCAST)
25118 Op = Op.getOperand(0);
25119 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25120 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25121 VT.getVectorElementType().getSizeInBits() ==
25122 OpVT.getVectorElementType().getSizeInBits()) {
25123 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25128 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25129 const X86Subtarget *Subtarget) {
25130 EVT VT = N->getValueType(0);
25131 if (!VT.isVector())
25134 SDValue N0 = N->getOperand(0);
25135 SDValue N1 = N->getOperand(1);
25136 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25139 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25140 // both SSE and AVX2 since there is no sign-extended shift right
25141 // operation on a vector with 64-bit elements.
25142 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25143 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25144 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25145 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25146 SDValue N00 = N0.getOperand(0);
25148 // EXTLOAD has a better solution on AVX2,
25149 // it may be replaced with X86ISD::VSEXT node.
25150 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25151 if (!ISD::isNormalLoad(N00.getNode()))
25154 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25155 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25157 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25163 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25164 TargetLowering::DAGCombinerInfo &DCI,
25165 const X86Subtarget *Subtarget) {
25166 SDValue N0 = N->getOperand(0);
25167 EVT VT = N->getValueType(0);
25169 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25170 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25171 // This exposes the sext to the sdivrem lowering, so that it directly extends
25172 // from AH (which we otherwise need to do contortions to access).
25173 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25174 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25176 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25177 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25178 N0.getOperand(0), N0.getOperand(1));
25179 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25180 return R.getValue(1);
25183 if (!DCI.isBeforeLegalizeOps())
25186 if (!Subtarget->hasFp256())
25189 if (VT.isVector() && VT.getSizeInBits() == 256) {
25190 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25198 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25199 const X86Subtarget* Subtarget) {
25201 EVT VT = N->getValueType(0);
25203 // Let legalize expand this if it isn't a legal type yet.
25204 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25207 EVT ScalarVT = VT.getScalarType();
25208 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25209 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25212 SDValue A = N->getOperand(0);
25213 SDValue B = N->getOperand(1);
25214 SDValue C = N->getOperand(2);
25216 bool NegA = (A.getOpcode() == ISD::FNEG);
25217 bool NegB = (B.getOpcode() == ISD::FNEG);
25218 bool NegC = (C.getOpcode() == ISD::FNEG);
25220 // Negative multiplication when NegA xor NegB
25221 bool NegMul = (NegA != NegB);
25223 A = A.getOperand(0);
25225 B = B.getOperand(0);
25227 C = C.getOperand(0);
25231 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25233 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25235 return DAG.getNode(Opcode, dl, VT, A, B, C);
25238 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25239 TargetLowering::DAGCombinerInfo &DCI,
25240 const X86Subtarget *Subtarget) {
25241 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25242 // (and (i32 x86isd::setcc_carry), 1)
25243 // This eliminates the zext. This transformation is necessary because
25244 // ISD::SETCC is always legalized to i8.
25246 SDValue N0 = N->getOperand(0);
25247 EVT VT = N->getValueType(0);
25249 if (N0.getOpcode() == ISD::AND &&
25251 N0.getOperand(0).hasOneUse()) {
25252 SDValue N00 = N0.getOperand(0);
25253 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25254 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25255 if (!C || C->getZExtValue() != 1)
25257 return DAG.getNode(ISD::AND, dl, VT,
25258 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25259 N00.getOperand(0), N00.getOperand(1)),
25260 DAG.getConstant(1, VT));
25264 if (N0.getOpcode() == ISD::TRUNCATE &&
25266 N0.getOperand(0).hasOneUse()) {
25267 SDValue N00 = N0.getOperand(0);
25268 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25269 return DAG.getNode(ISD::AND, dl, VT,
25270 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25271 N00.getOperand(0), N00.getOperand(1)),
25272 DAG.getConstant(1, VT));
25275 if (VT.is256BitVector()) {
25276 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25281 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25282 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25283 // This exposes the zext to the udivrem lowering, so that it directly extends
25284 // from AH (which we otherwise need to do contortions to access).
25285 if (N0.getOpcode() == ISD::UDIVREM &&
25286 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25287 (VT == MVT::i32 || VT == MVT::i64)) {
25288 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25289 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25290 N0.getOperand(0), N0.getOperand(1));
25291 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25292 return R.getValue(1);
25298 // Optimize x == -y --> x+y == 0
25299 // x != -y --> x+y != 0
25300 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25301 const X86Subtarget* Subtarget) {
25302 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25303 SDValue LHS = N->getOperand(0);
25304 SDValue RHS = N->getOperand(1);
25305 EVT VT = N->getValueType(0);
25308 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25309 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25310 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25311 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25312 LHS.getValueType(), RHS, LHS.getOperand(1));
25313 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25314 addV, DAG.getConstant(0, addV.getValueType()), CC);
25316 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25318 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25319 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25320 RHS.getValueType(), LHS, RHS.getOperand(1));
25321 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25322 addV, DAG.getConstant(0, addV.getValueType()), CC);
25325 if (VT.getScalarType() == MVT::i1) {
25326 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25327 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25328 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25329 if (!IsSEXT0 && !IsVZero0)
25331 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25332 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25333 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25335 if (!IsSEXT1 && !IsVZero1)
25338 if (IsSEXT0 && IsVZero1) {
25339 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25340 if (CC == ISD::SETEQ)
25341 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25342 return LHS.getOperand(0);
25344 if (IsSEXT1 && IsVZero0) {
25345 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25346 if (CC == ISD::SETEQ)
25347 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25348 return RHS.getOperand(0);
25355 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25356 const X86Subtarget *Subtarget) {
25358 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25359 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25360 "X86insertps is only defined for v4x32");
25362 SDValue Ld = N->getOperand(1);
25363 if (MayFoldLoad(Ld)) {
25364 // Extract the countS bits from the immediate so we can get the proper
25365 // address when narrowing the vector load to a specific element.
25366 // When the second source op is a memory address, interps doesn't use
25367 // countS and just gets an f32 from that address.
25368 unsigned DestIndex =
25369 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25370 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25374 // Create this as a scalar to vector to match the instruction pattern.
25375 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25376 // countS bits are ignored when loading from memory on insertps, which
25377 // means we don't need to explicitly set them to 0.
25378 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25379 LoadScalarToVector, N->getOperand(2));
25382 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25383 // as "sbb reg,reg", since it can be extended without zext and produces
25384 // an all-ones bit which is more useful than 0/1 in some cases.
25385 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25388 return DAG.getNode(ISD::AND, DL, VT,
25389 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25390 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25391 DAG.getConstant(1, VT));
25392 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25393 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25394 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25395 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25398 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25399 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25400 TargetLowering::DAGCombinerInfo &DCI,
25401 const X86Subtarget *Subtarget) {
25403 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25404 SDValue EFLAGS = N->getOperand(1);
25406 if (CC == X86::COND_A) {
25407 // Try to convert COND_A into COND_B in an attempt to facilitate
25408 // materializing "setb reg".
25410 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25411 // cannot take an immediate as its first operand.
25413 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25414 EFLAGS.getValueType().isInteger() &&
25415 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25416 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25417 EFLAGS.getNode()->getVTList(),
25418 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25419 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25420 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25424 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25425 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25427 if (CC == X86::COND_B)
25428 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25432 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25433 if (Flags.getNode()) {
25434 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25435 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25441 // Optimize branch condition evaluation.
25443 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25444 TargetLowering::DAGCombinerInfo &DCI,
25445 const X86Subtarget *Subtarget) {
25447 SDValue Chain = N->getOperand(0);
25448 SDValue Dest = N->getOperand(1);
25449 SDValue EFLAGS = N->getOperand(3);
25450 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25454 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25455 if (Flags.getNode()) {
25456 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25457 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25464 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25465 SelectionDAG &DAG) {
25466 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25467 // optimize away operation when it's from a constant.
25469 // The general transformation is:
25470 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25471 // AND(VECTOR_CMP(x,y), constant2)
25472 // constant2 = UNARYOP(constant)
25474 // Early exit if this isn't a vector operation, the operand of the
25475 // unary operation isn't a bitwise AND, or if the sizes of the operations
25476 // aren't the same.
25477 EVT VT = N->getValueType(0);
25478 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25479 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25480 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25483 // Now check that the other operand of the AND is a constant. We could
25484 // make the transformation for non-constant splats as well, but it's unclear
25485 // that would be a benefit as it would not eliminate any operations, just
25486 // perform one more step in scalar code before moving to the vector unit.
25487 if (BuildVectorSDNode *BV =
25488 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25489 // Bail out if the vector isn't a constant.
25490 if (!BV->isConstant())
25493 // Everything checks out. Build up the new and improved node.
25495 EVT IntVT = BV->getValueType(0);
25496 // Create a new constant of the appropriate type for the transformed
25498 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25499 // The AND node needs bitcasts to/from an integer vector type around it.
25500 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25501 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25502 N->getOperand(0)->getOperand(0), MaskConst);
25503 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25510 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25511 const X86TargetLowering *XTLI) {
25512 // First try to optimize away the conversion entirely when it's
25513 // conditionally from a constant. Vectors only.
25514 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25515 if (Res != SDValue())
25518 // Now move on to more general possibilities.
25519 SDValue Op0 = N->getOperand(0);
25520 EVT InVT = Op0->getValueType(0);
25522 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25523 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25525 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25526 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25527 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25530 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25531 // a 32-bit target where SSE doesn't support i64->FP operations.
25532 if (Op0.getOpcode() == ISD::LOAD) {
25533 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25534 EVT VT = Ld->getValueType(0);
25535 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25536 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25537 !XTLI->getSubtarget()->is64Bit() &&
25539 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25540 Ld->getChain(), Op0, DAG);
25541 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25548 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25549 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25550 X86TargetLowering::DAGCombinerInfo &DCI) {
25551 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25552 // the result is either zero or one (depending on the input carry bit).
25553 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25554 if (X86::isZeroNode(N->getOperand(0)) &&
25555 X86::isZeroNode(N->getOperand(1)) &&
25556 // We don't have a good way to replace an EFLAGS use, so only do this when
25558 SDValue(N, 1).use_empty()) {
25560 EVT VT = N->getValueType(0);
25561 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25562 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25563 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25564 DAG.getConstant(X86::COND_B,MVT::i8),
25566 DAG.getConstant(1, VT));
25567 return DCI.CombineTo(N, Res1, CarryOut);
25573 // fold (add Y, (sete X, 0)) -> adc 0, Y
25574 // (add Y, (setne X, 0)) -> sbb -1, Y
25575 // (sub (sete X, 0), Y) -> sbb 0, Y
25576 // (sub (setne X, 0), Y) -> adc -1, Y
25577 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25580 // Look through ZExts.
25581 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25582 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25585 SDValue SetCC = Ext.getOperand(0);
25586 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25589 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25590 if (CC != X86::COND_E && CC != X86::COND_NE)
25593 SDValue Cmp = SetCC.getOperand(1);
25594 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25595 !X86::isZeroNode(Cmp.getOperand(1)) ||
25596 !Cmp.getOperand(0).getValueType().isInteger())
25599 SDValue CmpOp0 = Cmp.getOperand(0);
25600 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25601 DAG.getConstant(1, CmpOp0.getValueType()));
25603 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25604 if (CC == X86::COND_NE)
25605 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25606 DL, OtherVal.getValueType(), OtherVal,
25607 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25608 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25609 DL, OtherVal.getValueType(), OtherVal,
25610 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25613 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25614 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25615 const X86Subtarget *Subtarget) {
25616 EVT VT = N->getValueType(0);
25617 SDValue Op0 = N->getOperand(0);
25618 SDValue Op1 = N->getOperand(1);
25620 // Try to synthesize horizontal adds from adds of shuffles.
25621 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25622 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25623 isHorizontalBinOp(Op0, Op1, true))
25624 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25626 return OptimizeConditionalInDecrement(N, DAG);
25629 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25630 const X86Subtarget *Subtarget) {
25631 SDValue Op0 = N->getOperand(0);
25632 SDValue Op1 = N->getOperand(1);
25634 // X86 can't encode an immediate LHS of a sub. See if we can push the
25635 // negation into a preceding instruction.
25636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25637 // If the RHS of the sub is a XOR with one use and a constant, invert the
25638 // immediate. Then add one to the LHS of the sub so we can turn
25639 // X-Y -> X+~Y+1, saving one register.
25640 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25641 isa<ConstantSDNode>(Op1.getOperand(1))) {
25642 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25643 EVT VT = Op0.getValueType();
25644 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25646 DAG.getConstant(~XorC, VT));
25647 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25648 DAG.getConstant(C->getAPIntValue()+1, VT));
25652 // Try to synthesize horizontal adds from adds of shuffles.
25653 EVT VT = N->getValueType(0);
25654 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25655 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25656 isHorizontalBinOp(Op0, Op1, true))
25657 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25659 return OptimizeConditionalInDecrement(N, DAG);
25662 /// performVZEXTCombine - Performs build vector combines
25663 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25664 TargetLowering::DAGCombinerInfo &DCI,
25665 const X86Subtarget *Subtarget) {
25667 MVT VT = N->getSimpleValueType(0);
25668 SDValue Op = N->getOperand(0);
25669 MVT OpVT = Op.getSimpleValueType();
25670 MVT OpEltVT = OpVT.getVectorElementType();
25671 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25673 // (vzext (bitcast (vzext (x)) -> (vzext x)
25675 while (V.getOpcode() == ISD::BITCAST)
25676 V = V.getOperand(0);
25678 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25679 MVT InnerVT = V.getSimpleValueType();
25680 MVT InnerEltVT = InnerVT.getVectorElementType();
25682 // If the element sizes match exactly, we can just do one larger vzext. This
25683 // is always an exact type match as vzext operates on integer types.
25684 if (OpEltVT == InnerEltVT) {
25685 assert(OpVT == InnerVT && "Types must match for vzext!");
25686 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25689 // The only other way we can combine them is if only a single element of the
25690 // inner vzext is used in the input to the outer vzext.
25691 if (InnerEltVT.getSizeInBits() < InputBits)
25694 // In this case, the inner vzext is completely dead because we're going to
25695 // only look at bits inside of the low element. Just do the outer vzext on
25696 // a bitcast of the input to the inner.
25697 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25698 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25701 // Check if we can bypass extracting and re-inserting an element of an input
25702 // vector. Essentialy:
25703 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25704 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25705 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25706 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25707 SDValue ExtractedV = V.getOperand(0);
25708 SDValue OrigV = ExtractedV.getOperand(0);
25709 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25710 if (ExtractIdx->getZExtValue() == 0) {
25711 MVT OrigVT = OrigV.getSimpleValueType();
25712 // Extract a subvector if necessary...
25713 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25714 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25715 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25716 OrigVT.getVectorNumElements() / Ratio);
25717 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25718 DAG.getIntPtrConstant(0));
25720 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25721 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25728 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25729 DAGCombinerInfo &DCI) const {
25730 SelectionDAG &DAG = DCI.DAG;
25731 switch (N->getOpcode()) {
25733 case ISD::EXTRACT_VECTOR_ELT:
25734 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25737 case X86ISD::SHRUNKBLEND:
25738 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25739 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25740 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25741 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25742 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25743 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25746 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25747 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25748 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25749 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25750 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25751 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25752 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25753 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25754 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25756 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25758 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25759 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25760 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25761 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25762 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25763 case ISD::ANY_EXTEND:
25764 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25765 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25766 case ISD::SIGN_EXTEND_INREG:
25767 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25768 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25769 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25770 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25771 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25772 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25773 case X86ISD::SHUFP: // Handle all target specific shuffles
25774 case X86ISD::PALIGNR:
25775 case X86ISD::UNPCKH:
25776 case X86ISD::UNPCKL:
25777 case X86ISD::MOVHLPS:
25778 case X86ISD::MOVLHPS:
25779 case X86ISD::PSHUFB:
25780 case X86ISD::PSHUFD:
25781 case X86ISD::PSHUFHW:
25782 case X86ISD::PSHUFLW:
25783 case X86ISD::MOVSS:
25784 case X86ISD::MOVSD:
25785 case X86ISD::VPERMILPI:
25786 case X86ISD::VPERM2X128:
25787 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25788 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25789 case ISD::INTRINSIC_WO_CHAIN:
25790 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25791 case X86ISD::INSERTPS:
25792 return PerformINSERTPSCombine(N, DAG, Subtarget);
25793 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25799 /// isTypeDesirableForOp - Return true if the target has native support for
25800 /// the specified value type and it is 'desirable' to use the type for the
25801 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25802 /// instruction encodings are longer and some i16 instructions are slow.
25803 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25804 if (!isTypeLegal(VT))
25806 if (VT != MVT::i16)
25813 case ISD::SIGN_EXTEND:
25814 case ISD::ZERO_EXTEND:
25815 case ISD::ANY_EXTEND:
25828 /// IsDesirableToPromoteOp - This method query the target whether it is
25829 /// beneficial for dag combiner to promote the specified node. If true, it
25830 /// should return the desired promotion type by reference.
25831 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25832 EVT VT = Op.getValueType();
25833 if (VT != MVT::i16)
25836 bool Promote = false;
25837 bool Commute = false;
25838 switch (Op.getOpcode()) {
25841 LoadSDNode *LD = cast<LoadSDNode>(Op);
25842 // If the non-extending load has a single use and it's not live out, then it
25843 // might be folded.
25844 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25845 Op.hasOneUse()*/) {
25846 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25847 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25848 // The only case where we'd want to promote LOAD (rather then it being
25849 // promoted as an operand is when it's only use is liveout.
25850 if (UI->getOpcode() != ISD::CopyToReg)
25857 case ISD::SIGN_EXTEND:
25858 case ISD::ZERO_EXTEND:
25859 case ISD::ANY_EXTEND:
25864 SDValue N0 = Op.getOperand(0);
25865 // Look out for (store (shl (load), x)).
25866 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25879 SDValue N0 = Op.getOperand(0);
25880 SDValue N1 = Op.getOperand(1);
25881 if (!Commute && MayFoldLoad(N1))
25883 // Avoid disabling potential load folding opportunities.
25884 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25886 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25896 //===----------------------------------------------------------------------===//
25897 // X86 Inline Assembly Support
25898 //===----------------------------------------------------------------------===//
25901 // Helper to match a string separated by whitespace.
25902 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25903 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25905 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25906 StringRef piece(*args[i]);
25907 if (!s.startswith(piece)) // Check if the piece matches.
25910 s = s.substr(piece.size());
25911 StringRef::size_type pos = s.find_first_not_of(" \t");
25912 if (pos == 0) // We matched a prefix.
25920 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25923 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25925 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25926 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25927 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25928 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25930 if (AsmPieces.size() == 3)
25932 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25939 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25940 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25942 std::string AsmStr = IA->getAsmString();
25944 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25945 if (!Ty || Ty->getBitWidth() % 16 != 0)
25948 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25949 SmallVector<StringRef, 4> AsmPieces;
25950 SplitString(AsmStr, AsmPieces, ";\n");
25952 switch (AsmPieces.size()) {
25953 default: return false;
25955 // FIXME: this should verify that we are targeting a 486 or better. If not,
25956 // we will turn this bswap into something that will be lowered to logical
25957 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25958 // lower so don't worry about this.
25960 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25961 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25962 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25963 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25964 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25965 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25966 // No need to check constraints, nothing other than the equivalent of
25967 // "=r,0" would be valid here.
25968 return IntrinsicLowering::LowerToByteSwap(CI);
25971 // rorw $$8, ${0:w} --> llvm.bswap.i16
25972 if (CI->getType()->isIntegerTy(16) &&
25973 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25974 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25975 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25977 const std::string &ConstraintsStr = IA->getConstraintString();
25978 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25979 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25980 if (clobbersFlagRegisters(AsmPieces))
25981 return IntrinsicLowering::LowerToByteSwap(CI);
25985 if (CI->getType()->isIntegerTy(32) &&
25986 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25987 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25988 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25989 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25991 const std::string &ConstraintsStr = IA->getConstraintString();
25992 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25993 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25994 if (clobbersFlagRegisters(AsmPieces))
25995 return IntrinsicLowering::LowerToByteSwap(CI);
25998 if (CI->getType()->isIntegerTy(64)) {
25999 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26000 if (Constraints.size() >= 2 &&
26001 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26002 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26003 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26004 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
26005 matchAsm(AsmPieces[1], "bswap", "%edx") &&
26006 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
26007 return IntrinsicLowering::LowerToByteSwap(CI);
26015 /// getConstraintType - Given a constraint letter, return the type of
26016 /// constraint it is for this target.
26017 X86TargetLowering::ConstraintType
26018 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
26019 if (Constraint.size() == 1) {
26020 switch (Constraint[0]) {
26031 return C_RegisterClass;
26055 return TargetLowering::getConstraintType(Constraint);
26058 /// Examine constraint type and operand type and determine a weight value.
26059 /// This object must already have been set up with the operand type
26060 /// and the current alternative constraint selected.
26061 TargetLowering::ConstraintWeight
26062 X86TargetLowering::getSingleConstraintMatchWeight(
26063 AsmOperandInfo &info, const char *constraint) const {
26064 ConstraintWeight weight = CW_Invalid;
26065 Value *CallOperandVal = info.CallOperandVal;
26066 // If we don't have a value, we can't do a match,
26067 // but allow it at the lowest weight.
26068 if (!CallOperandVal)
26070 Type *type = CallOperandVal->getType();
26071 // Look at the constraint type.
26072 switch (*constraint) {
26074 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26085 if (CallOperandVal->getType()->isIntegerTy())
26086 weight = CW_SpecificReg;
26091 if (type->isFloatingPointTy())
26092 weight = CW_SpecificReg;
26095 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26096 weight = CW_SpecificReg;
26100 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26101 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26102 weight = CW_Register;
26105 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26106 if (C->getZExtValue() <= 31)
26107 weight = CW_Constant;
26111 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26112 if (C->getZExtValue() <= 63)
26113 weight = CW_Constant;
26117 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26118 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26119 weight = CW_Constant;
26123 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26124 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26125 weight = CW_Constant;
26129 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26130 if (C->getZExtValue() <= 3)
26131 weight = CW_Constant;
26135 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26136 if (C->getZExtValue() <= 0xff)
26137 weight = CW_Constant;
26142 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26143 weight = CW_Constant;
26147 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26148 if ((C->getSExtValue() >= -0x80000000LL) &&
26149 (C->getSExtValue() <= 0x7fffffffLL))
26150 weight = CW_Constant;
26154 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26155 if (C->getZExtValue() <= 0xffffffff)
26156 weight = CW_Constant;
26163 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26164 /// with another that has more specific requirements based on the type of the
26165 /// corresponding operand.
26166 const char *X86TargetLowering::
26167 LowerXConstraint(EVT ConstraintVT) const {
26168 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26169 // 'f' like normal targets.
26170 if (ConstraintVT.isFloatingPoint()) {
26171 if (Subtarget->hasSSE2())
26173 if (Subtarget->hasSSE1())
26177 return TargetLowering::LowerXConstraint(ConstraintVT);
26180 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26181 /// vector. If it is invalid, don't add anything to Ops.
26182 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26183 std::string &Constraint,
26184 std::vector<SDValue>&Ops,
26185 SelectionDAG &DAG) const {
26188 // Only support length 1 constraints for now.
26189 if (Constraint.length() > 1) return;
26191 char ConstraintLetter = Constraint[0];
26192 switch (ConstraintLetter) {
26195 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26196 if (C->getZExtValue() <= 31) {
26197 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26203 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26204 if (C->getZExtValue() <= 63) {
26205 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26212 if (isInt<8>(C->getSExtValue())) {
26213 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26219 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26220 if (C->getZExtValue() <= 255) {
26221 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26227 // 32-bit signed value
26228 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26229 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26230 C->getSExtValue())) {
26231 // Widen to 64 bits here to get it sign extended.
26232 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26235 // FIXME gcc accepts some relocatable values here too, but only in certain
26236 // memory models; it's complicated.
26241 // 32-bit unsigned value
26242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26243 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26244 C->getZExtValue())) {
26245 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26249 // FIXME gcc accepts some relocatable values here too, but only in certain
26250 // memory models; it's complicated.
26254 // Literal immediates are always ok.
26255 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26256 // Widen to 64 bits here to get it sign extended.
26257 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26261 // In any sort of PIC mode addresses need to be computed at runtime by
26262 // adding in a register or some sort of table lookup. These can't
26263 // be used as immediates.
26264 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26267 // If we are in non-pic codegen mode, we allow the address of a global (with
26268 // an optional displacement) to be used with 'i'.
26269 GlobalAddressSDNode *GA = nullptr;
26270 int64_t Offset = 0;
26272 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26274 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26275 Offset += GA->getOffset();
26277 } else if (Op.getOpcode() == ISD::ADD) {
26278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26279 Offset += C->getZExtValue();
26280 Op = Op.getOperand(0);
26283 } else if (Op.getOpcode() == ISD::SUB) {
26284 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26285 Offset += -C->getZExtValue();
26286 Op = Op.getOperand(0);
26291 // Otherwise, this isn't something we can handle, reject it.
26295 const GlobalValue *GV = GA->getGlobal();
26296 // If we require an extra load to get this address, as in PIC mode, we
26297 // can't accept it.
26298 if (isGlobalStubReference(
26299 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26302 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26303 GA->getValueType(0), Offset);
26308 if (Result.getNode()) {
26309 Ops.push_back(Result);
26312 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26315 std::pair<unsigned, const TargetRegisterClass*>
26316 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26318 // First, see if this is a constraint that directly corresponds to an LLVM
26320 if (Constraint.size() == 1) {
26321 // GCC Constraint Letters
26322 switch (Constraint[0]) {
26324 // TODO: Slight differences here in allocation order and leaving
26325 // RIP in the class. Do they matter any more here than they do
26326 // in the normal allocation?
26327 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26328 if (Subtarget->is64Bit()) {
26329 if (VT == MVT::i32 || VT == MVT::f32)
26330 return std::make_pair(0U, &X86::GR32RegClass);
26331 if (VT == MVT::i16)
26332 return std::make_pair(0U, &X86::GR16RegClass);
26333 if (VT == MVT::i8 || VT == MVT::i1)
26334 return std::make_pair(0U, &X86::GR8RegClass);
26335 if (VT == MVT::i64 || VT == MVT::f64)
26336 return std::make_pair(0U, &X86::GR64RegClass);
26339 // 32-bit fallthrough
26340 case 'Q': // Q_REGS
26341 if (VT == MVT::i32 || VT == MVT::f32)
26342 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26343 if (VT == MVT::i16)
26344 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26345 if (VT == MVT::i8 || VT == MVT::i1)
26346 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26347 if (VT == MVT::i64)
26348 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26350 case 'r': // GENERAL_REGS
26351 case 'l': // INDEX_REGS
26352 if (VT == MVT::i8 || VT == MVT::i1)
26353 return std::make_pair(0U, &X86::GR8RegClass);
26354 if (VT == MVT::i16)
26355 return std::make_pair(0U, &X86::GR16RegClass);
26356 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26357 return std::make_pair(0U, &X86::GR32RegClass);
26358 return std::make_pair(0U, &X86::GR64RegClass);
26359 case 'R': // LEGACY_REGS
26360 if (VT == MVT::i8 || VT == MVT::i1)
26361 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26362 if (VT == MVT::i16)
26363 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26364 if (VT == MVT::i32 || !Subtarget->is64Bit())
26365 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26366 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26367 case 'f': // FP Stack registers.
26368 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26369 // value to the correct fpstack register class.
26370 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26371 return std::make_pair(0U, &X86::RFP32RegClass);
26372 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26373 return std::make_pair(0U, &X86::RFP64RegClass);
26374 return std::make_pair(0U, &X86::RFP80RegClass);
26375 case 'y': // MMX_REGS if MMX allowed.
26376 if (!Subtarget->hasMMX()) break;
26377 return std::make_pair(0U, &X86::VR64RegClass);
26378 case 'Y': // SSE_REGS if SSE2 allowed
26379 if (!Subtarget->hasSSE2()) break;
26381 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26382 if (!Subtarget->hasSSE1()) break;
26384 switch (VT.SimpleTy) {
26386 // Scalar SSE types.
26389 return std::make_pair(0U, &X86::FR32RegClass);
26392 return std::make_pair(0U, &X86::FR64RegClass);
26400 return std::make_pair(0U, &X86::VR128RegClass);
26408 return std::make_pair(0U, &X86::VR256RegClass);
26413 return std::make_pair(0U, &X86::VR512RegClass);
26419 // Use the default implementation in TargetLowering to convert the register
26420 // constraint into a member of a register class.
26421 std::pair<unsigned, const TargetRegisterClass*> Res;
26422 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26424 // Not found as a standard register?
26426 // Map st(0) -> st(7) -> ST0
26427 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26428 tolower(Constraint[1]) == 's' &&
26429 tolower(Constraint[2]) == 't' &&
26430 Constraint[3] == '(' &&
26431 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26432 Constraint[5] == ')' &&
26433 Constraint[6] == '}') {
26435 Res.first = X86::FP0+Constraint[4]-'0';
26436 Res.second = &X86::RFP80RegClass;
26440 // GCC allows "st(0)" to be called just plain "st".
26441 if (StringRef("{st}").equals_lower(Constraint)) {
26442 Res.first = X86::FP0;
26443 Res.second = &X86::RFP80RegClass;
26448 if (StringRef("{flags}").equals_lower(Constraint)) {
26449 Res.first = X86::EFLAGS;
26450 Res.second = &X86::CCRRegClass;
26454 // 'A' means EAX + EDX.
26455 if (Constraint == "A") {
26456 Res.first = X86::EAX;
26457 Res.second = &X86::GR32_ADRegClass;
26463 // Otherwise, check to see if this is a register class of the wrong value
26464 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26465 // turn into {ax},{dx}.
26466 if (Res.second->hasType(VT))
26467 return Res; // Correct type already, nothing to do.
26469 // All of the single-register GCC register classes map their values onto
26470 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26471 // really want an 8-bit or 32-bit register, map to the appropriate register
26472 // class and return the appropriate register.
26473 if (Res.second == &X86::GR16RegClass) {
26474 if (VT == MVT::i8 || VT == MVT::i1) {
26475 unsigned DestReg = 0;
26476 switch (Res.first) {
26478 case X86::AX: DestReg = X86::AL; break;
26479 case X86::DX: DestReg = X86::DL; break;
26480 case X86::CX: DestReg = X86::CL; break;
26481 case X86::BX: DestReg = X86::BL; break;
26484 Res.first = DestReg;
26485 Res.second = &X86::GR8RegClass;
26487 } else if (VT == MVT::i32 || VT == MVT::f32) {
26488 unsigned DestReg = 0;
26489 switch (Res.first) {
26491 case X86::AX: DestReg = X86::EAX; break;
26492 case X86::DX: DestReg = X86::EDX; break;
26493 case X86::CX: DestReg = X86::ECX; break;
26494 case X86::BX: DestReg = X86::EBX; break;
26495 case X86::SI: DestReg = X86::ESI; break;
26496 case X86::DI: DestReg = X86::EDI; break;
26497 case X86::BP: DestReg = X86::EBP; break;
26498 case X86::SP: DestReg = X86::ESP; break;
26501 Res.first = DestReg;
26502 Res.second = &X86::GR32RegClass;
26504 } else if (VT == MVT::i64 || VT == MVT::f64) {
26505 unsigned DestReg = 0;
26506 switch (Res.first) {
26508 case X86::AX: DestReg = X86::RAX; break;
26509 case X86::DX: DestReg = X86::RDX; break;
26510 case X86::CX: DestReg = X86::RCX; break;
26511 case X86::BX: DestReg = X86::RBX; break;
26512 case X86::SI: DestReg = X86::RSI; break;
26513 case X86::DI: DestReg = X86::RDI; break;
26514 case X86::BP: DestReg = X86::RBP; break;
26515 case X86::SP: DestReg = X86::RSP; break;
26518 Res.first = DestReg;
26519 Res.second = &X86::GR64RegClass;
26522 } else if (Res.second == &X86::FR32RegClass ||
26523 Res.second == &X86::FR64RegClass ||
26524 Res.second == &X86::VR128RegClass ||
26525 Res.second == &X86::VR256RegClass ||
26526 Res.second == &X86::FR32XRegClass ||
26527 Res.second == &X86::FR64XRegClass ||
26528 Res.second == &X86::VR128XRegClass ||
26529 Res.second == &X86::VR256XRegClass ||
26530 Res.second == &X86::VR512RegClass) {
26531 // Handle references to XMM physical registers that got mapped into the
26532 // wrong class. This can happen with constraints like {xmm0} where the
26533 // target independent register mapper will just pick the first match it can
26534 // find, ignoring the required type.
26536 if (VT == MVT::f32 || VT == MVT::i32)
26537 Res.second = &X86::FR32RegClass;
26538 else if (VT == MVT::f64 || VT == MVT::i64)
26539 Res.second = &X86::FR64RegClass;
26540 else if (X86::VR128RegClass.hasType(VT))
26541 Res.second = &X86::VR128RegClass;
26542 else if (X86::VR256RegClass.hasType(VT))
26543 Res.second = &X86::VR256RegClass;
26544 else if (X86::VR512RegClass.hasType(VT))
26545 Res.second = &X86::VR512RegClass;
26551 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26553 // Scaling factors are not free at all.
26554 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26555 // will take 2 allocations in the out of order engine instead of 1
26556 // for plain addressing mode, i.e. inst (reg1).
26558 // vaddps (%rsi,%drx), %ymm0, %ymm1
26559 // Requires two allocations (one for the load, one for the computation)
26561 // vaddps (%rsi), %ymm0, %ymm1
26562 // Requires just 1 allocation, i.e., freeing allocations for other operations
26563 // and having less micro operations to execute.
26565 // For some X86 architectures, this is even worse because for instance for
26566 // stores, the complex addressing mode forces the instruction to use the
26567 // "load" ports instead of the dedicated "store" port.
26568 // E.g., on Haswell:
26569 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26570 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26571 if (isLegalAddressingMode(AM, Ty))
26572 // Scale represents reg2 * scale, thus account for 1
26573 // as soon as we use a second register.
26574 return AM.Scale != 0;
26578 bool X86TargetLowering::isTargetFTOL() const {
26579 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();