1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
77 SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
84 bool hasBaseOrIndexReg() const {
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
104 dbgs() << "X86ISelAddressMode " << this << '\n';
105 dbgs() << "Base_Reg ";
106 if (Base_Reg.getNode() != 0)
107 Base_Reg.getNode()->dump();
110 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
111 << " Scale" << Scale << '\n'
113 if (IndexReg.getNode() != 0)
114 IndexReg.getNode()->dump();
117 dbgs() << " Disp " << Disp << '\n'
134 dbgs() << " JT" << JT << " Align" << Align << '\n';
140 //===--------------------------------------------------------------------===//
141 /// ISel - X86 specific code to select X86 machine instructions for
142 /// SelectionDAG operations.
144 class X86DAGToDAGISel : public SelectionDAGISel {
145 /// X86Lowering - This object fully describes how to lower LLVM code to an
146 /// X86-specific SelectionDAG.
147 const X86TargetLowering &X86Lowering;
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel),
160 X86Lowering(*tm.getTargetLowering()),
161 Subtarget(&tm.getSubtarget<X86Subtarget>()),
164 virtual const char *getPassName() const {
165 return "X86 DAG->DAG Instruction Selection";
168 virtual void EmitFunctionEntryCode();
170 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
172 virtual void PreprocessISelDAG();
174 inline bool immSext8(SDNode *N) const {
175 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
178 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
179 // sign extended field.
180 inline bool i64immSExt32(SDNode *N) const {
181 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
182 return (int64_t)v == (int32_t)v;
185 // Include the pieces autogenerated from the target description.
186 #include "X86GenDAGISel.inc"
189 SDNode *Select(SDNode *N);
190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
191 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
193 bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
194 bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
195 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
196 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
197 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
199 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
200 bool SelectAddr(SDValue N, SDValue &Base,
201 SDValue &Scale, SDValue &Index, SDValue &Disp,
203 bool SelectLEAAddr(SDValue N, SDValue &Base,
204 SDValue &Scale, SDValue &Index, SDValue &Disp,
206 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
207 SDValue &Scale, SDValue &Index, SDValue &Disp,
209 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
210 SDValue &Base, SDValue &Scale,
211 SDValue &Index, SDValue &Disp,
213 SDValue &NodeWithChain);
215 bool TryFoldLoad(SDNode *P, SDValue N,
216 SDValue &Base, SDValue &Scale,
217 SDValue &Index, SDValue &Disp,
220 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
221 /// inline asm expressions.
222 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
224 std::vector<SDValue> &OutOps);
226 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
228 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
229 SDValue &Scale, SDValue &Index,
230 SDValue &Disp, SDValue &Segment) {
231 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
232 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
234 Scale = getI8Imm(AM.Scale);
236 // These are 32-bit even in 64-bit mode since RIP relative offset
239 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
243 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
244 AM.Align, AM.Disp, AM.SymbolFlags);
246 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
247 else if (AM.JT != -1)
248 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
249 else if (AM.BlockAddr)
250 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
251 true, AM.SymbolFlags);
253 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
255 if (AM.Segment.getNode())
256 Segment = AM.Segment;
258 Segment = CurDAG->getRegister(0, MVT::i32);
261 /// getI8Imm - Return a target constant with the specified value, of type
263 inline SDValue getI8Imm(unsigned Imm) {
264 return CurDAG->getTargetConstant(Imm, MVT::i8);
267 /// getI32Imm - Return a target constant with the specified value, of type
269 inline SDValue getI32Imm(unsigned Imm) {
270 return CurDAG->getTargetConstant(Imm, MVT::i32);
273 /// getGlobalBaseReg - Return an SDNode that returns the value of
274 /// the global base register. Output instructions required to
275 /// initialize the global base register, if necessary.
277 SDNode *getGlobalBaseReg();
279 /// getTargetMachine - Return a reference to the TargetMachine, casted
280 /// to the target-specific type.
281 const X86TargetMachine &getTargetMachine() {
282 return static_cast<const X86TargetMachine &>(TM);
285 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
286 /// to the target-specific type.
287 const X86InstrInfo *getInstrInfo() {
288 return getTargetMachine().getInstrInfo();
295 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
296 if (OptLevel == CodeGenOpt::None) return false;
301 if (N.getOpcode() != ISD::LOAD)
304 // If N is a load, do additional profitability checks.
306 switch (U->getOpcode()) {
319 SDValue Op1 = U->getOperand(1);
321 // If the other operand is a 8-bit immediate we should fold the immediate
322 // instead. This reduces code size.
324 // movl 4(%esp), %eax
328 // addl 4(%esp), %eax
329 // The former is 2 bytes shorter. In case where the increment is 1, then
330 // the saving can be 4 bytes (by using incl %eax).
331 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
332 if (Imm->getAPIntValue().isSignedIntN(8))
335 // If the other operand is a TLS address, we should fold it instead.
338 // leal i@NTPOFF(%eax), %eax
340 // movl $i@NTPOFF, %eax
342 // if the block also has an access to a second TLS address this will save
344 // FIXME: This is probably also true for non TLS addresses.
345 if (Op1.getOpcode() == X86ISD::Wrapper) {
346 SDValue Val = Op1.getOperand(0);
347 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
357 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
358 /// load's chain operand and move load below the call's chain operand.
359 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
360 SDValue Call, SDValue OrigChain) {
361 SmallVector<SDValue, 8> Ops;
362 SDValue Chain = OrigChain.getOperand(0);
363 if (Chain.getNode() == Load.getNode())
364 Ops.push_back(Load.getOperand(0));
366 assert(Chain.getOpcode() == ISD::TokenFactor &&
367 "Unexpected chain operand");
368 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
369 if (Chain.getOperand(i).getNode() == Load.getNode())
370 Ops.push_back(Load.getOperand(0));
372 Ops.push_back(Chain.getOperand(i));
374 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
375 MVT::Other, &Ops[0], Ops.size());
377 Ops.push_back(NewChain);
379 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
380 Ops.push_back(OrigChain.getOperand(i));
381 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
382 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
383 Load.getOperand(1), Load.getOperand(2));
385 Ops.push_back(SDValue(Load.getNode(), 1));
386 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
387 Ops.push_back(Call.getOperand(i));
388 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size());
391 /// isCalleeLoad - Return true if call address is a load and it can be
392 /// moved below CALLSEQ_START and the chains leading up to the call.
393 /// Return the CALLSEQ_START by reference as a second output.
394 /// In the case of a tail call, there isn't a callseq node between the call
395 /// chain and the load.
396 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
397 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
399 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
402 LD->getAddressingMode() != ISD::UNINDEXED ||
403 LD->getExtensionType() != ISD::NON_EXTLOAD)
406 // FIXME: Calls can't fold loads through segment registers yet.
407 if (LD->getPointerInfo().getAddrSpace() > 255)
410 // Now let's find the callseq_start.
411 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
412 if (!Chain.hasOneUse())
414 Chain = Chain.getOperand(0);
417 if (!Chain.getNumOperands())
419 if (Chain.getOperand(0).getNode() == Callee.getNode())
421 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
422 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
423 Callee.getValue(1).hasOneUse())
428 void X86DAGToDAGISel::PreprocessISelDAG() {
429 // OptForSize is used in pattern predicates that isel is matching.
430 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
432 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
433 E = CurDAG->allnodes_end(); I != E; ) {
434 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
436 if (OptLevel != CodeGenOpt::None &&
437 (N->getOpcode() == X86ISD::CALL ||
438 N->getOpcode() == X86ISD::TC_RETURN)) {
439 /// Also try moving call address load from outside callseq_start to just
440 /// before the call to allow it to be folded.
458 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
459 SDValue Chain = N->getOperand(0);
460 SDValue Load = N->getOperand(1);
461 if (!isCalleeLoad(Load, Chain, HasCallSeq))
463 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
468 // Lower fpround and fpextend nodes that target the FP stack to be store and
469 // load to the stack. This is a gross hack. We would like to simply mark
470 // these as being illegal, but when we do that, legalize produces these when
471 // it expands calls, then expands these in the same legalize pass. We would
472 // like dag combine to be able to hack on these between the call expansion
473 // and the node legalization. As such this pass basically does "really
474 // late" legalization of these inline with the X86 isel pass.
475 // FIXME: This should only happen when not compiled with -O0.
476 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
479 // If the source and destination are SSE registers, then this is a legal
480 // conversion that should not be lowered.
481 EVT SrcVT = N->getOperand(0).getValueType();
482 EVT DstVT = N->getValueType(0);
483 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
484 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
485 if (SrcIsSSE && DstIsSSE)
488 if (!SrcIsSSE && !DstIsSSE) {
489 // If this is an FPStack extension, it is a noop.
490 if (N->getOpcode() == ISD::FP_EXTEND)
492 // If this is a value-preserving FPStack truncation, it is a noop.
493 if (N->getConstantOperandVal(1))
497 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
498 // FPStack has extload and truncstore. SSE can fold direct loads into other
499 // operations. Based on this, decide what we want to do.
501 if (N->getOpcode() == ISD::FP_ROUND)
502 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
504 MemVT = SrcIsSSE ? SrcVT : DstVT;
506 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
507 DebugLoc dl = N->getDebugLoc();
509 // FIXME: optimize the case where the src/dest is a load or store?
510 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
512 MemTmp, MachinePointerInfo(), MemVT,
514 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, dl, Store, MemTmp,
515 MachinePointerInfo(),
516 MemVT, false, false, 0);
518 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
519 // extload we created. This will cause general havok on the dag because
520 // anything below the conversion could be folded into other existing nodes.
521 // To avoid invalidating 'I', back it up to the convert node.
523 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
525 // Now that we did that, the node is dead. Increment the iterator to the
526 // next node to process, then delete N.
528 CurDAG->DeleteNode(N);
533 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
534 /// the main function.
535 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
536 MachineFrameInfo *MFI) {
537 const TargetInstrInfo *TII = TM.getInstrInfo();
538 if (Subtarget->isTargetCygMing())
539 BuildMI(BB, DebugLoc(),
540 TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
543 void X86DAGToDAGISel::EmitFunctionEntryCode() {
544 // If this is main, emit special code for main.
545 if (const Function *Fn = MF->getFunction())
546 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
547 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
551 bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
552 X86ISelAddressMode &AM) {
553 assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
554 SDValue Segment = N.getOperand(0);
556 if (AM.Segment.getNode() == 0) {
557 AM.Segment = Segment;
564 bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
565 // This optimization is valid because the GNU TLS model defines that
566 // gs:0 (or fs:0 on X86-64) contains its own address.
567 // For more information see http://people.redhat.com/drepper/tls.pdf
569 SDValue Address = N.getOperand(1);
570 if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
571 !MatchSegmentBaseAddress(Address, AM))
577 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
578 /// into an addressing mode. These wrap things that will resolve down into a
579 /// symbol reference. If no match is possible, this returns true, otherwise it
581 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
582 // If the addressing mode already has a symbol as the displacement, we can
583 // never match another symbol.
584 if (AM.hasSymbolicDisplacement())
587 SDValue N0 = N.getOperand(0);
588 CodeModel::Model M = TM.getCodeModel();
590 // Handle X86-64 rip-relative addresses. We check this before checking direct
591 // folding because RIP is preferable to non-RIP accesses.
592 if (Subtarget->is64Bit() &&
593 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
594 // they cannot be folded into immediate fields.
595 // FIXME: This can be improved for kernel and other models?
596 (M == CodeModel::Small || M == CodeModel::Kernel) &&
597 // Base and index reg must be 0 in order to use %rip as base and lowering
599 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
600 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
601 int64_t Offset = AM.Disp + G->getOffset();
602 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
603 AM.GV = G->getGlobal();
605 AM.SymbolFlags = G->getTargetFlags();
606 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
607 int64_t Offset = AM.Disp + CP->getOffset();
608 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
609 AM.CP = CP->getConstVal();
610 AM.Align = CP->getAlignment();
612 AM.SymbolFlags = CP->getTargetFlags();
613 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
614 AM.ES = S->getSymbol();
615 AM.SymbolFlags = S->getTargetFlags();
616 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
617 AM.JT = J->getIndex();
618 AM.SymbolFlags = J->getTargetFlags();
620 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
621 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
624 if (N.getOpcode() == X86ISD::WrapperRIP)
625 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
629 // Handle the case when globals fit in our immediate field: This is true for
630 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit
631 // mode, this results in a non-RIP-relative computation.
632 if (!Subtarget->is64Bit() ||
633 ((M == CodeModel::Small || M == CodeModel::Kernel) &&
634 TM.getRelocationModel() == Reloc::Static)) {
635 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
636 AM.GV = G->getGlobal();
637 AM.Disp += G->getOffset();
638 AM.SymbolFlags = G->getTargetFlags();
639 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
640 AM.CP = CP->getConstVal();
641 AM.Align = CP->getAlignment();
642 AM.Disp += CP->getOffset();
643 AM.SymbolFlags = CP->getTargetFlags();
644 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
645 AM.ES = S->getSymbol();
646 AM.SymbolFlags = S->getTargetFlags();
647 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
648 AM.JT = J->getIndex();
649 AM.SymbolFlags = J->getTargetFlags();
651 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
652 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
660 /// MatchAddress - Add the specified node to the specified addressing mode,
661 /// returning true if it cannot be done. This just pattern matches for the
663 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
664 if (MatchAddressRecursively(N, AM, 0))
667 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
668 // a smaller encoding and avoids a scaled-index.
670 AM.BaseType == X86ISelAddressMode::RegBase &&
671 AM.Base_Reg.getNode() == 0) {
672 AM.Base_Reg = AM.IndexReg;
676 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
677 // because it has a smaller encoding.
678 // TODO: Which other code models can use this?
679 if (TM.getCodeModel() == CodeModel::Small &&
680 Subtarget->is64Bit() &&
682 AM.BaseType == X86ISelAddressMode::RegBase &&
683 AM.Base_Reg.getNode() == 0 &&
684 AM.IndexReg.getNode() == 0 &&
685 AM.SymbolFlags == X86II::MO_NO_FLAG &&
686 AM.hasSymbolicDisplacement())
687 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
692 /// isLogicallyAddWithConstant - Return true if this node is semantically an
693 /// add of a value with a constantint.
694 static bool isLogicallyAddWithConstant(SDValue V, SelectionDAG *CurDAG) {
695 // Check for (add x, Cst)
696 if (V->getOpcode() == ISD::ADD)
697 return isa<ConstantSDNode>(V->getOperand(1));
699 // Check for (or x, Cst), where Cst & x == 0.
700 if (V->getOpcode() != ISD::OR ||
701 !isa<ConstantSDNode>(V->getOperand(1)))
704 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
705 ConstantSDNode *CN = cast<ConstantSDNode>(V->getOperand(1));
707 // Check to see if the LHS & C is zero.
708 return CurDAG->MaskedValueIsZero(V->getOperand(0), CN->getAPIntValue());
711 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
713 bool is64Bit = Subtarget->is64Bit();
714 DebugLoc dl = N.getDebugLoc();
716 dbgs() << "MatchAddress: ";
721 return MatchAddressBase(N, AM);
723 CodeModel::Model M = TM.getCodeModel();
725 // If this is already a %rip relative address, we can only merge immediates
726 // into it. Instead of handling this in every case, we handle it here.
727 // RIP relative addressing: %rip + 32-bit displacement!
728 if (AM.isRIPRelative()) {
729 // FIXME: JumpTable and ExternalSymbol address currently don't like
730 // displacements. It isn't very important, but this should be fixed for
732 if (!AM.ES && AM.JT != -1) return true;
734 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) {
735 int64_t Val = AM.Disp + Cst->getSExtValue();
736 if (X86::isOffsetSuitableForCodeModel(Val, M,
737 AM.hasSymbolicDisplacement())) {
745 switch (N.getOpcode()) {
747 case ISD::Constant: {
748 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
750 X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M,
751 AM.hasSymbolicDisplacement())) {
758 case X86ISD::SegmentBaseAddress:
759 if (!MatchSegmentBaseAddress(N, AM))
763 case X86ISD::Wrapper:
764 case X86ISD::WrapperRIP:
765 if (!MatchWrapper(N, AM))
770 if (!MatchLoad(N, AM))
774 case ISD::FrameIndex:
775 if (AM.BaseType == X86ISelAddressMode::RegBase
776 && AM.Base_Reg.getNode() == 0) {
777 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
778 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
784 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
788 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
789 unsigned Val = CN->getZExtValue();
790 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
791 // that the base operand remains free for further matching. If
792 // the base doesn't end up getting used, a post-processing step
793 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
794 if (Val == 1 || Val == 2 || Val == 3) {
796 SDValue ShVal = N.getNode()->getOperand(0);
798 // Okay, we know that we have a scale by now. However, if the scaled
799 // value is an add of something and a constant, we can fold the
800 // constant into the disp field here.
801 if (isLogicallyAddWithConstant(ShVal, CurDAG)) {
802 AM.IndexReg = ShVal.getNode()->getOperand(0);
803 ConstantSDNode *AddVal =
804 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
805 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
807 X86::isOffsetSuitableForCodeModel(Disp, M,
808 AM.hasSymbolicDisplacement()))
822 // A mul_lohi where we need the low part can be folded as a plain multiply.
823 if (N.getResNo() != 0) break;
826 case X86ISD::MUL_IMM:
827 // X*[3,5,9] -> X+X*[2,4,8]
828 if (AM.BaseType == X86ISelAddressMode::RegBase &&
829 AM.Base_Reg.getNode() == 0 &&
830 AM.IndexReg.getNode() == 0) {
832 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
833 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
834 CN->getZExtValue() == 9) {
835 AM.Scale = unsigned(CN->getZExtValue())-1;
837 SDValue MulVal = N.getNode()->getOperand(0);
840 // Okay, we know that we have a scale by now. However, if the scaled
841 // value is an add of something and a constant, we can fold the
842 // constant into the disp field here.
843 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
844 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
845 Reg = MulVal.getNode()->getOperand(0);
846 ConstantSDNode *AddVal =
847 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
848 uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
851 X86::isOffsetSuitableForCodeModel(Disp, M,
852 AM.hasSymbolicDisplacement()))
855 Reg = N.getNode()->getOperand(0);
857 Reg = N.getNode()->getOperand(0);
860 AM.IndexReg = AM.Base_Reg = Reg;
867 // Given A-B, if A can be completely folded into the address and
868 // the index field with the index field unused, use -B as the index.
869 // This is a win if a has multiple parts that can be folded into
870 // the address. Also, this saves a mov if the base register has
871 // other uses, since it avoids a two-address sub instruction, however
872 // it costs an additional mov if the index register has other uses.
874 // Add an artificial use to this node so that we can keep track of
875 // it if it gets CSE'd with a different node.
876 HandleSDNode Handle(N);
878 // Test if the LHS of the sub can be folded.
879 X86ISelAddressMode Backup = AM;
880 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
884 // Test if the index field is free for use.
885 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
891 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
892 // If the RHS involves a register with multiple uses, this
893 // transformation incurs an extra mov, due to the neg instruction
894 // clobbering its operand.
895 if (!RHS.getNode()->hasOneUse() ||
896 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
897 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
898 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
899 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
900 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
902 // If the base is a register with multiple uses, this
903 // transformation may save a mov.
904 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
905 AM.Base_Reg.getNode() &&
906 !AM.Base_Reg.getNode()->hasOneUse()) ||
907 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
909 // If the folded LHS was interesting, this transformation saves
910 // address arithmetic.
911 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
912 ((AM.Disp != 0) && (Backup.Disp == 0)) +
913 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
915 // If it doesn't look like it may be an overall win, don't do it.
921 // Ok, the transformation is legal and appears profitable. Go for it.
922 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
923 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
927 // Insert the new nodes into the topological ordering.
928 if (Zero.getNode()->getNodeId() == -1 ||
929 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
930 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
931 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
933 if (Neg.getNode()->getNodeId() == -1 ||
934 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
935 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
936 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
942 // Add an artificial use to this node so that we can keep track of
943 // it if it gets CSE'd with a different node.
944 HandleSDNode Handle(N);
945 SDValue LHS = Handle.getValue().getNode()->getOperand(0);
946 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
948 X86ISelAddressMode Backup = AM;
949 if (!MatchAddressRecursively(LHS, AM, Depth+1) &&
950 !MatchAddressRecursively(RHS, AM, Depth+1))
953 LHS = Handle.getValue().getNode()->getOperand(0);
954 RHS = Handle.getValue().getNode()->getOperand(1);
956 // Try again after commuting the operands.
957 if (!MatchAddressRecursively(RHS, AM, Depth+1) &&
958 !MatchAddressRecursively(LHS, AM, Depth+1))
961 LHS = Handle.getValue().getNode()->getOperand(0);
962 RHS = Handle.getValue().getNode()->getOperand(1);
964 // If we couldn't fold both operands into the address at the same time,
965 // see if we can just put each operand into a register and fold at least
967 if (AM.BaseType == X86ISelAddressMode::RegBase &&
968 !AM.Base_Reg.getNode() &&
969 !AM.IndexReg.getNode()) {
979 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
980 if (isLogicallyAddWithConstant(N, CurDAG)) {
981 X86ISelAddressMode Backup = AM;
982 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
983 uint64_t Offset = CN->getSExtValue();
985 // Start with the LHS as an addr mode.
986 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
987 // Address could not have picked a GV address for the displacement.
989 // On x86-64, the resultant disp must fit in 32-bits.
991 X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M,
992 AM.hasSymbolicDisplacement()))) {
1001 // Perform some heroic transforms on an and of a constant-count shift
1002 // with a constant to enable use of the scaled offset field.
1004 SDValue Shift = N.getOperand(0);
1005 if (Shift.getNumOperands() != 2) break;
1007 // Scale must not be used already.
1008 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1010 SDValue X = Shift.getOperand(0);
1011 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
1012 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
1013 if (!C1 || !C2) break;
1015 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This
1016 // allows us to convert the shift and and into an h-register extract and
1018 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) {
1019 unsigned ScaleLog = 8 - C1->getZExtValue();
1020 if (ScaleLog > 0 && ScaleLog < 4 &&
1021 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
1022 SDValue Eight = CurDAG->getConstant(8, MVT::i8);
1023 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
1024 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1026 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
1028 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
1029 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1032 // Insert the new nodes into the topological ordering.
1033 if (Eight.getNode()->getNodeId() == -1 ||
1034 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1035 CurDAG->RepositionNode(X.getNode(), Eight.getNode());
1036 Eight.getNode()->setNodeId(X.getNode()->getNodeId());
1038 if (Mask.getNode()->getNodeId() == -1 ||
1039 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1040 CurDAG->RepositionNode(X.getNode(), Mask.getNode());
1041 Mask.getNode()->setNodeId(X.getNode()->getNodeId());
1043 if (Srl.getNode()->getNodeId() == -1 ||
1044 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1045 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode());
1046 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId());
1048 if (And.getNode()->getNodeId() == -1 ||
1049 And.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1050 CurDAG->RepositionNode(N.getNode(), And.getNode());
1051 And.getNode()->setNodeId(N.getNode()->getNodeId());
1053 if (ShlCount.getNode()->getNodeId() == -1 ||
1054 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1055 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode());
1056 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId());
1058 if (Shl.getNode()->getNodeId() == -1 ||
1059 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1060 CurDAG->RepositionNode(N.getNode(), Shl.getNode());
1061 Shl.getNode()->setNodeId(N.getNode()->getNodeId());
1063 CurDAG->ReplaceAllUsesWith(N, Shl);
1065 AM.Scale = (1 << ScaleLog);
1070 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
1071 // allows us to fold the shift into this addressing mode.
1072 if (Shift.getOpcode() != ISD::SHL) break;
1074 // Not likely to be profitable if either the AND or SHIFT node has more
1075 // than one use (unless all uses are for address computation). Besides,
1076 // isel mechanism requires their node ids to be reused.
1077 if (!N.hasOneUse() || !Shift.hasOneUse())
1080 // Verify that the shift amount is something we can fold.
1081 unsigned ShiftCst = C1->getZExtValue();
1082 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
1085 // Get the new AND mask, this folds to a constant.
1086 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1087 SDValue(C2, 0), SDValue(C1, 0));
1088 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
1090 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1091 NewAND, SDValue(C1, 0));
1093 // Insert the new nodes into the topological ordering.
1094 if (C1->getNodeId() > X.getNode()->getNodeId()) {
1095 CurDAG->RepositionNode(X.getNode(), C1);
1096 C1->setNodeId(X.getNode()->getNodeId());
1098 if (NewANDMask.getNode()->getNodeId() == -1 ||
1099 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1100 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
1101 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
1103 if (NewAND.getNode()->getNodeId() == -1 ||
1104 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1105 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
1106 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
1108 if (NewSHIFT.getNode()->getNodeId() == -1 ||
1109 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1110 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
1111 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
1114 CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
1116 AM.Scale = 1 << ShiftCst;
1117 AM.IndexReg = NewAND;
1122 return MatchAddressBase(N, AM);
1125 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1126 /// specified addressing mode without any further recursion.
1127 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1128 // Is the base register already occupied?
1129 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1130 // If so, check to see if the scale index register is set.
1131 if (AM.IndexReg.getNode() == 0) {
1137 // Otherwise, we cannot select it.
1141 // Default, generate it as a register.
1142 AM.BaseType = X86ISelAddressMode::RegBase;
1147 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1148 /// It returns the operands which make up the maximal addressing mode it can
1149 /// match by reference.
1150 bool X86DAGToDAGISel::SelectAddr(SDValue N, SDValue &Base,
1151 SDValue &Scale, SDValue &Index,
1152 SDValue &Disp, SDValue &Segment) {
1153 X86ISelAddressMode AM;
1154 if (MatchAddress(N, AM))
1157 EVT VT = N.getValueType();
1158 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1159 if (!AM.Base_Reg.getNode())
1160 AM.Base_Reg = CurDAG->getRegister(0, VT);
1163 if (!AM.IndexReg.getNode())
1164 AM.IndexReg = CurDAG->getRegister(0, VT);
1166 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1170 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1171 /// match a load whose top elements are either undef or zeros. The load flavor
1172 /// is derived from the type of N, which is either v4f32 or v2f64.
1175 /// PatternChainNode: this is the matched node that has a chain input and
1177 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1178 SDValue N, SDValue &Base,
1179 SDValue &Scale, SDValue &Index,
1180 SDValue &Disp, SDValue &Segment,
1181 SDValue &PatternNodeWithChain) {
1182 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1183 PatternNodeWithChain = N.getOperand(0);
1184 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1185 PatternNodeWithChain.hasOneUse() &&
1186 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1187 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1188 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1189 if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp,Segment))
1195 // Also handle the case where we explicitly require zeros in the top
1196 // elements. This is a vector shuffle from the zero vector.
1197 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1198 // Check to see if the top elements are all zeros (or bitcast of zeros).
1199 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1200 N.getOperand(0).getNode()->hasOneUse() &&
1201 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1202 N.getOperand(0).getOperand(0).hasOneUse() &&
1203 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1204 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1205 // Okay, this is a zero extending load. Fold it.
1206 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1207 if (!SelectAddr(LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1209 PatternNodeWithChain = SDValue(LD, 0);
1216 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1217 /// mode it matches can be cost effectively emitted as an LEA instruction.
1218 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1219 SDValue &Base, SDValue &Scale,
1220 SDValue &Index, SDValue &Disp,
1222 X86ISelAddressMode AM;
1224 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1226 SDValue Copy = AM.Segment;
1227 SDValue T = CurDAG->getRegister(0, MVT::i32);
1229 if (MatchAddress(N, AM))
1231 assert (T == AM.Segment);
1234 EVT VT = N.getValueType();
1235 unsigned Complexity = 0;
1236 if (AM.BaseType == X86ISelAddressMode::RegBase)
1237 if (AM.Base_Reg.getNode())
1240 AM.Base_Reg = CurDAG->getRegister(0, VT);
1241 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1244 if (AM.IndexReg.getNode())
1247 AM.IndexReg = CurDAG->getRegister(0, VT);
1249 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1254 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1255 // to a LEA. This is determined with some expermentation but is by no means
1256 // optimal (especially for code size consideration). LEA is nice because of
1257 // its three-address nature. Tweak the cost function again when we can run
1258 // convertToThreeAddress() at register allocation time.
1259 if (AM.hasSymbolicDisplacement()) {
1260 // For X86-64, we should always use lea to materialize RIP relative
1262 if (Subtarget->is64Bit())
1268 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1271 // If it isn't worth using an LEA, reject it.
1272 if (Complexity <= 2)
1275 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1279 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1280 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1281 SDValue &Scale, SDValue &Index,
1282 SDValue &Disp, SDValue &Segment) {
1283 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1284 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1286 X86ISelAddressMode AM;
1287 AM.GV = GA->getGlobal();
1288 AM.Disp += GA->getOffset();
1289 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1290 AM.SymbolFlags = GA->getTargetFlags();
1292 if (N.getValueType() == MVT::i32) {
1294 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1296 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1299 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1304 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1305 SDValue &Base, SDValue &Scale,
1306 SDValue &Index, SDValue &Disp,
1308 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1309 !IsProfitableToFold(N, P, P) ||
1310 !IsLegalToFold(N, P, P, OptLevel))
1313 return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp, Segment);
1316 /// getGlobalBaseReg - Return an SDNode that returns the value of
1317 /// the global base register. Output instructions required to
1318 /// initialize the global base register, if necessary.
1320 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1321 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1322 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1325 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1326 SDValue Chain = Node->getOperand(0);
1327 SDValue In1 = Node->getOperand(1);
1328 SDValue In2L = Node->getOperand(2);
1329 SDValue In2H = Node->getOperand(3);
1330 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1331 if (!SelectAddr(In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1333 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1334 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1335 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1336 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1337 MVT::i32, MVT::i32, MVT::Other, Ops,
1338 array_lengthof(Ops));
1339 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1343 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1344 if (Node->hasAnyUseOfValue(0))
1347 // Optimize common patterns for __sync_add_and_fetch and
1348 // __sync_sub_and_fetch where the result is not used. This allows us
1349 // to use "lock" version of add, sub, inc, dec instructions.
1350 // FIXME: Do not use special instructions but instead add the "lock"
1351 // prefix to the target node somehow. The extra information will then be
1352 // transferred to machine instruction and it denotes the prefix.
1353 SDValue Chain = Node->getOperand(0);
1354 SDValue Ptr = Node->getOperand(1);
1355 SDValue Val = Node->getOperand(2);
1356 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1357 if (!SelectAddr(Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1360 bool isInc = false, isDec = false, isSub = false, isCN = false;
1361 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1364 int64_t CNVal = CN->getSExtValue();
1367 else if (CNVal == -1)
1369 else if (CNVal >= 0)
1370 Val = CurDAG->getTargetConstant(CNVal, NVT);
1373 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1375 } else if (Val.hasOneUse() &&
1376 Val.getOpcode() == ISD::SUB &&
1377 X86::isZeroNode(Val.getOperand(0))) {
1379 Val = Val.getOperand(1);
1383 switch (NVT.getSimpleVT().SimpleTy) {
1387 Opc = X86::LOCK_INC8m;
1389 Opc = X86::LOCK_DEC8m;
1392 Opc = X86::LOCK_SUB8mi;
1394 Opc = X86::LOCK_SUB8mr;
1397 Opc = X86::LOCK_ADD8mi;
1399 Opc = X86::LOCK_ADD8mr;
1404 Opc = X86::LOCK_INC16m;
1406 Opc = X86::LOCK_DEC16m;
1409 if (immSext8(Val.getNode()))
1410 Opc = X86::LOCK_SUB16mi8;
1412 Opc = X86::LOCK_SUB16mi;
1414 Opc = X86::LOCK_SUB16mr;
1417 if (immSext8(Val.getNode()))
1418 Opc = X86::LOCK_ADD16mi8;
1420 Opc = X86::LOCK_ADD16mi;
1422 Opc = X86::LOCK_ADD16mr;
1427 Opc = X86::LOCK_INC32m;
1429 Opc = X86::LOCK_DEC32m;
1432 if (immSext8(Val.getNode()))
1433 Opc = X86::LOCK_SUB32mi8;
1435 Opc = X86::LOCK_SUB32mi;
1437 Opc = X86::LOCK_SUB32mr;
1440 if (immSext8(Val.getNode()))
1441 Opc = X86::LOCK_ADD32mi8;
1443 Opc = X86::LOCK_ADD32mi;
1445 Opc = X86::LOCK_ADD32mr;
1450 Opc = X86::LOCK_INC64m;
1452 Opc = X86::LOCK_DEC64m;
1454 Opc = X86::LOCK_SUB64mr;
1456 if (immSext8(Val.getNode()))
1457 Opc = X86::LOCK_SUB64mi8;
1458 else if (i64immSExt32(Val.getNode()))
1459 Opc = X86::LOCK_SUB64mi32;
1462 Opc = X86::LOCK_ADD64mr;
1464 if (immSext8(Val.getNode()))
1465 Opc = X86::LOCK_ADD64mi8;
1466 else if (i64immSExt32(Val.getNode()))
1467 Opc = X86::LOCK_ADD64mi32;
1473 DebugLoc dl = Node->getDebugLoc();
1474 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1476 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1477 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1478 if (isInc || isDec) {
1479 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1480 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
1481 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1482 SDValue RetVals[] = { Undef, Ret };
1483 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1485 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1486 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1487 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1488 SDValue RetVals[] = { Undef, Ret };
1489 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1493 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1494 /// any uses which require the SF or OF bits to be accurate.
1495 static bool HasNoSignedComparisonUses(SDNode *N) {
1496 // Examine each user of the node.
1497 for (SDNode::use_iterator UI = N->use_begin(),
1498 UE = N->use_end(); UI != UE; ++UI) {
1499 // Only examine CopyToReg uses.
1500 if (UI->getOpcode() != ISD::CopyToReg)
1502 // Only examine CopyToReg uses that copy to EFLAGS.
1503 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1506 // Examine each user of the CopyToReg use.
1507 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1508 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1509 // Only examine the Flag result.
1510 if (FlagUI.getUse().getResNo() != 1) continue;
1511 // Anything unusual: assume conservatively.
1512 if (!FlagUI->isMachineOpcode()) return false;
1513 // Examine the opcode of the user.
1514 switch (FlagUI->getMachineOpcode()) {
1515 // These comparisons don't treat the most significant bit specially.
1516 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1517 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1518 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1519 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1520 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1521 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1522 case X86::CMOVA16rr: case X86::CMOVA16rm:
1523 case X86::CMOVA32rr: case X86::CMOVA32rm:
1524 case X86::CMOVA64rr: case X86::CMOVA64rm:
1525 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1526 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1527 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1528 case X86::CMOVB16rr: case X86::CMOVB16rm:
1529 case X86::CMOVB32rr: case X86::CMOVB32rm:
1530 case X86::CMOVB64rr: case X86::CMOVB64rm:
1531 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1532 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1533 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1534 case X86::CMOVE16rr: case X86::CMOVE16rm:
1535 case X86::CMOVE32rr: case X86::CMOVE32rm:
1536 case X86::CMOVE64rr: case X86::CMOVE64rm:
1537 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1538 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1539 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1540 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1541 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1542 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1543 case X86::CMOVP16rr: case X86::CMOVP16rm:
1544 case X86::CMOVP32rr: case X86::CMOVP32rm:
1545 case X86::CMOVP64rr: case X86::CMOVP64rm:
1547 // Anything else: assume conservatively.
1548 default: return false;
1555 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
1556 EVT NVT = Node->getValueType(0);
1558 unsigned Opcode = Node->getOpcode();
1559 DebugLoc dl = Node->getDebugLoc();
1561 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
1563 if (Node->isMachineOpcode()) {
1564 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
1565 return NULL; // Already selected.
1570 case X86ISD::GlobalBaseReg:
1571 return getGlobalBaseReg();
1573 case X86ISD::ATOMOR64_DAG:
1574 return SelectAtomic64(Node, X86::ATOMOR6432);
1575 case X86ISD::ATOMXOR64_DAG:
1576 return SelectAtomic64(Node, X86::ATOMXOR6432);
1577 case X86ISD::ATOMADD64_DAG:
1578 return SelectAtomic64(Node, X86::ATOMADD6432);
1579 case X86ISD::ATOMSUB64_DAG:
1580 return SelectAtomic64(Node, X86::ATOMSUB6432);
1581 case X86ISD::ATOMNAND64_DAG:
1582 return SelectAtomic64(Node, X86::ATOMNAND6432);
1583 case X86ISD::ATOMAND64_DAG:
1584 return SelectAtomic64(Node, X86::ATOMAND6432);
1585 case X86ISD::ATOMSWAP64_DAG:
1586 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1588 case ISD::ATOMIC_LOAD_ADD: {
1589 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
1595 case ISD::SMUL_LOHI:
1596 case ISD::UMUL_LOHI: {
1597 SDValue N0 = Node->getOperand(0);
1598 SDValue N1 = Node->getOperand(1);
1600 bool isSigned = Opcode == ISD::SMUL_LOHI;
1602 switch (NVT.getSimpleVT().SimpleTy) {
1603 default: llvm_unreachable("Unsupported VT!");
1604 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1605 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1606 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1607 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1610 switch (NVT.getSimpleVT().SimpleTy) {
1611 default: llvm_unreachable("Unsupported VT!");
1612 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1613 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1614 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1615 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1619 unsigned LoReg, HiReg;
1620 switch (NVT.getSimpleVT().SimpleTy) {
1621 default: llvm_unreachable("Unsupported VT!");
1622 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1623 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1624 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1625 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1628 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1629 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1630 // Multiply is commmutative.
1632 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1637 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1638 N0, SDValue()).getValue(1);
1641 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1644 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1645 array_lengthof(Ops));
1646 InFlag = SDValue(CNode, 1);
1647 // Update the chain.
1648 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1651 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1654 // Prevent use of AH in a REX instruction by referencing AX instead.
1655 if (HiReg == X86::AH && Subtarget->is64Bit() &&
1656 !SDValue(Node, 1).use_empty()) {
1657 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1658 X86::AX, MVT::i16, InFlag);
1659 InFlag = Result.getValue(2);
1660 // Get the low part if needed. Don't use getCopyFromReg for aliasing
1662 if (!SDValue(Node, 0).use_empty())
1663 ReplaceUses(SDValue(Node, 1),
1664 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1666 // Shift AX down 8 bits.
1667 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
1669 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1670 // Then truncate it down to i8.
1671 ReplaceUses(SDValue(Node, 1),
1672 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1674 // Copy the low half of the result, if it is needed.
1675 if (!SDValue(Node, 0).use_empty()) {
1676 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1677 LoReg, NVT, InFlag);
1678 InFlag = Result.getValue(2);
1679 ReplaceUses(SDValue(Node, 0), Result);
1680 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1682 // Copy the high half of the result, if it is needed.
1683 if (!SDValue(Node, 1).use_empty()) {
1684 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1685 HiReg, NVT, InFlag);
1686 InFlag = Result.getValue(2);
1687 ReplaceUses(SDValue(Node, 1), Result);
1688 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1695 case ISD::UDIVREM: {
1696 SDValue N0 = Node->getOperand(0);
1697 SDValue N1 = Node->getOperand(1);
1699 bool isSigned = Opcode == ISD::SDIVREM;
1701 switch (NVT.getSimpleVT().SimpleTy) {
1702 default: llvm_unreachable("Unsupported VT!");
1703 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1704 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1705 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1706 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1709 switch (NVT.getSimpleVT().SimpleTy) {
1710 default: llvm_unreachable("Unsupported VT!");
1711 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1712 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1713 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1714 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1718 unsigned LoReg, HiReg, ClrReg;
1719 unsigned ClrOpcode, SExtOpcode;
1720 switch (NVT.getSimpleVT().SimpleTy) {
1721 default: llvm_unreachable("Unsupported VT!");
1723 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
1725 SExtOpcode = X86::CBW;
1728 LoReg = X86::AX; HiReg = X86::DX;
1729 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
1730 SExtOpcode = X86::CWD;
1733 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
1734 ClrOpcode = X86::MOV32r0;
1735 SExtOpcode = X86::CDQ;
1738 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
1739 ClrOpcode = X86::MOV64r0;
1740 SExtOpcode = X86::CQO;
1744 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1745 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1746 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
1749 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
1750 // Special case for div8, just use a move with zero extension to AX to
1751 // clear the upper 8 bits (AH).
1752 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
1753 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
1754 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
1756 SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16,
1758 array_lengthof(Ops)), 0);
1759 Chain = Move.getValue(1);
1760 ReplaceUses(N0.getValue(1), Chain);
1763 SDValue(CurDAG->getMachineNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
1764 Chain = CurDAG->getEntryNode();
1766 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
1767 InFlag = Chain.getValue(1);
1770 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
1771 LoReg, N0, SDValue()).getValue(1);
1772 if (isSigned && !signBitIsZero) {
1773 // Sign extend the low part into the high part.
1775 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
1777 // Zero out the high part, effectively zero extending the input.
1779 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
1780 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
1781 ClrNode, InFlag).getValue(1);
1786 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1789 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1790 array_lengthof(Ops));
1791 InFlag = SDValue(CNode, 1);
1792 // Update the chain.
1793 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1796 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1799 // Prevent use of AH in a REX instruction by referencing AX instead.
1800 // Shift it down 8 bits.
1801 if (HiReg == X86::AH && Subtarget->is64Bit() &&
1802 !SDValue(Node, 1).use_empty()) {
1803 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1804 X86::AX, MVT::i16, InFlag);
1805 InFlag = Result.getValue(2);
1807 // If we also need AL (the quotient), get it by extracting a subreg from
1808 // Result. The fast register allocator does not like multiple CopyFromReg
1809 // nodes using aliasing registers.
1810 if (!SDValue(Node, 0).use_empty())
1811 ReplaceUses(SDValue(Node, 0),
1812 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1814 // Shift AX right by 8 bits instead of using AH.
1815 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
1817 CurDAG->getTargetConstant(8, MVT::i8)),
1819 ReplaceUses(SDValue(Node, 1),
1820 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1822 // Copy the division (low) result, if it is needed.
1823 if (!SDValue(Node, 0).use_empty()) {
1824 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1825 LoReg, NVT, InFlag);
1826 InFlag = Result.getValue(2);
1827 ReplaceUses(SDValue(Node, 0), Result);
1828 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1830 // Copy the remainder (high) result, if it is needed.
1831 if (!SDValue(Node, 1).use_empty()) {
1832 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1833 HiReg, NVT, InFlag);
1834 InFlag = Result.getValue(2);
1835 ReplaceUses(SDValue(Node, 1), Result);
1836 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1842 SDValue N0 = Node->getOperand(0);
1843 SDValue N1 = Node->getOperand(1);
1845 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
1846 // use a smaller encoding.
1847 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
1848 HasNoSignedComparisonUses(Node))
1849 // Look past the truncate if CMP is the only use of it.
1850 N0 = N0.getOperand(0);
1851 if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
1852 N0.getValueType() != MVT::i8 &&
1853 X86::isZeroNode(N1)) {
1854 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
1857 // For example, convert "testl %eax, $8" to "testb %al, $8"
1858 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
1859 (!(C->getZExtValue() & 0x80) ||
1860 HasNoSignedComparisonUses(Node))) {
1861 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
1862 SDValue Reg = N0.getNode()->getOperand(0);
1864 // On x86-32, only the ABCD registers have 8-bit subregisters.
1865 if (!Subtarget->is64Bit()) {
1866 TargetRegisterClass *TRC = 0;
1867 switch (N0.getValueType().getSimpleVT().SimpleTy) {
1868 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
1869 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
1870 default: llvm_unreachable("Unsupported TEST operand type!");
1872 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
1873 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
1874 Reg.getValueType(), Reg, RC), 0);
1877 // Extract the l-register.
1878 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
1882 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
1885 // For example, "testl %eax, $2048" to "testb %ah, $8".
1886 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
1887 (!(C->getZExtValue() & 0x8000) ||
1888 HasNoSignedComparisonUses(Node))) {
1889 // Shift the immediate right by 8 bits.
1890 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
1892 SDValue Reg = N0.getNode()->getOperand(0);
1894 // Put the value in an ABCD register.
1895 TargetRegisterClass *TRC = 0;
1896 switch (N0.getValueType().getSimpleVT().SimpleTy) {
1897 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
1898 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
1899 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
1900 default: llvm_unreachable("Unsupported TEST operand type!");
1902 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
1903 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
1904 Reg.getValueType(), Reg, RC), 0);
1906 // Extract the h-register.
1907 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
1910 // Emit a testb. No special NOREX tricks are needed since there's
1911 // only one GPR operand!
1912 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
1913 Subreg, ShiftedImm);
1916 // For example, "testl %eax, $32776" to "testw %ax, $32776".
1917 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
1918 N0.getValueType() != MVT::i16 &&
1919 (!(C->getZExtValue() & 0x8000) ||
1920 HasNoSignedComparisonUses(Node))) {
1921 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
1922 SDValue Reg = N0.getNode()->getOperand(0);
1924 // Extract the 16-bit subregister.
1925 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
1929 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
1932 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
1933 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
1934 N0.getValueType() == MVT::i64 &&
1935 (!(C->getZExtValue() & 0x80000000) ||
1936 HasNoSignedComparisonUses(Node))) {
1937 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
1938 SDValue Reg = N0.getNode()->getOperand(0);
1940 // Extract the 32-bit subregister.
1941 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
1945 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
1952 SDNode *ResNode = SelectCode(Node);
1954 DEBUG(dbgs() << "=> ";
1955 if (ResNode == NULL || ResNode == Node)
1958 ResNode->dump(CurDAG);
1964 bool X86DAGToDAGISel::
1965 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1966 std::vector<SDValue> &OutOps) {
1967 SDValue Op0, Op1, Op2, Op3, Op4;
1968 switch (ConstraintCode) {
1969 case 'o': // offsetable ??
1970 case 'v': // not offsetable ??
1971 default: return true;
1973 if (!SelectAddr(Op, Op0, Op1, Op2, Op3, Op4))
1978 OutOps.push_back(Op0);
1979 OutOps.push_back(Op1);
1980 OutOps.push_back(Op2);
1981 OutOps.push_back(Op3);
1982 OutOps.push_back(Op4);
1986 /// createX86ISelDag - This pass converts a legalized DAG into a
1987 /// X86-specific DAG, ready for instruction scheduling.
1989 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
1990 llvm::CodeGenOpt::Level OptLevel) {
1991 return new X86DAGToDAGISel(TM, OptLevel);