1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
77 SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
84 bool hasBaseOrIndexReg() const {
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
104 dbgs() << "X86ISelAddressMode " << this << '\n';
105 dbgs() << "Base_Reg ";
106 if (Base_Reg.getNode() != 0)
107 Base_Reg.getNode()->dump();
110 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
111 << " Scale" << Scale << '\n'
113 if (IndexReg.getNode() != 0)
114 IndexReg.getNode()->dump();
117 dbgs() << " Disp " << Disp << '\n'
134 dbgs() << " JT" << JT << " Align" << Align << '\n';
140 //===--------------------------------------------------------------------===//
141 /// ISel - X86 specific code to select X86 machine instructions for
142 /// SelectionDAG operations.
144 class X86DAGToDAGISel : public SelectionDAGISel {
145 /// X86Lowering - This object fully describes how to lower LLVM code to an
146 /// X86-specific SelectionDAG.
147 const X86TargetLowering &X86Lowering;
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel),
160 X86Lowering(*tm.getTargetLowering()),
161 Subtarget(&tm.getSubtarget<X86Subtarget>()),
164 virtual const char *getPassName() const {
165 return "X86 DAG->DAG Instruction Selection";
168 virtual void EmitFunctionEntryCode();
170 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
172 virtual void PreprocessISelDAG();
174 // Include the pieces autogenerated from the target description.
175 #include "X86GenDAGISel.inc"
178 SDNode *Select(SDNode *N);
179 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
180 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
182 bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
183 bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
184 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
185 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
186 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
188 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
189 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
190 SDValue &Scale, SDValue &Index, SDValue &Disp,
192 bool SelectLEAAddr(SDNode *Op, SDValue N, SDValue &Base,
193 SDValue &Scale, SDValue &Index, SDValue &Disp);
194 bool SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base,
195 SDValue &Scale, SDValue &Index, SDValue &Disp);
196 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
197 SDValue &Base, SDValue &Scale,
198 SDValue &Index, SDValue &Disp,
200 SDValue &NodeWithChain);
202 bool TryFoldLoad(SDNode *P, SDValue N,
203 SDValue &Base, SDValue &Scale,
204 SDValue &Index, SDValue &Disp,
207 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
208 /// inline asm expressions.
209 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
211 std::vector<SDValue> &OutOps);
213 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
215 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
216 SDValue &Scale, SDValue &Index,
217 SDValue &Disp, SDValue &Segment) {
218 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
219 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
221 Scale = getI8Imm(AM.Scale);
223 // These are 32-bit even in 64-bit mode since RIP relative offset
226 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
230 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
231 AM.Align, AM.Disp, AM.SymbolFlags);
233 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
234 else if (AM.JT != -1)
235 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
236 else if (AM.BlockAddr)
237 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
238 true, AM.SymbolFlags);
240 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
242 if (AM.Segment.getNode())
243 Segment = AM.Segment;
245 Segment = CurDAG->getRegister(0, MVT::i32);
248 /// getI8Imm - Return a target constant with the specified value, of type
250 inline SDValue getI8Imm(unsigned Imm) {
251 return CurDAG->getTargetConstant(Imm, MVT::i8);
254 /// getI16Imm - Return a target constant with the specified value, of type
256 inline SDValue getI16Imm(unsigned Imm) {
257 return CurDAG->getTargetConstant(Imm, MVT::i16);
260 /// getI32Imm - Return a target constant with the specified value, of type
262 inline SDValue getI32Imm(unsigned Imm) {
263 return CurDAG->getTargetConstant(Imm, MVT::i32);
266 /// getGlobalBaseReg - Return an SDNode that returns the value of
267 /// the global base register. Output instructions required to
268 /// initialize the global base register, if necessary.
270 SDNode *getGlobalBaseReg();
272 /// getTargetMachine - Return a reference to the TargetMachine, casted
273 /// to the target-specific type.
274 const X86TargetMachine &getTargetMachine() {
275 return static_cast<const X86TargetMachine &>(TM);
278 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
279 /// to the target-specific type.
280 const X86InstrInfo *getInstrInfo() {
281 return getTargetMachine().getInstrInfo();
288 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
289 if (OptLevel == CodeGenOpt::None) return false;
294 if (N.getOpcode() != ISD::LOAD)
297 // If N is a load, do additional profitability checks.
299 switch (U->getOpcode()) {
312 SDValue Op1 = U->getOperand(1);
314 // If the other operand is a 8-bit immediate we should fold the immediate
315 // instead. This reduces code size.
317 // movl 4(%esp), %eax
321 // addl 4(%esp), %eax
322 // The former is 2 bytes shorter. In case where the increment is 1, then
323 // the saving can be 4 bytes (by using incl %eax).
324 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
325 if (Imm->getAPIntValue().isSignedIntN(8))
328 // If the other operand is a TLS address, we should fold it instead.
331 // leal i@NTPOFF(%eax), %eax
333 // movl $i@NTPOFF, %eax
335 // if the block also has an access to a second TLS address this will save
337 // FIXME: This is probably also true for non TLS addresses.
338 if (Op1.getOpcode() == X86ISD::Wrapper) {
339 SDValue Val = Op1.getOperand(0);
340 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
350 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
351 /// load's chain operand and move load below the call's chain operand.
352 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
353 SDValue Call, SDValue OrigChain) {
354 SmallVector<SDValue, 8> Ops;
355 SDValue Chain = OrigChain.getOperand(0);
356 if (Chain.getNode() == Load.getNode())
357 Ops.push_back(Load.getOperand(0));
359 assert(Chain.getOpcode() == ISD::TokenFactor &&
360 "Unexpected chain operand");
361 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
362 if (Chain.getOperand(i).getNode() == Load.getNode())
363 Ops.push_back(Load.getOperand(0));
365 Ops.push_back(Chain.getOperand(i));
367 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
368 MVT::Other, &Ops[0], Ops.size());
370 Ops.push_back(NewChain);
372 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
373 Ops.push_back(OrigChain.getOperand(i));
374 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
375 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
376 Load.getOperand(1), Load.getOperand(2));
378 Ops.push_back(SDValue(Load.getNode(), 1));
379 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
380 Ops.push_back(Call.getOperand(i));
381 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size());
384 /// isCalleeLoad - Return true if call address is a load and it can be
385 /// moved below CALLSEQ_START and the chains leading up to the call.
386 /// Return the CALLSEQ_START by reference as a second output.
387 /// In the case of a tail call, there isn't a callseq node between the call
388 /// chain and the load.
389 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
390 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
392 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
395 LD->getAddressingMode() != ISD::UNINDEXED ||
396 LD->getExtensionType() != ISD::NON_EXTLOAD)
399 // Now let's find the callseq_start.
400 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
401 if (!Chain.hasOneUse())
403 Chain = Chain.getOperand(0);
406 if (!Chain.getNumOperands())
408 if (Chain.getOperand(0).getNode() == Callee.getNode())
410 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
411 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
412 Callee.getValue(1).hasOneUse())
417 void X86DAGToDAGISel::PreprocessISelDAG() {
418 // OptForSize is used in pattern predicates that isel is matching.
419 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
421 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
422 E = CurDAG->allnodes_end(); I != E; ) {
423 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
425 if (OptLevel != CodeGenOpt::None &&
426 (N->getOpcode() == X86ISD::CALL ||
427 N->getOpcode() == X86ISD::TC_RETURN)) {
428 /// Also try moving call address load from outside callseq_start to just
429 /// before the call to allow it to be folded.
447 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
448 SDValue Chain = N->getOperand(0);
449 SDValue Load = N->getOperand(1);
450 if (!isCalleeLoad(Load, Chain, HasCallSeq))
452 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
457 // Lower fpround and fpextend nodes that target the FP stack to be store and
458 // load to the stack. This is a gross hack. We would like to simply mark
459 // these as being illegal, but when we do that, legalize produces these when
460 // it expands calls, then expands these in the same legalize pass. We would
461 // like dag combine to be able to hack on these between the call expansion
462 // and the node legalization. As such this pass basically does "really
463 // late" legalization of these inline with the X86 isel pass.
464 // FIXME: This should only happen when not compiled with -O0.
465 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
468 // If the source and destination are SSE registers, then this is a legal
469 // conversion that should not be lowered.
470 EVT SrcVT = N->getOperand(0).getValueType();
471 EVT DstVT = N->getValueType(0);
472 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
473 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
474 if (SrcIsSSE && DstIsSSE)
477 if (!SrcIsSSE && !DstIsSSE) {
478 // If this is an FPStack extension, it is a noop.
479 if (N->getOpcode() == ISD::FP_EXTEND)
481 // If this is a value-preserving FPStack truncation, it is a noop.
482 if (N->getConstantOperandVal(1))
486 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
487 // FPStack has extload and truncstore. SSE can fold direct loads into other
488 // operations. Based on this, decide what we want to do.
490 if (N->getOpcode() == ISD::FP_ROUND)
491 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
493 MemVT = SrcIsSSE ? SrcVT : DstVT;
495 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
496 DebugLoc dl = N->getDebugLoc();
498 // FIXME: optimize the case where the src/dest is a load or store?
499 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
501 MemTmp, NULL, 0, MemVT,
503 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
504 NULL, 0, MemVT, false, false, 0);
506 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
507 // extload we created. This will cause general havok on the dag because
508 // anything below the conversion could be folded into other existing nodes.
509 // To avoid invalidating 'I', back it up to the convert node.
511 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
513 // Now that we did that, the node is dead. Increment the iterator to the
514 // next node to process, then delete N.
516 CurDAG->DeleteNode(N);
521 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
522 /// the main function.
523 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
524 MachineFrameInfo *MFI) {
525 const TargetInstrInfo *TII = TM.getInstrInfo();
526 if (Subtarget->isTargetCygMing())
527 BuildMI(BB, DebugLoc(),
528 TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
531 void X86DAGToDAGISel::EmitFunctionEntryCode() {
532 // If this is main, emit special code for main.
533 if (const Function *Fn = MF->getFunction())
534 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
535 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
539 bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
540 X86ISelAddressMode &AM) {
541 assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
542 SDValue Segment = N.getOperand(0);
544 if (AM.Segment.getNode() == 0) {
545 AM.Segment = Segment;
552 bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
553 // This optimization is valid because the GNU TLS model defines that
554 // gs:0 (or fs:0 on X86-64) contains its own address.
555 // For more information see http://people.redhat.com/drepper/tls.pdf
557 SDValue Address = N.getOperand(1);
558 if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
559 !MatchSegmentBaseAddress (Address, AM))
565 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
566 /// into an addressing mode. These wrap things that will resolve down into a
567 /// symbol reference. If no match is possible, this returns true, otherwise it
569 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
570 // If the addressing mode already has a symbol as the displacement, we can
571 // never match another symbol.
572 if (AM.hasSymbolicDisplacement())
575 SDValue N0 = N.getOperand(0);
576 CodeModel::Model M = TM.getCodeModel();
578 // Handle X86-64 rip-relative addresses. We check this before checking direct
579 // folding because RIP is preferable to non-RIP accesses.
580 if (Subtarget->is64Bit() &&
581 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
582 // they cannot be folded into immediate fields.
583 // FIXME: This can be improved for kernel and other models?
584 (M == CodeModel::Small || M == CodeModel::Kernel) &&
585 // Base and index reg must be 0 in order to use %rip as base and lowering
587 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
588 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
589 int64_t Offset = AM.Disp + G->getOffset();
590 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
591 AM.GV = G->getGlobal();
593 AM.SymbolFlags = G->getTargetFlags();
594 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
595 int64_t Offset = AM.Disp + CP->getOffset();
596 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
597 AM.CP = CP->getConstVal();
598 AM.Align = CP->getAlignment();
600 AM.SymbolFlags = CP->getTargetFlags();
601 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
602 AM.ES = S->getSymbol();
603 AM.SymbolFlags = S->getTargetFlags();
604 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
605 AM.JT = J->getIndex();
606 AM.SymbolFlags = J->getTargetFlags();
608 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
609 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
612 if (N.getOpcode() == X86ISD::WrapperRIP)
613 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
617 // Handle the case when globals fit in our immediate field: This is true for
618 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit
619 // mode, this results in a non-RIP-relative computation.
620 if (!Subtarget->is64Bit() ||
621 ((M == CodeModel::Small || M == CodeModel::Kernel) &&
622 TM.getRelocationModel() == Reloc::Static)) {
623 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
624 AM.GV = G->getGlobal();
625 AM.Disp += G->getOffset();
626 AM.SymbolFlags = G->getTargetFlags();
627 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
628 AM.CP = CP->getConstVal();
629 AM.Align = CP->getAlignment();
630 AM.Disp += CP->getOffset();
631 AM.SymbolFlags = CP->getTargetFlags();
632 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
633 AM.ES = S->getSymbol();
634 AM.SymbolFlags = S->getTargetFlags();
635 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
636 AM.JT = J->getIndex();
637 AM.SymbolFlags = J->getTargetFlags();
639 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
640 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
648 /// MatchAddress - Add the specified node to the specified addressing mode,
649 /// returning true if it cannot be done. This just pattern matches for the
651 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
652 if (MatchAddressRecursively(N, AM, 0))
655 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
656 // a smaller encoding and avoids a scaled-index.
658 AM.BaseType == X86ISelAddressMode::RegBase &&
659 AM.Base_Reg.getNode() == 0) {
660 AM.Base_Reg = AM.IndexReg;
664 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
665 // because it has a smaller encoding.
666 // TODO: Which other code models can use this?
667 if (TM.getCodeModel() == CodeModel::Small &&
668 Subtarget->is64Bit() &&
670 AM.BaseType == X86ISelAddressMode::RegBase &&
671 AM.Base_Reg.getNode() == 0 &&
672 AM.IndexReg.getNode() == 0 &&
673 AM.SymbolFlags == X86II::MO_NO_FLAG &&
674 AM.hasSymbolicDisplacement())
675 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
680 /// isLogicallyAddWithConstant - Return true if this node is semantically an
681 /// add of a value with a constantint.
682 static bool isLogicallyAddWithConstant(SDValue V, SelectionDAG *CurDAG) {
683 // Check for (add x, Cst)
684 if (V->getOpcode() == ISD::ADD)
685 return isa<ConstantSDNode>(V->getOperand(1));
687 // Check for (or x, Cst), where Cst & x == 0.
688 if (V->getOpcode() != ISD::OR ||
689 !isa<ConstantSDNode>(V->getOperand(1)))
692 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
693 ConstantSDNode *CN = cast<ConstantSDNode>(V->getOperand(1));
695 // Check to see if the LHS & C is zero.
696 return CurDAG->MaskedValueIsZero(V->getOperand(0), CN->getAPIntValue());
699 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
701 bool is64Bit = Subtarget->is64Bit();
702 DebugLoc dl = N.getDebugLoc();
704 dbgs() << "MatchAddress: ";
709 return MatchAddressBase(N, AM);
711 CodeModel::Model M = TM.getCodeModel();
713 // If this is already a %rip relative address, we can only merge immediates
714 // into it. Instead of handling this in every case, we handle it here.
715 // RIP relative addressing: %rip + 32-bit displacement!
716 if (AM.isRIPRelative()) {
717 // FIXME: JumpTable and ExternalSymbol address currently don't like
718 // displacements. It isn't very important, but this should be fixed for
720 if (!AM.ES && AM.JT != -1) return true;
722 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) {
723 int64_t Val = AM.Disp + Cst->getSExtValue();
724 if (X86::isOffsetSuitableForCodeModel(Val, M,
725 AM.hasSymbolicDisplacement())) {
733 switch (N.getOpcode()) {
735 case ISD::Constant: {
736 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
738 X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M,
739 AM.hasSymbolicDisplacement())) {
746 case X86ISD::SegmentBaseAddress:
747 if (!MatchSegmentBaseAddress(N, AM))
751 case X86ISD::Wrapper:
752 case X86ISD::WrapperRIP:
753 if (!MatchWrapper(N, AM))
758 if (!MatchLoad(N, AM))
762 case ISD::FrameIndex:
763 if (AM.BaseType == X86ISelAddressMode::RegBase
764 && AM.Base_Reg.getNode() == 0) {
765 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
766 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
772 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
776 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
777 unsigned Val = CN->getZExtValue();
778 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
779 // that the base operand remains free for further matching. If
780 // the base doesn't end up getting used, a post-processing step
781 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
782 if (Val == 1 || Val == 2 || Val == 3) {
784 SDValue ShVal = N.getNode()->getOperand(0);
786 // Okay, we know that we have a scale by now. However, if the scaled
787 // value is an add of something and a constant, we can fold the
788 // constant into the disp field here.
789 if (isLogicallyAddWithConstant(ShVal, CurDAG)) {
790 AM.IndexReg = ShVal.getNode()->getOperand(0);
791 ConstantSDNode *AddVal =
792 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
793 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
795 X86::isOffsetSuitableForCodeModel(Disp, M,
796 AM.hasSymbolicDisplacement()))
810 // A mul_lohi where we need the low part can be folded as a plain multiply.
811 if (N.getResNo() != 0) break;
814 case X86ISD::MUL_IMM:
815 // X*[3,5,9] -> X+X*[2,4,8]
816 if (AM.BaseType == X86ISelAddressMode::RegBase &&
817 AM.Base_Reg.getNode() == 0 &&
818 AM.IndexReg.getNode() == 0) {
820 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
821 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
822 CN->getZExtValue() == 9) {
823 AM.Scale = unsigned(CN->getZExtValue())-1;
825 SDValue MulVal = N.getNode()->getOperand(0);
828 // Okay, we know that we have a scale by now. However, if the scaled
829 // value is an add of something and a constant, we can fold the
830 // constant into the disp field here.
831 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
832 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
833 Reg = MulVal.getNode()->getOperand(0);
834 ConstantSDNode *AddVal =
835 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
836 uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
839 X86::isOffsetSuitableForCodeModel(Disp, M,
840 AM.hasSymbolicDisplacement()))
843 Reg = N.getNode()->getOperand(0);
845 Reg = N.getNode()->getOperand(0);
848 AM.IndexReg = AM.Base_Reg = Reg;
855 // Given A-B, if A can be completely folded into the address and
856 // the index field with the index field unused, use -B as the index.
857 // This is a win if a has multiple parts that can be folded into
858 // the address. Also, this saves a mov if the base register has
859 // other uses, since it avoids a two-address sub instruction, however
860 // it costs an additional mov if the index register has other uses.
862 // Add an artificial use to this node so that we can keep track of
863 // it if it gets CSE'd with a different node.
864 HandleSDNode Handle(N);
866 // Test if the LHS of the sub can be folded.
867 X86ISelAddressMode Backup = AM;
868 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
872 // Test if the index field is free for use.
873 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
879 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
880 // If the RHS involves a register with multiple uses, this
881 // transformation incurs an extra mov, due to the neg instruction
882 // clobbering its operand.
883 if (!RHS.getNode()->hasOneUse() ||
884 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
885 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
886 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
887 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
888 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
890 // If the base is a register with multiple uses, this
891 // transformation may save a mov.
892 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
893 AM.Base_Reg.getNode() &&
894 !AM.Base_Reg.getNode()->hasOneUse()) ||
895 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
897 // If the folded LHS was interesting, this transformation saves
898 // address arithmetic.
899 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
900 ((AM.Disp != 0) && (Backup.Disp == 0)) +
901 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
903 // If it doesn't look like it may be an overall win, don't do it.
909 // Ok, the transformation is legal and appears profitable. Go for it.
910 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
911 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
915 // Insert the new nodes into the topological ordering.
916 if (Zero.getNode()->getNodeId() == -1 ||
917 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
918 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
919 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
921 if (Neg.getNode()->getNodeId() == -1 ||
922 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
923 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
924 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
930 // Add an artificial use to this node so that we can keep track of
931 // it if it gets CSE'd with a different node.
932 HandleSDNode Handle(N);
933 SDValue LHS = Handle.getValue().getNode()->getOperand(0);
934 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
936 X86ISelAddressMode Backup = AM;
937 if (!MatchAddressRecursively(LHS, AM, Depth+1) &&
938 !MatchAddressRecursively(RHS, AM, Depth+1))
941 LHS = Handle.getValue().getNode()->getOperand(0);
942 RHS = Handle.getValue().getNode()->getOperand(1);
944 // Try again after commuting the operands.
945 if (!MatchAddressRecursively(RHS, AM, Depth+1) &&
946 !MatchAddressRecursively(LHS, AM, Depth+1))
949 LHS = Handle.getValue().getNode()->getOperand(0);
950 RHS = Handle.getValue().getNode()->getOperand(1);
952 // If we couldn't fold both operands into the address at the same time,
953 // see if we can just put each operand into a register and fold at least
955 if (AM.BaseType == X86ISelAddressMode::RegBase &&
956 !AM.Base_Reg.getNode() &&
957 !AM.IndexReg.getNode()) {
967 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
968 if (isLogicallyAddWithConstant(N, CurDAG)) {
969 X86ISelAddressMode Backup = AM;
970 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
971 uint64_t Offset = CN->getSExtValue();
973 // Start with the LHS as an addr mode.
974 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
975 // Address could not have picked a GV address for the displacement.
977 // On x86-64, the resultant disp must fit in 32-bits.
979 X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M,
980 AM.hasSymbolicDisplacement()))) {
989 // Perform some heroic transforms on an and of a constant-count shift
990 // with a constant to enable use of the scaled offset field.
992 SDValue Shift = N.getOperand(0);
993 if (Shift.getNumOperands() != 2) break;
995 // Scale must not be used already.
996 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
998 SDValue X = Shift.getOperand(0);
999 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
1000 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
1001 if (!C1 || !C2) break;
1003 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This
1004 // allows us to convert the shift and and into an h-register extract and
1006 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) {
1007 unsigned ScaleLog = 8 - C1->getZExtValue();
1008 if (ScaleLog > 0 && ScaleLog < 4 &&
1009 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
1010 SDValue Eight = CurDAG->getConstant(8, MVT::i8);
1011 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
1012 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1014 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
1016 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
1017 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1020 // Insert the new nodes into the topological ordering.
1021 if (Eight.getNode()->getNodeId() == -1 ||
1022 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1023 CurDAG->RepositionNode(X.getNode(), Eight.getNode());
1024 Eight.getNode()->setNodeId(X.getNode()->getNodeId());
1026 if (Mask.getNode()->getNodeId() == -1 ||
1027 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1028 CurDAG->RepositionNode(X.getNode(), Mask.getNode());
1029 Mask.getNode()->setNodeId(X.getNode()->getNodeId());
1031 if (Srl.getNode()->getNodeId() == -1 ||
1032 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1033 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode());
1034 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId());
1036 if (And.getNode()->getNodeId() == -1 ||
1037 And.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1038 CurDAG->RepositionNode(N.getNode(), And.getNode());
1039 And.getNode()->setNodeId(N.getNode()->getNodeId());
1041 if (ShlCount.getNode()->getNodeId() == -1 ||
1042 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1043 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode());
1044 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId());
1046 if (Shl.getNode()->getNodeId() == -1 ||
1047 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1048 CurDAG->RepositionNode(N.getNode(), Shl.getNode());
1049 Shl.getNode()->setNodeId(N.getNode()->getNodeId());
1051 CurDAG->ReplaceAllUsesWith(N, Shl);
1053 AM.Scale = (1 << ScaleLog);
1058 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
1059 // allows us to fold the shift into this addressing mode.
1060 if (Shift.getOpcode() != ISD::SHL) break;
1062 // Not likely to be profitable if either the AND or SHIFT node has more
1063 // than one use (unless all uses are for address computation). Besides,
1064 // isel mechanism requires their node ids to be reused.
1065 if (!N.hasOneUse() || !Shift.hasOneUse())
1068 // Verify that the shift amount is something we can fold.
1069 unsigned ShiftCst = C1->getZExtValue();
1070 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
1073 // Get the new AND mask, this folds to a constant.
1074 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1075 SDValue(C2, 0), SDValue(C1, 0));
1076 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
1078 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1079 NewAND, SDValue(C1, 0));
1081 // Insert the new nodes into the topological ordering.
1082 if (C1->getNodeId() > X.getNode()->getNodeId()) {
1083 CurDAG->RepositionNode(X.getNode(), C1);
1084 C1->setNodeId(X.getNode()->getNodeId());
1086 if (NewANDMask.getNode()->getNodeId() == -1 ||
1087 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1088 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
1089 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
1091 if (NewAND.getNode()->getNodeId() == -1 ||
1092 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1093 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
1094 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
1096 if (NewSHIFT.getNode()->getNodeId() == -1 ||
1097 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1098 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
1099 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
1102 CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
1104 AM.Scale = 1 << ShiftCst;
1105 AM.IndexReg = NewAND;
1110 return MatchAddressBase(N, AM);
1113 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1114 /// specified addressing mode without any further recursion.
1115 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1116 // Is the base register already occupied?
1117 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1118 // If so, check to see if the scale index register is set.
1119 if (AM.IndexReg.getNode() == 0) {
1125 // Otherwise, we cannot select it.
1129 // Default, generate it as a register.
1130 AM.BaseType = X86ISelAddressMode::RegBase;
1135 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1136 /// It returns the operands which make up the maximal addressing mode it can
1137 /// match by reference.
1138 bool X86DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
1139 SDValue &Scale, SDValue &Index,
1140 SDValue &Disp, SDValue &Segment) {
1141 X86ISelAddressMode AM;
1142 if (MatchAddress(N, AM))
1145 EVT VT = N.getValueType();
1146 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1147 if (!AM.Base_Reg.getNode())
1148 AM.Base_Reg = CurDAG->getRegister(0, VT);
1151 if (!AM.IndexReg.getNode())
1152 AM.IndexReg = CurDAG->getRegister(0, VT);
1154 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1158 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1159 /// match a load whose top elements are either undef or zeros. The load flavor
1160 /// is derived from the type of N, which is either v4f32 or v2f64.
1163 /// PatternChainNode: this is the matched node that has a chain input and
1165 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1166 SDValue N, SDValue &Base,
1167 SDValue &Scale, SDValue &Index,
1168 SDValue &Disp, SDValue &Segment,
1169 SDValue &PatternNodeWithChain) {
1170 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1171 PatternNodeWithChain = N.getOperand(0);
1172 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1173 PatternNodeWithChain.hasOneUse() &&
1174 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1175 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1176 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1177 if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp,Segment))
1183 // Also handle the case where we explicitly require zeros in the top
1184 // elements. This is a vector shuffle from the zero vector.
1185 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1186 // Check to see if the top elements are all zeros (or bitcast of zeros).
1187 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1188 N.getOperand(0).getNode()->hasOneUse() &&
1189 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1190 N.getOperand(0).getOperand(0).hasOneUse() &&
1191 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1192 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1193 // Okay, this is a zero extending load. Fold it.
1194 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1195 if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1197 PatternNodeWithChain = SDValue(LD, 0);
1204 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1205 /// mode it matches can be cost effectively emitted as an LEA instruction.
1206 bool X86DAGToDAGISel::SelectLEAAddr(SDNode *Op, SDValue N,
1207 SDValue &Base, SDValue &Scale,
1208 SDValue &Index, SDValue &Disp) {
1209 X86ISelAddressMode AM;
1211 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1213 SDValue Copy = AM.Segment;
1214 SDValue T = CurDAG->getRegister(0, MVT::i32);
1216 if (MatchAddress(N, AM))
1218 assert (T == AM.Segment);
1221 EVT VT = N.getValueType();
1222 unsigned Complexity = 0;
1223 if (AM.BaseType == X86ISelAddressMode::RegBase)
1224 if (AM.Base_Reg.getNode())
1227 AM.Base_Reg = CurDAG->getRegister(0, VT);
1228 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1231 if (AM.IndexReg.getNode())
1234 AM.IndexReg = CurDAG->getRegister(0, VT);
1236 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1241 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1242 // to a LEA. This is determined with some expermentation but is by no means
1243 // optimal (especially for code size consideration). LEA is nice because of
1244 // its three-address nature. Tweak the cost function again when we can run
1245 // convertToThreeAddress() at register allocation time.
1246 if (AM.hasSymbolicDisplacement()) {
1247 // For X86-64, we should always use lea to materialize RIP relative
1249 if (Subtarget->is64Bit())
1255 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1258 // If it isn't worth using an LEA, reject it.
1259 if (Complexity <= 2)
1263 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1267 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1268 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDNode *Op, SDValue N, SDValue &Base,
1269 SDValue &Scale, SDValue &Index,
1271 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1272 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1274 X86ISelAddressMode AM;
1275 AM.GV = GA->getGlobal();
1276 AM.Disp += GA->getOffset();
1277 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1278 AM.SymbolFlags = GA->getTargetFlags();
1280 if (N.getValueType() == MVT::i32) {
1282 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1284 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1288 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1293 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1294 SDValue &Base, SDValue &Scale,
1295 SDValue &Index, SDValue &Disp,
1297 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1298 !IsProfitableToFold(N, P, P) ||
1299 !IsLegalToFold(N, P, P, OptLevel))
1302 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
1305 /// getGlobalBaseReg - Return an SDNode that returns the value of
1306 /// the global base register. Output instructions required to
1307 /// initialize the global base register, if necessary.
1309 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1310 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1311 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1314 static SDNode *FindCallStartFromCall(SDNode *Node) {
1315 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1316 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1317 "Node doesn't have a token chain argument!");
1318 return FindCallStartFromCall(Node->getOperand(0).getNode());
1321 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1322 SDValue Chain = Node->getOperand(0);
1323 SDValue In1 = Node->getOperand(1);
1324 SDValue In2L = Node->getOperand(2);
1325 SDValue In2H = Node->getOperand(3);
1326 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1327 if (!SelectAddr(In1.getNode(), In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1329 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1330 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1331 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1332 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1333 MVT::i32, MVT::i32, MVT::Other, Ops,
1334 array_lengthof(Ops));
1335 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1339 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1340 if (Node->hasAnyUseOfValue(0))
1343 // Optimize common patterns for __sync_add_and_fetch and
1344 // __sync_sub_and_fetch where the result is not used. This allows us
1345 // to use "lock" version of add, sub, inc, dec instructions.
1346 // FIXME: Do not use special instructions but instead add the "lock"
1347 // prefix to the target node somehow. The extra information will then be
1348 // transferred to machine instruction and it denotes the prefix.
1349 SDValue Chain = Node->getOperand(0);
1350 SDValue Ptr = Node->getOperand(1);
1351 SDValue Val = Node->getOperand(2);
1352 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1353 if (!SelectAddr(Ptr.getNode(), Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1356 bool isInc = false, isDec = false, isSub = false, isCN = false;
1357 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1360 int64_t CNVal = CN->getSExtValue();
1363 else if (CNVal == -1)
1365 else if (CNVal >= 0)
1366 Val = CurDAG->getTargetConstant(CNVal, NVT);
1369 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1371 } else if (Val.hasOneUse() &&
1372 Val.getOpcode() == ISD::SUB &&
1373 X86::isZeroNode(Val.getOperand(0))) {
1375 Val = Val.getOperand(1);
1379 switch (NVT.getSimpleVT().SimpleTy) {
1383 Opc = X86::LOCK_INC8m;
1385 Opc = X86::LOCK_DEC8m;
1388 Opc = X86::LOCK_SUB8mi;
1390 Opc = X86::LOCK_SUB8mr;
1393 Opc = X86::LOCK_ADD8mi;
1395 Opc = X86::LOCK_ADD8mr;
1400 Opc = X86::LOCK_INC16m;
1402 Opc = X86::LOCK_DEC16m;
1405 if (Predicate_immSext8(Val.getNode()))
1406 Opc = X86::LOCK_SUB16mi8;
1408 Opc = X86::LOCK_SUB16mi;
1410 Opc = X86::LOCK_SUB16mr;
1413 if (Predicate_immSext8(Val.getNode()))
1414 Opc = X86::LOCK_ADD16mi8;
1416 Opc = X86::LOCK_ADD16mi;
1418 Opc = X86::LOCK_ADD16mr;
1423 Opc = X86::LOCK_INC32m;
1425 Opc = X86::LOCK_DEC32m;
1428 if (Predicate_immSext8(Val.getNode()))
1429 Opc = X86::LOCK_SUB32mi8;
1431 Opc = X86::LOCK_SUB32mi;
1433 Opc = X86::LOCK_SUB32mr;
1436 if (Predicate_immSext8(Val.getNode()))
1437 Opc = X86::LOCK_ADD32mi8;
1439 Opc = X86::LOCK_ADD32mi;
1441 Opc = X86::LOCK_ADD32mr;
1446 Opc = X86::LOCK_INC64m;
1448 Opc = X86::LOCK_DEC64m;
1450 Opc = X86::LOCK_SUB64mr;
1452 if (Predicate_immSext8(Val.getNode()))
1453 Opc = X86::LOCK_SUB64mi8;
1454 else if (Predicate_i64immSExt32(Val.getNode()))
1455 Opc = X86::LOCK_SUB64mi32;
1458 Opc = X86::LOCK_ADD64mr;
1460 if (Predicate_immSext8(Val.getNode()))
1461 Opc = X86::LOCK_ADD64mi8;
1462 else if (Predicate_i64immSExt32(Val.getNode()))
1463 Opc = X86::LOCK_ADD64mi32;
1469 DebugLoc dl = Node->getDebugLoc();
1470 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1472 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1473 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1474 if (isInc || isDec) {
1475 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1476 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
1477 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1478 SDValue RetVals[] = { Undef, Ret };
1479 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1481 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1482 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1483 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1484 SDValue RetVals[] = { Undef, Ret };
1485 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1489 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1490 /// any uses which require the SF or OF bits to be accurate.
1491 static bool HasNoSignedComparisonUses(SDNode *N) {
1492 // Examine each user of the node.
1493 for (SDNode::use_iterator UI = N->use_begin(),
1494 UE = N->use_end(); UI != UE; ++UI) {
1495 // Only examine CopyToReg uses.
1496 if (UI->getOpcode() != ISD::CopyToReg)
1498 // Only examine CopyToReg uses that copy to EFLAGS.
1499 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1502 // Examine each user of the CopyToReg use.
1503 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1504 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1505 // Only examine the Flag result.
1506 if (FlagUI.getUse().getResNo() != 1) continue;
1507 // Anything unusual: assume conservatively.
1508 if (!FlagUI->isMachineOpcode()) return false;
1509 // Examine the opcode of the user.
1510 switch (FlagUI->getMachineOpcode()) {
1511 // These comparisons don't treat the most significant bit specially.
1512 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1513 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1514 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1515 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1516 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1517 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1518 case X86::CMOVA16rr: case X86::CMOVA16rm:
1519 case X86::CMOVA32rr: case X86::CMOVA32rm:
1520 case X86::CMOVA64rr: case X86::CMOVA64rm:
1521 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1522 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1523 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1524 case X86::CMOVB16rr: case X86::CMOVB16rm:
1525 case X86::CMOVB32rr: case X86::CMOVB32rm:
1526 case X86::CMOVB64rr: case X86::CMOVB64rm:
1527 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1528 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1529 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1530 case X86::CMOVE16rr: case X86::CMOVE16rm:
1531 case X86::CMOVE32rr: case X86::CMOVE32rm:
1532 case X86::CMOVE64rr: case X86::CMOVE64rm:
1533 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1534 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1535 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1536 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1537 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1538 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1539 case X86::CMOVP16rr: case X86::CMOVP16rm:
1540 case X86::CMOVP32rr: case X86::CMOVP32rm:
1541 case X86::CMOVP64rr: case X86::CMOVP64rm:
1543 // Anything else: assume conservatively.
1544 default: return false;
1551 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
1552 EVT NVT = Node->getValueType(0);
1554 unsigned Opcode = Node->getOpcode();
1555 DebugLoc dl = Node->getDebugLoc();
1557 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
1559 if (Node->isMachineOpcode()) {
1560 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
1561 return NULL; // Already selected.
1566 case X86ISD::GlobalBaseReg:
1567 return getGlobalBaseReg();
1569 case X86ISD::ATOMOR64_DAG:
1570 return SelectAtomic64(Node, X86::ATOMOR6432);
1571 case X86ISD::ATOMXOR64_DAG:
1572 return SelectAtomic64(Node, X86::ATOMXOR6432);
1573 case X86ISD::ATOMADD64_DAG:
1574 return SelectAtomic64(Node, X86::ATOMADD6432);
1575 case X86ISD::ATOMSUB64_DAG:
1576 return SelectAtomic64(Node, X86::ATOMSUB6432);
1577 case X86ISD::ATOMNAND64_DAG:
1578 return SelectAtomic64(Node, X86::ATOMNAND6432);
1579 case X86ISD::ATOMAND64_DAG:
1580 return SelectAtomic64(Node, X86::ATOMAND6432);
1581 case X86ISD::ATOMSWAP64_DAG:
1582 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1584 case ISD::ATOMIC_LOAD_ADD: {
1585 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
1591 case ISD::SMUL_LOHI:
1592 case ISD::UMUL_LOHI: {
1593 SDValue N0 = Node->getOperand(0);
1594 SDValue N1 = Node->getOperand(1);
1596 bool isSigned = Opcode == ISD::SMUL_LOHI;
1598 switch (NVT.getSimpleVT().SimpleTy) {
1599 default: llvm_unreachable("Unsupported VT!");
1600 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1601 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1602 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1603 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1606 switch (NVT.getSimpleVT().SimpleTy) {
1607 default: llvm_unreachable("Unsupported VT!");
1608 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1609 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1610 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1611 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1615 unsigned LoReg, HiReg;
1616 switch (NVT.getSimpleVT().SimpleTy) {
1617 default: llvm_unreachable("Unsupported VT!");
1618 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1619 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1620 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1621 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1624 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1625 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1626 // Multiply is commmutative.
1628 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1633 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1634 N0, SDValue()).getValue(1);
1637 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1640 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1641 array_lengthof(Ops));
1642 InFlag = SDValue(CNode, 1);
1643 // Update the chain.
1644 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1647 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1650 // Prevent use of AH in a REX instruction by referencing AX instead.
1651 if (HiReg == X86::AH && Subtarget->is64Bit() &&
1652 !SDValue(Node, 1).use_empty()) {
1653 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1654 X86::AX, MVT::i16, InFlag);
1655 InFlag = Result.getValue(2);
1656 // Get the low part if needed. Don't use getCopyFromReg for aliasing
1658 if (!SDValue(Node, 0).use_empty())
1659 ReplaceUses(SDValue(Node, 1),
1660 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1662 // Shift AX down 8 bits.
1663 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
1665 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1666 // Then truncate it down to i8.
1667 ReplaceUses(SDValue(Node, 1),
1668 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1670 // Copy the low half of the result, if it is needed.
1671 if (!SDValue(Node, 0).use_empty()) {
1672 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1673 LoReg, NVT, InFlag);
1674 InFlag = Result.getValue(2);
1675 ReplaceUses(SDValue(Node, 0), Result);
1676 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1678 // Copy the high half of the result, if it is needed.
1679 if (!SDValue(Node, 1).use_empty()) {
1680 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1681 HiReg, NVT, InFlag);
1682 InFlag = Result.getValue(2);
1683 ReplaceUses(SDValue(Node, 1), Result);
1684 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1691 case ISD::UDIVREM: {
1692 SDValue N0 = Node->getOperand(0);
1693 SDValue N1 = Node->getOperand(1);
1695 bool isSigned = Opcode == ISD::SDIVREM;
1697 switch (NVT.getSimpleVT().SimpleTy) {
1698 default: llvm_unreachable("Unsupported VT!");
1699 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1700 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1701 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1702 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1705 switch (NVT.getSimpleVT().SimpleTy) {
1706 default: llvm_unreachable("Unsupported VT!");
1707 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1708 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1709 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1710 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1714 unsigned LoReg, HiReg, ClrReg;
1715 unsigned ClrOpcode, SExtOpcode;
1716 switch (NVT.getSimpleVT().SimpleTy) {
1717 default: llvm_unreachable("Unsupported VT!");
1719 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
1721 SExtOpcode = X86::CBW;
1724 LoReg = X86::AX; HiReg = X86::DX;
1725 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
1726 SExtOpcode = X86::CWD;
1729 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
1730 ClrOpcode = X86::MOV32r0;
1731 SExtOpcode = X86::CDQ;
1734 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
1735 ClrOpcode = X86::MOV64r0;
1736 SExtOpcode = X86::CQO;
1740 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1741 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1742 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
1745 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
1746 // Special case for div8, just use a move with zero extension to AX to
1747 // clear the upper 8 bits (AH).
1748 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
1749 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
1750 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
1752 SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16,
1754 array_lengthof(Ops)), 0);
1755 Chain = Move.getValue(1);
1756 ReplaceUses(N0.getValue(1), Chain);
1759 SDValue(CurDAG->getMachineNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
1760 Chain = CurDAG->getEntryNode();
1762 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
1763 InFlag = Chain.getValue(1);
1766 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
1767 LoReg, N0, SDValue()).getValue(1);
1768 if (isSigned && !signBitIsZero) {
1769 // Sign extend the low part into the high part.
1771 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
1773 // Zero out the high part, effectively zero extending the input.
1775 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
1776 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
1777 ClrNode, InFlag).getValue(1);
1782 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1785 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1786 array_lengthof(Ops));
1787 InFlag = SDValue(CNode, 1);
1788 // Update the chain.
1789 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1792 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1795 // Prevent use of AH in a REX instruction by referencing AX instead.
1796 // Shift it down 8 bits.
1797 if (HiReg == X86::AH && Subtarget->is64Bit() &&
1798 !SDValue(Node, 1).use_empty()) {
1799 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1800 X86::AX, MVT::i16, InFlag);
1801 InFlag = Result.getValue(2);
1803 // If we also need AL (the quotient), get it by extracting a subreg from
1804 // Result. The fast register allocator does not like multiple CopyFromReg
1805 // nodes using aliasing registers.
1806 if (!SDValue(Node, 0).use_empty())
1807 ReplaceUses(SDValue(Node, 0),
1808 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1810 // Shift AX right by 8 bits instead of using AH.
1811 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
1813 CurDAG->getTargetConstant(8, MVT::i8)),
1815 ReplaceUses(SDValue(Node, 1),
1816 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1818 // Copy the division (low) result, if it is needed.
1819 if (!SDValue(Node, 0).use_empty()) {
1820 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1821 LoReg, NVT, InFlag);
1822 InFlag = Result.getValue(2);
1823 ReplaceUses(SDValue(Node, 0), Result);
1824 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1826 // Copy the remainder (high) result, if it is needed.
1827 if (!SDValue(Node, 1).use_empty()) {
1828 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1829 HiReg, NVT, InFlag);
1830 InFlag = Result.getValue(2);
1831 ReplaceUses(SDValue(Node, 1), Result);
1832 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1838 SDValue N0 = Node->getOperand(0);
1839 SDValue N1 = Node->getOperand(1);
1841 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
1842 // use a smaller encoding.
1843 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse())
1844 // Look past the truncate if CMP is the only use of it.
1845 N0 = N0.getOperand(0);
1846 if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
1847 N0.getValueType() != MVT::i8 &&
1848 X86::isZeroNode(N1)) {
1849 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
1852 // For example, convert "testl %eax, $8" to "testb %al, $8"
1853 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
1854 (!(C->getZExtValue() & 0x80) ||
1855 HasNoSignedComparisonUses(Node))) {
1856 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
1857 SDValue Reg = N0.getNode()->getOperand(0);
1859 // On x86-32, only the ABCD registers have 8-bit subregisters.
1860 if (!Subtarget->is64Bit()) {
1861 TargetRegisterClass *TRC = 0;
1862 switch (N0.getValueType().getSimpleVT().SimpleTy) {
1863 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
1864 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
1865 default: llvm_unreachable("Unsupported TEST operand type!");
1867 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
1868 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
1869 Reg.getValueType(), Reg, RC), 0);
1872 // Extract the l-register.
1873 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
1877 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
1880 // For example, "testl %eax, $2048" to "testb %ah, $8".
1881 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
1882 (!(C->getZExtValue() & 0x8000) ||
1883 HasNoSignedComparisonUses(Node))) {
1884 // Shift the immediate right by 8 bits.
1885 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
1887 SDValue Reg = N0.getNode()->getOperand(0);
1889 // Put the value in an ABCD register.
1890 TargetRegisterClass *TRC = 0;
1891 switch (N0.getValueType().getSimpleVT().SimpleTy) {
1892 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
1893 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
1894 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
1895 default: llvm_unreachable("Unsupported TEST operand type!");
1897 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
1898 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
1899 Reg.getValueType(), Reg, RC), 0);
1901 // Extract the h-register.
1902 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
1905 // Emit a testb. No special NOREX tricks are needed since there's
1906 // only one GPR operand!
1907 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
1908 Subreg, ShiftedImm);
1911 // For example, "testl %eax, $32776" to "testw %ax, $32776".
1912 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
1913 N0.getValueType() != MVT::i16 &&
1914 (!(C->getZExtValue() & 0x8000) ||
1915 HasNoSignedComparisonUses(Node))) {
1916 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
1917 SDValue Reg = N0.getNode()->getOperand(0);
1919 // Extract the 16-bit subregister.
1920 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
1924 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
1927 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
1928 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
1929 N0.getValueType() == MVT::i64 &&
1930 (!(C->getZExtValue() & 0x80000000) ||
1931 HasNoSignedComparisonUses(Node))) {
1932 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
1933 SDValue Reg = N0.getNode()->getOperand(0);
1935 // Extract the 32-bit subregister.
1936 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
1940 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
1947 SDNode *ResNode = SelectCode(Node);
1949 DEBUG(dbgs() << "=> ";
1950 if (ResNode == NULL || ResNode == Node)
1953 ResNode->dump(CurDAG);
1959 bool X86DAGToDAGISel::
1960 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1961 std::vector<SDValue> &OutOps) {
1962 SDValue Op0, Op1, Op2, Op3, Op4;
1963 switch (ConstraintCode) {
1964 case 'o': // offsetable ??
1965 case 'v': // not offsetable ??
1966 default: return true;
1968 if (!SelectAddr(Op.getNode(), Op, Op0, Op1, Op2, Op3, Op4))
1973 OutOps.push_back(Op0);
1974 OutOps.push_back(Op1);
1975 OutOps.push_back(Op2);
1976 OutOps.push_back(Op3);
1977 OutOps.push_back(Op4);
1981 /// createX86ISelDag - This pass converts a legalized DAG into a
1982 /// X86-specific DAG, ready for instruction scheduling.
1984 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
1985 llvm::CodeGenOpt::Level OptLevel) {
1986 return new X86DAGToDAGISel(TM, OptLevel);