1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// This corresponds to X86AddressMode, but uses SDValue's instead of register
50 /// numbers for the leaves of the matched tree.
51 struct X86ISelAddressMode {
57 // This is really a union, discriminated by BaseType!
65 const GlobalValue *GV;
67 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
77 MCSym(nullptr), JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {}
79 bool hasSymbolicDisplacement() const {
80 return GV != nullptr || CP != nullptr || ES != nullptr ||
81 MCSym != nullptr || JT != -1 || BlockAddr != nullptr;
84 bool hasBaseOrIndexReg() const {
85 return BaseType == FrameIndexBase ||
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
89 /// Return true if this addressing mode is already RIP-relative.
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
103 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
105 dbgs() << "X86ISelAddressMode " << this << '\n';
106 dbgs() << "Base_Reg ";
107 if (Base_Reg.getNode())
108 Base_Reg.getNode()->dump();
111 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
112 << " Scale" << Scale << '\n'
114 if (IndexReg.getNode())
115 IndexReg.getNode()->dump();
118 dbgs() << " Disp " << Disp << '\n'
140 dbgs() << " JT" << JT << " Align" << Align << '\n';
147 //===--------------------------------------------------------------------===//
148 /// ISel - X86-specific code to select X86 machine instructions for
149 /// SelectionDAG operations.
151 class X86DAGToDAGISel final : public SelectionDAGISel {
152 /// Keep a pointer to the X86Subtarget around so that we can
153 /// make the right decision when generating code for different targets.
154 const X86Subtarget *Subtarget;
156 /// If true, selector should try to optimize for code size instead of
161 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
162 : SelectionDAGISel(tm, OptLevel), OptForSize(false) {}
164 const char *getPassName() const override {
165 return "X86 DAG->DAG Instruction Selection";
168 bool runOnMachineFunction(MachineFunction &MF) override {
169 // Reset the subtarget each time through.
170 Subtarget = &MF.getSubtarget<X86Subtarget>();
171 SelectionDAGISel::runOnMachineFunction(MF);
175 void EmitFunctionEntryCode() override;
177 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
179 void PreprocessISelDAG() override;
181 inline bool immSext8(SDNode *N) const {
182 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
185 // True if the 64-bit immediate fits in a 32-bit sign-extended field.
186 inline bool i64immSExt32(SDNode *N) const {
187 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
188 return (int64_t)v == (int32_t)v;
191 // Include the pieces autogenerated from the target description.
192 #include "X86GenDAGISel.inc"
195 SDNode *Select(SDNode *N) override;
196 SDNode *selectGather(SDNode *N, unsigned Opc);
197 SDNode *selectAtomicLoadArith(SDNode *Node, MVT NVT);
199 bool foldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
200 bool matchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
201 bool matchWrapper(SDValue N, X86ISelAddressMode &AM);
202 bool matchAddress(SDValue N, X86ISelAddressMode &AM);
203 bool matchAdd(SDValue N, X86ISelAddressMode &AM, unsigned Depth);
204 bool matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
206 bool matchAddressBase(SDValue N, X86ISelAddressMode &AM);
207 bool selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
208 SDValue &Scale, SDValue &Index, SDValue &Disp,
210 bool selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
211 SDValue &Scale, SDValue &Index, SDValue &Disp,
213 bool selectMOV64Imm32(SDValue N, SDValue &Imm);
214 bool selectLEAAddr(SDValue N, SDValue &Base,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
217 bool selectLEA64_32Addr(SDValue N, SDValue &Base,
218 SDValue &Scale, SDValue &Index, SDValue &Disp,
220 bool selectTLSADDRAddr(SDValue N, SDValue &Base,
221 SDValue &Scale, SDValue &Index, SDValue &Disp,
223 bool selectScalarSSELoad(SDNode *Root, SDValue N,
224 SDValue &Base, SDValue &Scale,
225 SDValue &Index, SDValue &Disp,
227 SDValue &NodeWithChain);
229 bool tryFoldLoad(SDNode *P, SDValue N,
230 SDValue &Base, SDValue &Scale,
231 SDValue &Index, SDValue &Disp,
234 /// Implement addressing mode selection for inline asm expressions.
235 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
236 unsigned ConstraintID,
237 std::vector<SDValue> &OutOps) override;
239 void emitSpecialCodeForMain();
241 inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL,
242 SDValue &Base, SDValue &Scale,
243 SDValue &Index, SDValue &Disp,
245 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
246 ? CurDAG->getTargetFrameIndex(
248 TLI->getPointerTy(CurDAG->getDataLayout()))
250 Scale = getI8Imm(AM.Scale, DL);
252 // These are 32-bit even in 64-bit mode since RIP-relative offset
255 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
259 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
260 AM.Align, AM.Disp, AM.SymbolFlags);
262 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
263 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
264 } else if (AM.MCSym) {
265 assert(!AM.Disp && "Non-zero displacement is ignored with MCSym.");
266 assert(AM.SymbolFlags == 0 && "oo");
267 Disp = CurDAG->getMCSymbol(AM.MCSym, MVT::i32);
268 } else if (AM.JT != -1) {
269 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
270 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
271 } else if (AM.BlockAddr)
272 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
275 Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);
277 if (AM.Segment.getNode())
278 Segment = AM.Segment;
280 Segment = CurDAG->getRegister(0, MVT::i32);
283 // Utility function to determine whether we should avoid selecting
284 // immediate forms of instructions for better code size or not.
285 // At a high level, we'd like to avoid such instructions when
286 // we have similar constants used within the same basic block
287 // that can be kept in a register.
289 bool shouldAvoidImmediateInstFormsForSize(SDNode *N) const {
290 uint32_t UseCount = 0;
292 // Do not want to hoist if we're not optimizing for size.
293 // TODO: We'd like to remove this restriction.
294 // See the comment in X86InstrInfo.td for more info.
298 // Walk all the users of the immediate.
299 for (SDNode::use_iterator UI = N->use_begin(),
300 UE = N->use_end(); (UI != UE) && (UseCount < 2); ++UI) {
304 // This user is already selected. Count it as a legitimate use and
306 if (User->isMachineOpcode()) {
311 // We want to count stores of immediates as real uses.
312 if (User->getOpcode() == ISD::STORE &&
313 User->getOperand(1).getNode() == N) {
318 // We don't currently match users that have > 2 operands (except
319 // for stores, which are handled above)
320 // Those instruction won't match in ISEL, for now, and would
321 // be counted incorrectly.
322 // This may change in the future as we add additional instruction
324 if (User->getNumOperands() != 2)
327 // Immediates that are used for offsets as part of stack
328 // manipulation should be left alone. These are typically
329 // used to indicate SP offsets for argument passing and
330 // will get pulled into stores/pushes (implicitly).
331 if (User->getOpcode() == X86ISD::ADD ||
332 User->getOpcode() == ISD::ADD ||
333 User->getOpcode() == X86ISD::SUB ||
334 User->getOpcode() == ISD::SUB) {
336 // Find the other operand of the add/sub.
337 SDValue OtherOp = User->getOperand(0);
338 if (OtherOp.getNode() == N)
339 OtherOp = User->getOperand(1);
341 // Don't count if the other operand is SP.
342 RegisterSDNode *RegNode;
343 if (OtherOp->getOpcode() == ISD::CopyFromReg &&
344 (RegNode = dyn_cast_or_null<RegisterSDNode>(
345 OtherOp->getOperand(1).getNode())))
346 if ((RegNode->getReg() == X86::ESP) ||
347 (RegNode->getReg() == X86::RSP))
351 // ... otherwise, count this and move on.
355 // If we have more than 1 use, then recommend for hoisting.
356 return (UseCount > 1);
359 /// Return a target constant with the specified value of type i8.
360 inline SDValue getI8Imm(unsigned Imm, SDLoc DL) {
361 return CurDAG->getTargetConstant(Imm, DL, MVT::i8);
364 /// Return a target constant with the specified value, of type i32.
365 inline SDValue getI32Imm(unsigned Imm, SDLoc DL) {
366 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
369 /// Return an SDNode that returns the value of the global base register.
370 /// Output instructions required to initialize the global base register,
372 SDNode *getGlobalBaseReg();
374 /// Return a reference to the TargetMachine, casted to the target-specific
376 const X86TargetMachine &getTargetMachine() const {
377 return static_cast<const X86TargetMachine &>(TM);
380 /// Return a reference to the TargetInstrInfo, casted to the target-specific
382 const X86InstrInfo *getInstrInfo() const {
383 return Subtarget->getInstrInfo();
386 /// \brief Address-mode matching performs shift-of-and to and-of-shift
387 /// reassociation in order to expose more scaled addressing
389 bool ComplexPatternFuncMutatesDAG() const override {
397 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
398 if (OptLevel == CodeGenOpt::None) return false;
403 if (N.getOpcode() != ISD::LOAD)
406 // If N is a load, do additional profitability checks.
408 switch (U->getOpcode()) {
421 SDValue Op1 = U->getOperand(1);
423 // If the other operand is a 8-bit immediate we should fold the immediate
424 // instead. This reduces code size.
426 // movl 4(%esp), %eax
430 // addl 4(%esp), %eax
431 // The former is 2 bytes shorter. In case where the increment is 1, then
432 // the saving can be 4 bytes (by using incl %eax).
433 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
434 if (Imm->getAPIntValue().isSignedIntN(8))
437 // If the other operand is a TLS address, we should fold it instead.
440 // leal i@NTPOFF(%eax), %eax
442 // movl $i@NTPOFF, %eax
444 // if the block also has an access to a second TLS address this will save
446 // FIXME: This is probably also true for non-TLS addresses.
447 if (Op1.getOpcode() == X86ISD::Wrapper) {
448 SDValue Val = Op1.getOperand(0);
449 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
459 /// Replace the original chain operand of the call with
460 /// load's chain operand and move load below the call's chain operand.
461 static void moveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
462 SDValue Call, SDValue OrigChain) {
463 SmallVector<SDValue, 8> Ops;
464 SDValue Chain = OrigChain.getOperand(0);
465 if (Chain.getNode() == Load.getNode())
466 Ops.push_back(Load.getOperand(0));
468 assert(Chain.getOpcode() == ISD::TokenFactor &&
469 "Unexpected chain operand");
470 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
471 if (Chain.getOperand(i).getNode() == Load.getNode())
472 Ops.push_back(Load.getOperand(0));
474 Ops.push_back(Chain.getOperand(i));
476 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
478 Ops.push_back(NewChain);
480 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
481 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
482 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
483 Load.getOperand(1), Load.getOperand(2));
486 Ops.push_back(SDValue(Load.getNode(), 1));
487 Ops.append(Call->op_begin() + 1, Call->op_end());
488 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
491 /// Return true if call address is a load and it can be
492 /// moved below CALLSEQ_START and the chains leading up to the call.
493 /// Return the CALLSEQ_START by reference as a second output.
494 /// In the case of a tail call, there isn't a callseq node between the call
495 /// chain and the load.
496 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
497 // The transformation is somewhat dangerous if the call's chain was glued to
498 // the call. After MoveBelowOrigChain the load is moved between the call and
499 // the chain, this can create a cycle if the load is not folded. So it is
500 // *really* important that we are sure the load will be folded.
501 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
503 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
506 LD->getAddressingMode() != ISD::UNINDEXED ||
507 LD->getExtensionType() != ISD::NON_EXTLOAD)
510 // Now let's find the callseq_start.
511 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
512 if (!Chain.hasOneUse())
514 Chain = Chain.getOperand(0);
517 if (!Chain.getNumOperands())
519 // Since we are not checking for AA here, conservatively abort if the chain
520 // writes to memory. It's not safe to move the callee (a load) across a store.
521 if (isa<MemSDNode>(Chain.getNode()) &&
522 cast<MemSDNode>(Chain.getNode())->writeMem())
524 if (Chain.getOperand(0).getNode() == Callee.getNode())
526 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
527 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
528 Callee.getValue(1).hasOneUse())
533 void X86DAGToDAGISel::PreprocessISelDAG() {
534 // OptForSize is used in pattern predicates that isel is matching.
535 OptForSize = MF->getFunction()->optForSize();
537 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
538 E = CurDAG->allnodes_end(); I != E; ) {
539 SDNode *N = &*I++; // Preincrement iterator to avoid invalidation issues.
541 if (OptLevel != CodeGenOpt::None &&
542 // Only does this when target favors doesn't favor register indirect
544 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
545 (N->getOpcode() == X86ISD::TC_RETURN &&
546 // Only does this if load can be folded into TC_RETURN.
547 (Subtarget->is64Bit() ||
548 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
549 /// Also try moving call address load from outside callseq_start to just
550 /// before the call to allow it to be folded.
568 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
569 SDValue Chain = N->getOperand(0);
570 SDValue Load = N->getOperand(1);
571 if (!isCalleeLoad(Load, Chain, HasCallSeq))
573 moveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
578 // Lower fpround and fpextend nodes that target the FP stack to be store and
579 // load to the stack. This is a gross hack. We would like to simply mark
580 // these as being illegal, but when we do that, legalize produces these when
581 // it expands calls, then expands these in the same legalize pass. We would
582 // like dag combine to be able to hack on these between the call expansion
583 // and the node legalization. As such this pass basically does "really
584 // late" legalization of these inline with the X86 isel pass.
585 // FIXME: This should only happen when not compiled with -O0.
586 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
589 MVT SrcVT = N->getOperand(0).getSimpleValueType();
590 MVT DstVT = N->getSimpleValueType(0);
592 // If any of the sources are vectors, no fp stack involved.
593 if (SrcVT.isVector() || DstVT.isVector())
596 // If the source and destination are SSE registers, then this is a legal
597 // conversion that should not be lowered.
598 const X86TargetLowering *X86Lowering =
599 static_cast<const X86TargetLowering *>(TLI);
600 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
601 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
602 if (SrcIsSSE && DstIsSSE)
605 if (!SrcIsSSE && !DstIsSSE) {
606 // If this is an FPStack extension, it is a noop.
607 if (N->getOpcode() == ISD::FP_EXTEND)
609 // If this is a value-preserving FPStack truncation, it is a noop.
610 if (N->getConstantOperandVal(1))
614 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
615 // FPStack has extload and truncstore. SSE can fold direct loads into other
616 // operations. Based on this, decide what we want to do.
618 if (N->getOpcode() == ISD::FP_ROUND)
619 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
621 MemVT = SrcIsSSE ? SrcVT : DstVT;
623 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
626 // FIXME: optimize the case where the src/dest is a load or store?
627 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
629 MemTmp, MachinePointerInfo(), MemVT,
631 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
632 MachinePointerInfo(),
633 MemVT, false, false, false, 0);
635 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
636 // extload we created. This will cause general havok on the dag because
637 // anything below the conversion could be folded into other existing nodes.
638 // To avoid invalidating 'I', back it up to the convert node.
640 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
642 // Now that we did that, the node is dead. Increment the iterator to the
643 // next node to process, then delete N.
645 CurDAG->DeleteNode(N);
650 /// Emit any code that needs to be executed only in the main function.
651 void X86DAGToDAGISel::emitSpecialCodeForMain() {
652 if (Subtarget->isTargetCygMing()) {
653 TargetLowering::ArgListTy Args;
654 auto &DL = CurDAG->getDataLayout();
656 TargetLowering::CallLoweringInfo CLI(*CurDAG);
657 CLI.setChain(CurDAG->getRoot())
658 .setCallee(CallingConv::C, Type::getVoidTy(*CurDAG->getContext()),
659 CurDAG->getExternalSymbol("__main", TLI->getPointerTy(DL)),
661 const TargetLowering &TLI = CurDAG->getTargetLoweringInfo();
662 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
663 CurDAG->setRoot(Result.second);
667 void X86DAGToDAGISel::EmitFunctionEntryCode() {
668 // If this is main, emit special code for main.
669 if (const Function *Fn = MF->getFunction())
670 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
671 emitSpecialCodeForMain();
674 static bool isDispSafeForFrameIndex(int64_t Val) {
675 // On 64-bit platforms, we can run into an issue where a frame index
676 // includes a displacement that, when added to the explicit displacement,
677 // will overflow the displacement field. Assuming that the frame index
678 // displacement fits into a 31-bit integer (which is only slightly more
679 // aggressive than the current fundamental assumption that it fits into
680 // a 32-bit integer), a 31-bit disp should always be safe.
681 return isInt<31>(Val);
684 bool X86DAGToDAGISel::foldOffsetIntoAddress(uint64_t Offset,
685 X86ISelAddressMode &AM) {
686 // Cannot combine ExternalSymbol displacements with integer offsets.
687 if (Offset != 0 && (AM.ES || AM.MCSym))
689 int64_t Val = AM.Disp + Offset;
690 CodeModel::Model M = TM.getCodeModel();
691 if (Subtarget->is64Bit()) {
692 if (!X86::isOffsetSuitableForCodeModel(Val, M,
693 AM.hasSymbolicDisplacement()))
695 // In addition to the checks required for a register base, check that
696 // we do not try to use an unsafe Disp with a frame index.
697 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
698 !isDispSafeForFrameIndex(Val))
706 bool X86DAGToDAGISel::matchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
707 SDValue Address = N->getOperand(1);
709 // load gs:0 -> GS segment register.
710 // load fs:0 -> FS segment register.
712 // This optimization is valid because the GNU TLS model defines that
713 // gs:0 (or fs:0 on X86-64) contains its own address.
714 // For more information see http://people.redhat.com/drepper/tls.pdf
715 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
716 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
717 Subtarget->isTargetLinux())
718 switch (N->getPointerInfo().getAddrSpace()) {
720 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
723 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
730 /// Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes into an addressing
731 /// mode. These wrap things that will resolve down into a symbol reference.
732 /// If no match is possible, this returns true, otherwise it returns false.
733 bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
734 // If the addressing mode already has a symbol as the displacement, we can
735 // never match another symbol.
736 if (AM.hasSymbolicDisplacement())
739 SDValue N0 = N.getOperand(0);
740 CodeModel::Model M = TM.getCodeModel();
742 // Handle X86-64 rip-relative addresses. We check this before checking direct
743 // folding because RIP is preferable to non-RIP accesses.
744 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
745 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
746 // they cannot be folded into immediate fields.
747 // FIXME: This can be improved for kernel and other models?
748 (M == CodeModel::Small || M == CodeModel::Kernel)) {
749 // Base and index reg must be 0 in order to use %rip as base.
750 if (AM.hasBaseOrIndexReg())
752 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
753 X86ISelAddressMode Backup = AM;
754 AM.GV = G->getGlobal();
755 AM.SymbolFlags = G->getTargetFlags();
756 if (foldOffsetIntoAddress(G->getOffset(), AM)) {
760 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
761 X86ISelAddressMode Backup = AM;
762 AM.CP = CP->getConstVal();
763 AM.Align = CP->getAlignment();
764 AM.SymbolFlags = CP->getTargetFlags();
765 if (foldOffsetIntoAddress(CP->getOffset(), AM)) {
769 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
770 AM.ES = S->getSymbol();
771 AM.SymbolFlags = S->getTargetFlags();
772 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
773 AM.MCSym = S->getMCSymbol();
774 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
775 AM.JT = J->getIndex();
776 AM.SymbolFlags = J->getTargetFlags();
777 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
778 X86ISelAddressMode Backup = AM;
779 AM.BlockAddr = BA->getBlockAddress();
780 AM.SymbolFlags = BA->getTargetFlags();
781 if (foldOffsetIntoAddress(BA->getOffset(), AM)) {
786 llvm_unreachable("Unhandled symbol reference node.");
788 if (N.getOpcode() == X86ISD::WrapperRIP)
789 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
793 // Handle the case when globals fit in our immediate field: This is true for
794 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
795 // mode, this only applies to a non-RIP-relative computation.
796 if (!Subtarget->is64Bit() ||
797 M == CodeModel::Small || M == CodeModel::Kernel) {
798 assert(N.getOpcode() != X86ISD::WrapperRIP &&
799 "RIP-relative addressing already handled");
800 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
801 AM.GV = G->getGlobal();
802 AM.Disp += G->getOffset();
803 AM.SymbolFlags = G->getTargetFlags();
804 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
805 AM.CP = CP->getConstVal();
806 AM.Align = CP->getAlignment();
807 AM.Disp += CP->getOffset();
808 AM.SymbolFlags = CP->getTargetFlags();
809 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
810 AM.ES = S->getSymbol();
811 AM.SymbolFlags = S->getTargetFlags();
812 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
813 AM.MCSym = S->getMCSymbol();
814 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
815 AM.JT = J->getIndex();
816 AM.SymbolFlags = J->getTargetFlags();
817 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
818 AM.BlockAddr = BA->getBlockAddress();
819 AM.Disp += BA->getOffset();
820 AM.SymbolFlags = BA->getTargetFlags();
822 llvm_unreachable("Unhandled symbol reference node.");
829 /// Add the specified node to the specified addressing mode, returning true if
830 /// it cannot be done. This just pattern matches for the addressing mode.
831 bool X86DAGToDAGISel::matchAddress(SDValue N, X86ISelAddressMode &AM) {
832 if (matchAddressRecursively(N, AM, 0))
835 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
836 // a smaller encoding and avoids a scaled-index.
838 AM.BaseType == X86ISelAddressMode::RegBase &&
839 AM.Base_Reg.getNode() == nullptr) {
840 AM.Base_Reg = AM.IndexReg;
844 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
845 // because it has a smaller encoding.
846 // TODO: Which other code models can use this?
847 if (TM.getCodeModel() == CodeModel::Small &&
848 Subtarget->is64Bit() &&
850 AM.BaseType == X86ISelAddressMode::RegBase &&
851 AM.Base_Reg.getNode() == nullptr &&
852 AM.IndexReg.getNode() == nullptr &&
853 AM.SymbolFlags == X86II::MO_NO_FLAG &&
854 AM.hasSymbolicDisplacement())
855 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
860 bool X86DAGToDAGISel::matchAdd(SDValue N, X86ISelAddressMode &AM,
862 // Add an artificial use to this node so that we can keep track of
863 // it if it gets CSE'd with a different node.
864 HandleSDNode Handle(N);
866 X86ISelAddressMode Backup = AM;
867 if (!matchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
868 !matchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
872 // Try again after commuting the operands.
873 if (!matchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1) &&
874 !matchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
878 // If we couldn't fold both operands into the address at the same time,
879 // see if we can just put each operand into a register and fold at least
881 if (AM.BaseType == X86ISelAddressMode::RegBase &&
882 !AM.Base_Reg.getNode() &&
883 !AM.IndexReg.getNode()) {
884 N = Handle.getValue();
885 AM.Base_Reg = N.getOperand(0);
886 AM.IndexReg = N.getOperand(1);
890 N = Handle.getValue();
894 // Insert a node into the DAG at least before the Pos node's position. This
895 // will reposition the node as needed, and will assign it a node ID that is <=
896 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
897 // IDs! The selection DAG must no longer depend on their uniqueness when this
899 static void insertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
900 if (N.getNode()->getNodeId() == -1 ||
901 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
902 DAG.RepositionNode(Pos.getNode()->getIterator(), N.getNode());
903 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
907 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
908 // safe. This allows us to convert the shift and and into an h-register
909 // extract and a scaled index. Returns false if the simplification is
911 static bool foldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
913 SDValue Shift, SDValue X,
914 X86ISelAddressMode &AM) {
915 if (Shift.getOpcode() != ISD::SRL ||
916 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
920 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
921 if (ScaleLog <= 0 || ScaleLog >= 4 ||
922 Mask != (0xffu << ScaleLog))
925 MVT VT = N.getSimpleValueType();
927 SDValue Eight = DAG.getConstant(8, DL, MVT::i8);
928 SDValue NewMask = DAG.getConstant(0xff, DL, VT);
929 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
930 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
931 SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8);
932 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
934 // Insert the new nodes into the topological ordering. We must do this in
935 // a valid topological ordering as nothing is going to go back and re-sort
936 // these nodes. We continually insert before 'N' in sequence as this is
937 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
938 // hierarchy left to express.
939 insertDAGNode(DAG, N, Eight);
940 insertDAGNode(DAG, N, Srl);
941 insertDAGNode(DAG, N, NewMask);
942 insertDAGNode(DAG, N, And);
943 insertDAGNode(DAG, N, ShlCount);
944 insertDAGNode(DAG, N, Shl);
945 DAG.ReplaceAllUsesWith(N, Shl);
947 AM.Scale = (1 << ScaleLog);
951 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
952 // allows us to fold the shift into this addressing mode. Returns false if the
953 // transform succeeded.
954 static bool foldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
956 SDValue Shift, SDValue X,
957 X86ISelAddressMode &AM) {
958 if (Shift.getOpcode() != ISD::SHL ||
959 !isa<ConstantSDNode>(Shift.getOperand(1)))
962 // Not likely to be profitable if either the AND or SHIFT node has more
963 // than one use (unless all uses are for address computation). Besides,
964 // isel mechanism requires their node ids to be reused.
965 if (!N.hasOneUse() || !Shift.hasOneUse())
968 // Verify that the shift amount is something we can fold.
969 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
970 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
973 MVT VT = N.getSimpleValueType();
975 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
976 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
977 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
979 // Insert the new nodes into the topological ordering. We must do this in
980 // a valid topological ordering as nothing is going to go back and re-sort
981 // these nodes. We continually insert before 'N' in sequence as this is
982 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
983 // hierarchy left to express.
984 insertDAGNode(DAG, N, NewMask);
985 insertDAGNode(DAG, N, NewAnd);
986 insertDAGNode(DAG, N, NewShift);
987 DAG.ReplaceAllUsesWith(N, NewShift);
989 AM.Scale = 1 << ShiftAmt;
990 AM.IndexReg = NewAnd;
994 // Implement some heroics to detect shifts of masked values where the mask can
995 // be replaced by extending the shift and undoing that in the addressing mode
996 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
997 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
998 // the addressing mode. This results in code such as:
1000 // int f(short *y, int *lookup_table) {
1002 // return *y + lookup_table[*y >> 11];
1006 // movzwl (%rdi), %eax
1009 // addl (%rsi,%rcx,4), %eax
1012 // movzwl (%rdi), %eax
1016 // addl (%rsi,%rcx), %eax
1018 // Note that this function assumes the mask is provided as a mask *after* the
1019 // value is shifted. The input chain may or may not match that, but computing
1020 // such a mask is trivial.
1021 static bool foldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
1023 SDValue Shift, SDValue X,
1024 X86ISelAddressMode &AM) {
1025 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
1026 !isa<ConstantSDNode>(Shift.getOperand(1)))
1029 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
1030 unsigned MaskLZ = countLeadingZeros(Mask);
1031 unsigned MaskTZ = countTrailingZeros(Mask);
1033 // The amount of shift we're trying to fit into the addressing mode is taken
1034 // from the trailing zeros of the mask.
1035 unsigned AMShiftAmt = MaskTZ;
1037 // There is nothing we can do here unless the mask is removing some bits.
1038 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
1039 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
1041 // We also need to ensure that mask is a continuous run of bits.
1042 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
1044 // Scale the leading zero count down based on the actual size of the value.
1045 // Also scale it down based on the size of the shift.
1046 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
1048 // The final check is to ensure that any masked out high bits of X are
1049 // already known to be zero. Otherwise, the mask has a semantic impact
1050 // other than masking out a couple of low bits. Unfortunately, because of
1051 // the mask, zero extensions will be removed from operands in some cases.
1052 // This code works extra hard to look through extensions because we can
1053 // replace them with zero extensions cheaply if necessary.
1054 bool ReplacingAnyExtend = false;
1055 if (X.getOpcode() == ISD::ANY_EXTEND) {
1056 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
1057 X.getOperand(0).getSimpleValueType().getSizeInBits();
1058 // Assume that we'll replace the any-extend with a zero-extend, and
1059 // narrow the search to the extended value.
1060 X = X.getOperand(0);
1061 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
1062 ReplacingAnyExtend = true;
1064 APInt MaskedHighBits =
1065 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
1066 APInt KnownZero, KnownOne;
1067 DAG.computeKnownBits(X, KnownZero, KnownOne);
1068 if (MaskedHighBits != KnownZero) return true;
1070 // We've identified a pattern that can be transformed into a single shift
1071 // and an addressing mode. Make it so.
1072 MVT VT = N.getSimpleValueType();
1073 if (ReplacingAnyExtend) {
1074 assert(X.getValueType() != VT);
1075 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
1076 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
1077 insertDAGNode(DAG, N, NewX);
1081 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
1082 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
1083 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);
1084 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
1086 // Insert the new nodes into the topological ordering. We must do this in
1087 // a valid topological ordering as nothing is going to go back and re-sort
1088 // these nodes. We continually insert before 'N' in sequence as this is
1089 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
1090 // hierarchy left to express.
1091 insertDAGNode(DAG, N, NewSRLAmt);
1092 insertDAGNode(DAG, N, NewSRL);
1093 insertDAGNode(DAG, N, NewSHLAmt);
1094 insertDAGNode(DAG, N, NewSHL);
1095 DAG.ReplaceAllUsesWith(N, NewSHL);
1097 AM.Scale = 1 << AMShiftAmt;
1098 AM.IndexReg = NewSRL;
1102 bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
1106 dbgs() << "MatchAddress: ";
1111 return matchAddressBase(N, AM);
1113 // If this is already a %rip relative address, we can only merge immediates
1114 // into it. Instead of handling this in every case, we handle it here.
1115 // RIP relative addressing: %rip + 32-bit displacement!
1116 if (AM.isRIPRelative()) {
1117 // FIXME: JumpTable and ExternalSymbol address currently don't like
1118 // displacements. It isn't very important, but this should be fixed for
1120 if (!(AM.ES || AM.MCSym) && AM.JT != -1)
1123 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
1124 if (!foldOffsetIntoAddress(Cst->getSExtValue(), AM))
1129 switch (N.getOpcode()) {
1131 case ISD::LOCAL_RECOVER: {
1132 if (!AM.hasSymbolicDisplacement() && AM.Disp == 0)
1133 if (const auto *ESNode = dyn_cast<MCSymbolSDNode>(N.getOperand(0))) {
1134 // Use the symbol and don't prefix it.
1135 AM.MCSym = ESNode->getMCSymbol();
1140 case ISD::Constant: {
1141 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1142 if (!foldOffsetIntoAddress(Val, AM))
1147 case X86ISD::Wrapper:
1148 case X86ISD::WrapperRIP:
1149 if (!matchWrapper(N, AM))
1154 if (!matchLoadInAddress(cast<LoadSDNode>(N), AM))
1158 case ISD::FrameIndex:
1159 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1160 AM.Base_Reg.getNode() == nullptr &&
1161 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1162 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1163 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1169 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1173 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1174 unsigned Val = CN->getZExtValue();
1175 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1176 // that the base operand remains free for further matching. If
1177 // the base doesn't end up getting used, a post-processing step
1178 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1179 if (Val == 1 || Val == 2 || Val == 3) {
1180 AM.Scale = 1 << Val;
1181 SDValue ShVal = N.getNode()->getOperand(0);
1183 // Okay, we know that we have a scale by now. However, if the scaled
1184 // value is an add of something and a constant, we can fold the
1185 // constant into the disp field here.
1186 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1187 AM.IndexReg = ShVal.getNode()->getOperand(0);
1188 ConstantSDNode *AddVal =
1189 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1190 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1191 if (!foldOffsetIntoAddress(Disp, AM))
1195 AM.IndexReg = ShVal;
1202 // Scale must not be used already.
1203 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1205 SDValue And = N.getOperand(0);
1206 if (And.getOpcode() != ISD::AND) break;
1207 SDValue X = And.getOperand(0);
1209 // We only handle up to 64-bit values here as those are what matter for
1210 // addressing mode optimizations.
1211 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1213 // The mask used for the transform is expected to be post-shift, but we
1214 // found the shift first so just apply the shift to the mask before passing
1216 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1217 !isa<ConstantSDNode>(And.getOperand(1)))
1219 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1221 // Try to fold the mask and shift into the scale, and return false if we
1223 if (!foldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1228 case ISD::SMUL_LOHI:
1229 case ISD::UMUL_LOHI:
1230 // A mul_lohi where we need the low part can be folded as a plain multiply.
1231 if (N.getResNo() != 0) break;
1234 case X86ISD::MUL_IMM:
1235 // X*[3,5,9] -> X+X*[2,4,8]
1236 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1237 AM.Base_Reg.getNode() == nullptr &&
1238 AM.IndexReg.getNode() == nullptr) {
1240 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1241 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1242 CN->getZExtValue() == 9) {
1243 AM.Scale = unsigned(CN->getZExtValue())-1;
1245 SDValue MulVal = N.getNode()->getOperand(0);
1248 // Okay, we know that we have a scale by now. However, if the scaled
1249 // value is an add of something and a constant, we can fold the
1250 // constant into the disp field here.
1251 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1252 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1253 Reg = MulVal.getNode()->getOperand(0);
1254 ConstantSDNode *AddVal =
1255 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1256 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1257 if (foldOffsetIntoAddress(Disp, AM))
1258 Reg = N.getNode()->getOperand(0);
1260 Reg = N.getNode()->getOperand(0);
1263 AM.IndexReg = AM.Base_Reg = Reg;
1270 // Given A-B, if A can be completely folded into the address and
1271 // the index field with the index field unused, use -B as the index.
1272 // This is a win if a has multiple parts that can be folded into
1273 // the address. Also, this saves a mov if the base register has
1274 // other uses, since it avoids a two-address sub instruction, however
1275 // it costs an additional mov if the index register has other uses.
1277 // Add an artificial use to this node so that we can keep track of
1278 // it if it gets CSE'd with a different node.
1279 HandleSDNode Handle(N);
1281 // Test if the LHS of the sub can be folded.
1282 X86ISelAddressMode Backup = AM;
1283 if (matchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1287 // Test if the index field is free for use.
1288 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1294 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1295 // If the RHS involves a register with multiple uses, this
1296 // transformation incurs an extra mov, due to the neg instruction
1297 // clobbering its operand.
1298 if (!RHS.getNode()->hasOneUse() ||
1299 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1300 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1301 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1302 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1303 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1305 // If the base is a register with multiple uses, this
1306 // transformation may save a mov.
1307 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1308 AM.Base_Reg.getNode() &&
1309 !AM.Base_Reg.getNode()->hasOneUse()) ||
1310 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1312 // If the folded LHS was interesting, this transformation saves
1313 // address arithmetic.
1314 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1315 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1316 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1318 // If it doesn't look like it may be an overall win, don't do it.
1324 // Ok, the transformation is legal and appears profitable. Go for it.
1325 SDValue Zero = CurDAG->getConstant(0, dl, N.getValueType());
1326 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1330 // Insert the new nodes into the topological ordering.
1331 insertDAGNode(*CurDAG, N, Zero);
1332 insertDAGNode(*CurDAG, N, Neg);
1337 if (!matchAdd(N, AM, Depth))
1342 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1343 if (CurDAG->isBaseWithConstantOffset(N)) {
1344 X86ISelAddressMode Backup = AM;
1345 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1347 // Start with the LHS as an addr mode.
1348 if (!matchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1349 !foldOffsetIntoAddress(CN->getSExtValue(), AM))
1356 // Perform some heroic transforms on an and of a constant-count shift
1357 // with a constant to enable use of the scaled offset field.
1359 // Scale must not be used already.
1360 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1362 SDValue Shift = N.getOperand(0);
1363 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1364 SDValue X = Shift.getOperand(0);
1366 // We only handle up to 64-bit values here as those are what matter for
1367 // addressing mode optimizations.
1368 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1370 if (!isa<ConstantSDNode>(N.getOperand(1)))
1372 uint64_t Mask = N.getConstantOperandVal(1);
1374 // Try to fold the mask and shift into an extract and scale.
1375 if (!foldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1378 // Try to fold the mask and shift directly into the scale.
1379 if (!foldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1382 // Try to swap the mask and shift to place shifts which can be done as
1383 // a scale on the outside of the mask.
1384 if (!foldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1390 return matchAddressBase(N, AM);
1393 /// Helper for MatchAddress. Add the specified node to the
1394 /// specified addressing mode without any further recursion.
1395 bool X86DAGToDAGISel::matchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1396 // Is the base register already occupied?
1397 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1398 // If so, check to see if the scale index register is set.
1399 if (!AM.IndexReg.getNode()) {
1405 // Otherwise, we cannot select it.
1409 // Default, generate it as a register.
1410 AM.BaseType = X86ISelAddressMode::RegBase;
1415 bool X86DAGToDAGISel::selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
1416 SDValue &Scale, SDValue &Index,
1417 SDValue &Disp, SDValue &Segment) {
1419 MaskedGatherScatterSDNode *Mgs = dyn_cast<MaskedGatherScatterSDNode>(Parent);
1422 X86ISelAddressMode AM;
1423 unsigned AddrSpace = Mgs->getPointerInfo().getAddrSpace();
1424 // AddrSpace 256 -> GS, 257 -> FS.
1425 if (AddrSpace == 256)
1426 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1427 if (AddrSpace == 257)
1428 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1431 Base = Mgs->getBasePtr();
1432 Index = Mgs->getIndex();
1433 unsigned ScalarSize = Mgs->getValue().getValueType().getScalarSizeInBits();
1434 Scale = getI8Imm(ScalarSize/8, DL);
1436 // If Base is 0, the whole address is in index and the Scale is 1
1437 if (isa<ConstantSDNode>(Base)) {
1438 assert(cast<ConstantSDNode>(Base)->isNullValue() &&
1439 "Unexpected base in gather/scatter");
1440 Scale = getI8Imm(1, DL);
1441 Base = CurDAG->getRegister(0, MVT::i32);
1443 if (AM.Segment.getNode())
1444 Segment = AM.Segment;
1446 Segment = CurDAG->getRegister(0, MVT::i32);
1447 Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1451 /// Returns true if it is able to pattern match an addressing mode.
1452 /// It returns the operands which make up the maximal addressing mode it can
1453 /// match by reference.
1455 /// Parent is the parent node of the addr operand that is being matched. It
1456 /// is always a load, store, atomic node, or null. It is only null when
1457 /// checking memory operands for inline asm nodes.
1458 bool X86DAGToDAGISel::selectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1459 SDValue &Scale, SDValue &Index,
1460 SDValue &Disp, SDValue &Segment) {
1461 X86ISelAddressMode AM;
1464 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1465 // that are not a MemSDNode, and thus don't have proper addrspace info.
1466 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1467 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1468 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1469 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1470 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1471 unsigned AddrSpace =
1472 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1473 // AddrSpace 256 -> GS, 257 -> FS.
1474 if (AddrSpace == 256)
1475 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1476 if (AddrSpace == 257)
1477 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1480 if (matchAddress(N, AM))
1483 MVT VT = N.getSimpleValueType();
1484 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1485 if (!AM.Base_Reg.getNode())
1486 AM.Base_Reg = CurDAG->getRegister(0, VT);
1489 if (!AM.IndexReg.getNode())
1490 AM.IndexReg = CurDAG->getRegister(0, VT);
1492 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1496 /// Match a scalar SSE load. In particular, we want to match a load whose top
1497 /// elements are either undef or zeros. The load flavor is derived from the
1498 /// type of N, which is either v4f32 or v2f64.
1501 /// PatternChainNode: this is the matched node that has a chain input and
1503 bool X86DAGToDAGISel::selectScalarSSELoad(SDNode *Root,
1504 SDValue N, SDValue &Base,
1505 SDValue &Scale, SDValue &Index,
1506 SDValue &Disp, SDValue &Segment,
1507 SDValue &PatternNodeWithChain) {
1508 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1509 PatternNodeWithChain = N.getOperand(0);
1510 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1511 PatternNodeWithChain.hasOneUse() &&
1512 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1513 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1514 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1515 if (!selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1521 // Also handle the case where we explicitly require zeros in the top
1522 // elements. This is a vector shuffle from the zero vector.
1523 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1524 // Check to see if the top elements are all zeros (or bitcast of zeros).
1525 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1526 N.getOperand(0).getNode()->hasOneUse() &&
1527 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1528 N.getOperand(0).getOperand(0).hasOneUse() &&
1529 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1530 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1531 // Okay, this is a zero extending load. Fold it.
1532 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1533 if (!selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1535 PatternNodeWithChain = SDValue(LD, 0);
1542 bool X86DAGToDAGISel::selectMOV64Imm32(SDValue N, SDValue &Imm) {
1543 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1544 uint64_t ImmVal = CN->getZExtValue();
1545 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1548 Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64);
1552 // In static codegen with small code model, we can get the address of a label
1553 // into a register with 'movl'. TableGen has already made sure we're looking
1554 // at a label of some kind.
1555 assert(N->getOpcode() == X86ISD::Wrapper &&
1556 "Unexpected node type for MOV32ri64");
1557 N = N.getOperand(0);
1559 if (N->getOpcode() != ISD::TargetConstantPool &&
1560 N->getOpcode() != ISD::TargetJumpTable &&
1561 N->getOpcode() != ISD::TargetGlobalAddress &&
1562 N->getOpcode() != ISD::TargetExternalSymbol &&
1563 N->getOpcode() != ISD::MCSymbol &&
1564 N->getOpcode() != ISD::TargetBlockAddress)
1568 return TM.getCodeModel() == CodeModel::Small;
1571 bool X86DAGToDAGISel::selectLEA64_32Addr(SDValue N, SDValue &Base,
1572 SDValue &Scale, SDValue &Index,
1573 SDValue &Disp, SDValue &Segment) {
1574 if (!selectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1578 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1579 if (RN && RN->getReg() == 0)
1580 Base = CurDAG->getRegister(0, MVT::i64);
1581 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1582 // Base could already be %rip, particularly in the x32 ABI.
1583 Base = SDValue(CurDAG->getMachineNode(
1584 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1585 CurDAG->getTargetConstant(0, DL, MVT::i64),
1587 CurDAG->getTargetConstant(X86::sub_32bit, DL, MVT::i32)),
1591 RN = dyn_cast<RegisterSDNode>(Index);
1592 if (RN && RN->getReg() == 0)
1593 Index = CurDAG->getRegister(0, MVT::i64);
1595 assert(Index.getValueType() == MVT::i32 &&
1596 "Expect to be extending 32-bit registers for use in LEA");
1597 Index = SDValue(CurDAG->getMachineNode(
1598 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1599 CurDAG->getTargetConstant(0, DL, MVT::i64),
1601 CurDAG->getTargetConstant(X86::sub_32bit, DL,
1609 /// Calls SelectAddr and determines if the maximal addressing
1610 /// mode it matches can be cost effectively emitted as an LEA instruction.
1611 bool X86DAGToDAGISel::selectLEAAddr(SDValue N,
1612 SDValue &Base, SDValue &Scale,
1613 SDValue &Index, SDValue &Disp,
1615 X86ISelAddressMode AM;
1617 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1619 SDValue Copy = AM.Segment;
1620 SDValue T = CurDAG->getRegister(0, MVT::i32);
1622 if (matchAddress(N, AM))
1624 assert (T == AM.Segment);
1627 MVT VT = N.getSimpleValueType();
1628 unsigned Complexity = 0;
1629 if (AM.BaseType == X86ISelAddressMode::RegBase)
1630 if (AM.Base_Reg.getNode())
1633 AM.Base_Reg = CurDAG->getRegister(0, VT);
1634 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1637 if (AM.IndexReg.getNode())
1640 AM.IndexReg = CurDAG->getRegister(0, VT);
1642 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1647 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1648 // to a LEA. This is determined with some experimentation but is by no means
1649 // optimal (especially for code size consideration). LEA is nice because of
1650 // its three-address nature. Tweak the cost function again when we can run
1651 // convertToThreeAddress() at register allocation time.
1652 if (AM.hasSymbolicDisplacement()) {
1653 // For X86-64, always use LEA to materialize RIP-relative addresses.
1654 if (Subtarget->is64Bit())
1660 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1663 // If it isn't worth using an LEA, reject it.
1664 if (Complexity <= 2)
1667 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1671 /// This is only run on TargetGlobalTLSAddress nodes.
1672 bool X86DAGToDAGISel::selectTLSADDRAddr(SDValue N, SDValue &Base,
1673 SDValue &Scale, SDValue &Index,
1674 SDValue &Disp, SDValue &Segment) {
1675 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1676 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1678 X86ISelAddressMode AM;
1679 AM.GV = GA->getGlobal();
1680 AM.Disp += GA->getOffset();
1681 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1682 AM.SymbolFlags = GA->getTargetFlags();
1684 if (N.getValueType() == MVT::i32) {
1686 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1688 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1691 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1696 bool X86DAGToDAGISel::tryFoldLoad(SDNode *P, SDValue N,
1697 SDValue &Base, SDValue &Scale,
1698 SDValue &Index, SDValue &Disp,
1700 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1701 !IsProfitableToFold(N, P, P) ||
1702 !IsLegalToFold(N, P, P, OptLevel))
1705 return selectAddr(N.getNode(),
1706 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1709 /// Return an SDNode that returns the value of the global base register.
1710 /// Output instructions required to initialize the global base register,
1712 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1713 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1714 auto &DL = MF->getDataLayout();
1715 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy(DL)).getNode();
1718 /// Atomic opcode table
1746 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1757 X86::LOCK_ADD64mi32,
1770 X86::LOCK_SUB64mi32,
1822 X86::LOCK_AND64mi32,
1835 X86::LOCK_XOR64mi32,
1840 // Return the target constant operand for atomic-load-op and do simple
1841 // translations, such as from atomic-load-add to lock-sub. The return value is
1842 // one of the following 3 cases:
1843 // + target-constant, the operand could be supported as a target constant.
1844 // + empty, the operand is not needed any more with the new op selected.
1845 // + non-empty, otherwise.
1846 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1848 enum AtomicOpc &Op, MVT NVT,
1850 const X86Subtarget *Subtarget) {
1851 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1852 int64_t CNVal = CN->getSExtValue();
1853 // Quit if not 32-bit imm.
1854 if ((int32_t)CNVal != CNVal)
1856 // Quit if INT32_MIN: it would be negated as it is negative and overflow,
1857 // producing an immediate that does not fit in the 32 bits available for
1858 // an immediate operand to sub. However, it still fits in 32 bits for the
1859 // add (since it is not negated) so we can return target-constant.
1860 if (CNVal == INT32_MIN)
1861 return CurDAG->getTargetConstant(CNVal, dl, NVT);
1862 // For atomic-load-add, we could do some optimizations.
1864 // Translate to INC/DEC if ADD by 1 or -1.
1865 if (((CNVal == 1) || (CNVal == -1)) && !Subtarget->slowIncDec()) {
1866 Op = (CNVal == 1) ? INC : DEC;
1867 // No more constant operand after being translated into INC/DEC.
1870 // Translate to SUB if ADD by negative value.
1876 return CurDAG->getTargetConstant(CNVal, dl, NVT);
1879 // If the value operand is single-used, try to optimize it.
1880 if (Op == ADD && Val.hasOneUse()) {
1881 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1882 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1884 return Val.getOperand(1);
1886 // A special case for i16, which needs truncating as, in most cases, it's
1887 // promoted to i32. We will translate
1888 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1889 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1890 Val.getOperand(0).getOpcode() == ISD::SUB &&
1891 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1893 Val = Val.getOperand(0);
1894 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1902 SDNode *X86DAGToDAGISel::selectAtomicLoadArith(SDNode *Node, MVT NVT) {
1903 if (Node->hasAnyUseOfValue(0))
1908 // Optimize common patterns for __sync_or_and_fetch and similar arith
1909 // operations where the result is not used. This allows us to use the "lock"
1910 // version of the arithmetic instruction.
1911 SDValue Chain = Node->getOperand(0);
1912 SDValue Ptr = Node->getOperand(1);
1913 SDValue Val = Node->getOperand(2);
1914 SDValue Base, Scale, Index, Disp, Segment;
1915 if (!selectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
1918 // Which index into the table.
1920 switch (Node->getOpcode()) {
1923 case ISD::ATOMIC_LOAD_OR:
1926 case ISD::ATOMIC_LOAD_AND:
1929 case ISD::ATOMIC_LOAD_XOR:
1932 case ISD::ATOMIC_LOAD_ADD:
1937 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val, Subtarget);
1938 bool isUnOp = !Val.getNode();
1939 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1942 switch (NVT.SimpleTy) {
1943 default: return nullptr;
1946 Opc = AtomicOpcTbl[Op][ConstantI8];
1948 Opc = AtomicOpcTbl[Op][I8];
1952 if (immSext8(Val.getNode()))
1953 Opc = AtomicOpcTbl[Op][SextConstantI16];
1955 Opc = AtomicOpcTbl[Op][ConstantI16];
1957 Opc = AtomicOpcTbl[Op][I16];
1961 if (immSext8(Val.getNode()))
1962 Opc = AtomicOpcTbl[Op][SextConstantI32];
1964 Opc = AtomicOpcTbl[Op][ConstantI32];
1966 Opc = AtomicOpcTbl[Op][I32];
1970 if (immSext8(Val.getNode()))
1971 Opc = AtomicOpcTbl[Op][SextConstantI64];
1972 else if (i64immSExt32(Val.getNode()))
1973 Opc = AtomicOpcTbl[Op][ConstantI64];
1975 llvm_unreachable("True 64 bits constant in SelectAtomicLoadArith");
1977 Opc = AtomicOpcTbl[Op][I64];
1981 assert(Opc != 0 && "Invalid arith lock transform!");
1983 // Building the new node.
1986 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1987 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1989 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1990 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1993 // Copying the MachineMemOperand.
1994 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1995 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1996 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1998 // We need to have two outputs as that is what the original instruction had.
1999 // So we add a dummy, undefined output. This is safe as we checked first
2000 // that no-one uses our output anyway.
2001 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
2003 SDValue RetVals[] = { Undef, Ret };
2004 return CurDAG->getMergeValues(RetVals, dl).getNode();
2007 /// Test whether the given X86ISD::CMP node has any uses which require the SF
2008 /// or OF bits to be accurate.
2009 static bool hasNoSignedComparisonUses(SDNode *N) {
2010 // Examine each user of the node.
2011 for (SDNode::use_iterator UI = N->use_begin(),
2012 UE = N->use_end(); UI != UE; ++UI) {
2013 // Only examine CopyToReg uses.
2014 if (UI->getOpcode() != ISD::CopyToReg)
2016 // Only examine CopyToReg uses that copy to EFLAGS.
2017 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
2020 // Examine each user of the CopyToReg use.
2021 for (SDNode::use_iterator FlagUI = UI->use_begin(),
2022 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
2023 // Only examine the Flag result.
2024 if (FlagUI.getUse().getResNo() != 1) continue;
2025 // Anything unusual: assume conservatively.
2026 if (!FlagUI->isMachineOpcode()) return false;
2027 // Examine the opcode of the user.
2028 switch (FlagUI->getMachineOpcode()) {
2029 // These comparisons don't treat the most significant bit specially.
2030 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
2031 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
2032 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
2033 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
2034 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
2035 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
2036 case X86::CMOVA16rr: case X86::CMOVA16rm:
2037 case X86::CMOVA32rr: case X86::CMOVA32rm:
2038 case X86::CMOVA64rr: case X86::CMOVA64rm:
2039 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
2040 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
2041 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
2042 case X86::CMOVB16rr: case X86::CMOVB16rm:
2043 case X86::CMOVB32rr: case X86::CMOVB32rm:
2044 case X86::CMOVB64rr: case X86::CMOVB64rm:
2045 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
2046 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
2047 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
2048 case X86::CMOVE16rr: case X86::CMOVE16rm:
2049 case X86::CMOVE32rr: case X86::CMOVE32rm:
2050 case X86::CMOVE64rr: case X86::CMOVE64rm:
2051 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
2052 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
2053 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
2054 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
2055 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
2056 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
2057 case X86::CMOVP16rr: case X86::CMOVP16rm:
2058 case X86::CMOVP32rr: case X86::CMOVP32rm:
2059 case X86::CMOVP64rr: case X86::CMOVP64rm:
2061 // Anything else: assume conservatively.
2062 default: return false;
2069 /// Check whether or not the chain ending in StoreNode is suitable for doing
2070 /// the {load; increment or decrement; store} to modify transformation.
2071 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
2072 SDValue StoredVal, SelectionDAG *CurDAG,
2073 LoadSDNode* &LoadNode, SDValue &InputChain) {
2075 // is the value stored the result of a DEC or INC?
2076 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
2078 // is the stored value result 0 of the load?
2079 if (StoredVal.getResNo() != 0) return false;
2081 // are there other uses of the loaded value than the inc or dec?
2082 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
2084 // is the store non-extending and non-indexed?
2085 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
2088 SDValue Load = StoredVal->getOperand(0);
2089 // Is the stored value a non-extending and non-indexed load?
2090 if (!ISD::isNormalLoad(Load.getNode())) return false;
2092 // Return LoadNode by reference.
2093 LoadNode = cast<LoadSDNode>(Load);
2094 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
2095 EVT LdVT = LoadNode->getMemoryVT();
2096 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
2100 // Is store the only read of the loaded value?
2101 if (!Load.hasOneUse())
2104 // Is the address of the store the same as the load?
2105 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
2106 LoadNode->getOffset() != StoreNode->getOffset())
2109 // Check if the chain is produced by the load or is a TokenFactor with
2110 // the load output chain as an operand. Return InputChain by reference.
2111 SDValue Chain = StoreNode->getChain();
2113 bool ChainCheck = false;
2114 if (Chain == Load.getValue(1)) {
2116 InputChain = LoadNode->getChain();
2117 } else if (Chain.getOpcode() == ISD::TokenFactor) {
2118 SmallVector<SDValue, 4> ChainOps;
2119 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
2120 SDValue Op = Chain.getOperand(i);
2121 if (Op == Load.getValue(1)) {
2126 // Make sure using Op as part of the chain would not cause a cycle here.
2127 // In theory, we could check whether the chain node is a predecessor of
2128 // the load. But that can be very expensive. Instead visit the uses and
2129 // make sure they all have smaller node id than the load.
2130 int LoadId = LoadNode->getNodeId();
2131 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
2132 UE = UI->use_end(); UI != UE; ++UI) {
2133 if (UI.getUse().getResNo() != 0)
2135 if (UI->getNodeId() > LoadId)
2139 ChainOps.push_back(Op);
2143 // Make a new TokenFactor with all the other input chains except
2145 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2146 MVT::Other, ChainOps);
2154 /// Get the appropriate X86 opcode for an in-memory increment or decrement.
2155 /// Opc should be X86ISD::DEC or X86ISD::INC.
2156 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2157 if (Opc == X86ISD::DEC) {
2158 if (LdVT == MVT::i64) return X86::DEC64m;
2159 if (LdVT == MVT::i32) return X86::DEC32m;
2160 if (LdVT == MVT::i16) return X86::DEC16m;
2161 if (LdVT == MVT::i8) return X86::DEC8m;
2163 assert(Opc == X86ISD::INC && "unrecognized opcode");
2164 if (LdVT == MVT::i64) return X86::INC64m;
2165 if (LdVT == MVT::i32) return X86::INC32m;
2166 if (LdVT == MVT::i16) return X86::INC16m;
2167 if (LdVT == MVT::i8) return X86::INC8m;
2169 llvm_unreachable("unrecognized size for LdVT");
2172 /// Customized ISel for GATHER operations.
2173 SDNode *X86DAGToDAGISel::selectGather(SDNode *Node, unsigned Opc) {
2174 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2175 SDValue Chain = Node->getOperand(0);
2176 SDValue VSrc = Node->getOperand(2);
2177 SDValue Base = Node->getOperand(3);
2178 SDValue VIdx = Node->getOperand(4);
2179 SDValue VMask = Node->getOperand(5);
2180 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2184 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2189 // Memory Operands: Base, Scale, Index, Disp, Segment
2190 SDValue Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
2191 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2192 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue(), DL), VIdx,
2193 Disp, Segment, VMask, Chain};
2194 SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2195 // Node has 2 outputs: VDst and MVT::Other.
2196 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2197 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2199 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2200 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2204 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2205 MVT NVT = Node->getSimpleValueType(0);
2207 unsigned Opcode = Node->getOpcode();
2210 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2212 if (Node->isMachineOpcode()) {
2213 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2214 Node->setNodeId(-1);
2215 return nullptr; // Already selected.
2221 if (Subtarget->isTargetNaCl())
2222 // NaCl has its own pass where jmp %r32 are converted to jmp %r64. We
2223 // leave the instruction alone.
2225 if (Subtarget->isTarget64BitILP32()) {
2226 // Converts a 32-bit register to a 64-bit, zero-extended version of
2227 // it. This is needed because x86-64 can do many things, but jmp %r32
2228 // ain't one of them.
2229 const SDValue &Target = Node->getOperand(1);
2230 assert(Target.getSimpleValueType() == llvm::MVT::i32);
2231 SDValue ZextTarget = CurDAG->getZExtOrTrunc(Target, dl, EVT(MVT::i64));
2232 SDValue Brind = CurDAG->getNode(ISD::BRIND, dl, MVT::Other,
2233 Node->getOperand(0), ZextTarget);
2234 ReplaceUses(SDValue(Node, 0), Brind);
2235 SelectCode(ZextTarget.getNode());
2236 SelectCode(Brind.getNode());
2241 case ISD::INTRINSIC_W_CHAIN: {
2242 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2245 case Intrinsic::x86_avx2_gather_d_pd:
2246 case Intrinsic::x86_avx2_gather_d_pd_256:
2247 case Intrinsic::x86_avx2_gather_q_pd:
2248 case Intrinsic::x86_avx2_gather_q_pd_256:
2249 case Intrinsic::x86_avx2_gather_d_ps:
2250 case Intrinsic::x86_avx2_gather_d_ps_256:
2251 case Intrinsic::x86_avx2_gather_q_ps:
2252 case Intrinsic::x86_avx2_gather_q_ps_256:
2253 case Intrinsic::x86_avx2_gather_d_q:
2254 case Intrinsic::x86_avx2_gather_d_q_256:
2255 case Intrinsic::x86_avx2_gather_q_q:
2256 case Intrinsic::x86_avx2_gather_q_q_256:
2257 case Intrinsic::x86_avx2_gather_d_d:
2258 case Intrinsic::x86_avx2_gather_d_d_256:
2259 case Intrinsic::x86_avx2_gather_q_d:
2260 case Intrinsic::x86_avx2_gather_q_d_256: {
2261 if (!Subtarget->hasAVX2())
2265 default: llvm_unreachable("Impossible intrinsic");
2266 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2267 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2268 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2269 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2270 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2271 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2272 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2273 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2274 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2275 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2276 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2277 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2278 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2279 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2280 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2281 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2283 SDNode *RetVal = selectGather(Node, Opc);
2285 // We already called ReplaceUses inside SelectGather.
2292 case X86ISD::GlobalBaseReg:
2293 return getGlobalBaseReg();
2295 case X86ISD::SHRUNKBLEND: {
2296 // SHRUNKBLEND selects like a regular VSELECT.
2297 SDValue VSelect = CurDAG->getNode(
2298 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2299 Node->getOperand(1), Node->getOperand(2));
2300 ReplaceUses(SDValue(Node, 0), VSelect);
2301 SelectCode(VSelect.getNode());
2302 // We already called ReplaceUses.
2306 case ISD::ATOMIC_LOAD_XOR:
2307 case ISD::ATOMIC_LOAD_AND:
2308 case ISD::ATOMIC_LOAD_OR:
2309 case ISD::ATOMIC_LOAD_ADD: {
2310 SDNode *RetVal = selectAtomicLoadArith(Node, NVT);
2318 // For operations of the form (x << C1) op C2, check if we can use a smaller
2319 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2320 SDValue N0 = Node->getOperand(0);
2321 SDValue N1 = Node->getOperand(1);
2323 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2326 // i8 is unshrinkable, i16 should be promoted to i32.
2327 if (NVT != MVT::i32 && NVT != MVT::i64)
2330 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2331 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2332 if (!Cst || !ShlCst)
2335 int64_t Val = Cst->getSExtValue();
2336 uint64_t ShlVal = ShlCst->getZExtValue();
2338 // Make sure that we don't change the operation by removing bits.
2339 // This only matters for OR and XOR, AND is unaffected.
2340 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2341 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2344 unsigned ShlOp, AddOp, Op;
2347 // Check the minimum bitwidth for the new constant.
2348 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2349 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2350 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2351 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2353 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2356 // Bail if there is no smaller encoding.
2360 switch (NVT.SimpleTy) {
2361 default: llvm_unreachable("Unsupported VT!");
2363 assert(CstVT == MVT::i8);
2364 ShlOp = X86::SHL32ri;
2365 AddOp = X86::ADD32rr;
2368 default: llvm_unreachable("Impossible opcode");
2369 case ISD::AND: Op = X86::AND32ri8; break;
2370 case ISD::OR: Op = X86::OR32ri8; break;
2371 case ISD::XOR: Op = X86::XOR32ri8; break;
2375 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2376 ShlOp = X86::SHL64ri;
2377 AddOp = X86::ADD64rr;
2380 default: llvm_unreachable("Impossible opcode");
2381 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2382 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2383 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2388 // Emit the smaller op and the shift.
2389 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, dl, CstVT);
2390 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2392 return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
2394 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2395 getI8Imm(ShlVal, dl));
2398 case X86ISD::SMUL8: {
2399 SDValue N0 = Node->getOperand(0);
2400 SDValue N1 = Node->getOperand(1);
2402 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2404 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2405 N0, SDValue()).getValue(1);
2407 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2408 SDValue Ops[] = {N1, InFlag};
2409 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2411 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2412 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2416 case X86ISD::UMUL: {
2417 SDValue N0 = Node->getOperand(0);
2418 SDValue N1 = Node->getOperand(1);
2421 switch (NVT.SimpleTy) {
2422 default: llvm_unreachable("Unsupported VT!");
2423 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2424 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2425 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2426 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2429 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2430 N0, SDValue()).getValue(1);
2432 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2433 SDValue Ops[] = {N1, InFlag};
2434 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2436 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2437 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2438 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2442 case ISD::SMUL_LOHI:
2443 case ISD::UMUL_LOHI: {
2444 SDValue N0 = Node->getOperand(0);
2445 SDValue N1 = Node->getOperand(1);
2447 bool isSigned = Opcode == ISD::SMUL_LOHI;
2448 bool hasBMI2 = Subtarget->hasBMI2();
2450 switch (NVT.SimpleTy) {
2451 default: llvm_unreachable("Unsupported VT!");
2452 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2453 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2454 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2455 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2456 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2457 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2460 switch (NVT.SimpleTy) {
2461 default: llvm_unreachable("Unsupported VT!");
2462 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2463 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2464 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2465 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2469 unsigned SrcReg, LoReg, HiReg;
2471 default: llvm_unreachable("Unknown MUL opcode!");
2474 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2478 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2482 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2486 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2489 SrcReg = X86::EDX; LoReg = HiReg = 0;
2492 SrcReg = X86::RDX; LoReg = HiReg = 0;
2496 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2497 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2498 // Multiply is commmutative.
2500 foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2505 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2506 N0, SDValue()).getValue(1);
2507 SDValue ResHi, ResLo;
2511 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2513 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2514 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2515 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2516 ResHi = SDValue(CNode, 0);
2517 ResLo = SDValue(CNode, 1);
2518 Chain = SDValue(CNode, 2);
2519 InFlag = SDValue(CNode, 3);
2521 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2522 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2523 Chain = SDValue(CNode, 0);
2524 InFlag = SDValue(CNode, 1);
2527 // Update the chain.
2528 ReplaceUses(N1.getValue(1), Chain);
2530 SDValue Ops[] = { N1, InFlag };
2531 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2532 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2533 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2534 ResHi = SDValue(CNode, 0);
2535 ResLo = SDValue(CNode, 1);
2536 InFlag = SDValue(CNode, 2);
2538 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2539 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2540 InFlag = SDValue(CNode, 0);
2544 // Prevent use of AH in a REX instruction by referencing AX instead.
2545 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2546 !SDValue(Node, 1).use_empty()) {
2547 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2548 X86::AX, MVT::i16, InFlag);
2549 InFlag = Result.getValue(2);
2550 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2552 if (!SDValue(Node, 0).use_empty())
2553 ReplaceUses(SDValue(Node, 1),
2554 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2556 // Shift AX down 8 bits.
2557 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2559 CurDAG->getTargetConstant(8, dl, MVT::i8)),
2561 // Then truncate it down to i8.
2562 ReplaceUses(SDValue(Node, 1),
2563 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2565 // Copy the low half of the result, if it is needed.
2566 if (!SDValue(Node, 0).use_empty()) {
2567 if (!ResLo.getNode()) {
2568 assert(LoReg && "Register for low half is not defined!");
2569 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2571 InFlag = ResLo.getValue(2);
2573 ReplaceUses(SDValue(Node, 0), ResLo);
2574 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2576 // Copy the high half of the result, if it is needed.
2577 if (!SDValue(Node, 1).use_empty()) {
2578 if (!ResHi.getNode()) {
2579 assert(HiReg && "Register for high half is not defined!");
2580 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2582 InFlag = ResHi.getValue(2);
2584 ReplaceUses(SDValue(Node, 1), ResHi);
2585 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2593 case X86ISD::SDIVREM8_SEXT_HREG:
2594 case X86ISD::UDIVREM8_ZEXT_HREG: {
2595 SDValue N0 = Node->getOperand(0);
2596 SDValue N1 = Node->getOperand(1);
2598 bool isSigned = (Opcode == ISD::SDIVREM ||
2599 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2601 switch (NVT.SimpleTy) {
2602 default: llvm_unreachable("Unsupported VT!");
2603 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2604 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2605 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2606 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2609 switch (NVT.SimpleTy) {
2610 default: llvm_unreachable("Unsupported VT!");
2611 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2612 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2613 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2614 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2618 unsigned LoReg, HiReg, ClrReg;
2619 unsigned SExtOpcode;
2620 switch (NVT.SimpleTy) {
2621 default: llvm_unreachable("Unsupported VT!");
2623 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2624 SExtOpcode = X86::CBW;
2627 LoReg = X86::AX; HiReg = X86::DX;
2629 SExtOpcode = X86::CWD;
2632 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2633 SExtOpcode = X86::CDQ;
2636 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2637 SExtOpcode = X86::CQO;
2641 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2642 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2643 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2646 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2647 // Special case for div8, just use a move with zero extension to AX to
2648 // clear the upper 8 bits (AH).
2649 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2650 if (tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2651 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2653 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2654 MVT::Other, Ops), 0);
2655 Chain = Move.getValue(1);
2656 ReplaceUses(N0.getValue(1), Chain);
2659 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2660 Chain = CurDAG->getEntryNode();
2662 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2663 InFlag = Chain.getValue(1);
2666 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2667 LoReg, N0, SDValue()).getValue(1);
2668 if (isSigned && !signBitIsZero) {
2669 // Sign extend the low part into the high part.
2671 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2673 // Zero out the high part, effectively zero extending the input.
2674 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2675 switch (NVT.SimpleTy) {
2678 SDValue(CurDAG->getMachineNode(
2679 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2680 CurDAG->getTargetConstant(X86::sub_16bit, dl,
2688 SDValue(CurDAG->getMachineNode(
2689 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2690 CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode,
2691 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2696 llvm_unreachable("Unexpected division source");
2699 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2700 ClrNode, InFlag).getValue(1);
2705 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2708 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2709 InFlag = SDValue(CNode, 1);
2710 // Update the chain.
2711 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2714 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2717 // Prevent use of AH in a REX instruction by explicitly copying it to
2718 // an ABCD_L register.
2720 // The current assumption of the register allocator is that isel
2721 // won't generate explicit references to the GR8_ABCD_H registers. If
2722 // the allocator and/or the backend get enhanced to be more robust in
2723 // that regard, this can be, and should be, removed.
2724 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2725 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2726 unsigned AHExtOpcode =
2727 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2729 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2730 MVT::Glue, AHCopy, InFlag);
2731 SDValue Result(RNode, 0);
2732 InFlag = SDValue(RNode, 1);
2734 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2735 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2736 if (Node->getValueType(1) == MVT::i64) {
2737 // It's not possible to directly movsx AH to a 64bit register, because
2738 // the latter needs the REX prefix, but the former can't have it.
2739 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2740 "Unexpected i64 sext of h-register");
2742 SDValue(CurDAG->getMachineNode(
2743 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2744 CurDAG->getTargetConstant(0, dl, MVT::i64), Result,
2745 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2751 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2753 ReplaceUses(SDValue(Node, 1), Result);
2754 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2756 // Copy the division (low) result, if it is needed.
2757 if (!SDValue(Node, 0).use_empty()) {
2758 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2759 LoReg, NVT, InFlag);
2760 InFlag = Result.getValue(2);
2761 ReplaceUses(SDValue(Node, 0), Result);
2762 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2764 // Copy the remainder (high) result, if it is needed.
2765 if (!SDValue(Node, 1).use_empty()) {
2766 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2767 HiReg, NVT, InFlag);
2768 InFlag = Result.getValue(2);
2769 ReplaceUses(SDValue(Node, 1), Result);
2770 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2777 // Sometimes a SUB is used to perform comparison.
2778 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2779 // This node is not a CMP.
2781 SDValue N0 = Node->getOperand(0);
2782 SDValue N1 = Node->getOperand(1);
2784 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2785 hasNoSignedComparisonUses(Node))
2786 N0 = N0.getOperand(0);
2788 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2789 // use a smaller encoding.
2790 // Look past the truncate if CMP is the only use of it.
2791 if ((N0.getNode()->getOpcode() == ISD::AND ||
2792 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2793 N0.getNode()->hasOneUse() &&
2794 N0.getValueType() != MVT::i8 &&
2795 X86::isZeroNode(N1)) {
2796 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2799 // For example, convert "testl %eax, $8" to "testb %al, $8"
2800 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2801 (!(C->getZExtValue() & 0x80) ||
2802 hasNoSignedComparisonUses(Node))) {
2803 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, MVT::i8);
2804 SDValue Reg = N0.getNode()->getOperand(0);
2806 // On x86-32, only the ABCD registers have 8-bit subregisters.
2807 if (!Subtarget->is64Bit()) {
2808 const TargetRegisterClass *TRC;
2809 switch (N0.getSimpleValueType().SimpleTy) {
2810 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2811 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2812 default: llvm_unreachable("Unsupported TEST operand type!");
2814 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2815 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2816 Reg.getValueType(), Reg, RC), 0);
2819 // Extract the l-register.
2820 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2824 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2826 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2827 // one, do not call ReplaceAllUsesWith.
2828 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2829 SDValue(NewNode, 0));
2833 // For example, "testl %eax, $2048" to "testb %ah, $8".
2834 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2835 (!(C->getZExtValue() & 0x8000) ||
2836 hasNoSignedComparisonUses(Node))) {
2837 // Shift the immediate right by 8 bits.
2838 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2840 SDValue Reg = N0.getNode()->getOperand(0);
2842 // Put the value in an ABCD register.
2843 const TargetRegisterClass *TRC;
2844 switch (N0.getSimpleValueType().SimpleTy) {
2845 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2846 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2847 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2848 default: llvm_unreachable("Unsupported TEST operand type!");
2850 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2851 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2852 Reg.getValueType(), Reg, RC), 0);
2854 // Extract the h-register.
2855 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2858 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2859 // target GR8_NOREX registers, so make sure the register class is
2861 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2862 MVT::i32, Subreg, ShiftedImm);
2863 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2864 // one, do not call ReplaceAllUsesWith.
2865 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2866 SDValue(NewNode, 0));
2870 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2871 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2872 N0.getValueType() != MVT::i16 &&
2873 (!(C->getZExtValue() & 0x8000) ||
2874 hasNoSignedComparisonUses(Node))) {
2875 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2877 SDValue Reg = N0.getNode()->getOperand(0);
2879 // Extract the 16-bit subregister.
2880 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2884 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2886 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2887 // one, do not call ReplaceAllUsesWith.
2888 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2889 SDValue(NewNode, 0));
2893 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2894 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2895 N0.getValueType() == MVT::i64 &&
2896 (!(C->getZExtValue() & 0x80000000) ||
2897 hasNoSignedComparisonUses(Node))) {
2898 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2900 SDValue Reg = N0.getNode()->getOperand(0);
2902 // Extract the 32-bit subregister.
2903 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2907 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2909 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2910 // one, do not call ReplaceAllUsesWith.
2911 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2912 SDValue(NewNode, 0));
2919 // Change a chain of {load; incr or dec; store} of the same value into
2920 // a simple increment or decrement through memory of that value, if the
2921 // uses of the modified value and its address are suitable.
2922 // The DEC64m tablegen pattern is currently not able to match the case where
2923 // the EFLAGS on the original DEC are used. (This also applies to
2924 // {INC,DEC}X{64,32,16,8}.)
2925 // We'll need to improve tablegen to allow flags to be transferred from a
2926 // node in the pattern to the result node. probably with a new keyword
2927 // for example, we have this
2928 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2929 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2930 // (implicit EFLAGS)]>;
2931 // but maybe need something like this
2932 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2933 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2934 // (transferrable EFLAGS)]>;
2936 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2937 SDValue StoredVal = StoreNode->getOperand(1);
2938 unsigned Opc = StoredVal->getOpcode();
2940 LoadSDNode *LoadNode = nullptr;
2942 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2943 LoadNode, InputChain))
2946 SDValue Base, Scale, Index, Disp, Segment;
2947 if (!selectAddr(LoadNode, LoadNode->getBasePtr(),
2948 Base, Scale, Index, Disp, Segment))
2951 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2952 MemOp[0] = StoreNode->getMemOperand();
2953 MemOp[1] = LoadNode->getMemOperand();
2954 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2955 EVT LdVT = LoadNode->getMemoryVT();
2956 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2957 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2959 MVT::i32, MVT::Other, Ops);
2960 Result->setMemRefs(MemOp, MemOp + 2);
2962 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2963 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2969 SDNode *ResNode = SelectCode(Node);
2971 DEBUG(dbgs() << "=> ";
2972 if (ResNode == nullptr || ResNode == Node)
2975 ResNode->dump(CurDAG);
2981 bool X86DAGToDAGISel::
2982 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
2983 std::vector<SDValue> &OutOps) {
2984 SDValue Op0, Op1, Op2, Op3, Op4;
2985 switch (ConstraintID) {
2987 llvm_unreachable("Unexpected asm memory constraint");
2988 case InlineAsm::Constraint_i:
2989 // FIXME: It seems strange that 'i' is needed here since it's supposed to
2990 // be an immediate and not a memory constraint.
2992 case InlineAsm::Constraint_o: // offsetable ??
2993 case InlineAsm::Constraint_v: // not offsetable ??
2994 case InlineAsm::Constraint_m: // memory
2995 case InlineAsm::Constraint_X:
2996 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
3001 OutOps.push_back(Op0);
3002 OutOps.push_back(Op1);
3003 OutOps.push_back(Op2);
3004 OutOps.push_back(Op3);
3005 OutOps.push_back(Op4);
3009 /// This pass converts a legalized DAG into a X86-specific DAG,
3010 /// ready for instruction scheduling.
3011 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
3012 CodeGenOpt::Level OptLevel) {
3013 return new X86DAGToDAGISel(TM, OptLevel);