1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
77 JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != nullptr || CP != nullptr || ES != nullptr ||
82 JT != -1 || BlockAddr != nullptr;
85 bool hasBaseOrIndexReg() const {
86 return BaseType == FrameIndexBase ||
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
90 /// isRIPRelative - Return true if this addressing mode is already RIP
92 bool isRIPRelative() const {
93 if (BaseType != RegBase) return false;
94 if (RegisterSDNode *RegNode =
95 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
96 return RegNode->getReg() == X86::RIP;
100 void setBaseReg(SDValue Reg) {
105 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
107 dbgs() << "X86ISelAddressMode " << this << '\n';
108 dbgs() << "Base_Reg ";
109 if (Base_Reg.getNode())
110 Base_Reg.getNode()->dump();
113 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
114 << " Scale" << Scale << '\n'
116 if (IndexReg.getNode())
117 IndexReg.getNode()->dump();
120 dbgs() << " Disp " << Disp << '\n'
137 dbgs() << " JT" << JT << " Align" << Align << '\n';
144 //===--------------------------------------------------------------------===//
145 /// ISel - X86 specific code to select X86 machine instructions for
146 /// SelectionDAG operations.
148 class X86DAGToDAGISel final : public SelectionDAGISel {
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel), OptForSize(false) {}
161 const char *getPassName() const override {
162 return "X86 DAG->DAG Instruction Selection";
165 bool runOnMachineFunction(MachineFunction &MF) override {
166 // Reset the subtarget each time through.
167 Subtarget = &MF.getSubtarget<X86Subtarget>();
168 SelectionDAGISel::runOnMachineFunction(MF);
172 void EmitFunctionEntryCode() override;
174 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
176 void PreprocessISelDAG() override;
178 inline bool immSext8(SDNode *N) const {
179 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
182 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
183 // sign extended field.
184 inline bool i64immSExt32(SDNode *N) const {
185 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
186 return (int64_t)v == (int32_t)v;
189 // Include the pieces autogenerated from the target description.
190 #include "X86GenDAGISel.inc"
193 SDNode *Select(SDNode *N) override;
194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
208 bool SelectLEAAddr(SDValue N, SDValue &Base,
209 SDValue &Scale, SDValue &Index, SDValue &Disp,
211 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
212 SDValue &Scale, SDValue &Index, SDValue &Disp,
214 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
217 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
218 SDValue &Base, SDValue &Scale,
219 SDValue &Index, SDValue &Disp,
221 SDValue &NodeWithChain);
223 bool TryFoldLoad(SDNode *P, SDValue N,
224 SDValue &Base, SDValue &Scale,
225 SDValue &Index, SDValue &Disp,
228 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
229 /// inline asm expressions.
230 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
232 std::vector<SDValue> &OutOps) override;
234 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
236 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
237 SDValue &Scale, SDValue &Index,
238 SDValue &Disp, SDValue &Segment) {
239 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
240 ? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
243 Scale = getI8Imm(AM.Scale);
245 // These are 32-bit even in 64-bit mode since RIP relative offset
248 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
252 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
253 AM.Align, AM.Disp, AM.SymbolFlags);
255 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
256 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
257 } else if (AM.JT != -1) {
258 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
259 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
260 } else if (AM.BlockAddr)
261 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
264 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
266 if (AM.Segment.getNode())
267 Segment = AM.Segment;
269 Segment = CurDAG->getRegister(0, MVT::i32);
272 /// getI8Imm - Return a target constant with the specified value, of type
274 inline SDValue getI8Imm(unsigned Imm) {
275 return CurDAG->getTargetConstant(Imm, MVT::i8);
278 /// getI32Imm - Return a target constant with the specified value, of type
280 inline SDValue getI32Imm(unsigned Imm) {
281 return CurDAG->getTargetConstant(Imm, MVT::i32);
284 /// getGlobalBaseReg - Return an SDNode that returns the value of
285 /// the global base register. Output instructions required to
286 /// initialize the global base register, if necessary.
288 SDNode *getGlobalBaseReg();
290 /// getTargetMachine - Return a reference to the TargetMachine, casted
291 /// to the target-specific type.
292 const X86TargetMachine &getTargetMachine() const {
293 return static_cast<const X86TargetMachine &>(TM);
296 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
297 /// to the target-specific type.
298 const X86InstrInfo *getInstrInfo() const {
299 return Subtarget->getInstrInfo();
302 /// \brief Address-mode matching performs shift-of-and to and-of-shift
303 /// reassociation in order to expose more scaled addressing
305 bool ComplexPatternFuncMutatesDAG() const override {
313 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
314 if (OptLevel == CodeGenOpt::None) return false;
319 if (N.getOpcode() != ISD::LOAD)
322 // If N is a load, do additional profitability checks.
324 switch (U->getOpcode()) {
337 SDValue Op1 = U->getOperand(1);
339 // If the other operand is a 8-bit immediate we should fold the immediate
340 // instead. This reduces code size.
342 // movl 4(%esp), %eax
346 // addl 4(%esp), %eax
347 // The former is 2 bytes shorter. In case where the increment is 1, then
348 // the saving can be 4 bytes (by using incl %eax).
349 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
350 if (Imm->getAPIntValue().isSignedIntN(8))
353 // If the other operand is a TLS address, we should fold it instead.
356 // leal i@NTPOFF(%eax), %eax
358 // movl $i@NTPOFF, %eax
360 // if the block also has an access to a second TLS address this will save
362 // FIXME: This is probably also true for non-TLS addresses.
363 if (Op1.getOpcode() == X86ISD::Wrapper) {
364 SDValue Val = Op1.getOperand(0);
365 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
375 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
376 /// load's chain operand and move load below the call's chain operand.
377 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
378 SDValue Call, SDValue OrigChain) {
379 SmallVector<SDValue, 8> Ops;
380 SDValue Chain = OrigChain.getOperand(0);
381 if (Chain.getNode() == Load.getNode())
382 Ops.push_back(Load.getOperand(0));
384 assert(Chain.getOpcode() == ISD::TokenFactor &&
385 "Unexpected chain operand");
386 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
387 if (Chain.getOperand(i).getNode() == Load.getNode())
388 Ops.push_back(Load.getOperand(0));
390 Ops.push_back(Chain.getOperand(i));
392 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
394 Ops.push_back(NewChain);
396 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
397 Ops.push_back(OrigChain.getOperand(i));
398 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
399 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
400 Load.getOperand(1), Load.getOperand(2));
402 unsigned NumOps = Call.getNode()->getNumOperands();
404 Ops.push_back(SDValue(Load.getNode(), 1));
405 for (unsigned i = 1, e = NumOps; i != e; ++i)
406 Ops.push_back(Call.getOperand(i));
407 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
410 /// isCalleeLoad - Return true if call address is a load and it can be
411 /// moved below CALLSEQ_START and the chains leading up to the call.
412 /// Return the CALLSEQ_START by reference as a second output.
413 /// In the case of a tail call, there isn't a callseq node between the call
414 /// chain and the load.
415 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
416 // The transformation is somewhat dangerous if the call's chain was glued to
417 // the call. After MoveBelowOrigChain the load is moved between the call and
418 // the chain, this can create a cycle if the load is not folded. So it is
419 // *really* important that we are sure the load will be folded.
420 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
422 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
425 LD->getAddressingMode() != ISD::UNINDEXED ||
426 LD->getExtensionType() != ISD::NON_EXTLOAD)
429 // Now let's find the callseq_start.
430 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
431 if (!Chain.hasOneUse())
433 Chain = Chain.getOperand(0);
436 if (!Chain.getNumOperands())
438 // Since we are not checking for AA here, conservatively abort if the chain
439 // writes to memory. It's not safe to move the callee (a load) across a store.
440 if (isa<MemSDNode>(Chain.getNode()) &&
441 cast<MemSDNode>(Chain.getNode())->writeMem())
443 if (Chain.getOperand(0).getNode() == Callee.getNode())
445 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
446 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
447 Callee.getValue(1).hasOneUse())
452 void X86DAGToDAGISel::PreprocessISelDAG() {
453 // OptForSize is used in pattern predicates that isel is matching.
454 OptForSize = MF->getFunction()->getAttributes().
455 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
457 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
458 E = CurDAG->allnodes_end(); I != E; ) {
459 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
461 if (OptLevel != CodeGenOpt::None &&
462 // Only does this when target favors doesn't favor register indirect
464 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
465 (N->getOpcode() == X86ISD::TC_RETURN &&
466 // Only does this if load can be folded into TC_RETURN.
467 (Subtarget->is64Bit() ||
468 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
469 /// Also try moving call address load from outside callseq_start to just
470 /// before the call to allow it to be folded.
488 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
489 SDValue Chain = N->getOperand(0);
490 SDValue Load = N->getOperand(1);
491 if (!isCalleeLoad(Load, Chain, HasCallSeq))
493 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
498 // Lower fpround and fpextend nodes that target the FP stack to be store and
499 // load to the stack. This is a gross hack. We would like to simply mark
500 // these as being illegal, but when we do that, legalize produces these when
501 // it expands calls, then expands these in the same legalize pass. We would
502 // like dag combine to be able to hack on these between the call expansion
503 // and the node legalization. As such this pass basically does "really
504 // late" legalization of these inline with the X86 isel pass.
505 // FIXME: This should only happen when not compiled with -O0.
506 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
509 MVT SrcVT = N->getOperand(0).getSimpleValueType();
510 MVT DstVT = N->getSimpleValueType(0);
512 // If any of the sources are vectors, no fp stack involved.
513 if (SrcVT.isVector() || DstVT.isVector())
516 // If the source and destination are SSE registers, then this is a legal
517 // conversion that should not be lowered.
518 const X86TargetLowering *X86Lowering =
519 static_cast<const X86TargetLowering *>(TLI);
520 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
521 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
522 if (SrcIsSSE && DstIsSSE)
525 if (!SrcIsSSE && !DstIsSSE) {
526 // If this is an FPStack extension, it is a noop.
527 if (N->getOpcode() == ISD::FP_EXTEND)
529 // If this is a value-preserving FPStack truncation, it is a noop.
530 if (N->getConstantOperandVal(1))
534 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
535 // FPStack has extload and truncstore. SSE can fold direct loads into other
536 // operations. Based on this, decide what we want to do.
538 if (N->getOpcode() == ISD::FP_ROUND)
539 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
541 MemVT = SrcIsSSE ? SrcVT : DstVT;
543 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
546 // FIXME: optimize the case where the src/dest is a load or store?
547 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
549 MemTmp, MachinePointerInfo(), MemVT,
551 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
552 MachinePointerInfo(),
553 MemVT, false, false, false, 0);
555 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
556 // extload we created. This will cause general havok on the dag because
557 // anything below the conversion could be folded into other existing nodes.
558 // To avoid invalidating 'I', back it up to the convert node.
560 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
562 // Now that we did that, the node is dead. Increment the iterator to the
563 // next node to process, then delete N.
565 CurDAG->DeleteNode(N);
570 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
571 /// the main function.
572 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
573 MachineFrameInfo *MFI) {
574 const TargetInstrInfo *TII = getInstrInfo();
575 if (Subtarget->isTargetCygMing()) {
577 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
578 BuildMI(BB, DebugLoc(),
579 TII->get(CallOp)).addExternalSymbol("__main");
583 void X86DAGToDAGISel::EmitFunctionEntryCode() {
584 // If this is main, emit special code for main.
585 if (const Function *Fn = MF->getFunction())
586 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
587 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
590 static bool isDispSafeForFrameIndex(int64_t Val) {
591 // On 64-bit platforms, we can run into an issue where a frame index
592 // includes a displacement that, when added to the explicit displacement,
593 // will overflow the displacement field. Assuming that the frame index
594 // displacement fits into a 31-bit integer (which is only slightly more
595 // aggressive than the current fundamental assumption that it fits into
596 // a 32-bit integer), a 31-bit disp should always be safe.
597 return isInt<31>(Val);
600 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
601 X86ISelAddressMode &AM) {
602 int64_t Val = AM.Disp + Offset;
603 CodeModel::Model M = TM.getCodeModel();
604 if (Subtarget->is64Bit()) {
605 if (!X86::isOffsetSuitableForCodeModel(Val, M,
606 AM.hasSymbolicDisplacement()))
608 // In addition to the checks required for a register base, check that
609 // we do not try to use an unsafe Disp with a frame index.
610 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
611 !isDispSafeForFrameIndex(Val))
619 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
620 SDValue Address = N->getOperand(1);
622 // load gs:0 -> GS segment register.
623 // load fs:0 -> FS segment register.
625 // This optimization is valid because the GNU TLS model defines that
626 // gs:0 (or fs:0 on X86-64) contains its own address.
627 // For more information see http://people.redhat.com/drepper/tls.pdf
628 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
629 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
630 Subtarget->isTargetLinux())
631 switch (N->getPointerInfo().getAddrSpace()) {
633 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
636 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
643 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
644 /// into an addressing mode. These wrap things that will resolve down into a
645 /// symbol reference. If no match is possible, this returns true, otherwise it
647 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
648 // If the addressing mode already has a symbol as the displacement, we can
649 // never match another symbol.
650 if (AM.hasSymbolicDisplacement())
653 SDValue N0 = N.getOperand(0);
654 CodeModel::Model M = TM.getCodeModel();
656 // Handle X86-64 rip-relative addresses. We check this before checking direct
657 // folding because RIP is preferable to non-RIP accesses.
658 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
659 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
660 // they cannot be folded into immediate fields.
661 // FIXME: This can be improved for kernel and other models?
662 (M == CodeModel::Small || M == CodeModel::Kernel)) {
663 // Base and index reg must be 0 in order to use %rip as base.
664 if (AM.hasBaseOrIndexReg())
666 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
667 X86ISelAddressMode Backup = AM;
668 AM.GV = G->getGlobal();
669 AM.SymbolFlags = G->getTargetFlags();
670 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
674 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
675 X86ISelAddressMode Backup = AM;
676 AM.CP = CP->getConstVal();
677 AM.Align = CP->getAlignment();
678 AM.SymbolFlags = CP->getTargetFlags();
679 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
683 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
684 AM.ES = S->getSymbol();
685 AM.SymbolFlags = S->getTargetFlags();
686 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
687 AM.JT = J->getIndex();
688 AM.SymbolFlags = J->getTargetFlags();
689 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
690 X86ISelAddressMode Backup = AM;
691 AM.BlockAddr = BA->getBlockAddress();
692 AM.SymbolFlags = BA->getTargetFlags();
693 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
698 llvm_unreachable("Unhandled symbol reference node.");
700 if (N.getOpcode() == X86ISD::WrapperRIP)
701 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
705 // Handle the case when globals fit in our immediate field: This is true for
706 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
707 // mode, this only applies to a non-RIP-relative computation.
708 if (!Subtarget->is64Bit() ||
709 M == CodeModel::Small || M == CodeModel::Kernel) {
710 assert(N.getOpcode() != X86ISD::WrapperRIP &&
711 "RIP-relative addressing already handled");
712 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
713 AM.GV = G->getGlobal();
714 AM.Disp += G->getOffset();
715 AM.SymbolFlags = G->getTargetFlags();
716 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
717 AM.CP = CP->getConstVal();
718 AM.Align = CP->getAlignment();
719 AM.Disp += CP->getOffset();
720 AM.SymbolFlags = CP->getTargetFlags();
721 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
722 AM.ES = S->getSymbol();
723 AM.SymbolFlags = S->getTargetFlags();
724 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
725 AM.JT = J->getIndex();
726 AM.SymbolFlags = J->getTargetFlags();
727 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
728 AM.BlockAddr = BA->getBlockAddress();
729 AM.Disp += BA->getOffset();
730 AM.SymbolFlags = BA->getTargetFlags();
732 llvm_unreachable("Unhandled symbol reference node.");
739 /// MatchAddress - Add the specified node to the specified addressing mode,
740 /// returning true if it cannot be done. This just pattern matches for the
742 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
743 if (MatchAddressRecursively(N, AM, 0))
746 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
747 // a smaller encoding and avoids a scaled-index.
749 AM.BaseType == X86ISelAddressMode::RegBase &&
750 AM.Base_Reg.getNode() == nullptr) {
751 AM.Base_Reg = AM.IndexReg;
755 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
756 // because it has a smaller encoding.
757 // TODO: Which other code models can use this?
758 if (TM.getCodeModel() == CodeModel::Small &&
759 Subtarget->is64Bit() &&
761 AM.BaseType == X86ISelAddressMode::RegBase &&
762 AM.Base_Reg.getNode() == nullptr &&
763 AM.IndexReg.getNode() == nullptr &&
764 AM.SymbolFlags == X86II::MO_NO_FLAG &&
765 AM.hasSymbolicDisplacement())
766 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
771 // Insert a node into the DAG at least before the Pos node's position. This
772 // will reposition the node as needed, and will assign it a node ID that is <=
773 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
774 // IDs! The selection DAG must no longer depend on their uniqueness when this
776 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
777 if (N.getNode()->getNodeId() == -1 ||
778 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
779 DAG.RepositionNode(Pos.getNode(), N.getNode());
780 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
784 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
785 // safe. This allows us to convert the shift and and into an h-register
786 // extract and a scaled index. Returns false if the simplification is
788 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
790 SDValue Shift, SDValue X,
791 X86ISelAddressMode &AM) {
792 if (Shift.getOpcode() != ISD::SRL ||
793 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
797 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
798 if (ScaleLog <= 0 || ScaleLog >= 4 ||
799 Mask != (0xffu << ScaleLog))
802 MVT VT = N.getSimpleValueType();
804 SDValue Eight = DAG.getConstant(8, MVT::i8);
805 SDValue NewMask = DAG.getConstant(0xff, VT);
806 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
807 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
808 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
809 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
811 // Insert the new nodes into the topological ordering. We must do this in
812 // a valid topological ordering as nothing is going to go back and re-sort
813 // these nodes. We continually insert before 'N' in sequence as this is
814 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
815 // hierarchy left to express.
816 InsertDAGNode(DAG, N, Eight);
817 InsertDAGNode(DAG, N, Srl);
818 InsertDAGNode(DAG, N, NewMask);
819 InsertDAGNode(DAG, N, And);
820 InsertDAGNode(DAG, N, ShlCount);
821 InsertDAGNode(DAG, N, Shl);
822 DAG.ReplaceAllUsesWith(N, Shl);
824 AM.Scale = (1 << ScaleLog);
828 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
829 // allows us to fold the shift into this addressing mode. Returns false if the
830 // transform succeeded.
831 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
833 SDValue Shift, SDValue X,
834 X86ISelAddressMode &AM) {
835 if (Shift.getOpcode() != ISD::SHL ||
836 !isa<ConstantSDNode>(Shift.getOperand(1)))
839 // Not likely to be profitable if either the AND or SHIFT node has more
840 // than one use (unless all uses are for address computation). Besides,
841 // isel mechanism requires their node ids to be reused.
842 if (!N.hasOneUse() || !Shift.hasOneUse())
845 // Verify that the shift amount is something we can fold.
846 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
847 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
850 MVT VT = N.getSimpleValueType();
852 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
853 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
854 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
856 // Insert the new nodes into the topological ordering. We must do this in
857 // a valid topological ordering as nothing is going to go back and re-sort
858 // these nodes. We continually insert before 'N' in sequence as this is
859 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
860 // hierarchy left to express.
861 InsertDAGNode(DAG, N, NewMask);
862 InsertDAGNode(DAG, N, NewAnd);
863 InsertDAGNode(DAG, N, NewShift);
864 DAG.ReplaceAllUsesWith(N, NewShift);
866 AM.Scale = 1 << ShiftAmt;
867 AM.IndexReg = NewAnd;
871 // Implement some heroics to detect shifts of masked values where the mask can
872 // be replaced by extending the shift and undoing that in the addressing mode
873 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
874 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
875 // the addressing mode. This results in code such as:
877 // int f(short *y, int *lookup_table) {
879 // return *y + lookup_table[*y >> 11];
883 // movzwl (%rdi), %eax
886 // addl (%rsi,%rcx,4), %eax
889 // movzwl (%rdi), %eax
893 // addl (%rsi,%rcx), %eax
895 // Note that this function assumes the mask is provided as a mask *after* the
896 // value is shifted. The input chain may or may not match that, but computing
897 // such a mask is trivial.
898 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
900 SDValue Shift, SDValue X,
901 X86ISelAddressMode &AM) {
902 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
903 !isa<ConstantSDNode>(Shift.getOperand(1)))
906 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
907 unsigned MaskLZ = countLeadingZeros(Mask);
908 unsigned MaskTZ = countTrailingZeros(Mask);
910 // The amount of shift we're trying to fit into the addressing mode is taken
911 // from the trailing zeros of the mask.
912 unsigned AMShiftAmt = MaskTZ;
914 // There is nothing we can do here unless the mask is removing some bits.
915 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
916 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
918 // We also need to ensure that mask is a continuous run of bits.
919 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
921 // Scale the leading zero count down based on the actual size of the value.
922 // Also scale it down based on the size of the shift.
923 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
925 // The final check is to ensure that any masked out high bits of X are
926 // already known to be zero. Otherwise, the mask has a semantic impact
927 // other than masking out a couple of low bits. Unfortunately, because of
928 // the mask, zero extensions will be removed from operands in some cases.
929 // This code works extra hard to look through extensions because we can
930 // replace them with zero extensions cheaply if necessary.
931 bool ReplacingAnyExtend = false;
932 if (X.getOpcode() == ISD::ANY_EXTEND) {
933 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
934 X.getOperand(0).getSimpleValueType().getSizeInBits();
935 // Assume that we'll replace the any-extend with a zero-extend, and
936 // narrow the search to the extended value.
938 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
939 ReplacingAnyExtend = true;
941 APInt MaskedHighBits =
942 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
943 APInt KnownZero, KnownOne;
944 DAG.computeKnownBits(X, KnownZero, KnownOne);
945 if (MaskedHighBits != KnownZero) return true;
947 // We've identified a pattern that can be transformed into a single shift
948 // and an addressing mode. Make it so.
949 MVT VT = N.getSimpleValueType();
950 if (ReplacingAnyExtend) {
951 assert(X.getValueType() != VT);
952 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
953 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
954 InsertDAGNode(DAG, N, NewX);
958 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
959 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
960 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
961 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
963 // Insert the new nodes into the topological ordering. We must do this in
964 // a valid topological ordering as nothing is going to go back and re-sort
965 // these nodes. We continually insert before 'N' in sequence as this is
966 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
967 // hierarchy left to express.
968 InsertDAGNode(DAG, N, NewSRLAmt);
969 InsertDAGNode(DAG, N, NewSRL);
970 InsertDAGNode(DAG, N, NewSHLAmt);
971 InsertDAGNode(DAG, N, NewSHL);
972 DAG.ReplaceAllUsesWith(N, NewSHL);
974 AM.Scale = 1 << AMShiftAmt;
975 AM.IndexReg = NewSRL;
979 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
983 dbgs() << "MatchAddress: ";
988 return MatchAddressBase(N, AM);
990 // If this is already a %rip relative address, we can only merge immediates
991 // into it. Instead of handling this in every case, we handle it here.
992 // RIP relative addressing: %rip + 32-bit displacement!
993 if (AM.isRIPRelative()) {
994 // FIXME: JumpTable and ExternalSymbol address currently don't like
995 // displacements. It isn't very important, but this should be fixed for
997 if (!AM.ES && AM.JT != -1) return true;
999 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
1000 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
1005 switch (N.getOpcode()) {
1007 case ISD::Constant: {
1008 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1009 if (!FoldOffsetIntoAddress(Val, AM))
1014 case X86ISD::Wrapper:
1015 case X86ISD::WrapperRIP:
1016 if (!MatchWrapper(N, AM))
1021 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1025 case ISD::FrameIndex:
1026 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1027 AM.Base_Reg.getNode() == nullptr &&
1028 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1029 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1030 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1036 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1040 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1041 unsigned Val = CN->getZExtValue();
1042 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1043 // that the base operand remains free for further matching. If
1044 // the base doesn't end up getting used, a post-processing step
1045 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1046 if (Val == 1 || Val == 2 || Val == 3) {
1047 AM.Scale = 1 << Val;
1048 SDValue ShVal = N.getNode()->getOperand(0);
1050 // Okay, we know that we have a scale by now. However, if the scaled
1051 // value is an add of something and a constant, we can fold the
1052 // constant into the disp field here.
1053 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1054 AM.IndexReg = ShVal.getNode()->getOperand(0);
1055 ConstantSDNode *AddVal =
1056 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1057 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1058 if (!FoldOffsetIntoAddress(Disp, AM))
1062 AM.IndexReg = ShVal;
1069 // Scale must not be used already.
1070 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1072 SDValue And = N.getOperand(0);
1073 if (And.getOpcode() != ISD::AND) break;
1074 SDValue X = And.getOperand(0);
1076 // We only handle up to 64-bit values here as those are what matter for
1077 // addressing mode optimizations.
1078 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1080 // The mask used for the transform is expected to be post-shift, but we
1081 // found the shift first so just apply the shift to the mask before passing
1083 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1084 !isa<ConstantSDNode>(And.getOperand(1)))
1086 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1088 // Try to fold the mask and shift into the scale, and return false if we
1090 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1095 case ISD::SMUL_LOHI:
1096 case ISD::UMUL_LOHI:
1097 // A mul_lohi where we need the low part can be folded as a plain multiply.
1098 if (N.getResNo() != 0) break;
1101 case X86ISD::MUL_IMM:
1102 // X*[3,5,9] -> X+X*[2,4,8]
1103 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1104 AM.Base_Reg.getNode() == nullptr &&
1105 AM.IndexReg.getNode() == nullptr) {
1107 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1108 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1109 CN->getZExtValue() == 9) {
1110 AM.Scale = unsigned(CN->getZExtValue())-1;
1112 SDValue MulVal = N.getNode()->getOperand(0);
1115 // Okay, we know that we have a scale by now. However, if the scaled
1116 // value is an add of something and a constant, we can fold the
1117 // constant into the disp field here.
1118 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1119 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1120 Reg = MulVal.getNode()->getOperand(0);
1121 ConstantSDNode *AddVal =
1122 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1123 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1124 if (FoldOffsetIntoAddress(Disp, AM))
1125 Reg = N.getNode()->getOperand(0);
1127 Reg = N.getNode()->getOperand(0);
1130 AM.IndexReg = AM.Base_Reg = Reg;
1137 // Given A-B, if A can be completely folded into the address and
1138 // the index field with the index field unused, use -B as the index.
1139 // This is a win if a has multiple parts that can be folded into
1140 // the address. Also, this saves a mov if the base register has
1141 // other uses, since it avoids a two-address sub instruction, however
1142 // it costs an additional mov if the index register has other uses.
1144 // Add an artificial use to this node so that we can keep track of
1145 // it if it gets CSE'd with a different node.
1146 HandleSDNode Handle(N);
1148 // Test if the LHS of the sub can be folded.
1149 X86ISelAddressMode Backup = AM;
1150 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1154 // Test if the index field is free for use.
1155 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1161 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1162 // If the RHS involves a register with multiple uses, this
1163 // transformation incurs an extra mov, due to the neg instruction
1164 // clobbering its operand.
1165 if (!RHS.getNode()->hasOneUse() ||
1166 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1167 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1168 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1169 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1170 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1172 // If the base is a register with multiple uses, this
1173 // transformation may save a mov.
1174 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1175 AM.Base_Reg.getNode() &&
1176 !AM.Base_Reg.getNode()->hasOneUse()) ||
1177 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1179 // If the folded LHS was interesting, this transformation saves
1180 // address arithmetic.
1181 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1182 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1183 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1185 // If it doesn't look like it may be an overall win, don't do it.
1191 // Ok, the transformation is legal and appears profitable. Go for it.
1192 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1193 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1197 // Insert the new nodes into the topological ordering.
1198 InsertDAGNode(*CurDAG, N, Zero);
1199 InsertDAGNode(*CurDAG, N, Neg);
1204 // Add an artificial use to this node so that we can keep track of
1205 // it if it gets CSE'd with a different node.
1206 HandleSDNode Handle(N);
1208 X86ISelAddressMode Backup = AM;
1209 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1210 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1214 // Try again after commuting the operands.
1215 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1216 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1220 // If we couldn't fold both operands into the address at the same time,
1221 // see if we can just put each operand into a register and fold at least
1223 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1224 !AM.Base_Reg.getNode() &&
1225 !AM.IndexReg.getNode()) {
1226 N = Handle.getValue();
1227 AM.Base_Reg = N.getOperand(0);
1228 AM.IndexReg = N.getOperand(1);
1232 N = Handle.getValue();
1237 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1238 if (CurDAG->isBaseWithConstantOffset(N)) {
1239 X86ISelAddressMode Backup = AM;
1240 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1242 // Start with the LHS as an addr mode.
1243 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1244 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1251 // Perform some heroic transforms on an and of a constant-count shift
1252 // with a constant to enable use of the scaled offset field.
1254 // Scale must not be used already.
1255 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1257 SDValue Shift = N.getOperand(0);
1258 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1259 SDValue X = Shift.getOperand(0);
1261 // We only handle up to 64-bit values here as those are what matter for
1262 // addressing mode optimizations.
1263 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1265 if (!isa<ConstantSDNode>(N.getOperand(1)))
1267 uint64_t Mask = N.getConstantOperandVal(1);
1269 // Try to fold the mask and shift into an extract and scale.
1270 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1273 // Try to fold the mask and shift directly into the scale.
1274 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1277 // Try to swap the mask and shift to place shifts which can be done as
1278 // a scale on the outside of the mask.
1279 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1285 return MatchAddressBase(N, AM);
1288 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1289 /// specified addressing mode without any further recursion.
1290 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1291 // Is the base register already occupied?
1292 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1293 // If so, check to see if the scale index register is set.
1294 if (!AM.IndexReg.getNode()) {
1300 // Otherwise, we cannot select it.
1304 // Default, generate it as a register.
1305 AM.BaseType = X86ISelAddressMode::RegBase;
1310 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1311 /// It returns the operands which make up the maximal addressing mode it can
1312 /// match by reference.
1314 /// Parent is the parent node of the addr operand that is being matched. It
1315 /// is always a load, store, atomic node, or null. It is only null when
1316 /// checking memory operands for inline asm nodes.
1317 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1318 SDValue &Scale, SDValue &Index,
1319 SDValue &Disp, SDValue &Segment) {
1320 X86ISelAddressMode AM;
1323 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1324 // that are not a MemSDNode, and thus don't have proper addrspace info.
1325 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1326 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1327 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1328 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1329 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1330 unsigned AddrSpace =
1331 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1332 // AddrSpace 256 -> GS, 257 -> FS.
1333 if (AddrSpace == 256)
1334 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1335 if (AddrSpace == 257)
1336 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1339 if (MatchAddress(N, AM))
1342 MVT VT = N.getSimpleValueType();
1343 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1344 if (!AM.Base_Reg.getNode())
1345 AM.Base_Reg = CurDAG->getRegister(0, VT);
1348 if (!AM.IndexReg.getNode())
1349 AM.IndexReg = CurDAG->getRegister(0, VT);
1351 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1355 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1356 /// match a load whose top elements are either undef or zeros. The load flavor
1357 /// is derived from the type of N, which is either v4f32 or v2f64.
1360 /// PatternChainNode: this is the matched node that has a chain input and
1362 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1363 SDValue N, SDValue &Base,
1364 SDValue &Scale, SDValue &Index,
1365 SDValue &Disp, SDValue &Segment,
1366 SDValue &PatternNodeWithChain) {
1367 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1368 PatternNodeWithChain = N.getOperand(0);
1369 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1370 PatternNodeWithChain.hasOneUse() &&
1371 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1372 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1373 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1374 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1380 // Also handle the case where we explicitly require zeros in the top
1381 // elements. This is a vector shuffle from the zero vector.
1382 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1383 // Check to see if the top elements are all zeros (or bitcast of zeros).
1384 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1385 N.getOperand(0).getNode()->hasOneUse() &&
1386 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1387 N.getOperand(0).getOperand(0).hasOneUse() &&
1388 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1389 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1390 // Okay, this is a zero extending load. Fold it.
1391 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1392 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1394 PatternNodeWithChain = SDValue(LD, 0);
1401 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1402 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1403 uint64_t ImmVal = CN->getZExtValue();
1404 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1407 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1411 // In static codegen with small code model, we can get the address of a label
1412 // into a register with 'movl'. TableGen has already made sure we're looking
1413 // at a label of some kind.
1414 assert(N->getOpcode() == X86ISD::Wrapper &&
1415 "Unexpected node type for MOV32ri64");
1416 N = N.getOperand(0);
1418 if (N->getOpcode() != ISD::TargetConstantPool &&
1419 N->getOpcode() != ISD::TargetJumpTable &&
1420 N->getOpcode() != ISD::TargetGlobalAddress &&
1421 N->getOpcode() != ISD::TargetExternalSymbol &&
1422 N->getOpcode() != ISD::TargetBlockAddress)
1426 return TM.getCodeModel() == CodeModel::Small;
1429 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1430 SDValue &Scale, SDValue &Index,
1431 SDValue &Disp, SDValue &Segment) {
1432 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1436 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1437 if (RN && RN->getReg() == 0)
1438 Base = CurDAG->getRegister(0, MVT::i64);
1439 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1440 // Base could already be %rip, particularly in the x32 ABI.
1441 Base = SDValue(CurDAG->getMachineNode(
1442 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1443 CurDAG->getTargetConstant(0, MVT::i64),
1445 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1449 RN = dyn_cast<RegisterSDNode>(Index);
1450 if (RN && RN->getReg() == 0)
1451 Index = CurDAG->getRegister(0, MVT::i64);
1453 assert(Index.getValueType() == MVT::i32 &&
1454 "Expect to be extending 32-bit registers for use in LEA");
1455 Index = SDValue(CurDAG->getMachineNode(
1456 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1457 CurDAG->getTargetConstant(0, MVT::i64),
1459 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1466 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1467 /// mode it matches can be cost effectively emitted as an LEA instruction.
1468 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1469 SDValue &Base, SDValue &Scale,
1470 SDValue &Index, SDValue &Disp,
1472 X86ISelAddressMode AM;
1474 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1476 SDValue Copy = AM.Segment;
1477 SDValue T = CurDAG->getRegister(0, MVT::i32);
1479 if (MatchAddress(N, AM))
1481 assert (T == AM.Segment);
1484 MVT VT = N.getSimpleValueType();
1485 unsigned Complexity = 0;
1486 if (AM.BaseType == X86ISelAddressMode::RegBase)
1487 if (AM.Base_Reg.getNode())
1490 AM.Base_Reg = CurDAG->getRegister(0, VT);
1491 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1494 if (AM.IndexReg.getNode())
1497 AM.IndexReg = CurDAG->getRegister(0, VT);
1499 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1504 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1505 // to a LEA. This is determined with some expermentation but is by no means
1506 // optimal (especially for code size consideration). LEA is nice because of
1507 // its three-address nature. Tweak the cost function again when we can run
1508 // convertToThreeAddress() at register allocation time.
1509 if (AM.hasSymbolicDisplacement()) {
1510 // For X86-64, we should always use lea to materialize RIP relative
1512 if (Subtarget->is64Bit())
1518 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1521 // If it isn't worth using an LEA, reject it.
1522 if (Complexity <= 2)
1525 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1529 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1530 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1531 SDValue &Scale, SDValue &Index,
1532 SDValue &Disp, SDValue &Segment) {
1533 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1534 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1536 X86ISelAddressMode AM;
1537 AM.GV = GA->getGlobal();
1538 AM.Disp += GA->getOffset();
1539 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1540 AM.SymbolFlags = GA->getTargetFlags();
1542 if (N.getValueType() == MVT::i32) {
1544 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1546 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1549 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1554 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1555 SDValue &Base, SDValue &Scale,
1556 SDValue &Index, SDValue &Disp,
1558 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1559 !IsProfitableToFold(N, P, P) ||
1560 !IsLegalToFold(N, P, P, OptLevel))
1563 return SelectAddr(N.getNode(),
1564 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1567 /// getGlobalBaseReg - Return an SDNode that returns the value of
1568 /// the global base register. Output instructions required to
1569 /// initialize the global base register, if necessary.
1571 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1572 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1573 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
1576 /// Atomic opcode table
1604 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1615 X86::LOCK_ADD64mi32,
1628 X86::LOCK_SUB64mi32,
1680 X86::LOCK_AND64mi32,
1693 X86::LOCK_XOR64mi32,
1698 // Return the target constant operand for atomic-load-op and do simple
1699 // translations, such as from atomic-load-add to lock-sub. The return value is
1700 // one of the following 3 cases:
1701 // + target-constant, the operand could be supported as a target constant.
1702 // + empty, the operand is not needed any more with the new op selected.
1703 // + non-empty, otherwise.
1704 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1706 enum AtomicOpc &Op, MVT NVT,
1708 const X86Subtarget *Subtarget) {
1709 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1710 int64_t CNVal = CN->getSExtValue();
1711 // Quit if not 32-bit imm.
1712 if ((int32_t)CNVal != CNVal)
1714 // Quit if INT32_MIN: it would be negated as it is negative and overflow,
1715 // producing an immediate that does not fit in the 32 bits available for
1716 // an immediate operand to sub. However, it still fits in 32 bits for the
1717 // add (since it is not negated) so we can return target-constant.
1718 if (CNVal == INT32_MIN)
1719 return CurDAG->getTargetConstant(CNVal, NVT);
1720 // For atomic-load-add, we could do some optimizations.
1722 // Translate to INC/DEC if ADD by 1 or -1.
1723 if (((CNVal == 1) || (CNVal == -1)) && !Subtarget->slowIncDec()) {
1724 Op = (CNVal == 1) ? INC : DEC;
1725 // No more constant operand after being translated into INC/DEC.
1728 // Translate to SUB if ADD by negative value.
1734 return CurDAG->getTargetConstant(CNVal, NVT);
1737 // If the value operand is single-used, try to optimize it.
1738 if (Op == ADD && Val.hasOneUse()) {
1739 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1740 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1742 return Val.getOperand(1);
1744 // A special case for i16, which needs truncating as, in most cases, it's
1745 // promoted to i32. We will translate
1746 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1747 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1748 Val.getOperand(0).getOpcode() == ISD::SUB &&
1749 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1751 Val = Val.getOperand(0);
1752 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1760 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1761 if (Node->hasAnyUseOfValue(0))
1766 // Optimize common patterns for __sync_or_and_fetch and similar arith
1767 // operations where the result is not used. This allows us to use the "lock"
1768 // version of the arithmetic instruction.
1769 SDValue Chain = Node->getOperand(0);
1770 SDValue Ptr = Node->getOperand(1);
1771 SDValue Val = Node->getOperand(2);
1772 SDValue Base, Scale, Index, Disp, Segment;
1773 if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
1776 // Which index into the table.
1778 switch (Node->getOpcode()) {
1781 case ISD::ATOMIC_LOAD_OR:
1784 case ISD::ATOMIC_LOAD_AND:
1787 case ISD::ATOMIC_LOAD_XOR:
1790 case ISD::ATOMIC_LOAD_ADD:
1795 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val, Subtarget);
1796 bool isUnOp = !Val.getNode();
1797 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1800 switch (NVT.SimpleTy) {
1801 default: return nullptr;
1804 Opc = AtomicOpcTbl[Op][ConstantI8];
1806 Opc = AtomicOpcTbl[Op][I8];
1810 if (immSext8(Val.getNode()))
1811 Opc = AtomicOpcTbl[Op][SextConstantI16];
1813 Opc = AtomicOpcTbl[Op][ConstantI16];
1815 Opc = AtomicOpcTbl[Op][I16];
1819 if (immSext8(Val.getNode()))
1820 Opc = AtomicOpcTbl[Op][SextConstantI32];
1822 Opc = AtomicOpcTbl[Op][ConstantI32];
1824 Opc = AtomicOpcTbl[Op][I32];
1828 if (immSext8(Val.getNode()))
1829 Opc = AtomicOpcTbl[Op][SextConstantI64];
1830 else if (i64immSExt32(Val.getNode()))
1831 Opc = AtomicOpcTbl[Op][ConstantI64];
1833 llvm_unreachable("True 64 bits constant in SelectAtomicLoadArith");
1835 Opc = AtomicOpcTbl[Op][I64];
1839 assert(Opc != 0 && "Invalid arith lock transform!");
1841 // Building the new node.
1844 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1845 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1847 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1848 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1851 // Copying the MachineMemOperand.
1852 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1853 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1854 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1856 // We need to have two outputs as that is what the original instruction had.
1857 // So we add a dummy, undefined output. This is safe as we checked first
1858 // that no-one uses our output anyway.
1859 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1861 SDValue RetVals[] = { Undef, Ret };
1862 return CurDAG->getMergeValues(RetVals, dl).getNode();
1865 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1866 /// any uses which require the SF or OF bits to be accurate.
1867 static bool HasNoSignedComparisonUses(SDNode *N) {
1868 // Examine each user of the node.
1869 for (SDNode::use_iterator UI = N->use_begin(),
1870 UE = N->use_end(); UI != UE; ++UI) {
1871 // Only examine CopyToReg uses.
1872 if (UI->getOpcode() != ISD::CopyToReg)
1874 // Only examine CopyToReg uses that copy to EFLAGS.
1875 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1878 // Examine each user of the CopyToReg use.
1879 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1880 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1881 // Only examine the Flag result.
1882 if (FlagUI.getUse().getResNo() != 1) continue;
1883 // Anything unusual: assume conservatively.
1884 if (!FlagUI->isMachineOpcode()) return false;
1885 // Examine the opcode of the user.
1886 switch (FlagUI->getMachineOpcode()) {
1887 // These comparisons don't treat the most significant bit specially.
1888 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1889 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1890 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1891 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1892 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
1893 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
1894 case X86::CMOVA16rr: case X86::CMOVA16rm:
1895 case X86::CMOVA32rr: case X86::CMOVA32rm:
1896 case X86::CMOVA64rr: case X86::CMOVA64rm:
1897 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1898 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1899 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1900 case X86::CMOVB16rr: case X86::CMOVB16rm:
1901 case X86::CMOVB32rr: case X86::CMOVB32rm:
1902 case X86::CMOVB64rr: case X86::CMOVB64rm:
1903 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1904 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1905 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1906 case X86::CMOVE16rr: case X86::CMOVE16rm:
1907 case X86::CMOVE32rr: case X86::CMOVE32rm:
1908 case X86::CMOVE64rr: case X86::CMOVE64rm:
1909 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1910 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1911 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1912 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1913 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1914 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1915 case X86::CMOVP16rr: case X86::CMOVP16rm:
1916 case X86::CMOVP32rr: case X86::CMOVP32rm:
1917 case X86::CMOVP64rr: case X86::CMOVP64rm:
1919 // Anything else: assume conservatively.
1920 default: return false;
1927 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1928 /// is suitable for doing the {load; increment or decrement; store} to modify
1930 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1931 SDValue StoredVal, SelectionDAG *CurDAG,
1932 LoadSDNode* &LoadNode, SDValue &InputChain) {
1934 // is the value stored the result of a DEC or INC?
1935 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1937 // is the stored value result 0 of the load?
1938 if (StoredVal.getResNo() != 0) return false;
1940 // are there other uses of the loaded value than the inc or dec?
1941 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1943 // is the store non-extending and non-indexed?
1944 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1947 SDValue Load = StoredVal->getOperand(0);
1948 // Is the stored value a non-extending and non-indexed load?
1949 if (!ISD::isNormalLoad(Load.getNode())) return false;
1951 // Return LoadNode by reference.
1952 LoadNode = cast<LoadSDNode>(Load);
1953 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1954 EVT LdVT = LoadNode->getMemoryVT();
1955 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1959 // Is store the only read of the loaded value?
1960 if (!Load.hasOneUse())
1963 // Is the address of the store the same as the load?
1964 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1965 LoadNode->getOffset() != StoreNode->getOffset())
1968 // Check if the chain is produced by the load or is a TokenFactor with
1969 // the load output chain as an operand. Return InputChain by reference.
1970 SDValue Chain = StoreNode->getChain();
1972 bool ChainCheck = false;
1973 if (Chain == Load.getValue(1)) {
1975 InputChain = LoadNode->getChain();
1976 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1977 SmallVector<SDValue, 4> ChainOps;
1978 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1979 SDValue Op = Chain.getOperand(i);
1980 if (Op == Load.getValue(1)) {
1985 // Make sure using Op as part of the chain would not cause a cycle here.
1986 // In theory, we could check whether the chain node is a predecessor of
1987 // the load. But that can be very expensive. Instead visit the uses and
1988 // make sure they all have smaller node id than the load.
1989 int LoadId = LoadNode->getNodeId();
1990 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1991 UE = UI->use_end(); UI != UE; ++UI) {
1992 if (UI.getUse().getResNo() != 0)
1994 if (UI->getNodeId() > LoadId)
1998 ChainOps.push_back(Op);
2002 // Make a new TokenFactor with all the other input chains except
2004 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2005 MVT::Other, ChainOps);
2013 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2014 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2015 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2016 if (Opc == X86ISD::DEC) {
2017 if (LdVT == MVT::i64) return X86::DEC64m;
2018 if (LdVT == MVT::i32) return X86::DEC32m;
2019 if (LdVT == MVT::i16) return X86::DEC16m;
2020 if (LdVT == MVT::i8) return X86::DEC8m;
2022 assert(Opc == X86ISD::INC && "unrecognized opcode");
2023 if (LdVT == MVT::i64) return X86::INC64m;
2024 if (LdVT == MVT::i32) return X86::INC32m;
2025 if (LdVT == MVT::i16) return X86::INC16m;
2026 if (LdVT == MVT::i8) return X86::INC8m;
2028 llvm_unreachable("unrecognized size for LdVT");
2031 /// SelectGather - Customized ISel for GATHER operations.
2033 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2034 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2035 SDValue Chain = Node->getOperand(0);
2036 SDValue VSrc = Node->getOperand(2);
2037 SDValue Base = Node->getOperand(3);
2038 SDValue VIdx = Node->getOperand(4);
2039 SDValue VMask = Node->getOperand(5);
2040 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2044 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2047 // Memory Operands: Base, Scale, Index, Disp, Segment
2048 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
2049 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2050 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
2051 Disp, Segment, VMask, Chain};
2052 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
2053 // Node has 2 outputs: VDst and MVT::Other.
2054 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2055 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2057 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2058 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2062 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2063 MVT NVT = Node->getSimpleValueType(0);
2065 unsigned Opcode = Node->getOpcode();
2068 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2070 if (Node->isMachineOpcode()) {
2071 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2072 Node->setNodeId(-1);
2073 return nullptr; // Already selected.
2078 case ISD::INTRINSIC_W_CHAIN: {
2079 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2082 case Intrinsic::x86_avx2_gather_d_pd:
2083 case Intrinsic::x86_avx2_gather_d_pd_256:
2084 case Intrinsic::x86_avx2_gather_q_pd:
2085 case Intrinsic::x86_avx2_gather_q_pd_256:
2086 case Intrinsic::x86_avx2_gather_d_ps:
2087 case Intrinsic::x86_avx2_gather_d_ps_256:
2088 case Intrinsic::x86_avx2_gather_q_ps:
2089 case Intrinsic::x86_avx2_gather_q_ps_256:
2090 case Intrinsic::x86_avx2_gather_d_q:
2091 case Intrinsic::x86_avx2_gather_d_q_256:
2092 case Intrinsic::x86_avx2_gather_q_q:
2093 case Intrinsic::x86_avx2_gather_q_q_256:
2094 case Intrinsic::x86_avx2_gather_d_d:
2095 case Intrinsic::x86_avx2_gather_d_d_256:
2096 case Intrinsic::x86_avx2_gather_q_d:
2097 case Intrinsic::x86_avx2_gather_q_d_256: {
2098 if (!Subtarget->hasAVX2())
2102 default: llvm_unreachable("Impossible intrinsic");
2103 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2104 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2105 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2106 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2107 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2108 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2109 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2110 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2111 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2112 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2113 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2114 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2115 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2116 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2117 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2118 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2120 SDNode *RetVal = SelectGather(Node, Opc);
2122 // We already called ReplaceUses inside SelectGather.
2129 case X86ISD::GlobalBaseReg:
2130 return getGlobalBaseReg();
2132 case X86ISD::SHRUNKBLEND: {
2133 // SHRUNKBLEND selects like a regular VSELECT.
2134 SDValue VSelect = CurDAG->getNode(
2135 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2136 Node->getOperand(1), Node->getOperand(2));
2137 ReplaceUses(SDValue(Node, 0), VSelect);
2138 SelectCode(VSelect.getNode());
2139 // We already called ReplaceUses.
2143 case ISD::ATOMIC_LOAD_XOR:
2144 case ISD::ATOMIC_LOAD_AND:
2145 case ISD::ATOMIC_LOAD_OR:
2146 case ISD::ATOMIC_LOAD_ADD: {
2147 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2155 // For operations of the form (x << C1) op C2, check if we can use a smaller
2156 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2157 SDValue N0 = Node->getOperand(0);
2158 SDValue N1 = Node->getOperand(1);
2160 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2163 // i8 is unshrinkable, i16 should be promoted to i32.
2164 if (NVT != MVT::i32 && NVT != MVT::i64)
2167 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2168 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2169 if (!Cst || !ShlCst)
2172 int64_t Val = Cst->getSExtValue();
2173 uint64_t ShlVal = ShlCst->getZExtValue();
2175 // Make sure that we don't change the operation by removing bits.
2176 // This only matters for OR and XOR, AND is unaffected.
2177 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2178 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2184 // Check the minimum bitwidth for the new constant.
2185 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2186 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2187 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2188 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2190 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2193 // Bail if there is no smaller encoding.
2197 switch (NVT.SimpleTy) {
2198 default: llvm_unreachable("Unsupported VT!");
2200 assert(CstVT == MVT::i8);
2201 ShlOp = X86::SHL32ri;
2204 default: llvm_unreachable("Impossible opcode");
2205 case ISD::AND: Op = X86::AND32ri8; break;
2206 case ISD::OR: Op = X86::OR32ri8; break;
2207 case ISD::XOR: Op = X86::XOR32ri8; break;
2211 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2212 ShlOp = X86::SHL64ri;
2215 default: llvm_unreachable("Impossible opcode");
2216 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2217 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2218 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2223 // Emit the smaller op and the shift.
2224 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2225 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2226 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2230 case X86ISD::SMUL8: {
2231 SDValue N0 = Node->getOperand(0);
2232 SDValue N1 = Node->getOperand(1);
2234 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2236 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2237 N0, SDValue()).getValue(1);
2239 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2240 SDValue Ops[] = {N1, InFlag};
2241 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2243 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2244 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2248 case X86ISD::UMUL: {
2249 SDValue N0 = Node->getOperand(0);
2250 SDValue N1 = Node->getOperand(1);
2253 switch (NVT.SimpleTy) {
2254 default: llvm_unreachable("Unsupported VT!");
2255 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2256 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2257 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2258 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2261 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2262 N0, SDValue()).getValue(1);
2264 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2265 SDValue Ops[] = {N1, InFlag};
2266 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2268 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2269 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2270 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2274 case ISD::SMUL_LOHI:
2275 case ISD::UMUL_LOHI: {
2276 SDValue N0 = Node->getOperand(0);
2277 SDValue N1 = Node->getOperand(1);
2279 bool isSigned = Opcode == ISD::SMUL_LOHI;
2280 bool hasBMI2 = Subtarget->hasBMI2();
2282 switch (NVT.SimpleTy) {
2283 default: llvm_unreachable("Unsupported VT!");
2284 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2285 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2286 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2287 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2288 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2289 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2292 switch (NVT.SimpleTy) {
2293 default: llvm_unreachable("Unsupported VT!");
2294 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2295 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2296 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2297 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2301 unsigned SrcReg, LoReg, HiReg;
2303 default: llvm_unreachable("Unknown MUL opcode!");
2306 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2310 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2314 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2318 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2321 SrcReg = X86::EDX; LoReg = HiReg = 0;
2324 SrcReg = X86::RDX; LoReg = HiReg = 0;
2328 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2329 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2330 // Multiply is commmutative.
2332 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2337 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2338 N0, SDValue()).getValue(1);
2339 SDValue ResHi, ResLo;
2343 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2345 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2346 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2347 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2348 ResHi = SDValue(CNode, 0);
2349 ResLo = SDValue(CNode, 1);
2350 Chain = SDValue(CNode, 2);
2351 InFlag = SDValue(CNode, 3);
2353 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2354 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2355 Chain = SDValue(CNode, 0);
2356 InFlag = SDValue(CNode, 1);
2359 // Update the chain.
2360 ReplaceUses(N1.getValue(1), Chain);
2362 SDValue Ops[] = { N1, InFlag };
2363 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2364 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2365 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2366 ResHi = SDValue(CNode, 0);
2367 ResLo = SDValue(CNode, 1);
2368 InFlag = SDValue(CNode, 2);
2370 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2371 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2372 InFlag = SDValue(CNode, 0);
2376 // Prevent use of AH in a REX instruction by referencing AX instead.
2377 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2378 !SDValue(Node, 1).use_empty()) {
2379 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2380 X86::AX, MVT::i16, InFlag);
2381 InFlag = Result.getValue(2);
2382 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2384 if (!SDValue(Node, 0).use_empty())
2385 ReplaceUses(SDValue(Node, 1),
2386 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2388 // Shift AX down 8 bits.
2389 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2391 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2392 // Then truncate it down to i8.
2393 ReplaceUses(SDValue(Node, 1),
2394 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2396 // Copy the low half of the result, if it is needed.
2397 if (!SDValue(Node, 0).use_empty()) {
2398 if (!ResLo.getNode()) {
2399 assert(LoReg && "Register for low half is not defined!");
2400 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2402 InFlag = ResLo.getValue(2);
2404 ReplaceUses(SDValue(Node, 0), ResLo);
2405 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2407 // Copy the high half of the result, if it is needed.
2408 if (!SDValue(Node, 1).use_empty()) {
2409 if (!ResHi.getNode()) {
2410 assert(HiReg && "Register for high half is not defined!");
2411 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2413 InFlag = ResHi.getValue(2);
2415 ReplaceUses(SDValue(Node, 1), ResHi);
2416 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2424 case X86ISD::SDIVREM8_SEXT_HREG:
2425 case X86ISD::UDIVREM8_ZEXT_HREG: {
2426 SDValue N0 = Node->getOperand(0);
2427 SDValue N1 = Node->getOperand(1);
2429 bool isSigned = (Opcode == ISD::SDIVREM ||
2430 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2432 switch (NVT.SimpleTy) {
2433 default: llvm_unreachable("Unsupported VT!");
2434 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2435 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2436 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2437 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2440 switch (NVT.SimpleTy) {
2441 default: llvm_unreachable("Unsupported VT!");
2442 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2443 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2444 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2445 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2449 unsigned LoReg, HiReg, ClrReg;
2450 unsigned SExtOpcode;
2451 switch (NVT.SimpleTy) {
2452 default: llvm_unreachable("Unsupported VT!");
2454 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2455 SExtOpcode = X86::CBW;
2458 LoReg = X86::AX; HiReg = X86::DX;
2460 SExtOpcode = X86::CWD;
2463 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2464 SExtOpcode = X86::CDQ;
2467 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2468 SExtOpcode = X86::CQO;
2472 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2473 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2474 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2477 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2478 // Special case for div8, just use a move with zero extension to AX to
2479 // clear the upper 8 bits (AH).
2480 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2481 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2482 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2484 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2485 MVT::Other, Ops), 0);
2486 Chain = Move.getValue(1);
2487 ReplaceUses(N0.getValue(1), Chain);
2490 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2491 Chain = CurDAG->getEntryNode();
2493 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2494 InFlag = Chain.getValue(1);
2497 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2498 LoReg, N0, SDValue()).getValue(1);
2499 if (isSigned && !signBitIsZero) {
2500 // Sign extend the low part into the high part.
2502 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2504 // Zero out the high part, effectively zero extending the input.
2505 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2506 switch (NVT.SimpleTy) {
2509 SDValue(CurDAG->getMachineNode(
2510 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2511 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2518 SDValue(CurDAG->getMachineNode(
2519 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2520 CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
2521 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2525 llvm_unreachable("Unexpected division source");
2528 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2529 ClrNode, InFlag).getValue(1);
2534 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2537 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2538 InFlag = SDValue(CNode, 1);
2539 // Update the chain.
2540 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2543 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2546 // Prevent use of AH in a REX instruction by explicitly copying it to
2547 // an ABCD_L register.
2549 // The current assumption of the register allocator is that isel
2550 // won't generate explicit references to the GR8_ABCD_H registers. If
2551 // the allocator and/or the backend get enhanced to be more robust in
2552 // that regard, this can be, and should be, removed.
2553 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2554 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2555 unsigned AHExtOpcode =
2556 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2558 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2559 MVT::Glue, AHCopy, InFlag);
2560 SDValue Result(RNode, 0);
2561 InFlag = SDValue(RNode, 1);
2563 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2564 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2565 if (Node->getValueType(1) == MVT::i64) {
2566 // It's not possible to directly movsx AH to a 64bit register, because
2567 // the latter needs the REX prefix, but the former can't have it.
2568 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2569 "Unexpected i64 sext of h-register");
2571 SDValue(CurDAG->getMachineNode(
2572 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2573 CurDAG->getTargetConstant(0, MVT::i64), Result,
2574 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2579 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2581 ReplaceUses(SDValue(Node, 1), Result);
2582 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2584 // Copy the division (low) result, if it is needed.
2585 if (!SDValue(Node, 0).use_empty()) {
2586 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2587 LoReg, NVT, InFlag);
2588 InFlag = Result.getValue(2);
2589 ReplaceUses(SDValue(Node, 0), Result);
2590 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2592 // Copy the remainder (high) result, if it is needed.
2593 if (!SDValue(Node, 1).use_empty()) {
2594 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2595 HiReg, NVT, InFlag);
2596 InFlag = Result.getValue(2);
2597 ReplaceUses(SDValue(Node, 1), Result);
2598 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2605 // Sometimes a SUB is used to perform comparison.
2606 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2607 // This node is not a CMP.
2609 SDValue N0 = Node->getOperand(0);
2610 SDValue N1 = Node->getOperand(1);
2612 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2613 HasNoSignedComparisonUses(Node))
2614 N0 = N0.getOperand(0);
2616 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2617 // use a smaller encoding.
2618 // Look past the truncate if CMP is the only use of it.
2619 if ((N0.getNode()->getOpcode() == ISD::AND ||
2620 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2621 N0.getNode()->hasOneUse() &&
2622 N0.getValueType() != MVT::i8 &&
2623 X86::isZeroNode(N1)) {
2624 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2627 // For example, convert "testl %eax, $8" to "testb %al, $8"
2628 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2629 (!(C->getZExtValue() & 0x80) ||
2630 HasNoSignedComparisonUses(Node))) {
2631 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2632 SDValue Reg = N0.getNode()->getOperand(0);
2634 // On x86-32, only the ABCD registers have 8-bit subregisters.
2635 if (!Subtarget->is64Bit()) {
2636 const TargetRegisterClass *TRC;
2637 switch (N0.getSimpleValueType().SimpleTy) {
2638 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2639 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2640 default: llvm_unreachable("Unsupported TEST operand type!");
2642 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2643 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2644 Reg.getValueType(), Reg, RC), 0);
2647 // Extract the l-register.
2648 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2652 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2654 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2655 // one, do not call ReplaceAllUsesWith.
2656 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2657 SDValue(NewNode, 0));
2661 // For example, "testl %eax, $2048" to "testb %ah, $8".
2662 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2663 (!(C->getZExtValue() & 0x8000) ||
2664 HasNoSignedComparisonUses(Node))) {
2665 // Shift the immediate right by 8 bits.
2666 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2668 SDValue Reg = N0.getNode()->getOperand(0);
2670 // Put the value in an ABCD register.
2671 const TargetRegisterClass *TRC;
2672 switch (N0.getSimpleValueType().SimpleTy) {
2673 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2674 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2675 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2676 default: llvm_unreachable("Unsupported TEST operand type!");
2678 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2679 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2680 Reg.getValueType(), Reg, RC), 0);
2682 // Extract the h-register.
2683 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2686 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2687 // target GR8_NOREX registers, so make sure the register class is
2689 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2690 MVT::i32, Subreg, ShiftedImm);
2691 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2692 // one, do not call ReplaceAllUsesWith.
2693 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2694 SDValue(NewNode, 0));
2698 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2699 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2700 N0.getValueType() != MVT::i16 &&
2701 (!(C->getZExtValue() & 0x8000) ||
2702 HasNoSignedComparisonUses(Node))) {
2703 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2704 SDValue Reg = N0.getNode()->getOperand(0);
2706 // Extract the 16-bit subregister.
2707 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2711 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2713 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2714 // one, do not call ReplaceAllUsesWith.
2715 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2716 SDValue(NewNode, 0));
2720 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2721 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2722 N0.getValueType() == MVT::i64 &&
2723 (!(C->getZExtValue() & 0x80000000) ||
2724 HasNoSignedComparisonUses(Node))) {
2725 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2726 SDValue Reg = N0.getNode()->getOperand(0);
2728 // Extract the 32-bit subregister.
2729 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2733 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2735 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2736 // one, do not call ReplaceAllUsesWith.
2737 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2738 SDValue(NewNode, 0));
2745 // Change a chain of {load; incr or dec; store} of the same value into
2746 // a simple increment or decrement through memory of that value, if the
2747 // uses of the modified value and its address are suitable.
2748 // The DEC64m tablegen pattern is currently not able to match the case where
2749 // the EFLAGS on the original DEC are used. (This also applies to
2750 // {INC,DEC}X{64,32,16,8}.)
2751 // We'll need to improve tablegen to allow flags to be transferred from a
2752 // node in the pattern to the result node. probably with a new keyword
2753 // for example, we have this
2754 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2755 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2756 // (implicit EFLAGS)]>;
2757 // but maybe need something like this
2758 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2759 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2760 // (transferrable EFLAGS)]>;
2762 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2763 SDValue StoredVal = StoreNode->getOperand(1);
2764 unsigned Opc = StoredVal->getOpcode();
2766 LoadSDNode *LoadNode = nullptr;
2768 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2769 LoadNode, InputChain))
2772 SDValue Base, Scale, Index, Disp, Segment;
2773 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2774 Base, Scale, Index, Disp, Segment))
2777 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2778 MemOp[0] = StoreNode->getMemOperand();
2779 MemOp[1] = LoadNode->getMemOperand();
2780 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2781 EVT LdVT = LoadNode->getMemoryVT();
2782 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2783 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2785 MVT::i32, MVT::Other, Ops);
2786 Result->setMemRefs(MemOp, MemOp + 2);
2788 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2789 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2795 SDNode *ResNode = SelectCode(Node);
2797 DEBUG(dbgs() << "=> ";
2798 if (ResNode == nullptr || ResNode == Node)
2801 ResNode->dump(CurDAG);
2807 bool X86DAGToDAGISel::
2808 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2809 std::vector<SDValue> &OutOps) {
2810 SDValue Op0, Op1, Op2, Op3, Op4;
2811 switch (ConstraintCode) {
2812 case 'o': // offsetable ??
2813 case 'v': // not offsetable ??
2814 default: return true;
2816 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2821 OutOps.push_back(Op0);
2822 OutOps.push_back(Op1);
2823 OutOps.push_back(Op2);
2824 OutOps.push_back(Op3);
2825 OutOps.push_back(Op4);
2829 /// createX86ISelDag - This pass converts a legalized DAG into a
2830 /// X86-specific DAG, ready for instruction scheduling.
2832 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2833 CodeGenOpt::Level OptLevel) {
2834 return new X86DAGToDAGISel(TM, OptLevel);