1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 // FIXME: completely move here.
38 extern cl::opt<bool> ForceStackAlign;
40 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
41 return !MF.getFrameInfo()->hasVarSizedObjects() &&
42 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
45 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
46 /// call frame pseudos can be simplified. Having a FP, as in the default
47 /// implementation, is not sufficient here since we can't always use it.
48 /// Use a more nuanced condition.
50 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
51 const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>
52 (MF.getSubtarget().getRegisterInfo());
53 return hasReservedCallFrame(MF) ||
54 (hasFP(MF) && !TRI->needsStackRealignment(MF))
55 || TRI->hasBasePointer(MF);
58 // needsFrameIndexResolution - Do we need to perform FI resolution for
59 // this function. Normally, this is required only when the function
60 // has any stack objects. However, FI resolution actually has another job,
61 // not apparent from the title - it resolves callframesetup/destroy
62 // that were not simplified earlier.
63 // So, this is required for x86 functions that have push sequences even
64 // when there are no stack objects.
66 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
67 return MF.getFrameInfo()->hasStackObjects() ||
68 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
71 /// hasFP - Return true if the specified function should have a dedicated frame
72 /// pointer register. This is true if the function has variable sized allocas
73 /// or if frame pointer elimination is disabled.
74 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
75 const MachineFrameInfo *MFI = MF.getFrameInfo();
76 const MachineModuleInfo &MMI = MF.getMMI();
77 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
79 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
80 RegInfo->needsStackRealignment(MF) ||
81 MFI->hasVarSizedObjects() ||
82 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
83 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
84 MMI.callsUnwindInit() || MMI.callsEHReturn() ||
85 MFI->hasStackMap() || MFI->hasPatchPoint());
88 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
92 return X86::SUB64ri32;
100 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
103 return X86::ADD64ri8;
104 return X86::ADD64ri32;
107 return X86::ADD32ri8;
112 static unsigned getSUBrrOpcode(unsigned isLP64) {
113 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
116 static unsigned getADDrrOpcode(unsigned isLP64) {
117 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
120 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
123 return X86::AND64ri8;
124 return X86::AND64ri32;
127 return X86::AND32ri8;
131 static unsigned getLEArOpcode(unsigned IsLP64) {
132 return IsLP64 ? X86::LEA64r : X86::LEA32r;
135 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
136 /// when it reaches the "return" instruction. We can then pop a stack object
137 /// to this register without worry about clobbering it.
138 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator &MBBI,
140 const TargetRegisterInfo &TRI,
142 const MachineFunction *MF = MBB.getParent();
143 const Function *F = MF->getFunction();
144 if (!F || MF->getMMI().callsEHReturn())
147 static const uint16_t CallerSavedRegs32Bit[] = {
148 X86::EAX, X86::EDX, X86::ECX, 0
151 static const uint16_t CallerSavedRegs64Bit[] = {
152 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
153 X86::R8, X86::R9, X86::R10, X86::R11, 0
156 unsigned Opc = MBBI->getOpcode();
163 case X86::TCRETURNdi:
164 case X86::TCRETURNri:
165 case X86::TCRETURNmi:
166 case X86::TCRETURNdi64:
167 case X86::TCRETURNri64:
168 case X86::TCRETURNmi64:
170 case X86::EH_RETURN64: {
171 SmallSet<uint16_t, 8> Uses;
172 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
173 MachineOperand &MO = MBBI->getOperand(i);
174 if (!MO.isReg() || MO.isDef())
176 unsigned Reg = MO.getReg();
179 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
183 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
185 if (!Uses.count(*CS))
193 static bool isEAXLiveIn(MachineFunction &MF) {
194 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
195 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
196 unsigned Reg = II->first;
198 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
199 Reg == X86::AH || Reg == X86::AL)
206 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
207 /// stack pointer by a constant value.
209 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
210 unsigned StackPtr, int64_t NumBytes,
211 bool Is64BitTarget, bool Is64BitStackPtr, bool UseLEA,
212 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
213 bool isSub = NumBytes < 0;
214 uint64_t Offset = isSub ? -NumBytes : NumBytes;
217 Opc = getLEArOpcode(Is64BitStackPtr);
220 ? getSUBriOpcode(Is64BitStackPtr, Offset)
221 : getADDriOpcode(Is64BitStackPtr, Offset);
223 uint64_t Chunk = (1LL << 31) - 1;
224 DebugLoc DL = MBB.findDebugLoc(MBBI);
227 if (Offset > Chunk) {
228 // Rather than emit a long series of instructions for large offsets,
229 // load the offset into a register and do one sub/add
232 if (isSub && !isEAXLiveIn(*MBB.getParent()))
233 Reg = (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX);
235 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
238 Opc = Is64BitTarget ? X86::MOV64ri : X86::MOV32ri;
239 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
242 ? getSUBrrOpcode(Is64BitTarget)
243 : getADDrrOpcode(Is64BitTarget);
244 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
247 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
253 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
254 if (ThisVal == (Is64BitTarget ? 8 : 4)) {
255 // Use push / pop instead.
257 ? (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX)
258 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
261 ? (Is64BitTarget ? X86::PUSH64r : X86::PUSH32r)
262 : (Is64BitTarget ? X86::POP64r : X86::POP32r);
263 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
264 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
266 MI->setFlag(MachineInstr::FrameSetup);
272 MachineInstr *MI = nullptr;
275 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
276 StackPtr, false, isSub ? -ThisVal : ThisVal);
278 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
281 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
285 MI->setFlag(MachineInstr::FrameSetup);
291 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
293 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
294 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
295 if (MBBI == MBB.begin()) return;
297 MachineBasicBlock::iterator PI = std::prev(MBBI);
298 unsigned Opc = PI->getOpcode();
299 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
300 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
301 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
302 PI->getOperand(0).getReg() == StackPtr) {
304 *NumBytes += PI->getOperand(2).getImm();
306 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
307 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
308 PI->getOperand(0).getReg() == StackPtr) {
310 *NumBytes -= PI->getOperand(2).getImm();
315 /// mergeSPUpdates - Checks the instruction before/after the passed
316 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
317 /// the stack adjustment is returned as a positive value for ADD/LEA and a
318 /// negative for SUB.
319 static int mergeSPUpdates(MachineBasicBlock &MBB,
320 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
321 bool doMergeWithPrevious) {
322 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
323 (!doMergeWithPrevious && MBBI == MBB.end()))
326 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
327 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
329 unsigned Opc = PI->getOpcode();
332 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
333 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
334 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
335 PI->getOperand(0).getReg() == StackPtr){
336 Offset += PI->getOperand(2).getImm();
338 if (!doMergeWithPrevious) MBBI = NI;
339 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
340 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
341 PI->getOperand(0).getReg() == StackPtr) {
342 Offset -= PI->getOperand(2).getImm();
344 if (!doMergeWithPrevious) MBBI = NI;
351 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator MBBI,
354 MachineFunction &MF = *MBB.getParent();
355 MachineFrameInfo *MFI = MF.getFrameInfo();
356 MachineModuleInfo &MMI = MF.getMMI();
357 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
358 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
360 // Add callee saved registers to move list.
361 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
362 if (CSI.empty()) return;
364 // Calculate offsets.
365 for (std::vector<CalleeSavedInfo>::const_iterator
366 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
367 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
368 unsigned Reg = I->getReg();
370 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
372 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
374 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
375 .addCFIIndex(CFIIndex);
379 /// usesTheStack - This function checks if any of the users of EFLAGS
380 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
381 /// to use the stack, and if we don't adjust the stack we clobber the first
383 /// See X86InstrInfo::copyPhysReg.
384 static bool usesTheStack(const MachineFunction &MF) {
385 const MachineRegisterInfo &MRI = MF.getRegInfo();
387 for (MachineRegisterInfo::reg_instr_iterator
388 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
396 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
397 MachineBasicBlock &MBB,
398 MachineBasicBlock::iterator MBBI,
400 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
401 const TargetInstrInfo &TII = *STI.getInstrInfo();
402 bool Is64Bit = STI.is64Bit();
403 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
407 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
409 CallOp = X86::CALLpcrel32;
413 if (STI.isTargetCygMing()) {
414 Symbol = "___chkstk_ms";
418 } else if (STI.isTargetCygMing())
423 MachineInstrBuilder CI;
425 // All current stack probes take AX and SP as input, clobber flags, and
426 // preserve all registers. x86_64 probes leave RSP unmodified.
427 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
428 // For the large code model, we have to call through a register. Use R11,
429 // as it is scratch in all supported calling conventions.
430 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
431 .addExternalSymbol(Symbol);
432 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
434 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
437 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
438 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
439 CI.addReg(AX, RegState::Implicit)
440 .addReg(SP, RegState::Implicit)
441 .addReg(AX, RegState::Define | RegState::Implicit)
442 .addReg(SP, RegState::Define | RegState::Implicit)
443 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
446 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
447 // themselves. It also does not clobber %rax so we can reuse it when
449 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
455 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
456 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
457 // and might require smaller successive adjustments.
458 const uint64_t Win64MaxSEHOffset = 128;
459 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
460 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
461 return SEHFrameOffset & -16;
464 // If we're forcing a stack realignment we can't rely on just the frame
465 // info, we need to know the ABI stack alignment as well in case we
466 // have a call out. Otherwise just make sure we have some alignment - we'll
467 // go with the minimum SlotSize.
468 static uint64_t calculateMaxStackAlign(const MachineFunction &MF) {
469 const MachineFrameInfo *MFI = MF.getFrameInfo();
470 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
471 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
472 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
473 unsigned SlotSize = RegInfo->getSlotSize();
474 unsigned StackAlign = STI.getFrameLowering()->getStackAlignment();
475 if (ForceStackAlign) {
477 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
478 else if (MaxAlign < SlotSize)
484 /// emitPrologue - Push callee-saved registers onto the stack, which
485 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
486 /// space for local variables. Also emit labels used by the exception handler to
487 /// generate the exception handling frames.
490 Here's a gist of what gets emitted:
492 ; Establish frame pointer, if needed
495 .cfi_def_cfa_offset 16
496 .cfi_offset %rbp, -16
499 .cfi_def_cfa_register %rbp
501 ; Spill general-purpose registers
502 [for all callee-saved GPRs]
505 .cfi_def_cfa_offset (offset from RETADDR)
508 ; If the required stack alignment > default stack alignment
509 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
510 ; of unknown size in the stack frame.
511 [if stack needs re-alignment]
514 ; Allocate space for locals
515 [if target is Windows and allocated space > 4096 bytes]
516 ; Windows needs special care for allocations larger
519 call ___chkstk_ms/___chkstk
525 .seh_stackalloc (size of XMM spill slots)
526 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
531 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
532 ; they may get spilled on any platform, if the current function
533 ; calls @llvm.eh.unwind.init
535 [for all callee-saved XMM registers]
536 movaps %<xmm reg>, -MMM(%rbp)
537 [for all callee-saved XMM registers]
538 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
539 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
541 [for all callee-saved XMM registers]
542 movaps %<xmm reg>, KKK(%rsp)
543 [for all callee-saved XMM registers]
544 .seh_savexmm %<xmm reg>, KKK
548 [if needs base pointer]
550 [if needs to restore base pointer]
555 [for all callee-saved registers]
556 .cfi_offset %<reg>, (offset from %rbp)
558 .cfi_def_cfa_offset (offset from RETADDR)
559 [for all callee-saved registers]
560 .cfi_offset %<reg>, (offset from %rsp)
563 - .seh directives are emitted only for Windows 64 ABI
564 - .cfi directives are emitted for all other ABIs
565 - for 32-bit code, substitute %e?? registers for %r??
568 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
569 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
570 MachineBasicBlock::iterator MBBI = MBB.begin();
571 MachineFrameInfo *MFI = MF.getFrameInfo();
572 const Function *Fn = MF.getFunction();
573 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
574 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
575 const TargetInstrInfo &TII = *STI.getInstrInfo();
576 MachineModuleInfo &MMI = MF.getMMI();
577 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
578 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
579 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
580 bool HasFP = hasFP(MF);
581 bool Is64Bit = STI.is64Bit();
582 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
583 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
584 bool IsWin64 = STI.isTargetWin64();
585 // Not necessarily synonymous with IsWin64.
586 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
587 bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
589 !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
590 bool UseLEA = STI.useLeaForSP();
591 unsigned SlotSize = RegInfo->getSlotSize();
592 unsigned FramePtr = RegInfo->getFrameRegister(MF);
593 const unsigned MachineFramePtr =
594 STI.isTarget64BitILP32()
595 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
597 unsigned StackPtr = RegInfo->getStackRegister();
598 unsigned BasePtr = RegInfo->getBaseRegister();
601 // Add RETADDR move area to callee saved frame size.
602 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
603 if (TailCallReturnAddrDelta && IsWinEH)
604 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
606 if (TailCallReturnAddrDelta < 0)
607 X86FI->setCalleeSavedFrameSize(
608 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
610 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
612 // The default stack probe size is 4096 if the function has no stackprobesize
614 unsigned StackProbeSize = 4096;
615 if (Fn->hasFnAttribute("stack-probe-size"))
616 Fn->getFnAttribute("stack-probe-size")
618 .getAsInteger(0, StackProbeSize);
620 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
621 // function, and use up to 128 bytes of stack space, don't have a frame
622 // pointer, calls, or dynamic alloca then we do not need to adjust the
623 // stack pointer (we fit in the Red Zone). We also check that we don't
624 // push and pop from the stack.
625 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
626 !RegInfo->needsStackRealignment(MF) &&
627 !MFI->hasVarSizedObjects() && // No dynamic alloca.
628 !MFI->adjustsStack() && // No calls.
629 !IsWin64 && // Win64 has no Red Zone
630 !usesTheStack(MF) && // Don't push and pop.
631 !MF.shouldSplitStack()) { // Regular stack
632 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
633 if (HasFP) MinSize += SlotSize;
634 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
635 MFI->setStackSize(StackSize);
638 // Insert stack pointer adjustment for later moving of return addr. Only
639 // applies to tail call optimized functions where the callee argument stack
640 // size is bigger than the callers.
641 if (TailCallReturnAddrDelta < 0) {
643 BuildMI(MBB, MBBI, DL,
644 TII.get(getSUBriOpcode(Uses64BitFramePtr, -TailCallReturnAddrDelta)),
647 .addImm(-TailCallReturnAddrDelta)
648 .setMIFlag(MachineInstr::FrameSetup);
649 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
652 // Mapping for machine moves:
654 // DST: VirtualFP AND
655 // SRC: VirtualFP => DW_CFA_def_cfa_offset
656 // ELSE => DW_CFA_def_cfa
658 // SRC: VirtualFP AND
659 // DST: Register => DW_CFA_def_cfa_register
662 // OFFSET < 0 => DW_CFA_offset_extended_sf
663 // REG < 64 => DW_CFA_offset + Reg
664 // ELSE => DW_CFA_offset_extended
666 uint64_t NumBytes = 0;
667 int stackGrowth = -SlotSize;
670 // Calculate required stack adjustment.
671 uint64_t FrameSize = StackSize - SlotSize;
672 // If required, include space for extra hidden slot for stashing base pointer.
673 if (X86FI->getRestoreBasePointer())
674 FrameSize += SlotSize;
676 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
678 // Callee-saved registers are pushed on stack before the stack is realigned.
679 if (RegInfo->needsStackRealignment(MF) && !IsWinEH)
680 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
682 // Get the offset of the stack slot for the EBP register, which is
683 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
684 // Update the frame offset adjustment.
685 MFI->setOffsetAdjustment(-NumBytes);
687 // Save EBP/RBP into the appropriate stack slot.
688 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
689 .addReg(MachineFramePtr, RegState::Kill)
690 .setMIFlag(MachineInstr::FrameSetup);
693 // Mark the place where EBP/RBP was saved.
694 // Define the current CFA rule to use the provided offset.
696 unsigned CFIIndex = MMI.addFrameInst(
697 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
698 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
699 .addCFIIndex(CFIIndex);
701 // Change the rule for the FramePtr to be an "offset" rule.
702 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
703 CFIIndex = MMI.addFrameInst(
704 MCCFIInstruction::createOffset(nullptr,
705 DwarfFramePtr, 2 * stackGrowth));
706 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
707 .addCFIIndex(CFIIndex);
711 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
713 .setMIFlag(MachineInstr::FrameSetup);
717 // Update EBP with the new base value.
718 BuildMI(MBB, MBBI, DL,
719 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
722 .setMIFlag(MachineInstr::FrameSetup);
726 // Mark effective beginning of when frame pointer becomes valid.
727 // Define the current CFA to use the EBP/RBP register.
728 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
729 unsigned CFIIndex = MMI.addFrameInst(
730 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
731 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
732 .addCFIIndex(CFIIndex);
735 // Mark the FramePtr as live-in in every block.
736 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
737 I->addLiveIn(MachineFramePtr);
739 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
742 // Skip the callee-saved push instructions.
743 bool PushedRegs = false;
744 int StackOffset = 2 * stackGrowth;
746 while (MBBI != MBB.end() &&
747 (MBBI->getOpcode() == X86::PUSH32r ||
748 MBBI->getOpcode() == X86::PUSH64r)) {
750 unsigned Reg = MBBI->getOperand(0).getReg();
753 if (!HasFP && NeedsDwarfCFI) {
754 // Mark callee-saved push instruction.
755 // Define the current CFA rule to use the provided offset.
757 unsigned CFIIndex = MMI.addFrameInst(
758 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
759 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
760 .addCFIIndex(CFIIndex);
761 StackOffset += stackGrowth;
765 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
766 MachineInstr::FrameSetup);
770 // Realign stack after we pushed callee-saved registers (so that we'll be
771 // able to calculate their offsets from the frame pointer).
772 // Don't do this for Win64, it needs to realign the stack after the prologue.
773 if (!IsWinEH && RegInfo->needsStackRealignment(MF)) {
774 assert(HasFP && "There should be a frame pointer if stack is realigned.");
775 uint64_t Val = -MaxAlign;
777 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
781 .setMIFlag(MachineInstr::FrameSetup);
783 // The EFLAGS implicit def is dead.
784 MI->getOperand(3).setIsDead();
787 // If there is an SUB32ri of ESP immediately before this instruction, merge
788 // the two. This can be the case when tail call elimination is enabled and
789 // the callee has more arguments then the caller.
790 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
792 // Adjust stack pointer: ESP -= numbytes.
794 // Windows and cygwin/mingw require a prologue helper routine when allocating
795 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
796 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
797 // stack and adjust the stack pointer in one go. The 64-bit version of
798 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
799 // responsible for adjusting the stack pointer. Touching the stack at 4K
800 // increments is necessary to ensure that the guard pages used by the OS
801 // virtual memory manager are allocated in correct sequence.
802 uint64_t AlignedNumBytes = NumBytes;
803 if (IsWinEH && RegInfo->needsStackRealignment(MF))
804 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
805 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
806 // Check whether EAX is livein for this function.
807 bool isEAXAlive = isEAXLiveIn(MF);
810 // Sanity check that EAX is not livein for this function.
811 // It should not be, so throw an assert.
812 assert(!Is64Bit && "EAX is livein in x64 case!");
815 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
816 .addReg(X86::EAX, RegState::Kill)
817 .setMIFlag(MachineInstr::FrameSetup);
821 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
822 // Function prologue is responsible for adjusting the stack pointer.
823 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
825 .setMIFlag(MachineInstr::FrameSetup);
827 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
828 // We'll also use 4 already allocated bytes for EAX.
829 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
830 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
831 .setMIFlag(MachineInstr::FrameSetup);
834 // Save a pointer to the MI where we set AX.
835 MachineBasicBlock::iterator SetRAX = MBBI;
838 // Call __chkstk, __chkstk_ms, or __alloca.
839 emitStackProbeCall(MF, MBB, MBBI, DL);
841 // Apply the frame setup flag to all inserted instrs.
842 for (; SetRAX != MBBI; ++SetRAX)
843 SetRAX->setFlag(MachineInstr::FrameSetup);
847 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
849 StackPtr, false, NumBytes - 4);
850 MI->setFlag(MachineInstr::FrameSetup);
851 MBB.insert(MBBI, MI);
853 } else if (NumBytes) {
854 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, Uses64BitFramePtr,
855 UseLEA, TII, *RegInfo);
858 if (NeedsWinEH && NumBytes)
859 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
861 .setMIFlag(MachineInstr::FrameSetup);
863 int SEHFrameOffset = 0;
864 if (IsWinEH && HasFP) {
865 SEHFrameOffset = calculateSetFPREG(NumBytes);
867 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
868 StackPtr, false, SEHFrameOffset);
870 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr).addReg(StackPtr);
873 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
875 .addImm(SEHFrameOffset)
876 .setMIFlag(MachineInstr::FrameSetup);
879 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
880 const MachineInstr *FrameInstr = &*MBBI;
885 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
886 if (X86::FR64RegClass.contains(Reg)) {
887 int Offset = getFrameIndexOffset(MF, FI);
888 Offset += SEHFrameOffset;
890 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
893 .setMIFlag(MachineInstr::FrameSetup);
900 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
901 .setMIFlag(MachineInstr::FrameSetup);
903 // Realign stack after we spilled callee-saved registers (so that we'll be
904 // able to calculate their offsets from the frame pointer).
905 // Win64 requires aligning the stack after the prologue.
906 if (IsWinEH && RegInfo->needsStackRealignment(MF)) {
907 assert(HasFP && "There should be a frame pointer if stack is realigned.");
908 uint64_t Val = -MaxAlign;
910 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
914 .setMIFlag(MachineInstr::FrameSetup);
916 // The EFLAGS implicit def is dead.
917 MI->getOperand(3).setIsDead();
920 // If we need a base pointer, set it up here. It's whatever the value
921 // of the stack pointer is at this point. Any variable size objects
922 // will be allocated after this, so we can still use the base pointer
923 // to reference locals.
924 if (RegInfo->hasBasePointer(MF)) {
925 // Update the base pointer with the current stack pointer.
926 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
927 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
929 .setMIFlag(MachineInstr::FrameSetup);
930 if (X86FI->getRestoreBasePointer()) {
931 // Stash value of base pointer. Saving RSP instead of EBP shortens dependence chain.
932 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
933 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
934 FramePtr, true, X86FI->getRestoreBasePointerOffset())
936 .setMIFlag(MachineInstr::FrameSetup);
940 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
941 // Mark end of stack pointer adjustment.
942 if (!HasFP && NumBytes) {
943 // Define the current CFA rule to use the provided offset.
945 unsigned CFIIndex = MMI.addFrameInst(
946 MCCFIInstruction::createDefCfaOffset(nullptr,
947 -StackSize + stackGrowth));
949 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
950 .addCFIIndex(CFIIndex);
953 // Emit DWARF info specifying the offsets of the callee-saved registers.
955 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
959 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
960 MachineBasicBlock &MBB) const {
961 const MachineFrameInfo *MFI = MF.getFrameInfo();
962 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
963 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
964 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
965 const TargetInstrInfo &TII = *STI.getInstrInfo();
966 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
967 assert(MBBI != MBB.end() && "Returning block has no instructions");
968 unsigned RetOpcode = MBBI->getOpcode();
969 DebugLoc DL = MBBI->getDebugLoc();
970 bool Is64Bit = STI.is64Bit();
971 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
972 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
973 const bool Is64BitILP32 = STI.isTarget64BitILP32();
974 bool UseLEA = STI.useLeaForSP();
975 unsigned SlotSize = RegInfo->getSlotSize();
976 unsigned FramePtr = RegInfo->getFrameRegister(MF);
977 unsigned MachineFramePtr =
978 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
980 unsigned StackPtr = RegInfo->getStackRegister();
982 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
983 bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
987 llvm_unreachable("Can only insert epilogue into returning blocks");
992 case X86::TCRETURNdi:
993 case X86::TCRETURNri:
994 case X86::TCRETURNmi:
995 case X86::TCRETURNdi64:
996 case X86::TCRETURNri64:
997 case X86::TCRETURNmi64:
999 case X86::EH_RETURN64:
1000 break; // These are ok
1003 // Get the number of bytes to allocate from the FrameInfo.
1004 uint64_t StackSize = MFI->getStackSize();
1005 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1006 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1007 uint64_t NumBytes = 0;
1010 // Calculate required stack adjustment.
1011 uint64_t FrameSize = StackSize - SlotSize;
1012 NumBytes = FrameSize - CSSize;
1014 // Callee-saved registers were pushed on stack before the stack was
1016 if (RegInfo->needsStackRealignment(MF) && !IsWinEH)
1017 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1020 BuildMI(MBB, MBBI, DL,
1021 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
1023 NumBytes = StackSize - CSSize;
1025 uint64_t SEHStackAllocAmt = NumBytes;
1027 // Skip the callee-saved pop instructions.
1028 while (MBBI != MBB.begin()) {
1029 MachineBasicBlock::iterator PI = std::prev(MBBI);
1030 unsigned Opc = PI->getOpcode();
1032 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1033 !PI->isTerminator())
1038 MachineBasicBlock::iterator FirstCSPop = MBBI;
1040 DL = MBBI->getDebugLoc();
1042 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1043 // instruction, merge the two instructions.
1044 if (NumBytes || MFI->hasVarSizedObjects())
1045 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1047 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1048 // slot before popping them off! Same applies for the case, when stack was
1050 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1051 if (RegInfo->needsStackRealignment(MF))
1054 // There are only two legal forms of epilogue:
1055 // - add SEHAllocationSize, %rsp
1056 // - lea SEHAllocationSize(%FramePtr), %rsp
1058 // We are *not* permitted to use 'mov %FramePtr, %rsp' because the Win64
1059 // unwinder will not recognize 'mov' as an epilogue instruction.
1060 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1061 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), StackPtr),
1062 FramePtr, false, SEHStackAllocAmt - SEHFrameOffset);
1064 } else if (CSSize != 0) {
1065 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1066 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1067 FramePtr, false, -CSSize);
1070 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1071 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1075 } else if (NumBytes) {
1076 // Adjust stack pointer back: ESP += numbytes.
1077 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, Uses64BitFramePtr, UseLEA,
1082 // Windows unwinder will not invoke function's exception handler if IP is
1083 // either in prologue or in epilogue. This behavior causes a problem when a
1084 // call immediately precedes an epilogue, because the return address points
1085 // into the epilogue. To cope with that, we insert an epilogue marker here,
1086 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1087 // final emitted code.
1089 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1091 // We're returning from function via eh_return.
1092 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1093 MBBI = MBB.getLastNonDebugInstr();
1094 MachineOperand &DestAddr = MBBI->getOperand(0);
1095 assert(DestAddr.isReg() && "Offset should be in register!");
1096 BuildMI(MBB, MBBI, DL,
1097 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1098 StackPtr).addReg(DestAddr.getReg());
1099 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1100 RetOpcode == X86::TCRETURNmi ||
1101 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1102 RetOpcode == X86::TCRETURNmi64) {
1103 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1104 // Tail call return: adjust the stack pointer and jump to callee.
1105 MBBI = MBB.getLastNonDebugInstr();
1106 MachineOperand &JumpTarget = MBBI->getOperand(0);
1107 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1108 assert(StackAdjust.isImm() && "Expecting immediate value.");
1110 // Adjust stack pointer.
1111 int StackAdj = StackAdjust.getImm();
1112 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1114 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1116 // Incoporate the retaddr area.
1117 Offset = StackAdj-MaxTCDelta;
1118 assert(Offset >= 0 && "Offset should never be negative");
1121 // Check for possible merge with preceding ADD instruction.
1122 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1123 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, Uses64BitFramePtr,
1124 UseLEA, TII, *RegInfo);
1127 // Jump to label or value in register.
1128 bool IsWin64 = STI.isTargetWin64();
1129 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1130 unsigned Op = (RetOpcode == X86::TCRETURNdi)
1132 : (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);
1133 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(Op));
1134 if (JumpTarget.isGlobal())
1135 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1136 JumpTarget.getTargetFlags());
1138 assert(JumpTarget.isSymbol());
1139 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1140 JumpTarget.getTargetFlags());
1142 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1143 unsigned Op = (RetOpcode == X86::TCRETURNmi)
1145 : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
1146 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(Op));
1147 for (unsigned i = 0; i != 5; ++i)
1148 MIB.addOperand(MBBI->getOperand(i));
1149 } else if (RetOpcode == X86::TCRETURNri64) {
1150 BuildMI(MBB, MBBI, DL,
1151 TII.get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
1152 .addReg(JumpTarget.getReg(), RegState::Kill);
1154 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1155 addReg(JumpTarget.getReg(), RegState::Kill);
1158 MachineInstr *NewMI = std::prev(MBBI);
1159 NewMI->copyImplicitOps(MF, MBBI);
1161 // Delete the pseudo instruction TCRETURN.
1163 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1164 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1165 (X86FI->getTCReturnAddrDelta() < 0)) {
1166 // Add the return addr area delta back since we are not tail calling.
1167 int delta = -1*X86FI->getTCReturnAddrDelta();
1168 MBBI = MBB.getLastNonDebugInstr();
1170 // Check for possible merge with preceding ADD instruction.
1171 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1172 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, Uses64BitFramePtr, UseLEA, TII,
1177 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1179 const X86RegisterInfo *RegInfo =
1180 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1181 const MachineFrameInfo *MFI = MF.getFrameInfo();
1182 // Offset will hold the offset from the stack pointer at function entry to the
1184 // We need to factor in additional offsets applied during the prologue to the
1185 // frame, base, and stack pointer depending on which is used.
1186 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1187 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1188 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1189 uint64_t StackSize = MFI->getStackSize();
1190 unsigned SlotSize = RegInfo->getSlotSize();
1191 bool HasFP = hasFP(MF);
1192 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1193 int64_t FPDelta = 0;
1196 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1198 // Calculate required stack adjustment.
1199 uint64_t FrameSize = StackSize - SlotSize;
1200 // If required, include space for extra hidden slot for stashing base pointer.
1201 if (X86FI->getRestoreBasePointer())
1202 FrameSize += SlotSize;
1203 uint64_t NumBytes = FrameSize - CSSize;
1205 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1206 if (FI && FI == X86FI->getFAIndex())
1207 return -SEHFrameOffset;
1209 // FPDelta is the offset from the "traditional" FP location of the old base
1210 // pointer followed by return address and the location required by the
1211 // restricted Win64 prologue.
1212 // Add FPDelta to all offsets below that go through the frame pointer.
1213 FPDelta = FrameSize - SEHFrameOffset;
1214 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1215 "FPDelta isn't aligned per the Win64 ABI!");
1219 if (RegInfo->hasBasePointer(MF)) {
1220 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1222 // Skip the saved EBP.
1223 return Offset + SlotSize + FPDelta;
1225 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1226 return Offset + StackSize;
1228 } else if (RegInfo->needsStackRealignment(MF)) {
1230 // Skip the saved EBP.
1231 return Offset + SlotSize + FPDelta;
1233 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1234 return Offset + StackSize;
1236 // FIXME: Support tail calls
1239 return Offset + StackSize;
1241 // Skip the saved EBP.
1244 // Skip the RETADDR move area
1245 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1246 if (TailCallReturnAddrDelta < 0)
1247 Offset -= TailCallReturnAddrDelta;
1250 return Offset + FPDelta;
1253 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1254 unsigned &FrameReg) const {
1255 const X86RegisterInfo *RegInfo =
1256 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1257 // We can't calculate offset from frame pointer if the stack is realigned,
1258 // so enforce usage of stack/base pointer. The base pointer is used when we
1259 // have dynamic allocas in addition to dynamic realignment.
1260 if (RegInfo->hasBasePointer(MF))
1261 FrameReg = RegInfo->getBaseRegister();
1262 else if (RegInfo->needsStackRealignment(MF))
1263 FrameReg = RegInfo->getStackRegister();
1265 FrameReg = RegInfo->getFrameRegister(MF);
1266 return getFrameIndexOffset(MF, FI);
1269 // Simplified from getFrameIndexOffset keeping only StackPointer cases
1270 int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
1271 const MachineFrameInfo *MFI = MF.getFrameInfo();
1272 // Does not include any dynamic realign.
1273 const uint64_t StackSize = MFI->getStackSize();
1276 const X86RegisterInfo *RegInfo =
1277 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1278 // Note: LLVM arranges the stack as:
1279 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1280 // > "Stack Slots" (<--SP)
1281 // We can always address StackSlots from RSP. We can usually (unless
1282 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1283 // address them from RBP. FixedObjects can be placed anywhere in the stack
1284 // frame depending on their specific requirements (i.e. we can actually
1285 // refer to arguments to the function which are stored in the *callers*
1286 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1287 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1289 assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");
1291 // We don't handle tail calls, and shouldn't be seeing them
1293 int TailCallReturnAddrDelta =
1294 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1295 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1299 // This is how the math works out:
1301 // %rsp grows (i.e. gets lower) left to right. Each box below is
1302 // one word (eight bytes). Obj0 is the stack slot we're trying to
1305 // ----------------------------------
1306 // | BP | Obj0 | Obj1 | ... | ObjN |
1307 // ----------------------------------
1311 // A is the incoming stack pointer.
1312 // (B - A) is the local area offset (-8 for x86-64) [1]
1313 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1315 // |(E - B)| is the StackSize (absolute value, positive). For a
1316 // stack that grown down, this works out to be (B - E). [3]
1318 // E is also the value of %rsp after stack has been set up, and we
1319 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1320 // (C - E) == (C - A) - (B - A) + (B - E)
1321 // { Using [1], [2] and [3] above }
1322 // == getObjectOffset - LocalAreaOffset + StackSize
1325 // Get the Offset from the StackPointer
1326 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1328 return Offset + StackSize;
1330 // Simplified from getFrameIndexReference keeping only StackPointer cases
1331 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1333 unsigned &FrameReg) const {
1334 const X86RegisterInfo *RegInfo =
1335 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1336 assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");
1338 FrameReg = RegInfo->getStackRegister();
1339 return getFrameIndexOffsetFromSP(MF, FI);
1342 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1343 MachineFunction &MF, const TargetRegisterInfo *TRI,
1344 std::vector<CalleeSavedInfo> &CSI) const {
1345 MachineFrameInfo *MFI = MF.getFrameInfo();
1346 const X86RegisterInfo *RegInfo =
1347 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1348 unsigned SlotSize = RegInfo->getSlotSize();
1349 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1351 unsigned CalleeSavedFrameSize = 0;
1352 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1355 // emitPrologue always spills frame register the first thing.
1356 SpillSlotOffset -= SlotSize;
1357 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1359 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1360 // the frame register, we can delete it from CSI list and not have to worry
1361 // about avoiding it later.
1362 unsigned FPReg = RegInfo->getFrameRegister(MF);
1363 for (unsigned i = 0; i < CSI.size(); ++i) {
1364 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1365 CSI.erase(CSI.begin() + i);
1371 // Assign slots for GPRs. It increases frame size.
1372 for (unsigned i = CSI.size(); i != 0; --i) {
1373 unsigned Reg = CSI[i - 1].getReg();
1375 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1378 SpillSlotOffset -= SlotSize;
1379 CalleeSavedFrameSize += SlotSize;
1381 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1382 CSI[i - 1].setFrameIdx(SlotIndex);
1385 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1387 // Assign slots for XMMs.
1388 for (unsigned i = CSI.size(); i != 0; --i) {
1389 unsigned Reg = CSI[i - 1].getReg();
1390 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1393 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1395 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1397 SpillSlotOffset -= RC->getSize();
1399 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1400 CSI[i - 1].setFrameIdx(SlotIndex);
1401 MFI->ensureMaxAlignment(RC->getAlignment());
1407 bool X86FrameLowering::spillCalleeSavedRegisters(
1408 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1409 const std::vector<CalleeSavedInfo> &CSI,
1410 const TargetRegisterInfo *TRI) const {
1411 DebugLoc DL = MBB.findDebugLoc(MI);
1413 MachineFunction &MF = *MBB.getParent();
1414 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1415 const TargetInstrInfo &TII = *STI.getInstrInfo();
1417 // Push GPRs. It increases frame size.
1418 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1419 for (unsigned i = CSI.size(); i != 0; --i) {
1420 unsigned Reg = CSI[i - 1].getReg();
1422 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1424 // Add the callee-saved register as live-in. It's killed at the spill.
1427 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1428 .setMIFlag(MachineInstr::FrameSetup);
1431 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1432 // It can be done by spilling XMMs to stack frame.
1433 for (unsigned i = CSI.size(); i != 0; --i) {
1434 unsigned Reg = CSI[i-1].getReg();
1435 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1437 // Add the callee-saved register as live-in. It's killed at the spill.
1439 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1441 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1444 MI->setFlag(MachineInstr::FrameSetup);
1451 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1452 MachineBasicBlock::iterator MI,
1453 const std::vector<CalleeSavedInfo> &CSI,
1454 const TargetRegisterInfo *TRI) const {
1458 DebugLoc DL = MBB.findDebugLoc(MI);
1460 MachineFunction &MF = *MBB.getParent();
1461 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1462 const TargetInstrInfo &TII = *STI.getInstrInfo();
1464 // Reload XMMs from stack frame.
1465 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1466 unsigned Reg = CSI[i].getReg();
1467 if (X86::GR64RegClass.contains(Reg) ||
1468 X86::GR32RegClass.contains(Reg))
1471 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1472 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1476 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1477 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1478 unsigned Reg = CSI[i].getReg();
1479 if (!X86::GR64RegClass.contains(Reg) &&
1480 !X86::GR32RegClass.contains(Reg))
1483 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1489 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1490 RegScavenger *RS) const {
1491 MachineFrameInfo *MFI = MF.getFrameInfo();
1492 const X86RegisterInfo *RegInfo =
1493 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1494 unsigned SlotSize = RegInfo->getSlotSize();
1496 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1497 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1499 if (TailCallReturnAddrDelta < 0) {
1500 // create RETURNADDR area
1509 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1510 TailCallReturnAddrDelta - SlotSize, true);
1513 // Spill the BasePtr if it's used.
1514 if (RegInfo->hasBasePointer(MF))
1515 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1519 HasNestArgument(const MachineFunction *MF) {
1520 const Function *F = MF->getFunction();
1521 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1523 if (I->hasNestAttr())
1529 /// GetScratchRegister - Get a temp register for performing work in the
1530 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1531 /// and the properties of the function either one or two registers will be
1532 /// needed. Set primary to true for the first register, false for the second.
1534 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1535 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1538 if (CallingConvention == CallingConv::HiPE) {
1540 return Primary ? X86::R14 : X86::R13;
1542 return Primary ? X86::EBX : X86::EDI;
1547 return Primary ? X86::R11 : X86::R12;
1549 return Primary ? X86::R11D : X86::R12D;
1552 bool IsNested = HasNestArgument(&MF);
1554 if (CallingConvention == CallingConv::X86_FastCall ||
1555 CallingConvention == CallingConv::Fast) {
1557 report_fatal_error("Segmented stacks does not support fastcall with "
1558 "nested function.");
1559 return Primary ? X86::EAX : X86::ECX;
1562 return Primary ? X86::EDX : X86::EAX;
1563 return Primary ? X86::ECX : X86::EAX;
1566 // The stack limit in the TCB is set to this many bytes above the actual stack
1568 static const uint64_t kSplitStackAvailable = 256;
1571 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1572 MachineBasicBlock &prologueMBB = MF.front();
1573 MachineFrameInfo *MFI = MF.getFrameInfo();
1574 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1575 const TargetInstrInfo &TII = *STI.getInstrInfo();
1577 bool Is64Bit = STI.is64Bit();
1578 const bool IsLP64 = STI.isTarget64BitLP64();
1579 unsigned TlsReg, TlsOffset;
1582 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1583 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1584 "Scratch register is live-in");
1586 if (MF.getFunction()->isVarArg())
1587 report_fatal_error("Segmented stacks do not support vararg functions.");
1588 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1589 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1590 !STI.isTargetDragonFly())
1591 report_fatal_error("Segmented stacks not supported on this platform.");
1593 // Eventually StackSize will be calculated by a link-time pass; which will
1594 // also decide whether checking code needs to be injected into this particular
1596 StackSize = MFI->getStackSize();
1598 // Do not generate a prologue for functions with a stack of size zero
1602 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1603 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1604 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1605 bool IsNested = false;
1607 // We need to know if the function has a nest argument only in 64 bit mode.
1609 IsNested = HasNestArgument(&MF);
1611 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1612 // allocMBB needs to be last (terminating) instruction.
1614 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1615 e = prologueMBB.livein_end(); i != e; i++) {
1616 allocMBB->addLiveIn(*i);
1617 checkMBB->addLiveIn(*i);
1621 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1623 MF.push_front(allocMBB);
1624 MF.push_front(checkMBB);
1626 // When the frame size is less than 256 we just compare the stack
1627 // boundary directly to the value of the stack pointer, per gcc.
1628 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1630 // Read the limit off the current stacklet off the stack_guard location.
1632 if (STI.isTargetLinux()) {
1634 TlsOffset = IsLP64 ? 0x70 : 0x40;
1635 } else if (STI.isTargetDarwin()) {
1637 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1638 } else if (STI.isTargetWin64()) {
1640 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1641 } else if (STI.isTargetFreeBSD()) {
1644 } else if (STI.isTargetDragonFly()) {
1646 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1648 report_fatal_error("Segmented stacks not supported on this platform.");
1651 if (CompareStackPointer)
1652 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1654 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1655 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1657 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1658 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1660 if (STI.isTargetLinux()) {
1663 } else if (STI.isTargetDarwin()) {
1665 TlsOffset = 0x48 + 90*4;
1666 } else if (STI.isTargetWin32()) {
1668 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1669 } else if (STI.isTargetDragonFly()) {
1671 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1672 } else if (STI.isTargetFreeBSD()) {
1673 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1675 report_fatal_error("Segmented stacks not supported on this platform.");
1678 if (CompareStackPointer)
1679 ScratchReg = X86::ESP;
1681 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1682 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1684 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1685 STI.isTargetDragonFly()) {
1686 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1687 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1688 } else if (STI.isTargetDarwin()) {
1690 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1691 unsigned ScratchReg2;
1693 if (CompareStackPointer) {
1694 // The primary scratch register is available for holding the TLS offset.
1695 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1696 SaveScratch2 = false;
1698 // Need to use a second register to hold the TLS offset
1699 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1701 // Unfortunately, with fastcc the second scratch register may hold an
1703 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1706 // If Scratch2 is live-in then it needs to be saved.
1707 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1708 "Scratch register is live-in and not saved");
1711 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1712 .addReg(ScratchReg2, RegState::Kill);
1714 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1716 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1718 .addReg(ScratchReg2).addImm(1).addReg(0)
1723 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1727 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1728 // It jumps to normal execution of the function body.
1729 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&prologueMBB);
1731 // On 32 bit we first push the arguments size and then the frame size. On 64
1732 // bit, we pass the stack frame size in r10 and the argument size in r11.
1734 // Functions with nested arguments use R10, so it needs to be saved across
1735 // the call to _morestack
1737 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1738 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1739 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1740 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1741 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1744 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1746 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1748 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1749 .addImm(X86FI->getArgumentStackSize());
1750 MF.getRegInfo().setPhysRegUsed(Reg10);
1751 MF.getRegInfo().setPhysRegUsed(Reg11);
1753 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1754 .addImm(X86FI->getArgumentStackSize());
1755 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1759 // __morestack is in libgcc
1760 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1761 // Under the large code model, we cannot assume that __morestack lives
1762 // within 2^31 bytes of the call site, so we cannot use pc-relative
1763 // addressing. We cannot perform the call via a temporary register,
1764 // as the rax register may be used to store the static chain, and all
1765 // other suitable registers may be either callee-save or used for
1766 // parameter passing. We cannot use the stack at this point either
1767 // because __morestack manipulates the stack directly.
1769 // To avoid these issues, perform an indirect call via a read-only memory
1770 // location containing the address.
1772 // This solution is not perfect, as it assumes that the .rodata section
1773 // is laid out within 2^31 bytes of each function body, but this seems
1774 // to be sufficient for JIT.
1775 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1779 .addExternalSymbol("__morestack_addr")
1781 MF.getMMI().setUsesMorestackAddr(true);
1784 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1785 .addExternalSymbol("__morestack");
1787 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1788 .addExternalSymbol("__morestack");
1792 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1794 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1796 allocMBB->addSuccessor(&prologueMBB);
1798 checkMBB->addSuccessor(allocMBB);
1799 checkMBB->addSuccessor(&prologueMBB);
1806 /// Erlang programs may need a special prologue to handle the stack size they
1807 /// might need at runtime. That is because Erlang/OTP does not implement a C
1808 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1809 /// (for more information see Eric Stenman's Ph.D. thesis:
1810 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1813 /// temp0 = sp - MaxStack
1814 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1818 /// call inc_stack # doubles the stack space
1819 /// temp0 = sp - MaxStack
1820 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1821 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1822 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1823 const TargetInstrInfo &TII = *STI.getInstrInfo();
1824 MachineFrameInfo *MFI = MF.getFrameInfo();
1825 const unsigned SlotSize = STI.getRegisterInfo()->getSlotSize();
1826 const bool Is64Bit = STI.is64Bit();
1827 const bool IsLP64 = STI.isTarget64BitLP64();
1829 // HiPE-specific values
1830 const unsigned HipeLeafWords = 24;
1831 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1832 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1833 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1834 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1835 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1837 assert(STI.isTargetLinux() &&
1838 "HiPE prologue is only supported on Linux operating systems.");
1840 // Compute the largest caller's frame that is needed to fit the callees'
1841 // frames. This 'MaxStack' is computed from:
1843 // a) the fixed frame size, which is the space needed for all spilled temps,
1844 // b) outgoing on-stack parameter areas, and
1845 // c) the minimum stack space this function needs to make available for the
1846 // functions it calls (a tunable ABI property).
1847 if (MFI->hasCalls()) {
1848 unsigned MoreStackForCalls = 0;
1850 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1851 MBBI != MBBE; ++MBBI)
1852 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1857 // Get callee operand.
1858 const MachineOperand &MO = MI->getOperand(0);
1860 // Only take account of global function calls (no closures etc.).
1864 const Function *F = dyn_cast<Function>(MO.getGlobal());
1868 // Do not update 'MaxStack' for primitive and built-in functions
1869 // (encoded with names either starting with "erlang."/"bif_" or not
1870 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1871 // "_", such as the BIF "suspend_0") as they are executed on another
1873 if (F->getName().find("erlang.") != StringRef::npos ||
1874 F->getName().find("bif_") != StringRef::npos ||
1875 F->getName().find_first_of("._") == StringRef::npos)
1878 unsigned CalleeStkArity =
1879 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1880 if (HipeLeafWords - 1 > CalleeStkArity)
1881 MoreStackForCalls = std::max(MoreStackForCalls,
1882 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1884 MaxStack += MoreStackForCalls;
1887 // If the stack frame needed is larger than the guaranteed then runtime checks
1888 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1889 if (MaxStack > Guaranteed) {
1890 MachineBasicBlock &prologueMBB = MF.front();
1891 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1892 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1894 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1895 E = prologueMBB.livein_end(); I != E; I++) {
1896 stackCheckMBB->addLiveIn(*I);
1897 incStackMBB->addLiveIn(*I);
1900 MF.push_front(incStackMBB);
1901 MF.push_front(stackCheckMBB);
1903 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1904 unsigned LEAop, CMPop, CALLop;
1908 LEAop = X86::LEA64r;
1909 CMPop = X86::CMP64rm;
1910 CALLop = X86::CALL64pcrel32;
1911 SPLimitOffset = 0x90;
1915 LEAop = X86::LEA32r;
1916 CMPop = X86::CMP32rm;
1917 CALLop = X86::CALLpcrel32;
1918 SPLimitOffset = 0x4c;
1921 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1922 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1923 "HiPE prologue scratch register is live-in");
1925 // Create new MBB for StackCheck:
1926 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1927 SPReg, false, -MaxStack);
1928 // SPLimitOffset is in a fixed heap location (pointed by BP).
1929 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1930 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1931 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&prologueMBB);
1933 // Create new MBB for IncStack:
1934 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1935 addExternalSymbol("inc_stack_0");
1936 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1937 SPReg, false, -MaxStack);
1938 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1939 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1940 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1942 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1943 stackCheckMBB->addSuccessor(incStackMBB, 1);
1944 incStackMBB->addSuccessor(&prologueMBB, 99);
1945 incStackMBB->addSuccessor(incStackMBB, 1);
1952 void X86FrameLowering::
1953 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1954 MachineBasicBlock::iterator I) const {
1955 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1956 const TargetInstrInfo &TII = *STI.getInstrInfo();
1957 const X86RegisterInfo &RegInfo = *STI.getRegisterInfo();
1958 unsigned StackPtr = RegInfo.getStackRegister();
1959 bool reserveCallFrame = hasReservedCallFrame(MF);
1960 int Opcode = I->getOpcode();
1961 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1962 bool IsLP64 = STI.isTarget64BitLP64();
1963 DebugLoc DL = I->getDebugLoc();
1964 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
1965 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
1968 if (!reserveCallFrame) {
1969 // If the stack pointer can be changed after prologue, turn the
1970 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1971 // adjcallstackdown instruction into 'add ESP, <amt>'
1975 // We need to keep the stack aligned properly. To do this, we round the
1976 // amount of space needed for the outgoing arguments up to the next
1977 // alignment boundary.
1978 unsigned StackAlign = getStackAlignment();
1979 Amount = RoundUpToAlignment(Amount, StackAlign);
1981 MachineInstr *New = nullptr;
1983 // Factor out the amount that gets handled inside the sequence
1984 // (Pushes of argument for frame setup, callee pops for frame destroy)
1985 Amount -= InternalAmt;
1988 if (Opcode == TII.getCallFrameSetupOpcode()) {
1989 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)), StackPtr)
1990 .addReg(StackPtr).addImm(Amount);
1992 assert(Opcode == TII.getCallFrameDestroyOpcode());
1994 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1995 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1996 .addReg(StackPtr).addImm(Amount);
2001 // The EFLAGS implicit def is dead.
2002 New->getOperand(3).setIsDead();
2004 // Replace the pseudo instruction with a new instruction.
2011 if (Opcode == TII.getCallFrameDestroyOpcode() && InternalAmt) {
2012 // If we are performing frame pointer elimination and if the callee pops
2013 // something off the stack pointer, add it back. We do this until we have
2014 // more advanced stack pointer tracking ability.
2015 unsigned Opc = getSUBriOpcode(IsLP64, InternalAmt);
2016 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
2017 .addReg(StackPtr).addImm(InternalAmt);
2019 // The EFLAGS implicit def is dead.
2020 New->getOperand(3).setIsDead();
2022 // We are not tracking the stack pointer adjustment by the callee, so make
2023 // sure we restore the stack pointer immediately after the call, there may
2024 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2025 MachineBasicBlock::iterator B = MBB.begin();
2026 while (I != B && !std::prev(I)->isCall())