1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned IsLP64) {
83 return IsLP64 ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
114 case X86::TCRETURNdi:
115 case X86::TCRETURNri:
116 case X86::TCRETURNmi:
117 case X86::TCRETURNdi64:
118 case X86::TCRETURNri64:
119 case X86::TCRETURNmi64:
121 case X86::EH_RETURN64: {
122 SmallSet<uint16_t, 8> Uses;
123 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
124 MachineOperand &MO = MBBI->getOperand(i);
125 if (!MO.isReg() || MO.isDef())
127 unsigned Reg = MO.getReg();
130 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
134 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
136 if (!Uses.count(*CS))
145 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
146 /// stack pointer by a constant value.
148 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
149 unsigned StackPtr, int64_t NumBytes,
150 bool Is64Bit, bool IsLP64, bool UseLEA,
151 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
152 bool isSub = NumBytes < 0;
153 uint64_t Offset = isSub ? -NumBytes : NumBytes;
156 Opc = getLEArOpcode(IsLP64);
159 ? getSUBriOpcode(IsLP64, Offset)
160 : getADDriOpcode(IsLP64, Offset);
162 uint64_t Chunk = (1LL << 31) - 1;
163 DebugLoc DL = MBB.findDebugLoc(MBBI);
166 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
167 if (ThisVal == (Is64Bit ? 8 : 4)) {
168 // Use push / pop instead.
170 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
171 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
174 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
175 : (Is64Bit ? X86::POP64r : X86::POP32r);
176 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
177 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
179 MI->setFlag(MachineInstr::FrameSetup);
185 MachineInstr *MI = nullptr;
188 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 StackPtr, false, isSub ? -ThisVal : ThisVal);
191 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
194 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
198 MI->setFlag(MachineInstr::FrameSetup);
204 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
206 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
207 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
208 if (MBBI == MBB.begin()) return;
210 MachineBasicBlock::iterator PI = std::prev(MBBI);
211 unsigned Opc = PI->getOpcode();
212 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
213 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
214 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
215 PI->getOperand(0).getReg() == StackPtr) {
217 *NumBytes += PI->getOperand(2).getImm();
219 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
220 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
221 PI->getOperand(0).getReg() == StackPtr) {
223 *NumBytes -= PI->getOperand(2).getImm();
228 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower
231 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
232 MachineBasicBlock::iterator &MBBI,
233 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
234 // FIXME: THIS ISN'T RUN!!!
237 if (MBBI == MBB.end()) return;
239 MachineBasicBlock::iterator NI = std::next(MBBI);
240 if (NI == MBB.end()) return;
242 unsigned Opc = NI->getOpcode();
243 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
244 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
245 NI->getOperand(0).getReg() == StackPtr) {
247 *NumBytes -= NI->getOperand(2).getImm();
250 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
251 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
252 NI->getOperand(0).getReg() == StackPtr) {
254 *NumBytes += NI->getOperand(2).getImm();
260 /// mergeSPUpdates - Checks the instruction before/after the passed
261 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
262 /// the stack adjustment is returned as a positive value for ADD/LEA and a
263 /// negative for SUB.
264 static int mergeSPUpdates(MachineBasicBlock &MBB,
265 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
266 bool doMergeWithPrevious) {
267 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
268 (!doMergeWithPrevious && MBBI == MBB.end()))
271 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
272 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
274 unsigned Opc = PI->getOpcode();
277 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
278 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
279 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
280 PI->getOperand(0).getReg() == StackPtr){
281 Offset += PI->getOperand(2).getImm();
283 if (!doMergeWithPrevious) MBBI = NI;
284 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
285 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
286 PI->getOperand(0).getReg() == StackPtr) {
287 Offset -= PI->getOperand(2).getImm();
289 if (!doMergeWithPrevious) MBBI = NI;
295 static bool isEAXLiveIn(MachineFunction &MF) {
296 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
297 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
298 unsigned Reg = II->first;
300 if (Reg == X86::EAX || Reg == X86::AX ||
301 Reg == X86::AH || Reg == X86::AL)
308 void X86FrameLowering::emitCalleeSavedFrameMoves(
309 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
310 unsigned FramePtr) const {
311 MachineFunction &MF = *MBB.getParent();
312 MachineFrameInfo *MFI = MF.getFrameInfo();
313 MachineModuleInfo &MMI = MF.getMMI();
314 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
315 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
317 // Add callee saved registers to move list.
318 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
319 if (CSI.empty()) return;
321 const X86RegisterInfo *RegInfo =
322 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
323 bool HasFP = hasFP(MF);
325 // Calculate amount of bytes used for return address storing.
326 int stackGrowth = -RegInfo->getSlotSize();
328 // FIXME: This is dirty hack. The code itself is pretty mess right now.
329 // It should be rewritten from scratch and generalized sometimes.
331 // Determine maximum offset (minimum due to stack growth).
332 int64_t MaxOffset = 0;
333 for (std::vector<CalleeSavedInfo>::const_iterator
334 I = CSI.begin(), E = CSI.end(); I != E; ++I)
335 MaxOffset = std::min(MaxOffset,
336 MFI->getObjectOffset(I->getFrameIdx()));
338 // Calculate offsets.
339 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
340 for (std::vector<CalleeSavedInfo>::const_iterator
341 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
342 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
343 unsigned Reg = I->getReg();
344 Offset = MaxOffset - Offset + saveAreaOffset;
346 // Don't output a new machine move if we're re-saving the frame
347 // pointer. This happens when the PrologEpilogInserter has inserted an extra
348 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
349 // generates one when frame pointers are used. If we generate a "machine
350 // move" for this extra "PUSH", the linker will lose track of the fact that
351 // the frame pointer should have the value of the first "PUSH" when it's
354 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
355 // another bug. I.e., one where we generate a prolog like this:
363 // The immediate re-push of EBP is unnecessary. At the least, it's an
364 // optimization bug. EBP can be used as a scratch register in certain
365 // cases, but probably not when we have a frame pointer.
366 if (HasFP && FramePtr == Reg)
369 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
371 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
373 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
374 .addCFIIndex(CFIIndex);
378 /// usesTheStack - This function checks if any of the users of EFLAGS
379 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
380 /// to use the stack, and if we don't adjust the stack we clobber the first
382 /// See X86InstrInfo::copyPhysReg.
383 static bool usesTheStack(const MachineFunction &MF) {
384 const MachineRegisterInfo &MRI = MF.getRegInfo();
386 for (MachineRegisterInfo::reg_instr_iterator
387 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
395 /// emitPrologue - Push callee-saved registers onto the stack, which
396 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
397 /// space for local variables. Also emit labels used by the exception handler to
398 /// generate the exception handling frames.
399 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
400 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
401 MachineBasicBlock::iterator MBBI = MBB.begin();
402 MachineFrameInfo *MFI = MF.getFrameInfo();
403 const Function *Fn = MF.getFunction();
404 const X86RegisterInfo *RegInfo =
405 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
406 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
407 MachineModuleInfo &MMI = MF.getMMI();
408 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
409 bool needsFrameMoves = MMI.hasDebugInfo() ||
410 Fn->needsUnwindTableEntry();
411 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
412 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
413 bool HasFP = hasFP(MF);
414 bool Is64Bit = STI.is64Bit();
415 bool IsLP64 = STI.isTarget64BitLP64();
416 bool IsWin64 = STI.isTargetWin64();
417 bool UseLEA = STI.useLeaForSP();
418 unsigned StackAlign = getStackAlignment();
419 unsigned SlotSize = RegInfo->getSlotSize();
420 unsigned FramePtr = RegInfo->getFrameRegister(MF);
421 unsigned StackPtr = RegInfo->getStackRegister();
422 unsigned BasePtr = RegInfo->getBaseRegister();
425 // If we're forcing a stack realignment we can't rely on just the frame
426 // info, we need to know the ABI stack alignment as well in case we
427 // have a call out. Otherwise just make sure we have some alignment - we'll
428 // go with the minimum SlotSize.
429 if (ForceStackAlign) {
431 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
432 else if (MaxAlign < SlotSize)
436 // Add RETADDR move area to callee saved frame size.
437 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
438 if (TailCallReturnAddrDelta < 0)
439 X86FI->setCalleeSavedFrameSize(
440 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
442 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
443 // function, and use up to 128 bytes of stack space, don't have a frame
444 // pointer, calls, or dynamic alloca then we do not need to adjust the
445 // stack pointer (we fit in the Red Zone). We also check that we don't
446 // push and pop from the stack.
447 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
448 Attribute::NoRedZone) &&
449 !RegInfo->needsStackRealignment(MF) &&
450 !MFI->hasVarSizedObjects() && // No dynamic alloca.
451 !MFI->adjustsStack() && // No calls.
452 !IsWin64 && // Win64 has no Red Zone
453 !usesTheStack(MF) && // Don't push and pop.
454 !MF.shouldSplitStack()) { // Regular stack
455 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
456 if (HasFP) MinSize += SlotSize;
457 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
458 MFI->setStackSize(StackSize);
461 // Insert stack pointer adjustment for later moving of return addr. Only
462 // applies to tail call optimized functions where the callee argument stack
463 // size is bigger than the callers.
464 if (TailCallReturnAddrDelta < 0) {
466 BuildMI(MBB, MBBI, DL,
467 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
470 .addImm(-TailCallReturnAddrDelta)
471 .setMIFlag(MachineInstr::FrameSetup);
472 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
475 // Mapping for machine moves:
477 // DST: VirtualFP AND
478 // SRC: VirtualFP => DW_CFA_def_cfa_offset
479 // ELSE => DW_CFA_def_cfa
481 // SRC: VirtualFP AND
482 // DST: Register => DW_CFA_def_cfa_register
485 // OFFSET < 0 => DW_CFA_offset_extended_sf
486 // REG < 64 => DW_CFA_offset + Reg
487 // ELSE => DW_CFA_offset_extended
489 uint64_t NumBytes = 0;
490 int stackGrowth = -SlotSize;
493 // Calculate required stack adjustment.
494 uint64_t FrameSize = StackSize - SlotSize;
495 if (RegInfo->needsStackRealignment(MF)) {
496 // Callee-saved registers are pushed on stack before the stack
498 FrameSize -= X86FI->getCalleeSavedFrameSize();
499 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
501 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
504 // Get the offset of the stack slot for the EBP register, which is
505 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
506 // Update the frame offset adjustment.
507 MFI->setOffsetAdjustment(-NumBytes);
509 // Save EBP/RBP into the appropriate stack slot.
510 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
511 .addReg(FramePtr, RegState::Kill)
512 .setMIFlag(MachineInstr::FrameSetup);
514 if (needsFrameMoves) {
515 // Mark the place where EBP/RBP was saved.
516 // Define the current CFA rule to use the provided offset.
518 unsigned CFIIndex = MMI.addFrameInst(
519 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
520 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
521 .addCFIIndex(CFIIndex);
523 // Change the rule for the FramePtr to be an "offset" rule.
524 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
525 CFIIndex = MMI.addFrameInst(
526 MCCFIInstruction::createOffset(nullptr,
527 DwarfFramePtr, 2 * stackGrowth));
528 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
529 .addCFIIndex(CFIIndex);
532 // Update EBP with the new base value.
533 BuildMI(MBB, MBBI, DL,
534 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
536 .setMIFlag(MachineInstr::FrameSetup);
538 if (needsFrameMoves) {
539 // Mark effective beginning of when frame pointer becomes valid.
540 // Define the current CFA to use the EBP/RBP register.
541 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
542 unsigned CFIIndex = MMI.addFrameInst(
543 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
544 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
545 .addCFIIndex(CFIIndex);
548 // Mark the FramePtr as live-in in every block except the entry.
549 for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
551 I->addLiveIn(FramePtr);
553 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
556 // Skip the callee-saved push instructions.
557 bool PushedRegs = false;
558 int StackOffset = 2 * stackGrowth;
560 while (MBBI != MBB.end() &&
561 (MBBI->getOpcode() == X86::PUSH32r ||
562 MBBI->getOpcode() == X86::PUSH64r)) {
564 MBBI->setFlag(MachineInstr::FrameSetup);
567 if (!HasFP && needsFrameMoves) {
568 // Mark callee-saved push instruction.
569 // Define the current CFA rule to use the provided offset.
571 unsigned CFIIndex = MMI.addFrameInst(
572 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
573 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
574 .addCFIIndex(CFIIndex);
575 StackOffset += stackGrowth;
579 // Realign stack after we pushed callee-saved registers (so that we'll be
580 // able to calculate their offsets from the frame pointer).
582 // NOTE: We push the registers before realigning the stack, so
583 // vector callee-saved (xmm) registers may be saved w/o proper
584 // alignment in this way. However, currently these regs are saved in
585 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
586 // this shouldn't be a problem.
587 if (RegInfo->needsStackRealignment(MF)) {
588 assert(HasFP && "There should be a frame pointer if stack is realigned.");
590 BuildMI(MBB, MBBI, DL,
591 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
594 .setMIFlag(MachineInstr::FrameSetup);
596 // The EFLAGS implicit def is dead.
597 MI->getOperand(3).setIsDead();
600 // If there is an SUB32ri of ESP immediately before this instruction, merge
601 // the two. This can be the case when tail call elimination is enabled and
602 // the callee has more arguments then the caller.
603 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
605 // If there is an ADD32ri or SUB32ri of ESP immediately after this
606 // instruction, merge the two instructions.
607 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
609 // Adjust stack pointer: ESP -= numbytes.
611 // Windows and cygwin/mingw require a prologue helper routine when allocating
612 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
613 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
614 // stack and adjust the stack pointer in one go. The 64-bit version of
615 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
616 // responsible for adjusting the stack pointer. Touching the stack at 4K
617 // increments is necessary to ensure that the guard pages used by the OS
618 // virtual memory manager are allocated in correct sequence.
619 if (NumBytes >= 4096 && STI.isOSWindows() && !STI.isTargetMacho()) {
620 const char *StackProbeSymbol;
623 if (STI.isTargetCygMing()) {
624 StackProbeSymbol = "___chkstk_ms";
626 StackProbeSymbol = "__chkstk";
628 } else if (STI.isTargetCygMing())
629 StackProbeSymbol = "_alloca";
631 StackProbeSymbol = "_chkstk";
633 // Check whether EAX is livein for this function.
634 bool isEAXAlive = isEAXLiveIn(MF);
637 // Sanity check that EAX is not livein for this function.
638 // It should not be, so throw an assert.
639 assert(!Is64Bit && "EAX is livein in x64 case!");
642 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
643 .addReg(X86::EAX, RegState::Kill)
644 .setMIFlag(MachineInstr::FrameSetup);
648 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
649 // Function prologue is responsible for adjusting the stack pointer.
650 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
652 .setMIFlag(MachineInstr::FrameSetup);
654 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
655 // We'll also use 4 already allocated bytes for EAX.
656 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
657 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
658 .setMIFlag(MachineInstr::FrameSetup);
661 BuildMI(MBB, MBBI, DL,
662 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
663 .addExternalSymbol(StackProbeSymbol)
664 .addReg(StackPtr, RegState::Define | RegState::Implicit)
665 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
666 .setMIFlag(MachineInstr::FrameSetup);
669 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
670 // themself. It also does not clobber %rax so we can reuse it when
672 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
675 .setMIFlag(MachineInstr::FrameSetup);
679 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
681 StackPtr, false, NumBytes - 4);
682 MI->setFlag(MachineInstr::FrameSetup);
683 MBB.insert(MBBI, MI);
686 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
687 UseLEA, TII, *RegInfo);
689 // If we need a base pointer, set it up here. It's whatever the value
690 // of the stack pointer is at this point. Any variable size objects
691 // will be allocated after this, so we can still use the base pointer
692 // to reference locals.
693 if (RegInfo->hasBasePointer(MF)) {
694 // Update the frame pointer with the current stack pointer.
695 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
696 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
698 .setMIFlag(MachineInstr::FrameSetup);
701 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
702 // Mark end of stack pointer adjustment.
703 if (!HasFP && NumBytes) {
704 // Define the current CFA rule to use the provided offset.
706 unsigned CFIIndex = MMI.addFrameInst(
707 MCCFIInstruction::createDefCfaOffset(nullptr,
708 -StackSize + stackGrowth));
710 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
711 .addCFIIndex(CFIIndex);
714 // Emit DWARF info specifying the offsets of the callee-saved registers.
716 emitCalleeSavedFrameMoves(MBB, MBBI, DL, HasFP ? FramePtr : StackPtr);
720 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
721 MachineBasicBlock &MBB) const {
722 const MachineFrameInfo *MFI = MF.getFrameInfo();
723 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
724 const X86RegisterInfo *RegInfo =
725 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
726 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
727 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
728 assert(MBBI != MBB.end() && "Returning block has no instructions");
729 unsigned RetOpcode = MBBI->getOpcode();
730 DebugLoc DL = MBBI->getDebugLoc();
731 bool Is64Bit = STI.is64Bit();
732 bool IsLP64 = STI.isTarget64BitLP64();
733 bool UseLEA = STI.useLeaForSP();
734 unsigned StackAlign = getStackAlignment();
735 unsigned SlotSize = RegInfo->getSlotSize();
736 unsigned FramePtr = RegInfo->getFrameRegister(MF);
737 unsigned StackPtr = RegInfo->getStackRegister();
741 llvm_unreachable("Can only insert epilog into returning blocks");
746 case X86::TCRETURNdi:
747 case X86::TCRETURNri:
748 case X86::TCRETURNmi:
749 case X86::TCRETURNdi64:
750 case X86::TCRETURNri64:
751 case X86::TCRETURNmi64:
753 case X86::EH_RETURN64:
754 break; // These are ok
757 // Get the number of bytes to allocate from the FrameInfo.
758 uint64_t StackSize = MFI->getStackSize();
759 uint64_t MaxAlign = MFI->getMaxAlignment();
760 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
761 uint64_t NumBytes = 0;
763 // If we're forcing a stack realignment we can't rely on just the frame
764 // info, we need to know the ABI stack alignment as well in case we
765 // have a call out. Otherwise just make sure we have some alignment - we'll
766 // go with the minimum.
767 if (ForceStackAlign) {
769 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
771 MaxAlign = MaxAlign ? MaxAlign : 4;
775 // Calculate required stack adjustment.
776 uint64_t FrameSize = StackSize - SlotSize;
777 if (RegInfo->needsStackRealignment(MF)) {
778 // Callee-saved registers were pushed on stack before the stack
781 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
783 NumBytes = FrameSize - CSSize;
787 BuildMI(MBB, MBBI, DL,
788 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
790 NumBytes = StackSize - CSSize;
793 // Skip the callee-saved pop instructions.
794 while (MBBI != MBB.begin()) {
795 MachineBasicBlock::iterator PI = std::prev(MBBI);
796 unsigned Opc = PI->getOpcode();
798 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
804 MachineBasicBlock::iterator FirstCSPop = MBBI;
806 DL = MBBI->getDebugLoc();
808 // If there is an ADD32ri or SUB32ri of ESP immediately before this
809 // instruction, merge the two instructions.
810 if (NumBytes || MFI->hasVarSizedObjects())
811 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
813 // If dynamic alloca is used, then reset esp to point to the last callee-saved
814 // slot before popping them off! Same applies for the case, when stack was
816 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
817 if (RegInfo->needsStackRealignment(MF))
820 unsigned Opc = getLEArOpcode(IsLP64);
821 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
822 FramePtr, false, -CSSize);
824 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
825 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
828 } else if (NumBytes) {
829 // Adjust stack pointer back: ESP += numbytes.
830 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
834 // We're returning from function via eh_return.
835 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
836 MBBI = MBB.getLastNonDebugInstr();
837 MachineOperand &DestAddr = MBBI->getOperand(0);
838 assert(DestAddr.isReg() && "Offset should be in register!");
839 BuildMI(MBB, MBBI, DL,
840 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
841 StackPtr).addReg(DestAddr.getReg());
842 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
843 RetOpcode == X86::TCRETURNmi ||
844 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
845 RetOpcode == X86::TCRETURNmi64) {
846 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
847 // Tail call return: adjust the stack pointer and jump to callee.
848 MBBI = MBB.getLastNonDebugInstr();
849 MachineOperand &JumpTarget = MBBI->getOperand(0);
850 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
851 assert(StackAdjust.isImm() && "Expecting immediate value.");
853 // Adjust stack pointer.
854 int StackAdj = StackAdjust.getImm();
855 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
857 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
859 // Incoporate the retaddr area.
860 Offset = StackAdj-MaxTCDelta;
861 assert(Offset >= 0 && "Offset should never be negative");
864 // Check for possible merge with preceding ADD instruction.
865 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
866 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
867 UseLEA, TII, *RegInfo);
870 // Jump to label or value in register.
871 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
872 MachineInstrBuilder MIB =
873 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
874 ? X86::TAILJMPd : X86::TAILJMPd64));
875 if (JumpTarget.isGlobal())
876 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
877 JumpTarget.getTargetFlags());
879 assert(JumpTarget.isSymbol());
880 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
881 JumpTarget.getTargetFlags());
883 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
884 MachineInstrBuilder MIB =
885 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
886 ? X86::TAILJMPm : X86::TAILJMPm64));
887 for (unsigned i = 0; i != 5; ++i)
888 MIB.addOperand(MBBI->getOperand(i));
889 } else if (RetOpcode == X86::TCRETURNri64) {
890 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
891 addReg(JumpTarget.getReg(), RegState::Kill);
893 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
894 addReg(JumpTarget.getReg(), RegState::Kill);
897 MachineInstr *NewMI = std::prev(MBBI);
898 NewMI->copyImplicitOps(MF, MBBI);
900 // Delete the pseudo instruction TCRETURN.
902 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
903 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
904 (X86FI->getTCReturnAddrDelta() < 0)) {
905 // Add the return addr area delta back since we are not tail calling.
906 int delta = -1*X86FI->getTCReturnAddrDelta();
907 MBBI = MBB.getLastNonDebugInstr();
909 // Check for possible merge with preceding ADD instruction.
910 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
911 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
916 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
918 const X86RegisterInfo *RegInfo =
919 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
920 const MachineFrameInfo *MFI = MF.getFrameInfo();
921 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
922 uint64_t StackSize = MFI->getStackSize();
924 if (RegInfo->hasBasePointer(MF)) {
925 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
927 // Skip the saved EBP.
928 return Offset + RegInfo->getSlotSize();
930 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
931 return Offset + StackSize;
933 } else if (RegInfo->needsStackRealignment(MF)) {
935 // Skip the saved EBP.
936 return Offset + RegInfo->getSlotSize();
938 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
939 return Offset + StackSize;
941 // FIXME: Support tail calls
944 return Offset + StackSize;
946 // Skip the saved EBP.
947 Offset += RegInfo->getSlotSize();
949 // Skip the RETADDR move area
950 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
951 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
952 if (TailCallReturnAddrDelta < 0)
953 Offset -= TailCallReturnAddrDelta;
959 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
960 unsigned &FrameReg) const {
961 const X86RegisterInfo *RegInfo =
962 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
963 // We can't calculate offset from frame pointer if the stack is realigned,
964 // so enforce usage of stack/base pointer. The base pointer is used when we
965 // have dynamic allocas in addition to dynamic realignment.
966 if (RegInfo->hasBasePointer(MF))
967 FrameReg = RegInfo->getBaseRegister();
968 else if (RegInfo->needsStackRealignment(MF))
969 FrameReg = RegInfo->getStackRegister();
971 FrameReg = RegInfo->getFrameRegister(MF);
972 return getFrameIndexOffset(MF, FI);
975 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
976 MachineBasicBlock::iterator MI,
977 const std::vector<CalleeSavedInfo> &CSI,
978 const TargetRegisterInfo *TRI) const {
982 DebugLoc DL = MBB.findDebugLoc(MI);
984 MachineFunction &MF = *MBB.getParent();
986 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
987 unsigned FPReg = TRI->getFrameRegister(MF);
988 unsigned CalleeFrameSize = 0;
990 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
991 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
993 // Push GPRs. It increases frame size.
994 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
995 for (unsigned i = CSI.size(); i != 0; --i) {
996 unsigned Reg = CSI[i-1].getReg();
997 if (!X86::GR64RegClass.contains(Reg) &&
998 !X86::GR32RegClass.contains(Reg))
1000 // Add the callee-saved register as live-in. It's killed at the spill.
1003 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1005 CalleeFrameSize += SlotSize;
1006 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1007 .setMIFlag(MachineInstr::FrameSetup);
1010 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1012 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1013 // It can be done by spilling XMMs to stack frame.
1014 // Note that only Win64 ABI might spill XMMs.
1015 for (unsigned i = CSI.size(); i != 0; --i) {
1016 unsigned Reg = CSI[i-1].getReg();
1017 if (X86::GR64RegClass.contains(Reg) ||
1018 X86::GR32RegClass.contains(Reg))
1020 // Add the callee-saved register as live-in. It's killed at the spill.
1022 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1023 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1030 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1031 MachineBasicBlock::iterator MI,
1032 const std::vector<CalleeSavedInfo> &CSI,
1033 const TargetRegisterInfo *TRI) const {
1037 DebugLoc DL = MBB.findDebugLoc(MI);
1039 MachineFunction &MF = *MBB.getParent();
1040 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1042 // Reload XMMs from stack frame.
1043 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1044 unsigned Reg = CSI[i].getReg();
1045 if (X86::GR64RegClass.contains(Reg) ||
1046 X86::GR32RegClass.contains(Reg))
1048 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1049 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1054 unsigned FPReg = TRI->getFrameRegister(MF);
1055 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1056 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1057 unsigned Reg = CSI[i].getReg();
1058 if (!X86::GR64RegClass.contains(Reg) &&
1059 !X86::GR32RegClass.contains(Reg))
1062 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1064 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1070 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1071 RegScavenger *RS) const {
1072 MachineFrameInfo *MFI = MF.getFrameInfo();
1073 const X86RegisterInfo *RegInfo =
1074 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
1075 unsigned SlotSize = RegInfo->getSlotSize();
1077 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1078 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1080 if (TailCallReturnAddrDelta < 0) {
1081 // create RETURNADDR area
1090 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1091 TailCallReturnAddrDelta - SlotSize, true);
1095 assert((TailCallReturnAddrDelta <= 0) &&
1096 "The Delta should always be zero or negative");
1097 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1099 // Create a frame entry for the EBP register that must be saved.
1100 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1102 TFI.getOffsetOfLocalArea() +
1103 TailCallReturnAddrDelta,
1105 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1106 "Slot for EBP register must be last in order to be found!");
1110 // Spill the BasePtr if it's used.
1111 if (RegInfo->hasBasePointer(MF))
1112 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1116 HasNestArgument(const MachineFunction *MF) {
1117 const Function *F = MF->getFunction();
1118 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1120 if (I->hasNestAttr())
1126 /// GetScratchRegister - Get a temp register for performing work in the
1127 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1128 /// and the properties of the function either one or two registers will be
1129 /// needed. Set primary to true for the first register, false for the second.
1131 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1132 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1135 if (CallingConvention == CallingConv::HiPE) {
1137 return Primary ? X86::R14 : X86::R13;
1139 return Primary ? X86::EBX : X86::EDI;
1143 return Primary ? X86::R11 : X86::R12;
1145 bool IsNested = HasNestArgument(&MF);
1147 if (CallingConvention == CallingConv::X86_FastCall ||
1148 CallingConvention == CallingConv::Fast) {
1150 report_fatal_error("Segmented stacks does not support fastcall with "
1151 "nested function.");
1152 return Primary ? X86::EAX : X86::ECX;
1155 return Primary ? X86::EDX : X86::EAX;
1156 return Primary ? X86::ECX : X86::EAX;
1159 // The stack limit in the TCB is set to this many bytes above the actual stack
1161 static const uint64_t kSplitStackAvailable = 256;
1164 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1165 MachineBasicBlock &prologueMBB = MF.front();
1166 MachineFrameInfo *MFI = MF.getFrameInfo();
1167 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1169 bool Is64Bit = STI.is64Bit();
1170 unsigned TlsReg, TlsOffset;
1173 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1174 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1175 "Scratch register is live-in");
1177 if (MF.getFunction()->isVarArg())
1178 report_fatal_error("Segmented stacks do not support vararg functions.");
1179 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1180 !STI.isTargetWin32() && !STI.isTargetWin64() && !STI.isTargetFreeBSD())
1181 report_fatal_error("Segmented stacks not supported on this platform.");
1183 // Eventually StackSize will be calculated by a link-time pass; which will
1184 // also decide whether checking code needs to be injected into this particular
1186 StackSize = MFI->getStackSize();
1188 // Do not generate a prologue for functions with a stack of size zero
1192 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1193 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1194 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1195 bool IsNested = false;
1197 // We need to know if the function has a nest argument only in 64 bit mode.
1199 IsNested = HasNestArgument(&MF);
1201 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1202 // allocMBB needs to be last (terminating) instruction.
1204 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1205 e = prologueMBB.livein_end(); i != e; i++) {
1206 allocMBB->addLiveIn(*i);
1207 checkMBB->addLiveIn(*i);
1211 allocMBB->addLiveIn(X86::R10);
1213 MF.push_front(allocMBB);
1214 MF.push_front(checkMBB);
1216 // When the frame size is less than 256 we just compare the stack
1217 // boundary directly to the value of the stack pointer, per gcc.
1218 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1220 // Read the limit off the current stacklet off the stack_guard location.
1222 if (STI.isTargetLinux()) {
1225 } else if (STI.isTargetDarwin()) {
1227 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1228 } else if (STI.isTargetWin64()) {
1230 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1231 } else if (STI.isTargetFreeBSD()) {
1235 report_fatal_error("Segmented stacks not supported on this platform.");
1238 if (CompareStackPointer)
1239 ScratchReg = X86::RSP;
1241 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1242 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1244 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1245 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1247 if (STI.isTargetLinux()) {
1250 } else if (STI.isTargetDarwin()) {
1252 TlsOffset = 0x48 + 90*4;
1253 } else if (STI.isTargetWin32()) {
1255 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1256 } else if (STI.isTargetFreeBSD()) {
1257 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1259 report_fatal_error("Segmented stacks not supported on this platform.");
1262 if (CompareStackPointer)
1263 ScratchReg = X86::ESP;
1265 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1266 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1268 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64()) {
1269 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1270 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1271 } else if (STI.isTargetDarwin()) {
1273 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1274 unsigned ScratchReg2;
1276 if (CompareStackPointer) {
1277 // The primary scratch register is available for holding the TLS offset.
1278 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1279 SaveScratch2 = false;
1281 // Need to use a second register to hold the TLS offset
1282 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1284 // Unfortunately, with fastcc the second scratch register may hold an
1286 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1289 // If Scratch2 is live-in then it needs to be saved.
1290 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1291 "Scratch register is live-in and not saved");
1294 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1295 .addReg(ScratchReg2, RegState::Kill);
1297 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1299 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1301 .addReg(ScratchReg2).addImm(1).addReg(0)
1306 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1310 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1311 // It jumps to normal execution of the function body.
1312 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1314 // On 32 bit we first push the arguments size and then the frame size. On 64
1315 // bit, we pass the stack frame size in r10 and the argument size in r11.
1317 // Functions with nested arguments use R10, so it needs to be saved across
1318 // the call to _morestack
1321 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1323 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1325 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1326 .addImm(X86FI->getArgumentStackSize());
1327 MF.getRegInfo().setPhysRegUsed(X86::R10);
1328 MF.getRegInfo().setPhysRegUsed(X86::R11);
1330 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1331 .addImm(X86FI->getArgumentStackSize());
1332 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1336 // __morestack is in libgcc
1338 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1339 .addExternalSymbol("__morestack");
1341 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1342 .addExternalSymbol("__morestack");
1345 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1347 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1349 allocMBB->addSuccessor(&prologueMBB);
1351 checkMBB->addSuccessor(allocMBB);
1352 checkMBB->addSuccessor(&prologueMBB);
1359 /// Erlang programs may need a special prologue to handle the stack size they
1360 /// might need at runtime. That is because Erlang/OTP does not implement a C
1361 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1362 /// (for more information see Eric Stenman's Ph.D. thesis:
1363 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1366 /// temp0 = sp - MaxStack
1367 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1371 /// call inc_stack # doubles the stack space
1372 /// temp0 = sp - MaxStack
1373 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1374 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1375 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1376 MachineFrameInfo *MFI = MF.getFrameInfo();
1377 const unsigned SlotSize =
1378 static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo())
1380 const bool Is64Bit = STI.is64Bit();
1382 // HiPE-specific values
1383 const unsigned HipeLeafWords = 24;
1384 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1385 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1386 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1387 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1388 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1390 assert(STI.isTargetLinux() &&
1391 "HiPE prologue is only supported on Linux operating systems.");
1393 // Compute the largest caller's frame that is needed to fit the callees'
1394 // frames. This 'MaxStack' is computed from:
1396 // a) the fixed frame size, which is the space needed for all spilled temps,
1397 // b) outgoing on-stack parameter areas, and
1398 // c) the minimum stack space this function needs to make available for the
1399 // functions it calls (a tunable ABI property).
1400 if (MFI->hasCalls()) {
1401 unsigned MoreStackForCalls = 0;
1403 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1404 MBBI != MBBE; ++MBBI)
1405 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1410 // Get callee operand.
1411 const MachineOperand &MO = MI->getOperand(0);
1413 // Only take account of global function calls (no closures etc.).
1417 const Function *F = dyn_cast<Function>(MO.getGlobal());
1421 // Do not update 'MaxStack' for primitive and built-in functions
1422 // (encoded with names either starting with "erlang."/"bif_" or not
1423 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1424 // "_", such as the BIF "suspend_0") as they are executed on another
1426 if (F->getName().find("erlang.") != StringRef::npos ||
1427 F->getName().find("bif_") != StringRef::npos ||
1428 F->getName().find_first_of("._") == StringRef::npos)
1431 unsigned CalleeStkArity =
1432 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1433 if (HipeLeafWords - 1 > CalleeStkArity)
1434 MoreStackForCalls = std::max(MoreStackForCalls,
1435 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1437 MaxStack += MoreStackForCalls;
1440 // If the stack frame needed is larger than the guaranteed then runtime checks
1441 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1442 if (MaxStack > Guaranteed) {
1443 MachineBasicBlock &prologueMBB = MF.front();
1444 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1445 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1447 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1448 E = prologueMBB.livein_end(); I != E; I++) {
1449 stackCheckMBB->addLiveIn(*I);
1450 incStackMBB->addLiveIn(*I);
1453 MF.push_front(incStackMBB);
1454 MF.push_front(stackCheckMBB);
1456 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1457 unsigned LEAop, CMPop, CALLop;
1461 LEAop = X86::LEA64r;
1462 CMPop = X86::CMP64rm;
1463 CALLop = X86::CALL64pcrel32;
1464 SPLimitOffset = 0x90;
1468 LEAop = X86::LEA32r;
1469 CMPop = X86::CMP32rm;
1470 CALLop = X86::CALLpcrel32;
1471 SPLimitOffset = 0x4c;
1474 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1475 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1476 "HiPE prologue scratch register is live-in");
1478 // Create new MBB for StackCheck:
1479 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1480 SPReg, false, -MaxStack);
1481 // SPLimitOffset is in a fixed heap location (pointed by BP).
1482 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1483 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1484 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1486 // Create new MBB for IncStack:
1487 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1488 addExternalSymbol("inc_stack_0");
1489 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1490 SPReg, false, -MaxStack);
1491 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1492 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1493 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1495 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1496 stackCheckMBB->addSuccessor(incStackMBB, 1);
1497 incStackMBB->addSuccessor(&prologueMBB, 99);
1498 incStackMBB->addSuccessor(incStackMBB, 1);
1505 void X86FrameLowering::
1506 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1507 MachineBasicBlock::iterator I) const {
1508 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1509 const X86RegisterInfo &RegInfo =
1510 *static_cast<const X86RegisterInfo *>(MF.getTarget().getRegisterInfo());
1511 unsigned StackPtr = RegInfo.getStackRegister();
1512 bool reseveCallFrame = hasReservedCallFrame(MF);
1513 int Opcode = I->getOpcode();
1514 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1515 bool IsLP64 = STI.isTarget64BitLP64();
1516 DebugLoc DL = I->getDebugLoc();
1517 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1518 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1521 if (!reseveCallFrame) {
1522 // If the stack pointer can be changed after prologue, turn the
1523 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1524 // adjcallstackdown instruction into 'add ESP, <amt>'
1525 // TODO: consider using push / pop instead of sub + store / add
1529 // We need to keep the stack aligned properly. To do this, we round the
1530 // amount of space needed for the outgoing arguments up to the next
1531 // alignment boundary.
1532 unsigned StackAlign =
1533 MF.getTarget().getFrameLowering()->getStackAlignment();
1534 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1536 MachineInstr *New = nullptr;
1537 if (Opcode == TII.getCallFrameSetupOpcode()) {
1538 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1543 assert(Opcode == TII.getCallFrameDestroyOpcode());
1545 // Factor out the amount the callee already popped.
1546 Amount -= CalleeAmt;
1549 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1550 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1551 .addReg(StackPtr).addImm(Amount);
1556 // The EFLAGS implicit def is dead.
1557 New->getOperand(3).setIsDead();
1559 // Replace the pseudo instruction with a new instruction.
1566 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1567 // If we are performing frame pointer elimination and if the callee pops
1568 // something off the stack pointer, add it back. We do this until we have
1569 // more advanced stack pointer tracking ability.
1570 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1571 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1572 .addReg(StackPtr).addImm(CalleeAmt);
1574 // The EFLAGS implicit def is dead.
1575 New->getOperand(3).setIsDead();
1577 // We are not tracking the stack pointer adjustment by the callee, so make
1578 // sure we restore the stack pointer immediately after the call, there may
1579 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1580 MachineBasicBlock::iterator B = MBB.begin();
1581 while (I != B && !std::prev(I)->isCall())