1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // pseudo registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // The x87 hardware tracks liveness of the stack registers, so it is necessary
16 // to implement exact liveness tracking between basic blocks. The CFG edges are
17 // partitioned into bundles where the same FP registers must be live in
18 // identical stack positions. Instructions are inserted at the end of each basic
19 // block to rearrange the live registers to match the outgoing bundle.
21 // This approach avoids splitting critical edges at the potential cost of more
22 // live register shuffling instructions when critical edges are present.
24 //===----------------------------------------------------------------------===//
26 #define DEBUG_TYPE "x86-codegen"
28 #include "X86InstrInfo.h"
29 #include "llvm/ADT/DepthFirstIterator.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/CodeGen/EdgeBundles.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetMachine.h"
48 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
49 STATISTIC(NumFP , "Number of floating point instructions");
52 struct FPS : public MachineFunctionPass {
54 FPS() : MachineFunctionPass(ID) {
55 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
56 // This is really only to keep valgrind quiet.
57 // The logic in isLive() is too much for it.
58 memset(Stack, 0, sizeof(Stack));
59 memset(RegMap, 0, sizeof(RegMap));
62 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 AU.addRequired<EdgeBundles>();
65 AU.addPreservedID(MachineLoopInfoID);
66 AU.addPreservedID(MachineDominatorsID);
67 MachineFunctionPass::getAnalysisUsage(AU);
70 virtual bool runOnMachineFunction(MachineFunction &MF);
72 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
75 const TargetInstrInfo *TII; // Machine instruction info.
77 // Two CFG edges are related if they leave the same block, or enter the same
78 // block. The transitive closure of an edge under this relation is a
79 // LiveBundle. It represents a set of CFG edges where the live FP stack
80 // registers must be allocated identically in the x87 stack.
82 // A LiveBundle is usually all the edges leaving a block, or all the edges
83 // entering a block, but it can contain more edges if critical edges are
86 // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
87 // but the exact mapping of FP registers to stack slots is fixed later.
89 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
92 // Number of pre-assigned live registers in FixStack. This is 0 when the
93 // stack order has not yet been fixed.
96 // Assigned stack order for live-in registers.
97 // FixStack[i] == getStackEntry(i) for all i < FixCount.
98 unsigned char FixStack[8];
100 LiveBundle(unsigned m = 0) : Mask(m), FixCount(0) {}
102 // Have the live registers been assigned a stack order yet?
103 bool isFixed() const { return !Mask || FixCount; }
106 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
107 // with no live FP registers.
108 SmallVector<LiveBundle, 8> LiveBundles;
110 // Map each MBB in the current function to an (ingoing, outgoing) index into
111 // LiveBundles. Blocks with no FP registers live in or out map to (0, 0)
112 // and are not actually stored in the map.
113 DenseMap<MachineBasicBlock*, std::pair<unsigned, unsigned> > BlockBundle;
115 // Return a bitmask of FP registers in block's live-in list.
116 unsigned calcLiveInMask(MachineBasicBlock *MBB) {
118 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
119 E = MBB->livein_end(); I != E; ++I) {
120 unsigned Reg = *I - X86::FP0;
127 // Partition all the CFG edges into LiveBundles.
128 void bundleCFG(MachineFunction &MF);
130 MachineBasicBlock *MBB; // Current basic block
131 unsigned Stack[8]; // FP<n> Registers in each stack slot...
132 unsigned RegMap[8]; // Track which stack slot contains each register
133 unsigned StackTop; // The current top of the FP stack.
135 // Set up our stack model to match the incoming registers to MBB.
136 void setupBlockStack();
138 // Shuffle live registers to match the expectations of successor blocks.
139 void finishBlockStack();
141 void dumpStack() const {
142 dbgs() << "Stack contents:";
143 for (unsigned i = 0; i != StackTop; ++i) {
144 dbgs() << " FP" << Stack[i];
145 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
150 /// getSlot - Return the stack slot number a particular register number is
152 unsigned getSlot(unsigned RegNo) const {
153 assert(RegNo < 8 && "Regno out of range!");
154 return RegMap[RegNo];
157 /// isLive - Is RegNo currently live in the stack?
158 bool isLive(unsigned RegNo) const {
159 unsigned Slot = getSlot(RegNo);
160 return Slot < StackTop && Stack[Slot] == RegNo;
163 /// getScratchReg - Return an FP register that is not currently in use.
164 unsigned getScratchReg() {
165 for (int i = 7; i >= 0; --i)
168 llvm_unreachable("Ran out of scratch FP registers");
171 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
172 unsigned getStackEntry(unsigned STi) const {
174 report_fatal_error("Access past stack top!");
175 return Stack[StackTop-1-STi];
178 /// getSTReg - Return the X86::ST(i) register which contains the specified
179 /// FP<RegNo> register.
180 unsigned getSTReg(unsigned RegNo) const {
181 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
184 // pushReg - Push the specified FP<n> register onto the stack.
185 void pushReg(unsigned Reg) {
186 assert(Reg < 8 && "Register number out of range!");
188 report_fatal_error("Stack overflow!");
189 Stack[StackTop] = Reg;
190 RegMap[Reg] = StackTop++;
193 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
194 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
195 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
196 if (isAtTop(RegNo)) return;
198 unsigned STReg = getSTReg(RegNo);
199 unsigned RegOnTop = getStackEntry(0);
201 // Swap the slots the regs are in.
202 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
204 // Swap stack slot contents.
205 if (RegMap[RegOnTop] >= StackTop)
206 report_fatal_error("Access past stack top!");
207 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
209 // Emit an fxch to update the runtime processors version of the state.
210 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
214 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
215 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
216 unsigned STReg = getSTReg(RegNo);
217 pushReg(AsReg); // New register on top of stack
219 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
222 /// popStackAfter - Pop the current value off of the top of the FP stack
223 /// after the specified instruction.
224 void popStackAfter(MachineBasicBlock::iterator &I);
226 /// freeStackSlotAfter - Free the specified register from the register
227 /// stack, so that it is no longer in a register. If the register is
228 /// currently at the top of the stack, we just pop the current instruction,
229 /// otherwise we store the current top-of-stack into the specified slot,
230 /// then pop the top of stack.
231 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
233 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
235 MachineBasicBlock::iterator
236 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
238 /// Adjust the live registers to be the set in Mask.
239 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
241 /// Shuffle the top FixCount stack entries susch that FP reg FixStack[0] is
242 /// st(0), FP reg FixStack[1] is st(1) etc.
243 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
244 MachineBasicBlock::iterator I);
246 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
248 void handleZeroArgFP(MachineBasicBlock::iterator &I);
249 void handleOneArgFP(MachineBasicBlock::iterator &I);
250 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
251 void handleTwoArgFP(MachineBasicBlock::iterator &I);
252 void handleCompareFP(MachineBasicBlock::iterator &I);
253 void handleCondMovFP(MachineBasicBlock::iterator &I);
254 void handleSpecialFP(MachineBasicBlock::iterator &I);
256 bool translateCopy(MachineInstr*);
261 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
263 /// getFPReg - Return the X86::FPx register number for the specified operand.
264 /// For example, this returns 3 for X86::FP3.
265 static unsigned getFPReg(const MachineOperand &MO) {
266 assert(MO.isReg() && "Expected an FP register!");
267 unsigned Reg = MO.getReg();
268 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
269 return Reg - X86::FP0;
272 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
273 /// register references into FP stack references.
275 bool FPS::runOnMachineFunction(MachineFunction &MF) {
276 // We only need to run this pass if there are any FP registers used in this
277 // function. If it is all integer, there is nothing for us to do!
278 bool FPIsUsed = false;
280 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
281 for (unsigned i = 0; i <= 6; ++i)
282 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
288 if (!FPIsUsed) return false;
290 TII = MF.getTarget().getInstrInfo();
292 // Prepare cross-MBB liveness.
297 // Process the function in depth first order so that we process at least one
298 // of the predecessors for every reachable block in the function.
299 SmallPtrSet<MachineBasicBlock*, 8> Processed;
300 MachineBasicBlock *Entry = MF.begin();
302 bool Changed = false;
303 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
304 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
306 Changed |= processBasicBlock(MF, **I);
308 // Process any unreachable blocks in arbitrary order now.
309 if (MF.size() != Processed.size())
310 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
311 if (Processed.insert(BB))
312 Changed |= processBasicBlock(MF, *BB);
320 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
321 /// live-out sets for the FP registers. Consistent means that the set of
322 /// registers live-out from a block is identical to the live-in set of all
323 /// successors. This is not enforced by the normal live-in lists since
324 /// registers may be implicitly defined, or not used by all successors.
325 void FPS::bundleCFG(MachineFunction &MF) {
326 assert(LiveBundles.empty() && "Stale data in LiveBundles");
327 assert(BlockBundle.empty() && "Stale data in BlockBundle");
328 SmallPtrSet<MachineBasicBlock*, 8> PropDown, PropUp;
330 // LiveBundle[0] is the empty live-in set.
331 LiveBundles.resize(1);
333 // First gather the actual live-in masks for all MBBs.
334 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
335 MachineBasicBlock *MBB = I;
336 const unsigned Mask = calcLiveInMask(MBB);
339 // Ingoing bundle index.
340 unsigned &Idx = BlockBundle[MBB].first;
341 // Already assigned an ingoing bundle?
344 // Allocate a new LiveBundle struct for this block's live-ins.
345 const unsigned BundleIdx = Idx = LiveBundles.size();
346 DEBUG(dbgs() << "Creating LB#" << BundleIdx << ": in:BB#"
347 << MBB->getNumber());
348 LiveBundles.push_back(Mask);
349 LiveBundle &Bundle = LiveBundles.back();
351 // Make sure all predecessors have the same live-out set.
354 // Keep pushing liveness up and down the CFG until convergence.
355 // Only critical edges cause iteration here, but when they do, multiple
356 // blocks can be assigned to the same LiveBundle index.
358 // Assign BundleIdx as liveout from predecessors in PropUp.
359 for (SmallPtrSet<MachineBasicBlock*, 16>::iterator I = PropUp.begin(),
360 E = PropUp.end(); I != E; ++I) {
361 MachineBasicBlock *MBB = *I;
362 for (MachineBasicBlock::const_pred_iterator LinkI = MBB->pred_begin(),
363 LinkE = MBB->pred_end(); LinkI != LinkE; ++LinkI) {
364 MachineBasicBlock *PredMBB = *LinkI;
365 // PredMBB's liveout bundle should be set to LIIdx.
366 unsigned &Idx = BlockBundle[PredMBB].second;
368 assert(Idx == BundleIdx && "Inconsistent CFG");
372 DEBUG(dbgs() << " out:BB#" << PredMBB->getNumber());
373 // Propagate to siblings.
374 if (PredMBB->succ_size() > 1)
375 PropDown.insert(PredMBB);
380 // Assign BundleIdx as livein to successors in PropDown.
381 for (SmallPtrSet<MachineBasicBlock*, 16>::iterator I = PropDown.begin(),
382 E = PropDown.end(); I != E; ++I) {
383 MachineBasicBlock *MBB = *I;
384 for (MachineBasicBlock::const_succ_iterator LinkI = MBB->succ_begin(),
385 LinkE = MBB->succ_end(); LinkI != LinkE; ++LinkI) {
386 MachineBasicBlock *SuccMBB = *LinkI;
387 // LinkMBB's livein bundle should be set to BundleIdx.
388 unsigned &Idx = BlockBundle[SuccMBB].first;
390 assert(Idx == BundleIdx && "Inconsistent CFG");
394 DEBUG(dbgs() << " in:BB#" << SuccMBB->getNumber());
395 // Propagate to siblings.
396 if (SuccMBB->pred_size() > 1)
397 PropUp.insert(SuccMBB);
398 // Also accumulate the bundle liveness mask from the liveins here.
399 Bundle.Mask |= calcLiveInMask(SuccMBB);
403 } while (!PropUp.empty());
406 for (unsigned i = 0; i < 8; ++i)
407 if (Bundle.Mask & (1<<i))
408 dbgs() << " %FP" << i;
414 /// processBasicBlock - Loop over all of the instructions in the basic block,
415 /// transforming FP instructions into their stack form.
417 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
418 bool Changed = false;
423 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
424 MachineInstr *MI = I;
425 uint64_t Flags = MI->getDesc().TSFlags;
427 unsigned FPInstClass = Flags & X86II::FPTypeMask;
428 if (MI->isInlineAsm())
429 FPInstClass = X86II::SpecialFP;
431 if (MI->isCopy() && translateCopy(MI))
432 FPInstClass = X86II::SpecialFP;
434 if (FPInstClass == X86II::NotFP)
435 continue; // Efficiently ignore non-fp insts!
437 MachineInstr *PrevMI = 0;
441 ++NumFP; // Keep track of # of pseudo instrs
442 DEBUG(dbgs() << "\nFPInst:\t" << *MI);
444 // Get dead variables list now because the MI pointer may be deleted as part
446 SmallVector<unsigned, 8> DeadRegs;
447 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
448 const MachineOperand &MO = MI->getOperand(i);
449 if (MO.isReg() && MO.isDead())
450 DeadRegs.push_back(MO.getReg());
453 switch (FPInstClass) {
454 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
455 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
456 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
457 case X86II::TwoArgFP: handleTwoArgFP(I); break;
458 case X86II::CompareFP: handleCompareFP(I); break;
459 case X86II::CondMovFP: handleCondMovFP(I); break;
460 case X86II::SpecialFP: handleSpecialFP(I); break;
461 default: llvm_unreachable("Unknown FP Type!");
464 // Check to see if any of the values defined by this instruction are dead
465 // after definition. If so, pop them.
466 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
467 unsigned Reg = DeadRegs[i];
468 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
469 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
470 freeStackSlotAfter(I, Reg-X86::FP0);
474 // Print out all of the instructions expanded to if -debug
476 MachineBasicBlock::iterator PrevI(PrevMI);
478 dbgs() << "Just deleted pseudo instruction\n";
480 MachineBasicBlock::iterator Start = I;
481 // Rewind to first instruction newly inserted.
482 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
483 dbgs() << "Inserted instructions:\n\t";
484 Start->print(dbgs(), &MF.getTarget());
485 while (++Start != llvm::next(I)) {}
498 /// setupBlockStack - Use the BlockBundle map to set up our model of the stack
499 /// to match predecessors' live out stack.
500 void FPS::setupBlockStack() {
501 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
502 << " derived from " << MBB->getName() << ".\n");
504 const LiveBundle &Bundle = LiveBundles[BlockBundle.lookup(MBB).first];
507 DEBUG(dbgs() << "Block has no FP live-ins.\n");
511 // Depth-first iteration should ensure that we always have an assigned stack.
512 assert(Bundle.isFixed() && "Reached block before any predecessors");
514 // Push the fixed live-in registers.
515 for (unsigned i = Bundle.FixCount; i > 0; --i) {
516 MBB->addLiveIn(X86::ST0+i-1);
517 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
518 << unsigned(Bundle.FixStack[i-1]) << '\n');
519 pushReg(Bundle.FixStack[i-1]);
522 // Kill off unwanted live-ins. This can happen with a critical edge.
523 // FIXME: We could keep these live registers around as zombies. They may need
524 // to be revived at the end of a short block. It might save a few instrs.
525 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
529 /// finishBlockStack - Revive live-outs that are implicitly defined out of
530 /// MBB. Shuffle live registers to match the expected fixed stack of any
531 /// predecessors, and ensure that all predecessors are expecting the same
533 void FPS::finishBlockStack() {
534 // The RET handling below takes care of return blocks for us.
535 if (MBB->succ_empty())
538 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
539 << " derived from " << MBB->getName() << ".\n");
541 unsigned BundleIdx = BlockBundle.lookup(MBB).second;
542 LiveBundle &Bundle = LiveBundles[BundleIdx];
544 // We may need to kill and define some registers to match successors.
545 // FIXME: This can probably be combined with the shuffle below.
546 MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
547 adjustLiveRegs(Bundle.Mask, Term);
550 DEBUG(dbgs() << "No live-outs.\n");
554 // Has the stack order been fixed yet?
555 DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
556 if (Bundle.isFixed()) {
557 DEBUG(dbgs() << "Shuffling stack to match.\n");
558 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
560 // Not fixed yet, we get to choose.
561 DEBUG(dbgs() << "Fixing stack order now.\n");
562 Bundle.FixCount = StackTop;
563 for (unsigned i = 0; i < StackTop; ++i)
564 Bundle.FixStack[i] = getStackEntry(i);
569 //===----------------------------------------------------------------------===//
570 // Efficient Lookup Table Support
571 //===----------------------------------------------------------------------===//
577 bool operator<(const TableEntry &TE) const { return from < TE.from; }
578 friend bool operator<(const TableEntry &TE, unsigned V) {
581 friend bool LLVM_ATTRIBUTE_USED operator<(unsigned V,
582 const TableEntry &TE) {
589 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
590 for (unsigned i = 0; i != NumEntries-1; ++i)
591 if (!(Table[i] < Table[i+1])) return false;
596 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
597 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
598 if (I != Table+N && I->from == Opcode)
604 #define ASSERT_SORTED(TABLE)
606 #define ASSERT_SORTED(TABLE) \
607 { static bool TABLE##Checked = false; \
608 if (!TABLE##Checked) { \
609 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
610 "All lookup tables must be sorted for efficient access!"); \
611 TABLE##Checked = true; \
616 //===----------------------------------------------------------------------===//
617 // Register File -> Register Stack Mapping Methods
618 //===----------------------------------------------------------------------===//
620 // OpcodeTable - Sorted map of register instructions to their stack version.
621 // The first element is an register file pseudo instruction, the second is the
622 // concrete X86 instruction which uses the register stack.
624 static const TableEntry OpcodeTable[] = {
625 { X86::ABS_Fp32 , X86::ABS_F },
626 { X86::ABS_Fp64 , X86::ABS_F },
627 { X86::ABS_Fp80 , X86::ABS_F },
628 { X86::ADD_Fp32m , X86::ADD_F32m },
629 { X86::ADD_Fp64m , X86::ADD_F64m },
630 { X86::ADD_Fp64m32 , X86::ADD_F32m },
631 { X86::ADD_Fp80m32 , X86::ADD_F32m },
632 { X86::ADD_Fp80m64 , X86::ADD_F64m },
633 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
634 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
635 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
636 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
637 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
638 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
639 { X86::CHS_Fp32 , X86::CHS_F },
640 { X86::CHS_Fp64 , X86::CHS_F },
641 { X86::CHS_Fp80 , X86::CHS_F },
642 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
643 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
644 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
645 { X86::CMOVB_Fp32 , X86::CMOVB_F },
646 { X86::CMOVB_Fp64 , X86::CMOVB_F },
647 { X86::CMOVB_Fp80 , X86::CMOVB_F },
648 { X86::CMOVE_Fp32 , X86::CMOVE_F },
649 { X86::CMOVE_Fp64 , X86::CMOVE_F },
650 { X86::CMOVE_Fp80 , X86::CMOVE_F },
651 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
652 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
653 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
654 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
655 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
656 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
657 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
658 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
659 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
660 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
661 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
662 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
663 { X86::CMOVP_Fp32 , X86::CMOVP_F },
664 { X86::CMOVP_Fp64 , X86::CMOVP_F },
665 { X86::CMOVP_Fp80 , X86::CMOVP_F },
666 { X86::COS_Fp32 , X86::COS_F },
667 { X86::COS_Fp64 , X86::COS_F },
668 { X86::COS_Fp80 , X86::COS_F },
669 { X86::DIVR_Fp32m , X86::DIVR_F32m },
670 { X86::DIVR_Fp64m , X86::DIVR_F64m },
671 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
672 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
673 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
674 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
675 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
676 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
677 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
678 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
679 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
680 { X86::DIV_Fp32m , X86::DIV_F32m },
681 { X86::DIV_Fp64m , X86::DIV_F64m },
682 { X86::DIV_Fp64m32 , X86::DIV_F32m },
683 { X86::DIV_Fp80m32 , X86::DIV_F32m },
684 { X86::DIV_Fp80m64 , X86::DIV_F64m },
685 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
686 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
687 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
688 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
689 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
690 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
691 { X86::ILD_Fp16m32 , X86::ILD_F16m },
692 { X86::ILD_Fp16m64 , X86::ILD_F16m },
693 { X86::ILD_Fp16m80 , X86::ILD_F16m },
694 { X86::ILD_Fp32m32 , X86::ILD_F32m },
695 { X86::ILD_Fp32m64 , X86::ILD_F32m },
696 { X86::ILD_Fp32m80 , X86::ILD_F32m },
697 { X86::ILD_Fp64m32 , X86::ILD_F64m },
698 { X86::ILD_Fp64m64 , X86::ILD_F64m },
699 { X86::ILD_Fp64m80 , X86::ILD_F64m },
700 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
701 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
702 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
703 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
704 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
705 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
706 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
707 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
708 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
709 { X86::IST_Fp16m32 , X86::IST_F16m },
710 { X86::IST_Fp16m64 , X86::IST_F16m },
711 { X86::IST_Fp16m80 , X86::IST_F16m },
712 { X86::IST_Fp32m32 , X86::IST_F32m },
713 { X86::IST_Fp32m64 , X86::IST_F32m },
714 { X86::IST_Fp32m80 , X86::IST_F32m },
715 { X86::IST_Fp64m32 , X86::IST_FP64m },
716 { X86::IST_Fp64m64 , X86::IST_FP64m },
717 { X86::IST_Fp64m80 , X86::IST_FP64m },
718 { X86::LD_Fp032 , X86::LD_F0 },
719 { X86::LD_Fp064 , X86::LD_F0 },
720 { X86::LD_Fp080 , X86::LD_F0 },
721 { X86::LD_Fp132 , X86::LD_F1 },
722 { X86::LD_Fp164 , X86::LD_F1 },
723 { X86::LD_Fp180 , X86::LD_F1 },
724 { X86::LD_Fp32m , X86::LD_F32m },
725 { X86::LD_Fp32m64 , X86::LD_F32m },
726 { X86::LD_Fp32m80 , X86::LD_F32m },
727 { X86::LD_Fp64m , X86::LD_F64m },
728 { X86::LD_Fp64m80 , X86::LD_F64m },
729 { X86::LD_Fp80m , X86::LD_F80m },
730 { X86::MUL_Fp32m , X86::MUL_F32m },
731 { X86::MUL_Fp64m , X86::MUL_F64m },
732 { X86::MUL_Fp64m32 , X86::MUL_F32m },
733 { X86::MUL_Fp80m32 , X86::MUL_F32m },
734 { X86::MUL_Fp80m64 , X86::MUL_F64m },
735 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
736 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
737 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
738 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
739 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
740 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
741 { X86::SIN_Fp32 , X86::SIN_F },
742 { X86::SIN_Fp64 , X86::SIN_F },
743 { X86::SIN_Fp80 , X86::SIN_F },
744 { X86::SQRT_Fp32 , X86::SQRT_F },
745 { X86::SQRT_Fp64 , X86::SQRT_F },
746 { X86::SQRT_Fp80 , X86::SQRT_F },
747 { X86::ST_Fp32m , X86::ST_F32m },
748 { X86::ST_Fp64m , X86::ST_F64m },
749 { X86::ST_Fp64m32 , X86::ST_F32m },
750 { X86::ST_Fp80m32 , X86::ST_F32m },
751 { X86::ST_Fp80m64 , X86::ST_F64m },
752 { X86::ST_FpP80m , X86::ST_FP80m },
753 { X86::SUBR_Fp32m , X86::SUBR_F32m },
754 { X86::SUBR_Fp64m , X86::SUBR_F64m },
755 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
756 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
757 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
758 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
759 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
760 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
761 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
762 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
763 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
764 { X86::SUB_Fp32m , X86::SUB_F32m },
765 { X86::SUB_Fp64m , X86::SUB_F64m },
766 { X86::SUB_Fp64m32 , X86::SUB_F32m },
767 { X86::SUB_Fp80m32 , X86::SUB_F32m },
768 { X86::SUB_Fp80m64 , X86::SUB_F64m },
769 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
770 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
771 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
772 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
773 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
774 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
775 { X86::TST_Fp32 , X86::TST_F },
776 { X86::TST_Fp64 , X86::TST_F },
777 { X86::TST_Fp80 , X86::TST_F },
778 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
779 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
780 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
781 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
782 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
783 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
786 static unsigned getConcreteOpcode(unsigned Opcode) {
787 ASSERT_SORTED(OpcodeTable);
788 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
789 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
793 //===----------------------------------------------------------------------===//
795 //===----------------------------------------------------------------------===//
797 // PopTable - Sorted map of instructions to their popping version. The first
798 // element is an instruction, the second is the version which pops.
800 static const TableEntry PopTable[] = {
801 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
803 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
804 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
806 { X86::IST_F16m , X86::IST_FP16m },
807 { X86::IST_F32m , X86::IST_FP32m },
809 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
811 { X86::ST_F32m , X86::ST_FP32m },
812 { X86::ST_F64m , X86::ST_FP64m },
813 { X86::ST_Frr , X86::ST_FPrr },
815 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
816 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
818 { X86::UCOM_FIr , X86::UCOM_FIPr },
820 { X86::UCOM_FPr , X86::UCOM_FPPr },
821 { X86::UCOM_Fr , X86::UCOM_FPr },
824 /// popStackAfter - Pop the current value off of the top of the FP stack after
825 /// the specified instruction. This attempts to be sneaky and combine the pop
826 /// into the instruction itself if possible. The iterator is left pointing to
827 /// the last instruction, be it a new pop instruction inserted, or the old
828 /// instruction if it was modified in place.
830 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
831 MachineInstr* MI = I;
832 DebugLoc dl = MI->getDebugLoc();
833 ASSERT_SORTED(PopTable);
835 report_fatal_error("Cannot pop empty stack!");
836 RegMap[Stack[--StackTop]] = ~0; // Update state
838 // Check to see if there is a popping version of this instruction...
839 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
841 I->setDesc(TII->get(Opcode));
842 if (Opcode == X86::UCOM_FPPr)
844 } else { // Insert an explicit pop
845 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
849 /// freeStackSlotAfter - Free the specified register from the register stack, so
850 /// that it is no longer in a register. If the register is currently at the top
851 /// of the stack, we just pop the current instruction, otherwise we store the
852 /// current top-of-stack into the specified slot, then pop the top of stack.
853 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
854 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
859 // Otherwise, store the top of stack into the dead slot, killing the operand
860 // without having to add in an explicit xchg then pop.
862 I = freeStackSlotBefore(++I, FPRegNo);
865 /// freeStackSlotBefore - Free the specified register without trying any
867 MachineBasicBlock::iterator
868 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
869 unsigned STReg = getSTReg(FPRegNo);
870 unsigned OldSlot = getSlot(FPRegNo);
871 unsigned TopReg = Stack[StackTop-1];
872 Stack[OldSlot] = TopReg;
873 RegMap[TopReg] = OldSlot;
874 RegMap[FPRegNo] = ~0;
875 Stack[--StackTop] = ~0;
876 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg);
879 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
880 /// registers with a bit in Mask are live.
881 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
882 unsigned Defs = Mask;
884 for (unsigned i = 0; i < StackTop; ++i) {
885 unsigned RegNo = Stack[i];
886 if (!(Defs & (1 << RegNo)))
887 // This register is live, but we don't want it.
888 Kills |= (1 << RegNo);
890 // We don't need to imp-def this live register.
891 Defs &= ~(1 << RegNo);
893 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
895 // Produce implicit-defs for free by using killed registers.
896 while (Kills && Defs) {
897 unsigned KReg = CountTrailingZeros_32(Kills);
898 unsigned DReg = CountTrailingZeros_32(Defs);
899 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
900 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
901 std::swap(RegMap[KReg], RegMap[DReg]);
902 Kills &= ~(1 << KReg);
903 Defs &= ~(1 << DReg);
906 // Kill registers by popping.
907 if (Kills && I != MBB->begin()) {
908 MachineBasicBlock::iterator I2 = llvm::prior(I);
910 unsigned KReg = getStackEntry(0);
911 if (!(Kills & (1 << KReg)))
913 DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
915 Kills &= ~(1 << KReg);
919 // Manually kill the rest.
921 unsigned KReg = CountTrailingZeros_32(Kills);
922 DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
923 freeStackSlotBefore(I, KReg);
924 Kills &= ~(1 << KReg);
927 // Load zeros for all the imp-defs.
929 unsigned DReg = CountTrailingZeros_32(Defs);
930 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
931 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
933 Defs &= ~(1 << DReg);
936 // Now we should have the correct registers live.
938 assert(StackTop == CountPopulation_32(Mask) && "Live count mismatch");
941 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
942 /// FixCount entries into the order given by FixStack.
943 /// FIXME: Is there a better algorithm than insertion sort?
944 void FPS::shuffleStackTop(const unsigned char *FixStack,
946 MachineBasicBlock::iterator I) {
947 // Move items into place, starting from the desired stack bottom.
949 // Old register at position FixCount.
950 unsigned OldReg = getStackEntry(FixCount);
951 // Desired register at position FixCount.
952 unsigned Reg = FixStack[FixCount];
955 // (Reg st0) (OldReg st0) = (Reg OldReg st0)
957 moveToTop(OldReg, I);
963 //===----------------------------------------------------------------------===//
964 // Instruction transformation implementation
965 //===----------------------------------------------------------------------===//
967 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
969 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
970 MachineInstr *MI = I;
971 unsigned DestReg = getFPReg(MI->getOperand(0));
973 // Change from the pseudo instruction to the concrete instruction.
974 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
975 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
977 // Result gets pushed on the stack.
981 /// handleOneArgFP - fst <mem>, ST(0)
983 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
984 MachineInstr *MI = I;
985 unsigned NumOps = MI->getDesc().getNumOperands();
986 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
987 "Can only handle fst* & ftst instructions!");
989 // Is this the last use of the source register?
990 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
991 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
993 // FISTP64m is strange because there isn't a non-popping versions.
994 // If we have one _and_ we don't want to pop the operand, duplicate the value
995 // on the stack instead of moving it. This ensure that popping the value is
997 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
1000 (MI->getOpcode() == X86::IST_Fp64m32 ||
1001 MI->getOpcode() == X86::ISTT_Fp16m32 ||
1002 MI->getOpcode() == X86::ISTT_Fp32m32 ||
1003 MI->getOpcode() == X86::ISTT_Fp64m32 ||
1004 MI->getOpcode() == X86::IST_Fp64m64 ||
1005 MI->getOpcode() == X86::ISTT_Fp16m64 ||
1006 MI->getOpcode() == X86::ISTT_Fp32m64 ||
1007 MI->getOpcode() == X86::ISTT_Fp64m64 ||
1008 MI->getOpcode() == X86::IST_Fp64m80 ||
1009 MI->getOpcode() == X86::ISTT_Fp16m80 ||
1010 MI->getOpcode() == X86::ISTT_Fp32m80 ||
1011 MI->getOpcode() == X86::ISTT_Fp64m80 ||
1012 MI->getOpcode() == X86::ST_FpP80m)) {
1013 duplicateToTop(Reg, getScratchReg(), I);
1015 moveToTop(Reg, I); // Move to the top of the stack...
1018 // Convert from the pseudo instruction to the concrete instruction.
1019 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
1020 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1022 if (MI->getOpcode() == X86::IST_FP64m ||
1023 MI->getOpcode() == X86::ISTT_FP16m ||
1024 MI->getOpcode() == X86::ISTT_FP32m ||
1025 MI->getOpcode() == X86::ISTT_FP64m ||
1026 MI->getOpcode() == X86::ST_FP80m) {
1028 report_fatal_error("Stack empty??");
1030 } else if (KillsSrc) { // Last use of operand?
1036 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1037 /// replace the value with a newly computed value. These instructions may have
1038 /// non-fp operands after their FP operands.
1042 /// R1 = fadd R2, [mem]
1044 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1045 MachineInstr *MI = I;
1047 unsigned NumOps = MI->getDesc().getNumOperands();
1048 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1051 // Is this the last use of the source register?
1052 unsigned Reg = getFPReg(MI->getOperand(1));
1053 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
1056 // If this is the last use of the source register, just make sure it's on
1057 // the top of the stack.
1060 report_fatal_error("Stack cannot be empty!");
1062 pushReg(getFPReg(MI->getOperand(0)));
1064 // If this is not the last use of the source register, _copy_ it to the top
1066 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
1069 // Change from the pseudo instruction to the concrete instruction.
1070 MI->RemoveOperand(1); // Drop the source operand.
1071 MI->RemoveOperand(0); // Drop the destination operand.
1072 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1076 //===----------------------------------------------------------------------===//
1077 // Define tables of various ways to map pseudo instructions
1080 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1081 static const TableEntry ForwardST0Table[] = {
1082 { X86::ADD_Fp32 , X86::ADD_FST0r },
1083 { X86::ADD_Fp64 , X86::ADD_FST0r },
1084 { X86::ADD_Fp80 , X86::ADD_FST0r },
1085 { X86::DIV_Fp32 , X86::DIV_FST0r },
1086 { X86::DIV_Fp64 , X86::DIV_FST0r },
1087 { X86::DIV_Fp80 , X86::DIV_FST0r },
1088 { X86::MUL_Fp32 , X86::MUL_FST0r },
1089 { X86::MUL_Fp64 , X86::MUL_FST0r },
1090 { X86::MUL_Fp80 , X86::MUL_FST0r },
1091 { X86::SUB_Fp32 , X86::SUB_FST0r },
1092 { X86::SUB_Fp64 , X86::SUB_FST0r },
1093 { X86::SUB_Fp80 , X86::SUB_FST0r },
1096 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1097 static const TableEntry ReverseST0Table[] = {
1098 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1099 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1100 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1101 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1102 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1103 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1104 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1105 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1106 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1107 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1108 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1109 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1112 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1113 static const TableEntry ForwardSTiTable[] = {
1114 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1115 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1116 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1117 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1118 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1119 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1120 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1121 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1122 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1123 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1124 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1125 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1128 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1129 static const TableEntry ReverseSTiTable[] = {
1130 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1131 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1132 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1133 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1134 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1135 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1136 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1137 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1138 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1139 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1140 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1141 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1145 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1146 /// instructions which need to be simplified and possibly transformed.
1148 /// Result: ST(0) = fsub ST(0), ST(i)
1149 /// ST(i) = fsub ST(0), ST(i)
1150 /// ST(0) = fsubr ST(0), ST(i)
1151 /// ST(i) = fsubr ST(0), ST(i)
1153 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1154 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1155 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1156 MachineInstr *MI = I;
1158 unsigned NumOperands = MI->getDesc().getNumOperands();
1159 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1160 unsigned Dest = getFPReg(MI->getOperand(0));
1161 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1162 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1163 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1164 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1165 DebugLoc dl = MI->getDebugLoc();
1167 unsigned TOS = getStackEntry(0);
1169 // One of our operands must be on the top of the stack. If neither is yet, we
1170 // need to move one.
1171 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1172 // We can choose to move either operand to the top of the stack. If one of
1173 // the operands is killed by this instruction, we want that one so that we
1174 // can update right on top of the old version.
1176 moveToTop(Op0, I); // Move dead operand to TOS.
1178 } else if (KillsOp1) {
1182 // All of the operands are live after this instruction executes, so we
1183 // cannot update on top of any operand. Because of this, we must
1184 // duplicate one of the stack elements to the top. It doesn't matter
1185 // which one we pick.
1187 duplicateToTop(Op0, Dest, I);
1191 } else if (!KillsOp0 && !KillsOp1) {
1192 // If we DO have one of our operands at the top of the stack, but we don't
1193 // have a dead operand, we must duplicate one of the operands to a new slot
1195 duplicateToTop(Op0, Dest, I);
1200 // Now we know that one of our operands is on the top of the stack, and at
1201 // least one of our operands is killed by this instruction.
1202 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1203 "Stack conditions not set up right!");
1205 // We decide which form to use based on what is on the top of the stack, and
1206 // which operand is killed by this instruction.
1207 const TableEntry *InstTable;
1208 bool isForward = TOS == Op0;
1209 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1212 InstTable = ForwardST0Table;
1214 InstTable = ReverseST0Table;
1217 InstTable = ForwardSTiTable;
1219 InstTable = ReverseSTiTable;
1222 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
1224 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1226 // NotTOS - The register which is not on the top of stack...
1227 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1229 // Replace the old instruction with a new instruction
1231 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1233 // If both operands are killed, pop one off of the stack in addition to
1234 // overwriting the other one.
1235 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1236 assert(!updateST0 && "Should have updated other operand!");
1237 popStackAfter(I); // Pop the top of stack
1240 // Update stack information so that we know the destination register is now on
1242 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1243 assert(UpdatedSlot < StackTop && Dest < 7);
1244 Stack[UpdatedSlot] = Dest;
1245 RegMap[Dest] = UpdatedSlot;
1246 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
1249 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1250 /// register arguments and no explicit destinations.
1252 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1253 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1254 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1255 MachineInstr *MI = I;
1257 unsigned NumOperands = MI->getDesc().getNumOperands();
1258 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1259 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1260 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1261 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1262 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1264 // Make sure the first operand is on the top of stack, the other one can be
1268 // Change from the pseudo instruction to the concrete instruction.
1269 MI->getOperand(0).setReg(getSTReg(Op1));
1270 MI->RemoveOperand(1);
1271 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1273 // If any of the operands are killed by this instruction, free them.
1274 if (KillsOp0) freeStackSlotAfter(I, Op0);
1275 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1278 /// handleCondMovFP - Handle two address conditional move instructions. These
1279 /// instructions move a st(i) register to st(0) iff a condition is true. These
1280 /// instructions require that the first operand is at the top of the stack, but
1281 /// otherwise don't modify the stack at all.
1282 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1283 MachineInstr *MI = I;
1285 unsigned Op0 = getFPReg(MI->getOperand(0));
1286 unsigned Op1 = getFPReg(MI->getOperand(2));
1287 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1289 // The first operand *must* be on the top of the stack.
1292 // Change the second operand to the stack register that the operand is in.
1293 // Change from the pseudo instruction to the concrete instruction.
1294 MI->RemoveOperand(0);
1295 MI->RemoveOperand(1);
1296 MI->getOperand(0).setReg(getSTReg(Op1));
1297 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1299 // If we kill the second operand, make sure to pop it from the stack.
1300 if (Op0 != Op1 && KillsOp1) {
1301 // Get this value off of the register stack.
1302 freeStackSlotAfter(I, Op1);
1307 /// handleSpecialFP - Handle special instructions which behave unlike other
1308 /// floating point instructions. This is primarily intended for use by pseudo
1311 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
1312 MachineInstr *MI = I;
1313 switch (MI->getOpcode()) {
1314 default: llvm_unreachable("Unknown SpecialFP instruction!");
1315 case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
1316 case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
1317 case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
1318 assert(StackTop == 0 && "Stack should be empty after a call!");
1319 pushReg(getFPReg(MI->getOperand(0)));
1321 case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
1322 case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
1323 case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
1324 // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
1325 // The pattern we expect is:
1330 // At this point, we've pushed FP1 on the top of stack, so it should be
1331 // present if it isn't dead. If it was dead, we already emitted a pop to
1332 // remove it from the stack and StackTop = 0.
1334 // Push FP4 as top of stack next.
1335 pushReg(getFPReg(MI->getOperand(0)));
1337 // If StackTop was 0 before we pushed our operand, then ST(0) must have been
1338 // dead. In this case, the ST(1) value is the only thing that is live, so
1339 // it should be on the TOS (after the pop that was emitted) and is. Just
1340 // continue in this case.
1344 // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
1345 // elements so that our accounting is correct.
1346 unsigned RegOnTop = getStackEntry(0);
1347 unsigned RegNo = getStackEntry(1);
1349 // Swap the slots the regs are in.
1350 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
1352 // Swap stack slot contents.
1353 if (RegMap[RegOnTop] >= StackTop)
1354 report_fatal_error("Access past stack top!");
1355 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
1358 case X86::FpSET_ST0_32:
1359 case X86::FpSET_ST0_64:
1360 case X86::FpSET_ST0_80: {
1361 // FpSET_ST0_80 is generated by copyRegToReg for setting up inline asm
1362 // arguments that use an st constraint. We expect a sequence of
1363 // instructions: Fp_SET_ST0 Fp_SET_ST1? INLINEASM
1364 unsigned Op0 = getFPReg(MI->getOperand(0));
1366 if (!MI->killsRegister(X86::FP0 + Op0)) {
1367 // Duplicate Op0 into a temporary on the stack top.
1368 duplicateToTop(Op0, getScratchReg(), I);
1370 // Op0 is killed, so just swap it into position.
1373 --StackTop; // "Forget" we have something on the top of stack!
1376 case X86::FpSET_ST1_32:
1377 case X86::FpSET_ST1_64:
1378 case X86::FpSET_ST1_80: {
1379 // Set up st(1) for inline asm. We are assuming that st(0) has already been
1380 // set up by FpSET_ST0, and our StackTop is off by one because of it.
1381 unsigned Op0 = getFPReg(MI->getOperand(0));
1382 // Restore the actual StackTop from before Fp_SET_ST0.
1383 // Note we can't handle Fp_SET_ST1 without a preceeding Fp_SET_ST0, and we
1384 // are not enforcing the constraint.
1386 unsigned RegOnTop = getStackEntry(0); // This reg must remain in st(0).
1387 if (!MI->killsRegister(X86::FP0 + Op0)) {
1388 duplicateToTop(Op0, getScratchReg(), I);
1389 moveToTop(RegOnTop, I);
1390 } else if (getSTReg(Op0) != X86::ST1) {
1391 // We have the wrong value at st(1). Shuffle! Untested!
1392 moveToTop(getStackEntry(1), I);
1394 moveToTop(RegOnTop, I);
1396 assert(StackTop >= 2 && "Too few live registers");
1397 StackTop -= 2; // "Forget" both st(0) and st(1).
1400 case X86::MOV_Fp3232:
1401 case X86::MOV_Fp3264:
1402 case X86::MOV_Fp6432:
1403 case X86::MOV_Fp6464:
1404 case X86::MOV_Fp3280:
1405 case X86::MOV_Fp6480:
1406 case X86::MOV_Fp8032:
1407 case X86::MOV_Fp8064:
1408 case X86::MOV_Fp8080: {
1409 const MachineOperand &MO1 = MI->getOperand(1);
1410 unsigned SrcReg = getFPReg(MO1);
1412 const MachineOperand &MO0 = MI->getOperand(0);
1413 unsigned DestReg = getFPReg(MO0);
1414 if (MI->killsRegister(X86::FP0+SrcReg)) {
1415 // If the input operand is killed, we can just change the owner of the
1416 // incoming stack slot into the result.
1417 unsigned Slot = getSlot(SrcReg);
1418 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
1419 Stack[Slot] = DestReg;
1420 RegMap[DestReg] = Slot;
1423 // For FMOV we just duplicate the specified value to a new stack slot.
1424 // This could be made better, but would require substantial changes.
1425 duplicateToTop(SrcReg, DestReg, I);
1429 case TargetOpcode::INLINEASM: {
1430 // The inline asm MachineInstr currently only *uses* FP registers for the
1431 // 'f' constraint. These should be turned into the current ST(x) register
1432 // in the machine instr. Also, any kills should be explicitly popped after
1435 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1436 MachineOperand &Op = MI->getOperand(i);
1437 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1439 assert(Op.isUse() && "Only handle inline asm uses right now");
1441 unsigned FPReg = getFPReg(Op);
1442 Op.setReg(getSTReg(FPReg));
1444 // If we kill this operand, make sure to pop it from the stack after the
1445 // asm. We just remember it for now, and pop them all off at the end in
1448 Kills |= 1U << FPReg;
1451 // If this asm kills any FP registers (is the last use of them) we must
1452 // explicitly emit pop instructions for them. Do this now after the asm has
1453 // executed so that the ST(x) numbers are not off (which would happen if we
1454 // did this inline with operand rewriting).
1456 // Note: this might be a non-optimal pop sequence. We might be able to do
1457 // better by trying to pop in stack order or something.
1458 MachineBasicBlock::iterator InsertPt = MI;
1460 unsigned FPReg = CountTrailingZeros_32(Kills);
1461 freeStackSlotAfter(InsertPt, FPReg);
1462 Kills &= ~(1U << FPReg);
1464 // Don't delete the inline asm!
1470 // If RET has an FP register use operand, pass the first one in ST(0) and
1471 // the second one in ST(1).
1473 // Find the register operands.
1474 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1475 unsigned LiveMask = 0;
1477 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1478 MachineOperand &Op = MI->getOperand(i);
1479 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1481 // FP Register uses must be kills unless there are two uses of the same
1482 // register, in which case only one will be a kill.
1483 assert(Op.isUse() &&
1484 (Op.isKill() || // Marked kill.
1485 getFPReg(Op) == FirstFPRegOp || // Second instance.
1486 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1487 "Ret only defs operands, and values aren't live beyond it");
1489 if (FirstFPRegOp == ~0U)
1490 FirstFPRegOp = getFPReg(Op);
1492 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1493 SecondFPRegOp = getFPReg(Op);
1495 LiveMask |= (1 << getFPReg(Op));
1497 // Remove the operand so that later passes don't see it.
1498 MI->RemoveOperand(i);
1502 // We may have been carrying spurious live-ins, so make sure only the returned
1503 // registers are left live.
1504 adjustLiveRegs(LiveMask, MI);
1505 if (!LiveMask) return; // Quick check to see if any are possible.
1507 // There are only four possibilities here:
1508 // 1) we are returning a single FP value. In this case, it has to be in
1509 // ST(0) already, so just declare success by removing the value from the
1511 if (SecondFPRegOp == ~0U) {
1512 // Assert that the top of stack contains the right FP register.
1513 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1514 "Top of stack not the right register for RET!");
1516 // Ok, everything is good, mark the value as not being on the stack
1517 // anymore so that our assertion about the stack being empty at end of
1518 // block doesn't fire.
1523 // Otherwise, we are returning two values:
1524 // 2) If returning the same value for both, we only have one thing in the FP
1525 // stack. Consider: RET FP1, FP1
1526 if (StackTop == 1) {
1527 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1528 "Stack misconfiguration for RET!");
1530 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1531 // register to hold it.
1532 unsigned NewReg = getScratchReg();
1533 duplicateToTop(FirstFPRegOp, NewReg, MI);
1534 FirstFPRegOp = NewReg;
1537 /// Okay we know we have two different FPx operands now:
1538 assert(StackTop == 2 && "Must have two values live!");
1540 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1541 /// in ST(1). In this case, emit an fxch.
1542 if (getStackEntry(0) == SecondFPRegOp) {
1543 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1544 moveToTop(FirstFPRegOp, MI);
1547 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1548 /// ST(1). Just remove both from our understanding of the stack and return.
1549 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1550 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1555 I = MBB->erase(I); // Remove the pseudo instruction
1557 // We want to leave I pointing to the previous instruction, but what if we
1558 // just erased the first instruction?
1559 if (I == MBB->begin()) {
1560 DEBUG(dbgs() << "Inserting dummy KILL\n");
1561 I = BuildMI(*MBB, I, DebugLoc(), TII->get(TargetOpcode::KILL));
1566 // Translate a COPY instruction to a pseudo-op that handleSpecialFP understands.
1567 bool FPS::translateCopy(MachineInstr *MI) {
1568 unsigned DstReg = MI->getOperand(0).getReg();
1569 unsigned SrcReg = MI->getOperand(1).getReg();
1571 if (DstReg == X86::ST0) {
1572 MI->setDesc(TII->get(X86::FpSET_ST0_80));
1573 MI->RemoveOperand(0);
1576 if (DstReg == X86::ST1) {
1577 MI->setDesc(TII->get(X86::FpSET_ST1_80));
1578 MI->RemoveOperand(0);
1581 if (SrcReg == X86::ST0) {
1582 MI->setDesc(TII->get(X86::FpGET_ST0_80));
1585 if (SrcReg == X86::ST1) {
1586 MI->setDesc(TII->get(X86::FpGET_ST1_80));
1589 if (X86::RFP80RegClass.contains(DstReg, SrcReg)) {
1590 MI->setDesc(TII->get(X86::MOV_Fp8080));