1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/Operator.h"
27 #include "llvm/CodeGen/Analysis.h"
28 #include "llvm/CodeGen/FastISel.h"
29 #include "llvm/CodeGen/FunctionLoweringInfo.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Support/CallSite.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/GetElementPtrTypeIterator.h"
36 #include "llvm/Target/TargetOptions.h"
41 class X86FastISel : public FastISel {
42 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
43 /// make the right decision when generating code for different targets.
44 const X86Subtarget *Subtarget;
46 /// StackPtr - Register used as the stack pointer.
50 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
51 /// floating point ops.
52 /// When SSE is available, use it for f32 operations.
53 /// When SSE2 is available, use it for f64 operations.
58 explicit X86FastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
59 Subtarget = &TM.getSubtarget<X86Subtarget>();
60 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
61 X86ScalarSSEf64 = Subtarget->hasSSE2();
62 X86ScalarSSEf32 = Subtarget->hasSSE1();
65 virtual bool TargetSelectInstruction(const Instruction *I);
67 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
68 /// vreg is being provided by the specified load instruction. If possible,
69 /// try to fold the load as an operand to the instruction, returning true if
71 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
74 #include "X86GenFastISel.inc"
77 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
79 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
81 bool X86FastEmitStore(EVT VT, const Value *Val,
82 const X86AddressMode &AM);
83 bool X86FastEmitStore(EVT VT, unsigned Val,
84 const X86AddressMode &AM);
86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
89 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
90 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
92 bool X86SelectLoad(const Instruction *I);
94 bool X86SelectStore(const Instruction *I);
96 bool X86SelectRet(const Instruction *I);
98 bool X86SelectCmp(const Instruction *I);
100 bool X86SelectZExt(const Instruction *I);
102 bool X86SelectBranch(const Instruction *I);
104 bool X86SelectShift(const Instruction *I);
106 bool X86SelectSelect(const Instruction *I);
108 bool X86SelectTrunc(const Instruction *I);
110 bool X86SelectFPExt(const Instruction *I);
111 bool X86SelectFPTrunc(const Instruction *I);
113 bool X86SelectExtractValue(const Instruction *I);
115 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
116 bool X86SelectCall(const Instruction *I);
118 const X86InstrInfo *getInstrInfo() const {
119 return getTargetMachine()->getInstrInfo();
121 const X86TargetMachine *getTargetMachine() const {
122 return static_cast<const X86TargetMachine *>(&TM);
125 unsigned TargetMaterializeConstant(const Constant *C);
127 unsigned TargetMaterializeAlloca(const AllocaInst *C);
129 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
130 /// computed in an SSE register, not on the X87 floating point stack.
131 bool isScalarFPTypeInSSEReg(EVT VT) const {
132 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
133 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
136 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
139 } // end anonymous namespace.
141 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
142 EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true);
143 if (evt == MVT::Other || !evt.isSimple())
144 // Unhandled type. Halt "fast" selection and bail.
147 VT = evt.getSimpleVT();
148 // For now, require SSE/SSE2 for performing floating-point operations,
149 // since x87 requires additional work.
150 if (VT == MVT::f64 && !X86ScalarSSEf64)
152 if (VT == MVT::f32 && !X86ScalarSSEf32)
154 // Similarly, no f80 support yet.
157 // We only handle legal types. For example, on x86-32 the instruction
158 // selector contains all of the 64-bit instructions from x86-64,
159 // under the assumption that i64 won't be used if the target doesn't
161 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
164 #include "X86GenCallingConv.inc"
166 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
167 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
168 /// Return true and the result register by reference if it is possible.
169 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
170 unsigned &ResultReg) {
171 // Get opcode and regclass of the output for the given load instruction.
173 const TargetRegisterClass *RC = NULL;
174 switch (VT.getSimpleVT().SimpleTy) {
175 default: return false;
179 RC = X86::GR8RegisterClass;
183 RC = X86::GR16RegisterClass;
187 RC = X86::GR32RegisterClass;
190 // Must be in x86-64 mode.
192 RC = X86::GR64RegisterClass;
195 if (Subtarget->hasSSE1()) {
197 RC = X86::FR32RegisterClass;
200 RC = X86::RFP32RegisterClass;
204 if (Subtarget->hasSSE2()) {
206 RC = X86::FR64RegisterClass;
209 RC = X86::RFP64RegisterClass;
213 // No f80 support yet.
217 ResultReg = createResultReg(RC);
218 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
219 DL, TII.get(Opc), ResultReg), AM);
223 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
224 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
225 /// and a displacement offset, or a GlobalAddress,
226 /// i.e. V. Return true if it is possible.
228 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
229 const X86AddressMode &AM) {
230 // Get opcode and regclass of the output for the given store instruction.
232 switch (VT.getSimpleVT().SimpleTy) {
233 case MVT::f80: // No f80 support yet.
234 default: return false;
236 // Mask out all but lowest bit.
237 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
238 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
239 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
242 // FALLTHROUGH, handling i1 as i8.
243 case MVT::i8: Opc = X86::MOV8mr; break;
244 case MVT::i16: Opc = X86::MOV16mr; break;
245 case MVT::i32: Opc = X86::MOV32mr; break;
246 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
248 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
251 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
255 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
256 DL, TII.get(Opc)), AM).addReg(Val);
260 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
261 const X86AddressMode &AM) {
262 // Handle 'null' like i32/i64 0.
263 if (isa<ConstantPointerNull>(Val))
264 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
266 // If this is a store of a simple constant, fold the constant into the store.
267 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
270 switch (VT.getSimpleVT().SimpleTy) {
272 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
273 case MVT::i8: Opc = X86::MOV8mi; break;
274 case MVT::i16: Opc = X86::MOV16mi; break;
275 case MVT::i32: Opc = X86::MOV32mi; break;
277 // Must be a 32-bit sign extended value.
278 if ((int)CI->getSExtValue() == CI->getSExtValue())
279 Opc = X86::MOV64mi32;
284 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
285 DL, TII.get(Opc)), AM)
286 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
292 unsigned ValReg = getRegForValue(Val);
296 return X86FastEmitStore(VT, ValReg, AM);
299 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
300 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
301 /// ISD::SIGN_EXTEND).
302 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
303 unsigned Src, EVT SrcVT,
304 unsigned &ResultReg) {
305 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
306 Src, /*TODO: Kill=*/false);
315 /// X86SelectAddress - Attempt to fill in an address from the given value.
317 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
318 const User *U = NULL;
319 unsigned Opcode = Instruction::UserOp1;
320 if (const Instruction *I = dyn_cast<Instruction>(V)) {
321 // Don't walk into other basic blocks; it's possible we haven't
322 // visited them yet, so the instructions may not yet be assigned
323 // virtual registers.
324 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(V)) ||
325 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
326 Opcode = I->getOpcode();
329 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
330 Opcode = C->getOpcode();
334 if (const PointerType *Ty = dyn_cast<PointerType>(V->getType()))
335 if (Ty->getAddressSpace() > 255)
336 // Fast instruction selection doesn't support the special
342 case Instruction::BitCast:
343 // Look past bitcasts.
344 return X86SelectAddress(U->getOperand(0), AM);
346 case Instruction::IntToPtr:
347 // Look past no-op inttoptrs.
348 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
349 return X86SelectAddress(U->getOperand(0), AM);
352 case Instruction::PtrToInt:
353 // Look past no-op ptrtoints.
354 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
355 return X86SelectAddress(U->getOperand(0), AM);
358 case Instruction::Alloca: {
359 // Do static allocas.
360 const AllocaInst *A = cast<AllocaInst>(V);
361 DenseMap<const AllocaInst*, int>::iterator SI =
362 FuncInfo.StaticAllocaMap.find(A);
363 if (SI != FuncInfo.StaticAllocaMap.end()) {
364 AM.BaseType = X86AddressMode::FrameIndexBase;
365 AM.Base.FrameIndex = SI->second;
371 case Instruction::Add: {
372 // Adds of constants are common and easy enough.
373 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
374 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
375 // They have to fit in the 32-bit signed displacement field though.
376 if (isInt<32>(Disp)) {
377 AM.Disp = (uint32_t)Disp;
378 return X86SelectAddress(U->getOperand(0), AM);
384 case Instruction::GetElementPtr: {
385 X86AddressMode SavedAM = AM;
387 // Pattern-match simple GEPs.
388 uint64_t Disp = (int32_t)AM.Disp;
389 unsigned IndexReg = AM.IndexReg;
390 unsigned Scale = AM.Scale;
391 gep_type_iterator GTI = gep_type_begin(U);
392 // Iterate through the indices, folding what we can. Constants can be
393 // folded, and one dynamic index can be handled, if the scale is supported.
394 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
395 i != e; ++i, ++GTI) {
396 const Value *Op = *i;
397 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
398 const StructLayout *SL = TD.getStructLayout(STy);
399 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue());
403 // A array/variable index is always of the form i*S where S is the
404 // constant scale size. See if we can push the scale into immediates.
405 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
407 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
408 // Constant-offset addressing.
409 Disp += CI->getSExtValue() * S;
412 if (isa<AddOperator>(Op) &&
413 (!isa<Instruction>(Op) ||
414 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
416 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
417 // An add (in the same block) with a constant operand. Fold the
420 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
421 Disp += CI->getSExtValue() * S;
422 // Iterate on the other operand.
423 Op = cast<AddOperator>(Op)->getOperand(0);
427 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
428 (S == 1 || S == 2 || S == 4 || S == 8)) {
429 // Scaled-index addressing.
431 IndexReg = getRegForGEPIndex(Op).first;
437 goto unsupported_gep;
440 // Check for displacement overflow.
441 if (!isInt<32>(Disp))
443 // Ok, the GEP indices were covered by constant-offset and scaled-index
444 // addressing. Update the address state and move on to examining the base.
445 AM.IndexReg = IndexReg;
447 AM.Disp = (uint32_t)Disp;
448 if (X86SelectAddress(U->getOperand(0), AM))
451 // If we couldn't merge the gep value into this addr mode, revert back to
452 // our address and just match the value instead of completely failing.
456 // Ok, the GEP indices weren't all covered.
461 // Handle constant address.
462 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
463 // Can't handle alternate code models or TLS yet.
464 if (TM.getCodeModel() != CodeModel::Small)
467 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
468 if (GVar->isThreadLocal())
471 // RIP-relative addresses can't have additional register operands, so if
472 // we've already folded stuff into the addressing mode, just force the
473 // global value into its own register, which we can use as the basereg.
474 if (!Subtarget->isPICStyleRIPRel() ||
475 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
476 // Okay, we've committed to selecting this global. Set up the address.
479 // Allow the subtarget to classify the global.
480 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
482 // If this reference is relative to the pic base, set it now.
483 if (isGlobalRelativeToPICBase(GVFlags)) {
484 // FIXME: How do we know Base.Reg is free??
485 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
488 // Unless the ABI requires an extra load, return a direct reference to
490 if (!isGlobalStubReference(GVFlags)) {
491 if (Subtarget->isPICStyleRIPRel()) {
492 // Use rip-relative addressing if we can. Above we verified that the
493 // base and index registers are unused.
494 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
495 AM.Base.Reg = X86::RIP;
497 AM.GVOpFlags = GVFlags;
501 // Ok, we need to do a load from a stub. If we've already loaded from
502 // this stub, reuse the loaded pointer, otherwise emit the load now.
503 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
505 if (I != LocalValueMap.end() && I->second != 0) {
508 // Issue load from stub.
510 const TargetRegisterClass *RC = NULL;
511 X86AddressMode StubAM;
512 StubAM.Base.Reg = AM.Base.Reg;
514 StubAM.GVOpFlags = GVFlags;
516 // Prepare for inserting code in the local-value area.
517 SavePoint SaveInsertPt = enterLocalValueArea();
519 if (TLI.getPointerTy() == MVT::i64) {
521 RC = X86::GR64RegisterClass;
523 if (Subtarget->isPICStyleRIPRel())
524 StubAM.Base.Reg = X86::RIP;
527 RC = X86::GR32RegisterClass;
530 LoadReg = createResultReg(RC);
531 MachineInstrBuilder LoadMI =
532 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
533 addFullAddress(LoadMI, StubAM);
535 // Ok, back to normal mode.
536 leaveLocalValueArea(SaveInsertPt);
538 // Prevent loading GV stub multiple times in same MBB.
539 LocalValueMap[V] = LoadReg;
542 // Now construct the final address. Note that the Disp, Scale,
543 // and Index values may already be set here.
544 AM.Base.Reg = LoadReg;
550 // If all else fails, try to materialize the value in a register.
551 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
552 if (AM.Base.Reg == 0) {
553 AM.Base.Reg = getRegForValue(V);
554 return AM.Base.Reg != 0;
556 if (AM.IndexReg == 0) {
557 assert(AM.Scale == 1 && "Scale with no index!");
558 AM.IndexReg = getRegForValue(V);
559 return AM.IndexReg != 0;
566 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
568 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
569 const User *U = NULL;
570 unsigned Opcode = Instruction::UserOp1;
571 if (const Instruction *I = dyn_cast<Instruction>(V)) {
572 Opcode = I->getOpcode();
574 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
575 Opcode = C->getOpcode();
581 case Instruction::BitCast:
582 // Look past bitcasts.
583 return X86SelectCallAddress(U->getOperand(0), AM);
585 case Instruction::IntToPtr:
586 // Look past no-op inttoptrs.
587 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
588 return X86SelectCallAddress(U->getOperand(0), AM);
591 case Instruction::PtrToInt:
592 // Look past no-op ptrtoints.
593 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
594 return X86SelectCallAddress(U->getOperand(0), AM);
598 // Handle constant address.
599 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
600 // Can't handle alternate code models yet.
601 if (TM.getCodeModel() != CodeModel::Small)
604 // RIP-relative addresses can't have additional register operands.
605 if (Subtarget->isPICStyleRIPRel() &&
606 (AM.Base.Reg != 0 || AM.IndexReg != 0))
609 // Can't handle DLLImport.
610 if (GV->hasDLLImportLinkage())
614 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
615 if (GVar->isThreadLocal())
618 // Okay, we've committed to selecting this global. Set up the basic address.
621 // No ABI requires an extra load for anything other than DLLImport, which
622 // we rejected above. Return a direct reference to the global.
623 if (Subtarget->isPICStyleRIPRel()) {
624 // Use rip-relative addressing if we can. Above we verified that the
625 // base and index registers are unused.
626 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
627 AM.Base.Reg = X86::RIP;
628 } else if (Subtarget->isPICStyleStubPIC()) {
629 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
630 } else if (Subtarget->isPICStyleGOT()) {
631 AM.GVOpFlags = X86II::MO_GOTOFF;
637 // If all else fails, try to materialize the value in a register.
638 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
639 if (AM.Base.Reg == 0) {
640 AM.Base.Reg = getRegForValue(V);
641 return AM.Base.Reg != 0;
643 if (AM.IndexReg == 0) {
644 assert(AM.Scale == 1 && "Scale with no index!");
645 AM.IndexReg = getRegForValue(V);
646 return AM.IndexReg != 0;
654 /// X86SelectStore - Select and emit code to implement store instructions.
655 bool X86FastISel::X86SelectStore(const Instruction *I) {
657 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
661 if (!X86SelectAddress(I->getOperand(1), AM))
664 return X86FastEmitStore(VT, I->getOperand(0), AM);
667 /// X86SelectRet - Select and emit code to implement ret instructions.
668 bool X86FastISel::X86SelectRet(const Instruction *I) {
669 const ReturnInst *Ret = cast<ReturnInst>(I);
670 const Function &F = *I->getParent()->getParent();
672 if (!FuncInfo.CanLowerReturn)
675 CallingConv::ID CC = F.getCallingConv();
676 if (CC != CallingConv::C &&
677 CC != CallingConv::Fast &&
678 CC != CallingConv::X86_FastCall)
681 if (Subtarget->isTargetWin64())
684 // Don't handle popping bytes on return for now.
685 if (FuncInfo.MF->getInfo<X86MachineFunctionInfo>()
686 ->getBytesToPopOnReturn() != 0)
689 // fastcc with -tailcallopt is intended to provide a guaranteed
690 // tail call optimization. Fastisel doesn't know how to do that.
691 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
694 // Let SDISel handle vararg functions.
698 if (Ret->getNumOperands() > 0) {
699 SmallVector<ISD::OutputArg, 4> Outs;
700 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
703 // Analyze operands of the call, assigning locations to each operand.
704 SmallVector<CCValAssign, 16> ValLocs;
705 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
706 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
708 const Value *RV = Ret->getOperand(0);
709 unsigned Reg = getRegForValue(RV);
713 // Only handle a single return value for now.
714 if (ValLocs.size() != 1)
717 CCValAssign &VA = ValLocs[0];
719 // Don't bother handling odd stuff for now.
720 if (VA.getLocInfo() != CCValAssign::Full)
722 // Only handle register returns for now.
725 // TODO: For now, don't try to handle cases where getLocInfo()
726 // says Full but the types don't match.
727 if (TLI.getValueType(RV->getType()) != VA.getValVT())
730 // The calling-convention tables for x87 returns don't tell
732 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
736 unsigned SrcReg = Reg + VA.getValNo();
737 unsigned DstReg = VA.getLocReg();
738 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
739 // Avoid a cross-class copy. This is very unlikely.
740 if (!SrcRC->contains(DstReg))
742 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
743 DstReg).addReg(SrcReg);
745 // Mark the register as live out of the function.
746 MRI.addLiveOut(VA.getLocReg());
750 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
754 /// X86SelectLoad - Select and emit code to implement load instructions.
756 bool X86FastISel::X86SelectLoad(const Instruction *I) {
758 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
762 if (!X86SelectAddress(I->getOperand(0), AM))
765 unsigned ResultReg = 0;
766 if (X86FastEmitLoad(VT, AM, ResultReg)) {
767 UpdateValueMap(I, ResultReg);
773 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
774 switch (VT.getSimpleVT().SimpleTy) {
776 case MVT::i8: return X86::CMP8rr;
777 case MVT::i16: return X86::CMP16rr;
778 case MVT::i32: return X86::CMP32rr;
779 case MVT::i64: return X86::CMP64rr;
780 case MVT::f32: return Subtarget->hasSSE1() ? X86::UCOMISSrr : 0;
781 case MVT::f64: return Subtarget->hasSSE2() ? X86::UCOMISDrr : 0;
785 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
786 /// of the comparison, return an opcode that works for the compare (e.g.
787 /// CMP32ri) otherwise return 0.
788 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
789 switch (VT.getSimpleVT().SimpleTy) {
790 // Otherwise, we can't fold the immediate into this comparison.
792 case MVT::i8: return X86::CMP8ri;
793 case MVT::i16: return X86::CMP16ri;
794 case MVT::i32: return X86::CMP32ri;
796 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
798 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
799 return X86::CMP64ri32;
804 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
806 unsigned Op0Reg = getRegForValue(Op0);
807 if (Op0Reg == 0) return false;
809 // Handle 'null' like i32/i64 0.
810 if (isa<ConstantPointerNull>(Op1))
811 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
813 // We have two options: compare with register or immediate. If the RHS of
814 // the compare is an immediate that we can fold into this compare, use
815 // CMPri, otherwise use CMPrr.
816 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
817 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
818 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
820 .addImm(Op1C->getSExtValue());
825 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget);
826 if (CompareOpc == 0) return false;
828 unsigned Op1Reg = getRegForValue(Op1);
829 if (Op1Reg == 0) return false;
830 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
837 bool X86FastISel::X86SelectCmp(const Instruction *I) {
838 const CmpInst *CI = cast<CmpInst>(I);
841 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
844 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
846 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
847 switch (CI->getPredicate()) {
848 case CmpInst::FCMP_OEQ: {
849 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
852 unsigned EReg = createResultReg(&X86::GR8RegClass);
853 unsigned NPReg = createResultReg(&X86::GR8RegClass);
854 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
856 TII.get(X86::SETNPr), NPReg);
857 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
858 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
859 UpdateValueMap(I, ResultReg);
862 case CmpInst::FCMP_UNE: {
863 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
866 unsigned NEReg = createResultReg(&X86::GR8RegClass);
867 unsigned PReg = createResultReg(&X86::GR8RegClass);
868 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg);
869 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg);
870 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg)
871 .addReg(PReg).addReg(NEReg);
872 UpdateValueMap(I, ResultReg);
875 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
876 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
877 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
878 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
879 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
880 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
881 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
882 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
883 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
884 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
885 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
886 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
888 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
889 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
890 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
891 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
892 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
893 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
894 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
895 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
896 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
897 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
902 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
906 // Emit a compare of Op0/Op1.
907 if (!X86FastEmitCompare(Op0, Op1, VT))
910 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
911 UpdateValueMap(I, ResultReg);
915 bool X86FastISel::X86SelectZExt(const Instruction *I) {
916 // Handle zero-extension from i1 to i8, which is common.
917 if (I->getType()->isIntegerTy(8) &&
918 I->getOperand(0)->getType()->isIntegerTy(1)) {
919 unsigned ResultReg = getRegForValue(I->getOperand(0));
920 if (ResultReg == 0) return false;
921 // Set the high bits to zero.
922 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
923 if (ResultReg == 0) return false;
924 UpdateValueMap(I, ResultReg);
932 bool X86FastISel::X86SelectBranch(const Instruction *I) {
933 // Unconditional branches are selected by tablegen-generated code.
934 // Handle a conditional branch.
935 const BranchInst *BI = cast<BranchInst>(I);
936 MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
937 MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
939 // Fold the common case of a conditional branch with a comparison
940 // in the same block (values defined on other blocks may not have
941 // initialized registers).
942 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
943 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
944 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
946 // Try to take advantage of fallthrough opportunities.
947 CmpInst::Predicate Predicate = CI->getPredicate();
948 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
949 std::swap(TrueMBB, FalseMBB);
950 Predicate = CmpInst::getInversePredicate(Predicate);
953 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
954 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
957 case CmpInst::FCMP_OEQ:
958 std::swap(TrueMBB, FalseMBB);
959 Predicate = CmpInst::FCMP_UNE;
961 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
962 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
963 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
964 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
965 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
966 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
967 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
968 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
969 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
970 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
971 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
972 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
973 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
975 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
976 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
977 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
978 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
979 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
980 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
981 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
982 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
983 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
984 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
989 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
993 // Emit a compare of the LHS and RHS, setting the flags.
994 if (!X86FastEmitCompare(Op0, Op1, VT))
997 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
1000 if (Predicate == CmpInst::FCMP_UNE) {
1001 // X86 requires a second branch to handle UNE (and OEQ,
1002 // which is mapped to UNE above).
1003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1007 FastEmitBranch(FalseMBB, DL);
1008 FuncInfo.MBB->addSuccessor(TrueMBB);
1011 } else if (ExtractValueInst *EI =
1012 dyn_cast<ExtractValueInst>(BI->getCondition())) {
1013 // Check to see if the branch instruction is from an "arithmetic with
1014 // overflow" intrinsic. The main way these intrinsics are used is:
1016 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
1017 // %sum = extractvalue { i32, i1 } %t, 0
1018 // %obit = extractvalue { i32, i1 } %t, 1
1019 // br i1 %obit, label %overflow, label %normal
1021 // The %sum and %obit are converted in an ADD and a SETO/SETB before
1022 // reaching the branch. Therefore, we search backwards through the MBB
1023 // looking for the SETO/SETB instruction. If an instruction modifies the
1024 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
1025 // convert the branch into a JO/JB instruction.
1026 if (const IntrinsicInst *CI =
1027 dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
1028 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
1029 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
1030 const MachineInstr *SetMI = 0;
1031 unsigned Reg = getRegForValue(EI);
1033 for (MachineBasicBlock::const_reverse_iterator
1034 RI = FuncInfo.MBB->rbegin(), RE = FuncInfo.MBB->rend();
1036 const MachineInstr &MI = *RI;
1038 if (MI.definesRegister(Reg)) {
1040 Reg = MI.getOperand(1).getReg();
1048 const TargetInstrDesc &TID = MI.getDesc();
1049 if (TID.hasImplicitDefOfPhysReg(X86::EFLAGS) ||
1050 MI.hasUnmodeledSideEffects())
1055 unsigned OpCode = SetMI->getOpcode();
1057 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
1058 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1059 TII.get(OpCode == X86::SETOr ? X86::JO_4 : X86::JB_4))
1061 FastEmitBranch(FalseMBB, DL);
1062 FuncInfo.MBB->addSuccessor(TrueMBB);
1068 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1069 // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which
1070 // typically happen for _Bool and C++ bools.
1072 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1073 isTypeLegal(TI->getOperand(0)->getType(), SourceVT)) {
1074 unsigned TestOpc = 0;
1075 switch (SourceVT.SimpleTy) {
1077 case MVT::i8: TestOpc = X86::TEST8ri; break;
1078 case MVT::i16: TestOpc = X86::TEST16ri; break;
1079 case MVT::i32: TestOpc = X86::TEST32ri; break;
1080 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1083 unsigned OpReg = getRegForValue(TI->getOperand(0));
1084 if (OpReg == 0) return false;
1085 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TestOpc))
1086 .addReg(OpReg).addImm(1);
1087 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1089 FastEmitBranch(FalseMBB, DL);
1090 FuncInfo.MBB->addSuccessor(TrueMBB);
1096 // Otherwise do a clumsy setcc and re-test it.
1097 unsigned OpReg = getRegForValue(BI->getCondition());
1098 if (OpReg == 0) return false;
1100 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1101 .addReg(OpReg).addReg(OpReg);
1102 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1104 FastEmitBranch(FalseMBB, DL);
1105 FuncInfo.MBB->addSuccessor(TrueMBB);
1109 bool X86FastISel::X86SelectShift(const Instruction *I) {
1110 unsigned CReg = 0, OpReg = 0;
1111 const TargetRegisterClass *RC = NULL;
1112 if (I->getType()->isIntegerTy(8)) {
1114 RC = &X86::GR8RegClass;
1115 switch (I->getOpcode()) {
1116 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1117 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1118 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1119 default: return false;
1121 } else if (I->getType()->isIntegerTy(16)) {
1123 RC = &X86::GR16RegClass;
1124 switch (I->getOpcode()) {
1125 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1126 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1127 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1128 default: return false;
1130 } else if (I->getType()->isIntegerTy(32)) {
1132 RC = &X86::GR32RegClass;
1133 switch (I->getOpcode()) {
1134 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1135 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1136 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1137 default: return false;
1139 } else if (I->getType()->isIntegerTy(64)) {
1141 RC = &X86::GR64RegClass;
1142 switch (I->getOpcode()) {
1143 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1144 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1145 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1146 default: return false;
1153 if (!isTypeLegal(I->getType(), VT))
1156 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1157 if (Op0Reg == 0) return false;
1159 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1160 if (Op1Reg == 0) return false;
1161 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1162 CReg).addReg(Op1Reg);
1164 // The shift instruction uses X86::CL. If we defined a super-register
1165 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1166 if (CReg != X86::CL)
1167 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1168 TII.get(TargetOpcode::KILL), X86::CL)
1169 .addReg(CReg, RegState::Kill);
1171 unsigned ResultReg = createResultReg(RC);
1172 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
1174 UpdateValueMap(I, ResultReg);
1178 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1180 if (!isTypeLegal(I->getType(), VT))
1183 // We only use cmov here, if we don't have a cmov instruction bail.
1184 if (!Subtarget->hasCMov()) return false;
1187 const TargetRegisterClass *RC = NULL;
1188 if (VT == MVT::i16) {
1189 Opc = X86::CMOVE16rr;
1190 RC = &X86::GR16RegClass;
1191 } else if (VT == MVT::i32) {
1192 Opc = X86::CMOVE32rr;
1193 RC = &X86::GR32RegClass;
1194 } else if (VT == MVT::i64) {
1195 Opc = X86::CMOVE64rr;
1196 RC = &X86::GR64RegClass;
1201 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1202 if (Op0Reg == 0) return false;
1203 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1204 if (Op1Reg == 0) return false;
1205 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1206 if (Op2Reg == 0) return false;
1208 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1209 .addReg(Op0Reg).addReg(Op0Reg);
1210 unsigned ResultReg = createResultReg(RC);
1211 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1212 .addReg(Op1Reg).addReg(Op2Reg);
1213 UpdateValueMap(I, ResultReg);
1217 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1218 // fpext from float to double.
1219 if (Subtarget->hasSSE2() &&
1220 I->getType()->isDoubleTy()) {
1221 const Value *V = I->getOperand(0);
1222 if (V->getType()->isFloatTy()) {
1223 unsigned OpReg = getRegForValue(V);
1224 if (OpReg == 0) return false;
1225 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1226 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1227 TII.get(X86::CVTSS2SDrr), ResultReg)
1229 UpdateValueMap(I, ResultReg);
1237 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1238 if (Subtarget->hasSSE2()) {
1239 if (I->getType()->isFloatTy()) {
1240 const Value *V = I->getOperand(0);
1241 if (V->getType()->isDoubleTy()) {
1242 unsigned OpReg = getRegForValue(V);
1243 if (OpReg == 0) return false;
1244 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1245 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1246 TII.get(X86::CVTSD2SSrr), ResultReg)
1248 UpdateValueMap(I, ResultReg);
1257 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1258 if (Subtarget->is64Bit())
1259 // All other cases should be handled by the tblgen generated code.
1261 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1262 EVT DstVT = TLI.getValueType(I->getType());
1264 // This code only handles truncation to byte right now.
1265 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1266 // All other cases should be handled by the tblgen generated code.
1268 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1269 // All other cases should be handled by the tblgen generated code.
1272 unsigned InputReg = getRegForValue(I->getOperand(0));
1274 // Unhandled operand. Halt "fast" selection and bail.
1277 // First issue a copy to GR16_ABCD or GR32_ABCD.
1278 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1279 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1280 unsigned CopyReg = createResultReg(CopyRC);
1281 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1282 CopyReg).addReg(InputReg);
1284 // Then issue an extract_subreg.
1285 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1286 CopyReg, /*Kill=*/true,
1291 UpdateValueMap(I, ResultReg);
1295 bool X86FastISel::X86SelectExtractValue(const Instruction *I) {
1296 const ExtractValueInst *EI = cast<ExtractValueInst>(I);
1297 const Value *Agg = EI->getAggregateOperand();
1299 if (const IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1300 switch (CI->getIntrinsicID()) {
1302 case Intrinsic::sadd_with_overflow:
1303 case Intrinsic::uadd_with_overflow: {
1304 // Cheat a little. We know that the registers for "add" and "seto" are
1305 // allocated sequentially. However, we only keep track of the register
1306 // for "add" in the value map. Use extractvalue's index to get the
1307 // correct register for "seto".
1308 unsigned OpReg = getRegForValue(Agg);
1311 UpdateValueMap(I, OpReg + *EI->idx_begin());
1320 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1321 // FIXME: Handle more intrinsics.
1322 switch (I.getIntrinsicID()) {
1323 default: return false;
1324 case Intrinsic::stackprotector: {
1325 // Emit code inline code to store the stack guard onto the stack.
1326 EVT PtrTy = TLI.getPointerTy();
1328 const Value *Op1 = I.getArgOperand(0); // The guard's value.
1329 const AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
1331 // Grab the frame index.
1333 if (!X86SelectAddress(Slot, AM)) return false;
1335 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1339 case Intrinsic::objectsize: {
1340 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
1341 const Type *Ty = I.getCalledFunction()->getReturnType();
1343 assert(CI && "Non-constant type in Intrinsic::objectsize?");
1346 if (!isTypeLegal(Ty, VT))
1352 else if (VT == MVT::i64)
1357 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1358 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg).
1359 addImm(CI->isZero() ? -1ULL : 0);
1360 UpdateValueMap(&I, ResultReg);
1363 case Intrinsic::dbg_declare: {
1364 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1366 assert(DI->getAddress() && "Null address should be checked earlier!");
1367 if (!X86SelectAddress(DI->getAddress(), AM))
1369 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1370 // FIXME may need to add RegState::Debug to any registers produced,
1371 // although ESP/EBP should be the only ones at the moment.
1372 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
1373 addImm(0).addMetadata(DI->getVariable());
1376 case Intrinsic::trap: {
1377 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1380 case Intrinsic::sadd_with_overflow:
1381 case Intrinsic::uadd_with_overflow: {
1382 // Replace "add with overflow" intrinsics with an "add" instruction followed
1383 // by a seto/setc instruction. Later on, when the "extractvalue"
1384 // instructions are encountered, we use the fact that two registers were
1385 // created sequentially to get the correct registers for the "sum" and the
1387 const Function *Callee = I.getCalledFunction();
1389 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1392 if (!isTypeLegal(RetTy, VT))
1395 const Value *Op1 = I.getArgOperand(0);
1396 const Value *Op2 = I.getArgOperand(1);
1397 unsigned Reg1 = getRegForValue(Op1);
1398 unsigned Reg2 = getRegForValue(Op2);
1400 if (Reg1 == 0 || Reg2 == 0)
1401 // FIXME: Handle values *not* in registers.
1407 else if (VT == MVT::i64)
1412 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1413 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
1414 .addReg(Reg1).addReg(Reg2);
1415 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1417 // If the add with overflow is an intra-block value then we just want to
1418 // create temporaries for it like normal. If it is a cross-block value then
1419 // UpdateValueMap will return the cross-block register used. Since we
1420 // *really* want the value to be live in the register pair known by
1421 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1422 // the cross block case. In the non-cross-block case, we should just make
1423 // another register for the value.
1424 if (DestReg1 != ResultReg)
1425 ResultReg = DestReg1+1;
1427 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1429 unsigned Opc = X86::SETBr;
1430 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1432 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
1438 bool X86FastISel::X86SelectCall(const Instruction *I) {
1439 const CallInst *CI = cast<CallInst>(I);
1440 const Value *Callee = CI->getCalledValue();
1442 // Can't handle inline asm yet.
1443 if (isa<InlineAsm>(Callee))
1446 // Handle intrinsic calls.
1447 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1448 return X86VisitIntrinsicCall(*II);
1450 // Handle only C and fastcc calling conventions for now.
1451 ImmutableCallSite CS(CI);
1452 CallingConv::ID CC = CS.getCallingConv();
1453 if (CC != CallingConv::C &&
1454 CC != CallingConv::Fast &&
1455 CC != CallingConv::X86_FastCall)
1458 // fastcc with -tailcallopt is intended to provide a guaranteed
1459 // tail call optimization. Fastisel doesn't know how to do that.
1460 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1463 // Let SDISel handle vararg functions.
1464 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1465 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1466 if (FTy->isVarArg())
1469 // Fast-isel doesn't know about callee-pop yet.
1470 if (Subtarget->IsCalleePop(FTy->isVarArg(), CC))
1473 // Handle *simple* calls for now.
1474 const Type *RetTy = CS.getType();
1476 if (RetTy->isVoidTy())
1477 RetVT = MVT::isVoid;
1478 else if (!isTypeLegal(RetTy, RetVT, true))
1481 // Materialize callee address in a register. FIXME: GV address can be
1482 // handled with a CALLpcrel32 instead.
1483 X86AddressMode CalleeAM;
1484 if (!X86SelectCallAddress(Callee, CalleeAM))
1486 unsigned CalleeOp = 0;
1487 const GlobalValue *GV = 0;
1488 if (CalleeAM.GV != 0) {
1490 } else if (CalleeAM.Base.Reg != 0) {
1491 CalleeOp = CalleeAM.Base.Reg;
1495 // Allow calls which produce i1 results.
1496 bool AndToI1 = false;
1497 if (RetVT == MVT::i1) {
1502 // Deal with call operands first.
1503 SmallVector<const Value *, 8> ArgVals;
1504 SmallVector<unsigned, 8> Args;
1505 SmallVector<MVT, 8> ArgVTs;
1506 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1507 Args.reserve(CS.arg_size());
1508 ArgVals.reserve(CS.arg_size());
1509 ArgVTs.reserve(CS.arg_size());
1510 ArgFlags.reserve(CS.arg_size());
1511 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1513 unsigned Arg = getRegForValue(*i);
1516 ISD::ArgFlagsTy Flags;
1517 unsigned AttrInd = i - CS.arg_begin() + 1;
1518 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1520 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1523 // FIXME: Only handle *easy* calls for now.
1524 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1525 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1526 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1527 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1530 const Type *ArgTy = (*i)->getType();
1532 if (!isTypeLegal(ArgTy, ArgVT))
1534 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1535 Flags.setOrigAlign(OriginalAlignment);
1537 Args.push_back(Arg);
1538 ArgVals.push_back(*i);
1539 ArgVTs.push_back(ArgVT);
1540 ArgFlags.push_back(Flags);
1543 // Analyze operands of the call, assigning locations to each operand.
1544 SmallVector<CCValAssign, 16> ArgLocs;
1545 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
1547 // Allocate shadow area for Win64
1548 if (Subtarget->isTargetWin64()) {
1549 CCInfo.AllocateStack(32, 8);
1552 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_X86);
1554 // Get a count of how many bytes are to be pushed on the stack.
1555 unsigned NumBytes = CCInfo.getNextStackOffset();
1557 // Issue CALLSEQ_START
1558 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1559 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1562 // Process argument: walk the register/memloc assignments, inserting
1564 SmallVector<unsigned, 4> RegArgs;
1565 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1566 CCValAssign &VA = ArgLocs[i];
1567 unsigned Arg = Args[VA.getValNo()];
1568 EVT ArgVT = ArgVTs[VA.getValNo()];
1570 // Promote the value if needed.
1571 switch (VA.getLocInfo()) {
1572 default: llvm_unreachable("Unknown loc info!");
1573 case CCValAssign::Full: break;
1574 case CCValAssign::SExt: {
1575 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1577 assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
1578 ArgVT = VA.getLocVT();
1581 case CCValAssign::ZExt: {
1582 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1584 assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
1585 ArgVT = VA.getLocVT();
1588 case CCValAssign::AExt: {
1589 // We don't handle MMX parameters yet.
1590 if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() == 128)
1592 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1595 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1598 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1601 assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
1602 ArgVT = VA.getLocVT();
1605 case CCValAssign::BCvt: {
1606 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(),
1607 ISD::BITCAST, Arg, /*TODO: Kill=*/false);
1608 assert(BC != 0 && "Failed to emit a bitcast!");
1610 ArgVT = VA.getLocVT();
1615 if (VA.isRegLoc()) {
1616 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1617 VA.getLocReg()).addReg(Arg);
1618 RegArgs.push_back(VA.getLocReg());
1620 unsigned LocMemOffset = VA.getLocMemOffset();
1622 AM.Base.Reg = StackPtr;
1623 AM.Disp = LocMemOffset;
1624 const Value *ArgVal = ArgVals[VA.getValNo()];
1626 // If this is a really simple value, emit this with the Value* version of
1627 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1628 // can cause us to reevaluate the argument.
1629 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1630 X86FastEmitStore(ArgVT, ArgVal, AM);
1632 X86FastEmitStore(ArgVT, Arg, AM);
1636 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1638 if (Subtarget->isPICStyleGOT()) {
1639 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1640 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1641 X86::EBX).addReg(Base);
1645 MachineInstrBuilder MIB;
1647 // Register-indirect call.
1649 if (Subtarget->isTargetWin64())
1650 CallOpc = X86::WINCALL64r;
1651 else if (Subtarget->is64Bit())
1652 CallOpc = X86::CALL64r;
1654 CallOpc = X86::CALL32r;
1655 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1660 assert(GV && "Not a direct call");
1662 if (Subtarget->isTargetWin64())
1663 CallOpc = X86::WINCALL64pcrel32;
1664 else if (Subtarget->is64Bit())
1665 CallOpc = X86::CALL64pcrel32;
1667 CallOpc = X86::CALLpcrel32;
1669 // See if we need any target-specific flags on the GV operand.
1670 unsigned char OpFlags = 0;
1672 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1673 // external symbols most go through the PLT in PIC mode. If the symbol
1674 // has hidden or protected visibility, or if it is static or local, then
1675 // we don't need to use the PLT - we can directly call it.
1676 if (Subtarget->isTargetELF() &&
1677 TM.getRelocationModel() == Reloc::PIC_ &&
1678 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1679 OpFlags = X86II::MO_PLT;
1680 } else if (Subtarget->isPICStyleStubAny() &&
1681 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1682 Subtarget->getDarwinVers() < 9) {
1683 // PC-relative references to external symbols should go through $stub,
1684 // unless we're building with the leopard linker or later, which
1685 // automatically synthesizes these stubs.
1686 OpFlags = X86II::MO_DARWIN_STUB;
1690 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1691 .addGlobalAddress(GV, 0, OpFlags);
1694 // Add an implicit use GOT pointer in EBX.
1695 if (Subtarget->isPICStyleGOT())
1696 MIB.addReg(X86::EBX);
1698 // Add implicit physical register uses to the call.
1699 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1700 MIB.addReg(RegArgs[i]);
1702 // Issue CALLSEQ_END
1703 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1704 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1705 .addImm(NumBytes).addImm(0);
1707 // Now handle call return value (if any).
1708 SmallVector<unsigned, 4> UsedRegs;
1709 if (RetVT != MVT::isVoid) {
1710 SmallVector<CCValAssign, 16> RVLocs;
1711 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1712 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1714 // Copy all of the result registers out of their specified physreg.
1715 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1716 EVT CopyVT = RVLocs[0].getValVT();
1717 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1719 // If this is a call to a function that returns an fp value on the x87 fp
1720 // stack, but where we prefer to use the value in xmm registers, copy it
1721 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1722 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1723 RVLocs[0].getLocReg() == X86::ST1) &&
1724 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1726 DstRC = X86::RFP80RegisterClass;
1729 unsigned ResultReg = createResultReg(DstRC);
1730 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1731 ResultReg).addReg(RVLocs[0].getLocReg());
1732 UsedRegs.push_back(RVLocs[0].getLocReg());
1734 if (CopyVT != RVLocs[0].getValVT()) {
1735 // Round the F80 the right size, which also moves to the appropriate xmm
1736 // register. This is accomplished by storing the F80 value in memory and
1737 // then loading it back. Ewww...
1738 EVT ResVT = RVLocs[0].getValVT();
1739 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1740 unsigned MemSize = ResVT.getSizeInBits()/8;
1741 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1742 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1745 DstRC = ResVT == MVT::f32
1746 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1747 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1748 ResultReg = createResultReg(DstRC);
1749 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1750 TII.get(Opc), ResultReg), FI);
1754 // Mask out all but lowest bit for some call which produces an i1.
1755 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1756 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1757 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1758 ResultReg = AndResult;
1761 UpdateValueMap(I, ResultReg);
1764 // Set all unused physreg defs as dead.
1765 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1772 X86FastISel::TargetSelectInstruction(const Instruction *I) {
1773 switch (I->getOpcode()) {
1775 case Instruction::Load:
1776 return X86SelectLoad(I);
1777 case Instruction::Store:
1778 return X86SelectStore(I);
1779 case Instruction::Ret:
1780 return X86SelectRet(I);
1781 case Instruction::ICmp:
1782 case Instruction::FCmp:
1783 return X86SelectCmp(I);
1784 case Instruction::ZExt:
1785 return X86SelectZExt(I);
1786 case Instruction::Br:
1787 return X86SelectBranch(I);
1788 case Instruction::Call:
1789 return X86SelectCall(I);
1790 case Instruction::LShr:
1791 case Instruction::AShr:
1792 case Instruction::Shl:
1793 return X86SelectShift(I);
1794 case Instruction::Select:
1795 return X86SelectSelect(I);
1796 case Instruction::Trunc:
1797 return X86SelectTrunc(I);
1798 case Instruction::FPExt:
1799 return X86SelectFPExt(I);
1800 case Instruction::FPTrunc:
1801 return X86SelectFPTrunc(I);
1802 case Instruction::ExtractValue:
1803 return X86SelectExtractValue(I);
1804 case Instruction::IntToPtr: // Deliberate fall-through.
1805 case Instruction::PtrToInt: {
1806 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1807 EVT DstVT = TLI.getValueType(I->getType());
1808 if (DstVT.bitsGT(SrcVT))
1809 return X86SelectZExt(I);
1810 if (DstVT.bitsLT(SrcVT))
1811 return X86SelectTrunc(I);
1812 unsigned Reg = getRegForValue(I->getOperand(0));
1813 if (Reg == 0) return false;
1814 UpdateValueMap(I, Reg);
1822 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
1824 if (!isTypeLegal(C->getType(), VT))
1827 // Get opcode and regclass of the output for the given load instruction.
1829 const TargetRegisterClass *RC = NULL;
1830 switch (VT.SimpleTy) {
1831 default: return false;
1834 RC = X86::GR8RegisterClass;
1838 RC = X86::GR16RegisterClass;
1842 RC = X86::GR32RegisterClass;
1845 // Must be in x86-64 mode.
1847 RC = X86::GR64RegisterClass;
1850 if (Subtarget->hasSSE1()) {
1852 RC = X86::FR32RegisterClass;
1854 Opc = X86::LD_Fp32m;
1855 RC = X86::RFP32RegisterClass;
1859 if (Subtarget->hasSSE2()) {
1861 RC = X86::FR64RegisterClass;
1863 Opc = X86::LD_Fp64m;
1864 RC = X86::RFP64RegisterClass;
1868 // No f80 support yet.
1872 // Materialize addresses with LEA instructions.
1873 if (isa<GlobalValue>(C)) {
1875 if (X86SelectAddress(C, AM)) {
1876 // If the expression is just a basereg, then we're done, otherwise we need
1878 if (AM.BaseType == X86AddressMode::RegBase &&
1879 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0)
1882 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
1883 unsigned ResultReg = createResultReg(RC);
1884 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1885 TII.get(Opc), ResultReg), AM);
1891 // MachineConstantPool wants an explicit alignment.
1892 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1894 // Alignment of vector types. FIXME!
1895 Align = TD.getTypeAllocSize(C->getType());
1898 // x86-32 PIC requires a PIC base register for constant pools.
1899 unsigned PICBase = 0;
1900 unsigned char OpFlag = 0;
1901 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
1902 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1903 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1904 } else if (Subtarget->isPICStyleGOT()) {
1905 OpFlag = X86II::MO_GOTOFF;
1906 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1907 } else if (Subtarget->isPICStyleRIPRel() &&
1908 TM.getCodeModel() == CodeModel::Small) {
1912 // Create the load from the constant pool.
1913 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1914 unsigned ResultReg = createResultReg(RC);
1915 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1916 TII.get(Opc), ResultReg),
1917 MCPOffset, PICBase, OpFlag);
1922 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
1923 // Fail on dynamic allocas. At this point, getRegForValue has already
1924 // checked its CSE maps, so if we're here trying to handle a dynamic
1925 // alloca, we're not going to succeed. X86SelectAddress has a
1926 // check for dynamic allocas, because it's called directly from
1927 // various places, but TargetMaterializeAlloca also needs a check
1928 // in order to avoid recursion between getRegForValue,
1929 // X86SelectAddrss, and TargetMaterializeAlloca.
1930 if (!FuncInfo.StaticAllocaMap.count(C))
1934 if (!X86SelectAddress(C, AM))
1936 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1937 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1938 unsigned ResultReg = createResultReg(RC);
1939 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1940 TII.get(Opc), ResultReg), AM);
1944 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
1945 /// vreg is being provided by the specified load instruction. If possible,
1946 /// try to fold the load as an operand to the instruction, returning true if
1948 bool X86FastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
1949 const LoadInst *LI) {
1951 if (!X86SelectAddress(LI->getOperand(0), AM))
1954 X86InstrInfo &XII = (X86InstrInfo&)TII;
1956 unsigned Size = TD.getTypeAllocSize(LI->getType());
1957 unsigned Alignment = LI->getAlignment();
1959 SmallVector<MachineOperand, 8> AddrOps;
1960 AM.getFullAddress(AddrOps);
1962 MachineInstr *Result =
1963 XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment);
1964 if (Result == 0) return false;
1966 FuncInfo.MBB->insert(FuncInfo.InsertPt, Result);
1967 MI->eraseFromParent();
1973 llvm::FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) {
1974 return new X86FastISel(funcInfo);