1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/Function.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Target/TargetOptions.h"
35 // FIXME: This should be some header
36 static const int X86AddrNumOperands = 4;
38 STATISTIC(NumEmitted, "Number of machine instructions emitted");
41 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
42 const X86InstrInfo *II;
45 MachineCodeEmitter &MCE;
46 intptr_t PICBaseOffset;
51 explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
52 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
53 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
54 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
55 Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
56 const X86InstrInfo &ii, const TargetData &td, bool is64)
57 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
58 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
59 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
61 bool runOnMachineFunction(MachineFunction &MF);
63 virtual const char *getPassName() const {
64 return "X86 Machine Code Emitter";
67 void emitInstruction(const MachineInstr &MI,
68 const TargetInstrDesc *Desc);
70 void getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<MachineModuleInfo>();
72 MachineFunctionPass::getAnalysisUsage(AU);
76 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
77 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
78 intptr_t Disp = 0, intptr_t PCAdj = 0,
79 bool NeedStub = false, bool Indirect = false);
80 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
81 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
83 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
86 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
89 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
90 void emitRegModRMByte(unsigned RegOpcodeField);
91 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
92 void emitConstant(uint64_t Val, unsigned Size);
94 void emitMemModRMByte(const MachineInstr &MI,
95 unsigned Op, unsigned RegOpcodeField,
98 unsigned getX86RegNum(unsigned RegNo) const;
100 bool gvNeedsNonLazyPtr(const GlobalValue *GV);
102 char Emitter::ID = 0;
105 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
106 /// to the specified MCE object.
107 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
108 MachineCodeEmitter &MCE) {
109 return new Emitter(TM, MCE);
112 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
114 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
116 II = TM.getInstrInfo();
117 TD = TM.getTargetData();
118 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
119 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
122 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
123 MCE.startFunction(MF);
124 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
126 MCE.StartMachineBasicBlock(MBB);
127 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
129 const TargetInstrDesc &Desc = I->getDesc();
130 emitInstruction(*I, &Desc);
131 // MOVPC32r is basically a call plus a pop instruction.
132 if (Desc.getOpcode() == X86::MOVPC32r)
133 emitInstruction(*I, &II->get(X86::POP32r));
134 NumEmitted++; // Keep track of the # of mi's emitted
137 } while (MCE.finishFunction(MF));
142 /// emitPCRelativeBlockAddress - This method keeps track of the information
143 /// necessary to resolve the address of this block later and emits a dummy
146 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
147 // Remember where this reference was and where it is to so we can
148 // deal with it later.
149 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
150 X86::reloc_pcrel_word, MBB));
154 /// emitGlobalAddress - Emit the specified address to the code stream assuming
155 /// this is part of a "take the address of a global" instruction.
157 void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
158 intptr_t Disp /* = 0 */,
159 intptr_t PCAdj /* = 0 */,
160 bool NeedStub /* = false */,
161 bool Indirect /* = false */) {
162 intptr_t RelocCST = 0;
163 if (Reloc == X86::reloc_picrel_word)
164 RelocCST = PICBaseOffset;
165 else if (Reloc == X86::reloc_pcrel_word)
167 MachineRelocation MR = Indirect
168 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
169 GV, RelocCST, NeedStub)
170 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
171 GV, RelocCST, NeedStub);
172 MCE.addRelocation(MR);
173 // The relocated value will be added to the displacement
174 if (Reloc == X86::reloc_absolute_dword)
175 MCE.emitDWordLE(Disp);
177 MCE.emitWordLE((int32_t)Disp);
180 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
181 /// be emitted to the current location in the function, and allow it to be PC
183 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
184 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
185 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
186 Reloc, ES, RelocCST));
187 if (Reloc == X86::reloc_absolute_dword)
193 /// emitConstPoolAddress - Arrange for the address of an constant pool
194 /// to be emitted to the current location in the function, and allow it to be PC
196 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
197 intptr_t Disp /* = 0 */,
198 intptr_t PCAdj /* = 0 */) {
199 intptr_t RelocCST = 0;
200 if (Reloc == X86::reloc_picrel_word)
201 RelocCST = PICBaseOffset;
202 else if (Reloc == X86::reloc_pcrel_word)
204 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
205 Reloc, CPI, RelocCST));
206 // The relocated value will be added to the displacement
207 if (Reloc == X86::reloc_absolute_dword)
208 MCE.emitDWordLE(Disp);
210 MCE.emitWordLE((int32_t)Disp);
213 /// emitJumpTableAddress - Arrange for the address of a jump table to
214 /// be emitted to the current location in the function, and allow it to be PC
216 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
217 intptr_t PCAdj /* = 0 */) {
218 intptr_t RelocCST = 0;
219 if (Reloc == X86::reloc_picrel_word)
220 RelocCST = PICBaseOffset;
221 else if (Reloc == X86::reloc_pcrel_word)
223 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
224 Reloc, JTI, RelocCST));
225 // The relocated value will be added to the displacement
226 if (Reloc == X86::reloc_absolute_dword)
232 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
233 return II->getRegisterInfo().getX86RegNum(RegNo);
236 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
238 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
239 return RM | (RegOpcode << 3) | (Mod << 6);
242 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
243 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
246 void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) {
247 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
250 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
251 // SIB byte is in the same format as the ModRMByte...
252 MCE.emitByte(ModRMByte(SS, Index, Base));
255 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
256 // Output the constant in little endian byte order...
257 for (unsigned i = 0; i != Size; ++i) {
258 MCE.emitByte(Val & 255);
263 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
264 /// sign-extended field.
265 static bool isDisp8(int Value) {
266 return Value == (signed char)Value;
269 bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) {
270 // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer
271 // mechanism as 32-bit mode.
272 return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
273 TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
276 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
277 int DispVal, intptr_t PCAdj) {
278 // If this is a simple integer displacement that doesn't require a relocation,
281 emitConstant(DispVal, 4);
285 // Otherwise, this is something that requires a relocation. Emit it as such
287 if (RelocOp->isGlobal()) {
288 // In 64-bit static small code model, we could potentially emit absolute.
289 // But it's probably not beneficial.
290 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
291 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
292 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
293 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
294 bool NeedStub = isa<Function>(RelocOp->getGlobal());
295 bool Indirect = gvNeedsNonLazyPtr(RelocOp->getGlobal());
296 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
297 PCAdj, NeedStub, Indirect);
298 } else if (RelocOp->isCPI()) {
299 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
300 emitConstPoolAddress(RelocOp->getIndex(), rt,
301 RelocOp->getOffset(), PCAdj);
302 } else if (RelocOp->isJTI()) {
303 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
304 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
306 assert(0 && "Unknown value to relocate!");
310 void Emitter::emitMemModRMByte(const MachineInstr &MI,
311 unsigned Op, unsigned RegOpcodeField,
313 const MachineOperand &Op3 = MI.getOperand(Op+3);
315 const MachineOperand *DispForReloc = 0;
317 // Figure out what sort of displacement we have to handle here.
318 if (Op3.isGlobal()) {
320 } else if (Op3.isCPI()) {
321 if (Is64BitMode || IsPIC) {
324 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
325 DispVal += Op3.getOffset();
327 } else if (Op3.isJTI()) {
328 if (Is64BitMode || IsPIC) {
331 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
334 DispVal = Op3.getImm();
337 const MachineOperand &Base = MI.getOperand(Op);
338 const MachineOperand &Scale = MI.getOperand(Op+1);
339 const MachineOperand &IndexReg = MI.getOperand(Op+2);
341 unsigned BaseReg = Base.getReg();
343 // Is a SIB byte needed?
344 if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
345 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
346 if (BaseReg == 0) { // Just a displacement?
347 // Emit special case [disp32] encoding
348 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
350 emitDisplacementField(DispForReloc, DispVal, PCAdj);
352 unsigned BaseRegNo = getX86RegNum(BaseReg);
353 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
354 // Emit simple indirect register encoding... [EAX] f.e.
355 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
356 } else if (!DispForReloc && isDisp8(DispVal)) {
357 // Emit the disp8 encoding... [REG+disp8]
358 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
359 emitConstant(DispVal, 1);
361 // Emit the most general non-SIB encoding: [REG+disp32]
362 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
363 emitDisplacementField(DispForReloc, DispVal, PCAdj);
367 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
368 assert(IndexReg.getReg() != X86::ESP &&
369 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
371 bool ForceDisp32 = false;
372 bool ForceDisp8 = false;
374 // If there is no base register, we emit the special case SIB byte with
375 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
376 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
378 } else if (DispForReloc) {
379 // Emit the normal disp32 encoding.
380 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
382 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
383 // Emit no displacement ModR/M byte
384 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
385 } else if (isDisp8(DispVal)) {
386 // Emit the disp8 encoding...
387 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
388 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
390 // Emit the normal disp32 encoding...
391 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
394 // Calculate what the SS field value should be...
395 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
396 unsigned SS = SSTable[Scale.getImm()];
399 // Handle the SIB byte for the case where there is no base. The
400 // displacement has already been output.
402 if (IndexReg.getReg())
403 IndexRegNo = getX86RegNum(IndexReg.getReg());
405 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
406 emitSIBByte(SS, IndexRegNo, 5);
408 unsigned BaseRegNo = getX86RegNum(BaseReg);
410 if (IndexReg.getReg())
411 IndexRegNo = getX86RegNum(IndexReg.getReg());
413 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
414 emitSIBByte(SS, IndexRegNo, BaseRegNo);
417 // Do we need to output a displacement?
419 emitConstant(DispVal, 1);
420 } else if (DispVal != 0 || ForceDisp32) {
421 emitDisplacementField(DispForReloc, DispVal, PCAdj);
426 void Emitter::emitInstruction(const MachineInstr &MI,
427 const TargetInstrDesc *Desc) {
430 unsigned Opcode = Desc->Opcode;
432 // Emit the lock opcode prefix as needed.
433 if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
435 // Emit segment override opcode prefix as needed.
436 switch (Desc->TSFlags & X86II::SegOvrMask) {
443 default: assert(0 && "Invalid segment!");
444 case 0: break; // No segment override!
447 // Emit the repeat opcode prefix as needed.
448 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
450 // Emit the operand size opcode prefix as needed.
451 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
453 // Emit the address size opcode prefix as needed.
454 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
456 bool Need0FPrefix = false;
457 switch (Desc->TSFlags & X86II::Op0Mask) {
458 case X86II::TB: // Two-byte opcode prefix
459 case X86II::T8: // 0F 38
460 case X86II::TA: // 0F 3A
463 case X86II::REP: break; // already handled.
464 case X86II::XS: // F3 0F
468 case X86II::XD: // F2 0F
472 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
473 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
475 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
476 >> X86II::Op0Shift));
477 break; // Two-byte opcode prefix
478 default: assert(0 && "Invalid prefix!");
479 case 0: break; // No prefix!
484 unsigned REX = X86InstrInfo::determineREX(MI);
486 MCE.emitByte(0x40 | REX);
489 // 0x0F escape code must be emitted just before the opcode.
493 switch (Desc->TSFlags & X86II::Op0Mask) {
494 case X86II::T8: // 0F 38
497 case X86II::TA: // 0F 3A
502 // If this is a two-address instruction, skip one of the register operands.
503 unsigned NumOps = Desc->getNumOperands();
505 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
507 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
508 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
511 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
512 switch (Desc->TSFlags & X86II::FormMask) {
513 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
515 // Remember the current PC offset, this is the PIC relocation
519 assert(0 && "psuedo instructions should be removed before code emission");
521 case TargetInstrInfo::INLINEASM: {
522 // We allow inline assembler nodes with empty bodies - they can
523 // implicitly define registers, which is ok for JIT.
524 if (MI.getOperand(0).getSymbolName()[0]) {
525 assert(0 && "JIT does not support inline asm!\n");
530 case TargetInstrInfo::DBG_LABEL:
531 case TargetInstrInfo::EH_LABEL:
532 MCE.emitLabel(MI.getOperand(0).getImm());
534 case TargetInstrInfo::IMPLICIT_DEF:
535 case TargetInstrInfo::DECLARE:
537 case X86::FP_REG_KILL:
540 MCE.emitByte(BaseOpcode);
541 unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
542 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
546 case X86::TLS_gs_ri: {
547 MCE.emitByte(BaseOpcode);
548 unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
549 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
550 GlobalValue* GV = MI.getOperand(1).getGlobal();
551 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
552 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
553 emitGlobalAddress(GV, rt);
556 case X86::MOVPC32r: {
557 // This emits the "call" portion of this pseudo instruction.
558 MCE.emitByte(BaseOpcode);
559 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
560 // Remember PIC base.
561 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
562 X86JITInfo *JTI = TM.getJITInfo();
563 JTI->setPICBase(MCE.getCurrentPCValue());
570 MCE.emitByte(BaseOpcode);
572 if (CurOp != NumOps) {
573 const MachineOperand &MO = MI.getOperand(CurOp++);
575 DOUT << "RawFrm CurOp " << CurOp << "\n";
576 DOUT << "isMBB " << MO.isMBB() << "\n";
577 DOUT << "isGlobal " << MO.isGlobal() << "\n";
578 DOUT << "isSymbol " << MO.isSymbol() << "\n";
579 DOUT << "isImm " << MO.isImm() << "\n";
582 emitPCRelativeBlockAddress(MO.getMBB());
583 } else if (MO.isGlobal()) {
584 // Assume undefined functions may be outside the Small codespace.
587 (TM.getCodeModel() == CodeModel::Large ||
588 TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
589 Opcode == X86::TAILJMPd;
590 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
591 MO.getOffset(), 0, NeedStub);
592 } else if (MO.isSymbol()) {
593 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
594 } else if (MO.isImm()) {
595 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
596 // Fix up immediate operand for pc relative calls.
597 intptr_t Imm = (intptr_t)MO.getImm();
598 Imm = Imm - MCE.getCurrentPCValue() - 4;
599 emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
601 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
603 assert(0 && "Unknown RawFrm operand!");
608 case X86II::AddRegFrm:
609 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
611 if (CurOp != NumOps) {
612 const MachineOperand &MO1 = MI.getOperand(CurOp++);
613 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
615 emitConstant(MO1.getImm(), Size);
617 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
618 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
619 // This should not occur on Darwin for relocatable objects.
620 if (Opcode == X86::MOV64ri)
621 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
622 if (MO1.isGlobal()) {
623 bool NeedStub = isa<Function>(MO1.getGlobal());
624 bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
625 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
627 } else if (MO1.isSymbol())
628 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
629 else if (MO1.isCPI())
630 emitConstPoolAddress(MO1.getIndex(), rt);
631 else if (MO1.isJTI())
632 emitJumpTableAddress(MO1.getIndex(), rt);
637 case X86II::MRMDestReg: {
638 MCE.emitByte(BaseOpcode);
639 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
640 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
643 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
646 case X86II::MRMDestMem: {
647 MCE.emitByte(BaseOpcode);
648 emitMemModRMByte(MI, CurOp,
649 getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
651 CurOp += X86AddrNumOperands + 1;
653 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
657 case X86II::MRMSrcReg:
658 MCE.emitByte(BaseOpcode);
659 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
660 getX86RegNum(MI.getOperand(CurOp).getReg()));
663 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
666 case X86II::MRMSrcMem: {
667 intptr_t PCAdj = (CurOp + X86AddrNumOperands + 1 != NumOps) ?
668 X86InstrInfo::sizeOfImm(Desc) : 0;
670 MCE.emitByte(BaseOpcode);
671 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
673 CurOp += X86AddrNumOperands + 1;
675 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
679 case X86II::MRM0r: case X86II::MRM1r:
680 case X86II::MRM2r: case X86II::MRM3r:
681 case X86II::MRM4r: case X86II::MRM5r:
682 case X86II::MRM6r: case X86II::MRM7r: {
683 MCE.emitByte(BaseOpcode);
685 // Special handling of lfence and mfence.
686 if (Desc->getOpcode() == X86::LFENCE ||
687 Desc->getOpcode() == X86::MFENCE)
688 emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
690 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
691 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
693 if (CurOp != NumOps) {
694 const MachineOperand &MO1 = MI.getOperand(CurOp++);
695 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
697 emitConstant(MO1.getImm(), Size);
699 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
700 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
701 if (Opcode == X86::MOV64ri32)
702 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
703 if (MO1.isGlobal()) {
704 bool NeedStub = isa<Function>(MO1.getGlobal());
705 bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
706 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
708 } else if (MO1.isSymbol())
709 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
710 else if (MO1.isCPI())
711 emitConstPoolAddress(MO1.getIndex(), rt);
712 else if (MO1.isJTI())
713 emitJumpTableAddress(MO1.getIndex(), rt);
719 case X86II::MRM0m: case X86II::MRM1m:
720 case X86II::MRM2m: case X86II::MRM3m:
721 case X86II::MRM4m: case X86II::MRM5m:
722 case X86II::MRM6m: case X86II::MRM7m: {
723 intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
724 (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
726 MCE.emitByte(BaseOpcode);
727 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
729 CurOp += X86AddrNumOperands;
731 if (CurOp != NumOps) {
732 const MachineOperand &MO = MI.getOperand(CurOp++);
733 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
735 emitConstant(MO.getImm(), Size);
737 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
738 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
739 if (Opcode == X86::MOV64mi32)
740 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
742 bool NeedStub = isa<Function>(MO.getGlobal());
743 bool Indirect = gvNeedsNonLazyPtr(MO.getGlobal());
744 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
746 } else if (MO.isSymbol())
747 emitExternalSymbolAddress(MO.getSymbolName(), rt);
749 emitConstPoolAddress(MO.getIndex(), rt);
751 emitJumpTableAddress(MO.getIndex(), rt);
757 case X86II::MRMInitReg:
758 MCE.emitByte(BaseOpcode);
759 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
760 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
761 getX86RegNum(MI.getOperand(CurOp).getReg()));
766 if (!Desc->isVariadic() && CurOp != NumOps) {
767 cerr << "Cannot encode: ";