1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #include "X86InstrInfo.h"
16 #include "X86Subtarget.h"
17 #include "X86TargetMachine.h"
18 #include "X86Relocations.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/CodeGen/MachineCodeEmitter.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/Function.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Target/TargetOptions.h"
33 NumEmitted("x86-emitter", "Number of machine instructions emitted");
37 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
38 const X86InstrInfo *II;
41 MachineCodeEmitter &MCE;
44 explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
45 : II(0), TD(0), TM(tm), MCE(mce), Is64BitMode(false) {}
46 Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
47 const X86InstrInfo &ii, const TargetData &td, bool is64)
48 : II(&ii), TD(&td), TM(tm), MCE(mce), Is64BitMode(is64) {}
50 bool runOnMachineFunction(MachineFunction &MF);
52 virtual const char *getPassName() const {
53 return "X86 Machine Code Emitter";
56 void emitInstruction(const MachineInstr &MI);
59 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
60 void emitPCRelativeValue(intptr_t Address);
61 void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
62 void emitGlobalAddressForPtr(GlobalValue *GV, bool isPCRelative,
63 int Disp = 0, unsigned PCAdj = 0);
64 void emitExternalSymbolAddress(const char *ES, bool isPCRelative);
65 void emitPCRelativeConstPoolAddress(unsigned CPI, int Disp = 0,
67 void emitPCRelativeJumpTableAddress(unsigned JTI, unsigned PCAdj = 0);
69 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
72 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
73 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
74 void emitConstant(uint64_t Val, unsigned Size);
76 void emitMemModRMByte(const MachineInstr &MI,
77 unsigned Op, unsigned RegOpcodeField,
80 unsigned getX86RegNum(unsigned RegNo);
81 bool isX86_64ExtendedReg(const MachineOperand &MO);
82 unsigned determineREX(const MachineInstr &MI);
86 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
87 /// to the specified MCE object.
88 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
89 MachineCodeEmitter &MCE) {
90 return new Emitter(TM, MCE);
93 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
94 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
95 MF.getTarget().getRelocationModel() != Reloc::Static) &&
96 "JIT relocation model must be set to static or default!");
97 II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
98 TD = ((X86TargetMachine&)MF.getTarget()).getTargetData();
100 ((X86TargetMachine&)MF.getTarget()).getSubtarget<X86Subtarget>().is64Bit();
103 MCE.startFunction(MF);
104 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
106 MCE.StartMachineBasicBlock(MBB);
107 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
111 } while (MCE.finishFunction(MF));
116 /// emitPCRelativeValue - Emit a PC relative address.
118 void Emitter::emitPCRelativeValue(intptr_t Address) {
119 MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
122 /// emitPCRelativeBlockAddress - This method keeps track of the information
123 /// necessary to resolve the address of this block later and emits a dummy
126 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
127 // Remember where this reference was and where it is to so we can
128 // deal with it later.
129 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
130 X86::reloc_pcrel_word, MBB));
134 /// emitGlobalAddressForCall - Emit the specified address to the code stream
135 /// assuming this is part of a function call, which is PC relative.
137 void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
138 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
139 X86::reloc_pcrel_word, GV, 0,
144 /// emitGlobalAddress - Emit the specified address to the code stream assuming
145 /// this is part of a "take the address of a global" instruction.
147 void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, bool isPCRelative,
149 unsigned PCAdj /* = 0 */) {
150 unsigned rt = isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
151 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), rt,
153 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
156 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
157 /// be emitted to the current location in the function, and allow it to be PC
159 void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative) {
160 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
161 isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
165 /// emitPCRelativeConstPoolAddress - Arrange for the address of an constant pool
166 /// to be emitted to the current location in the function, and allow it to be PC
168 void Emitter::emitPCRelativeConstPoolAddress(unsigned CPI, int Disp /* = 0 */,
169 unsigned PCAdj /* = 0 */) {
170 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
171 X86::reloc_pcrel_word, CPI, PCAdj));
172 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
175 /// emitPCRelativeJumpTableAddress - Arrange for the address of a jump table to
176 /// be emitted to the current location in the function, and allow it to be PC
178 void Emitter::emitPCRelativeJumpTableAddress(unsigned JTI,
179 unsigned PCAdj /* = 0 */) {
180 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
181 X86::reloc_pcrel_word, JTI, PCAdj));
182 MCE.emitWordLE(0); // The relocated value will be added to the displacement
185 /// N86 namespace - Native X86 Register numbers... used by X86 backend.
189 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
193 // getX86RegNum - This function maps LLVM register identifiers to their X86
194 // specific numbering, which is used in various places encoding instructions.
196 unsigned Emitter::getX86RegNum(unsigned RegNo) {
198 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
199 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
200 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
201 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
202 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
204 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
206 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
208 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
211 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
213 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
215 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
217 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
219 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
221 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
223 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
225 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
228 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
229 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
230 return RegNo-X86::ST0;
232 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
233 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
234 return II->getRegisterInfo().getDwarfRegNum(RegNo) -
235 II->getRegisterInfo().getDwarfRegNum(X86::XMM0);
236 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
237 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
238 return II->getRegisterInfo().getDwarfRegNum(RegNo) -
239 II->getRegisterInfo().getDwarfRegNum(X86::XMM8);
242 assert(MRegisterInfo::isVirtualRegister(RegNo) &&
243 "Unknown physical register!");
244 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
249 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
251 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
252 return RM | (RegOpcode << 3) | (Mod << 6);
255 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
256 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
259 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
260 // SIB byte is in the same format as the ModRMByte...
261 MCE.emitByte(ModRMByte(SS, Index, Base));
264 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
265 // Output the constant in little endian byte order...
266 for (unsigned i = 0; i != Size; ++i) {
267 MCE.emitByte(Val & 255);
272 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
273 /// sign-extended field.
274 static bool isDisp8(int Value) {
275 return Value == (signed char)Value;
278 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
279 int DispVal, unsigned PCAdj) {
280 // If this is a simple integer displacement that doesn't require a relocation,
283 emitConstant(DispVal, 4);
287 // Otherwise, this is something that requires a relocation. Emit it as such
289 if (RelocOp->isGlobalAddress()) {
290 // In 64-bit static small code model, we could potentially emit absolute.
291 // But it's probably not beneficial.
292 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
293 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
294 emitGlobalAddressForPtr(RelocOp->getGlobal(), Is64BitMode,
295 RelocOp->getOffset(), PCAdj);
296 } else if (RelocOp->isConstantPoolIndex()) {
297 // Must be in 64-bit mode.
298 emitPCRelativeConstPoolAddress(RelocOp->getConstantPoolIndex(),
299 RelocOp->getOffset(), PCAdj);
300 } else if (RelocOp->isJumpTableIndex()) {
301 // Must be in 64-bit mode.
302 emitPCRelativeJumpTableAddress(RelocOp->getJumpTableIndex(), PCAdj);
304 assert(0 && "Unknown value to relocate!");
308 void Emitter::emitMemModRMByte(const MachineInstr &MI,
309 unsigned Op, unsigned RegOpcodeField,
311 const MachineOperand &Op3 = MI.getOperand(Op+3);
313 const MachineOperand *DispForReloc = 0;
315 // Figure out what sort of displacement we have to handle here.
316 if (Op3.isGlobalAddress()) {
318 } else if (Op3.isConstantPoolIndex()) {
322 DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
323 DispVal += Op3.getOffset();
325 } else if (Op3.isJumpTableIndex()) {
329 DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
332 DispVal = Op3.getImm();
335 const MachineOperand &Base = MI.getOperand(Op);
336 const MachineOperand &Scale = MI.getOperand(Op+1);
337 const MachineOperand &IndexReg = MI.getOperand(Op+2);
339 unsigned BaseReg = Base.getReg();
341 // Is a SIB byte needed?
342 if (IndexReg.getReg() == 0 &&
343 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
344 if (BaseReg == 0) { // Just a displacement?
345 // Emit special case [disp32] encoding
346 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
348 emitDisplacementField(DispForReloc, DispVal, PCAdj);
350 unsigned BaseRegNo = getX86RegNum(BaseReg);
351 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
352 // Emit simple indirect register encoding... [EAX] f.e.
353 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
354 } else if (!DispForReloc && isDisp8(DispVal)) {
355 // Emit the disp8 encoding... [REG+disp8]
356 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
357 emitConstant(DispVal, 1);
359 // Emit the most general non-SIB encoding: [REG+disp32]
360 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
361 emitDisplacementField(DispForReloc, DispVal, PCAdj);
365 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
366 assert(IndexReg.getReg() != X86::ESP &&
367 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
369 bool ForceDisp32 = false;
370 bool ForceDisp8 = false;
372 // If there is no base register, we emit the special case SIB byte with
373 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
374 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
376 } else if (DispForReloc) {
377 // Emit the normal disp32 encoding.
378 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
380 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
381 // Emit no displacement ModR/M byte
382 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
383 } else if (isDisp8(DispVal)) {
384 // Emit the disp8 encoding...
385 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
386 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
388 // Emit the normal disp32 encoding...
389 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
392 // Calculate what the SS field value should be...
393 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
394 unsigned SS = SSTable[Scale.getImm()];
397 // Handle the SIB byte for the case where there is no base. The
398 // displacement has already been output.
399 assert(IndexReg.getReg() && "Index register must be specified!");
400 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
402 unsigned BaseRegNo = getX86RegNum(BaseReg);
404 if (IndexReg.getReg())
405 IndexRegNo = getX86RegNum(IndexReg.getReg());
407 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
408 emitSIBByte(SS, IndexRegNo, BaseRegNo);
411 // Do we need to output a displacement?
413 emitConstant(DispVal, 1);
414 } else if (DispVal != 0 || ForceDisp32) {
415 emitDisplacementField(DispForReloc, DispVal, PCAdj);
420 static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
421 switch (Desc.TSFlags & X86II::ImmMask) {
422 case X86II::Imm8: return 1;
423 case X86II::Imm16: return 2;
424 case X86II::Imm32: return 4;
425 case X86II::Imm64: return 8;
426 default: assert(0 && "Immediate size not set!");
431 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
432 /// e.g. r8, xmm8, etc.
433 bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
434 if (!MO.isRegister()) return false;
435 unsigned RegNo = MO.getReg();
436 int DWNum = II->getRegisterInfo().getDwarfRegNum(RegNo);
437 if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::R8) &&
438 DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::R15))
440 if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::XMM8) &&
441 DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::XMM15))
446 inline static bool isX86_64TruncToByte(unsigned oc) {
447 return (oc == X86::TRUNC_64to8 || oc == X86::TRUNC_32to8 ||
448 oc == X86::TRUNC_16to8);
452 inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
453 return (reg == X86::SPL || reg == X86::BPL ||
454 reg == X86::SIL || reg == X86::DIL);
457 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
458 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
459 /// size, and 3) use of X86-64 extended registers.
460 unsigned Emitter::determineREX(const MachineInstr &MI) {
462 unsigned Opcode = MI.getOpcode();
463 const TargetInstrDescriptor &Desc = II->get(Opcode);
465 // Pseudo instructions do not need REX prefix byte.
466 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
468 if (Desc.TSFlags & X86II::REX_W)
471 unsigned NumOps = II->getNumOperands(Opcode);
473 bool isTwoAddr = NumOps > 1 &&
474 II->getOperandConstraint(Opcode, 1, TOI::TIED_TO) != -1;
476 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
477 bool isTrunc8 = isX86_64TruncToByte(Opcode);
478 unsigned i = isTwoAddr ? 1 : 0;
479 for (unsigned e = NumOps; i != e; ++i) {
480 const MachineOperand& MO = MI.getOperand(i);
481 if (MO.isRegister()) {
482 unsigned Reg = MO.getReg();
483 // Trunc to byte are actually movb. The real source operand is the low
484 // byte of the register.
485 if (isTrunc8 && i == 1)
486 Reg = getX86SubSuperRegister(Reg, MVT::i8);
487 if (isX86_64NonExtLowByteReg(Reg))
492 switch (Desc.TSFlags & X86II::FormMask) {
493 case X86II::MRMInitReg:
494 if (isX86_64ExtendedReg(MI.getOperand(0)))
495 REX |= (1 << 0) | (1 << 2);
497 case X86II::MRMSrcReg: {
498 if (isX86_64ExtendedReg(MI.getOperand(0)))
500 i = isTwoAddr ? 2 : 1;
501 for (unsigned e = NumOps; i != e; ++i) {
502 const MachineOperand& MO = MI.getOperand(i);
503 if (isX86_64ExtendedReg(MO))
508 case X86II::MRMSrcMem: {
509 if (isX86_64ExtendedReg(MI.getOperand(0)))
512 i = isTwoAddr ? 2 : 1;
513 for (; i != NumOps; ++i) {
514 const MachineOperand& MO = MI.getOperand(i);
515 if (MO.isRegister()) {
516 if (isX86_64ExtendedReg(MO))
523 case X86II::MRM0m: case X86II::MRM1m:
524 case X86II::MRM2m: case X86II::MRM3m:
525 case X86II::MRM4m: case X86II::MRM5m:
526 case X86II::MRM6m: case X86II::MRM7m:
527 case X86II::MRMDestMem: {
528 unsigned e = isTwoAddr ? 5 : 4;
529 i = isTwoAddr ? 1 : 0;
530 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
533 for (; i != e; ++i) {
534 const MachineOperand& MO = MI.getOperand(i);
535 if (MO.isRegister()) {
536 if (isX86_64ExtendedReg(MO))
544 if (isX86_64ExtendedReg(MI.getOperand(0)))
546 i = isTwoAddr ? 2 : 1;
547 for (unsigned e = NumOps; i != e; ++i) {
548 const MachineOperand& MO = MI.getOperand(i);
549 if (isX86_64ExtendedReg(MO))
559 void Emitter::emitInstruction(const MachineInstr &MI) {
560 NumEmitted++; // Keep track of the # of mi's emitted
562 unsigned Opcode = MI.getOpcode();
563 const TargetInstrDescriptor &Desc = II->get(Opcode);
565 // Emit the repeat opcode prefix as needed.
566 if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
568 // Emit the operand size opcode prefix as needed.
569 if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
571 // Emit the address size opcode prefix as needed.
572 if (Desc.TSFlags & X86II::AdSize) MCE.emitByte(0x67);
574 bool Need0FPrefix = false;
575 switch (Desc.TSFlags & X86II::Op0Mask) {
577 Need0FPrefix = true; // Two-byte opcode prefix
579 case X86II::REP: break; // already handled.
580 case X86II::XS: // F3 0F
584 case X86II::XD: // F2 0F
588 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
589 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
591 (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
592 >> X86II::Op0Shift));
593 break; // Two-byte opcode prefix
594 default: assert(0 && "Invalid prefix!");
595 case 0: break; // No prefix!
600 unsigned REX = determineREX(MI);
602 MCE.emitByte(0x40 | REX);
605 // 0x0F escape code must be emitted just before the opcode.
609 // If this is a two-address instruction, skip one of the register operands.
610 unsigned NumOps = II->getNumOperands(Opcode);
613 II->getOperandConstraint(Opcode, 1, TOI::TIED_TO) != -1)
616 unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
617 switch (Desc.TSFlags & X86II::FormMask) {
618 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
623 assert(0 && "psuedo instructions should be removed before code emission");
624 case TargetInstrInfo::INLINEASM:
625 assert(0 && "JIT does not support inline asm!\n");
626 case X86::IMPLICIT_USE:
627 case X86::IMPLICIT_DEF:
628 case X86::IMPLICIT_DEF_GR8:
629 case X86::IMPLICIT_DEF_GR16:
630 case X86::IMPLICIT_DEF_GR32:
631 case X86::IMPLICIT_DEF_GR64:
632 case X86::IMPLICIT_DEF_FR32:
633 case X86::IMPLICIT_DEF_FR64:
634 case X86::IMPLICIT_DEF_VR64:
635 case X86::IMPLICIT_DEF_VR128:
636 case X86::FP_REG_KILL:
644 MCE.emitByte(BaseOpcode);
645 if (CurOp != NumOps) {
646 const MachineOperand &MO = MI.getOperand(CurOp++);
647 if (MO.isMachineBasicBlock()) {
648 emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
649 } else if (MO.isGlobalAddress()) {
650 bool isTailCall = Opcode == X86::TAILJMPd ||
651 Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
652 emitGlobalAddressForCall(MO.getGlobal(), !isTailCall);
653 } else if (MO.isExternalSymbol()) {
654 emitExternalSymbolAddress(MO.getSymbolName(), true);
655 } else if (MO.isImmediate()) {
656 emitConstant(MO.getImm(), sizeOfImm(Desc));
658 assert(0 && "Unknown RawFrm operand!");
663 case X86II::AddRegFrm:
664 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
666 if (CurOp != NumOps) {
667 const MachineOperand &MO1 = MI.getOperand(CurOp++);
668 if (MO1.isGlobalAddress()) {
669 assert(sizeOfImm(Desc) == TD->getPointerSize() &&
670 "Don't know how to emit non-pointer values!");
671 emitGlobalAddressForPtr(MO1.getGlobal(), Is64BitMode, MO1.getOffset());
672 } else if (MO1.isExternalSymbol()) {
673 assert(sizeOfImm(Desc) == TD->getPointerSize() &&
674 "Don't know how to emit non-pointer values!");
675 emitExternalSymbolAddress(MO1.getSymbolName(), false);
676 } else if (MO1.isJumpTableIndex()) {
677 assert(sizeOfImm(Desc) == TD->getPointerSize() &&
678 "Don't know how to emit non-pointer values!");
679 emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
681 emitConstant(MO1.getImm(), sizeOfImm(Desc));
686 case X86II::MRMDestReg: {
687 MCE.emitByte(BaseOpcode);
688 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
689 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
692 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
695 case X86II::MRMDestMem: {
696 MCE.emitByte(BaseOpcode);
697 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
700 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
704 case X86II::MRMSrcReg:
705 MCE.emitByte(BaseOpcode);
706 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
707 getX86RegNum(MI.getOperand(CurOp).getReg()));
710 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
713 case X86II::MRMSrcMem: {
714 unsigned PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
716 MCE.emitByte(BaseOpcode);
717 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
721 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
725 case X86II::MRM0r: case X86II::MRM1r:
726 case X86II::MRM2r: case X86II::MRM3r:
727 case X86II::MRM4r: case X86II::MRM5r:
728 case X86II::MRM6r: case X86II::MRM7r:
729 MCE.emitByte(BaseOpcode);
730 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
731 (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
733 if (CurOp != NumOps && MI.getOperand(CurOp).isImmediate())
734 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
737 case X86II::MRM0m: case X86II::MRM1m:
738 case X86II::MRM2m: case X86II::MRM3m:
739 case X86II::MRM4m: case X86II::MRM5m:
740 case X86II::MRM6m: case X86II::MRM7m: {
741 unsigned PCAdj = (CurOp+4 != NumOps) ?
742 (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
744 MCE.emitByte(BaseOpcode);
745 emitMemModRMByte(MI, CurOp, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m,
749 if (CurOp != NumOps) {
750 const MachineOperand &MO = MI.getOperand(CurOp++);
751 if (MO.isImmediate())
752 emitConstant(MO.getImm(), sizeOfImm(Desc));
753 else if (MO.isGlobalAddress())
754 emitGlobalAddressForPtr(MO.getGlobal(), Is64BitMode, MO.getOffset());
755 else if (MO.isJumpTableIndex())
756 emitConstant(MCE.getJumpTableEntryAddress(MO.getJumpTableIndex()), 4);
758 assert(0 && "Unknown operand!");
763 case X86II::MRMInitReg:
764 MCE.emitByte(BaseOpcode);
765 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
766 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
767 getX86RegNum(MI.getOperand(CurOp).getReg()));
772 assert((Desc.Flags & M_VARIABLE_OPS) != 0 ||
773 CurOp == NumOps && "Unknown encoding!");