1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCMachObjectWriter.h"
18 #include "llvm/MC/MCObjectFormat.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSectionCOFF.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/Object/MachOFormat.h"
24 #include "llvm/Support/ELF.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegistry.h"
28 #include "llvm/Target/TargetAsmBackend.h"
31 static unsigned getFixupKindLog2Size(unsigned Kind) {
33 default: assert(0 && "invalid fixup kind!");
35 case FK_Data_1: return 0;
37 case FK_Data_2: return 1;
39 case X86::reloc_riprel_4byte:
40 case X86::reloc_riprel_4byte_movq_load:
41 case X86::reloc_signed_4byte:
42 case X86::reloc_global_offset_table:
43 case FK_Data_4: return 2;
44 case FK_Data_8: return 3;
49 class X86AsmBackend : public TargetAsmBackend {
51 X86AsmBackend(const Target &T)
52 : TargetAsmBackend() {}
54 unsigned getNumFixupKinds() const {
55 return X86::NumTargetFixupKinds;
58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
59 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
60 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
61 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
62 { "reloc_signed_4byte", 0, 4 * 8, 0},
63 { "reloc_global_offset_table", 0, 4 * 8, 0}
66 if (Kind < FirstTargetFixupKind)
67 return TargetAsmBackend::getFixupKindInfo(Kind);
69 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
71 return Infos[Kind - FirstTargetFixupKind];
74 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
75 uint64_t Value) const {
76 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
78 assert(Fixup.getOffset() + Size <= DataSize &&
79 "Invalid fixup offset!");
80 for (unsigned i = 0; i != Size; ++i)
81 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
84 bool MayNeedRelaxation(const MCInst &Inst) const;
86 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
88 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
90 } // end anonymous namespace
92 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
97 case X86::JAE_1: return X86::JAE_4;
98 case X86::JA_1: return X86::JA_4;
99 case X86::JBE_1: return X86::JBE_4;
100 case X86::JB_1: return X86::JB_4;
101 case X86::JE_1: return X86::JE_4;
102 case X86::JGE_1: return X86::JGE_4;
103 case X86::JG_1: return X86::JG_4;
104 case X86::JLE_1: return X86::JLE_4;
105 case X86::JL_1: return X86::JL_4;
106 case X86::JMP_1: return X86::JMP_4;
107 case X86::JNE_1: return X86::JNE_4;
108 case X86::JNO_1: return X86::JNO_4;
109 case X86::JNP_1: return X86::JNP_4;
110 case X86::JNS_1: return X86::JNS_4;
111 case X86::JO_1: return X86::JO_4;
112 case X86::JP_1: return X86::JP_4;
113 case X86::JS_1: return X86::JS_4;
117 static unsigned getRelaxedOpcodeArith(unsigned Op) {
123 case X86::IMUL16rri8: return X86::IMUL16rri;
124 case X86::IMUL16rmi8: return X86::IMUL16rmi;
125 case X86::IMUL32rri8: return X86::IMUL32rri;
126 case X86::IMUL32rmi8: return X86::IMUL32rmi;
127 case X86::IMUL64rri8: return X86::IMUL64rri32;
128 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
131 case X86::AND16ri8: return X86::AND16ri;
132 case X86::AND16mi8: return X86::AND16mi;
133 case X86::AND32ri8: return X86::AND32ri;
134 case X86::AND32mi8: return X86::AND32mi;
135 case X86::AND64ri8: return X86::AND64ri32;
136 case X86::AND64mi8: return X86::AND64mi32;
139 case X86::OR16ri8: return X86::OR16ri;
140 case X86::OR16mi8: return X86::OR16mi;
141 case X86::OR32ri8: return X86::OR32ri;
142 case X86::OR32mi8: return X86::OR32mi;
143 case X86::OR64ri8: return X86::OR64ri32;
144 case X86::OR64mi8: return X86::OR64mi32;
147 case X86::XOR16ri8: return X86::XOR16ri;
148 case X86::XOR16mi8: return X86::XOR16mi;
149 case X86::XOR32ri8: return X86::XOR32ri;
150 case X86::XOR32mi8: return X86::XOR32mi;
151 case X86::XOR64ri8: return X86::XOR64ri32;
152 case X86::XOR64mi8: return X86::XOR64mi32;
155 case X86::ADD16ri8: return X86::ADD16ri;
156 case X86::ADD16mi8: return X86::ADD16mi;
157 case X86::ADD32ri8: return X86::ADD32ri;
158 case X86::ADD32mi8: return X86::ADD32mi;
159 case X86::ADD64ri8: return X86::ADD64ri32;
160 case X86::ADD64mi8: return X86::ADD64mi32;
163 case X86::SUB16ri8: return X86::SUB16ri;
164 case X86::SUB16mi8: return X86::SUB16mi;
165 case X86::SUB32ri8: return X86::SUB32ri;
166 case X86::SUB32mi8: return X86::SUB32mi;
167 case X86::SUB64ri8: return X86::SUB64ri32;
168 case X86::SUB64mi8: return X86::SUB64mi32;
171 case X86::CMP16ri8: return X86::CMP16ri;
172 case X86::CMP16mi8: return X86::CMP16mi;
173 case X86::CMP32ri8: return X86::CMP32ri;
174 case X86::CMP32mi8: return X86::CMP32mi;
175 case X86::CMP64ri8: return X86::CMP64ri32;
176 case X86::CMP64mi8: return X86::CMP64mi32;
180 static unsigned getRelaxedOpcode(unsigned Op) {
181 unsigned R = getRelaxedOpcodeArith(Op);
184 return getRelaxedOpcodeBranch(Op);
187 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
188 // Branches can always be relaxed.
189 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
192 // Check if this instruction is ever relaxable.
193 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
197 // Check if it has an expression and is not RIP relative.
200 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
201 const MCOperand &Op = Inst.getOperand(i);
205 if (Op.isReg() && Op.getReg() == X86::RIP)
209 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
210 // how we do relaxations?
211 return hasExp && !hasRIP;
214 // FIXME: Can tblgen help at all here to verify there aren't other instructions
216 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
217 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
218 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
220 if (RelaxedOp == Inst.getOpcode()) {
221 SmallString<256> Tmp;
222 raw_svector_ostream OS(Tmp);
223 Inst.dump_pretty(OS);
225 report_fatal_error("unexpected instruction to relax: " + OS.str());
229 Res.setOpcode(RelaxedOp);
232 /// WriteNopData - Write optimal nops to the output file for the \arg Count
233 /// bytes. This returns the number of bytes written. It may return 0 if
234 /// the \arg Count is more than the maximum optimal nops.
235 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
236 static const uint8_t Nops[10][10] = {
244 {0x0f, 0x1f, 0x40, 0x00},
245 // nopl 0(%[re]ax,%[re]ax,1)
246 {0x0f, 0x1f, 0x44, 0x00, 0x00},
247 // nopw 0(%[re]ax,%[re]ax,1)
248 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
250 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
251 // nopl 0L(%[re]ax,%[re]ax,1)
252 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
253 // nopw 0L(%[re]ax,%[re]ax,1)
254 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
255 // nopw %cs:0L(%[re]ax,%[re]ax,1)
256 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
259 // Write an optimal sequence for the first 15 bytes.
260 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
261 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
262 for (uint64_t i = 0, e = Prefixes; i != e; i++)
264 const uint64_t Rest = OptimalCount - Prefixes;
265 for (uint64_t i = 0, e = Rest; i != e; i++)
266 OW->Write8(Nops[Rest - 1][i]);
268 // Finish with single byte nops.
269 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
278 class ELFX86AsmBackend : public X86AsmBackend {
279 MCELFObjectFormat Format;
282 Triple::OSType OSType;
283 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
284 : X86AsmBackend(T), OSType(_OSType) {
285 HasScatteredSymbols = true;
286 HasReliableSymbolDifference = true;
289 virtual const MCObjectFormat &getObjectFormat() const {
293 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
294 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
295 return ES.getFlags() & MCSectionELF::SHF_MERGE;
299 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
301 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
302 : ELFX86AsmBackend(T, OSType) {}
304 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
305 return createELFObjectWriter(OS, /*Is64Bit=*/false,
307 /*IsLittleEndian=*/true,
308 /*HasRelocationAddend=*/false);
312 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
314 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
315 : ELFX86AsmBackend(T, OSType) {}
317 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
318 return createELFObjectWriter(OS, /*Is64Bit=*/true,
319 OSType, ELF::EM_X86_64,
320 /*IsLittleEndian=*/true,
321 /*HasRelocationAddend=*/true);
325 class WindowsX86AsmBackend : public X86AsmBackend {
327 MCCOFFObjectFormat Format;
330 WindowsX86AsmBackend(const Target &T, bool is64Bit)
333 HasScatteredSymbols = true;
336 virtual const MCObjectFormat &getObjectFormat() const {
340 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
341 return createWinCOFFObjectWriter(OS, Is64Bit);
345 class DarwinX86AsmBackend : public X86AsmBackend {
346 MCMachOObjectFormat Format;
349 DarwinX86AsmBackend(const Target &T)
351 HasScatteredSymbols = true;
354 virtual const MCObjectFormat &getObjectFormat() const {
359 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
361 DarwinX86_32AsmBackend(const Target &T)
362 : DarwinX86AsmBackend(T) {}
364 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
365 return createMachObjectWriter(OS, /*Is64Bit=*/false,
366 object::mach::CTM_i386,
367 object::mach::CSX86_ALL,
368 /*IsLittleEndian=*/true);
372 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
374 DarwinX86_64AsmBackend(const Target &T)
375 : DarwinX86AsmBackend(T) {
376 HasReliableSymbolDifference = true;
379 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
380 return createMachObjectWriter(OS, /*Is64Bit=*/true,
381 object::mach::CTM_x86_64,
382 object::mach::CSX86_ALL,
383 /*IsLittleEndian=*/true);
386 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
387 // Temporary labels in the string literals sections require symbols. The
388 // issue is that the x86_64 relocation format does not allow symbol +
389 // offset, and so the linker does not have enough information to resolve the
390 // access to the appropriate atom unless an external relocation is used. For
391 // non-cstring sections, we expect the compiler to use a non-temporary label
392 // for anything that could have an addend pointing outside the symbol.
394 // See <rdar://problem/4765733>.
395 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
396 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
399 virtual bool isSectionAtomizable(const MCSection &Section) const {
400 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
401 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
402 switch (SMO.getType()) {
406 case MCSectionMachO::S_4BYTE_LITERALS:
407 case MCSectionMachO::S_8BYTE_LITERALS:
408 case MCSectionMachO::S_16BYTE_LITERALS:
409 case MCSectionMachO::S_LITERAL_POINTERS:
410 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
411 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
412 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
413 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
414 case MCSectionMachO::S_INTERPOSING:
420 } // end anonymous namespace
422 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
423 const std::string &TT) {
424 switch (Triple(TT).getOS()) {
426 return new DarwinX86_32AsmBackend(T);
427 case Triple::MinGW32:
430 return new WindowsX86AsmBackend(T, false);
432 return new ELFX86_32AsmBackend(T, Triple(TT).getOS());
436 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
437 const std::string &TT) {
438 switch (Triple(TT).getOS()) {
440 return new DarwinX86_64AsmBackend(T);
441 case Triple::MinGW64:
444 return new WindowsX86AsmBackend(T, true);
446 return new ELFX86_64AsmBackend(T, Triple(TT).getOS());