1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/ELFObjectWriter.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectFormat.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionCOFF.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSectionMachO.h"
22 #include "llvm/MC/MachObjectWriter.h"
23 #include "llvm/Support/ELF.h"
24 #include "llvm/Support/MachO.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegistry.h"
28 #include "llvm/Target/TargetAsmBackend.h"
32 static unsigned getFixupKindLog2Size(unsigned Kind) {
34 default: assert(0 && "invalid fixup kind!");
35 case X86::reloc_pcrel_1byte:
36 case FK_Data_1: return 0;
37 case X86::reloc_pcrel_2byte:
38 case FK_Data_2: return 1;
39 case X86::reloc_pcrel_4byte:
40 case X86::reloc_riprel_4byte:
41 case X86::reloc_riprel_4byte_movq_load:
42 case X86::reloc_signed_4byte:
43 case X86::reloc_global_offset_table:
44 case FK_Data_4: return 2;
45 case FK_Data_8: return 3;
50 class X86AsmBackend : public TargetAsmBackend {
52 X86AsmBackend(const Target &T)
53 : TargetAsmBackend(T) {}
55 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
56 uint64_t Value) const {
57 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
59 assert(Fixup.getOffset() + Size <= DF.getContents().size() &&
60 "Invalid fixup offset!");
61 for (unsigned i = 0; i != Size; ++i)
62 DF.getContents()[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
65 bool MayNeedRelaxation(const MCInst &Inst) const;
67 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
69 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
71 } // end anonymous namespace
73 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
78 case X86::JAE_1: return X86::JAE_4;
79 case X86::JA_1: return X86::JA_4;
80 case X86::JBE_1: return X86::JBE_4;
81 case X86::JB_1: return X86::JB_4;
82 case X86::JE_1: return X86::JE_4;
83 case X86::JGE_1: return X86::JGE_4;
84 case X86::JG_1: return X86::JG_4;
85 case X86::JLE_1: return X86::JLE_4;
86 case X86::JL_1: return X86::JL_4;
87 case X86::JMP_1: return X86::JMP_4;
88 case X86::JNE_1: return X86::JNE_4;
89 case X86::JNO_1: return X86::JNO_4;
90 case X86::JNP_1: return X86::JNP_4;
91 case X86::JNS_1: return X86::JNS_4;
92 case X86::JO_1: return X86::JO_4;
93 case X86::JP_1: return X86::JP_4;
94 case X86::JS_1: return X86::JS_4;
98 static unsigned getRelaxedOpcodeArith(unsigned Op) {
104 case X86::IMUL16rri8: return X86::IMUL16rri;
105 case X86::IMUL16rmi8: return X86::IMUL16rmi;
106 case X86::IMUL32rri8: return X86::IMUL32rri;
107 case X86::IMUL32rmi8: return X86::IMUL32rmi;
108 case X86::IMUL64rri8: return X86::IMUL64rri32;
109 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
112 case X86::AND16ri8: return X86::AND16ri;
113 case X86::AND16mi8: return X86::AND16mi;
114 case X86::AND32ri8: return X86::AND32ri;
115 case X86::AND32mi8: return X86::AND32mi;
116 case X86::AND64ri8: return X86::AND64ri32;
117 case X86::AND64mi8: return X86::AND64mi32;
120 case X86::OR16ri8: return X86::OR16ri;
121 case X86::OR16mi8: return X86::OR16mi;
122 case X86::OR32ri8: return X86::OR32ri;
123 case X86::OR32mi8: return X86::OR32mi;
124 case X86::OR64ri8: return X86::OR64ri32;
125 case X86::OR64mi8: return X86::OR64mi32;
128 case X86::XOR16ri8: return X86::XOR16ri;
129 case X86::XOR16mi8: return X86::XOR16mi;
130 case X86::XOR32ri8: return X86::XOR32ri;
131 case X86::XOR32mi8: return X86::XOR32mi;
132 case X86::XOR64ri8: return X86::XOR64ri32;
133 case X86::XOR64mi8: return X86::XOR64mi32;
136 case X86::ADD16ri8: return X86::ADD16ri;
137 case X86::ADD16mi8: return X86::ADD16mi;
138 case X86::ADD32ri8: return X86::ADD32ri;
139 case X86::ADD32mi8: return X86::ADD32mi;
140 case X86::ADD64ri8: return X86::ADD64ri32;
141 case X86::ADD64mi8: return X86::ADD64mi32;
144 case X86::SUB16ri8: return X86::SUB16ri;
145 case X86::SUB16mi8: return X86::SUB16mi;
146 case X86::SUB32ri8: return X86::SUB32ri;
147 case X86::SUB32mi8: return X86::SUB32mi;
148 case X86::SUB64ri8: return X86::SUB64ri32;
149 case X86::SUB64mi8: return X86::SUB64mi32;
152 case X86::CMP16ri8: return X86::CMP16ri;
153 case X86::CMP16mi8: return X86::CMP16mi;
154 case X86::CMP32ri8: return X86::CMP32ri;
155 case X86::CMP32mi8: return X86::CMP32mi;
156 case X86::CMP64ri8: return X86::CMP64ri32;
157 case X86::CMP64mi8: return X86::CMP64mi32;
161 static unsigned getRelaxedOpcode(unsigned Op) {
162 unsigned R = getRelaxedOpcodeArith(Op);
165 return getRelaxedOpcodeBranch(Op);
168 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
169 // Branches can always be relaxed.
170 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
173 // Check if this instruction is ever relaxable.
174 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
178 // Check if it has an expression and is not RIP relative.
181 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
182 const MCOperand &Op = Inst.getOperand(i);
186 if (Op.isReg() && Op.getReg() == X86::RIP)
190 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
191 // how we do relaxations?
192 return hasExp && !hasRIP;
195 // FIXME: Can tblgen help at all here to verify there aren't other instructions
197 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
198 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
199 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
201 if (RelaxedOp == Inst.getOpcode()) {
202 SmallString<256> Tmp;
203 raw_svector_ostream OS(Tmp);
204 Inst.dump_pretty(OS);
206 report_fatal_error("unexpected instruction to relax: " + OS.str());
210 Res.setOpcode(RelaxedOp);
213 /// WriteNopData - Write optimal nops to the output file for the \arg Count
214 /// bytes. This returns the number of bytes written. It may return 0 if
215 /// the \arg Count is more than the maximum optimal nops.
217 /// FIXME this is X86 32-bit specific and should move to a better place.
218 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
219 static const uint8_t Nops[16][16] = {
227 {0x0f, 0x1f, 0x40, 0x00},
228 // nopl 0(%[re]ax,%[re]ax,1)
229 {0x0f, 0x1f, 0x44, 0x00, 0x00},
230 // nopw 0(%[re]ax,%[re]ax,1)
231 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
233 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
234 // nopl 0L(%[re]ax,%[re]ax,1)
235 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
236 // nopw 0L(%[re]ax,%[re]ax,1)
237 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
238 // nopw %cs:0L(%[re]ax,%[re]ax,1)
239 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
240 // nopl 0(%[re]ax,%[re]ax,1)
241 // nopw 0(%[re]ax,%[re]ax,1)
242 {0x0f, 0x1f, 0x44, 0x00, 0x00,
243 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
244 // nopw 0(%[re]ax,%[re]ax,1)
245 // nopw 0(%[re]ax,%[re]ax,1)
246 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
247 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
248 // nopw 0(%[re]ax,%[re]ax,1)
249 // nopl 0L(%[re]ax) */
250 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
251 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
254 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
255 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
257 // nopl 0L(%[re]ax,%[re]ax,1)
258 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
259 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
262 // Write an optimal sequence for the first 15 bytes.
263 uint64_t OptimalCount = (Count < 16) ? Count : 15;
264 for (uint64_t i = 0, e = OptimalCount; i != e; i++)
265 OW->Write8(Nops[OptimalCount - 1][i]);
267 // Finish with single byte nops.
268 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
277 class ELFX86AsmBackend : public X86AsmBackend {
278 MCELFObjectFormat Format;
281 Triple::OSType OSType;
282 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
283 : X86AsmBackend(T), OSType(_OSType) {
284 HasScatteredSymbols = true;
285 HasReliableSymbolDifference = true;
288 virtual const MCObjectFormat &getObjectFormat() const {
292 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
293 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
294 return ES.getFlags() & MCSectionELF::SHF_MERGE;
297 bool isVirtualSection(const MCSection &Section) const {
298 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
299 return SE.getType() == MCSectionELF::SHT_NOBITS;
303 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
305 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
306 : ELFX86AsmBackend(T, OSType) {}
308 unsigned getPointerSize() const {
312 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
313 return new ELFObjectWriter(OS, /*Is64Bit=*/false,
315 /*IsLittleEndian=*/true,
316 /*HasRelocationAddend=*/false);
320 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
322 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
323 : ELFX86AsmBackend(T, OSType) {}
325 unsigned getPointerSize() const {
329 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
330 return new ELFObjectWriter(OS, /*Is64Bit=*/true,
331 OSType, ELF::EM_X86_64,
332 /*IsLittleEndian=*/true,
333 /*HasRelocationAddend=*/true);
337 class WindowsX86AsmBackend : public X86AsmBackend {
339 MCCOFFObjectFormat Format;
342 WindowsX86AsmBackend(const Target &T, bool is64Bit)
345 HasScatteredSymbols = true;
348 virtual const MCObjectFormat &getObjectFormat() const {
352 unsigned getPointerSize() const {
359 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
360 return createWinCOFFObjectWriter(OS, Is64Bit);
363 bool isVirtualSection(const MCSection &Section) const {
364 const MCSectionCOFF &SE = static_cast<const MCSectionCOFF&>(Section);
365 return SE.getCharacteristics() & COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA;
369 class DarwinX86AsmBackend : public X86AsmBackend {
370 MCMachOObjectFormat Format;
373 DarwinX86AsmBackend(const Target &T)
375 HasScatteredSymbols = true;
378 virtual const MCObjectFormat &getObjectFormat() const {
382 bool isVirtualSection(const MCSection &Section) const {
383 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
384 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
385 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL ||
386 SMO.getType() == MCSectionMachO::S_THREAD_LOCAL_ZEROFILL);
390 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
392 DarwinX86_32AsmBackend(const Target &T)
393 : DarwinX86AsmBackend(T) {}
395 unsigned getPointerSize() const {
399 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
400 return new MachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeI386,
401 MachO::CPUSubType_I386_ALL);
405 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
407 DarwinX86_64AsmBackend(const Target &T)
408 : DarwinX86AsmBackend(T) {
409 HasReliableSymbolDifference = true;
412 unsigned getPointerSize() const {
416 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
417 return new MachObjectWriter(OS, /*Is64Bit=*/true, MachO::CPUTypeX86_64,
418 MachO::CPUSubType_I386_ALL);
421 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
422 // Temporary labels in the string literals sections require symbols. The
423 // issue is that the x86_64 relocation format does not allow symbol +
424 // offset, and so the linker does not have enough information to resolve the
425 // access to the appropriate atom unless an external relocation is used. For
426 // non-cstring sections, we expect the compiler to use a non-temporary label
427 // for anything that could have an addend pointing outside the symbol.
429 // See <rdar://problem/4765733>.
430 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
431 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
434 virtual bool isSectionAtomizable(const MCSection &Section) const {
435 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
436 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
437 switch (SMO.getType()) {
441 case MCSectionMachO::S_4BYTE_LITERALS:
442 case MCSectionMachO::S_8BYTE_LITERALS:
443 case MCSectionMachO::S_16BYTE_LITERALS:
444 case MCSectionMachO::S_LITERAL_POINTERS:
445 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
446 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
447 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
448 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
449 case MCSectionMachO::S_INTERPOSING:
455 } // end anonymous namespace
457 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
458 const std::string &TT) {
459 switch (Triple(TT).getOS()) {
461 return new DarwinX86_32AsmBackend(T);
462 case Triple::MinGW32:
465 return new WindowsX86AsmBackend(T, false);
467 return new ELFX86_32AsmBackend(T, Triple(TT).getOS());
471 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
472 const std::string &TT) {
473 switch (Triple(TT).getOS()) {
475 return new DarwinX86_64AsmBackend(T);
476 case Triple::MinGW64:
479 return new WindowsX86AsmBackend(T, true);
481 return new ELFX86_64AsmBackend(T, Triple(TT).getOS());