1 //===-- X86ATTAsmPrinter.cpp - Convert X86 LLVM code to Intel assembly ----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to AT&T format assembly
12 // language. This printer is the output mechanism used by `llc'.
14 //===----------------------------------------------------------------------===//
16 #include "X86ATTAsmPrinter.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetAsmInfo.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Module.h"
23 #include "llvm/Support/Mangler.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Target/TargetOptions.h"
29 /// getSectionForFunction - Return the section that we should emit the
30 /// specified function body into.
31 std::string X86ATTAsmPrinter::getSectionForFunction(const Function &F) const {
32 switch (F.getLinkage()) {
33 default: assert(0 && "Unknown linkage type!");
34 case Function::InternalLinkage:
35 case Function::DLLExportLinkage:
36 case Function::ExternalLinkage:
37 return TAI->getTextSection();
38 case Function::WeakLinkage:
39 case Function::LinkOnceLinkage:
40 if (Subtarget->isTargetDarwin()) {
41 return ".section __TEXT,__textcoal_nt,coalesced,pure_instructions";
42 } else if (Subtarget->isTargetCygwin()) {
43 return "\t.section\t.llvm.linkonce.t." + CurrentFnName + ",\"ax\"\n";
45 return "\t.section\t.llvm.linkonce.t." + CurrentFnName +
46 ",\"ax\",@progbits\n";
51 /// runOnMachineFunction - This uses the printMachineInstruction()
52 /// method to print assembly for each instruction.
54 bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
55 if (Subtarget->isTargetDarwin()) {
56 // Let PassManager know we need debug information and relay
57 // the MachineDebugInfo address on to DwarfWriter.
58 DW.SetDebugInfo(&getAnalysis<MachineDebugInfo>());
61 SetupMachineFunction(MF);
64 // Print out constants referenced by the function
65 EmitConstantPool(MF.getConstantPool());
67 // Print out labels for the function.
68 const Function *F = MF.getFunction();
69 unsigned CC = F->getCallingConv();
71 // Populate function information map. Actually, We don't want to populate
72 // non-stdcall or non-fastcall functions' information right now.
73 if (CC == CallingConv::X86_StdCall || CC == CallingConv::X86_FastCall)
74 FunctionInfoMap[F] = *MF.getInfo<X86FunctionInfo>();
76 X86SharedAsmPrinter::decorateName(CurrentFnName, F);
78 SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
80 switch (F->getLinkage()) {
81 default: assert(0 && "Unknown linkage type!");
82 case Function::InternalLinkage: // Symbols default to internal.
83 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
85 case Function::DLLExportLinkage:
86 DLLExportedFns.insert(Mang->makeNameProper(F->getName(), ""));
88 case Function::ExternalLinkage:
89 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
90 O << "\t.globl\t" << CurrentFnName << "\n";
92 case Function::LinkOnceLinkage:
93 if (Subtarget->isTargetDarwin()) {
94 O << "\t.globl\t" << CurrentFnName << "\n";
95 O << "\t.weak_definition\t" << CurrentFnName << "\n";
96 } else if (Subtarget->isTargetCygwin()) {
97 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
98 O << "\t.linkonce discard\n";
99 O << "\t.globl " << CurrentFnName << "\n";
101 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
102 O << "\t.weak " << CurrentFnName << "\n";
105 case Function::WeakLinkage:
106 if (Subtarget->isTargetDarwin()) {
107 O << "\t.globl\t" << CurrentFnName << "\n";
108 O << "\t.weak_definition\t" << CurrentFnName << "\n";
109 } else if (Subtarget->isTargetCygwin()) {
110 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
111 O << "\t.weak " << CurrentFnName << "\n";
113 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
114 O << "\t.weak " << CurrentFnName << "\n";
118 O << CurrentFnName << ":\n";
120 if (Subtarget->isTargetDarwin()) {
121 // Emit pre-function debug information.
122 DW.BeginFunction(&MF);
125 // Print out code for the function.
126 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
128 // Print a label for the basic block.
129 if (I->pred_begin() != I->pred_end()) {
130 printBasicBlockLabel(I, true);
133 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
135 // Print the assembly for the instruction.
137 printMachineInstruction(II);
141 // Print out jump tables referenced by the function.
143 // Mac OS X requires that the jump table follow the function, so that the jump
144 // table is part of the same atom that the function is in.
145 EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
147 if (TAI->hasDotTypeDotSizeDirective())
148 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
150 if (Subtarget->isTargetDarwin()) {
151 // Emit post-function debug information.
155 // We didn't modify anything.
159 void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
160 const char *Modifier) {
161 const MachineOperand &MO = MI->getOperand(OpNo);
162 const MRegisterInfo &RI = *TM.getRegisterInfo();
163 switch (MO.getType()) {
164 case MachineOperand::MO_Register: {
165 assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
166 "Virtual registers should not make it this far!");
168 unsigned Reg = MO.getReg();
169 if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
170 MVT::ValueType VT = (strcmp(Modifier+6,"64") == 0) ?
171 MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
172 ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
173 Reg = getX86SubSuperRegister(Reg, VT);
175 for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
176 O << (char)tolower(*Name);
180 case MachineOperand::MO_Immediate:
181 if (!Modifier || strcmp(Modifier, "debug") != 0)
183 O << MO.getImmedValue();
185 case MachineOperand::MO_MachineBasicBlock:
186 printBasicBlockLabel(MO.getMachineBasicBlock());
188 case MachineOperand::MO_JumpTableIndex: {
189 bool isMemOp = Modifier && !strcmp(Modifier, "mem");
190 if (!isMemOp) O << '$';
191 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << "_"
192 << MO.getJumpTableIndex();
193 if (X86PICStyle == PICStyle::Stub &&
194 TM.getRelocationModel() == Reloc::PIC_)
195 O << "-\"L" << getFunctionNumber() << "$pb\"";
196 if (Subtarget->is64Bit())
200 case MachineOperand::MO_ConstantPoolIndex: {
201 bool isMemOp = Modifier && !strcmp(Modifier, "mem");
202 if (!isMemOp) O << '$';
203 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
204 << MO.getConstantPoolIndex();
205 if (X86PICStyle == PICStyle::Stub &&
206 TM.getRelocationModel() == Reloc::PIC_)
207 O << "-\"L" << getFunctionNumber() << "$pb\"";
208 int Offset = MO.getOffset();
214 if (Subtarget->is64Bit())
218 case MachineOperand::MO_GlobalAddress: {
219 bool isCallOp = Modifier && !strcmp(Modifier, "call");
220 bool isMemOp = Modifier && !strcmp(Modifier, "mem");
221 if (!isMemOp && !isCallOp) O << '$';
223 GlobalValue *GV = MO.getGlobal();
224 std::string Name = Mang->getValueName(GV);
226 bool isExt = (GV->isExternal() || GV->hasWeakLinkage() ||
227 GV->hasLinkOnceLinkage());
229 X86SharedAsmPrinter::decorateName(Name, GV);
231 if (X86PICStyle == PICStyle::Stub &&
232 TM.getRelocationModel() != Reloc::Static) {
233 // Link-once, External, or Weakly-linked global variables need
234 // non-lazily-resolved stubs
236 // Dynamically-resolved functions need a stub for the function.
237 if (isCallOp && isa<Function>(GV)) {
238 FnStubs.insert(Name);
239 O << "L" << Name << "$stub";
241 GVStubs.insert(Name);
242 O << "L" << Name << "$non_lazy_ptr";
245 if (GV->hasDLLImportLinkage()) {
251 if (!isCallOp && TM.getRelocationModel() == Reloc::PIC_)
252 O << "-\"L" << getFunctionNumber() << "$pb\"";
254 if (GV->hasDLLImportLinkage()) {
260 int Offset = MO.getOffset();
267 Subtarget->is64Bit()) {
268 if (isExt && TM.getRelocationModel() != Reloc::Static)
275 case MachineOperand::MO_ExternalSymbol: {
276 bool isCallOp = Modifier && !strcmp(Modifier, "call");
278 X86PICStyle == PICStyle::Stub &&
279 TM.getRelocationModel() != Reloc::Static) {
280 std::string Name(TAI->getGlobalPrefix());
281 Name += MO.getSymbolName();
282 FnStubs.insert(Name);
283 O << "L" << Name << "$stub";
286 if (!isCallOp) O << '$';
287 O << TAI->getGlobalPrefix() << MO.getSymbolName();
290 Subtarget->is64Bit())
296 O << "<unknown operand type>"; return;
300 void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
301 unsigned char value = MI->getOperand(Op).getImmedValue();
302 assert(value <= 7 && "Invalid ssecc argument!");
304 case 0: O << "eq"; break;
305 case 1: O << "lt"; break;
306 case 2: O << "le"; break;
307 case 3: O << "unord"; break;
308 case 4: O << "neq"; break;
309 case 5: O << "nlt"; break;
310 case 6: O << "nle"; break;
311 case 7: O << "ord"; break;
315 void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
316 const char *Modifier){
317 assert(isMem(MI, Op) && "Invalid memory reference!");
319 const MachineOperand &BaseReg = MI->getOperand(Op);
320 int ScaleVal = MI->getOperand(Op+1).getImmedValue();
321 const MachineOperand &IndexReg = MI->getOperand(Op+2);
322 const MachineOperand &DispSpec = MI->getOperand(Op+3);
324 if (BaseReg.isFrameIndex()) {
325 O << "[frame slot #" << BaseReg.getFrameIndex();
326 if (DispSpec.getImmedValue())
327 O << " + " << DispSpec.getImmedValue();
332 if (DispSpec.isGlobalAddress() ||
333 DispSpec.isConstantPoolIndex() ||
334 DispSpec.isJumpTableIndex()) {
335 printOperand(MI, Op+3, "mem");
337 int DispVal = DispSpec.getImmedValue();
338 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
342 if (IndexReg.getReg() || BaseReg.getReg()) {
344 if (BaseReg.getReg()) {
345 printOperand(MI, Op, Modifier);
348 if (IndexReg.getReg()) {
350 printOperand(MI, Op+2, Modifier);
352 O << "," << ScaleVal;
359 void X86ATTAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
360 O << "\"L" << getFunctionNumber() << "$pb\"\n";
361 O << "\"L" << getFunctionNumber() << "$pb\":";
365 bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
367 const MRegisterInfo &RI = *TM.getRegisterInfo();
368 unsigned Reg = MO.getReg();
370 default: return true; // Unknown mode.
371 case 'b': // Print QImode register
372 Reg = getX86SubSuperRegister(Reg, MVT::i8);
374 case 'h': // Print QImode high register
375 Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
377 case 'w': // Print HImode register
378 Reg = getX86SubSuperRegister(Reg, MVT::i16);
380 case 'k': // Print SImode register
381 Reg = getX86SubSuperRegister(Reg, MVT::i32);
386 for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
387 O << (char)tolower(*Name);
391 /// PrintAsmOperand - Print out an operand for an inline asm expression.
393 bool X86ATTAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
395 const char *ExtraCode) {
396 // Does this asm operand have a single letter operand modifier?
397 if (ExtraCode && ExtraCode[0]) {
398 if (ExtraCode[1] != 0) return true; // Unknown modifier.
400 switch (ExtraCode[0]) {
401 default: return true; // Unknown modifier.
402 case 'b': // Print QImode register
403 case 'h': // Print QImode high register
404 case 'w': // Print HImode register
405 case 'k': // Print SImode register
406 return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
410 printOperand(MI, OpNo);
414 bool X86ATTAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
417 const char *ExtraCode) {
418 if (ExtraCode && ExtraCode[0])
419 return true; // Unknown modifier.
420 printMemReference(MI, OpNo);
424 /// printMachineInstruction -- Print out a single X86 LLVM instruction
425 /// MI in Intel syntax to the current output stream.
427 void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
430 // See if a truncate instruction can be turned into a nop.
431 switch (MI->getOpcode()) {
433 case X86::TRUNC_64to32:
434 case X86::TRUNC_64to16:
435 case X86::TRUNC_32to16:
436 case X86::TRUNC_32to8:
437 case X86::TRUNC_16to8:
438 case X86::TRUNC_32_to8:
439 case X86::TRUNC_16_to8: {
440 const MachineOperand &MO0 = MI->getOperand(0);
441 const MachineOperand &MO1 = MI->getOperand(1);
442 unsigned Reg0 = MO0.getReg();
443 unsigned Reg1 = MO1.getReg();
444 unsigned Opc = MI->getOpcode();
445 if (Opc == X86::TRUNC_64to32)
446 Reg1 = getX86SubSuperRegister(Reg1, MVT::i32);
447 else if (Opc == X86::TRUNC_32to16 || Opc == X86::TRUNC_64to16)
448 Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
450 Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
451 O << TAI->getCommentString() << " TRUNCATE ";
456 case X86::PsMOVZX64rr32:
457 O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
461 // Call the autogenerated instruction printer routines.
462 printInstruction(MI);
465 // Include the auto-generated portion of the assembly writer.
466 #include "X86GenAsmWriter.inc"