lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state.
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25
  26 def ModeNaCl  : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
  27                                  "Native Client mode">;
  28
  29 //===----------------------------------------------------------------------===//
  30 // X86 Subtarget features.
  31 //===----------------------------------------------------------------------===//
  32
  33 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  34                                       "Enable conditional move instructions">;
  35
  36 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  37                                        "Support POPCNT instruction">;
  38
  39
  40 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  41                                       "Enable MMX instructions">;
  42 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  43                                       "Enable SSE instructions",
  44                                       // SSE codegen depends on cmovs, and all
  45                                       // SSE1+ processors support them.
  46                                       [FeatureMMX, FeatureCMOV]>;
  47 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  48                                       "Enable SSE2 instructions",
  49                                       [FeatureSSE1]>;
  50 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  51                                       "Enable SSE3 instructions",
  52                                       [FeatureSSE2]>;
  53 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  54                                       "Enable SSSE3 instructions",
  55                                       [FeatureSSE3]>;
  56 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  57                                       "Enable SSE 4.1 instructions",
  58                                       [FeatureSSSE3]>;
  59 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  60                                       "Enable SSE 4.2 instructions",
  61                                       [FeatureSSE41, FeaturePOPCNT]>;
  62 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  63                                       "Enable 3DNow! instructions",
  64                                       [FeatureMMX]>;
  65 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  66                                       "Enable 3DNow! Athlon instructions",
  67                                       [Feature3DNow]>;
  68 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  69 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  70 // without disabling 64-bit mode.
  71 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  72                                       "Support 64-bit instructions",
  73                                       [FeatureCMOV]>;
  74 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
  75                                       "64-bit with cmpxchg16b",
  76                                       [Feature64Bit]>;
  77 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  78                                        "Bit testing of memory is slow">;
  79 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  80                                         "IsUAMemFast", "true",
  81                                         "Fast unaligned memory access">;
  82 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  83                                       "Support SSE 4a instructions",
  84                                       [FeaturePOPCNT]>;
  85
  86 def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
  87                                       "Enable AVX instructions">;
  88 def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",
  89                                "Enable carry-less multiplication instructions">;
  90 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
  91                                      "Enable three-operand fused multiple-add">;
  92 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  93                                       "Enable four-operand fused multiple-add">;
  94 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
  95                                           "HasVectorUAMem", "true",
  96                  "Allow unaligned memory operands on vector/SIMD instructions">;
  97 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
  98                                       "Enable AES instructions">;
  99 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 100                                       "Support MOVBE instruction">;
 101 def FeatureRDRAND  : SubtargetFeature<"rdrand", "HasRDRAND", "true",
 102                                       "Support RDRAND instruction">;
 103 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 104                        "Support 16-bit floating point conversion instructions">;
 105
 106 //===----------------------------------------------------------------------===//
 107 // X86 processors supported.
 108 //===----------------------------------------------------------------------===//
 109
 110 class Proc<string Name, list<SubtargetFeature> Features>
 111  : Processor<Name, NoItineraries, Features>;
 112
 113 def : Proc<"generic",         []>;
 114 def : Proc<"i386",            []>;
 115 def : Proc<"i486",            []>;
 116 def : Proc<"i586",            []>;
 117 def : Proc<"pentium",         []>;
 118 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 119 def : Proc<"i686",            []>;
 120 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 121 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 122 def : Proc<"pentium3",        [FeatureSSE1]>;
 123 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 124 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 125 def : Proc<"pentium4",        [FeatureSSE2]>;
 126 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 127 def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
 128 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
 129 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
 130 def : Proc<"nocona",          [FeatureSSE3, FeatureCMPXCHG16B,
 131                                FeatureSlowBTMem]>;
 132 def : Proc<"core2",           [FeatureSSSE3, FeatureCMPXCHG16B,
 133                                FeatureSlowBTMem]>;
 134 def : Proc<"penryn",          [FeatureSSE41, FeatureCMPXCHG16B,
 135                                FeatureSlowBTMem]>;
 136 def : Proc<"atom",            [FeatureSSE3,  FeatureCMPXCHG16B,
 137                                FeatureSlowBTMem]>;
 138 // "Arrandale" along with corei3 and corei5
 139 def : Proc<"corei7",          [FeatureSSE42, FeatureCMPXCHG16B,
 140                                FeatureSlowBTMem, FeatureFastUAMem, FeatureAES]>;
 141 def : Proc<"nehalem",         [FeatureSSE42,  FeatureCMPXCHG16B,
 142                                FeatureSlowBTMem, FeatureFastUAMem]>;
 143 // Westmere is a similar machine to nehalem with some additional features.
 144 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 145 def : Proc<"westmere",        [FeatureSSE42, FeatureCMPXCHG16B,
 146                                FeatureSlowBTMem, FeatureFastUAMem, FeatureAES,
 147                                FeatureCLMUL]>;
 148 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 149 // rather than a superset.
 150 // FIXME: Disabling AVX for now since it's not ready.
 151 def : Proc<"corei7-avx",      [FeatureSSE42, FeatureCMPXCHG16B,
 152                                FeatureAES, FeatureCLMUL]>;
 153
 154 def : Proc<"k6",              [FeatureMMX]>;
 155 def : Proc<"k6-2",            [Feature3DNow]>;
 156 def : Proc<"k6-3",            [Feature3DNow]>;
 157 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem]>;
 158 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem]>;
 159 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 160 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 161 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 162 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 163                                FeatureSlowBTMem]>;
 164 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 165                                FeatureSlowBTMem]>;
 166 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 167                                FeatureSlowBTMem]>;
 168 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 169                                FeatureSlowBTMem]>;
 170 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 171                                FeatureSlowBTMem]>;
 172 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 173                                FeatureSlowBTMem]>;
 174 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 175                                FeatureSlowBTMem]>;
 176 def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
 177                                Feature3DNowA, FeatureCMPXCHG16B,
 178                                FeatureSlowBTMem]>;
 179 def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
 180                                Feature3DNowA, FeatureCMPXCHG16B,
 181                                FeatureSlowBTMem]>;
 182 def : Proc<"istanbul",        [Feature3DNowA, FeatureCMPXCHG16B,
 183                                FeatureSSE4A, Feature3DNowA]>;
 184 def : Proc<"shanghai",        [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A,
 185                                Feature3DNowA]>;
 186
 187 def : Proc<"winchip-c6",      [FeatureMMX]>;
 188 def : Proc<"winchip2",        [Feature3DNow]>;
 189 def : Proc<"c3",              [Feature3DNow]>;
 190 def : Proc<"c3-2",            [FeatureSSE1]>;
 191
 192 //===----------------------------------------------------------------------===//
 193 // Register File Description
 194 //===----------------------------------------------------------------------===//
 195
 196 include "X86RegisterInfo.td"
 197
 198 //===----------------------------------------------------------------------===//
 199 // Instruction Descriptions
 200 //===----------------------------------------------------------------------===//
 201
 202 include "X86InstrInfo.td"
 203
 204 def X86InstrInfo : InstrInfo;
 205
 206 //===----------------------------------------------------------------------===//
 207 // Calling Conventions
 208 //===----------------------------------------------------------------------===//
 209
 210 include "X86CallingConv.td"
 211
 212
 213 //===----------------------------------------------------------------------===//
 214 // Assembly Parser
 215 //===----------------------------------------------------------------------===//
 216
 217 // Currently the X86 assembly parser only supports ATT syntax.
 218 def ATTAsmParser : AsmParser {
 219   string AsmParserClassName = "ATTAsmParser";
 220   int Variant = 0;
 221
 222   // Discard comments in assembly strings.
 223   string CommentDelimiter = "#";
 224
 225   // Recognize hard coded registers.
 226   string RegisterPrefix = "%";
 227 }
 228
 229 //===----------------------------------------------------------------------===//
 230 // Assembly Printers
 231 //===----------------------------------------------------------------------===//
 232
 233 // The X86 target supports two different syntaxes for emitting machine code.
 234 // This is controlled by the -x86-asm-syntax={att|intel}
 235 def ATTAsmWriter : AsmWriter {
 236   string AsmWriterClassName  = "ATTInstPrinter";
 237   int Variant = 0;
 238   bit isMCAsmWriter = 1;
 239 }
 240 def IntelAsmWriter : AsmWriter {
 241   string AsmWriterClassName  = "IntelInstPrinter";
 242   int Variant = 1;
 243   bit isMCAsmWriter = 1;
 244 }
 245
 246 def X86 : Target {
 247   // Information about the instructions...
 248   let InstructionSet = X86InstrInfo;
 249
 250   let AssemblyParsers = [ATTAsmParser];
 251
 252   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 253 }