7bbb2b190337e23d486c49fd9affdeb04390a202
[oota-llvm.git] / lib / Target / X86 / X86.td
1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
12 //
13 //===----------------------------------------------------------------------===//
14
15 // Get the target-independent interfaces which we are implementing...
16 //
17 include "llvm/Target/Target.td"
18
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state.
21 //
22
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24                                   "64-bit mode (x86_64)">;
25
26 //===----------------------------------------------------------------------===//
27 // X86 Subtarget features.
28 //===----------------------------------------------------------------------===//
29
30 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
31                                       "Enable conditional move instructions">;
32
33 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
34                                        "Support POPCNT instruction">;
35
36
37 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
38                                       "Enable MMX instructions">;
39 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
40                                       "Enable SSE instructions",
41                                       // SSE codegen depends on cmovs, and all
42                                       // SSE1+ processors support them.
43                                       [FeatureMMX, FeatureCMOV]>;
44 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
45                                       "Enable SSE2 instructions",
46                                       [FeatureSSE1]>;
47 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48                                       "Enable SSE3 instructions",
49                                       [FeatureSSE2]>;
50 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
51                                       "Enable SSSE3 instructions",
52                                       [FeatureSSE3]>;
53 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
54                                       "Enable SSE 4.1 instructions",
55                                       [FeatureSSSE3]>;
56 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
57                                       "Enable SSE 4.2 instructions",
58                                       [FeatureSSE41]>;
59 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
60                                       "Enable 3DNow! instructions",
61                                       [FeatureMMX]>;
62 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
63                                       "Enable 3DNow! Athlon instructions",
64                                       [Feature3DNow]>;
65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
67 // without disabling 64-bit mode.
68 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
69                                       "Support 64-bit instructions",
70                                       [FeatureCMOV]>;
71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
72                                       "64-bit with cmpxchg16b",
73                                       [Feature64Bit]>;
74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
75                                        "Bit testing of memory is slow">;
76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
77                                         "IsUAMemFast", "true",
78                                         "Fast unaligned memory access">;
79 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
80                                       "Support SSE 4a instructions",
81                                       [FeatureSSE3]>;
82
83 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
84                                       "Enable AVX instructions",
85                                       [FeatureSSE42]>;
86 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
87                                       "Enable AVX2 instructions",
88                                       [FeatureAVX]>;
89 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
90                          "Enable packed carry-less multiplication instructions",
91                                [FeatureSSE2]>;
92 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
93                                       "Enable three-operand fused multiple-add",
94                                       [FeatureAVX]>;
95 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
96                                       "Enable four-operand fused multiple-add",
97                                       [FeatureAVX, FeatureSSE4A]>;
98 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
99                                       "Enable XOP instructions",
100                                       [FeatureAVX, FeatureSSE4A]>;
101 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
102                                           "HasVectorUAMem", "true",
103                  "Allow unaligned memory operands on vector/SIMD instructions">;
104 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
105                                       "Enable AES instructions",
106                                       [FeatureSSE2]>;
107 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
108                                       "Support MOVBE instruction">;
109 def FeatureRDRAND  : SubtargetFeature<"rdrand", "HasRDRAND", "true",
110                                       "Support RDRAND instruction">;
111 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
112                        "Support 16-bit floating point conversion instructions">;
113 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
114                                        "Support FS/GS Base instructions">;
115 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
116                                       "Support LZCNT instruction">;
117 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
118                                       "Support BMI instructions">;
119 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
120                                       "Support BMI2 instructions">;
121 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
122                                      "Use LEA for adjusting the stack pointer">;
123
124 //===----------------------------------------------------------------------===//
125 // X86 processors supported.
126 //===----------------------------------------------------------------------===//
127
128 include "X86Schedule.td"
129
130 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
131                     "Intel Atom processors">;
132
133 class Proc<string Name, list<SubtargetFeature> Features>
134  : Processor<Name, GenericItineraries, Features>;
135
136 class AtomProc<string Name, list<SubtargetFeature> Features>
137  : Processor<Name, AtomItineraries, Features>;
138
139 def : Proc<"generic",         []>;
140 def : Proc<"i386",            []>;
141 def : Proc<"i486",            []>;
142 def : Proc<"i586",            []>;
143 def : Proc<"pentium",         []>;
144 def : Proc<"pentium-mmx",     [FeatureMMX]>;
145 def : Proc<"i686",            []>;
146 def : Proc<"pentiumpro",      [FeatureCMOV]>;
147 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
148 def : Proc<"pentium3",        [FeatureSSE1]>;
149 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
150 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
151 def : Proc<"pentium4",        [FeatureSSE2]>;
152 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
153 def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
154 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
155 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
156 def : Proc<"nocona",          [FeatureSSE3, FeatureCMPXCHG16B,
157                                FeatureSlowBTMem]>;
158 def : Proc<"core2",           [FeatureSSSE3, FeatureCMPXCHG16B,
159                                FeatureSlowBTMem]>;
160 def : Proc<"penryn",          [FeatureSSE41, FeatureCMPXCHG16B,
161                                FeatureSlowBTMem]>;
162 def : AtomProc<"atom",        [ProcIntelAtom, FeatureSSE3, FeatureCMPXCHG16B,
163                                FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP]>;
164 // "Arrandale" along with corei3 and corei5
165 def : Proc<"corei7",          [FeatureSSE42, FeatureCMPXCHG16B,
166                                FeatureSlowBTMem, FeatureFastUAMem,
167                                FeaturePOPCNT, FeatureAES]>;
168 def : Proc<"nehalem",         [FeatureSSE42,  FeatureCMPXCHG16B,
169                                FeatureSlowBTMem, FeatureFastUAMem,
170                                FeaturePOPCNT]>;
171 // Westmere is a similar machine to nehalem with some additional features.
172 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
173 def : Proc<"westmere",        [FeatureSSE42, FeatureCMPXCHG16B,
174                                FeatureSlowBTMem, FeatureFastUAMem,
175                                FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
176 // Sandy Bridge
177 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
178 // rather than a superset.
179 def : Proc<"corei7-avx",      [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,
180                                FeatureAES, FeaturePCLMUL]>;
181 // Ivy Bridge
182 def : Proc<"core-avx-i",      [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,
183                                FeatureAES, FeaturePCLMUL,
184                                FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
185
186 // Haswell
187 def : Proc<"core-avx2",       [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT,
188                                FeatureAES, FeaturePCLMUL, FeatureRDRAND,
189                                FeatureF16C, FeatureFSGSBase,
190                                FeatureMOVBE, FeatureLZCNT, FeatureBMI,
191                                FeatureBMI2, FeatureFMA3]>;
192
193 def : Proc<"k6",              [FeatureMMX]>;
194 def : Proc<"k6-2",            [Feature3DNow]>;
195 def : Proc<"k6-3",            [Feature3DNow]>;
196 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem]>;
197 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem]>;
198 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
199 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
200 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
201 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
202                                FeatureSlowBTMem]>;
203 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
204                                FeatureSlowBTMem]>;
205 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
206                                FeatureSlowBTMem]>;
207 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
208                                FeatureSlowBTMem]>;
209 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
210                                FeatureSlowBTMem]>;
211 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
212                                FeatureSlowBTMem]>;
213 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
214                                FeatureSlowBTMem]>;
215 def : Proc<"amdfam10",        [FeatureSSE4A,
216                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
217                                FeaturePOPCNT, FeatureSlowBTMem]>;
218 // Bobcat
219 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
220                                FeatureLZCNT, FeaturePOPCNT]>;
221 // Bulldozer
222 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
223                                FeatureAES, FeaturePCLMUL,
224                                FeatureLZCNT, FeaturePOPCNT]>;
225 // Enhanced Bulldozer
226 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
227                                FeatureAES, FeaturePCLMUL,
228                                FeatureF16C, FeatureLZCNT,
229                                FeaturePOPCNT, FeatureBMI]>;
230
231 def : Proc<"winchip-c6",      [FeatureMMX]>;
232 def : Proc<"winchip2",        [Feature3DNow]>;
233 def : Proc<"c3",              [Feature3DNow]>;
234 def : Proc<"c3-2",            [FeatureSSE1]>;
235
236 //===----------------------------------------------------------------------===//
237 // Register File Description
238 //===----------------------------------------------------------------------===//
239
240 include "X86RegisterInfo.td"
241
242 //===----------------------------------------------------------------------===//
243 // Instruction Descriptions
244 //===----------------------------------------------------------------------===//
245
246 include "X86InstrInfo.td"
247
248 def X86InstrInfo : InstrInfo;
249
250 //===----------------------------------------------------------------------===//
251 // Calling Conventions
252 //===----------------------------------------------------------------------===//
253
254 include "X86CallingConv.td"
255
256
257 //===----------------------------------------------------------------------===//
258 // Assembly Parser
259 //===----------------------------------------------------------------------===//
260
261 def ATTAsmParser : AsmParser {
262   string AsmParserClassName = "AsmParser";
263 }
264
265 def ATTAsmParserVariant : AsmParserVariant {
266   int Variant = 0;
267
268   // Discard comments in assembly strings.
269   string CommentDelimiter = "#";
270
271   // Recognize hard coded registers.
272   string RegisterPrefix = "%";
273 }
274
275 def IntelAsmParserVariant : AsmParserVariant {
276   int Variant = 1;
277
278   // Discard comments in assembly strings.
279   string CommentDelimiter = ";";
280
281   // Recognize hard coded registers.
282   string RegisterPrefix = "";
283 }
284
285 //===----------------------------------------------------------------------===//
286 // Assembly Printers
287 //===----------------------------------------------------------------------===//
288
289 // The X86 target supports two different syntaxes for emitting machine code.
290 // This is controlled by the -x86-asm-syntax={att|intel}
291 def ATTAsmWriter : AsmWriter {
292   string AsmWriterClassName  = "ATTInstPrinter";
293   int Variant = 0;
294   bit isMCAsmWriter = 1;
295 }
296 def IntelAsmWriter : AsmWriter {
297   string AsmWriterClassName  = "IntelInstPrinter";
298   int Variant = 1;
299   bit isMCAsmWriter = 1;
300 }
301
302 def X86 : Target {
303   // Information about the instructions...
304   let InstructionSet = X86InstrInfo;
305   let AssemblyParsers = [ATTAsmParser];
306   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
307   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
308 }