1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
5 Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
6 Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
7 X86, & make the dag combiner produce it when needed. This will eliminate one
8 imul from the code generated for:
10 long long test(long long X, long long Y) { return X*Y; }
12 by using the EAX result from the mul. We should add a similar node for
17 long long test(int X, int Y) { return (long long)X*Y; }
19 ... which should only be one imul instruction.
21 //===---------------------------------------------------------------------===//
23 This should be one DIV/IDIV instruction, not a libcall:
25 unsigned test(unsigned long long X, unsigned Y) {
29 This can be done trivially with a custom legalizer. What about overflow
30 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
32 //===---------------------------------------------------------------------===//
34 Improvements to the multiply -> shift/add algorithm:
35 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
37 //===---------------------------------------------------------------------===//
39 Improve code like this (occurs fairly frequently, e.g. in LLVM):
40 long long foo(int x) { return 1LL << x; }
42 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
43 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
44 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
46 Another useful one would be ~0ULL >> X and ~0ULL << X.
48 One better solution for 1LL << x is:
57 But that requires good 8-bit subreg support.
61 //===---------------------------------------------------------------------===//
64 _Bool f(_Bool a) { return a!=1; }
71 //===---------------------------------------------------------------------===//
75 1. Dynamic programming based approach when compile time if not an
77 2. Code duplication (addressing mode) during isel.
78 3. Other ideas from "Register-Sensitive Selection, Duplication, and
79 Sequencing of Instructions".
80 4. Scheduling for reduced register pressure. E.g. "Minimum Register
81 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
82 and other related papers.
83 http://citeseer.ist.psu.edu/govindarajan01minimum.html
85 //===---------------------------------------------------------------------===//
87 Should we promote i16 to i32 to avoid partial register update stalls?
89 //===---------------------------------------------------------------------===//
91 Leave any_extend as pseudo instruction and hint to register
92 allocator. Delay codegen until post register allocation.
94 //===---------------------------------------------------------------------===//
96 Count leading zeros and count trailing zeros:
98 int clz(int X) { return __builtin_clz(X); }
99 int ctz(int X) { return __builtin_ctz(X); }
101 $ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
103 bsr %eax, DWORD PTR [%esp+4]
107 bsf %eax, DWORD PTR [%esp+4]
110 however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
113 //===---------------------------------------------------------------------===//
115 Use push/pop instructions in prolog/epilog sequences instead of stores off
116 ESP (certain code size win, perf win on some [which?] processors).
117 Also, it appears icc use push for parameter passing. Need to investigate.
119 //===---------------------------------------------------------------------===//
121 Only use inc/neg/not instructions on processors where they are faster than
122 add/sub/xor. They are slower on the P4 due to only updating some processor
125 //===---------------------------------------------------------------------===//
127 The instruction selector sometimes misses folding a load into a compare. The
128 pattern is written as (cmp reg, (load p)). Because the compare isn't
129 commutative, it is not matched with the load on both sides. The dag combiner
130 should be made smart enough to cannonicalize the load into the RHS of a compare
131 when it can invert the result of the compare for free.
133 //===---------------------------------------------------------------------===//
135 How about intrinsics? An example is:
136 *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
139 pmuludq (%eax), %xmm0
144 The transformation probably requires a X86 specific pass or a DAG combiner
145 target specific hook.
147 //===---------------------------------------------------------------------===//
149 In many cases, LLVM generates code like this:
158 on some processors (which ones?), it is more efficient to do this:
167 Doing this correctly is tricky though, as the xor clobbers the flags.
169 //===---------------------------------------------------------------------===//
171 We should generate bts/btr/etc instructions on targets where they are cheap or
172 when codesize is important. e.g., for:
174 void setbit(int *target, int bit) {
175 *target |= (1 << bit);
177 void clearbit(int *target, int bit) {
178 *target &= ~(1 << bit);
181 //===---------------------------------------------------------------------===//
183 Instead of the following for memset char*, 1, 10:
185 movl $16843009, 4(%edx)
186 movl $16843009, (%edx)
189 It might be better to generate
196 when we can spare a register. It reduces code size.
198 //===---------------------------------------------------------------------===//
200 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
217 GCC knows several different ways to codegen it, one of which is this:
227 which is probably slower, but it's interesting at least :)
229 //===---------------------------------------------------------------------===//
231 Should generate min/max for stuff like:
233 void minf(float a, float b, float *X) {
237 Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN
238 and ISD::FMAX node types?
240 //===---------------------------------------------------------------------===//
242 The first BB of this code:
246 %V = call bool %foo()
247 br bool %V, label %T, label %F
264 It would be better to emit "cmp %al, 1" than a xor and test.
266 //===---------------------------------------------------------------------===//
268 Enable X86InstrInfo::convertToThreeAddress().
270 //===---------------------------------------------------------------------===//
272 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
273 We should leave these as libcalls for everything over a much lower threshold,
274 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
275 stores, TLB preheating, etc)
277 //===---------------------------------------------------------------------===//
279 Optimize this into something reasonable:
280 x * copysign(1.0, y) * copysign(1.0, z)
282 //===---------------------------------------------------------------------===//
284 Optimize copysign(x, *y) to use an integer load from y.
286 //===---------------------------------------------------------------------===//
288 %X = weak global int 0
291 %N = cast int %N to uint
292 %tmp.24 = setgt int %N, 0
293 br bool %tmp.24, label %no_exit, label %return
296 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
297 %i.0.0 = cast uint %indvar to int
298 volatile store int %i.0.0, int* %X
299 %indvar.next = add uint %indvar, 1
300 %exitcond = seteq uint %indvar.next, %N
301 br bool %exitcond, label %return, label %no_exit
315 jl LBB_foo_4 # return
316 LBB_foo_1: # no_exit.preheader
319 movl L_X$non_lazy_ptr, %edx
323 jne LBB_foo_2 # no_exit
324 LBB_foo_3: # return.loopexit
328 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
329 remateralization is implemented. This can be accomplished with 1) a target
330 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
332 //===---------------------------------------------------------------------===//
334 The following tests perform worse with LSR:
336 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
338 //===---------------------------------------------------------------------===//
340 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
343 //===---------------------------------------------------------------------===//
351 Obviously it would have been better for the first mov (or any op) to store
352 directly %esp[0] if there are no other uses.
354 //===---------------------------------------------------------------------===//
356 Adding to the list of cmp / test poor codegen issues:
358 int test(__m128 *A, __m128 *B) {
359 if (_mm_comige_ss(*A, *B))
379 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
380 are a number of issues. 1) We are introducing a setcc between the result of the
381 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
382 so a any extend (which becomes a zero extend) is added.
384 We probably need some kind of target DAG combine hook to fix this.
386 //===---------------------------------------------------------------------===//
388 We generate significantly worse code for this than GCC:
389 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
390 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
392 There is also one case we do worse on PPC.
394 //===---------------------------------------------------------------------===//
396 If shorter, we should use things like:
401 The former can also be used when the two-addressy nature of the 'and' would
402 require a copy to be inserted (in X86InstrInfo::convertToThreeAddress).
404 //===---------------------------------------------------------------------===//
408 char foo(int x) { return x; }
416 SIGN_EXTEND_INREG can be implemented as (sext (trunc)) to take advantage of
419 //===---------------------------------------------------------------------===//
423 typedef struct pair { float A, B; } pair;
424 void pairtest(pair P, float *FP) {
428 We currently generate this code with llvmgcc4:
443 we should be able to generate:
451 The issue is that llvmgcc4 is forcing the struct to memory, then passing it as
452 integer chunks. It does this so that structs like {short,short} are passed in
453 a single 32-bit integer stack slot. We should handle the safe cases above much
454 nicer, while still handling the hard cases.
456 //===---------------------------------------------------------------------===//
458 Another instruction selector deficiency:
461 %tmp = load int (int)** %foo
462 %tmp = tail call int %tmp( int 3 )
468 movl L_foo$non_lazy_ptr, %eax
474 The current isel scheme will not allow the load to be folded in the call since
475 the load's chain result is read by the callseq_start.
477 //===---------------------------------------------------------------------===//
479 Don't forget to find a way to squash noop truncates in the JIT environment.
481 //===---------------------------------------------------------------------===//
483 Implement anyext in the same manner as truncate that would allow them to be
486 //===---------------------------------------------------------------------===//
488 How about implementing truncate / anyext as a property of machine instruction
489 operand? i.e. Print as 32-bit super-class register / 16-bit sub-class register.
490 Do this for the cases where a truncate / anyext is guaranteed to be eliminated.
491 For IA32 that is truncate from 32 to 16 and anyext from 16 to 32.
493 //===---------------------------------------------------------------------===//
503 imull $3, 4(%esp), %eax
505 Perhaps this is what we really should generate is? Is imull three or four
506 cycles? Note: ICC generates this:
508 leal (%eax,%eax,2), %eax
510 The current instruction priority is based on pattern complexity. The former is
511 more "complex" because it folds a load so the latter will not be emitted.
513 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
514 should always try to match LEA first since the LEA matching code does some
515 estimate to determine whether the match is profitable.
517 However, if we care more about code size, then imull is better. It's two bytes
518 shorter than movl + leal.
520 //===---------------------------------------------------------------------===//
522 Implement CTTZ, CTLZ with bsf and bsr.
524 //===---------------------------------------------------------------------===//
526 It appears gcc place string data with linkonce linkage in
527 .section __TEXT,__const_coal,coalesced instead of
528 .section __DATA,__const_coal,coalesced.
529 Take a look at darwin.h, there are other Darwin assembler directives that we
532 //===---------------------------------------------------------------------===//
534 We should handle __attribute__ ((__visibility__ ("hidden"))).
536 //===---------------------------------------------------------------------===//
538 int %foo(int* %a, int %t) {
542 cond_true: ; preds = %cond_true, %entry
543 %x.0.0 = phi int [ 0, %entry ], [ %tmp9, %cond_true ] ; <int> [#uses=3]
544 %t_addr.0.0 = phi int [ %t, %entry ], [ %tmp7, %cond_true ] ; <int> [#uses=1]
545 %tmp2 = getelementptr int* %a, int %x.0.0 ; <int*> [#uses=1]
546 %tmp3 = load int* %tmp2 ; <int> [#uses=1]
547 %tmp5 = add int %t_addr.0.0, %x.0.0 ; <int> [#uses=1]
548 %tmp7 = add int %tmp5, %tmp3 ; <int> [#uses=2]
549 %tmp9 = add int %x.0.0, 1 ; <int> [#uses=2]
550 %tmp = setgt int %tmp9, 39 ; <bool> [#uses=1]
551 br bool %tmp, label %bb12, label %cond_true
553 bb12: ; preds = %cond_true
557 is pessimized by -loop-reduce and -indvars
559 //===---------------------------------------------------------------------===//
561 Use cpuid to auto-detect CPU features such as SSE, SSE2, and SSE3.
563 //===---------------------------------------------------------------------===//
565 u32 to float conversion improvement:
567 float uint32_2_float( unsigned u ) {
568 float fl = (int) (u & 0xffff);
569 float fh = (int) (u >> 16);
574 00000000 subl $0x04,%esp
575 00000003 movl 0x08(%esp,1),%eax
576 00000007 movl %eax,%ecx
577 00000009 shrl $0x10,%ecx
578 0000000c cvtsi2ss %ecx,%xmm0
579 00000010 andl $0x0000ffff,%eax
580 00000015 cvtsi2ss %eax,%xmm1
581 00000019 mulss 0x00000078,%xmm0
582 00000021 addss %xmm1,%xmm0
583 00000025 movss %xmm0,(%esp,1)
584 0000002a flds (%esp,1)
585 0000002d addl $0x04,%esp
588 //===---------------------------------------------------------------------===//
590 When using fastcc abi, align stack slot of argument of type double on 8 byte
591 boundary to improve performance.
593 //===---------------------------------------------------------------------===//
597 int f(int a, int b) {
598 if (a == 4 || a == 6)
610 If we aren't going to do this, we should lower the switch better. We compile
622 jmp LBB1_2 #UnifiedReturnBlock
625 jne LBB1_2 #UnifiedReturnBlock
629 LBB1_2: #UnifiedReturnBlock
632 In the code above, the 'if' is turned into a 'switch' at the mid-level. It looks
633 like the 'lower to branches' mode could be improved a little here. In particular,
634 the fall-through to LBB1_3 doesn't need a branch. It would also be nice to
635 eliminate the redundant "cmp 6", maybe by lowering to a linear sequence of
636 compares if there are below a certain number of cases (instead of a binary sequence)?
638 //===---------------------------------------------------------------------===//
641 int %test(ulong *%tmp) {
642 %tmp = load ulong* %tmp ; <ulong> [#uses=1]
643 %tmp.mask = shr ulong %tmp, ubyte 50 ; <ulong> [#uses=1]
644 %tmp.mask = cast ulong %tmp.mask to ubyte ; <ubyte> [#uses=1]
645 %tmp2 = and ubyte %tmp.mask, 3 ; <ubyte> [#uses=1]
646 %tmp2 = cast ubyte %tmp2 to int ; <int> [#uses=1]
665 # TRUNCATE movb %al, %al
670 This saves a movzbl, and saves a truncate if it doesn't get coallesced right.
671 This is a simple DAGCombine to propagate the zext through the and.
673 //===---------------------------------------------------------------------===//
675 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
676 simplifications for integer "x cmp y ? a : b". For example, instead of:
679 void f(int X, int Y) {
705 //===---------------------------------------------------------------------===//