1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "InstPrinter/X86IntelInstPrinter.h"
17 #include "X86MCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/Host.h"
28 #include "llvm/Support/TargetRegistry.h"
30 #define GET_REGINFO_MC_DESC
31 #include "X86GenRegisterInfo.inc"
33 #define GET_INSTRINFO_MC_DESC
34 #include "X86GenInstrInfo.inc"
36 #define GET_SUBTARGETINFO_MC_DESC
37 #include "X86GenSubtargetInfo.inc"
46 std::string X86_MC::ParseX86Triple(StringRef TT) {
49 if (TheTriple.getArch() == Triple::x86_64)
50 FS = "+64bit-mode,-32bit-mode,-16bit-mode";
51 else if (TheTriple.getEnvironment() != Triple::CODE16)
52 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
54 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
59 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
60 /// specified arguments. If we can't run cpuid on the host, return true.
61 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
62 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
63 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
65 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
66 asm ("movq\t%%rbx, %%rsi\n\t"
68 "xchgq\t%%rbx, %%rsi\n\t"
75 #elif defined(_MSC_VER)
77 __cpuid(registers, value);
86 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
88 asm ("movl\t%%ebx, %%esi\n\t"
90 "xchgl\t%%ebx, %%esi\n\t"
97 #elif defined(_MSC_VER)
102 mov dword ptr [esi],eax
104 mov dword ptr [esi],ebx
106 mov dword ptr [esi],ecx
108 mov dword ptr [esi],edx
119 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
120 /// 4 values in the specified arguments. If we can't run cpuid on the host,
122 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
123 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
124 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
125 #if defined(__GNUC__)
126 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
127 asm ("movq\t%%rbx, %%rsi\n\t"
129 "xchgq\t%%rbx, %%rsi\n\t"
137 #elif defined(_MSC_VER)
138 // __cpuidex was added in MSVC++ 9.0 SP1
139 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
141 __cpuidex(registers, value, subleaf);
142 *rEAX = registers[0];
143 *rEBX = registers[1];
144 *rECX = registers[2];
145 *rEDX = registers[3];
153 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
154 #if defined(__GNUC__)
155 asm ("movl\t%%ebx, %%esi\n\t"
157 "xchgl\t%%ebx, %%esi\n\t"
165 #elif defined(_MSC_VER)
171 mov dword ptr [esi],eax
173 mov dword ptr [esi],ebx
175 mov dword ptr [esi],ecx
177 mov dword ptr [esi],edx
188 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
190 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
191 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
192 if (Family == 6 || Family == 0xf) {
194 // Examine extended family ID if family ID is F.
195 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
196 // Examine extended model ID if family ID is 6 or F.
197 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
201 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
202 Triple TheTriple(TT);
203 if (TheTriple.getArch() == Triple::x86_64)
204 return DWARFFlavour::X86_64;
206 if (TheTriple.isOSDarwin())
207 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
208 if (TheTriple.getOS() == Triple::MinGW32 ||
209 TheTriple.getOS() == Triple::Cygwin)
210 // Unsupported by now, just quick fallback
211 return DWARFFlavour::X86_32_Generic;
212 return DWARFFlavour::X86_32_Generic;
215 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
216 // FIXME: TableGen these.
217 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
218 unsigned SEH = MRI->getEncodingValue(Reg);
219 MRI->mapLLVMRegToSEHReg(Reg, SEH);
223 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
225 std::string ArchFS = X86_MC::ParseX86Triple(TT);
228 ArchFS = ArchFS + "," + FS.str();
233 std::string CPUName = CPU;
234 if (CPUName.empty()) {
235 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
236 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
237 CPUName = sys::getHostCPUName();
243 MCSubtargetInfo *X = new MCSubtargetInfo();
244 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
248 static MCInstrInfo *createX86MCInstrInfo() {
249 MCInstrInfo *X = new MCInstrInfo();
250 InitX86MCInstrInfo(X);
254 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
255 Triple TheTriple(TT);
256 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
257 ? X86::RIP // Should have dwarf #16.
258 : X86::EIP; // Should have dwarf #8.
260 MCRegisterInfo *X = new MCRegisterInfo();
261 InitX86MCRegisterInfo(X, RA,
262 X86_MC::getDwarfRegFlavour(TT, false),
263 X86_MC::getDwarfRegFlavour(TT, true),
265 X86_MC::InitLLVM2SEHRegisterMapping(X);
269 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
270 Triple TheTriple(TT);
271 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
274 if (TheTriple.isOSBinFormatMachO()) {
276 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
278 MAI = new X86MCAsmInfoDarwin(TheTriple);
279 } else if (TheTriple.getEnvironment() == Triple::ELF) {
280 // Force the use of an ELF container.
281 MAI = new X86ELFMCAsmInfo(TheTriple);
282 } else if (TheTriple.getOS() == Triple::Win32) {
283 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
284 } else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) {
285 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
287 // The default is ELF.
288 MAI = new X86ELFMCAsmInfo(TheTriple);
291 // Initialize initial frame state.
292 // Calculate amount of bytes used for return address storing
293 int stackGrowth = is64Bit ? -8 : -4;
295 // Initial state of the frame pointer is esp+stackGrowth.
296 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
297 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
298 0, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
299 MAI->addInitialFrameState(Inst);
301 // Add return address to move list
302 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
303 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
304 0, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
305 MAI->addInitialFrameState(Inst2);
310 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
312 CodeGenOpt::Level OL) {
313 MCCodeGenInfo *X = new MCCodeGenInfo();
316 bool is64Bit = T.getArch() == Triple::x86_64;
318 if (RM == Reloc::Default) {
319 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
320 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
321 // use static relocation model by default.
322 if (T.isOSDarwin()) {
326 RM = Reloc::DynamicNoPIC;
327 } else if (T.isOSWindows() && is64Bit)
333 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
334 // is defined as a model for code which may be used in static or dynamic
335 // executables but not necessarily a shared library. On X86-32 we just
336 // compile in -static mode, in x86-64 we use PIC.
337 if (RM == Reloc::DynamicNoPIC) {
340 else if (!T.isOSDarwin())
344 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
345 // the Mach-O file format doesn't support it.
346 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
349 // For static codegen, if we're not already set, use Small codegen.
350 if (CM == CodeModel::Default)
351 CM = CodeModel::Small;
352 else if (CM == CodeModel::JITDefault)
353 // 64-bit JIT places everything in the same buffer except external funcs.
354 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
356 X->InitMCCodeGenInfo(RM, CM, OL);
360 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
361 MCContext &Ctx, MCAsmBackend &MAB,
363 MCCodeEmitter *_Emitter,
364 const MCSubtargetInfo &STI,
367 Triple TheTriple(TT);
369 if (TheTriple.isOSBinFormatMachO())
370 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
372 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
373 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
375 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
378 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
379 unsigned SyntaxVariant,
380 const MCAsmInfo &MAI,
381 const MCInstrInfo &MII,
382 const MCRegisterInfo &MRI,
383 const MCSubtargetInfo &STI) {
384 if (SyntaxVariant == 0)
385 return new X86ATTInstPrinter(MAI, MII, MRI);
386 if (SyntaxVariant == 1)
387 return new X86IntelInstPrinter(MAI, MII, MRI);
391 static MCRelocationInfo *createX86MCRelocationInfo(StringRef TT,
393 Triple TheTriple(TT);
394 if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
395 return createX86_64MachORelocationInfo(Ctx);
396 else if (TheTriple.isOSBinFormatELF())
397 return createX86_64ELFRelocationInfo(Ctx);
398 // Default to the stock relocation info.
399 return llvm::createMCRelocationInfo(TT, Ctx);
402 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
403 return new MCInstrAnalysis(Info);
406 // Force static initialization.
407 extern "C" void LLVMInitializeX86TargetMC() {
408 // Register the MC asm info.
409 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
410 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
412 // Register the MC codegen info.
413 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
414 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
416 // Register the MC instruction info.
417 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
418 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
420 // Register the MC register info.
421 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
422 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
424 // Register the MC subtarget info.
425 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
426 X86_MC::createX86MCSubtargetInfo);
427 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
428 X86_MC::createX86MCSubtargetInfo);
430 // Register the MC instruction analyzer.
431 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
432 createX86MCInstrAnalysis);
433 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
434 createX86MCInstrAnalysis);
436 // Register the code emitter.
437 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
438 createX86MCCodeEmitter);
439 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
440 createX86MCCodeEmitter);
442 // Register the asm backend.
443 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
444 createX86_32AsmBackend);
445 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
446 createX86_64AsmBackend);
448 // Register the object streamer.
449 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
451 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
454 // Register the MCInstPrinter.
455 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
456 createX86MCInstPrinter);
457 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
458 createX86MCInstPrinter);
460 // Register the MC relocation info.
461 TargetRegistry::RegisterMCRelocationInfo(TheX86_32Target,
462 createX86MCRelocationInfo);
463 TargetRegistry::RegisterMCRelocationInfo(TheX86_64Target,
464 createX86MCRelocationInfo);