1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "X86MCAsmInfo.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "InstPrinter/X86IntelInstPrinter.h"
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Target/TargetRegistry.h"
24 #include "llvm/ADT/Triple.h"
25 #include "llvm/Support/Host.h"
27 #define GET_REGINFO_MC_DESC
28 #include "X86GenRegisterInfo.inc"
30 #define GET_INSTRINFO_MC_DESC
31 #include "X86GenInstrInfo.inc"
33 #define GET_SUBTARGETINFO_MC_DESC
34 #include "X86GenSubtargetInfo.inc"
39 std::string X86_MC::ParseX86Triple(StringRef TT) {
41 if (TheTriple.getArch() == Triple::x86_64)
46 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
47 /// specified arguments. If we can't run cpuid on the host, return true.
48 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
49 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
50 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
52 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
53 asm ("movq\t%%rbx, %%rsi\n\t"
55 "xchgq\t%%rbx, %%rsi\n\t"
62 #elif defined(_MSC_VER)
64 __cpuid(registers, value);
71 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
73 asm ("movl\t%%ebx, %%esi\n\t"
75 "xchgl\t%%ebx, %%esi\n\t"
82 #elif defined(_MSC_VER)
87 mov dword ptr [esi],eax
89 mov dword ptr [esi],ebx
91 mov dword ptr [esi],ecx
93 mov dword ptr [esi],edx
101 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
103 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
104 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
105 if (Family == 6 || Family == 0xf) {
107 // Examine extended family ID if family ID is F.
108 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
109 // Examine extended model ID if family ID is 6 or F.
110 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
114 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
115 Triple TheTriple(TT);
116 if (TheTriple.getArch() == Triple::x86_64)
117 return DWARFFlavour::X86_64;
119 if (TheTriple.isOSDarwin())
120 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
121 if (TheTriple.getOS() == Triple::MinGW32 ||
122 TheTriple.getOS() == Triple::Cygwin)
123 // Unsupported by now, just quick fallback
124 return DWARFFlavour::X86_32_Generic;
125 return DWARFFlavour::X86_32_Generic;
128 /// getX86RegNum - This function maps LLVM register identifiers to their X86
129 /// specific numbering, which is used in various places encoding instructions.
130 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
132 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
133 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
134 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
135 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
136 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
138 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
140 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
142 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
145 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
147 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
149 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
151 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
153 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
155 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
157 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
159 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
162 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
163 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
164 return RegNo-X86::ST0;
166 case X86::XMM0: case X86::XMM8:
167 case X86::YMM0: case X86::YMM8: case X86::MM0:
169 case X86::XMM1: case X86::XMM9:
170 case X86::YMM1: case X86::YMM9: case X86::MM1:
172 case X86::XMM2: case X86::XMM10:
173 case X86::YMM2: case X86::YMM10: case X86::MM2:
175 case X86::XMM3: case X86::XMM11:
176 case X86::YMM3: case X86::YMM11: case X86::MM3:
178 case X86::XMM4: case X86::XMM12:
179 case X86::YMM4: case X86::YMM12: case X86::MM4:
181 case X86::XMM5: case X86::XMM13:
182 case X86::YMM5: case X86::YMM13: case X86::MM5:
184 case X86::XMM6: case X86::XMM14:
185 case X86::YMM6: case X86::YMM14: case X86::MM6:
187 case X86::XMM7: case X86::XMM15:
188 case X86::YMM7: case X86::YMM15: case X86::MM7:
191 case X86::ES: return 0;
192 case X86::CS: return 1;
193 case X86::SS: return 2;
194 case X86::DS: return 3;
195 case X86::FS: return 4;
196 case X86::GS: return 5;
198 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
199 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
200 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
201 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
202 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
203 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
204 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
205 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
207 // Pseudo index registers are equivalent to a "none"
208 // scaled index (See Intel Manual 2A, table 2-3)
214 assert((int(RegNo) > 0) && "Unknown physical register!");
219 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
220 // FIXME: TableGen these.
221 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
222 int SEH = X86_MC::getX86RegNum(Reg);
224 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
225 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
226 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
227 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
228 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
229 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
230 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
231 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
232 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
233 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
234 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
235 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
239 MRI->mapLLVMRegToSEHReg(Reg, SEH);
243 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
245 std::string ArchFS = X86_MC::ParseX86Triple(TT);
248 ArchFS = ArchFS + "," + FS.str();
253 std::string CPUName = CPU;
254 if (CPUName.empty()) {
255 #if defined (__x86_64__) || defined(__i386__)
256 CPUName = sys::getHostCPUName();
262 MCSubtargetInfo *X = new MCSubtargetInfo();
263 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
267 static MCInstrInfo *createX86MCInstrInfo() {
268 MCInstrInfo *X = new MCInstrInfo();
269 InitX86MCInstrInfo(X);
273 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
274 Triple TheTriple(TT);
275 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
276 ? X86::RIP // Should have dwarf #16.
277 : X86::EIP; // Should have dwarf #8.
279 MCRegisterInfo *X = new MCRegisterInfo();
280 InitX86MCRegisterInfo(X, RA,
281 X86_MC::getDwarfRegFlavour(TT, false),
282 X86_MC::getDwarfRegFlavour(TT, true));
283 X86_MC::InitLLVM2SEHRegisterMapping(X);
287 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
288 Triple TheTriple(TT);
289 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
292 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
294 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
296 MAI = new X86MCAsmInfoDarwin(TheTriple);
297 } else if (TheTriple.isOSWindows()) {
298 MAI = new X86MCAsmInfoCOFF(TheTriple);
300 MAI = new X86ELFMCAsmInfo(TheTriple);
303 // Initialize initial frame state.
304 // Calculate amount of bytes used for return address storing
305 int stackGrowth = is64Bit ? -8 : -4;
307 // Initial state of the frame pointer is esp+stackGrowth.
308 MachineLocation Dst(MachineLocation::VirtualFP);
309 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
310 MAI->addInitialFrameState(0, Dst, Src);
312 // Add return address to move list
313 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
314 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
315 MAI->addInitialFrameState(0, CSDst, CSSrc);
320 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
321 CodeModel::Model CM) {
322 MCCodeGenInfo *X = new MCCodeGenInfo();
325 bool is64Bit = T.getArch() == Triple::x86_64;
327 if (RM == Reloc::Default) {
328 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
329 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
330 // use static relocation model by default.
331 if (T.isOSDarwin()) {
335 RM = Reloc::DynamicNoPIC;
336 } else if (T.isOSWindows() && is64Bit)
342 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
343 // is defined as a model for code which may be used in static or dynamic
344 // executables but not necessarily a shared library. On X86-32 we just
345 // compile in -static mode, in x86-64 we use PIC.
346 if (RM == Reloc::DynamicNoPIC) {
349 else if (!T.isOSDarwin())
353 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
354 // the Mach-O file format doesn't support it.
355 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
358 // For static codegen, if we're not already set, use Small codegen.
359 if (CM == CodeModel::Default)
360 CM = CodeModel::Small;
361 else if (CM == CodeModel::JITDefault)
362 // 64-bit JIT places everything in the same buffer except external funcs.
363 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
365 X->InitMCCodeGenInfo(RM, CM);
369 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
370 MCContext &Ctx, MCAsmBackend &MAB,
372 MCCodeEmitter *_Emitter,
375 Triple TheTriple(TT);
377 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
378 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
380 if (TheTriple.isOSWindows())
381 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
383 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
386 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
387 unsigned SyntaxVariant,
388 const MCAsmInfo &MAI) {
389 if (SyntaxVariant == 0)
390 return new X86ATTInstPrinter(MAI);
391 if (SyntaxVariant == 1)
392 return new X86IntelInstPrinter(MAI);
396 // Force static initialization.
397 extern "C" void LLVMInitializeX86TargetMC() {
398 // Register the MC asm info.
399 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
400 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
402 // Register the MC codegen info.
403 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
404 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
406 // Register the MC instruction info.
407 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
408 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
410 // Register the MC register info.
411 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
412 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
414 // Register the MC subtarget info.
415 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
416 X86_MC::createX86MCSubtargetInfo);
417 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
418 X86_MC::createX86MCSubtargetInfo);
420 // Register the code emitter.
421 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
422 createX86MCCodeEmitter);
423 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
424 createX86MCCodeEmitter);
426 // Register the asm backend.
427 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
428 createX86_32AsmBackend);
429 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
430 createX86_64AsmBackend);
432 // Register the object streamer.
433 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
435 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
438 // Register the MCInstPrinter.
439 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
440 createX86MCInstPrinter);
441 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
442 createX86MCInstPrinter);