1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the X86 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
20 #include "X86MCTargetDesc.h"
21 #include "llvm/Support/DataTypes.h"
27 // Enums for memory operand decoding. Each memory operand is represented with
28 // a 5 operand sequence in the form:
29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
30 // These enums help decode this.
37 /// AddrSegmentReg - The operand # of the segment in the memory operand.
40 /// AddrNumOperands - Total number of operands in a memory reference.
43 } // end namespace X86;
46 /// X86II - This namespace holds all of the target specific flags that
47 /// instruction info tracks.
50 /// Target Operand Flag enum.
52 //===------------------------------------------------------------------===//
53 // X86 Specific MachineOperand flags.
57 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
59 /// SYMBOL_LABEL + [. - PICBASELABEL]
60 MO_GOT_ABSOLUTE_ADDRESS,
62 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
63 /// immediate should get the value of the symbol minus the PIC base label:
64 /// SYMBOL_LABEL - PICBASELABEL
67 /// MO_GOT - On a symbol operand this indicates that the immediate is the
68 /// offset to the GOT entry for the symbol name from the base of the GOT.
70 /// See the X86-64 ELF ABI supplement for more details.
74 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
75 /// the offset to the location of the symbol name from the base of the GOT.
77 /// See the X86-64 ELF ABI supplement for more details.
78 /// SYMBOL_LABEL @GOTOFF
81 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
82 /// offset to the GOT entry for the symbol name from the current code
85 /// See the X86-64 ELF ABI supplement for more details.
86 /// SYMBOL_LABEL @GOTPCREL
89 /// MO_PLT - On a symbol operand this indicates that the immediate is
90 /// offset to the PLT entry of symbol name from the current code location.
92 /// See the X86-64 ELF ABI supplement for more details.
96 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
99 /// See 'ELF Handling for Thread-Local Storage' for more details.
100 /// SYMBOL_LABEL @TLSGD
103 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
106 /// See 'ELF Handling for Thread-Local Storage' for more details.
107 /// SYMBOL_LABEL @GOTTPOFF
110 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
113 /// See 'ELF Handling for Thread-Local Storage' for more details.
114 /// SYMBOL_LABEL @INDNTPOFF
117 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
120 /// See 'ELF Handling for Thread-Local Storage' for more details.
121 /// SYMBOL_LABEL @TPOFF
124 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
127 /// See 'ELF Handling for Thread-Local Storage' for more details.
128 /// SYMBOL_LABEL @NTPOFF
131 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
132 /// reference is actually to the "__imp_FOO" symbol. This is used for
133 /// dllimport linkage on windows.
136 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
137 /// reference is actually to the "FOO$stub" symbol. This is used for calls
138 /// and jumps to external functions on Tiger and earlier.
141 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
142 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
143 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
146 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
147 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
148 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
149 MO_DARWIN_NONLAZY_PIC_BASE,
151 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
152 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
153 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
155 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
157 /// MO_TLVP - On a symbol operand this indicates that the immediate is
160 /// This is the TLS offset for the Darwin TLS mechanism.
163 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
164 /// is some TLS offset from the picbase.
166 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
171 //===------------------------------------------------------------------===//
172 // Instruction encodings. These are the standard/most common forms for X86
176 // PseudoFrm - This represents an instruction that is a pseudo instruction
177 // or one that has not been implemented yet. It is illegal to code generate
178 // it, but tolerated for intermediate implementation stages.
181 /// Raw - This form is for instructions that don't have any operands, so
182 /// they are just a fixed opcode value, like 'leave'.
185 /// AddRegFrm - This form is used for instructions like 'push r32' that have
186 /// their one register operand added to their opcode.
189 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
190 /// to specify a destination, which in this case is a register.
194 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
195 /// to specify a destination, which in this case is memory.
199 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
200 /// to specify a source, which in this case is a register.
204 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
205 /// to specify a source, which in this case is memory.
209 /// MRM[0-7][rm] - These forms are used to represent instructions that use
210 /// a Mod/RM byte, and use the middle field to hold extended opcode
211 /// information. In the intel manual these are represented as /0, /1, ...
214 // First, instructions that operate on a register r/m operand...
215 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
216 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
218 // Next, instructions that operate on a memory r/m operand...
219 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
220 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
222 // MRMInitReg - This form is used for instructions whose source and
223 // destinations are the same register.
226 //// MRM_C1 - A mod/rm byte of exactly 0xC1.
240 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
241 /// immediates, the first of which is a 16-bit immediate (specified by
242 /// the imm encoding) and the second is a 8-bit fixed value.
245 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
246 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
247 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
248 /// manual, this operand is described as pntr16:32 and pntr16:16
253 //===------------------------------------------------------------------===//
256 // OpSize - Set if this instruction requires an operand size prefix (0x66),
257 // which most often indicates that the instruction operates on 16 bit data
258 // instead of 32 bit data.
261 // AsSize - Set if this instruction requires an operand size prefix (0x67),
262 // which most often indicates that the instruction address 16 bit address
263 // instead of 32 bit address (or 32 bit address in 64 bit mode).
266 //===------------------------------------------------------------------===//
267 // Op0Mask - There are several prefix bytes that are used to form two byte
268 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
269 // used to obtain the setting of this field. If no bits in this field is
270 // set, there is no prefix byte for obtaining a multibyte opcode.
273 Op0Mask = 0x1F << Op0Shift,
275 // TB - TwoByte - Set if this instruction has a two byte opcode, which
276 // starts with a 0x0F byte before the real opcode.
279 // REP - The 0xF3 prefix byte indicating repetition of the following
283 // D8-DF - These escape opcodes are used by the floating point unit. These
284 // values must remain sequential.
285 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
286 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
287 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
288 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
290 // XS, XD - These prefix codes are for single and double precision scalar
291 // floating point operations performed in the SSE registers.
292 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
294 // T8, TA, A6, A7 - Prefix after the 0x0F prefix.
295 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
296 A6 = 15 << Op0Shift, A7 = 16 << Op0Shift,
298 // T8XD - Prefix before and after 0x0F. Combination of T8 and XD.
299 T8XD = 17 << Op0Shift,
301 // T8XS - Prefix before and after 0x0F. Combination of T8 and XS.
302 T8XS = 18 << Op0Shift,
304 //===------------------------------------------------------------------===//
305 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
306 // They are used to specify GPRs and SSE registers, 64-bit operand size,
307 // etc. We only cares about REX.W and REX.R bits and only the former is
308 // statically determined.
310 REXShift = Op0Shift + 5,
311 REX_W = 1 << REXShift,
313 //===------------------------------------------------------------------===//
314 // This three-bit field describes the size of an immediate operand. Zero is
315 // unused so that we can tell if we forgot to set a value.
316 ImmShift = REXShift + 1,
317 ImmMask = 7 << ImmShift,
318 Imm8 = 1 << ImmShift,
319 Imm8PCRel = 2 << ImmShift,
320 Imm16 = 3 << ImmShift,
321 Imm16PCRel = 4 << ImmShift,
322 Imm32 = 5 << ImmShift,
323 Imm32PCRel = 6 << ImmShift,
324 Imm64 = 7 << ImmShift,
326 //===------------------------------------------------------------------===//
327 // FP Instruction Classification... Zero is non-fp instruction.
329 // FPTypeMask - Mask for all of the FP types...
330 FPTypeShift = ImmShift + 3,
331 FPTypeMask = 7 << FPTypeShift,
333 // NotFP - The default, set for instructions that do not use FP registers.
334 NotFP = 0 << FPTypeShift,
336 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
337 ZeroArgFP = 1 << FPTypeShift,
339 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
340 OneArgFP = 2 << FPTypeShift,
342 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
343 // result back to ST(0). For example, fcos, fsqrt, etc.
345 OneArgFPRW = 3 << FPTypeShift,
347 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
348 // explicit argument, storing the result to either ST(0) or the implicit
349 // argument. For example: fadd, fsub, fmul, etc...
350 TwoArgFP = 4 << FPTypeShift,
352 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
353 // explicit argument, but have no destination. Example: fucom, fucomi, ...
354 CompareFP = 5 << FPTypeShift,
356 // CondMovFP - "2 operand" floating point conditional move instructions.
357 CondMovFP = 6 << FPTypeShift,
359 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
360 SpecialFP = 7 << FPTypeShift,
363 LOCKShift = FPTypeShift + 3,
364 LOCK = 1 << LOCKShift,
366 // Segment override prefixes. Currently we just need ability to address
367 // stuff in gs and fs segments.
368 SegOvrShift = LOCKShift + 1,
369 SegOvrMask = 3 << SegOvrShift,
370 FS = 1 << SegOvrShift,
371 GS = 2 << SegOvrShift,
373 // Execution domain for SSE instructions in bits 23, 24.
374 // 0 in bits 23-24 means normal, non-SSE instruction.
375 SSEDomainShift = SegOvrShift + 2,
377 OpcodeShift = SSEDomainShift + 2,
379 //===------------------------------------------------------------------===//
380 /// VEX - The opcode prefix used by AVX instructions
381 VEXShift = OpcodeShift + 8,
384 /// VEX_W - Has a opcode specific functionality, but is used in the same
385 /// way as REX_W is for regular SSE instructions.
388 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
389 /// address instructions in SSE are represented as 3 address ones in AVX
390 /// and the additional register is encoded in VEX_VVVV prefix.
393 /// VEX_4VOp3 - Similar to VEX_4V, but used on instructions that encode
394 /// operand 3 with VEX.vvvv.
397 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
398 /// must be encoded in the i8 immediate field. This usually happens in
399 /// instructions with 4 operands.
402 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
403 /// instruction uses 256-bit wide registers. This is usually auto detected
404 /// if a VR256 register is used, but some AVX instructions also have this
405 /// field marked when using a f256 memory references.
408 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
409 // prefix. Usually used for scalar instructions. Needed by disassembler.
412 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
413 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
414 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
415 /// storing a classifier in the imm8 field. To simplify our implementation,
416 /// we handle this by storeing the classifier in the opcode field and using
417 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
418 Has3DNow0F0FOpcode = 1U << 7
421 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
422 // specified machine instruction.
424 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
425 return TSFlags >> X86II::OpcodeShift;
428 static inline bool hasImm(uint64_t TSFlags) {
429 return (TSFlags & X86II::ImmMask) != 0;
432 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
433 /// of the specified instruction.
434 static inline unsigned getSizeOfImm(uint64_t TSFlags) {
435 switch (TSFlags & X86II::ImmMask) {
436 default: assert(0 && "Unknown immediate size");
438 case X86II::Imm8PCRel: return 1;
440 case X86II::Imm16PCRel: return 2;
442 case X86II::Imm32PCRel: return 4;
443 case X86II::Imm64: return 8;
447 /// isImmPCRel - Return true if the immediate of the specified instruction's
448 /// TSFlags indicates that it is pc relative.
449 static inline unsigned isImmPCRel(uint64_t TSFlags) {
450 switch (TSFlags & X86II::ImmMask) {
451 default: assert(0 && "Unknown immediate size");
452 case X86II::Imm8PCRel:
453 case X86II::Imm16PCRel:
454 case X86II::Imm32PCRel:
464 /// getMemoryOperandNo - The function returns the MCInst operand # for the
465 /// first field of the memory operand. If the instruction doesn't have a
466 /// memory operand, this returns -1.
468 /// Note that this ignores tied operands. If there is a tied register which
469 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
470 /// counted as one operand.
472 static inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) {
473 switch (TSFlags & X86II::FormMask) {
474 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form");
475 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
478 case X86II::AddRegFrm:
479 case X86II::MRMDestReg:
480 case X86II::MRMSrcReg:
481 case X86II::RawFrmImm8:
482 case X86II::RawFrmImm16:
484 case X86II::MRMDestMem:
486 case X86II::MRMSrcMem: {
487 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
488 unsigned FirstMemOp = 1;
490 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
492 // FIXME: Maybe lea should have its own form? This is a horrible hack.
493 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
494 // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
497 case X86II::MRM0r: case X86II::MRM1r:
498 case X86II::MRM2r: case X86II::MRM3r:
499 case X86II::MRM4r: case X86II::MRM5r:
500 case X86II::MRM6r: case X86II::MRM7r:
502 case X86II::MRM0m: case X86II::MRM1m:
503 case X86II::MRM2m: case X86II::MRM3m:
504 case X86II::MRM4m: case X86II::MRM5m:
505 case X86II::MRM6m: case X86II::MRM7m: {
506 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
507 unsigned FirstMemOp = 0;
509 ++FirstMemOp;// Skip the register dest (which is encoded in VEX_VVVV).
528 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
529 /// higher) register? e.g. r8, xmm8, xmm13, etc.
530 static inline bool isX86_64ExtendedReg(unsigned RegNo) {
533 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
534 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
535 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
536 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
537 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
538 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
539 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
540 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
541 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
542 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
543 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
544 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
545 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
546 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
552 static inline bool isX86_64NonExtLowByteReg(unsigned reg) {
553 return (reg == X86::SPL || reg == X86::BPL ||
554 reg == X86::SIL || reg == X86::DIL);
558 } // end namespace llvm;