1 //===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86IntelInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "MCTargetDesc/X86MCTargetDesc.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/FormattedStream.h"
28 #include "X86GenAsmWriter1.inc"
30 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
31 OS << getRegisterName(RegNo);
34 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
36 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
37 uint64_t TSFlags = Desc.TSFlags;
39 if (TSFlags & X86II::LOCK)
42 printInstruction(MI, OS);
44 // Next always print the annotation.
45 printAnnotation(OS, Annot);
47 // If verbose assembly is enabled, we can print some informative comments.
49 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
52 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
54 switch (MI->getOperand(Op).getImm()) {
55 default: llvm_unreachable("Invalid ssecc argument!");
56 case 0: O << "eq"; break;
57 case 1: O << "lt"; break;
58 case 2: O << "le"; break;
59 case 3: O << "unord"; break;
60 case 4: O << "neq"; break;
61 case 5: O << "nlt"; break;
62 case 6: O << "nle"; break;
63 case 7: O << "ord"; break;
64 case 8: O << "eq_uq"; break;
65 case 9: O << "nge"; break;
66 case 0xa: O << "ngt"; break;
67 case 0xb: O << "false"; break;
68 case 0xc: O << "neq_oq"; break;
69 case 0xd: O << "ge"; break;
70 case 0xe: O << "gt"; break;
71 case 0xf: O << "true"; break;
72 case 0x10: O << "eq_os"; break;
73 case 0x11: O << "lt_oq"; break;
74 case 0x12: O << "le_oq"; break;
75 case 0x13: O << "unord_s"; break;
76 case 0x14: O << "neq_us"; break;
77 case 0x15: O << "nlt_uq"; break;
78 case 0x16: O << "nle_uq"; break;
79 case 0x17: O << "ord_s"; break;
80 case 0x18: O << "eq_us"; break;
81 case 0x19: O << "nge_uq"; break;
82 case 0x1a: O << "ngt_uq"; break;
83 case 0x1b: O << "false_os"; break;
84 case 0x1c: O << "neq_os"; break;
85 case 0x1d: O << "ge_oq"; break;
86 case 0x1e: O << "gt_oq"; break;
87 case 0x1f: O << "true_us"; break;
92 /// printPCRelImm - This is used to print an immediate value that ends up
93 /// being encoded as a pc-relative value.
94 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
96 const MCOperand &Op = MI->getOperand(OpNo);
100 assert(Op.isExpr() && "unknown pcrel immediate operand");
101 // If a symbolic branch target was added as a constant expression then print
102 // that address in hex.
103 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
105 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
107 O.write_hex(Address);
110 // Otherwise, just print the expression.
116 static void PrintRegName(raw_ostream &O, StringRef RegName) {
117 for (unsigned i = 0, e = RegName.size(); i != e; ++i)
118 O << (char)toupper(RegName[i]);
121 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
123 const MCOperand &Op = MI->getOperand(OpNo);
125 PrintRegName(O, getRegisterName(Op.getReg()));
126 } else if (Op.isImm()) {
129 assert(Op.isExpr() && "unknown operand kind in printOperand");
134 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
136 const MCOperand &BaseReg = MI->getOperand(Op);
137 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
138 const MCOperand &IndexReg = MI->getOperand(Op+2);
139 const MCOperand &DispSpec = MI->getOperand(Op+3);
140 const MCOperand &SegReg = MI->getOperand(Op+4);
142 // If this has a segment register, print it.
143 if (SegReg.getReg()) {
144 printOperand(MI, Op+4, O);
150 bool NeedPlus = false;
151 if (BaseReg.getReg()) {
152 printOperand(MI, Op, O);
156 if (IndexReg.getReg()) {
157 if (NeedPlus) O << " + ";
159 O << ScaleVal << '*';
160 printOperand(MI, Op+2, O);
165 if (!DispSpec.isImm()) {
166 if (NeedPlus) O << " + ";
167 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
168 O << *DispSpec.getExpr();
170 int64_t DispVal = DispSpec.getImm();
171 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {