1 //===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This defines functionality used to emit comments about X86 instructions to
11 // an output stream for -fverbose-asm.
13 //===----------------------------------------------------------------------===//
15 #include "X86InstComments.h"
16 #include "MCTargetDesc/X86MCTargetDesc.h"
17 #include "Utils/X86ShuffleDecode.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/CodeGen/MachineValueType.h"
20 #include "llvm/Support/raw_ostream.h"
24 static unsigned getVectorRegSize(unsigned RegNo) {
25 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
27 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
29 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
31 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
34 llvm_unreachable("Unknown vector reg!");
38 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
39 unsigned OperandIndex) {
40 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
41 return MVT::getVectorVT(ScalarVT,
42 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
45 /// \brief Extracts the src/dst types for a given zero extension instruction.
46 /// \note While the number of elements in DstVT type correct, the
47 /// number in the SrcVT type is expanded to fill the src xmm register and the
48 /// upper elements may not be included in the dst xmm/ymm register.
49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
50 switch (MI->getOpcode()) {
52 llvm_unreachable("Unknown zero extension instruction");
56 case X86::VPMOVZXBWrm:
57 case X86::VPMOVZXBWrr:
61 case X86::VPMOVZXBWYrm:
62 case X86::VPMOVZXBWYrr:
68 case X86::VPMOVZXBDrm:
69 case X86::VPMOVZXBDrr:
73 case X86::VPMOVZXBDYrm:
74 case X86::VPMOVZXBDYrr:
80 case X86::VPMOVZXBQrm:
81 case X86::VPMOVZXBQrr:
85 case X86::VPMOVZXBQYrm:
86 case X86::VPMOVZXBQYrr:
93 case X86::VPMOVZXWDrm:
94 case X86::VPMOVZXWDrr:
98 case X86::VPMOVZXWDYrm:
99 case X86::VPMOVZXWDYrr:
103 case X86::PMOVZXWQrm:
104 case X86::PMOVZXWQrr:
105 case X86::VPMOVZXWQrm:
106 case X86::VPMOVZXWQrr:
110 case X86::VPMOVZXWQYrm:
111 case X86::VPMOVZXWQYrr:
115 // i32 zero extension
116 case X86::PMOVZXDQrm:
117 case X86::PMOVZXDQrr:
118 case X86::VPMOVZXDQrm:
119 case X86::VPMOVZXDQrr:
123 case X86::VPMOVZXDQYrm:
124 case X86::VPMOVZXDQYrr:
131 #define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
132 case X86::V##Inst##Suffix##src: \
133 case X86::V##Inst##Suffix##src##k: \
134 case X86::V##Inst##Suffix##src##kz:
136 #define CASE_SSE_INS_COMMON(Inst, src) \
139 #define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
140 case X86::V##Inst##Suffix##src:
142 #define CASE_MOVDUP(Inst, src) \
143 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
144 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
145 CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
146 CASE_AVX_INS_COMMON(Inst, , r##src) \
147 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
148 CASE_SSE_INS_COMMON(Inst, r##src) \
150 #define CASE_VSHUF(Inst, src) \
151 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
152 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
153 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
154 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \
156 /// \brief Extracts the types and if it has memory operand for a given
157 /// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
158 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
160 switch (MI->getOpcode()) {
162 llvm_unreachable("Unknown VSHUF64x2 family instructions.");
165 HasMemOp = true; // FALL THROUGH.
167 VT = getRegOperandVectorVT(MI, MVT::i64, 0);
170 HasMemOp = true; // FALL THROUGH.
172 VT = getRegOperandVectorVT(MI, MVT::i32, 0);
177 //===----------------------------------------------------------------------===//
178 // Top Level Entrypoint
179 //===----------------------------------------------------------------------===//
181 /// EmitAnyX86InstComments - This function decodes x86 instructions and prints
182 /// newline terminated strings to the specified string if desired. This
183 /// information is shown in disassembly dumps when verbose assembly is enabled.
184 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
185 const char *(*getRegName)(unsigned)) {
186 // If this is a shuffle operation, the switch should fill in this state.
187 SmallVector<int, 8> ShuffleMask;
188 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
190 switch (MI->getOpcode()) {
192 // Not an instruction for which we can decode comments.
195 case X86::BLENDPDrri:
196 case X86::VBLENDPDrri:
197 Src2Name = getRegName(MI->getOperand(2).getReg());
199 case X86::BLENDPDrmi:
200 case X86::VBLENDPDrmi:
201 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
202 DecodeBLENDMask(MVT::v2f64,
203 MI->getOperand(MI->getNumOperands() - 1).getImm(),
205 Src1Name = getRegName(MI->getOperand(1).getReg());
206 DestName = getRegName(MI->getOperand(0).getReg());
209 case X86::VBLENDPDYrri:
210 Src2Name = getRegName(MI->getOperand(2).getReg());
212 case X86::VBLENDPDYrmi:
213 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
214 DecodeBLENDMask(MVT::v4f64,
215 MI->getOperand(MI->getNumOperands() - 1).getImm(),
217 Src1Name = getRegName(MI->getOperand(1).getReg());
218 DestName = getRegName(MI->getOperand(0).getReg());
221 case X86::BLENDPSrri:
222 case X86::VBLENDPSrri:
223 Src2Name = getRegName(MI->getOperand(2).getReg());
225 case X86::BLENDPSrmi:
226 case X86::VBLENDPSrmi:
227 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
228 DecodeBLENDMask(MVT::v4f32,
229 MI->getOperand(MI->getNumOperands() - 1).getImm(),
231 Src1Name = getRegName(MI->getOperand(1).getReg());
232 DestName = getRegName(MI->getOperand(0).getReg());
235 case X86::VBLENDPSYrri:
236 Src2Name = getRegName(MI->getOperand(2).getReg());
238 case X86::VBLENDPSYrmi:
239 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
240 DecodeBLENDMask(MVT::v8f32,
241 MI->getOperand(MI->getNumOperands() - 1).getImm(),
243 Src1Name = getRegName(MI->getOperand(1).getReg());
244 DestName = getRegName(MI->getOperand(0).getReg());
247 case X86::PBLENDWrri:
248 case X86::VPBLENDWrri:
249 Src2Name = getRegName(MI->getOperand(2).getReg());
251 case X86::PBLENDWrmi:
252 case X86::VPBLENDWrmi:
253 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
254 DecodeBLENDMask(MVT::v8i16,
255 MI->getOperand(MI->getNumOperands() - 1).getImm(),
257 Src1Name = getRegName(MI->getOperand(1).getReg());
258 DestName = getRegName(MI->getOperand(0).getReg());
261 case X86::VPBLENDWYrri:
262 Src2Name = getRegName(MI->getOperand(2).getReg());
264 case X86::VPBLENDWYrmi:
265 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
266 DecodeBLENDMask(MVT::v16i16,
267 MI->getOperand(MI->getNumOperands() - 1).getImm(),
269 Src1Name = getRegName(MI->getOperand(1).getReg());
270 DestName = getRegName(MI->getOperand(0).getReg());
273 case X86::VPBLENDDrri:
274 Src2Name = getRegName(MI->getOperand(2).getReg());
276 case X86::VPBLENDDrmi:
277 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
278 DecodeBLENDMask(MVT::v4i32,
279 MI->getOperand(MI->getNumOperands() - 1).getImm(),
281 Src1Name = getRegName(MI->getOperand(1).getReg());
282 DestName = getRegName(MI->getOperand(0).getReg());
285 case X86::VPBLENDDYrri:
286 Src2Name = getRegName(MI->getOperand(2).getReg());
288 case X86::VPBLENDDYrmi:
289 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
290 DecodeBLENDMask(MVT::v8i32,
291 MI->getOperand(MI->getNumOperands() - 1).getImm(),
293 Src1Name = getRegName(MI->getOperand(1).getReg());
294 DestName = getRegName(MI->getOperand(0).getReg());
297 case X86::INSERTPSrr:
298 case X86::VINSERTPSrr:
299 Src2Name = getRegName(MI->getOperand(2).getReg());
301 case X86::INSERTPSrm:
302 case X86::VINSERTPSrm:
303 DestName = getRegName(MI->getOperand(0).getReg());
304 Src1Name = getRegName(MI->getOperand(1).getReg());
305 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
306 DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
311 case X86::VMOVLHPSrr:
312 Src2Name = getRegName(MI->getOperand(2).getReg());
313 Src1Name = getRegName(MI->getOperand(1).getReg());
314 DestName = getRegName(MI->getOperand(0).getReg());
315 DecodeMOVLHPSMask(2, ShuffleMask);
319 case X86::VMOVHLPSrr:
320 Src2Name = getRegName(MI->getOperand(2).getReg());
321 Src1Name = getRegName(MI->getOperand(1).getReg());
322 DestName = getRegName(MI->getOperand(0).getReg());
323 DecodeMOVHLPSMask(2, ShuffleMask);
326 CASE_MOVDUP(MOVSLDUP, r)
327 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
329 CASE_MOVDUP(MOVSLDUP, m) {
330 MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
331 DestName = getRegName(MI->getOperand(0).getReg());
332 DecodeMOVSLDUPMask(VT, ShuffleMask);
336 CASE_MOVDUP(MOVSHDUP, r)
337 Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
339 CASE_MOVDUP(MOVSHDUP, m) {
340 MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
341 DestName = getRegName(MI->getOperand(0).getReg());
342 DecodeMOVSHDUPMask(VT, ShuffleMask);
346 case X86::VMOVDDUPYrr:
347 Src1Name = getRegName(MI->getOperand(1).getReg());
349 case X86::VMOVDDUPYrm:
350 DestName = getRegName(MI->getOperand(0).getReg());
351 DecodeMOVDDUPMask(MVT::v4f64, ShuffleMask);
355 case X86::VMOVDDUPrr:
356 Src1Name = getRegName(MI->getOperand(1).getReg());
359 case X86::VMOVDDUPrm:
360 DestName = getRegName(MI->getOperand(0).getReg());
361 DecodeMOVDDUPMask(MVT::v2f64, ShuffleMask);
366 case X86::VPSLLDQYri:
367 Src1Name = getRegName(MI->getOperand(1).getReg());
368 DestName = getRegName(MI->getOperand(0).getReg());
369 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
370 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
371 MI->getOperand(MI->getNumOperands() - 1).getImm(),
377 case X86::VPSRLDQYri:
378 Src1Name = getRegName(MI->getOperand(1).getReg());
379 DestName = getRegName(MI->getOperand(0).getReg());
380 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
381 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
382 MI->getOperand(MI->getNumOperands() - 1).getImm(),
386 case X86::PALIGNR128rr:
387 case X86::VPALIGNR128rr:
388 case X86::VPALIGNR256rr:
389 Src1Name = getRegName(MI->getOperand(2).getReg());
391 case X86::PALIGNR128rm:
392 case X86::VPALIGNR128rm:
393 case X86::VPALIGNR256rm:
394 Src2Name = getRegName(MI->getOperand(1).getReg());
395 DestName = getRegName(MI->getOperand(0).getReg());
396 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
397 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
398 MI->getOperand(MI->getNumOperands() - 1).getImm(),
404 case X86::VPSHUFDYri:
405 Src1Name = getRegName(MI->getOperand(1).getReg());
409 case X86::VPSHUFDYmi:
410 DestName = getRegName(MI->getOperand(0).getReg());
411 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
412 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
413 MI->getOperand(MI->getNumOperands() - 1).getImm(),
418 case X86::VPSHUFHWri:
419 case X86::VPSHUFHWYri:
420 Src1Name = getRegName(MI->getOperand(1).getReg());
423 case X86::VPSHUFHWmi:
424 case X86::VPSHUFHWYmi:
425 DestName = getRegName(MI->getOperand(0).getReg());
426 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
427 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
428 MI->getOperand(MI->getNumOperands() - 1).getImm(),
433 case X86::VPSHUFLWri:
434 case X86::VPSHUFLWYri:
435 Src1Name = getRegName(MI->getOperand(1).getReg());
438 case X86::VPSHUFLWmi:
439 case X86::VPSHUFLWYmi:
440 DestName = getRegName(MI->getOperand(0).getReg());
441 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
442 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
443 MI->getOperand(MI->getNumOperands() - 1).getImm(),
447 case X86::MMX_PSHUFWri:
448 Src1Name = getRegName(MI->getOperand(1).getReg());
450 case X86::MMX_PSHUFWmi:
451 DestName = getRegName(MI->getOperand(0).getReg());
452 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
453 DecodePSHUFMask(MVT::v4i16,
454 MI->getOperand(MI->getNumOperands() - 1).getImm(),
459 Src1Name = getRegName(MI->getOperand(1).getReg());
462 DestName = getRegName(MI->getOperand(0).getReg());
463 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
466 case X86::MMX_PUNPCKHBWirr:
467 case X86::PUNPCKHBWrr:
468 case X86::VPUNPCKHBWrr:
469 case X86::VPUNPCKHBWYrr:
470 Src2Name = getRegName(MI->getOperand(2).getReg());
472 case X86::MMX_PUNPCKHBWirm:
473 case X86::PUNPCKHBWrm:
474 case X86::VPUNPCKHBWrm:
475 case X86::VPUNPCKHBWYrm:
476 Src1Name = getRegName(MI->getOperand(1).getReg());
477 DestName = getRegName(MI->getOperand(0).getReg());
478 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
481 case X86::MMX_PUNPCKHWDirr:
482 case X86::PUNPCKHWDrr:
483 case X86::VPUNPCKHWDrr:
484 case X86::VPUNPCKHWDYrr:
485 Src2Name = getRegName(MI->getOperand(2).getReg());
487 case X86::MMX_PUNPCKHWDirm:
488 case X86::PUNPCKHWDrm:
489 case X86::VPUNPCKHWDrm:
490 case X86::VPUNPCKHWDYrm:
491 Src1Name = getRegName(MI->getOperand(1).getReg());
492 DestName = getRegName(MI->getOperand(0).getReg());
493 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
496 case X86::MMX_PUNPCKHDQirr:
497 case X86::PUNPCKHDQrr:
498 case X86::VPUNPCKHDQrr:
499 case X86::VPUNPCKHDQYrr:
500 case X86::VPUNPCKHDQZrr:
501 Src2Name = getRegName(MI->getOperand(2).getReg());
503 case X86::MMX_PUNPCKHDQirm:
504 case X86::PUNPCKHDQrm:
505 case X86::VPUNPCKHDQrm:
506 case X86::VPUNPCKHDQYrm:
507 case X86::VPUNPCKHDQZrm:
508 Src1Name = getRegName(MI->getOperand(1).getReg());
509 DestName = getRegName(MI->getOperand(0).getReg());
510 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
513 case X86::PUNPCKHQDQrr:
514 case X86::VPUNPCKHQDQrr:
515 case X86::VPUNPCKHQDQYrr:
516 case X86::VPUNPCKHQDQZrr:
517 Src2Name = getRegName(MI->getOperand(2).getReg());
519 case X86::PUNPCKHQDQrm:
520 case X86::VPUNPCKHQDQrm:
521 case X86::VPUNPCKHQDQYrm:
522 case X86::VPUNPCKHQDQZrm:
523 Src1Name = getRegName(MI->getOperand(1).getReg());
524 DestName = getRegName(MI->getOperand(0).getReg());
525 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
528 case X86::MMX_PUNPCKLBWirr:
529 case X86::PUNPCKLBWrr:
530 case X86::VPUNPCKLBWrr:
531 case X86::VPUNPCKLBWYrr:
532 Src2Name = getRegName(MI->getOperand(2).getReg());
534 case X86::MMX_PUNPCKLBWirm:
535 case X86::PUNPCKLBWrm:
536 case X86::VPUNPCKLBWrm:
537 case X86::VPUNPCKLBWYrm:
538 Src1Name = getRegName(MI->getOperand(1).getReg());
539 DestName = getRegName(MI->getOperand(0).getReg());
540 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
543 case X86::MMX_PUNPCKLWDirr:
544 case X86::PUNPCKLWDrr:
545 case X86::VPUNPCKLWDrr:
546 case X86::VPUNPCKLWDYrr:
547 Src2Name = getRegName(MI->getOperand(2).getReg());
549 case X86::MMX_PUNPCKLWDirm:
550 case X86::PUNPCKLWDrm:
551 case X86::VPUNPCKLWDrm:
552 case X86::VPUNPCKLWDYrm:
553 Src1Name = getRegName(MI->getOperand(1).getReg());
554 DestName = getRegName(MI->getOperand(0).getReg());
555 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
558 case X86::MMX_PUNPCKLDQirr:
559 case X86::PUNPCKLDQrr:
560 case X86::VPUNPCKLDQrr:
561 case X86::VPUNPCKLDQYrr:
562 case X86::VPUNPCKLDQZrr:
563 Src2Name = getRegName(MI->getOperand(2).getReg());
565 case X86::MMX_PUNPCKLDQirm:
566 case X86::PUNPCKLDQrm:
567 case X86::VPUNPCKLDQrm:
568 case X86::VPUNPCKLDQYrm:
569 case X86::VPUNPCKLDQZrm:
570 Src1Name = getRegName(MI->getOperand(1).getReg());
571 DestName = getRegName(MI->getOperand(0).getReg());
572 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
575 case X86::PUNPCKLQDQrr:
576 case X86::VPUNPCKLQDQrr:
577 case X86::VPUNPCKLQDQYrr:
578 case X86::VPUNPCKLQDQZrr:
579 Src2Name = getRegName(MI->getOperand(2).getReg());
581 case X86::PUNPCKLQDQrm:
582 case X86::VPUNPCKLQDQrm:
583 case X86::VPUNPCKLQDQYrm:
584 case X86::VPUNPCKLQDQZrm:
585 Src1Name = getRegName(MI->getOperand(1).getReg());
586 DestName = getRegName(MI->getOperand(0).getReg());
587 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
591 case X86::VSHUFPDrri:
592 case X86::VSHUFPDYrri:
593 Src2Name = getRegName(MI->getOperand(2).getReg());
596 case X86::VSHUFPDrmi:
597 case X86::VSHUFPDYrmi:
598 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
599 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
600 MI->getOperand(MI->getNumOperands() - 1).getImm(),
602 Src1Name = getRegName(MI->getOperand(1).getReg());
603 DestName = getRegName(MI->getOperand(0).getReg());
607 case X86::VSHUFPSrri:
608 case X86::VSHUFPSYrri:
609 Src2Name = getRegName(MI->getOperand(2).getReg());
612 case X86::VSHUFPSrmi:
613 case X86::VSHUFPSYrmi:
614 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
615 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
616 MI->getOperand(MI->getNumOperands() - 1).getImm(),
618 Src1Name = getRegName(MI->getOperand(1).getReg());
619 DestName = getRegName(MI->getOperand(0).getReg());
625 CASE_VSHUF(32X4, m) {
628 unsigned NumOp = MI->getNumOperands();
629 getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
630 decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
632 DestName = getRegName(MI->getOperand(0).getReg());
634 assert((NumOp >= 8) && "Expected at least 8 operands!");
635 Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
637 assert((NumOp >= 4) && "Expected at least 4 operands!");
638 Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
639 Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
644 case X86::UNPCKLPDrr:
645 case X86::VUNPCKLPDrr:
646 case X86::VUNPCKLPDYrr:
647 case X86::VUNPCKLPDZrr:
648 Src2Name = getRegName(MI->getOperand(2).getReg());
650 case X86::UNPCKLPDrm:
651 case X86::VUNPCKLPDrm:
652 case X86::VUNPCKLPDYrm:
653 case X86::VUNPCKLPDZrm:
654 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
655 Src1Name = getRegName(MI->getOperand(1).getReg());
656 DestName = getRegName(MI->getOperand(0).getReg());
659 case X86::UNPCKLPSrr:
660 case X86::VUNPCKLPSrr:
661 case X86::VUNPCKLPSYrr:
662 case X86::VUNPCKLPSZrr:
663 Src2Name = getRegName(MI->getOperand(2).getReg());
665 case X86::UNPCKLPSrm:
666 case X86::VUNPCKLPSrm:
667 case X86::VUNPCKLPSYrm:
668 case X86::VUNPCKLPSZrm:
669 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
670 Src1Name = getRegName(MI->getOperand(1).getReg());
671 DestName = getRegName(MI->getOperand(0).getReg());
674 case X86::UNPCKHPDrr:
675 case X86::VUNPCKHPDrr:
676 case X86::VUNPCKHPDYrr:
677 case X86::VUNPCKHPDZrr:
678 Src2Name = getRegName(MI->getOperand(2).getReg());
680 case X86::UNPCKHPDrm:
681 case X86::VUNPCKHPDrm:
682 case X86::VUNPCKHPDYrm:
683 case X86::VUNPCKHPDZrm:
684 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
685 Src1Name = getRegName(MI->getOperand(1).getReg());
686 DestName = getRegName(MI->getOperand(0).getReg());
689 case X86::UNPCKHPSrr:
690 case X86::VUNPCKHPSrr:
691 case X86::VUNPCKHPSYrr:
692 case X86::VUNPCKHPSZrr:
693 Src2Name = getRegName(MI->getOperand(2).getReg());
695 case X86::UNPCKHPSrm:
696 case X86::VUNPCKHPSrm:
697 case X86::VUNPCKHPSYrm:
698 case X86::VUNPCKHPSZrm:
699 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
700 Src1Name = getRegName(MI->getOperand(1).getReg());
701 DestName = getRegName(MI->getOperand(0).getReg());
704 case X86::VPERMILPSri:
705 case X86::VPERMILPSYri:
706 Src1Name = getRegName(MI->getOperand(1).getReg());
708 case X86::VPERMILPSmi:
709 case X86::VPERMILPSYmi:
710 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
711 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
712 MI->getOperand(MI->getNumOperands() - 1).getImm(),
714 DestName = getRegName(MI->getOperand(0).getReg());
717 case X86::VPERMILPDri:
718 case X86::VPERMILPDYri:
719 Src1Name = getRegName(MI->getOperand(1).getReg());
721 case X86::VPERMILPDmi:
722 case X86::VPERMILPDYmi:
723 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
724 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
725 MI->getOperand(MI->getNumOperands() - 1).getImm(),
727 DestName = getRegName(MI->getOperand(0).getReg());
730 case X86::VPERM2F128rr:
731 case X86::VPERM2I128rr:
732 Src2Name = getRegName(MI->getOperand(2).getReg());
734 case X86::VPERM2F128rm:
735 case X86::VPERM2I128rm:
736 // For instruction comments purpose, assume the 256-bit vector is v4i64.
737 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
738 DecodeVPERM2X128Mask(MVT::v4i64,
739 MI->getOperand(MI->getNumOperands() - 1).getImm(),
741 Src1Name = getRegName(MI->getOperand(1).getReg());
742 DestName = getRegName(MI->getOperand(0).getReg());
746 case X86::VPERMPDYri:
747 Src1Name = getRegName(MI->getOperand(1).getReg());
750 case X86::VPERMPDYmi:
751 if (MI->getOperand(MI->getNumOperands() - 1).isImm())
752 DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
754 DestName = getRegName(MI->getOperand(0).getReg());
759 Src2Name = getRegName(MI->getOperand(2).getReg());
760 Src1Name = getRegName(MI->getOperand(1).getReg());
764 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
765 DestName = getRegName(MI->getOperand(0).getReg());
769 Src2Name = getRegName(MI->getOperand(2).getReg());
770 Src1Name = getRegName(MI->getOperand(1).getReg());
774 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
775 DestName = getRegName(MI->getOperand(0).getReg());
778 case X86::MOVPQI2QIrr:
779 case X86::MOVZPQILo2PQIrr:
780 case X86::VMOVPQI2QIrr:
781 case X86::VMOVZPQILo2PQIrr:
782 Src1Name = getRegName(MI->getOperand(1).getReg());
784 case X86::MOVQI2PQIrm:
785 case X86::MOVZQI2PQIrm:
786 case X86::MOVZPQILo2PQIrm:
787 case X86::VMOVQI2PQIrm:
788 case X86::VMOVZQI2PQIrm:
789 case X86::VMOVZPQILo2PQIrm:
790 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
791 DestName = getRegName(MI->getOperand(0).getReg());
794 case X86::MOVDI2PDIrm:
795 case X86::VMOVDI2PDIrm:
796 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
797 DestName = getRegName(MI->getOperand(0).getReg());
801 if (MI->getOperand(2).isImm() &&
802 MI->getOperand(3).isImm())
803 DecodeEXTRQIMask(MI->getOperand(2).getImm(),
804 MI->getOperand(3).getImm(),
807 DestName = getRegName(MI->getOperand(0).getReg());
808 Src1Name = getRegName(MI->getOperand(1).getReg());
812 if (MI->getOperand(3).isImm() &&
813 MI->getOperand(4).isImm())
814 DecodeINSERTQIMask(MI->getOperand(3).getImm(),
815 MI->getOperand(4).getImm(),
818 DestName = getRegName(MI->getOperand(0).getReg());
819 Src1Name = getRegName(MI->getOperand(1).getReg());
820 Src2Name = getRegName(MI->getOperand(2).getReg());
823 case X86::PMOVZXBWrr:
824 case X86::PMOVZXBDrr:
825 case X86::PMOVZXBQrr:
826 case X86::PMOVZXWDrr:
827 case X86::PMOVZXWQrr:
828 case X86::PMOVZXDQrr:
829 case X86::VPMOVZXBWrr:
830 case X86::VPMOVZXBDrr:
831 case X86::VPMOVZXBQrr:
832 case X86::VPMOVZXWDrr:
833 case X86::VPMOVZXWQrr:
834 case X86::VPMOVZXDQrr:
835 case X86::VPMOVZXBWYrr:
836 case X86::VPMOVZXBDYrr:
837 case X86::VPMOVZXBQYrr:
838 case X86::VPMOVZXWDYrr:
839 case X86::VPMOVZXWQYrr:
840 case X86::VPMOVZXDQYrr:
841 Src1Name = getRegName(MI->getOperand(1).getReg());
843 case X86::PMOVZXBWrm:
844 case X86::PMOVZXBDrm:
845 case X86::PMOVZXBQrm:
846 case X86::PMOVZXWDrm:
847 case X86::PMOVZXWQrm:
848 case X86::PMOVZXDQrm:
849 case X86::VPMOVZXBWrm:
850 case X86::VPMOVZXBDrm:
851 case X86::VPMOVZXBQrm:
852 case X86::VPMOVZXWDrm:
853 case X86::VPMOVZXWQrm:
854 case X86::VPMOVZXDQrm:
855 case X86::VPMOVZXBWYrm:
856 case X86::VPMOVZXBDYrm:
857 case X86::VPMOVZXBQYrm:
858 case X86::VPMOVZXWDYrm:
859 case X86::VPMOVZXWQYrm:
860 case X86::VPMOVZXDQYrm: {
862 getZeroExtensionTypes(MI, SrcVT, DstVT);
863 DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask);
864 DestName = getRegName(MI->getOperand(0).getReg());
868 // The only comments we decode are shuffles, so give up if we were unable to
869 // decode a shuffle mask.
870 if (ShuffleMask.empty())
873 if (!DestName) DestName = Src1Name;
874 OS << (DestName ? DestName : "mem") << " = ";
876 // If the two sources are the same, canonicalize the input elements to be
877 // from the first src so that we get larger element spans.
878 if (Src1Name == Src2Name) {
879 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
880 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
881 ShuffleMask[i] >= (int)e) // From second mask.
886 // The shuffle mask specifies which elements of the src1/src2 fill in the
887 // destination, with a few sentinel values. Loop through and print them
889 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
892 if (ShuffleMask[i] == SM_SentinelZero) {
897 // Otherwise, it must come from src1 or src2. Print the span of elements
898 // that comes from this src.
899 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
900 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
901 OS << (SrcName ? SrcName : "mem") << '[';
903 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
904 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
909 if (ShuffleMask[i] == SM_SentinelUndef)
912 OS << ShuffleMask[i] % ShuffleMask.size();
916 --i; // For loop increments element #.
921 // We successfully added a comment to this instruction.