1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86ATTInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "MCTargetDesc/X86MCTargetDesc.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/Format.h"
27 #include "llvm/Support/FormattedStream.h"
31 // Include the auto-generated portion of the assembly writer.
32 #define PRINT_ALIAS_INSTR
33 #include "X86GenAsmWriter.inc"
35 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
36 unsigned RegNo) const {
39 OS << '%' << getRegisterName(RegNo);
44 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
46 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
47 uint64_t TSFlags = Desc.TSFlags;
49 if (TSFlags & X86II::LOCK)
52 // Try to print any aliases first.
53 if (!printAliasInstr(MI, OS))
54 printInstruction(MI, OS);
56 // Next always print the annotation.
57 printAnnotation(OS, Annot);
59 // If verbose assembly is enabled, we can print some informative comments.
61 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
64 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
66 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
68 default: llvm_unreachable("Invalid ssecc argument!");
69 case 0: O << "eq"; break;
70 case 1: O << "lt"; break;
71 case 2: O << "le"; break;
72 case 3: O << "unord"; break;
73 case 4: O << "neq"; break;
74 case 5: O << "nlt"; break;
75 case 6: O << "nle"; break;
76 case 7: O << "ord"; break;
77 case 8: O << "eq_uq"; break;
78 case 9: O << "nge"; break;
79 case 0xa: O << "ngt"; break;
80 case 0xb: O << "false"; break;
81 case 0xc: O << "neq_oq"; break;
82 case 0xd: O << "ge"; break;
83 case 0xe: O << "gt"; break;
84 case 0xf: O << "true"; break;
88 void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
90 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
92 default: llvm_unreachable("Invalid avxcc argument!");
93 case 0: O << "eq"; break;
94 case 1: O << "lt"; break;
95 case 2: O << "le"; break;
96 case 3: O << "unord"; break;
97 case 4: O << "neq"; break;
98 case 5: O << "nlt"; break;
99 case 6: O << "nle"; break;
100 case 7: O << "ord"; break;
101 case 8: O << "eq_uq"; break;
102 case 9: O << "nge"; break;
103 case 0xa: O << "ngt"; break;
104 case 0xb: O << "false"; break;
105 case 0xc: O << "neq_oq"; break;
106 case 0xd: O << "ge"; break;
107 case 0xe: O << "gt"; break;
108 case 0xf: O << "true"; break;
109 case 0x10: O << "eq_os"; break;
110 case 0x11: O << "lt_oq"; break;
111 case 0x12: O << "le_oq"; break;
112 case 0x13: O << "unord_s"; break;
113 case 0x14: O << "neq_us"; break;
114 case 0x15: O << "nlt_uq"; break;
115 case 0x16: O << "nle_uq"; break;
116 case 0x17: O << "ord_s"; break;
117 case 0x18: O << "eq_us"; break;
118 case 0x19: O << "nge_uq"; break;
119 case 0x1a: O << "ngt_uq"; break;
120 case 0x1b: O << "false_os"; break;
121 case 0x1c: O << "neq_os"; break;
122 case 0x1d: O << "ge_oq"; break;
123 case 0x1e: O << "gt_oq"; break;
124 case 0x1f: O << "true_us"; break;
128 /// printPCRelImm - This is used to print an immediate value that ends up
129 /// being encoded as a pc-relative value (e.g. for jumps and calls). These
130 /// print slightly differently than normal immediates. For example, a $ is not
132 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
134 const MCOperand &Op = MI->getOperand(OpNo);
138 assert(Op.isExpr() && "unknown pcrel immediate operand");
139 // If a symbolic branch target was added as a constant expression then print
140 // that address in hex.
141 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
143 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
145 O.write_hex(Address);
148 // Otherwise, just print the expression.
154 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
156 const MCOperand &Op = MI->getOperand(OpNo);
160 O << '%' << getRegisterName(Op.getReg());
163 } else if (Op.isImm()) {
166 // Print X86 immediates as signed values.
167 O << '$' << (int64_t)Op.getImm();
171 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
172 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
175 assert(Op.isExpr() && "unknown operand kind in printOperand");
178 O << '$' << *Op.getExpr();
184 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
186 const MCOperand &BaseReg = MI->getOperand(Op);
187 const MCOperand &IndexReg = MI->getOperand(Op+2);
188 const MCOperand &DispSpec = MI->getOperand(Op+3);
189 const MCOperand &SegReg = MI->getOperand(Op+4);
194 // If this has a segment register, print it.
195 if (SegReg.getReg()) {
196 printOperand(MI, Op+4, O);
200 if (DispSpec.isImm()) {
201 int64_t DispVal = DispSpec.getImm();
202 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
205 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
206 O << *DispSpec.getExpr();
209 if (IndexReg.getReg() || BaseReg.getReg()) {
211 if (BaseReg.getReg())
212 printOperand(MI, Op, O);
214 if (IndexReg.getReg()) {
216 printOperand(MI, Op+2, O);
217 unsigned ScaleVal = MI->getOperand(Op+1).getImm();