1 /*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===*
3 * The LLVM Compiler Infrastructure
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
8 *===----------------------------------------------------------------------===*
10 * This file is part of the X86 Disassembler.
11 * It contains the implementation of the instruction decoder.
12 * Documentation for the disassembler can be found in X86Disassembler.h.
14 *===----------------------------------------------------------------------===*/
16 #include <stdarg.h> /* for va_*() */
17 #include <stdio.h> /* for vsnprintf() */
18 #include <stdlib.h> /* for exit() */
19 #include <string.h> /* for memset() */
21 #include "X86DisassemblerDecoder.h"
23 #include "X86GenDisassemblerTables.inc"
31 #define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
33 #define debug(s) do { } while (0)
38 * contextForAttrs - Client for the instruction context table. Takes a set of
39 * attributes and returns the appropriate decode context.
41 * @param attrMask - Attributes, from the enumeration attributeBits.
42 * @return - The InstructionContext to use when looking up an
43 * an instruction with these attributes.
45 static InstructionContext contextForAttrs(uint8_t attrMask) {
46 return CONTEXTS_SYM[attrMask];
50 * modRMRequired - Reads the appropriate instruction table to determine whether
51 * the ModR/M byte is required to decode a particular instruction.
53 * @param type - The opcode type (i.e., how many bytes it has).
54 * @param insnContext - The context for the instruction, as returned by
56 * @param opcode - The last byte of the instruction's opcode, not counting
57 * ModR/M extensions and escapes.
58 * @return - TRUE if the ModR/M byte is required, FALSE otherwise.
60 static int modRMRequired(OpcodeType type,
61 InstructionContext insnContext,
63 const struct ContextDecision* decision = 0;
67 decision = &ONEBYTE_SYM;
70 decision = &TWOBYTE_SYM;
73 decision = &THREEBYTE38_SYM;
76 decision = &THREEBYTE3A_SYM;
79 decision = &THREEBYTEA6_SYM;
82 decision = &THREEBYTEA7_SYM;
86 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
87 modrm_type != MODRM_ONEENTRY;
91 * decode - Reads the appropriate instruction table to obtain the unique ID of
94 * @param type - See modRMRequired().
95 * @param insnContext - See modRMRequired().
96 * @param opcode - See modRMRequired().
97 * @param modRM - The ModR/M byte if required, or any value if not.
98 * @return - The UID of the instruction, or 0 on failure.
100 static InstrUID decode(OpcodeType type,
101 InstructionContext insnContext,
104 const struct ModRMDecision* dec = 0;
108 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
111 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
114 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
117 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
120 dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
123 dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
127 switch (dec->modrm_type) {
129 debug("Corrupt table! Unknown modrm_type");
132 return modRMTable[dec->instructionIDs];
134 if (modFromModRM(modRM) == 0x3)
135 return modRMTable[dec->instructionIDs+1];
136 return modRMTable[dec->instructionIDs];
138 if (modFromModRM(modRM) == 0x3)
139 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8];
140 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
141 case MODRM_SPLITMISC:
142 if (modFromModRM(modRM) == 0x3)
143 return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8];
144 return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)];
146 return modRMTable[dec->instructionIDs+modRM];
151 * specifierForUID - Given a UID, returns the name and operand specification for
154 * @param uid - The unique ID for the instruction. This should be returned by
155 * decode(); specifierForUID will not check bounds.
156 * @return - A pointer to the specification for that instruction.
158 static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
159 return &INSTRUCTIONS_SYM[uid];
163 * consumeByte - Uses the reader function provided by the user to consume one
164 * byte from the instruction's memory and advance the cursor.
166 * @param insn - The instruction with the reader function to use. The cursor
167 * for this instruction is advanced.
168 * @param byte - A pointer to a pre-allocated memory buffer to be populated
169 * with the data read.
170 * @return - 0 if the read was successful; nonzero otherwise.
172 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
173 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
176 ++(insn->readerCursor);
182 * lookAtByte - Like consumeByte, but does not advance the cursor.
184 * @param insn - See consumeByte().
185 * @param byte - See consumeByte().
186 * @return - See consumeByte().
188 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
189 return insn->reader(insn->readerArg, byte, insn->readerCursor);
192 static void unconsumeByte(struct InternalInstruction* insn) {
193 insn->readerCursor--;
196 #define CONSUME_FUNC(name, type) \
197 static int name(struct InternalInstruction* insn, type* ptr) { \
200 for (offset = 0; offset < sizeof(type); ++offset) { \
202 int ret = insn->reader(insn->readerArg, \
204 insn->readerCursor + offset); \
207 combined = combined | ((uint64_t)byte << (offset * 8)); \
210 insn->readerCursor += sizeof(type); \
215 * consume* - Use the reader function provided by the user to consume data
216 * values of various sizes from the instruction's memory and advance the
217 * cursor appropriately. These readers perform endian conversion.
219 * @param insn - See consumeByte().
220 * @param ptr - A pointer to a pre-allocated memory of appropriate size to
221 * be populated with the data read.
222 * @return - See consumeByte().
224 CONSUME_FUNC(consumeInt8, int8_t)
225 CONSUME_FUNC(consumeInt16, int16_t)
226 CONSUME_FUNC(consumeInt32, int32_t)
227 CONSUME_FUNC(consumeUInt16, uint16_t)
228 CONSUME_FUNC(consumeUInt32, uint32_t)
229 CONSUME_FUNC(consumeUInt64, uint64_t)
232 * dbgprintf - Uses the logging function provided by the user to log a single
233 * message, typically without a carriage-return.
235 * @param insn - The instruction containing the logging function.
236 * @param format - See printf().
237 * @param ... - See printf().
239 static void dbgprintf(struct InternalInstruction* insn,
248 va_start(ap, format);
249 (void)vsnprintf(buffer, sizeof(buffer), format, ap);
252 insn->dlog(insn->dlogArg, buffer);
258 * setPrefixPresent - Marks that a particular prefix is present at a particular
261 * @param insn - The instruction to be marked as having the prefix.
262 * @param prefix - The prefix that is present.
263 * @param location - The location where the prefix is located (in the address
264 * space of the instruction's reader).
266 static void setPrefixPresent(struct InternalInstruction* insn,
270 insn->prefixPresent[prefix] = 1;
271 insn->prefixLocations[prefix] = location;
275 * isPrefixAtLocation - Queries an instruction to determine whether a prefix is
276 * present at a given location.
278 * @param insn - The instruction to be queried.
279 * @param prefix - The prefix.
280 * @param location - The location to query.
281 * @return - Whether the prefix is at that location.
283 static BOOL isPrefixAtLocation(struct InternalInstruction* insn,
287 if (insn->prefixPresent[prefix] == 1 &&
288 insn->prefixLocations[prefix] == location)
295 * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the
296 * instruction as having them. Also sets the instruction's default operand,
297 * address, and other relevant data sizes to report operands correctly.
299 * @param insn - The instruction whose prefixes are to be read.
300 * @return - 0 if the instruction could be read until the end of the prefix
301 * bytes, and no prefixes conflicted; nonzero otherwise.
303 static int readPrefixes(struct InternalInstruction* insn) {
304 BOOL isPrefix = TRUE;
305 BOOL prefixGroups[4] = { FALSE };
306 uint64_t prefixLocation;
309 BOOL hasAdSize = FALSE;
310 BOOL hasOpSize = FALSE;
312 dbgprintf(insn, "readPrefixes()");
315 prefixLocation = insn->readerCursor;
317 /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */
318 if (consumeByte(insn, &byte))
322 * If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
323 * break and let it be disassembled as a normal "instruction".
325 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0)
329 if (insn->readerCursor - 1 == insn->startLocation
330 && (byte == 0xf2 || byte == 0xf3)
331 && !lookAtByte(insn, &nextByte))
334 * If the byte is 0xf2 or 0xf3, and any of the following conditions are
336 * - it is followed by a LOCK (0xf0) prefix
337 * - it is followed by an xchg instruction
338 * then it should be disassembled as a xacquire/xrelease not repne/rep.
340 if ((byte == 0xf2 || byte == 0xf3) &&
341 ((nextByte == 0xf0) |
342 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90)))
343 insn->xAcquireRelease = TRUE;
345 * Also if the byte is 0xf3, and the following condition is met:
346 * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
347 * "mov mem, imm" (opcode 0xc6/0xc7) instructions.
348 * then it should be disassembled as an xrelease not rep.
351 (nextByte == 0x88 || nextByte == 0x89 ||
352 nextByte == 0xc6 || nextByte == 0xc7))
353 insn->xAcquireRelease = TRUE;
354 if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) {
355 if (consumeByte(insn, &nextByte))
357 if (lookAtByte(insn, &nextByte))
361 if (nextByte != 0x0f && nextByte != 0x90)
366 case 0xf0: /* LOCK */
367 case 0xf2: /* REPNE/REPNZ */
368 case 0xf3: /* REP or REPE/REPZ */
370 dbgprintf(insn, "Redundant Group 1 prefix");
371 prefixGroups[0] = TRUE;
372 setPrefixPresent(insn, byte, prefixLocation);
374 case 0x2e: /* CS segment override -OR- Branch not taken */
375 case 0x36: /* SS segment override -OR- Branch taken */
376 case 0x3e: /* DS segment override */
377 case 0x26: /* ES segment override */
378 case 0x64: /* FS segment override */
379 case 0x65: /* GS segment override */
382 insn->segmentOverride = SEG_OVERRIDE_CS;
385 insn->segmentOverride = SEG_OVERRIDE_SS;
388 insn->segmentOverride = SEG_OVERRIDE_DS;
391 insn->segmentOverride = SEG_OVERRIDE_ES;
394 insn->segmentOverride = SEG_OVERRIDE_FS;
397 insn->segmentOverride = SEG_OVERRIDE_GS;
400 debug("Unhandled override");
404 dbgprintf(insn, "Redundant Group 2 prefix");
405 prefixGroups[1] = TRUE;
406 setPrefixPresent(insn, byte, prefixLocation);
408 case 0x66: /* Operand-size override */
410 dbgprintf(insn, "Redundant Group 3 prefix");
411 prefixGroups[2] = TRUE;
413 setPrefixPresent(insn, byte, prefixLocation);
415 case 0x67: /* Address-size override */
417 dbgprintf(insn, "Redundant Group 4 prefix");
418 prefixGroups[3] = TRUE;
420 setPrefixPresent(insn, byte, prefixLocation);
422 default: /* Not a prefix byte */
428 dbgprintf(insn, "Found prefix 0x%hhx", byte);
436 if (lookAtByte(insn, &byte1)) {
437 dbgprintf(insn, "Couldn't read second byte of VEX");
441 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
443 insn->necessaryPrefixLocation = insn->readerCursor - 1;
447 insn->necessaryPrefixLocation = insn->readerCursor - 1;
450 if (insn->vexSize == 3) {
451 insn->vexPrefix[0] = byte;
452 consumeByte(insn, &insn->vexPrefix[1]);
453 consumeByte(insn, &insn->vexPrefix[2]);
455 /* We simulate the REX prefix for simplicity's sake */
457 if (insn->mode == MODE_64BIT) {
458 insn->rexPrefix = 0x40
459 | (wFromVEX3of3(insn->vexPrefix[2]) << 3)
460 | (rFromVEX2of3(insn->vexPrefix[1]) << 2)
461 | (xFromVEX2of3(insn->vexPrefix[1]) << 1)
462 | (bFromVEX2of3(insn->vexPrefix[1]) << 0);
465 switch (ppFromVEX3of3(insn->vexPrefix[2]))
474 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1], insn->vexPrefix[2]);
477 else if (byte == 0xc5) {
480 if (lookAtByte(insn, &byte1)) {
481 dbgprintf(insn, "Couldn't read second byte of VEX");
485 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) {
492 if (insn->vexSize == 2) {
493 insn->vexPrefix[0] = byte;
494 consumeByte(insn, &insn->vexPrefix[1]);
496 if (insn->mode == MODE_64BIT) {
497 insn->rexPrefix = 0x40
498 | (rFromVEX2of2(insn->vexPrefix[1]) << 2);
501 switch (ppFromVEX2of2(insn->vexPrefix[1]))
510 dbgprintf(insn, "Found VEX prefix 0x%hhx 0x%hhx", insn->vexPrefix[0], insn->vexPrefix[1]);
514 if (insn->mode == MODE_64BIT) {
515 if ((byte & 0xf0) == 0x40) {
518 if (lookAtByte(insn, &opcodeByte) || ((opcodeByte & 0xf0) == 0x40)) {
519 dbgprintf(insn, "Redundant REX prefix");
523 insn->rexPrefix = byte;
524 insn->necessaryPrefixLocation = insn->readerCursor - 2;
526 dbgprintf(insn, "Found REX prefix 0x%hhx", byte);
529 insn->necessaryPrefixLocation = insn->readerCursor - 1;
533 insn->necessaryPrefixLocation = insn->readerCursor - 1;
537 if (insn->mode == MODE_16BIT) {
538 insn->registerSize = (hasOpSize ? 4 : 2);
539 insn->addressSize = (hasAdSize ? 4 : 2);
540 insn->displacementSize = (hasAdSize ? 4 : 2);
541 insn->immediateSize = (hasOpSize ? 4 : 2);
542 } else if (insn->mode == MODE_32BIT) {
543 insn->registerSize = (hasOpSize ? 2 : 4);
544 insn->addressSize = (hasAdSize ? 2 : 4);
545 insn->displacementSize = (hasAdSize ? 2 : 4);
546 insn->immediateSize = (hasOpSize ? 2 : 4);
547 } else if (insn->mode == MODE_64BIT) {
548 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
549 insn->registerSize = 8;
550 insn->addressSize = (hasAdSize ? 4 : 8);
551 insn->displacementSize = 4;
552 insn->immediateSize = 4;
553 } else if (insn->rexPrefix) {
554 insn->registerSize = (hasOpSize ? 2 : 4);
555 insn->addressSize = (hasAdSize ? 4 : 8);
556 insn->displacementSize = (hasOpSize ? 2 : 4);
557 insn->immediateSize = (hasOpSize ? 2 : 4);
559 insn->registerSize = (hasOpSize ? 2 : 4);
560 insn->addressSize = (hasAdSize ? 4 : 8);
561 insn->displacementSize = (hasOpSize ? 2 : 4);
562 insn->immediateSize = (hasOpSize ? 2 : 4);
570 * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of
571 * extended or escape opcodes).
573 * @param insn - The instruction whose opcode is to be read.
574 * @return - 0 if the opcode could be read successfully; nonzero otherwise.
576 static int readOpcode(struct InternalInstruction* insn) {
577 /* Determine the length of the primary opcode */
581 dbgprintf(insn, "readOpcode()");
583 insn->opcodeType = ONEBYTE;
585 if (insn->vexSize == 3)
587 switch (mmmmmFromVEX2of3(insn->vexPrefix[1]))
590 dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", mmmmmFromVEX2of3(insn->vexPrefix[1]));
595 insn->twoByteEscape = 0x0f;
596 insn->opcodeType = TWOBYTE;
597 return consumeByte(insn, &insn->opcode);
599 insn->twoByteEscape = 0x0f;
600 insn->threeByteEscape = 0x38;
601 insn->opcodeType = THREEBYTE_38;
602 return consumeByte(insn, &insn->opcode);
604 insn->twoByteEscape = 0x0f;
605 insn->threeByteEscape = 0x3a;
606 insn->opcodeType = THREEBYTE_3A;
607 return consumeByte(insn, &insn->opcode);
610 else if (insn->vexSize == 2)
612 insn->twoByteEscape = 0x0f;
613 insn->opcodeType = TWOBYTE;
614 return consumeByte(insn, &insn->opcode);
617 if (consumeByte(insn, ¤t))
620 if (current == 0x0f) {
621 dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current);
623 insn->twoByteEscape = current;
625 if (consumeByte(insn, ¤t))
628 if (current == 0x38) {
629 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
631 insn->threeByteEscape = current;
633 if (consumeByte(insn, ¤t))
636 insn->opcodeType = THREEBYTE_38;
637 } else if (current == 0x3a) {
638 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
640 insn->threeByteEscape = current;
642 if (consumeByte(insn, ¤t))
645 insn->opcodeType = THREEBYTE_3A;
646 } else if (current == 0xa6) {
647 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
649 insn->threeByteEscape = current;
651 if (consumeByte(insn, ¤t))
654 insn->opcodeType = THREEBYTE_A6;
655 } else if (current == 0xa7) {
656 dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
658 insn->threeByteEscape = current;
660 if (consumeByte(insn, ¤t))
663 insn->opcodeType = THREEBYTE_A7;
665 dbgprintf(insn, "Didn't find a three-byte escape prefix");
667 insn->opcodeType = TWOBYTE;
672 * At this point we have consumed the full opcode.
673 * Anything we consume from here on must be unconsumed.
676 insn->opcode = current;
681 static int readModRM(struct InternalInstruction* insn);
684 * getIDWithAttrMask - Determines the ID of an instruction, consuming
685 * the ModR/M byte as appropriate for extended and escape opcodes,
686 * and using a supplied attribute mask.
688 * @param instructionID - A pointer whose target is filled in with the ID of the
690 * @param insn - The instruction whose ID is to be determined.
691 * @param attrMask - The attribute mask to search.
692 * @return - 0 if the ModR/M could be read when needed or was not
693 * needed; nonzero otherwise.
695 static int getIDWithAttrMask(uint16_t* instructionID,
696 struct InternalInstruction* insn,
698 BOOL hasModRMExtension;
700 uint8_t instructionClass;
702 instructionClass = contextForAttrs(attrMask);
704 hasModRMExtension = modRMRequired(insn->opcodeType,
708 if (hasModRMExtension) {
712 *instructionID = decode(insn->opcodeType,
717 *instructionID = decode(insn->opcodeType,
727 * is16BitEquivalent - Determines whether two instruction names refer to
728 * equivalent instructions but one is 16-bit whereas the other is not.
730 * @param orig - The instruction that is not 16-bit
731 * @param equiv - The instruction that is 16-bit
733 static BOOL is16BitEquivalent(const char* orig, const char* equiv) {
737 if (orig[i] == '\0' && equiv[i] == '\0')
739 if (orig[i] == '\0' || equiv[i] == '\0')
741 if (orig[i] != equiv[i]) {
742 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
744 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
746 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
754 * getID - Determines the ID of an instruction, consuming the ModR/M byte as
755 * appropriate for extended and escape opcodes. Determines the attributes and
756 * context for the instruction before doing so.
758 * @param insn - The instruction whose ID is to be determined.
759 * @return - 0 if the ModR/M could be read when needed or was not needed;
762 static int getID(struct InternalInstruction* insn, const void *miiArg) {
764 uint16_t instructionID;
766 dbgprintf(insn, "getID()");
768 attrMask = ATTR_NONE;
770 if (insn->mode == MODE_64BIT)
771 attrMask |= ATTR_64BIT;
774 attrMask |= ATTR_VEX;
776 if (insn->vexSize == 3) {
777 switch (ppFromVEX3of3(insn->vexPrefix[2])) {
779 attrMask |= ATTR_OPSIZE;
789 if (lFromVEX3of3(insn->vexPrefix[2]))
790 attrMask |= ATTR_VEXL;
792 else if (insn->vexSize == 2) {
793 switch (ppFromVEX2of2(insn->vexPrefix[1])) {
795 attrMask |= ATTR_OPSIZE;
805 if (lFromVEX2of2(insn->vexPrefix[1]))
806 attrMask |= ATTR_VEXL;
813 if (isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation))
814 attrMask |= ATTR_OPSIZE;
815 else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation))
816 attrMask |= ATTR_ADSIZE;
817 else if (isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation))
819 else if (isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation))
823 if (insn->rexPrefix & 0x08)
824 attrMask |= ATTR_REXW;
826 if (getIDWithAttrMask(&instructionID, insn, attrMask))
829 /* The following clauses compensate for limitations of the tables. */
831 if ((attrMask & ATTR_VEXL) && (attrMask & ATTR_REXW) &&
832 !(attrMask & ATTR_OPSIZE)) {
834 * Some VEX instructions ignore the L-bit, but use the W-bit. Normally L-bit
835 * has precedence since there are no L-bit with W-bit entries in the tables.
836 * So if the L-bit isn't significant we should use the W-bit instead.
837 * We only need to do this if the instruction doesn't specify OpSize since
838 * there is a VEX_L_W_OPSIZE table.
841 const struct InstructionSpecifier *spec;
842 uint16_t instructionIDWithWBit;
843 const struct InstructionSpecifier *specWithWBit;
845 spec = specifierForUID(instructionID);
847 if (getIDWithAttrMask(&instructionIDWithWBit,
849 (attrMask & (~ATTR_VEXL)) | ATTR_REXW)) {
850 insn->instructionID = instructionID;
855 specWithWBit = specifierForUID(instructionIDWithWBit);
857 if (instructionID != instructionIDWithWBit) {
858 insn->instructionID = instructionIDWithWBit;
859 insn->spec = specWithWBit;
861 insn->instructionID = instructionID;
867 if (insn->prefixPresent[0x66] && !(attrMask & ATTR_OPSIZE)) {
869 * The instruction tables make no distinction between instructions that
870 * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
871 * particular spot (i.e., many MMX operations). In general we're
872 * conservative, but in the specific case where OpSize is present but not
873 * in the right place we check if there's a 16-bit operation.
876 const struct InstructionSpecifier *spec;
877 uint16_t instructionIDWithOpsize;
878 const char *specName, *specWithOpSizeName;
880 spec = specifierForUID(instructionID);
882 if (getIDWithAttrMask(&instructionIDWithOpsize,
884 attrMask | ATTR_OPSIZE)) {
886 * ModRM required with OpSize but not present; give up and return version
890 insn->instructionID = instructionID;
895 specName = x86DisassemblerGetInstrName(instructionID, miiArg);
897 x86DisassemblerGetInstrName(instructionIDWithOpsize, miiArg);
899 if (is16BitEquivalent(specName, specWithOpSizeName)) {
900 insn->instructionID = instructionIDWithOpsize;
901 insn->spec = specifierForUID(instructionIDWithOpsize);
903 insn->instructionID = instructionID;
909 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
910 insn->rexPrefix & 0x01) {
912 * NOOP shouldn't decode as NOOP if REX.b is set. Instead
913 * it should decode as XCHG %r8, %eax.
916 const struct InstructionSpecifier *spec;
917 uint16_t instructionIDWithNewOpcode;
918 const struct InstructionSpecifier *specWithNewOpcode;
920 spec = specifierForUID(instructionID);
922 /* Borrow opcode from one of the other XCHGar opcodes */
925 if (getIDWithAttrMask(&instructionIDWithNewOpcode,
930 insn->instructionID = instructionID;
935 specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);
940 insn->instructionID = instructionIDWithNewOpcode;
941 insn->spec = specWithNewOpcode;
946 insn->instructionID = instructionID;
947 insn->spec = specifierForUID(insn->instructionID);
953 * readSIB - Consumes the SIB byte to determine addressing information for an
956 * @param insn - The instruction whose SIB byte is to be read.
957 * @return - 0 if the SIB byte was successfully read; nonzero otherwise.
959 static int readSIB(struct InternalInstruction* insn) {
960 SIBIndex sibIndexBase = 0;
961 SIBBase sibBaseBase = 0;
964 dbgprintf(insn, "readSIB()");
966 if (insn->consumedSIB)
969 insn->consumedSIB = TRUE;
971 switch (insn->addressSize) {
973 dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode");
977 sibIndexBase = SIB_INDEX_EAX;
978 sibBaseBase = SIB_BASE_EAX;
981 sibIndexBase = SIB_INDEX_RAX;
982 sibBaseBase = SIB_BASE_RAX;
986 if (consumeByte(insn, &insn->sib))
989 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3);
993 insn->sibIndex = SIB_INDEX_NONE;
996 insn->sibIndex = (SIBIndex)(sibIndexBase + index);
997 if (insn->sibIndex == SIB_INDEX_sib ||
998 insn->sibIndex == SIB_INDEX_sib64)
999 insn->sibIndex = SIB_INDEX_NONE;
1003 switch (scaleFromSIB(insn->sib)) {
1018 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
1022 switch (modFromModRM(insn->modRM)) {
1024 insn->eaDisplacement = EA_DISP_32;
1025 insn->sibBase = SIB_BASE_NONE;
1028 insn->eaDisplacement = EA_DISP_8;
1029 insn->sibBase = (insn->addressSize == 4 ?
1030 SIB_BASE_EBP : SIB_BASE_RBP);
1033 insn->eaDisplacement = EA_DISP_32;
1034 insn->sibBase = (insn->addressSize == 4 ?
1035 SIB_BASE_EBP : SIB_BASE_RBP);
1038 debug("Cannot have Mod = 0b11 and a SIB byte");
1043 insn->sibBase = (SIBBase)(sibBaseBase + base);
1051 * readDisplacement - Consumes the displacement of an instruction.
1053 * @param insn - The instruction whose displacement is to be read.
1054 * @return - 0 if the displacement byte was successfully read; nonzero
1057 static int readDisplacement(struct InternalInstruction* insn) {
1062 dbgprintf(insn, "readDisplacement()");
1064 if (insn->consumedDisplacement)
1067 insn->consumedDisplacement = TRUE;
1068 insn->displacementOffset = insn->readerCursor - insn->startLocation;
1070 switch (insn->eaDisplacement) {
1072 insn->consumedDisplacement = FALSE;
1075 if (consumeInt8(insn, &d8))
1077 insn->displacement = d8;
1080 if (consumeInt16(insn, &d16))
1082 insn->displacement = d16;
1085 if (consumeInt32(insn, &d32))
1087 insn->displacement = d32;
1091 insn->consumedDisplacement = TRUE;
1096 * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and
1097 * displacement) for an instruction and interprets it.
1099 * @param insn - The instruction whose addressing information is to be read.
1100 * @return - 0 if the information was successfully read; nonzero otherwise.
1102 static int readModRM(struct InternalInstruction* insn) {
1103 uint8_t mod, rm, reg;
1105 dbgprintf(insn, "readModRM()");
1107 if (insn->consumedModRM)
1110 if (consumeByte(insn, &insn->modRM))
1112 insn->consumedModRM = TRUE;
1114 mod = modFromModRM(insn->modRM);
1115 rm = rmFromModRM(insn->modRM);
1116 reg = regFromModRM(insn->modRM);
1119 * This goes by insn->registerSize to pick the correct register, which messes
1120 * up if we're using (say) XMM or 8-bit register operands. That gets fixed in
1123 switch (insn->registerSize) {
1125 insn->regBase = MODRM_REG_AX;
1126 insn->eaRegBase = EA_REG_AX;
1129 insn->regBase = MODRM_REG_EAX;
1130 insn->eaRegBase = EA_REG_EAX;
1133 insn->regBase = MODRM_REG_RAX;
1134 insn->eaRegBase = EA_REG_RAX;
1138 reg |= rFromREX(insn->rexPrefix) << 3;
1139 rm |= bFromREX(insn->rexPrefix) << 3;
1141 insn->reg = (Reg)(insn->regBase + reg);
1143 switch (insn->addressSize) {
1145 insn->eaBaseBase = EA_BASE_BX_SI;
1150 insn->eaBase = EA_BASE_NONE;
1151 insn->eaDisplacement = EA_DISP_16;
1152 if (readDisplacement(insn))
1155 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1156 insn->eaDisplacement = EA_DISP_NONE;
1160 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1161 insn->eaDisplacement = EA_DISP_8;
1162 if (readDisplacement(insn))
1166 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1167 insn->eaDisplacement = EA_DISP_16;
1168 if (readDisplacement(insn))
1172 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1173 if (readDisplacement(insn))
1180 insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
1184 insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */
1187 case 0xc: /* in case REXW.b is set */
1188 insn->eaBase = (insn->addressSize == 4 ?
1189 EA_BASE_sib : EA_BASE_sib64);
1191 if (readDisplacement(insn))
1195 insn->eaBase = EA_BASE_NONE;
1196 insn->eaDisplacement = EA_DISP_32;
1197 if (readDisplacement(insn))
1201 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1207 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
1210 case 0xc: /* in case REXW.b is set */
1211 insn->eaBase = EA_BASE_sib;
1213 if (readDisplacement(insn))
1217 insn->eaBase = (EABase)(insn->eaBaseBase + rm);
1218 if (readDisplacement(insn))
1224 insn->eaDisplacement = EA_DISP_NONE;
1225 insn->eaBase = (EABase)(insn->eaRegBase + rm);
1229 } /* switch (insn->addressSize) */
1234 #define GENERIC_FIXUP_FUNC(name, base, prefix) \
1235 static uint8_t name(struct InternalInstruction *insn, \
1242 debug("Unhandled register type"); \
1246 return base + index; \
1248 if (insn->rexPrefix && \
1249 index >= 4 && index <= 7) { \
1250 return prefix##_SPL + (index - 4); \
1252 return prefix##_AL + index; \
1255 return prefix##_AX + index; \
1257 return prefix##_EAX + index; \
1259 return prefix##_RAX + index; \
1261 return prefix##_ZMM0 + index; \
1263 return prefix##_YMM0 + index; \
1268 return prefix##_XMM0 + index; \
1274 return prefix##_MM0 + index; \
1275 case TYPE_SEGMENTREG: \
1278 return prefix##_ES + index; \
1279 case TYPE_DEBUGREG: \
1282 return prefix##_DR0 + index; \
1283 case TYPE_CONTROLREG: \
1286 return prefix##_CR0 + index; \
1291 * fixup*Value - Consults an operand type to determine the meaning of the
1292 * reg or R/M field. If the operand is an XMM operand, for example, an
1293 * operand would be XMM0 instead of AX, which readModRM() would otherwise
1294 * misinterpret it as.
1296 * @param insn - The instruction containing the operand.
1297 * @param type - The operand type.
1298 * @param index - The existing value of the field as reported by readModRM().
1299 * @param valid - The address of a uint8_t. The target is set to 1 if the
1300 * field is valid for the register class; 0 if not.
1301 * @return - The proper value.
1303 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
1304 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
1307 * fixupReg - Consults an operand specifier to determine which of the
1308 * fixup*Value functions to use in correcting readModRM()'ss interpretation.
1310 * @param insn - See fixup*Value().
1311 * @param op - The operand specifier.
1312 * @return - 0 if fixup was successful; -1 if the register returned was
1313 * invalid for its class.
1315 static int fixupReg(struct InternalInstruction *insn,
1316 const struct OperandSpecifier *op) {
1319 dbgprintf(insn, "fixupReg()");
1321 switch ((OperandEncoding)op->encoding) {
1323 debug("Expected a REG or R/M encoding in fixupReg");
1326 insn->vvvv = (Reg)fixupRegValue(insn,
1327 (OperandType)op->type,
1334 insn->reg = (Reg)fixupRegValue(insn,
1335 (OperandType)op->type,
1336 insn->reg - insn->regBase,
1342 if (insn->eaBase >= insn->eaRegBase) {
1343 insn->eaBase = (EABase)fixupRMValue(insn,
1344 (OperandType)op->type,
1345 insn->eaBase - insn->eaRegBase,
1357 * readOpcodeModifier - Reads an operand from the opcode field of an
1358 * instruction. Handles AddRegFrm instructions.
1360 * @param insn - The instruction whose opcode field is to be read.
1361 * @param inModRM - Indicates that the opcode field is to be read from the
1362 * ModR/M extension; useful for escape opcodes
1363 * @return - 0 on success; nonzero otherwise.
1365 static int readOpcodeModifier(struct InternalInstruction* insn) {
1366 dbgprintf(insn, "readOpcodeModifier()");
1368 if (insn->consumedOpcodeModifier)
1371 insn->consumedOpcodeModifier = TRUE;
1373 switch (insn->spec->modifierType) {
1375 debug("Unknown modifier type.");
1378 debug("No modifier but an operand expects one.");
1380 case MODIFIER_OPCODE:
1381 insn->opcodeModifier = insn->opcode - insn->spec->modifierBase;
1383 case MODIFIER_MODRM:
1384 insn->opcodeModifier = insn->modRM - insn->spec->modifierBase;
1390 * readOpcodeRegister - Reads an operand from the opcode field of an
1391 * instruction and interprets it appropriately given the operand width.
1392 * Handles AddRegFrm instructions.
1394 * @param insn - See readOpcodeModifier().
1395 * @param size - The width (in bytes) of the register being specified.
1396 * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1398 * @return - 0 on success; nonzero otherwise.
1400 static int readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) {
1401 dbgprintf(insn, "readOpcodeRegister()");
1403 if (readOpcodeModifier(insn))
1407 size = insn->registerSize;
1411 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3)
1412 | insn->opcodeModifier));
1413 if (insn->rexPrefix &&
1414 insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1415 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1416 insn->opcodeRegister = (Reg)(MODRM_REG_SPL
1417 + (insn->opcodeRegister - MODRM_REG_AL - 4));
1422 insn->opcodeRegister = (Reg)(MODRM_REG_AX
1423 + ((bFromREX(insn->rexPrefix) << 3)
1424 | insn->opcodeModifier));
1427 insn->opcodeRegister = (Reg)(MODRM_REG_EAX
1428 + ((bFromREX(insn->rexPrefix) << 3)
1429 | insn->opcodeModifier));
1432 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
1433 + ((bFromREX(insn->rexPrefix) << 3)
1434 | insn->opcodeModifier));
1442 * readImmediate - Consumes an immediate operand from an instruction, given the
1443 * desired operand size.
1445 * @param insn - The instruction whose operand is to be read.
1446 * @param size - The width (in bytes) of the operand.
1447 * @return - 0 if the immediate was successfully consumed; nonzero
1450 static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
1456 dbgprintf(insn, "readImmediate()");
1458 if (insn->numImmediatesConsumed == 2) {
1459 debug("Already consumed two immediates");
1464 size = insn->immediateSize;
1466 insn->immediateSize = size;
1467 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1471 if (consumeByte(insn, &imm8))
1473 insn->immediates[insn->numImmediatesConsumed] = imm8;
1476 if (consumeUInt16(insn, &imm16))
1478 insn->immediates[insn->numImmediatesConsumed] = imm16;
1481 if (consumeUInt32(insn, &imm32))
1483 insn->immediates[insn->numImmediatesConsumed] = imm32;
1486 if (consumeUInt64(insn, &imm64))
1488 insn->immediates[insn->numImmediatesConsumed] = imm64;
1492 insn->numImmediatesConsumed++;
1498 * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix.
1500 * @param insn - The instruction whose operand is to be read.
1501 * @return - 0 if the vvvv was successfully consumed; nonzero
1504 static int readVVVV(struct InternalInstruction* insn) {
1505 dbgprintf(insn, "readVVVV()");
1507 if (insn->vexSize == 3)
1508 insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]);
1509 else if (insn->vexSize == 2)
1510 insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]);
1514 if (insn->mode != MODE_64BIT)
1521 * readOperands - Consults the specifier for an instruction and consumes all
1522 * operands for that instruction, interpreting them as it goes.
1524 * @param insn - The instruction whose operands are to be read and interpreted.
1525 * @return - 0 if all operands could be read; nonzero otherwise.
1527 static int readOperands(struct InternalInstruction* insn) {
1529 int hasVVVV, needVVVV;
1532 dbgprintf(insn, "readOperands()");
1534 /* If non-zero vvvv specified, need to make sure one of the operands
1536 hasVVVV = !readVVVV(insn);
1537 needVVVV = hasVVVV && (insn->vvvv != 0);
1539 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
1540 switch (x86OperandSets[insn->spec->operands][index].encoding) {
1545 if (readModRM(insn))
1547 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1556 dbgprintf(insn, "We currently don't hande code-offset encodings");
1560 /* Saw a register immediate so don't read again and instead split the
1561 previous immediate. FIXME: This is a hack. */
1562 insn->immediates[insn->numImmediatesConsumed] =
1563 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1564 ++insn->numImmediatesConsumed;
1567 if (readImmediate(insn, 1))
1569 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM3 &&
1570 insn->immediates[insn->numImmediatesConsumed - 1] > 7)
1572 if (x86OperandSets[insn->spec->operands][index].type == TYPE_IMM5 &&
1573 insn->immediates[insn->numImmediatesConsumed - 1] > 31)
1575 if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 ||
1576 x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256)
1580 if (readImmediate(insn, 2))
1584 if (readImmediate(insn, 4))
1588 if (readImmediate(insn, 8))
1592 if (readImmediate(insn, insn->immediateSize))
1596 if (readImmediate(insn, insn->addressSize))
1600 if (readOpcodeRegister(insn, 1))
1604 if (readOpcodeRegister(insn, 2))
1608 if (readOpcodeRegister(insn, 4))
1612 if (readOpcodeRegister(insn, 8))
1616 if (readOpcodeRegister(insn, 0))
1620 if (readOpcodeModifier(insn))
1624 needVVVV = 0; /* Mark that we have found a VVVV operand. */
1627 if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index]))
1633 dbgprintf(insn, "Encountered an operand with an unknown encoding.");
1638 /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */
1639 if (needVVVV) return -1;
1645 * decodeInstruction - Reads and interprets a full instruction provided by the
1648 * @param insn - A pointer to the instruction to be populated. Must be
1650 * @param reader - The function to be used to read the instruction's bytes.
1651 * @param readerArg - A generic argument to be passed to the reader to store
1652 * any internal state.
1653 * @param logger - If non-NULL, the function to be used to write log messages
1655 * @param loggerArg - A generic argument to be passed to the logger to store
1656 * any internal state.
1657 * @param startLoc - The address (in the reader's address space) of the first
1658 * byte in the instruction.
1659 * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to
1660 * decode the instruction in.
1661 * @return - 0 if the instruction's memory could be read; nonzero if
1664 int decodeInstruction(struct InternalInstruction* insn,
1665 byteReader_t reader,
1666 const void* readerArg,
1671 DisassemblerMode mode) {
1672 memset(insn, 0, sizeof(struct InternalInstruction));
1674 insn->reader = reader;
1675 insn->readerArg = readerArg;
1676 insn->dlog = logger;
1677 insn->dlogArg = loggerArg;
1678 insn->startLocation = startLoc;
1679 insn->readerCursor = startLoc;
1681 insn->numImmediatesConsumed = 0;
1683 if (readPrefixes(insn) ||
1685 getID(insn, miiArg) ||
1686 insn->instructionID == 0 ||
1690 insn->operands = &x86OperandSets[insn->spec->operands][0];
1692 insn->length = insn->readerCursor - insn->startLocation;
1694 dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu",
1695 startLoc, insn->readerCursor, insn->length);
1697 if (insn->length > 15)
1698 dbgprintf(insn, "Instruction exceeds 15-byte limit");