1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "X86Subtarget.h"
13 #include "llvm/Target/TargetRegistry.h"
14 #include "llvm/Target/TargetAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
33 class X86ATTAsmParser : public TargetAsmParser {
41 MCAsmParser &getParser() const { return Parser; }
43 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
49 X86Operand *ParseOperand();
50 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
52 bool ParseDirectiveWord(unsigned Size, SMLoc L);
54 bool MatchAndEmitInstruction(SMLoc IDLoc,
55 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
58 /// @name Auto-generated Matcher Functions
61 #define GET_ASSEMBLER_HEADER
62 #include "X86GenAsmMatcher.inc"
67 X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM)
68 : TargetAsmParser(T), Parser(parser), TM(TM) {
70 // Initialize the set of available features.
71 setAvailableFeatures(ComputeAvailableFeatures(
72 &TM.getSubtarget<X86Subtarget>()));
75 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
76 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
78 virtual bool ParseDirective(AsmToken DirectiveID);
81 class X86_32ATTAsmParser : public X86ATTAsmParser {
83 X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
84 : X86ATTAsmParser(T, Parser, TM) {
89 class X86_64ATTAsmParser : public X86ATTAsmParser {
91 X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
92 : X86ATTAsmParser(T, Parser, TM) {
97 } // end anonymous namespace
99 /// @name Auto-generated Match Functions
102 static unsigned MatchRegisterName(StringRef Name);
108 /// X86Operand - Instances of this class represent a parsed X86 machine
110 struct X86Operand : public MCParsedAsmOperand {
118 SMLoc StartLoc, EndLoc;
143 X86Operand(KindTy K, SMLoc Start, SMLoc End)
144 : Kind(K), StartLoc(Start), EndLoc(End) {}
146 /// getStartLoc - Get the location of the first token of this operand.
147 SMLoc getStartLoc() const { return StartLoc; }
148 /// getEndLoc - Get the location of the last token of this operand.
149 SMLoc getEndLoc() const { return EndLoc; }
151 virtual void dump(raw_ostream &OS) const {}
153 StringRef getToken() const {
154 assert(Kind == Token && "Invalid access!");
155 return StringRef(Tok.Data, Tok.Length);
157 void setTokenValue(StringRef Value) {
158 assert(Kind == Token && "Invalid access!");
159 Tok.Data = Value.data();
160 Tok.Length = Value.size();
163 unsigned getReg() const {
164 assert(Kind == Register && "Invalid access!");
168 const MCExpr *getImm() const {
169 assert(Kind == Immediate && "Invalid access!");
173 const MCExpr *getMemDisp() const {
174 assert(Kind == Memory && "Invalid access!");
177 unsigned getMemSegReg() const {
178 assert(Kind == Memory && "Invalid access!");
181 unsigned getMemBaseReg() const {
182 assert(Kind == Memory && "Invalid access!");
185 unsigned getMemIndexReg() const {
186 assert(Kind == Memory && "Invalid access!");
189 unsigned getMemScale() const {
190 assert(Kind == Memory && "Invalid access!");
194 bool isToken() const {return Kind == Token; }
196 bool isImm() const { return Kind == Immediate; }
198 bool isImmSExti16i8() const {
202 // If this isn't a constant expr, just assume it fits and let relaxation
204 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
208 // Otherwise, check the value is in a range that makes sense for this
210 uint64_t Value = CE->getValue();
211 return (( Value <= 0x000000000000007FULL)||
212 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
213 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
215 bool isImmSExti32i8() const {
219 // If this isn't a constant expr, just assume it fits and let relaxation
221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
225 // Otherwise, check the value is in a range that makes sense for this
227 uint64_t Value = CE->getValue();
228 return (( Value <= 0x000000000000007FULL)||
229 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
230 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
232 bool isImmSExti64i8() const {
236 // If this isn't a constant expr, just assume it fits and let relaxation
238 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
242 // Otherwise, check the value is in a range that makes sense for this
244 uint64_t Value = CE->getValue();
245 return (( Value <= 0x000000000000007FULL)||
246 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
248 bool isImmSExti64i32() const {
252 // If this isn't a constant expr, just assume it fits and let relaxation
254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
258 // Otherwise, check the value is in a range that makes sense for this
260 uint64_t Value = CE->getValue();
261 return (( Value <= 0x000000007FFFFFFFULL)||
262 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
265 bool isMem() const { return Kind == Memory; }
267 bool isAbsMem() const {
268 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
269 !getMemIndexReg() && getMemScale() == 1;
272 bool isReg() const { return Kind == Register; }
274 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
275 // Add as immediates when possible.
276 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
277 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
279 Inst.addOperand(MCOperand::CreateExpr(Expr));
282 void addRegOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(getReg()));
287 void addImmOperands(MCInst &Inst, unsigned N) const {
288 assert(N == 1 && "Invalid number of operands!");
289 addExpr(Inst, getImm());
292 void addMemOperands(MCInst &Inst, unsigned N) const {
293 assert((N == 5) && "Invalid number of operands!");
294 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
295 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
296 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
297 addExpr(Inst, getMemDisp());
298 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
301 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
302 assert((N == 1) && "Invalid number of operands!");
303 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
306 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
307 X86Operand *Res = new X86Operand(Token, Loc, Loc);
308 Res->Tok.Data = Str.data();
309 Res->Tok.Length = Str.size();
313 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
314 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
315 Res->Reg.RegNo = RegNo;
319 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
320 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
325 /// Create an absolute memory operand.
326 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
328 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
330 Res->Mem.Disp = Disp;
331 Res->Mem.BaseReg = 0;
332 Res->Mem.IndexReg = 0;
337 /// Create a generalized memory operand.
338 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
339 unsigned BaseReg, unsigned IndexReg,
340 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
341 // We should never just have a displacement, that should be parsed as an
342 // absolute memory operand.
343 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
345 // The scale should always be one of {1,2,4,8}.
346 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
348 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
349 Res->Mem.SegReg = SegReg;
350 Res->Mem.Disp = Disp;
351 Res->Mem.BaseReg = BaseReg;
352 Res->Mem.IndexReg = IndexReg;
353 Res->Mem.Scale = Scale;
358 } // end anonymous namespace.
361 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
362 SMLoc &StartLoc, SMLoc &EndLoc) {
364 const AsmToken &TokPercent = Parser.getTok();
365 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
366 StartLoc = TokPercent.getLoc();
367 Parser.Lex(); // Eat percent token.
369 const AsmToken &Tok = Parser.getTok();
370 if (Tok.isNot(AsmToken::Identifier))
371 return Error(Tok.getLoc(), "invalid register name");
373 // FIXME: Validate register for the current architecture; we have to do
374 // validation later, so maybe there is no need for this here.
375 RegNo = MatchRegisterName(Tok.getString());
377 // If the match failed, try the register name as lowercase.
379 RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
381 // FIXME: This should be done using Requires<In32BitMode> and
382 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
383 // can be also checked.
384 if (RegNo == X86::RIZ && !Is64Bit)
385 return Error(Tok.getLoc(), "riz register in 64-bit mode only");
387 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
388 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
390 EndLoc = Tok.getLoc();
391 Parser.Lex(); // Eat 'st'
393 // Check to see if we have '(4)' after %st.
394 if (getLexer().isNot(AsmToken::LParen))
399 const AsmToken &IntTok = Parser.getTok();
400 if (IntTok.isNot(AsmToken::Integer))
401 return Error(IntTok.getLoc(), "expected stack index");
402 switch (IntTok.getIntVal()) {
403 case 0: RegNo = X86::ST0; break;
404 case 1: RegNo = X86::ST1; break;
405 case 2: RegNo = X86::ST2; break;
406 case 3: RegNo = X86::ST3; break;
407 case 4: RegNo = X86::ST4; break;
408 case 5: RegNo = X86::ST5; break;
409 case 6: RegNo = X86::ST6; break;
410 case 7: RegNo = X86::ST7; break;
411 default: return Error(IntTok.getLoc(), "invalid stack index");
414 if (getParser().Lex().isNot(AsmToken::RParen))
415 return Error(Parser.getTok().getLoc(), "expected ')'");
417 EndLoc = Tok.getLoc();
418 Parser.Lex(); // Eat ')'
422 // If this is "db[0-7]", match it as an alias
424 if (RegNo == 0 && Tok.getString().size() == 3 &&
425 Tok.getString().startswith("db")) {
426 switch (Tok.getString()[2]) {
427 case '0': RegNo = X86::DR0; break;
428 case '1': RegNo = X86::DR1; break;
429 case '2': RegNo = X86::DR2; break;
430 case '3': RegNo = X86::DR3; break;
431 case '4': RegNo = X86::DR4; break;
432 case '5': RegNo = X86::DR5; break;
433 case '6': RegNo = X86::DR6; break;
434 case '7': RegNo = X86::DR7; break;
438 EndLoc = Tok.getLoc();
439 Parser.Lex(); // Eat it.
445 return Error(Tok.getLoc(), "invalid register name");
447 EndLoc = Tok.getLoc();
448 Parser.Lex(); // Eat identifier token.
452 X86Operand *X86ATTAsmParser::ParseOperand() {
453 switch (getLexer().getKind()) {
455 // Parse a memory operand with no segment register.
456 return ParseMemOperand(0, Parser.getTok().getLoc());
457 case AsmToken::Percent: {
458 // Read the register.
461 if (ParseRegister(RegNo, Start, End)) return 0;
462 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
463 Error(Start, "eiz and riz can only be used as index registers");
467 // If this is a segment register followed by a ':', then this is the start
468 // of a memory reference, otherwise this is a normal register reference.
469 if (getLexer().isNot(AsmToken::Colon))
470 return X86Operand::CreateReg(RegNo, Start, End);
473 getParser().Lex(); // Eat the colon.
474 return ParseMemOperand(RegNo, Start);
476 case AsmToken::Dollar: {
478 SMLoc Start = Parser.getTok().getLoc(), End;
481 if (getParser().ParseExpression(Val, End))
483 return X86Operand::CreateImm(Val, Start, End);
488 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
489 /// has already been parsed if present.
490 X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
492 // We have to disambiguate a parenthesized expression "(4+5)" from the start
493 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
494 // only way to do this without lookahead is to eat the '(' and see what is
496 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
497 if (getLexer().isNot(AsmToken::LParen)) {
499 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
501 // After parsing the base expression we could either have a parenthesized
502 // memory address or not. If not, return now. If so, eat the (.
503 if (getLexer().isNot(AsmToken::LParen)) {
504 // Unless we have a segment register, treat this as an immediate.
506 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
507 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
513 // Okay, we have a '('. We don't know if this is an expression or not, but
514 // so we have to eat the ( to see beyond it.
515 SMLoc LParenLoc = Parser.getTok().getLoc();
516 Parser.Lex(); // Eat the '('.
518 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
519 // Nothing to do here, fall into the code below with the '(' part of the
520 // memory operand consumed.
524 // It must be an parenthesized expression, parse it now.
525 if (getParser().ParseParenExpression(Disp, ExprEnd))
528 // After parsing the base expression we could either have a parenthesized
529 // memory address or not. If not, return now. If so, eat the (.
530 if (getLexer().isNot(AsmToken::LParen)) {
531 // Unless we have a segment register, treat this as an immediate.
533 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
534 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
542 // If we reached here, then we just ate the ( of the memory operand. Process
543 // the rest of the memory operand.
544 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
546 if (getLexer().is(AsmToken::Percent)) {
548 if (ParseRegister(BaseReg, L, L)) return 0;
549 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
550 Error(L, "eiz and riz can only be used as index registers");
555 if (getLexer().is(AsmToken::Comma)) {
556 Parser.Lex(); // Eat the comma.
558 // Following the comma we should have either an index register, or a scale
559 // value. We don't support the later form, but we want to parse it
562 // Not that even though it would be completely consistent to support syntax
563 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
564 if (getLexer().is(AsmToken::Percent)) {
566 if (ParseRegister(IndexReg, L, L)) return 0;
568 if (getLexer().isNot(AsmToken::RParen)) {
569 // Parse the scale amount:
570 // ::= ',' [scale-expression]
571 if (getLexer().isNot(AsmToken::Comma)) {
572 Error(Parser.getTok().getLoc(),
573 "expected comma in scale expression");
576 Parser.Lex(); // Eat the comma.
578 if (getLexer().isNot(AsmToken::RParen)) {
579 SMLoc Loc = Parser.getTok().getLoc();
582 if (getParser().ParseAbsoluteExpression(ScaleVal))
585 // Validate the scale amount.
586 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
587 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
590 Scale = (unsigned)ScaleVal;
593 } else if (getLexer().isNot(AsmToken::RParen)) {
594 // A scale amount without an index is ignored.
596 SMLoc Loc = Parser.getTok().getLoc();
599 if (getParser().ParseAbsoluteExpression(Value))
603 Warning(Loc, "scale factor without index register is ignored");
608 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
609 if (getLexer().isNot(AsmToken::RParen)) {
610 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
613 SMLoc MemEnd = Parser.getTok().getLoc();
614 Parser.Lex(); // Eat the ')'.
616 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
620 bool X86ATTAsmParser::
621 ParseInstruction(StringRef Name, SMLoc NameLoc,
622 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
623 // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
624 // represent alternative syntaxes in the .td file, without requiring
625 // instruction duplication.
626 StringRef PatchedName = StringSwitch<StringRef>(Name)
628 .Case("salb", "shlb")
629 .Case("sall", "shll")
630 .Case("salq", "shlq")
631 .Case("salw", "shlw")
634 .Case("repnz", "repne")
635 .Case("push", Is64Bit ? "pushq" : "pushl")
636 .Case("pop", Is64Bit ? "popq" : "popl")
637 .Case("pushf", Is64Bit ? "pushfq" : "pushfl")
638 .Case("popf", Is64Bit ? "popfq" : "popfl")
639 .Case("retl", Is64Bit ? "retl" : "ret")
640 .Case("retq", Is64Bit ? "ret" : "retq")
641 .Case("movzx", "movzb") // FIXME: Not correct.
642 .Case("fcompi", "fcomip")
645 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
646 const MCExpr *ExtraImmOp = 0;
647 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
648 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
649 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
650 bool IsVCMP = PatchedName.startswith("vcmp");
651 unsigned SSECCIdx = IsVCMP ? 4 : 3;
652 unsigned SSEComparisonCode = StringSwitch<unsigned>(
653 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
666 .Case("neq_oq", 0x0C)
673 .Case("unord_s", 0x13)
674 .Case("neq_us", 0x14)
675 .Case("nlt_uq", 0x15)
676 .Case("nle_uq", 0x16)
679 .Case("nge_uq", 0x19)
680 .Case("ngt_uq", 0x1A)
681 .Case("false_os", 0x1B)
682 .Case("neq_os", 0x1C)
685 .Case("true_us", 0x1F)
687 if (SSEComparisonCode != ~0U) {
688 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
689 getParser().getContext());
690 if (PatchedName.endswith("ss")) {
691 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
692 } else if (PatchedName.endswith("sd")) {
693 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
694 } else if (PatchedName.endswith("ps")) {
695 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
697 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
698 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
703 // FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
704 if (PatchedName.startswith("vpclmul")) {
705 unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
706 PatchedName.slice(7, PatchedName.size() - 2))
707 .Case("lqlq", 0x00) // src1[63:0], src2[63:0]
708 .Case("hqlq", 0x01) // src1[127:64], src2[63:0]
709 .Case("lqhq", 0x10) // src1[63:0], src2[127:64]
710 .Case("hqhq", 0x11) // src1[127:64], src2[127:64]
712 if (CLMULQuadWordSelect != ~0U) {
713 ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
714 getParser().getContext());
715 assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
716 PatchedName = "vpclmulqdq";
720 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
723 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
726 // Determine whether this is an instruction prefix.
728 PatchedName == "lock" || PatchedName == "rep" ||
729 PatchedName == "repne";
732 // This does the actual operand parsing. Don't parse any more if we have a
733 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
734 // just want to parse the "lock" as the first instruction and the "incl" as
736 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
738 // Parse '*' modifier.
739 if (getLexer().is(AsmToken::Star)) {
740 SMLoc Loc = Parser.getTok().getLoc();
741 Operands.push_back(X86Operand::CreateToken("*", Loc));
742 Parser.Lex(); // Eat the star.
745 // Read the first operand.
746 if (X86Operand *Op = ParseOperand())
747 Operands.push_back(Op);
749 Parser.EatToEndOfStatement();
753 while (getLexer().is(AsmToken::Comma)) {
754 Parser.Lex(); // Eat the comma.
756 // Parse and remember the operand.
757 if (X86Operand *Op = ParseOperand())
758 Operands.push_back(Op);
760 Parser.EatToEndOfStatement();
765 if (getLexer().isNot(AsmToken::EndOfStatement)) {
766 Parser.EatToEndOfStatement();
767 return TokError("unexpected token in argument list");
771 if (getLexer().is(AsmToken::EndOfStatement))
772 Parser.Lex(); // Consume the EndOfStatement
774 // Hack to allow 'movq <largeimm>, <reg>' as an alias for movabsq.
775 if ((Name == "movq" || Name == "mov") && Operands.size() == 3 &&
776 static_cast<X86Operand*>(Operands[2])->isReg() &&
777 static_cast<X86Operand*>(Operands[1])->isImm() &&
778 !static_cast<X86Operand*>(Operands[1])->isImmSExti64i32()) {
780 Operands[0] = X86Operand::CreateToken("movabsq", NameLoc);
783 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
785 if ((Name.startswith("shr") || Name.startswith("sar") ||
786 Name.startswith("shl") || Name.startswith("sal")) &&
787 Operands.size() == 3) {
788 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
789 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
790 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
792 Operands.erase(Operands.begin() + 1);
796 // FIXME: Hack to handle recognize "rc[lr] <op>" -> "rcl $1, <op>".
797 if ((Name.startswith("rcl") || Name.startswith("rcr")) &&
798 Operands.size() == 2) {
799 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
800 Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc));
801 std::swap(Operands[1], Operands[2]);
804 // FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op".
805 if ((Name.startswith("shld") || Name.startswith("shrd")) &&
806 Operands.size() == 3) {
807 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
808 Operands.insert(Operands.begin()+1,
809 X86Operand::CreateImm(One, NameLoc, NameLoc));
813 // FIXME: Hack to handle recognize "in[bwl] <op>". Canonicalize it to
815 if ((Name == "inb" || Name == "inw" || Name == "inl") &&
816 Operands.size() == 2) {
819 Reg = MatchRegisterName("al");
820 else if (Name[2] == 'w')
821 Reg = MatchRegisterName("ax");
823 Reg = MatchRegisterName("eax");
824 SMLoc Loc = Operands.back()->getEndLoc();
825 Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
828 // FIXME: Hack to handle recognize "out[bwl] <op>". Canonicalize it to
830 if ((Name == "outb" || Name == "outw" || Name == "outl") &&
831 Operands.size() == 2) {
834 Reg = MatchRegisterName("al");
835 else if (Name[3] == 'w')
836 Reg = MatchRegisterName("ax");
838 Reg = MatchRegisterName("eax");
839 SMLoc Loc = Operands.back()->getEndLoc();
840 Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
841 std::swap(Operands[1], Operands[2]);
844 // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx".
845 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
846 Operands.size() == 3) {
847 X86Operand &Op = *(X86Operand*)Operands.back();
848 if (Op.isMem() && Op.Mem.SegReg == 0 &&
849 isa<MCConstantExpr>(Op.Mem.Disp) &&
850 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
851 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
852 SMLoc Loc = Op.getEndLoc();
853 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
858 // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as
859 // "f{mul*,add*,sub*,div*} $op"
860 if ((Name.startswith("fmul") || Name.startswith("fadd") ||
861 Name.startswith("fsub") || Name.startswith("fdiv")) &&
862 Operands.size() == 3 &&
863 static_cast<X86Operand*>(Operands[2])->isReg() &&
864 static_cast<X86Operand*>(Operands[2])->getReg() == X86::ST0) {
866 Operands.erase(Operands.begin() + 2);
869 // FIXME: Hack to handle "f{mulp,addp} st(0), $op" the same as
870 // "f{mulp,addp} $op", since they commute. We also allow fdivrp/fsubrp even
871 // though they don't commute, solely because gas does support this.
872 if ((Name=="fmulp" || Name=="faddp" || Name=="fsubrp" || Name=="fdivrp") &&
873 Operands.size() == 3 &&
874 static_cast<X86Operand*>(Operands[1])->isReg() &&
875 static_cast<X86Operand*>(Operands[1])->getReg() == X86::ST0) {
877 Operands.erase(Operands.begin() + 1);
880 // FIXME: Hack to handle "imul <imm>, B" which is an alias for "imul <imm>, B,
882 if (Name.startswith("imul") && Operands.size() == 3 &&
883 static_cast<X86Operand*>(Operands[1])->isImm() &&
884 static_cast<X86Operand*>(Operands.back())->isReg()) {
885 X86Operand *Op = static_cast<X86Operand*>(Operands.back());
886 Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(),
890 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
891 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
892 // errors, since its encoding is the most compact.
893 if (Name == "sldt" && Operands.size() == 2 &&
894 static_cast<X86Operand*>(Operands[1])->isMem()) {
896 Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
899 // The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as
900 // synonyms. Our tables only have the "<reg>, <mem>" form, so if we see the
901 // other operand order, swap them.
902 if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"||
904 if (Operands.size() == 3 &&
905 static_cast<X86Operand*>(Operands[1])->isMem() &&
906 static_cast<X86Operand*>(Operands[2])->isReg()) {
907 std::swap(Operands[1], Operands[2]);
910 // The assembler accepts "testX <reg>, <mem>" and "testX <mem>, <reg>" as
911 // synonyms. Our tables only have the "<mem>, <reg>" form, so if we see the
912 // other operand order, swap them.
913 if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"||
915 if (Operands.size() == 3 &&
916 static_cast<X86Operand*>(Operands[1])->isReg() &&
917 static_cast<X86Operand*>(Operands[2])->isMem()) {
918 std::swap(Operands[1], Operands[2]);
921 // The assembler accepts these instructions with no operand as a synonym for
922 // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
923 if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||
924 Name == "faddp" || Name == "fsubp" || Name == "fsubrp" ||
925 Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") &&
926 Operands.size() == 1) {
927 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
931 // The assembler accepts this instruction with no operand as a synonym for an
932 // instruction taking %st(1),%st(0). e.g. "fcompi" -> "fcompi %st(1),st(0)".
933 if (Name == "fcompi" && Operands.size() == 1) {
934 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
936 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
940 // The assembler accepts these instructions with two few operands as a synonym
941 // for taking %st(1),%st(0) or X, %st(0).
942 if ((Name == "fcomi" || Name == "fucomi" || Name == "fucompi" ||
943 Name == "fcompi" ) &&
944 Operands.size() < 3) {
945 if (Operands.size() == 1)
946 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
948 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
952 // The assembler accepts various amounts of brokenness for fnstsw.
953 if (Name == "fnstsw" || Name == "fnstsww") {
954 if (Operands.size() == 2 &&
955 static_cast<X86Operand*>(Operands[1])->isReg()) {
956 // "fnstsw al" and "fnstsw eax" -> "fnstw"
957 unsigned Reg = static_cast<X86Operand*>(Operands[1])->Reg.RegNo;
958 if (Reg == MatchRegisterName("eax") ||
959 Reg == MatchRegisterName("al")) {
965 // "fnstw" -> "fnstw %ax"
966 if (Operands.size() == 1)
967 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("ax"),
971 // jmp $42,$5 -> ljmp, similarly for call.
972 if ((Name.startswith("call") || Name.startswith("jmp")) &&
973 Operands.size() == 3 &&
974 static_cast<X86Operand*>(Operands[1])->isImm() &&
975 static_cast<X86Operand*>(Operands[2])->isImm()) {
976 const char *NewOpName = StringSwitch<const char *>(Name)
978 .Case("jmpw", "ljmpw")
979 .Case("jmpl", "ljmpl")
980 .Case("jmpq", "ljmpq")
981 .Case("call", "lcall")
982 .Case("callw", "lcallw")
983 .Case("calll", "lcalll")
984 .Case("callq", "lcallq")
988 Operands[0] = X86Operand::CreateToken(NewOpName, NameLoc);
993 // lcall and ljmp -> lcalll and ljmpl
994 if ((Name == "lcall" || Name == "ljmp") && Operands.size() == 3) {
996 Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl",
1000 // call foo is not ambiguous with callw.
1001 if (Name == "call" && Operands.size() == 2) {
1002 const char *NewName = Is64Bit ? "callq" : "calll";
1004 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1008 // movsd -> movsl (when no operands are specified).
1009 if (Name == "movsd" && Operands.size() == 1) {
1011 Operands[0] = X86Operand::CreateToken("movsl", NameLoc);
1014 // fstp <mem> -> fstps <mem>. Without this, we'll default to fstpl due to
1015 // suffix searching.
1016 if (Name == "fstp" && Operands.size() == 2 &&
1017 static_cast<X86Operand*>(Operands[1])->isMem()) {
1019 Operands[0] = X86Operand::CreateToken("fstps", NameLoc);
1023 // "clr <reg>" -> "xor <reg>, <reg>".
1024 if ((Name == "clrb" || Name == "clrw" || Name == "clrl" || Name == "clrq" ||
1025 Name == "clr") && Operands.size() == 2 &&
1026 static_cast<X86Operand*>(Operands[1])->isReg()) {
1027 unsigned RegNo = static_cast<X86Operand*>(Operands[1])->getReg();
1028 Operands.push_back(X86Operand::CreateReg(RegNo, NameLoc, NameLoc));
1030 Operands[0] = X86Operand::CreateToken("xor", NameLoc);
1033 // FIXME: Hack to handle recognize "aa[dm]" -> "aa[dm] $0xA".
1034 if ((Name.startswith("aad") || Name.startswith("aam")) &&
1035 Operands.size() == 1) {
1036 const MCExpr *A = MCConstantExpr::Create(0xA, getParser().getContext());
1037 Operands.push_back(X86Operand::CreateImm(A, NameLoc, NameLoc));
1040 // "lgdtl" is not ambiguous 32-bit mode and is the same as "lgdt".
1041 // "lgdtq" is not ambiguous 64-bit mode and is the same as "lgdt".
1042 if ((Name == "lgdtl" && Is64Bit == false) ||
1043 (Name == "lgdtq" && Is64Bit == true)) {
1044 const char *NewName = "lgdt";
1046 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1050 // "lidtl" is not ambiguous 32-bit mode and is the same as "lidt".
1051 // "lidtq" is not ambiguous 64-bit mode and is the same as "lidt".
1052 if ((Name == "lidtl" && Is64Bit == false) ||
1053 (Name == "lidtq" && Is64Bit == true)) {
1054 const char *NewName = "lidt";
1056 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1060 // "sgdtl" is not ambiguous 32-bit mode and is the same as "sgdt".
1061 // "sgdtq" is not ambiguous 64-bit mode and is the same as "sgdt".
1062 if ((Name == "sgdtl" && Is64Bit == false) ||
1063 (Name == "sgdtq" && Is64Bit == true)) {
1064 const char *NewName = "sgdt";
1066 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1070 // "sidtl" is not ambiguous 32-bit mode and is the same as "sidt".
1071 // "sidtq" is not ambiguous 64-bit mode and is the same as "sidt".
1072 if ((Name == "sidtl" && Is64Bit == false) ||
1073 (Name == "sidtq" && Is64Bit == true)) {
1074 const char *NewName = "sidt";
1076 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1083 bool X86ATTAsmParser::
1084 MatchAndEmitInstruction(SMLoc IDLoc,
1085 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1087 assert(!Operands.empty() && "Unexpect empty operand list!");
1088 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1089 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1091 // First, handle aliases that expand to multiple instructions.
1092 // FIXME: This should be replaced with a real .td file alias mechanism.
1093 if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
1094 Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
1095 Op->getToken() == "finit" || Op->getToken() == "fsave" ||
1096 Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
1098 Inst.setOpcode(X86::WAIT);
1099 Out.EmitInstruction(Inst);
1102 StringSwitch<const char*>(Op->getToken())
1103 .Case("finit", "fninit")
1104 .Case("fsave", "fnsave")
1105 .Case("fstcw", "fnstcw")
1106 .Case("fstcww", "fnstcw")
1107 .Case("fstenv", "fnstenv")
1108 .Case("fstsw", "fnstsw")
1109 .Case("fstsww", "fnstsw")
1110 .Case("fclex", "fnclex")
1112 assert(Repl && "Unknown wait-prefixed instruction");
1114 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
1117 bool WasOriginallyInvalidOperand = false;
1118 unsigned OrigErrorInfo;
1121 // First, try a direct match.
1122 switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
1124 Out.EmitInstruction(Inst);
1126 case Match_MissingFeature:
1127 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1129 case Match_InvalidOperand:
1130 WasOriginallyInvalidOperand = true;
1132 case Match_MnemonicFail:
1136 // FIXME: Ideally, we would only attempt suffix matches for things which are
1137 // valid prefixes, and we could just infer the right unambiguous
1138 // type. However, that requires substantially more matcher support than the
1141 // Change the operand to point to a temporary token.
1142 StringRef Base = Op->getToken();
1143 SmallString<16> Tmp;
1146 Op->setTokenValue(Tmp.str());
1148 // Check for the various suffix matches.
1149 Tmp[Base.size()] = 'b';
1150 unsigned BErrorInfo, WErrorInfo, LErrorInfo, QErrorInfo;
1151 MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst, BErrorInfo);
1152 Tmp[Base.size()] = 'w';
1153 MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst, WErrorInfo);
1154 Tmp[Base.size()] = 'l';
1155 MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst, LErrorInfo);
1156 Tmp[Base.size()] = 'q';
1157 MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst, QErrorInfo);
1159 // Restore the old token.
1160 Op->setTokenValue(Base);
1162 // If exactly one matched, then we treat that as a successful match (and the
1163 // instruction will already have been filled in correctly, since the failing
1164 // matches won't have modified it).
1165 unsigned NumSuccessfulMatches =
1166 (MatchB == Match_Success) + (MatchW == Match_Success) +
1167 (MatchL == Match_Success) + (MatchQ == Match_Success);
1168 if (NumSuccessfulMatches == 1) {
1169 Out.EmitInstruction(Inst);
1173 // Otherwise, the match failed, try to produce a decent error message.
1175 // If we had multiple suffix matches, then identify this as an ambiguous
1177 if (NumSuccessfulMatches > 1) {
1179 unsigned NumMatches = 0;
1180 if (MatchB == Match_Success)
1181 MatchChars[NumMatches++] = 'b';
1182 if (MatchW == Match_Success)
1183 MatchChars[NumMatches++] = 'w';
1184 if (MatchL == Match_Success)
1185 MatchChars[NumMatches++] = 'l';
1186 if (MatchQ == Match_Success)
1187 MatchChars[NumMatches++] = 'q';
1189 SmallString<126> Msg;
1190 raw_svector_ostream OS(Msg);
1191 OS << "ambiguous instructions require an explicit suffix (could be ";
1192 for (unsigned i = 0; i != NumMatches; ++i) {
1195 if (i + 1 == NumMatches)
1197 OS << "'" << Base << MatchChars[i] << "'";
1200 Error(IDLoc, OS.str());
1204 // Okay, we know that none of the variants matched successfully.
1206 // If all of the instructions reported an invalid mnemonic, then the original
1207 // mnemonic was invalid.
1208 if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) &&
1209 (MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) {
1210 if (!WasOriginallyInvalidOperand) {
1211 Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
1215 // Recover location info for the operand if we know which was the problem.
1216 SMLoc ErrorLoc = IDLoc;
1217 if (OrigErrorInfo != ~0U) {
1218 if (OrigErrorInfo >= Operands.size())
1219 return Error(IDLoc, "too few operands for instruction");
1221 ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc();
1222 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1225 return Error(ErrorLoc, "invalid operand for instruction");
1228 // If one instruction matched with a missing feature, report this as a
1230 if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) +
1231 (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1){
1232 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1236 // If one instruction matched with an invalid operand, report this as an
1238 if ((MatchB == Match_InvalidOperand) + (MatchW == Match_InvalidOperand) +
1239 (MatchL == Match_InvalidOperand) + (MatchQ == Match_InvalidOperand) == 1){
1240 Error(IDLoc, "invalid operand for instruction");
1244 // If all of these were an outright failure, report it in a useless way.
1245 // FIXME: We should give nicer diagnostics about the exact failure.
1246 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
1251 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
1252 StringRef IDVal = DirectiveID.getIdentifier();
1253 if (IDVal == ".word")
1254 return ParseDirectiveWord(2, DirectiveID.getLoc());
1258 /// ParseDirectiveWord
1259 /// ::= .word [ expression (, expression)* ]
1260 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1261 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1263 const MCExpr *Value;
1264 if (getParser().ParseExpression(Value))
1267 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1269 if (getLexer().is(AsmToken::EndOfStatement))
1272 // FIXME: Improve diagnostic.
1273 if (getLexer().isNot(AsmToken::Comma))
1274 return Error(L, "unexpected token in directive");
1286 extern "C" void LLVMInitializeX86AsmLexer();
1288 // Force static initialization.
1289 extern "C" void LLVMInitializeX86AsmParser() {
1290 RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
1291 RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
1292 LLVMInitializeX86AsmLexer();
1295 #define GET_REGISTER_MATCHER
1296 #define GET_MATCHER_IMPLEMENTATION
1297 #include "X86GenAsmMatcher.inc"