1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "X86Subtarget.h"
13 #include "llvm/Target/TargetRegistry.h"
14 #include "llvm/Target/TargetAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
33 class X86ATTAsmParser : public TargetAsmParser {
41 MCAsmParser &getParser() const { return Parser; }
43 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
49 X86Operand *ParseOperand();
50 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
52 bool ParseDirectiveWord(unsigned Size, SMLoc L);
54 bool MatchInstruction(SMLoc IDLoc,
55 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
58 /// @name Auto-generated Matcher Functions
61 #define GET_ASSEMBLER_HEADER
62 #include "X86GenAsmMatcher.inc"
67 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
68 : TargetAsmParser(T), Parser(_Parser), TM(TM) {
70 // Initialize the set of available features.
71 setAvailableFeatures(ComputeAvailableFeatures(
72 &TM.getSubtarget<X86Subtarget>()));
75 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
76 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
78 virtual bool ParseDirective(AsmToken DirectiveID);
81 class X86_32ATTAsmParser : public X86ATTAsmParser {
83 X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
84 : X86ATTAsmParser(T, _Parser, TM) {
89 class X86_64ATTAsmParser : public X86ATTAsmParser {
91 X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
92 : X86ATTAsmParser(T, _Parser, TM) {
97 } // end anonymous namespace
99 /// @name Auto-generated Match Functions
102 static unsigned MatchRegisterName(StringRef Name);
108 /// X86Operand - Instances of this class represent a parsed X86 machine
110 struct X86Operand : public MCParsedAsmOperand {
118 SMLoc StartLoc, EndLoc;
143 X86Operand(KindTy K, SMLoc Start, SMLoc End)
144 : Kind(K), StartLoc(Start), EndLoc(End) {}
146 /// getStartLoc - Get the location of the first token of this operand.
147 SMLoc getStartLoc() const { return StartLoc; }
148 /// getEndLoc - Get the location of the last token of this operand.
149 SMLoc getEndLoc() const { return EndLoc; }
151 virtual void dump(raw_ostream &OS) const {}
153 StringRef getToken() const {
154 assert(Kind == Token && "Invalid access!");
155 return StringRef(Tok.Data, Tok.Length);
157 void setTokenValue(StringRef Value) {
158 assert(Kind == Token && "Invalid access!");
159 Tok.Data = Value.data();
160 Tok.Length = Value.size();
163 unsigned getReg() const {
164 assert(Kind == Register && "Invalid access!");
168 const MCExpr *getImm() const {
169 assert(Kind == Immediate && "Invalid access!");
173 const MCExpr *getMemDisp() const {
174 assert(Kind == Memory && "Invalid access!");
177 unsigned getMemSegReg() const {
178 assert(Kind == Memory && "Invalid access!");
181 unsigned getMemBaseReg() const {
182 assert(Kind == Memory && "Invalid access!");
185 unsigned getMemIndexReg() const {
186 assert(Kind == Memory && "Invalid access!");
189 unsigned getMemScale() const {
190 assert(Kind == Memory && "Invalid access!");
194 bool isToken() const {return Kind == Token; }
196 bool isImm() const { return Kind == Immediate; }
198 bool isImmSExti16i8() const {
202 // If this isn't a constant expr, just assume it fits and let relaxation
204 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
208 // Otherwise, check the value is in a range that makes sense for this
210 uint64_t Value = CE->getValue();
211 return (( Value <= 0x000000000000007FULL)||
212 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
213 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
215 bool isImmSExti32i8() const {
219 // If this isn't a constant expr, just assume it fits and let relaxation
221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
225 // Otherwise, check the value is in a range that makes sense for this
227 uint64_t Value = CE->getValue();
228 return (( Value <= 0x000000000000007FULL)||
229 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
230 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
232 bool isImmSExti64i8() const {
236 // If this isn't a constant expr, just assume it fits and let relaxation
238 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
242 // Otherwise, check the value is in a range that makes sense for this
244 uint64_t Value = CE->getValue();
245 return (( Value <= 0x000000000000007FULL)||
246 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
248 bool isImmSExti64i32() const {
252 // If this isn't a constant expr, just assume it fits and let relaxation
254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
258 // Otherwise, check the value is in a range that makes sense for this
260 uint64_t Value = CE->getValue();
261 return (( Value <= 0x000000007FFFFFFFULL)||
262 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
265 bool isMem() const { return Kind == Memory; }
267 bool isAbsMem() const {
268 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
269 !getMemIndexReg() && getMemScale() == 1;
272 bool isReg() const { return Kind == Register; }
274 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
275 // Add as immediates when possible.
276 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
277 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
279 Inst.addOperand(MCOperand::CreateExpr(Expr));
282 void addRegOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(getReg()));
287 void addImmOperands(MCInst &Inst, unsigned N) const {
288 assert(N == 1 && "Invalid number of operands!");
289 addExpr(Inst, getImm());
292 void addMemOperands(MCInst &Inst, unsigned N) const {
293 assert((N == 5) && "Invalid number of operands!");
294 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
295 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
296 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
297 addExpr(Inst, getMemDisp());
298 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
301 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
302 assert((N == 1) && "Invalid number of operands!");
303 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
306 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
307 X86Operand *Res = new X86Operand(Token, Loc, Loc);
308 Res->Tok.Data = Str.data();
309 Res->Tok.Length = Str.size();
313 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
314 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
315 Res->Reg.RegNo = RegNo;
319 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
320 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
325 /// Create an absolute memory operand.
326 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
328 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
330 Res->Mem.Disp = Disp;
331 Res->Mem.BaseReg = 0;
332 Res->Mem.IndexReg = 0;
337 /// Create a generalized memory operand.
338 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
339 unsigned BaseReg, unsigned IndexReg,
340 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
341 // We should never just have a displacement, that should be parsed as an
342 // absolute memory operand.
343 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
345 // The scale should always be one of {1,2,4,8}.
346 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
348 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
349 Res->Mem.SegReg = SegReg;
350 Res->Mem.Disp = Disp;
351 Res->Mem.BaseReg = BaseReg;
352 Res->Mem.IndexReg = IndexReg;
353 Res->Mem.Scale = Scale;
358 } // end anonymous namespace.
361 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
362 SMLoc &StartLoc, SMLoc &EndLoc) {
364 const AsmToken &TokPercent = Parser.getTok();
365 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
366 StartLoc = TokPercent.getLoc();
367 Parser.Lex(); // Eat percent token.
369 const AsmToken &Tok = Parser.getTok();
370 if (Tok.isNot(AsmToken::Identifier))
371 return Error(Tok.getLoc(), "invalid register name");
373 // FIXME: Validate register for the current architecture; we have to do
374 // validation later, so maybe there is no need for this here.
375 RegNo = MatchRegisterName(Tok.getString());
377 // If the match failed, try the register name as lowercase.
379 RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
381 // FIXME: This should be done using Requires<In32BitMode> and
382 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
383 // can be also checked.
384 if (RegNo == X86::RIZ && !Is64Bit)
385 return Error(Tok.getLoc(), "riz register in 64-bit mode only");
387 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
388 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
390 EndLoc = Tok.getLoc();
391 Parser.Lex(); // Eat 'st'
393 // Check to see if we have '(4)' after %st.
394 if (getLexer().isNot(AsmToken::LParen))
399 const AsmToken &IntTok = Parser.getTok();
400 if (IntTok.isNot(AsmToken::Integer))
401 return Error(IntTok.getLoc(), "expected stack index");
402 switch (IntTok.getIntVal()) {
403 case 0: RegNo = X86::ST0; break;
404 case 1: RegNo = X86::ST1; break;
405 case 2: RegNo = X86::ST2; break;
406 case 3: RegNo = X86::ST3; break;
407 case 4: RegNo = X86::ST4; break;
408 case 5: RegNo = X86::ST5; break;
409 case 6: RegNo = X86::ST6; break;
410 case 7: RegNo = X86::ST7; break;
411 default: return Error(IntTok.getLoc(), "invalid stack index");
414 if (getParser().Lex().isNot(AsmToken::RParen))
415 return Error(Parser.getTok().getLoc(), "expected ')'");
417 EndLoc = Tok.getLoc();
418 Parser.Lex(); // Eat ')'
422 // If this is "db[0-7]", match it as an alias
424 if (RegNo == 0 && Tok.getString().size() == 3 &&
425 Tok.getString().startswith("db")) {
426 switch (Tok.getString()[2]) {
427 case '0': RegNo = X86::DR0; break;
428 case '1': RegNo = X86::DR1; break;
429 case '2': RegNo = X86::DR2; break;
430 case '3': RegNo = X86::DR3; break;
431 case '4': RegNo = X86::DR4; break;
432 case '5': RegNo = X86::DR5; break;
433 case '6': RegNo = X86::DR6; break;
434 case '7': RegNo = X86::DR7; break;
438 EndLoc = Tok.getLoc();
439 Parser.Lex(); // Eat it.
445 return Error(Tok.getLoc(), "invalid register name");
447 EndLoc = Tok.getLoc();
448 Parser.Lex(); // Eat identifier token.
452 X86Operand *X86ATTAsmParser::ParseOperand() {
453 switch (getLexer().getKind()) {
455 // Parse a memory operand with no segment register.
456 return ParseMemOperand(0, Parser.getTok().getLoc());
457 case AsmToken::Percent: {
458 // Read the register.
461 if (ParseRegister(RegNo, Start, End)) return 0;
462 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
463 Error(Start, "eiz and riz can only be used as index registers");
467 // If this is a segment register followed by a ':', then this is the start
468 // of a memory reference, otherwise this is a normal register reference.
469 if (getLexer().isNot(AsmToken::Colon))
470 return X86Operand::CreateReg(RegNo, Start, End);
473 getParser().Lex(); // Eat the colon.
474 return ParseMemOperand(RegNo, Start);
476 case AsmToken::Dollar: {
478 SMLoc Start = Parser.getTok().getLoc(), End;
481 if (getParser().ParseExpression(Val, End))
483 return X86Operand::CreateImm(Val, Start, End);
488 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
489 /// has already been parsed if present.
490 X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
492 // We have to disambiguate a parenthesized expression "(4+5)" from the start
493 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
494 // only way to do this without lookahead is to eat the '(' and see what is
496 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
497 if (getLexer().isNot(AsmToken::LParen)) {
499 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
501 // After parsing the base expression we could either have a parenthesized
502 // memory address or not. If not, return now. If so, eat the (.
503 if (getLexer().isNot(AsmToken::LParen)) {
504 // Unless we have a segment register, treat this as an immediate.
506 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
507 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
513 // Okay, we have a '('. We don't know if this is an expression or not, but
514 // so we have to eat the ( to see beyond it.
515 SMLoc LParenLoc = Parser.getTok().getLoc();
516 Parser.Lex(); // Eat the '('.
518 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
519 // Nothing to do here, fall into the code below with the '(' part of the
520 // memory operand consumed.
524 // It must be an parenthesized expression, parse it now.
525 if (getParser().ParseParenExpression(Disp, ExprEnd))
528 // After parsing the base expression we could either have a parenthesized
529 // memory address or not. If not, return now. If so, eat the (.
530 if (getLexer().isNot(AsmToken::LParen)) {
531 // Unless we have a segment register, treat this as an immediate.
533 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
534 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
542 // If we reached here, then we just ate the ( of the memory operand. Process
543 // the rest of the memory operand.
544 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
546 if (getLexer().is(AsmToken::Percent)) {
548 if (ParseRegister(BaseReg, L, L)) return 0;
549 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
550 Error(L, "eiz and riz can only be used as index registers");
555 if (getLexer().is(AsmToken::Comma)) {
556 Parser.Lex(); // Eat the comma.
558 // Following the comma we should have either an index register, or a scale
559 // value. We don't support the later form, but we want to parse it
562 // Not that even though it would be completely consistent to support syntax
563 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
564 if (getLexer().is(AsmToken::Percent)) {
566 if (ParseRegister(IndexReg, L, L)) return 0;
568 if (getLexer().isNot(AsmToken::RParen)) {
569 // Parse the scale amount:
570 // ::= ',' [scale-expression]
571 if (getLexer().isNot(AsmToken::Comma)) {
572 Error(Parser.getTok().getLoc(),
573 "expected comma in scale expression");
576 Parser.Lex(); // Eat the comma.
578 if (getLexer().isNot(AsmToken::RParen)) {
579 SMLoc Loc = Parser.getTok().getLoc();
582 if (getParser().ParseAbsoluteExpression(ScaleVal))
585 // Validate the scale amount.
586 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
587 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
590 Scale = (unsigned)ScaleVal;
593 } else if (getLexer().isNot(AsmToken::RParen)) {
594 // A scale amount without an index is ignored.
596 SMLoc Loc = Parser.getTok().getLoc();
599 if (getParser().ParseAbsoluteExpression(Value))
603 Warning(Loc, "scale factor without index register is ignored");
608 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
609 if (getLexer().isNot(AsmToken::RParen)) {
610 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
613 SMLoc MemEnd = Parser.getTok().getLoc();
614 Parser.Lex(); // Eat the ')'.
616 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
620 bool X86ATTAsmParser::
621 ParseInstruction(StringRef Name, SMLoc NameLoc,
622 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
623 // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
624 // represent alternative syntaxes in the .td file, without requiring
625 // instruction duplication.
626 StringRef PatchedName = StringSwitch<StringRef>(Name)
628 .Case("salb", "shlb")
629 .Case("sall", "shll")
630 .Case("salq", "shlq")
631 .Case("salw", "shlw")
634 .Case("repnz", "repne")
635 .Case("iret", "iretl")
636 .Case("sysret", "sysretl")
637 .Case("smovb", "movsb")
638 .Case("smovw", "movsw")
639 .Case("smovl", "movsl")
640 .Case("smovq", "movsq")
641 .Case("push", Is64Bit ? "pushq" : "pushl")
642 .Case("pop", Is64Bit ? "popq" : "popl")
643 .Case("pushf", Is64Bit ? "pushfq" : "pushfl")
644 .Case("popf", Is64Bit ? "popfq" : "popfl")
645 .Case("pushfd", "pushfl")
646 .Case("popfd", "popfl")
647 .Case("retl", Is64Bit ? "retl" : "ret")
648 .Case("retq", Is64Bit ? "ret" : "retq")
649 .Case("setz", "sete") .Case("setnz", "setne")
650 .Case("setc", "setb") .Case("setna", "setbe")
651 .Case("setnae", "setb").Case("setnb", "setae")
652 .Case("setnbe", "seta").Case("setnc", "setae")
653 .Case("setng", "setle").Case("setnge", "setl")
654 .Case("setnl", "setge").Case("setnle", "setg")
655 .Case("setpe", "setp") .Case("setpo", "setnp")
656 .Case("jz", "je") .Case("jnz", "jne")
657 .Case("jc", "jb") .Case("jna", "jbe")
658 .Case("jnae", "jb").Case("jnb", "jae")
659 .Case("jnbe", "ja").Case("jnc", "jae")
660 .Case("jng", "jle").Case("jnge", "jl")
661 .Case("jnl", "jge").Case("jnle", "jg")
662 .Case("jpe", "jp") .Case("jpo", "jnp")
663 // Condition code aliases for 16-bit, 32-bit, 64-bit and unspec operands.
664 .Case("cmovcw", "cmovbw") .Case("cmovcl", "cmovbl")
665 .Case("cmovcq", "cmovbq") .Case("cmovc", "cmovb")
666 .Case("cmovnaew","cmovbw") .Case("cmovnael","cmovbl")
667 .Case("cmovnaeq","cmovbq") .Case("cmovnae", "cmovb")
668 .Case("cmovnaw", "cmovbew").Case("cmovnal", "cmovbel")
669 .Case("cmovnaq", "cmovbeq").Case("cmovna", "cmovbe")
670 .Case("cmovnbw", "cmovaew").Case("cmovnbl", "cmovael")
671 .Case("cmovnbq", "cmovaeq").Case("cmovnb", "cmovae")
672 .Case("cmovnbew","cmovaw") .Case("cmovnbel","cmoval")
673 .Case("cmovnbeq","cmovaq") .Case("cmovnbe", "cmova")
674 .Case("cmovncw", "cmovaew").Case("cmovncl", "cmovael")
675 .Case("cmovncq", "cmovaeq").Case("cmovnc", "cmovae")
676 .Case("cmovngw", "cmovlew").Case("cmovngl", "cmovlel")
677 .Case("cmovngq", "cmovleq").Case("cmovng", "cmovle")
678 .Case("cmovnw", "cmovgew").Case("cmovnl", "cmovgel")
679 .Case("cmovnq", "cmovgeq").Case("cmovn", "cmovge")
680 .Case("cmovngw", "cmovlew").Case("cmovngl", "cmovlel")
681 .Case("cmovngq", "cmovleq").Case("cmovng", "cmovle")
682 .Case("cmovngew","cmovlw") .Case("cmovngel","cmovll")
683 .Case("cmovngeq","cmovlq") .Case("cmovnge", "cmovl")
684 .Case("cmovnlw", "cmovgew").Case("cmovnll", "cmovgel")
685 .Case("cmovnlq", "cmovgeq").Case("cmovnl", "cmovge")
686 .Case("cmovnlew","cmovgw") .Case("cmovnlel","cmovgl")
687 .Case("cmovnleq","cmovgq") .Case("cmovnle", "cmovg")
688 .Case("cmovnzw", "cmovnew").Case("cmovnzl", "cmovnel")
689 .Case("cmovnzq", "cmovneq").Case("cmovnz", "cmovne")
690 .Case("cmovzw", "cmovew") .Case("cmovzl", "cmovel")
691 .Case("cmovzq", "cmoveq") .Case("cmovz", "cmove")
692 // Floating point stack cmov aliases.
693 .Case("fcmovz", "fcmove")
694 .Case("fcmova", "fcmovnbe")
695 .Case("fcmovnae", "fcmovb")
696 .Case("fcmovna", "fcmovbe")
697 .Case("fcmovae", "fcmovnb")
698 .Case("fwait", "wait")
699 .Case("movzx", "movzb") // FIXME: Not correct.
700 .Case("fildq", "fildll")
703 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
704 const MCExpr *ExtraImmOp = 0;
705 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
706 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
707 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
708 bool IsVCMP = PatchedName.startswith("vcmp");
709 unsigned SSECCIdx = IsVCMP ? 4 : 3;
710 unsigned SSEComparisonCode = StringSwitch<unsigned>(
711 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
724 .Case("neq_oq", 0x0C)
731 .Case("unord_s", 0x13)
732 .Case("neq_us", 0x14)
733 .Case("nlt_uq", 0x15)
734 .Case("nle_uq", 0x16)
737 .Case("nge_uq", 0x19)
738 .Case("ngt_uq", 0x1A)
739 .Case("false_os", 0x1B)
740 .Case("neq_os", 0x1C)
743 .Case("true_us", 0x1F)
745 if (SSEComparisonCode != ~0U) {
746 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
747 getParser().getContext());
748 if (PatchedName.endswith("ss")) {
749 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
750 } else if (PatchedName.endswith("sd")) {
751 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
752 } else if (PatchedName.endswith("ps")) {
753 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
755 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
756 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
761 // FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
762 if (PatchedName.startswith("vpclmul")) {
763 unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
764 PatchedName.slice(7, PatchedName.size() - 2))
765 .Case("lqlq", 0x00) // src1[63:0], src2[63:0]
766 .Case("hqlq", 0x01) // src1[127:64], src2[63:0]
767 .Case("lqhq", 0x10) // src1[63:0], src2[127:64]
768 .Case("hqhq", 0x11) // src1[127:64], src2[127:64]
770 if (CLMULQuadWordSelect != ~0U) {
771 ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
772 getParser().getContext());
773 assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
774 PatchedName = "vpclmulqdq";
778 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
781 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
784 // Determine whether this is an instruction prefix.
786 PatchedName == "lock" || PatchedName == "rep" ||
787 PatchedName == "repne";
790 // This does the actual operand parsing. Don't parse any more if we have a
791 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
792 // just want to parse the "lock" as the first instruction and the "incl" as
794 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
796 // Parse '*' modifier.
797 if (getLexer().is(AsmToken::Star)) {
798 SMLoc Loc = Parser.getTok().getLoc();
799 Operands.push_back(X86Operand::CreateToken("*", Loc));
800 Parser.Lex(); // Eat the star.
803 // Read the first operand.
804 if (X86Operand *Op = ParseOperand())
805 Operands.push_back(Op);
807 Parser.EatToEndOfStatement();
811 while (getLexer().is(AsmToken::Comma)) {
812 Parser.Lex(); // Eat the comma.
814 // Parse and remember the operand.
815 if (X86Operand *Op = ParseOperand())
816 Operands.push_back(Op);
818 Parser.EatToEndOfStatement();
823 if (getLexer().isNot(AsmToken::EndOfStatement)) {
824 Parser.EatToEndOfStatement();
825 return TokError("unexpected token in argument list");
829 if (getLexer().is(AsmToken::EndOfStatement))
830 Parser.Lex(); // Consume the EndOfStatement
832 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
834 if ((Name.startswith("shr") || Name.startswith("sar") ||
835 Name.startswith("shl")) &&
836 Operands.size() == 3) {
837 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
838 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
839 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
841 Operands.erase(Operands.begin() + 1);
845 // FIXME: Hack to handle recognize "rc[lr] <op>" -> "rcl $1, <op>".
846 if ((Name.startswith("rcl") || Name.startswith("rcr")) &&
847 Operands.size() == 2) {
848 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
849 Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc));
850 std::swap(Operands[1], Operands[2]);
853 // FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op".
854 if ((Name.startswith("shld") || Name.startswith("shrd")) &&
855 Operands.size() == 3) {
856 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
857 Operands.insert(Operands.begin()+1,
858 X86Operand::CreateImm(One, NameLoc, NameLoc));
862 // FIXME: Hack to handle recognize "in[bwl] <op>". Canonicalize it to
864 if ((Name == "inb" || Name == "inw" || Name == "inl") &&
865 Operands.size() == 2) {
868 Reg = MatchRegisterName("al");
869 else if (Name[2] == 'w')
870 Reg = MatchRegisterName("ax");
872 Reg = MatchRegisterName("eax");
873 SMLoc Loc = Operands.back()->getEndLoc();
874 Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
877 // FIXME: Hack to handle recognize "out[bwl] <op>". Canonicalize it to
879 if ((Name == "outb" || Name == "outw" || Name == "outl") &&
880 Operands.size() == 2) {
883 Reg = MatchRegisterName("al");
884 else if (Name[3] == 'w')
885 Reg = MatchRegisterName("ax");
887 Reg = MatchRegisterName("eax");
888 SMLoc Loc = Operands.back()->getEndLoc();
889 Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
890 std::swap(Operands[1], Operands[2]);
893 // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx".
894 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
895 Operands.size() == 3) {
896 X86Operand &Op = *(X86Operand*)Operands.back();
897 if (Op.isMem() && Op.Mem.SegReg == 0 &&
898 isa<MCConstantExpr>(Op.Mem.Disp) &&
899 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
900 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
901 SMLoc Loc = Op.getEndLoc();
902 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
907 // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as
908 // "f{mul*,add*,sub*,div*} $op"
909 if ((Name.startswith("fmul") || Name.startswith("fadd") ||
910 Name.startswith("fsub") || Name.startswith("fdiv")) &&
911 Operands.size() == 3 &&
912 static_cast<X86Operand*>(Operands[2])->isReg() &&
913 static_cast<X86Operand*>(Operands[2])->getReg() == X86::ST0) {
915 Operands.erase(Operands.begin() + 2);
918 // FIXME: Hack to handle "f{mulp,addp} st(0), $op" the same as
919 // "f{mulp,addp} $op", since they commute.
920 if ((Name == "fmulp" || Name == "faddp") && Operands.size() == 3 &&
921 static_cast<X86Operand*>(Operands[1])->isReg() &&
922 static_cast<X86Operand*>(Operands[1])->getReg() == X86::ST0) {
924 Operands.erase(Operands.begin() + 1);
927 // FIXME: Hack to handle "imul <imm>, B" which is an alias for "imul <imm>, B,
929 if (Name.startswith("imul") && Operands.size() == 3 &&
930 static_cast<X86Operand*>(Operands[1])->isImm() &&
931 static_cast<X86Operand*>(Operands.back())->isReg()) {
932 X86Operand *Op = static_cast<X86Operand*>(Operands.back());
933 Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(),
937 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
938 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
939 // errors, since its encoding is the most compact.
940 if (Name == "sldt" && Operands.size() == 2 &&
941 static_cast<X86Operand*>(Operands[1])->isMem()) {
943 Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
946 // The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as
947 // synonyms. Our tables only have the "<reg>, <mem>" form, so if we see the
948 // other operand order, swap them.
949 if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"||
951 if (Operands.size() == 3 &&
952 static_cast<X86Operand*>(Operands[1])->isMem() &&
953 static_cast<X86Operand*>(Operands[2])->isReg()) {
954 std::swap(Operands[1], Operands[2]);
957 // The assembler accepts "testX <reg>, <mem>" and "testX <mem>, <reg>" as
958 // synonyms. Our tables only have the "<mem>, <reg>" form, so if we see the
959 // other operand order, swap them.
960 if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"||
962 if (Operands.size() == 3 &&
963 static_cast<X86Operand*>(Operands[1])->isReg() &&
964 static_cast<X86Operand*>(Operands[2])->isMem()) {
965 std::swap(Operands[1], Operands[2]);
968 // The assembler accepts these instructions with no operand as a synonym for
969 // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
970 if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||
971 Name == "faddp" || Name == "fsubp" || Name == "fsubrp" ||
972 Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") &&
973 Operands.size() == 1) {
974 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
978 // The assembler accepts these instructions with two few operands as a synonym
979 // for taking %st(1),%st(0) or X, %st(0).
980 if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) {
981 if (Operands.size() == 1)
982 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
984 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
988 // The assembler accepts various amounts of brokenness for fnstsw.
989 if (Name == "fnstsw") {
990 if (Operands.size() == 2 &&
991 static_cast<X86Operand*>(Operands[1])->isReg()) {
992 // "fnstsw al" and "fnstsw eax" -> "fnstw"
993 unsigned Reg = static_cast<X86Operand*>(Operands[1])->Reg.RegNo;
994 if (Reg == MatchRegisterName("eax") ||
995 Reg == MatchRegisterName("al")) {
1001 // "fnstw" -> "fnstw %ax"
1002 if (Operands.size() == 1)
1003 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("ax"),
1007 // jmp $42,$5 -> ljmp, similarly for call.
1008 if ((Name.startswith("call") || Name.startswith("jmp")) &&
1009 Operands.size() == 3 &&
1010 static_cast<X86Operand*>(Operands[1])->isImm() &&
1011 static_cast<X86Operand*>(Operands[2])->isImm()) {
1012 const char *NewOpName = StringSwitch<const char *>(Name)
1013 .Case("jmp", "ljmp")
1014 .Case("jmpw", "ljmpw")
1015 .Case("jmpl", "ljmpl")
1016 .Case("jmpq", "ljmpq")
1017 .Case("call", "lcall")
1018 .Case("callw", "lcallw")
1019 .Case("calll", "lcalll")
1020 .Case("callq", "lcallq")
1024 Operands[0] = X86Operand::CreateToken(NewOpName, NameLoc);
1029 // lcall and ljmp -> lcalll and ljmpl
1030 if ((Name == "lcall" || Name == "ljmp") && Operands.size() == 3) {
1032 Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl",
1036 // call foo is not ambiguous with callw.
1037 if (Name == "call" && Operands.size() == 2) {
1038 const char *NewName = Is64Bit ? "callq" : "calll";
1040 Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
1044 // movsd -> movsl (when no operands are specified).
1045 if (Name == "movsd" && Operands.size() == 1) {
1047 Operands[0] = X86Operand::CreateToken("movsl", NameLoc);
1050 // fstp <mem> -> fstps <mem>. Without this, we'll default to fstpl due to
1051 // suffix searching.
1052 if (Name == "fstp" && Operands.size() == 2 &&
1053 static_cast<X86Operand*>(Operands[1])->isMem()) {
1055 Operands[0] = X86Operand::CreateToken("fstps", NameLoc);
1059 // "clr <reg>" -> "xor <reg>, <reg>".
1060 if ((Name == "clrb" || Name == "clrw" || Name == "clrl" || Name == "clrq" ||
1061 Name == "clr") && Operands.size() == 2 &&
1062 static_cast<X86Operand*>(Operands[1])->isReg()) {
1063 unsigned RegNo = static_cast<X86Operand*>(Operands[1])->getReg();
1064 Operands.push_back(X86Operand::CreateReg(RegNo, NameLoc, NameLoc));
1066 Operands[0] = X86Operand::CreateToken("xor", NameLoc);
1072 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
1073 StringRef IDVal = DirectiveID.getIdentifier();
1074 if (IDVal == ".word")
1075 return ParseDirectiveWord(2, DirectiveID.getLoc());
1079 /// ParseDirectiveWord
1080 /// ::= .word [ expression (, expression)* ]
1081 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1082 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1084 const MCExpr *Value;
1085 if (getParser().ParseExpression(Value))
1088 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1090 if (getLexer().is(AsmToken::EndOfStatement))
1093 // FIXME: Improve diagnostic.
1094 if (getLexer().isNot(AsmToken::Comma))
1095 return Error(L, "unexpected token in directive");
1105 bool X86ATTAsmParser::
1106 MatchInstruction(SMLoc IDLoc,
1107 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1109 assert(!Operands.empty() && "Unexpect empty operand list!");
1111 bool WasOriginallyInvalidOperand = false;
1112 unsigned OrigErrorInfo;
1114 // First, try a direct match.
1115 switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
1118 case Match_MissingFeature:
1119 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1121 case Match_InvalidOperand:
1122 WasOriginallyInvalidOperand = true;
1124 case Match_MnemonicFail:
1128 // FIXME: Ideally, we would only attempt suffix matches for things which are
1129 // valid prefixes, and we could just infer the right unambiguous
1130 // type. However, that requires substantially more matcher support than the
1133 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1134 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1136 // Change the operand to point to a temporary token.
1137 StringRef Base = Op->getToken();
1138 SmallString<16> Tmp;
1141 Op->setTokenValue(Tmp.str());
1143 // Check for the various suffix matches.
1144 Tmp[Base.size()] = 'b';
1145 unsigned BErrorInfo, WErrorInfo, LErrorInfo, QErrorInfo;
1146 MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst, BErrorInfo);
1147 Tmp[Base.size()] = 'w';
1148 MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst, WErrorInfo);
1149 Tmp[Base.size()] = 'l';
1150 MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst, LErrorInfo);
1151 Tmp[Base.size()] = 'q';
1152 MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst, QErrorInfo);
1154 // Restore the old token.
1155 Op->setTokenValue(Base);
1157 // If exactly one matched, then we treat that as a successful match (and the
1158 // instruction will already have been filled in correctly, since the failing
1159 // matches won't have modified it).
1160 unsigned NumSuccessfulMatches =
1161 (MatchB == Match_Success) + (MatchW == Match_Success) +
1162 (MatchL == Match_Success) + (MatchQ == Match_Success);
1163 if (NumSuccessfulMatches == 1)
1166 // Otherwise, the match failed, try to produce a decent error message.
1168 // If we had multiple suffix matches, then identify this as an ambiguous
1170 if (NumSuccessfulMatches > 1) {
1172 unsigned NumMatches = 0;
1173 if (MatchB == Match_Success)
1174 MatchChars[NumMatches++] = 'b';
1175 if (MatchW == Match_Success)
1176 MatchChars[NumMatches++] = 'w';
1177 if (MatchL == Match_Success)
1178 MatchChars[NumMatches++] = 'l';
1179 if (MatchQ == Match_Success)
1180 MatchChars[NumMatches++] = 'q';
1182 SmallString<126> Msg;
1183 raw_svector_ostream OS(Msg);
1184 OS << "ambiguous instructions require an explicit suffix (could be ";
1185 for (unsigned i = 0; i != NumMatches; ++i) {
1188 if (i + 1 == NumMatches)
1190 OS << "'" << Base << MatchChars[i] << "'";
1193 Error(IDLoc, OS.str());
1197 // Okay, we know that none of the variants matched successfully.
1199 // If all of the instructions reported an invalid mnemonic, then the original
1200 // mnemonic was invalid.
1201 if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) &&
1202 (MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) {
1203 if (!WasOriginallyInvalidOperand) {
1204 Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
1208 // Recover location info for the operand if we know which was the problem.
1209 SMLoc ErrorLoc = IDLoc;
1210 if (OrigErrorInfo != ~0U) {
1211 if (OrigErrorInfo >= Operands.size())
1212 return Error(IDLoc, "too few operands for instruction");
1214 ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc();
1215 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1218 return Error(ErrorLoc, "invalid operand for instruction");
1221 // If one instruction matched with a missing feature, report this as a
1223 if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) +
1224 (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1){
1225 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1229 // If one instruction matched with an invalid operand, report this as an
1231 if ((MatchB == Match_InvalidOperand) + (MatchW == Match_InvalidOperand) +
1232 (MatchL == Match_InvalidOperand) + (MatchQ == Match_InvalidOperand) == 1){
1233 Error(IDLoc, "invalid operand for instruction");
1237 // If all of these were an outright failure, report it in a useless way.
1238 // FIXME: We should give nicer diagnostics about the exact failure.
1239 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
1244 extern "C" void LLVMInitializeX86AsmLexer();
1246 // Force static initialization.
1247 extern "C" void LLVMInitializeX86AsmParser() {
1248 RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
1249 RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
1250 LLVMInitializeX86AsmLexer();
1253 #define GET_REGISTER_MATCHER
1254 #define GET_MATCHER_IMPLEMENTATION
1255 #include "X86GenAsmMatcher.inc"