1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmParser.h"
12 #include "X86Subtarget.h"
13 #include "llvm/Target/TargetRegistry.h"
14 #include "llvm/Target/TargetAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
33 class X86ATTAsmParser : public TargetAsmParser {
41 MCAsmParser &getParser() const { return Parser; }
43 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
49 X86Operand *ParseOperand();
50 X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
52 bool ParseDirectiveWord(unsigned Size, SMLoc L);
54 bool MatchInstruction(SMLoc IDLoc,
55 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
58 /// @name Auto-generated Matcher Functions
61 #define GET_ASSEMBLER_HEADER
62 #include "X86GenAsmMatcher.inc"
67 X86ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
68 : TargetAsmParser(T), Parser(_Parser), TM(TM) {
70 // Initialize the set of available features.
71 setAvailableFeatures(ComputeAvailableFeatures(
72 &TM.getSubtarget<X86Subtarget>()));
75 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
76 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
78 virtual bool ParseDirective(AsmToken DirectiveID);
81 class X86_32ATTAsmParser : public X86ATTAsmParser {
83 X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
84 : X86ATTAsmParser(T, _Parser, TM) {
89 class X86_64ATTAsmParser : public X86ATTAsmParser {
91 X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
92 : X86ATTAsmParser(T, _Parser, TM) {
97 } // end anonymous namespace
99 /// @name Auto-generated Match Functions
102 static unsigned MatchRegisterName(StringRef Name);
108 /// X86Operand - Instances of this class represent a parsed X86 machine
110 struct X86Operand : public MCParsedAsmOperand {
118 SMLoc StartLoc, EndLoc;
143 X86Operand(KindTy K, SMLoc Start, SMLoc End)
144 : Kind(K), StartLoc(Start), EndLoc(End) {}
146 /// getStartLoc - Get the location of the first token of this operand.
147 SMLoc getStartLoc() const { return StartLoc; }
148 /// getEndLoc - Get the location of the last token of this operand.
149 SMLoc getEndLoc() const { return EndLoc; }
151 virtual void dump(raw_ostream &OS) const {}
153 StringRef getToken() const {
154 assert(Kind == Token && "Invalid access!");
155 return StringRef(Tok.Data, Tok.Length);
157 void setTokenValue(StringRef Value) {
158 assert(Kind == Token && "Invalid access!");
159 Tok.Data = Value.data();
160 Tok.Length = Value.size();
163 unsigned getReg() const {
164 assert(Kind == Register && "Invalid access!");
168 const MCExpr *getImm() const {
169 assert(Kind == Immediate && "Invalid access!");
173 const MCExpr *getMemDisp() const {
174 assert(Kind == Memory && "Invalid access!");
177 unsigned getMemSegReg() const {
178 assert(Kind == Memory && "Invalid access!");
181 unsigned getMemBaseReg() const {
182 assert(Kind == Memory && "Invalid access!");
185 unsigned getMemIndexReg() const {
186 assert(Kind == Memory && "Invalid access!");
189 unsigned getMemScale() const {
190 assert(Kind == Memory && "Invalid access!");
194 bool isToken() const {return Kind == Token; }
196 bool isImm() const { return Kind == Immediate; }
198 bool isImmSExti16i8() const {
202 // If this isn't a constant expr, just assume it fits and let relaxation
204 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
208 // Otherwise, check the value is in a range that makes sense for this
210 uint64_t Value = CE->getValue();
211 return (( Value <= 0x000000000000007FULL)||
212 (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
213 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
215 bool isImmSExti32i8() const {
219 // If this isn't a constant expr, just assume it fits and let relaxation
221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
225 // Otherwise, check the value is in a range that makes sense for this
227 uint64_t Value = CE->getValue();
228 return (( Value <= 0x000000000000007FULL)||
229 (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
230 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
232 bool isImmSExti64i8() const {
236 // If this isn't a constant expr, just assume it fits and let relaxation
238 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
242 // Otherwise, check the value is in a range that makes sense for this
244 uint64_t Value = CE->getValue();
245 return (( Value <= 0x000000000000007FULL)||
246 (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
248 bool isImmSExti64i32() const {
252 // If this isn't a constant expr, just assume it fits and let relaxation
254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
258 // Otherwise, check the value is in a range that makes sense for this
260 uint64_t Value = CE->getValue();
261 return (( Value <= 0x000000007FFFFFFFULL)||
262 (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
265 bool isMem() const { return Kind == Memory; }
267 bool isAbsMem() const {
268 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
269 !getMemIndexReg() && getMemScale() == 1;
272 bool isReg() const { return Kind == Register; }
274 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
275 // Add as immediates when possible.
276 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
277 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
279 Inst.addOperand(MCOperand::CreateExpr(Expr));
282 void addRegOperands(MCInst &Inst, unsigned N) const {
283 assert(N == 1 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::CreateReg(getReg()));
287 void addImmOperands(MCInst &Inst, unsigned N) const {
288 assert(N == 1 && "Invalid number of operands!");
289 addExpr(Inst, getImm());
292 void addMemOperands(MCInst &Inst, unsigned N) const {
293 assert((N == 5) && "Invalid number of operands!");
294 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
295 Inst.addOperand(MCOperand::CreateImm(getMemScale()));
296 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
297 addExpr(Inst, getMemDisp());
298 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
301 void addAbsMemOperands(MCInst &Inst, unsigned N) const {
302 assert((N == 1) && "Invalid number of operands!");
303 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
306 static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
307 X86Operand *Res = new X86Operand(Token, Loc, Loc);
308 Res->Tok.Data = Str.data();
309 Res->Tok.Length = Str.size();
313 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
314 X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
315 Res->Reg.RegNo = RegNo;
319 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
320 X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
325 /// Create an absolute memory operand.
326 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
328 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
330 Res->Mem.Disp = Disp;
331 Res->Mem.BaseReg = 0;
332 Res->Mem.IndexReg = 0;
337 /// Create a generalized memory operand.
338 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
339 unsigned BaseReg, unsigned IndexReg,
340 unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
341 // We should never just have a displacement, that should be parsed as an
342 // absolute memory operand.
343 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
345 // The scale should always be one of {1,2,4,8}.
346 assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
348 X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
349 Res->Mem.SegReg = SegReg;
350 Res->Mem.Disp = Disp;
351 Res->Mem.BaseReg = BaseReg;
352 Res->Mem.IndexReg = IndexReg;
353 Res->Mem.Scale = Scale;
358 } // end anonymous namespace.
361 bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
362 SMLoc &StartLoc, SMLoc &EndLoc) {
364 const AsmToken &TokPercent = Parser.getTok();
365 assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
366 StartLoc = TokPercent.getLoc();
367 Parser.Lex(); // Eat percent token.
369 const AsmToken &Tok = Parser.getTok();
370 if (Tok.isNot(AsmToken::Identifier))
371 return Error(Tok.getLoc(), "invalid register name");
373 // FIXME: Validate register for the current architecture; we have to do
374 // validation later, so maybe there is no need for this here.
375 RegNo = MatchRegisterName(Tok.getString());
377 // If the match failed, try the register name as lowercase.
379 RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
381 // FIXME: This should be done using Requires<In32BitMode> and
382 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
383 // can be also checked.
384 if (RegNo == X86::RIZ && !Is64Bit)
385 return Error(Tok.getLoc(), "riz register in 64-bit mode only");
387 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
388 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
390 EndLoc = Tok.getLoc();
391 Parser.Lex(); // Eat 'st'
393 // Check to see if we have '(4)' after %st.
394 if (getLexer().isNot(AsmToken::LParen))
399 const AsmToken &IntTok = Parser.getTok();
400 if (IntTok.isNot(AsmToken::Integer))
401 return Error(IntTok.getLoc(), "expected stack index");
402 switch (IntTok.getIntVal()) {
403 case 0: RegNo = X86::ST0; break;
404 case 1: RegNo = X86::ST1; break;
405 case 2: RegNo = X86::ST2; break;
406 case 3: RegNo = X86::ST3; break;
407 case 4: RegNo = X86::ST4; break;
408 case 5: RegNo = X86::ST5; break;
409 case 6: RegNo = X86::ST6; break;
410 case 7: RegNo = X86::ST7; break;
411 default: return Error(IntTok.getLoc(), "invalid stack index");
414 if (getParser().Lex().isNot(AsmToken::RParen))
415 return Error(Parser.getTok().getLoc(), "expected ')'");
417 EndLoc = Tok.getLoc();
418 Parser.Lex(); // Eat ')'
422 // If this is "db[0-7]", match it as an alias
424 if (RegNo == 0 && Tok.getString().size() == 3 &&
425 Tok.getString().startswith("db")) {
426 switch (Tok.getString()[2]) {
427 case '0': RegNo = X86::DR0; break;
428 case '1': RegNo = X86::DR1; break;
429 case '2': RegNo = X86::DR2; break;
430 case '3': RegNo = X86::DR3; break;
431 case '4': RegNo = X86::DR4; break;
432 case '5': RegNo = X86::DR5; break;
433 case '6': RegNo = X86::DR6; break;
434 case '7': RegNo = X86::DR7; break;
438 EndLoc = Tok.getLoc();
439 Parser.Lex(); // Eat it.
445 return Error(Tok.getLoc(), "invalid register name");
447 EndLoc = Tok.getLoc();
448 Parser.Lex(); // Eat identifier token.
452 X86Operand *X86ATTAsmParser::ParseOperand() {
453 switch (getLexer().getKind()) {
455 // Parse a memory operand with no segment register.
456 return ParseMemOperand(0, Parser.getTok().getLoc());
457 case AsmToken::Percent: {
458 // Read the register.
461 if (ParseRegister(RegNo, Start, End)) return 0;
462 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
463 Error(Start, "eiz and riz can only be used as index registers");
467 // If this is a segment register followed by a ':', then this is the start
468 // of a memory reference, otherwise this is a normal register reference.
469 if (getLexer().isNot(AsmToken::Colon))
470 return X86Operand::CreateReg(RegNo, Start, End);
473 getParser().Lex(); // Eat the colon.
474 return ParseMemOperand(RegNo, Start);
476 case AsmToken::Dollar: {
478 SMLoc Start = Parser.getTok().getLoc(), End;
481 if (getParser().ParseExpression(Val, End))
483 return X86Operand::CreateImm(Val, Start, End);
488 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
489 /// has already been parsed if present.
490 X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
492 // We have to disambiguate a parenthesized expression "(4+5)" from the start
493 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
494 // only way to do this without lookahead is to eat the '(' and see what is
496 const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
497 if (getLexer().isNot(AsmToken::LParen)) {
499 if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
501 // After parsing the base expression we could either have a parenthesized
502 // memory address or not. If not, return now. If so, eat the (.
503 if (getLexer().isNot(AsmToken::LParen)) {
504 // Unless we have a segment register, treat this as an immediate.
506 return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
507 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
513 // Okay, we have a '('. We don't know if this is an expression or not, but
514 // so we have to eat the ( to see beyond it.
515 SMLoc LParenLoc = Parser.getTok().getLoc();
516 Parser.Lex(); // Eat the '('.
518 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
519 // Nothing to do here, fall into the code below with the '(' part of the
520 // memory operand consumed.
524 // It must be an parenthesized expression, parse it now.
525 if (getParser().ParseParenExpression(Disp, ExprEnd))
528 // After parsing the base expression we could either have a parenthesized
529 // memory address or not. If not, return now. If so, eat the (.
530 if (getLexer().isNot(AsmToken::LParen)) {
531 // Unless we have a segment register, treat this as an immediate.
533 return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
534 return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
542 // If we reached here, then we just ate the ( of the memory operand. Process
543 // the rest of the memory operand.
544 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
546 if (getLexer().is(AsmToken::Percent)) {
548 if (ParseRegister(BaseReg, L, L)) return 0;
549 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
550 Error(L, "eiz and riz can only be used as index registers");
555 if (getLexer().is(AsmToken::Comma)) {
556 Parser.Lex(); // Eat the comma.
558 // Following the comma we should have either an index register, or a scale
559 // value. We don't support the later form, but we want to parse it
562 // Not that even though it would be completely consistent to support syntax
563 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
564 if (getLexer().is(AsmToken::Percent)) {
566 if (ParseRegister(IndexReg, L, L)) return 0;
568 if (getLexer().isNot(AsmToken::RParen)) {
569 // Parse the scale amount:
570 // ::= ',' [scale-expression]
571 if (getLexer().isNot(AsmToken::Comma)) {
572 Error(Parser.getTok().getLoc(),
573 "expected comma in scale expression");
576 Parser.Lex(); // Eat the comma.
578 if (getLexer().isNot(AsmToken::RParen)) {
579 SMLoc Loc = Parser.getTok().getLoc();
582 if (getParser().ParseAbsoluteExpression(ScaleVal))
585 // Validate the scale amount.
586 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
587 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
590 Scale = (unsigned)ScaleVal;
593 } else if (getLexer().isNot(AsmToken::RParen)) {
594 // A scale amount without an index is ignored.
596 SMLoc Loc = Parser.getTok().getLoc();
599 if (getParser().ParseAbsoluteExpression(Value))
603 Warning(Loc, "scale factor without index register is ignored");
608 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
609 if (getLexer().isNot(AsmToken::RParen)) {
610 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
613 SMLoc MemEnd = Parser.getTok().getLoc();
614 Parser.Lex(); // Eat the ')'.
616 return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
620 bool X86ATTAsmParser::
621 ParseInstruction(StringRef Name, SMLoc NameLoc,
622 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
623 // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
624 // represent alternative syntaxes in the .td file, without requiring
625 // instruction duplication.
626 StringRef PatchedName = StringSwitch<StringRef>(Name)
628 .Case("salb", "shlb")
629 .Case("sall", "shll")
630 .Case("salq", "shlq")
631 .Case("salw", "shlw")
634 .Case("repnz", "repne")
635 .Case("iret", "iretl")
636 .Case("sysret", "sysretl")
637 .Case("push", Is64Bit ? "pushq" : "pushl")
638 .Case("pop", Is64Bit ? "popq" : "popl")
639 .Case("pushf", Is64Bit ? "pushfq" : "pushfl")
640 .Case("popf", Is64Bit ? "popfq" : "popfl")
641 .Case("pushfd", "pushfl")
642 .Case("popfd", "popfl")
643 .Case("retl", Is64Bit ? "retl" : "ret")
644 .Case("retq", Is64Bit ? "ret" : "retq")
645 .Case("setz", "sete") .Case("setnz", "setne")
646 .Case("setc", "setb") .Case("setna", "setbe")
647 .Case("setnae", "setb").Case("setnb", "setae")
648 .Case("setnbe", "seta").Case("setnc", "setae")
649 .Case("setng", "setle").Case("setnge", "setl")
650 .Case("setnl", "setge").Case("setnle", "setg")
651 .Case("setpe", "setp") .Case("setpo", "setnp")
652 .Case("jz", "je") .Case("jnz", "jne")
653 .Case("jc", "jb") .Case("jna", "jbe")
654 .Case("jnae", "jb").Case("jnb", "jae")
655 .Case("jnbe", "ja").Case("jnc", "jae")
656 .Case("jng", "jle").Case("jnge", "jl")
657 .Case("jnl", "jge").Case("jnle", "jg")
658 .Case("jpe", "jp") .Case("jpo", "jnp")
659 // Condition code aliases for 16-bit, 32-bit, 64-bit and unspec operands.
660 .Case("cmovcw", "cmovbw") .Case("cmovcl", "cmovbl")
661 .Case("cmovcq", "cmovbq") .Case("cmovc", "cmovb")
662 .Case("cmovnaew","cmovbw") .Case("cmovnael","cmovbl")
663 .Case("cmovnaeq","cmovbq") .Case("cmovnae", "cmovb")
664 .Case("cmovnaw", "cmovbew").Case("cmovnal", "cmovbel")
665 .Case("cmovnaq", "cmovbeq").Case("cmovna", "cmovbe")
666 .Case("cmovnbw", "cmovaew").Case("cmovnbl", "cmovael")
667 .Case("cmovnbq", "cmovaeq").Case("cmovnb", "cmovae")
668 .Case("cmovnbew","cmovaw") .Case("cmovnbel","cmoval")
669 .Case("cmovnbeq","cmovaq") .Case("cmovnbe", "cmova")
670 .Case("cmovncw", "cmovaew").Case("cmovncl", "cmovael")
671 .Case("cmovncq", "cmovaeq").Case("cmovnc", "cmovae")
672 .Case("cmovngw", "cmovlew").Case("cmovngl", "cmovlel")
673 .Case("cmovngq", "cmovleq").Case("cmovng", "cmovle")
674 .Case("cmovnw", "cmovgew").Case("cmovnl", "cmovgel")
675 .Case("cmovnq", "cmovgeq").Case("cmovn", "cmovge")
676 .Case("cmovngw", "cmovlew").Case("cmovngl", "cmovlel")
677 .Case("cmovngq", "cmovleq").Case("cmovng", "cmovle")
678 .Case("cmovngew","cmovlw") .Case("cmovngel","cmovll")
679 .Case("cmovngeq","cmovlq") .Case("cmovnge", "cmovl")
680 .Case("cmovnlw", "cmovgew").Case("cmovnll", "cmovgel")
681 .Case("cmovnlq", "cmovgeq").Case("cmovnl", "cmovge")
682 .Case("cmovnlew","cmovgw") .Case("cmovnlel","cmovgl")
683 .Case("cmovnleq","cmovgq") .Case("cmovnle", "cmovg")
684 .Case("cmovnzw", "cmovnew").Case("cmovnzl", "cmovnel")
685 .Case("cmovnzq", "cmovneq").Case("cmovnz", "cmovne")
686 .Case("cmovzw", "cmovew") .Case("cmovzl", "cmovel")
687 .Case("cmovzq", "cmoveq") .Case("cmovz", "cmove")
688 // Floating point stack cmov aliases.
689 .Case("fcmovz", "fcmove")
690 .Case("fcmova", "fcmovnbe")
691 .Case("fcmovnae", "fcmovb")
692 .Case("fcmovna", "fcmovbe")
693 .Case("fcmovae", "fcmovnb")
694 .Case("fwait", "wait")
695 .Case("movzx", "movzb") // FIXME: Not correct.
696 .Case("fildq", "fildll")
699 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
700 const MCExpr *ExtraImmOp = 0;
701 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
702 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
703 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
704 bool IsVCMP = PatchedName.startswith("vcmp");
705 unsigned SSECCIdx = IsVCMP ? 4 : 3;
706 unsigned SSEComparisonCode = StringSwitch<unsigned>(
707 PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
720 .Case("neq_oq", 0x0C)
727 .Case("unord_s", 0x13)
728 .Case("neq_us", 0x14)
729 .Case("nlt_uq", 0x15)
730 .Case("nle_uq", 0x16)
733 .Case("nge_uq", 0x19)
734 .Case("ngt_uq", 0x1A)
735 .Case("false_os", 0x1B)
736 .Case("neq_os", 0x1C)
739 .Case("true_us", 0x1F)
741 if (SSEComparisonCode != ~0U) {
742 ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
743 getParser().getContext());
744 if (PatchedName.endswith("ss")) {
745 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
746 } else if (PatchedName.endswith("sd")) {
747 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
748 } else if (PatchedName.endswith("ps")) {
749 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
751 assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
752 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
757 // FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
758 if (PatchedName.startswith("vpclmul")) {
759 unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
760 PatchedName.slice(7, PatchedName.size() - 2))
761 .Case("lqlq", 0x00) // src1[63:0], src2[63:0]
762 .Case("hqlq", 0x01) // src1[127:64], src2[63:0]
763 .Case("lqhq", 0x10) // src1[63:0], src2[127:64]
764 .Case("hqhq", 0x11) // src1[127:64], src2[127:64]
766 if (CLMULQuadWordSelect != ~0U) {
767 ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
768 getParser().getContext());
769 assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
770 PatchedName = "vpclmulqdq";
774 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
777 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
780 // Determine whether this is an instruction prefix.
782 PatchedName == "lock" || PatchedName == "rep" ||
783 PatchedName == "repne";
786 // This does the actual operand parsing. Don't parse any more if we have a
787 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
788 // just want to parse the "lock" as the first instruction and the "incl" as
790 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
792 // Parse '*' modifier.
793 if (getLexer().is(AsmToken::Star)) {
794 SMLoc Loc = Parser.getTok().getLoc();
795 Operands.push_back(X86Operand::CreateToken("*", Loc));
796 Parser.Lex(); // Eat the star.
799 // Read the first operand.
800 if (X86Operand *Op = ParseOperand())
801 Operands.push_back(Op);
803 Parser.EatToEndOfStatement();
807 while (getLexer().is(AsmToken::Comma)) {
808 Parser.Lex(); // Eat the comma.
810 // Parse and remember the operand.
811 if (X86Operand *Op = ParseOperand())
812 Operands.push_back(Op);
814 Parser.EatToEndOfStatement();
819 if (getLexer().isNot(AsmToken::EndOfStatement)) {
820 Parser.EatToEndOfStatement();
821 return TokError("unexpected token in argument list");
825 if (getLexer().is(AsmToken::EndOfStatement))
826 Parser.Lex(); // Consume the EndOfStatement
828 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
830 if ((Name.startswith("shr") || Name.startswith("sar") ||
831 Name.startswith("shl")) &&
832 Operands.size() == 3) {
833 X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
834 if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
835 cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
837 Operands.erase(Operands.begin() + 1);
841 // FIXME: Hack to handle recognize "rc[lr] <op>" -> "rcl $1, <op>".
842 if ((Name.startswith("rcl") || Name.startswith("rcr")) &&
843 Operands.size() == 2) {
844 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
845 Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc));
846 std::swap(Operands[1], Operands[2]);
849 // FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op".
850 if ((Name.startswith("shld") || Name.startswith("shrd")) &&
851 Operands.size() == 3) {
852 const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
853 Operands.insert(Operands.begin()+1,
854 X86Operand::CreateImm(One, NameLoc, NameLoc));
858 // FIXME: Hack to handle recognize "in[bwl] <op>". Canonicalize it to
860 if ((Name == "inb" || Name == "inw" || Name == "inl") &&
861 Operands.size() == 2) {
864 Reg = MatchRegisterName("al");
865 else if (Name[2] == 'w')
866 Reg = MatchRegisterName("ax");
868 Reg = MatchRegisterName("eax");
869 SMLoc Loc = Operands.back()->getEndLoc();
870 Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
873 // FIXME: Hack to handle recognize "out[bwl] <op>". Canonicalize it to
875 if ((Name == "outb" || Name == "outw" || Name == "outl") &&
876 Operands.size() == 2) {
879 Reg = MatchRegisterName("al");
880 else if (Name[3] == 'w')
881 Reg = MatchRegisterName("ax");
883 Reg = MatchRegisterName("eax");
884 SMLoc Loc = Operands.back()->getEndLoc();
885 Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
886 std::swap(Operands[1], Operands[2]);
889 // FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx".
890 if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
891 Operands.size() == 3) {
892 X86Operand &Op = *(X86Operand*)Operands.back();
893 if (Op.isMem() && Op.Mem.SegReg == 0 &&
894 isa<MCConstantExpr>(Op.Mem.Disp) &&
895 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
896 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
897 SMLoc Loc = Op.getEndLoc();
898 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
903 // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as
904 // "f{mul*,add*,sub*,div*} $op"
905 if ((Name.startswith("fmul") || Name.startswith("fadd") ||
906 Name.startswith("fsub") || Name.startswith("fdiv")) &&
907 Operands.size() == 3 &&
908 static_cast<X86Operand*>(Operands[2])->isReg() &&
909 static_cast<X86Operand*>(Operands[2])->getReg() == X86::ST0) {
911 Operands.erase(Operands.begin() + 2);
914 // FIXME: Hack to handle "imul <imm>, B" which is an alias for "imul <imm>, B,
916 if (Name.startswith("imul") && Operands.size() == 3 &&
917 static_cast<X86Operand*>(Operands[1])->isImm() &&
918 static_cast<X86Operand*>(Operands.back())->isReg()) {
919 X86Operand *Op = static_cast<X86Operand*>(Operands.back());
920 Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(),
924 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
925 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
926 // errors, since its encoding is the most compact.
927 if (Name == "sldt" && Operands.size() == 2 &&
928 static_cast<X86Operand*>(Operands[1])->isMem()) {
930 Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
933 // The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as
934 // synonyms. Our tables only have the "<reg>, <mem>" form, so if we see the
935 // other operand order, swap them.
936 if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"||
938 if (Operands.size() == 3 &&
939 static_cast<X86Operand*>(Operands[1])->isMem() &&
940 static_cast<X86Operand*>(Operands[2])->isReg()) {
941 std::swap(Operands[1], Operands[2]);
944 // The assembler accepts "testX <reg>, <mem>" and "testX <mem>, <reg>" as
945 // synonyms. Our tables only have the "<mem>, <reg>" form, so if we see the
946 // other operand order, swap them.
947 if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"||
949 if (Operands.size() == 3 &&
950 static_cast<X86Operand*>(Operands[1])->isReg() &&
951 static_cast<X86Operand*>(Operands[2])->isMem()) {
952 std::swap(Operands[1], Operands[2]);
955 // The assembler accepts these instructions with no operand as a synonym for
956 // an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
957 if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||
958 Name == "faddp" || Name == "fsubp" || Name == "fsubrp" ||
959 Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") &&
960 Operands.size() == 1) {
961 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
965 // The assembler accepts these instructions with two few operands as a synonym
966 // for taking %st(1),%st(0) or X, %st(0).
967 if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) {
968 if (Operands.size() == 1)
969 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
971 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
975 // The assembler accepts various amounts of brokenness for fnstsw.
976 if (Name == "fnstsw") {
977 if (Operands.size() == 2 &&
978 static_cast<X86Operand*>(Operands[1])->isReg()) {
979 // "fnstsw al" and "fnstsw eax" -> "fnstw"
980 unsigned Reg = static_cast<X86Operand*>(Operands[1])->Reg.RegNo;
981 if (Reg == MatchRegisterName("eax") ||
982 Reg == MatchRegisterName("al")) {
988 // "fnstw" -> "fnstw %ax"
989 if (Operands.size() == 1)
990 Operands.push_back(X86Operand::CreateReg(MatchRegisterName("ax"),
994 // jmp $42,$5 -> ljmp, similarly for call.
995 if ((Name.startswith("call") || Name.startswith("jmp")) &&
996 Operands.size() == 3 &&
997 static_cast<X86Operand*>(Operands[1])->isImm() &&
998 static_cast<X86Operand*>(Operands[2])->isImm()) {
999 const char *NewOpName = StringSwitch<const char *>(Name)
1000 .Case("jmp", "ljmp")
1001 .Case("jmpw", "ljmpw")
1002 .Case("jmpl", "ljmpl")
1003 .Case("jmpq", "ljmpq")
1004 .Case("call", "lcall")
1005 .Case("callw", "lcallw")
1006 .Case("calll", "lcalll")
1007 .Case("callq", "lcallq")
1011 Operands[0] = X86Operand::CreateToken(NewOpName, NameLoc);
1016 // lcall and ljmp -> lcalll and ljmpl
1017 if ((Name == "lcall" || Name == "ljmp") && Operands.size() == 3) {
1019 Operands[0] = X86Operand::CreateToken(Name == "lcall" ? "lcalll" : "ljmpl",
1023 // movsd -> movsl (when no operands are specified).
1024 if (Name == "movsd" && Operands.size() == 1) {
1026 Operands[0] = X86Operand::CreateToken("movsl", NameLoc);
1029 // fstp <mem> -> fstps <mem>. Without this, we'll default to fstpl due to
1030 // suffix searching.
1031 if (Name == "fstp" && Operands.size() == 2 &&
1032 static_cast<X86Operand*>(Operands[1])->isMem()) {
1034 Operands[0] = X86Operand::CreateToken("fstps", NameLoc);
1040 bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
1041 StringRef IDVal = DirectiveID.getIdentifier();
1042 if (IDVal == ".word")
1043 return ParseDirectiveWord(2, DirectiveID.getLoc());
1047 /// ParseDirectiveWord
1048 /// ::= .word [ expression (, expression)* ]
1049 bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1050 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1052 const MCExpr *Value;
1053 if (getParser().ParseExpression(Value))
1056 getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1058 if (getLexer().is(AsmToken::EndOfStatement))
1061 // FIXME: Improve diagnostic.
1062 if (getLexer().isNot(AsmToken::Comma))
1063 return Error(L, "unexpected token in directive");
1073 bool X86ATTAsmParser::
1074 MatchInstruction(SMLoc IDLoc,
1075 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1077 assert(!Operands.empty() && "Unexpect empty operand list!");
1079 bool WasOriginallyInvalidOperand = false;
1080 unsigned OrigErrorInfo;
1082 // First, try a direct match.
1083 switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
1086 case Match_MissingFeature:
1087 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1089 case Match_InvalidOperand:
1090 WasOriginallyInvalidOperand = true;
1092 case Match_MnemonicFail:
1096 // FIXME: Ideally, we would only attempt suffix matches for things which are
1097 // valid prefixes, and we could just infer the right unambiguous
1098 // type. However, that requires substantially more matcher support than the
1101 X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1102 assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1104 // Change the operand to point to a temporary token.
1105 StringRef Base = Op->getToken();
1106 SmallString<16> Tmp;
1109 Op->setTokenValue(Tmp.str());
1111 // Check for the various suffix matches.
1112 Tmp[Base.size()] = 'b';
1113 unsigned BErrorInfo, WErrorInfo, LErrorInfo, QErrorInfo;
1114 MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst, BErrorInfo);
1115 Tmp[Base.size()] = 'w';
1116 MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst, WErrorInfo);
1117 Tmp[Base.size()] = 'l';
1118 MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst, LErrorInfo);
1119 Tmp[Base.size()] = 'q';
1120 MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst, QErrorInfo);
1122 // Restore the old token.
1123 Op->setTokenValue(Base);
1125 // If exactly one matched, then we treat that as a successful match (and the
1126 // instruction will already have been filled in correctly, since the failing
1127 // matches won't have modified it).
1128 unsigned NumSuccessfulMatches =
1129 (MatchB == Match_Success) + (MatchW == Match_Success) +
1130 (MatchL == Match_Success) + (MatchQ == Match_Success);
1131 if (NumSuccessfulMatches == 1)
1134 // Otherwise, the match failed, try to produce a decent error message.
1136 // If we had multiple suffix matches, then identify this as an ambiguous
1138 if (NumSuccessfulMatches > 1) {
1140 unsigned NumMatches = 0;
1141 if (MatchB == Match_Success)
1142 MatchChars[NumMatches++] = 'b';
1143 if (MatchW == Match_Success)
1144 MatchChars[NumMatches++] = 'w';
1145 if (MatchL == Match_Success)
1146 MatchChars[NumMatches++] = 'l';
1147 if (MatchQ == Match_Success)
1148 MatchChars[NumMatches++] = 'q';
1150 SmallString<126> Msg;
1151 raw_svector_ostream OS(Msg);
1152 OS << "ambiguous instructions require an explicit suffix (could be ";
1153 for (unsigned i = 0; i != NumMatches; ++i) {
1156 if (i + 1 == NumMatches)
1158 OS << "'" << Base << MatchChars[i] << "'";
1161 Error(IDLoc, OS.str());
1165 // Okay, we know that none of the variants matched successfully.
1167 // If all of the instructions reported an invalid mnemonic, then the original
1168 // mnemonic was invalid.
1169 if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) &&
1170 (MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) {
1171 if (!WasOriginallyInvalidOperand) {
1172 Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
1176 // Recover location info for the operand if we know which was the problem.
1177 SMLoc ErrorLoc = IDLoc;
1178 if (OrigErrorInfo != ~0U) {
1179 if (OrigErrorInfo >= Operands.size())
1180 return Error(IDLoc, "too few operands for instruction");
1182 ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc();
1183 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1186 return Error(ErrorLoc, "invalid operand for instruction");
1189 // If one instruction matched with a missing feature, report this as a
1191 if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) +
1192 (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1){
1193 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1197 // If one instruction matched with an invalid operand, report this as an
1199 if ((MatchB == Match_InvalidOperand) + (MatchW == Match_InvalidOperand) +
1200 (MatchL == Match_InvalidOperand) + (MatchQ == Match_InvalidOperand) == 1){
1201 Error(IDLoc, "invalid operand for instruction");
1205 // If all of these were an outright failure, report it in a useless way.
1206 // FIXME: We should give nicer diagnostics about the exact failure.
1207 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
1212 extern "C" void LLVMInitializeX86AsmLexer();
1214 // Force static initialization.
1215 extern "C" void LLVMInitializeX86AsmParser() {
1216 RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
1217 RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
1218 LLVMInitializeX86AsmLexer();
1221 #define GET_REGISTER_MATCHER
1222 #define GET_MATCHER_IMPLEMENTATION
1223 #include "X86GenAsmMatcher.inc"