1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "X86AsmInstrumentation.h"
12 #include "X86Operand.h"
13 #include "X86RegisterInfo.h"
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/ADT/Triple.h"
16 #include "llvm/CodeGen/MachineValueType.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/MC/MCTargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
32 // Following comment describes how assembly instrumentation works.
33 // Currently we have only AddressSanitizer instrumentation, but we're
34 // planning to implement MemorySanitizer for inline assembly too. If
35 // you're not familiar with AddressSanitizer algorithm, please, read
36 // https://code.google.com/p/address-sanitizer/wiki/AddressSanitizerAlgorithm.
38 // When inline assembly is parsed by an instance of X86AsmParser, all
39 // instructions are emitted via EmitInstruction method. That's the
40 // place where X86AsmInstrumentation analyzes an instruction and
41 // decides, whether the instruction should be emitted as is or
42 // instrumentation is required. The latter case happens when an
43 // instruction reads from or writes to memory. Now instruction opcode
44 // is explicitly checked, and if an instruction has a memory operand
45 // (for instance, movq (%rsi, %rcx, 8), %rax) - it should be
46 // instrumented. There're also exist instructions that modify
47 // memory but don't have an explicit memory operands, for instance,
50 // Let's consider at first 8-byte memory accesses when an instruction
51 // has an explicit memory operand. In this case we need two registers -
52 // AddressReg to compute address of a memory cells which are accessed
53 // and ShadowReg to compute corresponding shadow address. So, we need
54 // to spill both registers before instrumentation code and restore them
55 // after instrumentation. Thus, in general, instrumentation code will
57 // PUSHF # Store flags, otherwise they will be overwritten
58 // PUSH AddressReg # spill AddressReg
59 // PUSH ShadowReg # spill ShadowReg
60 // LEA MemOp, AddressReg # compute address of the memory operand
61 // MOV AddressReg, ShadowReg
63 // # ShadowOffset(AddressReg >> 3) contains address of a shadow
64 // # corresponding to MemOp.
65 // CMP ShadowOffset(ShadowReg), 0 # test shadow value
66 // JZ .Done # when shadow equals to zero, everything is fine
67 // MOV AddressReg, RDI
68 // # Call __asan_report function with AddressReg as an argument
71 // POP ShadowReg # Restore ShadowReg
72 // POP AddressReg # Restore AddressReg
73 // POPF # Restore flags
75 // Memory accesses with different size (1-, 2-, 4- and 16-byte) are
76 // handled in a similar manner, but small memory accesses (less than 8
77 // byte) require an additional ScratchReg, which is used for shadow value.
79 // If, suppose, we're instrumenting an instruction like movs, only
80 // contents of RDI, RDI + AccessSize * RCX, RSI, RSI + AccessSize *
81 // RCX are checked. In this case there're no need to spill and restore
82 // AddressReg , ShadowReg or flags four times, they're saved on stack
83 // just once, before instrumentation of these four addresses, and restored
84 // at the end of the instrumentation.
86 // There exist several things which complicate this simple algorithm.
87 // * Instrumented memory operand can have RSP as a base or an index
88 // register. So we need to add a constant offset before computation
89 // of memory address, since flags, AddressReg, ShadowReg, etc. were
90 // already stored on stack and RSP was modified.
91 // * Debug info (usually, DWARF) should be adjusted, because sometimes
92 // RSP is used as a frame register. So, we need to select some
93 // register as a frame register and temprorary override current CFA
99 static cl::opt<bool> ClAsanInstrumentAssembly(
100 "asan-instrument-assembly",
101 cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
104 const int64_t MinAllowedDisplacement = std::numeric_limits<int32_t>::min();
105 const int64_t MaxAllowedDisplacement = std::numeric_limits<int32_t>::max();
107 int64_t ApplyDisplacementBounds(int64_t Displacement) {
108 return std::max(std::min(MaxAllowedDisplacement, Displacement),
109 MinAllowedDisplacement);
112 void CheckDisplacementBounds(int64_t Displacement) {
113 assert(Displacement >= MinAllowedDisplacement &&
114 Displacement <= MaxAllowedDisplacement);
117 bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; }
119 bool IsSmallMemAccess(unsigned AccessSize) { return AccessSize < 8; }
121 class X86AddressSanitizer : public X86AsmInstrumentation {
123 struct RegisterContext {
126 REG_OFFSET_ADDRESS = 0,
132 RegisterContext(unsigned AddressReg, unsigned ShadowReg,
133 unsigned ScratchReg) {
134 BusyRegs.push_back(convReg(AddressReg, MVT::i64));
135 BusyRegs.push_back(convReg(ShadowReg, MVT::i64));
136 BusyRegs.push_back(convReg(ScratchReg, MVT::i64));
139 unsigned AddressReg(MVT::SimpleValueType VT) const {
140 return convReg(BusyRegs[REG_OFFSET_ADDRESS], VT);
143 unsigned ShadowReg(MVT::SimpleValueType VT) const {
144 return convReg(BusyRegs[REG_OFFSET_SHADOW], VT);
147 unsigned ScratchReg(MVT::SimpleValueType VT) const {
148 return convReg(BusyRegs[REG_OFFSET_SCRATCH], VT);
151 void AddBusyReg(unsigned Reg) {
152 if (Reg != X86::NoRegister)
153 BusyRegs.push_back(convReg(Reg, MVT::i64));
156 void AddBusyRegs(const X86Operand &Op) {
157 AddBusyReg(Op.getMemBaseReg());
158 AddBusyReg(Op.getMemIndexReg());
161 unsigned ChooseFrameReg(MVT::SimpleValueType VT) const {
162 static const MCPhysReg Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
163 X86::RCX, X86::RDX, X86::RDI,
165 for (unsigned Reg : Candidates) {
166 if (!std::count(BusyRegs.begin(), BusyRegs.end(), Reg))
167 return convReg(Reg, VT);
169 return X86::NoRegister;
173 unsigned convReg(unsigned Reg, MVT::SimpleValueType VT) const {
174 return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, VT);
177 std::vector<unsigned> BusyRegs;
180 X86AddressSanitizer(const MCSubtargetInfo *&STI)
181 : X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
183 ~X86AddressSanitizer() override {}
185 // X86AsmInstrumentation implementation:
186 void InstrumentAndEmitInstruction(const MCInst &Inst,
187 OperandVector &Operands,
189 const MCInstrInfo &MII,
190 MCStreamer &Out) override {
191 InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
193 EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
195 InstrumentMOV(Inst, Operands, Ctx, MII, Out);
197 RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
199 EmitInstruction(Out, Inst);
202 // Adjusts up stack and saves all registers used in instrumentation.
203 virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
205 MCStreamer &Out) = 0;
207 // Restores all registers used in instrumentation and adjusts stack.
208 virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
210 MCStreamer &Out) = 0;
212 virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
214 const RegisterContext &RegCtx,
215 MCContext &Ctx, MCStreamer &Out) = 0;
216 virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
218 const RegisterContext &RegCtx,
219 MCContext &Ctx, MCStreamer &Out) = 0;
221 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
222 MCStreamer &Out) = 0;
224 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
225 const RegisterContext &RegCtx, MCContext &Ctx,
227 void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
228 unsigned AccessSize, MCContext &Ctx, MCStreamer &Out);
230 void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands,
231 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
232 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
233 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
236 void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
238 void EmitLEA(X86Operand &Op, MVT::SimpleValueType VT, unsigned Reg,
240 assert(VT == MVT::i32 || VT == MVT::i64);
242 Inst.setOpcode(VT == MVT::i32 ? X86::LEA32r : X86::LEA64r);
243 Inst.addOperand(MCOperand::createReg(getX86SubSuperRegister(Reg, VT)));
244 Op.addMemOperands(Inst, 5);
245 EmitInstruction(Out, Inst);
248 void ComputeMemOperandAddress(X86Operand &Op, MVT::SimpleValueType VT,
249 unsigned Reg, MCContext &Ctx, MCStreamer &Out);
251 // Creates new memory operand with Displacement added to an original
252 // displacement. Residue will contain a residue which could happen when the
253 // total displacement exceeds 32-bit limitation.
254 std::unique_ptr<X86Operand> AddDisplacement(X86Operand &Op,
255 int64_t Displacement,
256 MCContext &Ctx, int64_t *Residue);
258 bool is64BitMode() const {
259 return STI->getFeatureBits()[X86::Mode64Bit];
261 bool is32BitMode() const {
262 return STI->getFeatureBits()[X86::Mode32Bit];
264 bool is16BitMode() const {
265 return STI->getFeatureBits()[X86::Mode16Bit];
268 unsigned getPointerWidth() {
269 if (is16BitMode()) return 16;
270 if (is32BitMode()) return 32;
271 if (is64BitMode()) return 64;
272 llvm_unreachable("invalid mode");
275 // True when previous instruction was actually REP prefix.
278 // Offset from the original SP register.
279 int64_t OrigSPOffset;
282 void X86AddressSanitizer::InstrumentMemOperand(
283 X86Operand &Op, unsigned AccessSize, bool IsWrite,
284 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
285 assert(Op.isMem() && "Op should be a memory operand.");
286 assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
287 "AccessSize should be a power of two, less or equal than 16.");
288 // FIXME: take into account load/store alignment.
289 if (IsSmallMemAccess(AccessSize))
290 InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
292 InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
295 void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
298 MCContext &Ctx, MCStreamer &Out) {
299 // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
300 // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
301 RegisterContext RegCtx(X86::RDX /* AddressReg */, X86::RAX /* ShadowReg */,
302 IsSmallMemAccess(AccessSize)
304 : X86::NoRegister /* ScratchReg */);
305 RegCtx.AddBusyReg(DstReg);
306 RegCtx.AddBusyReg(SrcReg);
307 RegCtx.AddBusyReg(CntReg);
309 InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
313 const MCExpr *Disp = MCConstantExpr::create(0, Ctx);
314 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
315 getPointerWidth(), 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
316 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
320 // Test -1(%SrcReg, %CntReg, AccessSize)
322 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx);
323 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
324 getPointerWidth(), 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(),
326 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
332 const MCExpr *Disp = MCConstantExpr::create(0, Ctx);
333 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
334 getPointerWidth(), 0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
335 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
338 // Test -1(%DstReg, %CntReg, AccessSize)
340 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx);
341 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
342 getPointerWidth(), 0, Disp, DstReg, CntReg, AccessSize, SMLoc(),
344 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
347 InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
350 void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
351 OperandVector &Operands,
352 MCContext &Ctx, const MCInstrInfo &MII,
354 // Access size in bytes.
355 unsigned AccessSize = 0;
357 switch (Inst.getOpcode()) {
374 InstrumentMOVSImpl(AccessSize, Ctx, Out);
377 void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
378 OperandVector &Operands, MCContext &Ctx,
379 const MCInstrInfo &MII,
381 // Access size in bytes.
382 unsigned AccessSize = 0;
384 switch (Inst.getOpcode()) {
415 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
417 for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
418 assert(Operands[Ix]);
419 MCParsedAsmOperand &Op = *Operands[Ix];
421 X86Operand &MemOp = static_cast<X86Operand &>(Op);
422 RegisterContext RegCtx(
423 X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */,
424 IsSmallMemAccess(AccessSize) ? X86::RCX
425 : X86::NoRegister /* ScratchReg */);
426 RegCtx.AddBusyRegs(MemOp);
427 InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
428 InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out);
429 InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
434 void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
435 MVT::SimpleValueType VT,
436 unsigned Reg, MCContext &Ctx,
438 int64_t Displacement = 0;
439 if (IsStackReg(Op.getMemBaseReg()))
440 Displacement -= OrigSPOffset;
441 if (IsStackReg(Op.getMemIndexReg()))
442 Displacement -= OrigSPOffset * Op.getMemScale();
444 assert(Displacement >= 0);
447 if (Displacement == 0) {
448 EmitLEA(Op, VT, Reg, Out);
453 std::unique_ptr<X86Operand> NewOp =
454 AddDisplacement(Op, Displacement, Ctx, &Residue);
455 EmitLEA(*NewOp, VT, Reg, Out);
457 while (Residue != 0) {
458 const MCConstantExpr *Disp =
459 MCConstantExpr::create(ApplyDisplacementBounds(Residue), Ctx);
460 std::unique_ptr<X86Operand> DispOp =
461 X86Operand::CreateMem(getPointerWidth(), 0, Disp, Reg, 0, 1, SMLoc(),
463 EmitLEA(*DispOp, VT, Reg, Out);
464 Residue -= Disp->getValue();
468 std::unique_ptr<X86Operand>
469 X86AddressSanitizer::AddDisplacement(X86Operand &Op, int64_t Displacement,
470 MCContext &Ctx, int64_t *Residue) {
471 assert(Displacement >= 0);
473 if (Displacement == 0 ||
474 (Op.getMemDisp() && Op.getMemDisp()->getKind() != MCExpr::Constant)) {
475 *Residue = Displacement;
476 return X86Operand::CreateMem(Op.getMemModeSize(), Op.getMemSegReg(),
477 Op.getMemDisp(), Op.getMemBaseReg(),
478 Op.getMemIndexReg(), Op.getMemScale(),
482 int64_t OrigDisplacement =
483 static_cast<const MCConstantExpr *>(Op.getMemDisp())->getValue();
484 CheckDisplacementBounds(OrigDisplacement);
485 Displacement += OrigDisplacement;
487 int64_t NewDisplacement = ApplyDisplacementBounds(Displacement);
488 CheckDisplacementBounds(NewDisplacement);
490 *Residue = Displacement - NewDisplacement;
491 const MCExpr *Disp = MCConstantExpr::create(NewDisplacement, Ctx);
492 return X86Operand::CreateMem(Op.getMemModeSize(), Op.getMemSegReg(), Disp,
493 Op.getMemBaseReg(), Op.getMemIndexReg(),
494 Op.getMemScale(), SMLoc(), SMLoc());
497 class X86AddressSanitizer32 : public X86AddressSanitizer {
499 static const long kShadowOffset = 0x20000000;
501 X86AddressSanitizer32(const MCSubtargetInfo *&STI)
502 : X86AddressSanitizer(STI) {}
504 ~X86AddressSanitizer32() override {}
506 unsigned GetFrameReg(const MCContext &Ctx, MCStreamer &Out) {
507 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
508 if (FrameReg == X86::NoRegister)
510 return getX86SubSuperRegister(FrameReg, MVT::i32);
513 void SpillReg(MCStreamer &Out, unsigned Reg) {
514 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg));
518 void RestoreReg(MCStreamer &Out, unsigned Reg) {
519 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg));
523 void StoreFlags(MCStreamer &Out) {
524 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
528 void RestoreFlags(MCStreamer &Out) {
529 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
533 void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
535 MCStreamer &Out) override {
536 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
537 assert(LocalFrameReg != X86::NoRegister);
539 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
540 unsigned FrameReg = GetFrameReg(Ctx, Out);
541 if (MRI && FrameReg != X86::NoRegister) {
542 SpillReg(Out, LocalFrameReg);
543 if (FrameReg == X86::ESP) {
544 Out.EmitCFIAdjustCfaOffset(4 /* byte size of the LocalFrameReg */);
545 Out.EmitCFIRelOffset(
546 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
550 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg));
551 Out.EmitCFIRememberState();
552 Out.EmitCFIDefCfaRegister(
553 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
556 SpillReg(Out, RegCtx.AddressReg(MVT::i32));
557 SpillReg(Out, RegCtx.ShadowReg(MVT::i32));
558 if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
559 SpillReg(Out, RegCtx.ScratchReg(MVT::i32));
563 void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
565 MCStreamer &Out) override {
566 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i32);
567 assert(LocalFrameReg != X86::NoRegister);
570 if (RegCtx.ScratchReg(MVT::i32) != X86::NoRegister)
571 RestoreReg(Out, RegCtx.ScratchReg(MVT::i32));
572 RestoreReg(Out, RegCtx.ShadowReg(MVT::i32));
573 RestoreReg(Out, RegCtx.AddressReg(MVT::i32));
575 unsigned FrameReg = GetFrameReg(Ctx, Out);
576 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
577 RestoreReg(Out, LocalFrameReg);
578 Out.EmitCFIRestoreState();
579 if (FrameReg == X86::ESP)
580 Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the LocalFrameReg */);
584 void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
586 const RegisterContext &RegCtx,
588 MCStreamer &Out) override;
589 void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
591 const RegisterContext &RegCtx,
593 MCStreamer &Out) override;
594 void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
595 MCStreamer &Out) override;
598 void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
599 MCStreamer &Out, const RegisterContext &RegCtx) {
600 EmitInstruction(Out, MCInstBuilder(X86::CLD));
601 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
603 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
608 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(MVT::i32)));
610 MCSymbol *FnSym = Ctx.getOrCreateSymbol(llvm::Twine("__asan_report_") +
611 (IsWrite ? "store" : "load") +
612 llvm::Twine(AccessSize));
613 const MCSymbolRefExpr *FnExpr =
614 MCSymbolRefExpr::create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
615 EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
619 void X86AddressSanitizer32::InstrumentMemOperandSmall(
620 X86Operand &Op, unsigned AccessSize, bool IsWrite,
621 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
622 unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
623 unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
624 unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
626 assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
627 unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
629 ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
631 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
633 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
634 .addReg(ShadowRegI32)
635 .addReg(ShadowRegI32)
640 Inst.setOpcode(X86::MOV8rm);
641 Inst.addOperand(MCOperand::createReg(ShadowRegI8));
642 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx);
643 std::unique_ptr<X86Operand> Op(
644 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI32, 0, 1,
646 Op->addMemOperands(Inst, 5);
647 EmitInstruction(Out, Inst);
651 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
652 MCSymbol *DoneSym = Ctx.createTempSymbol();
653 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
654 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
656 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
658 EmitInstruction(Out, MCInstBuilder(X86::AND32ri)
659 .addReg(ScratchRegI32)
660 .addReg(ScratchRegI32)
663 switch (AccessSize) {
664 default: llvm_unreachable("Incorrect access size");
668 const MCExpr *Disp = MCConstantExpr::create(1, Ctx);
669 std::unique_ptr<X86Operand> Op(
670 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ScratchRegI32, 0, 1,
672 EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
676 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
677 .addReg(ScratchRegI32)
678 .addReg(ScratchRegI32)
685 MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
686 EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
688 EmitInstruction(Out, MCInstBuilder(X86::JL_1).addExpr(DoneExpr));
690 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
691 EmitLabel(Out, DoneSym);
694 void X86AddressSanitizer32::InstrumentMemOperandLarge(
695 X86Operand &Op, unsigned AccessSize, bool IsWrite,
696 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
697 unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
698 unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
700 ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
702 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
704 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
705 .addReg(ShadowRegI32)
706 .addReg(ShadowRegI32)
710 switch (AccessSize) {
711 default: llvm_unreachable("Incorrect access size");
713 Inst.setOpcode(X86::CMP8mi);
716 Inst.setOpcode(X86::CMP16mi);
719 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx);
720 std::unique_ptr<X86Operand> Op(
721 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI32, 0, 1,
723 Op->addMemOperands(Inst, 5);
724 Inst.addOperand(MCOperand::createImm(0));
725 EmitInstruction(Out, Inst);
727 MCSymbol *DoneSym = Ctx.createTempSymbol();
728 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
729 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
731 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
732 EmitLabel(Out, DoneSym);
735 void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
740 // No need to test when ECX is equals to zero.
741 MCSymbol *DoneSym = Ctx.createTempSymbol();
742 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
744 Out, MCInstBuilder(X86::TEST32rr).addReg(X86::ECX).addReg(X86::ECX));
745 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
747 // Instrument first and last elements in src and dst range.
748 InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
749 X86::ECX /* CntReg */, AccessSize, Ctx, Out);
751 EmitLabel(Out, DoneSym);
755 class X86AddressSanitizer64 : public X86AddressSanitizer {
757 static const long kShadowOffset = 0x7fff8000;
759 X86AddressSanitizer64(const MCSubtargetInfo *&STI)
760 : X86AddressSanitizer(STI) {}
762 ~X86AddressSanitizer64() override {}
764 unsigned GetFrameReg(const MCContext &Ctx, MCStreamer &Out) {
765 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
766 if (FrameReg == X86::NoRegister)
768 return getX86SubSuperRegister(FrameReg, MVT::i64);
771 void SpillReg(MCStreamer &Out, unsigned Reg) {
772 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(Reg));
776 void RestoreReg(MCStreamer &Out, unsigned Reg) {
777 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(Reg));
781 void StoreFlags(MCStreamer &Out) {
782 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
786 void RestoreFlags(MCStreamer &Out) {
787 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
791 void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
793 MCStreamer &Out) override {
794 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
795 assert(LocalFrameReg != X86::NoRegister);
797 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
798 unsigned FrameReg = GetFrameReg(Ctx, Out);
799 if (MRI && FrameReg != X86::NoRegister) {
800 SpillReg(Out, X86::RBP);
801 if (FrameReg == X86::RSP) {
802 Out.EmitCFIAdjustCfaOffset(8 /* byte size of the LocalFrameReg */);
803 Out.EmitCFIRelOffset(
804 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
808 MCInstBuilder(X86::MOV64rr).addReg(LocalFrameReg).addReg(FrameReg));
809 Out.EmitCFIRememberState();
810 Out.EmitCFIDefCfaRegister(
811 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
814 EmitAdjustRSP(Ctx, Out, -128);
815 SpillReg(Out, RegCtx.ShadowReg(MVT::i64));
816 SpillReg(Out, RegCtx.AddressReg(MVT::i64));
817 if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
818 SpillReg(Out, RegCtx.ScratchReg(MVT::i64));
822 void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
824 MCStreamer &Out) override {
825 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(MVT::i64);
826 assert(LocalFrameReg != X86::NoRegister);
829 if (RegCtx.ScratchReg(MVT::i64) != X86::NoRegister)
830 RestoreReg(Out, RegCtx.ScratchReg(MVT::i64));
831 RestoreReg(Out, RegCtx.AddressReg(MVT::i64));
832 RestoreReg(Out, RegCtx.ShadowReg(MVT::i64));
833 EmitAdjustRSP(Ctx, Out, 128);
835 unsigned FrameReg = GetFrameReg(Ctx, Out);
836 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
837 RestoreReg(Out, LocalFrameReg);
838 Out.EmitCFIRestoreState();
839 if (FrameReg == X86::RSP)
840 Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the LocalFrameReg */);
844 void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
846 const RegisterContext &RegCtx,
848 MCStreamer &Out) override;
849 void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
851 const RegisterContext &RegCtx,
853 MCStreamer &Out) override;
854 void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
855 MCStreamer &Out) override;
858 void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
859 const MCExpr *Disp = MCConstantExpr::create(Offset, Ctx);
860 std::unique_ptr<X86Operand> Op(
861 X86Operand::CreateMem(getPointerWidth(), 0, Disp, X86::RSP, 0, 1,
863 EmitLEA(*Op, MVT::i64, X86::RSP, Out);
864 OrigSPOffset += Offset;
867 void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
868 MCStreamer &Out, const RegisterContext &RegCtx) {
869 EmitInstruction(Out, MCInstBuilder(X86::CLD));
870 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
872 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
877 if (RegCtx.AddressReg(MVT::i64) != X86::RDI) {
878 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg(
879 RegCtx.AddressReg(MVT::i64)));
881 MCSymbol *FnSym = Ctx.getOrCreateSymbol(llvm::Twine("__asan_report_") +
882 (IsWrite ? "store" : "load") +
883 llvm::Twine(AccessSize));
884 const MCSymbolRefExpr *FnExpr =
885 MCSymbolRefExpr::create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
886 EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
890 void X86AddressSanitizer64::InstrumentMemOperandSmall(
891 X86Operand &Op, unsigned AccessSize, bool IsWrite,
892 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
893 unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
894 unsigned AddressRegI32 = RegCtx.AddressReg(MVT::i32);
895 unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
896 unsigned ShadowRegI32 = RegCtx.ShadowReg(MVT::i32);
897 unsigned ShadowRegI8 = RegCtx.ShadowReg(MVT::i8);
899 assert(RegCtx.ScratchReg(MVT::i32) != X86::NoRegister);
900 unsigned ScratchRegI32 = RegCtx.ScratchReg(MVT::i32);
902 ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
904 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
906 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
907 .addReg(ShadowRegI64)
908 .addReg(ShadowRegI64)
912 Inst.setOpcode(X86::MOV8rm);
913 Inst.addOperand(MCOperand::createReg(ShadowRegI8));
914 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx);
915 std::unique_ptr<X86Operand> Op(
916 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI64, 0, 1,
918 Op->addMemOperands(Inst, 5);
919 EmitInstruction(Out, Inst);
923 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
924 MCSymbol *DoneSym = Ctx.createTempSymbol();
925 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
926 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
928 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
930 EmitInstruction(Out, MCInstBuilder(X86::AND32ri)
931 .addReg(ScratchRegI32)
932 .addReg(ScratchRegI32)
935 switch (AccessSize) {
936 default: llvm_unreachable("Incorrect access size");
940 const MCExpr *Disp = MCConstantExpr::create(1, Ctx);
941 std::unique_ptr<X86Operand> Op(
942 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ScratchRegI32, 0, 1,
944 EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
948 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
949 .addReg(ScratchRegI32)
950 .addReg(ScratchRegI32)
957 MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
958 EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
960 EmitInstruction(Out, MCInstBuilder(X86::JL_1).addExpr(DoneExpr));
962 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
963 EmitLabel(Out, DoneSym);
966 void X86AddressSanitizer64::InstrumentMemOperandLarge(
967 X86Operand &Op, unsigned AccessSize, bool IsWrite,
968 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
969 unsigned AddressRegI64 = RegCtx.AddressReg(MVT::i64);
970 unsigned ShadowRegI64 = RegCtx.ShadowReg(MVT::i64);
972 ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
974 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
976 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
977 .addReg(ShadowRegI64)
978 .addReg(ShadowRegI64)
982 switch (AccessSize) {
983 default: llvm_unreachable("Incorrect access size");
985 Inst.setOpcode(X86::CMP8mi);
988 Inst.setOpcode(X86::CMP16mi);
991 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx);
992 std::unique_ptr<X86Operand> Op(
993 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI64, 0, 1,
995 Op->addMemOperands(Inst, 5);
996 Inst.addOperand(MCOperand::createImm(0));
997 EmitInstruction(Out, Inst);
1000 MCSymbol *DoneSym = Ctx.createTempSymbol();
1001 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
1002 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
1004 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
1005 EmitLabel(Out, DoneSym);
1008 void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
1013 // No need to test when RCX is equals to zero.
1014 MCSymbol *DoneSym = Ctx.createTempSymbol();
1015 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
1017 Out, MCInstBuilder(X86::TEST64rr).addReg(X86::RCX).addReg(X86::RCX));
1018 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
1020 // Instrument first and last elements in src and dst range.
1021 InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */,
1022 X86::RCX /* CntReg */, AccessSize, Ctx, Out);
1024 EmitLabel(Out, DoneSym);
1028 } // End anonymous namespace
1030 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo *&STI)
1031 : STI(STI), InitialFrameReg(0) {}
1033 X86AsmInstrumentation::~X86AsmInstrumentation() {}
1035 void X86AsmInstrumentation::InstrumentAndEmitInstruction(
1036 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
1037 const MCInstrInfo &MII, MCStreamer &Out) {
1038 EmitInstruction(Out, Inst);
1041 void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
1042 const MCInst &Inst) {
1043 Out.EmitInstruction(Inst, *STI);
1046 unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx,
1048 if (!Out.getNumFrameInfos()) // No active dwarf frame
1049 return X86::NoRegister;
1050 const MCDwarfFrameInfo &Frame = Out.getDwarfFrameInfos().back();
1051 if (Frame.End) // Active dwarf frame is closed
1052 return X86::NoRegister;
1053 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
1054 if (!MRI) // No register info
1055 return X86::NoRegister;
1057 if (InitialFrameReg) {
1058 // FrameReg is set explicitly, we're instrumenting a MachineFunction.
1059 return InitialFrameReg;
1062 return MRI->getLLVMRegNum(Frame.CurrentCfaRegister, true /* IsEH */);
1065 X86AsmInstrumentation *
1066 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
1067 const MCContext &Ctx, const MCSubtargetInfo *&STI) {
1068 Triple T(STI->getTargetTriple());
1069 const bool hasCompilerRTSupport = T.isOSLinux();
1070 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
1071 MCOptions.SanitizeAddress) {
1072 if (STI->getFeatureBits()[X86::Mode32Bit] != 0)
1073 return new X86AddressSanitizer32(STI);
1074 if (STI->getFeatureBits()[X86::Mode64Bit] != 0)
1075 return new X86AddressSanitizer64(STI);
1077 return new X86AsmInstrumentation(STI);
1080 } // end llvm namespace