lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

   1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "MCTargetDesc/X86BaseInfo.h"
  11 #include "X86AsmInstrumentation.h"
  12 #include "X86Operand.h"
  13 #include "llvm/ADT/StringExtras.h"
  14 #include "llvm/ADT/Triple.h"
  15 #include "llvm/IR/Function.h"
  16 #include "llvm/MC/MCContext.h"
  17 #include "llvm/MC/MCInst.h"
  18 #include "llvm/MC/MCInstBuilder.h"
  19 #include "llvm/MC/MCInstrInfo.h"
  20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
  21 #include "llvm/MC/MCStreamer.h"
  22 #include "llvm/MC/MCSubtargetInfo.h"
  23 #include "llvm/MC/MCTargetAsmParser.h"
  24 #include "llvm/MC/MCTargetOptions.h"
  25 #include "llvm/Support/CommandLine.h"
  26
  27 namespace llvm {
  28 namespace {
  29
  30 static cl::opt<bool> ClAsanInstrumentAssembly(
  31     "asan-instrument-assembly",
  32     cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
  33     cl::init(false));
  34
  35 bool IsStackReg(unsigned Reg) {
  36   return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
  37 }
  38
  39 std::string FuncName(unsigned AccessSize, bool IsWrite) {
  40   return std::string("__asan_report_") + (IsWrite ? "store" : "load") +
  41          utostr(AccessSize);
  42 }
  43
  44 class X86AddressSanitizer : public X86AsmInstrumentation {
  45  public:
  46   X86AddressSanitizer(const MCSubtargetInfo &STI)
  47       : X86AsmInstrumentation(STI), RepPrefix(false) {}
  48   virtual ~X86AddressSanitizer() {}
  49
  50   // X86AsmInstrumentation implementation:
  51   virtual void InstrumentAndEmitInstruction(const MCInst &Inst,
  52                                             OperandVector &Operands,
  53                                             MCContext &Ctx,
  54                                             const MCInstrInfo &MII,
  55                                             MCStreamer &Out) override {
  56     InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
  57     if (RepPrefix) EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
  58
  59     InstrumentMOV(Inst, Operands, Ctx, MII, Out);
  60
  61     RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
  62     if (!RepPrefix) EmitInstruction(Out, Inst);
  63   }
  64
  65   // Should be implemented differently in x86_32 and x86_64 subclasses.
  66   virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
  67                                              unsigned AccessSize, bool IsWrite,
  68                                              MCContext &Ctx,
  69                                              MCStreamer &Out) = 0;
  70   virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
  71                                              unsigned AccessSize, bool IsWrite,
  72                                              MCContext &Ctx,
  73                                              MCStreamer &Out) = 0;
  74   virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
  75                                   MCStreamer &Out) = 0;
  76
  77   void InstrumentMemOperand(MCParsedAsmOperand &Op, unsigned AccessSize,
  78                             bool IsWrite, MCContext &Ctx, MCStreamer &Out);
  79   void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
  80                           unsigned AccessSize, MCContext &Ctx, MCStreamer &Out);
  81   void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands,
  82                       MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
  83   void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
  84                      MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
  85
  86   void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
  87
  88  protected:
  89   // True when previous instruction was actually REP prefix.
  90   bool RepPrefix;
  91 };
  92
  93 void X86AddressSanitizer::InstrumentMemOperand(MCParsedAsmOperand &Op,
  94                                                unsigned AccessSize,
  95                                                bool IsWrite, MCContext &Ctx,
  96                                                MCStreamer &Out) {
  97   assert(Op.isMem() && "Op should be a memory operand.");
  98   assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
  99          "AccessSize should be a power of two, less or equal than 16.");
 100
 101   X86Operand &MemOp = static_cast<X86Operand &>(Op);
 102   // FIXME: get rid of this limitation.
 103   if (IsStackReg(MemOp.getMemBaseReg()) || IsStackReg(MemOp.getMemIndexReg()))
 104     return;
 105
 106   // FIXME: take into account load/store alignment.
 107   if (AccessSize < 8)
 108     InstrumentMemOperandSmallImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
 109   else
 110     InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
 111 }
 112
 113 void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
 114                                              unsigned CntReg,
 115                                              unsigned AccessSize,
 116                                              MCContext &Ctx, MCStreamer &Out) {
 117   // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
 118   // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
 119
 120   // FIXME: extract prolog and epilogue from InstrumentMemOperand()
 121   // and optimize this sequence of InstrumentMemOperand() calls.
 122
 123   // Test (%SrcReg)
 124   {
 125     const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
 126     std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
 127         0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
 128     InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, Ctx, Out);
 129   }
 130
 131   // Test -1(%SrcReg, %CntReg, AccessSize)
 132   {
 133     const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
 134     std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
 135         0, Disp, SrcReg, CntReg, AccessSize, SMLoc(), SMLoc()));
 136     InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, Ctx, Out);
 137   }
 138
 139   // Test (%DstReg)
 140   {
 141     const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
 142     std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
 143         0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
 144     InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, Ctx, Out);
 145   }
 146
 147   // Test -1(%DstReg, %CntReg, AccessSize)
 148   {
 149     const MCExpr *Disp = MCConstantExpr::Create(-1, Ctx);
 150     std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
 151         0, Disp, DstReg, CntReg, AccessSize, SMLoc(), SMLoc()));
 152     InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, Ctx, Out);
 153   }
 154 }
 155
 156 void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
 157                                          OperandVector &Operands,
 158                                          MCContext &Ctx, const MCInstrInfo &MII,
 159                                          MCStreamer &Out) {
 160   // Access size in bytes.
 161   unsigned AccessSize = 0;
 162
 163   switch (Inst.getOpcode()) {
 164     case X86::MOVSB:
 165       AccessSize = 1;
 166       break;
 167     case X86::MOVSW:
 168       AccessSize = 2;
 169       break;
 170     case X86::MOVSL:
 171       AccessSize = 4;
 172       break;
 173     case X86::MOVSQ:
 174       AccessSize = 8;
 175       break;
 176     default:
 177       return;
 178   }
 179
 180   InstrumentMOVSImpl(AccessSize, Ctx, Out);
 181 }
 182
 183 void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
 184                                         OperandVector &Operands, MCContext &Ctx,
 185                                         const MCInstrInfo &MII,
 186                                         MCStreamer &Out) {
 187   // Access size in bytes.
 188   unsigned AccessSize = 0;
 189
 190   switch (Inst.getOpcode()) {
 191     case X86::MOV8mi:
 192     case X86::MOV8mr:
 193     case X86::MOV8rm:
 194       AccessSize = 1;
 195       break;
 196     case X86::MOV16mi:
 197     case X86::MOV16mr:
 198     case X86::MOV16rm:
 199       AccessSize = 2;
 200       break;
 201     case X86::MOV32mi:
 202     case X86::MOV32mr:
 203     case X86::MOV32rm:
 204       AccessSize = 4;
 205       break;
 206     case X86::MOV64mi32:
 207     case X86::MOV64mr:
 208     case X86::MOV64rm:
 209       AccessSize = 8;
 210       break;
 211     case X86::MOVAPDmr:
 212     case X86::MOVAPSmr:
 213     case X86::MOVAPDrm:
 214     case X86::MOVAPSrm:
 215       AccessSize = 16;
 216       break;
 217     default:
 218       return;
 219   }
 220
 221   const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
 222   for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
 223     assert(Operands[Ix]);
 224     MCParsedAsmOperand &Op = *Operands[Ix];
 225     if (Op.isMem()) InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
 226   }
 227 }
 228
 229 class X86AddressSanitizer32 : public X86AddressSanitizer {
 230  public:
 231   static const long kShadowOffset = 0x20000000;
 232
 233   X86AddressSanitizer32(const MCSubtargetInfo &STI)
 234       : X86AddressSanitizer(STI) {}
 235   virtual ~X86AddressSanitizer32() {}
 236
 237   virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
 238                                              unsigned AccessSize, bool IsWrite,
 239                                              MCContext &Ctx,
 240                                              MCStreamer &Out) override;
 241   virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
 242                                              unsigned AccessSize, bool IsWrite,
 243                                              MCContext &Ctx,
 244                                              MCStreamer &Out) override;
 245   virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
 246                                   MCStreamer &Out) override;
 247
 248  private:
 249   void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
 250                           bool IsWrite, unsigned AddressReg) {
 251     EmitInstruction(Out, MCInstBuilder(X86::CLD));
 252     EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
 253
 254     EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
 255                              .addReg(X86::ESP)
 256                              .addReg(X86::ESP)
 257                              .addImm(-16));
 258     EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg));
 259
 260     const std::string &Fn = FuncName(AccessSize, IsWrite);
 261     MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
 262     const MCSymbolRefExpr *FnExpr =
 263         MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
 264     EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
 265   }
 266 };
 267
 268 void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(X86Operand &Op,
 269                                                           unsigned AccessSize,
 270                                                           bool IsWrite,
 271                                                           MCContext &Ctx,
 272                                                           MCStreamer &Out) {
 273   EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
 274   EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
 275   EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX));
 276   EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
 277
 278   {
 279     MCInst Inst;
 280     Inst.setOpcode(X86::LEA32r);
 281     Inst.addOperand(MCOperand::CreateReg(X86::EAX));
 282     Op.addMemOperands(Inst, 5);
 283     EmitInstruction(Out, Inst);
 284   }
 285
 286   EmitInstruction(
 287       Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
 288   EmitInstruction(
 289       Out,
 290       MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
 291
 292   {
 293     MCInst Inst;
 294     Inst.setOpcode(X86::MOV8rm);
 295     Inst.addOperand(MCOperand::CreateReg(X86::CL));
 296     const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
 297     std::unique_ptr<X86Operand> Op(
 298         X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
 299     Op->addMemOperands(Inst, 5);
 300     EmitInstruction(Out, Inst);
 301   }
 302
 303   EmitInstruction(Out,
 304                   MCInstBuilder(X86::TEST8rr).addReg(X86::CL).addReg(X86::CL));
 305   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
 306   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
 307   EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
 308
 309   EmitInstruction(
 310       Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX));
 311   EmitInstruction(
 312       Out,
 313       MCInstBuilder(X86::AND32ri).addReg(X86::EDX).addReg(X86::EDX).addImm(7));
 314
 315   switch (AccessSize) {
 316     case 1:
 317       break;
 318     case 2: {
 319       MCInst Inst;
 320       Inst.setOpcode(X86::LEA32r);
 321       Inst.addOperand(MCOperand::CreateReg(X86::EDX));
 322
 323       const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
 324       std::unique_ptr<X86Operand> Op(
 325           X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
 326       Op->addMemOperands(Inst, 5);
 327       EmitInstruction(Out, Inst);
 328       break;
 329     }
 330     case 4:
 331       EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
 332                                .addReg(X86::EDX)
 333                                .addReg(X86::EDX)
 334                                .addImm(3));
 335       break;
 336     default:
 337       assert(false && "Incorrect access size");
 338       break;
 339   }
 340
 341   EmitInstruction(
 342       Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::ECX).addReg(X86::CL));
 343   EmitInstruction(
 344       Out, MCInstBuilder(X86::CMP32rr).addReg(X86::EDX).addReg(X86::ECX));
 345   EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
 346
 347   EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
 348   EmitLabel(Out, DoneSym);
 349
 350   EmitInstruction(Out, MCInstBuilder(X86::POPF32));
 351   EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EDX));
 352   EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
 353   EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
 354 }
 355
 356 void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(X86Operand &Op,
 357                                                           unsigned AccessSize,
 358                                                           bool IsWrite,
 359                                                           MCContext &Ctx,
 360                                                           MCStreamer &Out) {
 361   EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
 362   EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
 363   EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
 364
 365   {
 366     MCInst Inst;
 367     Inst.setOpcode(X86::LEA32r);
 368     Inst.addOperand(MCOperand::CreateReg(X86::EAX));
 369     Op.addMemOperands(Inst, 5);
 370     EmitInstruction(Out, Inst);
 371   }
 372   EmitInstruction(
 373       Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
 374   EmitInstruction(
 375       Out,
 376       MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
 377   {
 378     MCInst Inst;
 379     switch (AccessSize) {
 380       case 8:
 381         Inst.setOpcode(X86::CMP8mi);
 382         break;
 383       case 16:
 384         Inst.setOpcode(X86::CMP16mi);
 385         break;
 386       default:
 387         assert(false && "Incorrect access size");
 388         break;
 389     }
 390     const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
 391     std::unique_ptr<X86Operand> Op(
 392         X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
 393     Op->addMemOperands(Inst, 5);
 394     Inst.addOperand(MCOperand::CreateImm(0));
 395     EmitInstruction(Out, Inst);
 396   }
 397   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
 398   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
 399   EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
 400
 401   EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite, X86::EAX);
 402   EmitLabel(Out, DoneSym);
 403
 404   EmitInstruction(Out, MCInstBuilder(X86::POPF32));
 405   EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::ECX));
 406   EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
 407 }
 408
 409 void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
 410                                                MCContext &Ctx,
 411                                                MCStreamer &Out) {
 412   EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
 413
 414   // No need to test when ECX is equals to zero.
 415   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
 416   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
 417   EmitInstruction(
 418       Out, MCInstBuilder(X86::TEST32rr).addReg(X86::ECX).addReg(X86::ECX));
 419   EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
 420
 421   // Instrument first and last elements in src and dst range.
 422   InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
 423                      X86::ECX /* CntReg */, AccessSize, Ctx, Out);
 424
 425   EmitLabel(Out, DoneSym);
 426   EmitInstruction(Out, MCInstBuilder(X86::POPF32));
 427 }
 428
 429 class X86AddressSanitizer64 : public X86AddressSanitizer {
 430  public:
 431   static const long kShadowOffset = 0x7fff8000;
 432
 433   X86AddressSanitizer64(const MCSubtargetInfo &STI)
 434       : X86AddressSanitizer(STI) {}
 435   virtual ~X86AddressSanitizer64() {}
 436
 437   virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
 438                                              unsigned AccessSize, bool IsWrite,
 439                                              MCContext &Ctx,
 440                                              MCStreamer &Out) override;
 441   virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
 442                                              unsigned AccessSize, bool IsWrite,
 443                                              MCContext &Ctx,
 444                                              MCStreamer &Out) override;
 445   virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
 446                                   MCStreamer &Out) override;
 447
 448  private:
 449   void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
 450     MCInst Inst;
 451     Inst.setOpcode(X86::LEA64r);
 452     Inst.addOperand(MCOperand::CreateReg(X86::RSP));
 453
 454     const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx);
 455     std::unique_ptr<X86Operand> Op(
 456         X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
 457     Op->addMemOperands(Inst, 5);
 458     EmitInstruction(Out, Inst);
 459   }
 460
 461   void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
 462                           bool IsWrite) {
 463     EmitInstruction(Out, MCInstBuilder(X86::CLD));
 464     EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
 465
 466     EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
 467                              .addReg(X86::RSP)
 468                              .addReg(X86::RSP)
 469                              .addImm(-16));
 470
 471     const std::string &Fn = FuncName(AccessSize, IsWrite);
 472     MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
 473     const MCSymbolRefExpr *FnExpr =
 474         MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
 475     EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
 476   }
 477 };
 478
 479 void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(X86Operand &Op,
 480                                                           unsigned AccessSize,
 481                                                           bool IsWrite,
 482                                                           MCContext &Ctx,
 483                                                           MCStreamer &Out) {
 484   EmitAdjustRSP(Ctx, Out, -128);
 485   EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
 486   EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX));
 487   EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RDI));
 488   EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
 489   {
 490     MCInst Inst;
 491     Inst.setOpcode(X86::LEA64r);
 492     Inst.addOperand(MCOperand::CreateReg(X86::RDI));
 493     Op.addMemOperands(Inst, 5);
 494     EmitInstruction(Out, Inst);
 495   }
 496   EmitInstruction(
 497       Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
 498   EmitInstruction(
 499       Out,
 500       MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
 501   {
 502     MCInst Inst;
 503     Inst.setOpcode(X86::MOV8rm);
 504     Inst.addOperand(MCOperand::CreateReg(X86::AL));
 505     const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
 506     std::unique_ptr<X86Operand> Op(
 507         X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
 508     Op->addMemOperands(Inst, 5);
 509     EmitInstruction(Out, Inst);
 510   }
 511
 512   EmitInstruction(Out,
 513                   MCInstBuilder(X86::TEST8rr).addReg(X86::AL).addReg(X86::AL));
 514   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
 515   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
 516   EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
 517
 518   EmitInstruction(
 519       Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI));
 520   EmitInstruction(
 521       Out,
 522       MCInstBuilder(X86::AND32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(7));
 523
 524   switch (AccessSize) {
 525     case 1:
 526       break;
 527     case 2: {
 528       MCInst Inst;
 529       Inst.setOpcode(X86::LEA32r);
 530       Inst.addOperand(MCOperand::CreateReg(X86::ECX));
 531
 532       const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
 533       std::unique_ptr<X86Operand> Op(
 534           X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
 535       Op->addMemOperands(Inst, 5);
 536       EmitInstruction(Out, Inst);
 537       break;
 538     }
 539     case 4:
 540       EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
 541                                .addReg(X86::ECX)
 542                                .addReg(X86::ECX)
 543                                .addImm(3));
 544       break;
 545     default:
 546       assert(false && "Incorrect access size");
 547       break;
 548   }
 549
 550   EmitInstruction(
 551       Out, MCInstBuilder(X86::MOVSX32rr8).addReg(X86::EAX).addReg(X86::AL));
 552   EmitInstruction(
 553       Out, MCInstBuilder(X86::CMP32rr).addReg(X86::ECX).addReg(X86::EAX));
 554   EmitInstruction(Out, MCInstBuilder(X86::JL_4).addExpr(DoneExpr));
 555
 556   EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite);
 557   EmitLabel(Out, DoneSym);
 558
 559   EmitInstruction(Out, MCInstBuilder(X86::POPF64));
 560   EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RDI));
 561   EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RCX));
 562   EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
 563   EmitAdjustRSP(Ctx, Out, 128);
 564 }
 565
 566 void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(X86Operand &Op,
 567                                                           unsigned AccessSize,
 568                                                           bool IsWrite,
 569                                                           MCContext &Ctx,
 570                                                           MCStreamer &Out) {
 571   EmitAdjustRSP(Ctx, Out, -128);
 572   EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
 573   EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
 574
 575   {
 576     MCInst Inst;
 577     Inst.setOpcode(X86::LEA64r);
 578     Inst.addOperand(MCOperand::CreateReg(X86::RAX));
 579     Op.addMemOperands(Inst, 5);
 580     EmitInstruction(Out, Inst);
 581   }
 582   EmitInstruction(
 583       Out,
 584       MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
 585   {
 586     MCInst Inst;
 587     switch (AccessSize) {
 588       case 8:
 589         Inst.setOpcode(X86::CMP8mi);
 590         break;
 591       case 16:
 592         Inst.setOpcode(X86::CMP16mi);
 593         break;
 594       default:
 595         assert(false && "Incorrect access size");
 596         break;
 597     }
 598     const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
 599     std::unique_ptr<X86Operand> Op(
 600         X86Operand::CreateMem(0, Disp, X86::RAX, 0, 1, SMLoc(), SMLoc()));
 601     Op->addMemOperands(Inst, 5);
 602     Inst.addOperand(MCOperand::CreateImm(0));
 603     EmitInstruction(Out, Inst);
 604   }
 605
 606   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
 607   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
 608   EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
 609
 610   EmitCallAsanReport(Ctx, Out, AccessSize, IsWrite);
 611   EmitLabel(Out, DoneSym);
 612
 613   EmitInstruction(Out, MCInstBuilder(X86::POPF64));
 614   EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(X86::RAX));
 615   EmitAdjustRSP(Ctx, Out, 128);
 616 }
 617
 618 void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
 619                                                MCContext &Ctx,
 620                                                MCStreamer &Out) {
 621   EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
 622
 623   // No need to test when RCX is equals to zero.
 624   MCSymbol *DoneSym = Ctx.CreateTempSymbol();
 625   const MCExpr *DoneExpr = MCSymbolRefExpr::Create(DoneSym, Ctx);
 626   EmitInstruction(
 627       Out, MCInstBuilder(X86::TEST64rr).addReg(X86::RCX).addReg(X86::RCX));
 628   EmitInstruction(Out, MCInstBuilder(X86::JE_4).addExpr(DoneExpr));
 629
 630   // Instrument first and last elements in src and dst range.
 631   InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */,
 632                      X86::RCX /* CntReg */, AccessSize, Ctx, Out);
 633
 634   EmitLabel(Out, DoneSym);
 635   EmitInstruction(Out, MCInstBuilder(X86::POPF64));
 636 }
 637
 638 }  // End anonymous namespace
 639
 640 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
 641     : STI(STI) {}
 642
 643 X86AsmInstrumentation::~X86AsmInstrumentation() {}
 644
 645 void X86AsmInstrumentation::InstrumentAndEmitInstruction(
 646     const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
 647     const MCInstrInfo &MII, MCStreamer &Out) {
 648   EmitInstruction(Out, Inst);
 649 }
 650
 651 void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
 652                                             const MCInst &Inst) {
 653   Out.EmitInstruction(Inst, STI);
 654 }
 655
 656 X86AsmInstrumentation *CreateX86AsmInstrumentation(
 657     const MCTargetOptions &MCOptions, const MCContext &Ctx,
 658     const MCSubtargetInfo &STI) {
 659   Triple T(STI.getTargetTriple());
 660   const bool hasCompilerRTSupport = T.isOSLinux();
 661   if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
 662       MCOptions.SanitizeAddress) {
 663     if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
 664       return new X86AddressSanitizer32(STI);
 665     if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
 666       return new X86AddressSanitizer64(STI);
 667   }
 668   return new X86AsmInstrumentation(STI);
 669 }
 670
 671 }  // End llvm namespace