1 //===-- WebAssemblyStoreResults.cpp - Optimize using store result values --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file implements an optimization pass using store result values.
13 /// WebAssembly's store instructions return the stored value, specifically to
14 /// enable the optimization of reducing get_local/set_local traffic, which is
15 /// what we're doing here.
17 //===----------------------------------------------------------------------===//
19 #include "WebAssembly.h"
20 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
21 #include "WebAssemblyMachineFunctionInfo.h"
22 #include "WebAssemblySubtarget.h"
23 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
31 #define DEBUG_TYPE "wasm-store-results"
34 class WebAssemblyStoreResults final : public MachineFunctionPass {
36 static char ID; // Pass identification, replacement for typeid
37 WebAssemblyStoreResults() : MachineFunctionPass(ID) {}
39 const char *getPassName() const override {
40 return "WebAssembly Store Results";
43 void getAnalysisUsage(AnalysisUsage &AU) const override {
45 AU.addRequired<MachineBlockFrequencyInfo>();
46 AU.addPreserved<MachineBlockFrequencyInfo>();
47 AU.addRequired<MachineDominatorTree>();
48 AU.addPreserved<MachineDominatorTree>();
49 MachineFunctionPass::getAnalysisUsage(AU);
52 bool runOnMachineFunction(MachineFunction &MF) override;
56 } // end anonymous namespace
58 char WebAssemblyStoreResults::ID = 0;
59 FunctionPass *llvm::createWebAssemblyStoreResults() {
60 return new WebAssemblyStoreResults();
63 bool WebAssemblyStoreResults::runOnMachineFunction(MachineFunction &MF) {
65 dbgs() << "********** Store Results **********\n"
66 << "********** Function: " << MF.getName() << '\n';
69 const MachineRegisterInfo &MRI = MF.getRegInfo();
70 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
72 for (auto &MBB : MF) {
73 DEBUG(dbgs() << "Basic Block: " << MBB.getName() << '\n');
75 switch (MI.getOpcode()) {
78 case WebAssembly::STORE8_I32:
79 case WebAssembly::STORE16_I32:
80 case WebAssembly::STORE8_I64:
81 case WebAssembly::STORE16_I64:
82 case WebAssembly::STORE32_I64:
83 case WebAssembly::STORE_F32:
84 case WebAssembly::STORE_F64:
85 case WebAssembly::STORE_I32:
86 case WebAssembly::STORE_I64:
87 unsigned ToReg = MI.getOperand(0).getReg();
88 unsigned FromReg = MI.getOperand(2).getReg();
89 for (auto I = MRI.use_begin(FromReg), E = MRI.use_end(); I != E;) {
90 MachineOperand &O = *I++;
91 MachineInstr *Where = O.getParent();
92 if (Where->getOpcode() == TargetOpcode::PHI)
93 Where = Where->getOperand(&O - &Where->getOperand(0) + 1)
95 ->getFirstTerminator();
96 if (&MI == Where || !MDT.dominates(&MI, Where))
98 DEBUG(dbgs() << "Setting operand " << O << " in " << *Where <<
99 " from " << MI <<"\n");