1 // WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief WebAssembly Memory operand code-gen constructs.
13 //===----------------------------------------------------------------------===//
17 // - WebAssemblyTargetLowering::isLegalAddressingMode
18 // - WebAssemblyTargetLowering having to do with atomics
19 // - Each has optional alignment and immediate byte offset.
21 // WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
22 // local types. These memory-only types instead zero- or sign-extend into local
23 // types when loading, and truncate when storing.
26 def LOAD_I32 : I<(outs I32:$dst), (ins I32:$addr),
27 [(set I32:$dst, (load I32:$addr))],
28 "i32.load\t$dst, $addr">;
29 def LOAD_I64 : I<(outs I64:$dst), (ins I32:$addr),
30 [(set I64:$dst, (load I32:$addr))],
31 "i64.load\t$dst, $addr">;
32 def LOAD_F32 : I<(outs F32:$dst), (ins I32:$addr),
33 [(set F32:$dst, (load I32:$addr))],
34 "f32.load\t$dst, $addr">;
35 def LOAD_F64 : I<(outs F64:$dst), (ins I32:$addr),
36 [(set F64:$dst, (load I32:$addr))],
37 "f64.load\t$dst, $addr">;
40 def LOAD8_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
41 [(set I32:$dst, (sextloadi8 I32:$addr))],
42 "i32.load8_s\t$dst, $addr">;
43 def LOAD8_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
44 [(set I32:$dst, (zextloadi8 I32:$addr))],
45 "i32.load8_u\t$dst, $addr">;
46 def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
47 [(set I32:$dst, (sextloadi16 I32:$addr))],
48 "i32.load16_s\t$dst, $addr">;
49 def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
50 [(set I32:$dst, (zextloadi16 I32:$addr))],
51 "i32.load16_u\t$dst, $addr">;
52 def LOAD8_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
53 [(set I64:$dst, (sextloadi8 I32:$addr))],
54 "i64.load8_s\t$dst, $addr">;
55 def LOAD8_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
56 [(set I64:$dst, (zextloadi8 I32:$addr))],
57 "i64.load8_u\t$dst, $addr">;
58 def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
59 [(set I64:$dst, (sextloadi16 I32:$addr))],
60 "i64.load16_s\t$dst, $addr">;
61 def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
62 [(set I64:$dst, (zextloadi16 I32:$addr))],
63 "i64.load16_u\t$dst, $addr">;
64 def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
65 [(set I64:$dst, (sextloadi32 I32:$addr))],
66 "i64.load32_s\t$dst, $addr">;
67 def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
68 [(set I64:$dst, (zextloadi32 I32:$addr))],
69 "i64.load32_u\t$dst, $addr">;
71 // "Don't care" extending load become zero-extending load.
72 def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 $addr)>;
73 def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 $addr)>;
74 def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 $addr)>;
75 def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 $addr)>;
76 def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 $addr)>;
79 // Note that we split the patterns out of the instruction definitions because
80 // WebAssembly's stores return their operand value, and tablegen doesn't like
81 // instruction definition patterns that don't reference all of the output
83 // Note: WebAssembly inverts SelectionDAG's usual operand order.
84 def STORE_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
85 "i32.store\t$dst, $addr, $val">;
86 def STORE_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
87 "i64.store\t$dst, $addr, $val">;
88 def STORE_F32 : I<(outs F32:$dst), (ins I32:$addr, F32:$val), [],
89 "f32.store\t$dst, $addr, $val">;
90 def STORE_F64 : I<(outs F64:$dst), (ins I32:$addr, F64:$val), [],
91 "f64.store\t$dst, $addr, $val">;
93 def : Pat<(store I32:$val, I32:$addr), (STORE_I32 I32:$addr, I32:$val)>;
94 def : Pat<(store I64:$val, I32:$addr), (STORE_I64 I32:$addr, I64:$val)>;
95 def : Pat<(store F32:$val, I32:$addr), (STORE_F32 I32:$addr, F32:$val)>;
96 def : Pat<(store F64:$val, I32:$addr), (STORE_F64 I32:$addr, F64:$val)>;
99 def STORE8_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
100 "i32.store8\t$dst, $addr, $val">;
101 def STORE16_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
102 "i32.store16\t$dst, $addr, $val">;
103 def STORE8_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
104 "i64.store8\t$dst, $addr, $val">;
105 def STORE16_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
106 "i64.store16\t$dst, $addr, $val">;
107 def STORE32_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
108 "i64.store32\t$dst, $addr, $val">;
110 def : Pat<(truncstorei8 I32:$val, I32:$addr),
111 (STORE8_I32 I32:$addr, I32:$val)>;
112 def : Pat<(truncstorei16 I32:$val, I32:$addr),
113 (STORE16_I32 I32:$addr, I32:$val)>;
114 def : Pat<(truncstorei8 I64:$val, I32:$addr),
115 (STORE8_I64 I32:$addr, I64:$val)>;
116 def : Pat<(truncstorei16 I64:$val, I32:$addr),
117 (STORE16_I64 I32:$addr, I64:$val)>;
118 def : Pat<(truncstorei32 I64:$val, I32:$addr),
119 (STORE32_I64 I32:$addr, I64:$val)>;
122 def MEMORY_SIZE_I32 : I<(outs I32:$dst), (ins),
123 [(set I32:$dst, (int_wasm_memory_size))],
124 "memory_size\t$dst">,
125 Requires<[HasAddr32]>;
126 def MEMORY_SIZE_I64 : I<(outs I64:$dst), (ins),
127 [(set I64:$dst, (int_wasm_memory_size))],
128 "memory_size\t$dst">,
129 Requires<[HasAddr64]>;
132 def GROW_MEMORY_I32 : I<(outs), (ins I32:$delta),
133 [(int_wasm_grow_memory I32:$delta)],
134 "grow_memory\t$delta">,
135 Requires<[HasAddr32]>;
136 def GROW_MEMORY_I64 : I<(outs), (ins I64:$delta),
137 [(int_wasm_grow_memory I64:$delta)],
138 "grow_memory\t$delta">,
139 Requires<[HasAddr64]>;