1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetRegisterInfo interface.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/Target/TargetFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/Support/raw_ostream.h"
24 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
25 regclass_iterator RCB, regclass_iterator RCE,
26 const char *const *subregindexnames,
28 const unsigned* subregs, const unsigned subregsize,
29 const unsigned* aliases, const unsigned aliasessize)
30 : SubregHash(subregs), SubregHashSize(subregsize),
31 AliasesHash(aliases), AliasesHashSize(aliasessize),
32 Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
33 RegClassBegin(RCB), RegClassEnd(RCE) {
34 assert(isPhysicalRegister(NumRegs) &&
35 "Target has too many physical registers!");
37 CallFrameSetupOpcode = CFSO;
38 CallFrameDestroyOpcode = CFDO;
41 TargetRegisterInfo::~TargetRegisterInfo() {}
43 void PrintReg::print(raw_ostream &OS) const {
46 else if (TargetRegisterInfo::isVirtualRegister(Reg))
47 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
49 OS << '%' << TRI->getName(Reg);
51 OS << "%physreg" << Reg;
54 OS << ':' << TRI->getSubRegIndexName(SubIdx);
56 OS << ":sub(" << SubIdx << ')';
60 /// getMinimalPhysRegClass - Returns the Register Class of a physical
61 /// register of the given type, picking the most sub register class of
62 /// the right type that contains this physreg.
63 const TargetRegisterClass *
64 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
65 assert(isPhysicalRegister(reg) && "reg must be a physical register");
67 // Pick the most sub register class of the right type that contains
69 const TargetRegisterClass* BestRC = 0;
70 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
71 const TargetRegisterClass* RC = *I;
72 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
73 (!BestRC || BestRC->hasSubClass(RC)))
77 assert(BestRC && "Couldn't find the register class");
81 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
82 /// registers for the specific register class.
83 static void getAllocatableSetForRC(const MachineFunction &MF,
84 const TargetRegisterClass *RC, BitVector &R){
85 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
86 E = RC->allocation_order_end(MF); I != E; ++I)
90 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
91 const TargetRegisterClass *RC) const {
92 BitVector Allocatable(NumRegs);
94 getAllocatableSetForRC(MF, RC, Allocatable);
96 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
97 E = regclass_end(); I != E; ++I)
98 getAllocatableSetForRC(MF, *I, Allocatable);
101 // Mask out the reserved registers
102 BitVector Reserved = getReservedRegs(MF);
103 Allocatable &= Reserved.flip();
108 const TargetRegisterClass *
109 llvm::getCommonSubClass(const TargetRegisterClass *A,
110 const TargetRegisterClass *B) {
111 // First take care of the trivial cases
117 // If B is a subclass of A, it will be handled in the loop below
118 if (B->hasSubClass(A))
121 const TargetRegisterClass *Best = 0;
122 for (TargetRegisterClass::sc_iterator I = A->subclasses_begin();
123 const TargetRegisterClass *X = *I; ++I) {
125 return B; // B is a subclass of A
127 // X must be a common subclass of A and B
128 if (!B->hasSubClass(X))
131 // A superclass is definitely better.
132 if (!Best || Best->hasSuperClass(X)) {
137 // A subclass is definitely worse
138 if (Best->hasSubClass(X))
141 // Best and *I have no super/sub class relation - pick the larger class, or
142 // the smaller spill size.
143 int nb = std::distance(Best->begin(), Best->end());
144 int ni = std::distance(X->begin(), X->end());
145 if (ni>nb || (ni==nb && X->getSize() < Best->getSize()))