1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Constant.h"
17 #include "llvm/DerivedTypes.h"
20 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
21 /// dest operand. Returns -1 if there isn't one.
22 int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
23 for (unsigned i = 0, e = numOperands; i != e; ++i) {
26 if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)
33 TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
35 : desc(Desc), NumOpcodes(numOpcodes) {
38 TargetInstrInfo::~TargetInstrInfo() {
41 // commuteInstruction - The default implementation of this method just exchanges
43 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
44 assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
45 "This only knows how to commute register operands so far");
46 unsigned Reg1 = MI->getOperand(1).getReg();
47 unsigned Reg2 = MI->getOperand(2).getReg();
48 bool Reg1IsKill = MI->getOperand(1).isKill();
49 bool Reg2IsKill = MI->getOperand(2).isKill();
50 MI->getOperand(2).setReg(Reg1);
51 MI->getOperand(1).setReg(Reg2);
52 MI->getOperand(2).setIsKill(Reg1IsKill);
53 MI->getOperand(1).setIsKill(Reg2IsKill);
57 bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
58 const std::vector<MachineOperand> &Pred) const {
59 bool MadeChange = false;
60 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
61 if (TID->Flags & M_PREDICABLE) {
62 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
63 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
64 MachineOperand &MO = MI->getOperand(i);
66 MO.setReg(Pred[j].getReg());
68 } else if (MO.isImm()) {
69 MO.setImm(Pred[j].getImm());
71 } else if (MO.isMBB()) {
72 MO.setMBB(Pred[j].getMBB());
82 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
83 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
84 if (TID->Flags & M_TERMINATOR_FLAG) {
85 // Conditional branch is a special case.
86 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
88 if ((TID->Flags & M_PREDICABLE) == 0)
90 return !isPredicated(MI);