1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "SystemZRegisterInfo.h"
11 #include "SystemZTargetMachine.h"
12 #include "llvm/CodeGen/MachineInstrBuilder.h"
13 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #define GET_REGINFO_TARGET_DESC
16 #include "SystemZGenRegisterInfo.inc"
20 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm)
21 : SystemZGenRegisterInfo(SystemZ::R14D), TM(tm) {}
24 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
25 static const uint16_t CalleeSavedRegs[] = {
26 SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
27 SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
28 SystemZ::R14D, SystemZ::R15D,
29 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
30 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
34 return CalleeSavedRegs;
38 SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
39 BitVector Reserved(getNumRegs());
40 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
43 // R11D is the frame pointer. Reserve all aliases.
44 Reserved.set(SystemZ::R11D);
45 Reserved.set(SystemZ::R11W);
46 Reserved.set(SystemZ::R10Q);
49 // R15D is the stack pointer. Reserve all aliases.
50 Reserved.set(SystemZ::R15D);
51 Reserved.set(SystemZ::R15W);
52 Reserved.set(SystemZ::R14Q);
57 SystemZRegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator SaveMBBI,
59 MachineBasicBlock::iterator &UseMBBI,
60 const TargetRegisterClass *RC,
62 MachineFunction &MF = *MBB.getParent();
63 const SystemZInstrInfo &TII =
64 *static_cast<const SystemZInstrInfo*>(TM.getInstrInfo());
65 const SystemZFrameLowering *TFI =
66 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
67 unsigned Base = getFrameRegister(MF);
68 uint64_t Offset = TFI->getEmergencySpillSlotOffset(MF);
71 unsigned LoadOpcode, StoreOpcode;
72 TII.getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
74 // The offset must always be in range of a 12-bit unsigned displacement.
75 BuildMI(MBB, SaveMBBI, DL, TII.get(StoreOpcode))
76 .addReg(Reg, RegState::Kill).addReg(Base).addImm(Offset).addReg(0);
77 BuildMI(MBB, UseMBBI, DL, TII.get(LoadOpcode), Reg)
78 .addReg(Base).addImm(Offset).addReg(0);
83 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
84 int SPAdj, unsigned FIOperandNum,
85 RegScavenger *RS) const {
86 assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
88 MachineBasicBlock &MBB = *MI->getParent();
89 MachineFunction &MF = *MBB.getParent();
90 const SystemZInstrInfo &TII =
91 *static_cast<const SystemZInstrInfo*>(TM.getInstrInfo());
92 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
93 DebugLoc DL = MI->getDebugLoc();
95 // Decompose the frame index into a base and offset.
96 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
97 unsigned BasePtr = getFrameRegister(MF);
98 int64_t Offset = (TFI->getFrameIndexOffset(MF, FrameIndex) +
99 MI->getOperand(FIOperandNum + 1).getImm());
101 // Special handling of dbg_value instructions.
102 if (MI->isDebugValue()) {
103 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
104 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
108 // See if the offset is in range, or if an equivalent instruction that
109 // accepts the offset exists.
110 unsigned Opcode = MI->getOpcode();
111 unsigned OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset);
113 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
115 // Create an anchor point that is in range. Start at 0xffff so that
116 // can use LLILH to load the immediate.
117 int64_t OldOffset = Offset;
118 int64_t Mask = 0xffff;
120 Offset = OldOffset & Mask;
121 OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset);
123 assert(Mask && "One offset must be OK");
124 } while (!OpcodeForOffset);
126 unsigned ScratchReg =
127 MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
128 int64_t HighOffset = OldOffset - Offset;
130 if (MI->getDesc().TSFlags & SystemZII::HasIndex
131 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
132 // Load the offset into the scratch register and use it as an index.
133 // The scratch register then dies here.
134 TII.loadImmediate(MBB, MI, ScratchReg, HighOffset);
135 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
136 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
139 // Load the anchor address into a scratch register.
140 unsigned LAOpcode = TII.getOpcodeForOffset(SystemZ::LA, HighOffset);
142 BuildMI(MBB, MI, DL, TII.get(LAOpcode),ScratchReg)
143 .addReg(BasePtr).addImm(HighOffset).addReg(0);
145 // Load the high offset into the scratch register and use it as
147 TII.loadImmediate(MBB, MI, ScratchReg, HighOffset);
148 BuildMI(MBB, MI, DL, TII.get(SystemZ::AGR),ScratchReg)
149 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
152 // Use the scratch register as the base. It then dies here.
153 MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
157 MI->setDesc(TII.get(OpcodeForOffset));
158 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
162 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
163 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
164 return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;