lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "SystemZInstrFormats.td"
  15
  16 //===----------------------------------------------------------------------===//
  17 // Type Constraints.
  18 //===----------------------------------------------------------------------===//
  19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  21 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  22 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  23
  24 //===----------------------------------------------------------------------===//
  25 // Type Profiles.
  26 //===----------------------------------------------------------------------===//
  27 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
  28 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  29 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  30 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  31 def SDT_BrCond              : SDTypeProfile<0, 2,
  32                                            [SDTCisVT<0, OtherVT>,
  33                                             SDTCisI8<1>]>;
  34 def SDT_SelectCC            : SDTypeProfile<1, 3,
  35                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  36                                             SDTCisI8<3>]>;
  37
  38
  39 //===----------------------------------------------------------------------===//
  40 // SystemZ Specific Node Definitions.
  41 //===----------------------------------------------------------------------===//
  42 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  43                      [SDNPHasChain, SDNPOptInFlag]>;
  44 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  45                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  46 def SystemZcallseq_start :
  47                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  48                         [SDNPHasChain, SDNPOutFlag]>;
  49 def SystemZcallseq_end :
  50                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  51                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  52 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  53 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  54 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  55                             [SDNPHasChain, SDNPInFlag]>;
  56 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  57
  58 //===----------------------------------------------------------------------===//
  59 // Instruction Pattern Stuff.
  60 //===----------------------------------------------------------------------===//
  61
  62 // SystemZ specific condition code. These correspond to CondCode in
  63 // SystemZ.h. They must be kept in synch.
  64 def SYSTEMZ_COND_E  : PatLeaf<(i8 0)>;
  65 def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>;
  66 def SYSTEMZ_COND_H  : PatLeaf<(i8 2)>;
  67 def SYSTEMZ_COND_L  : PatLeaf<(i8 3)>;
  68 def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>;
  69 def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>;
  70
  71 def LL16 : SDNodeXForm<imm, [{
  72   // Transformation function: return low 16 bits.
  73   return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
  74 }]>;
  75
  76 def LH16 : SDNodeXForm<imm, [{
  77   // Transformation function: return bits 16-31.
  78   return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
  79 }]>;
  80
  81 def HL16 : SDNodeXForm<imm, [{
  82   // Transformation function: return bits 32-47.
  83   return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
  84 }]>;
  85
  86 def HH16 : SDNodeXForm<imm, [{
  87   // Transformation function: return bits 48-63.
  88   return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
  89 }]>;
  90
  91 def LO32 : SDNodeXForm<imm, [{
  92   // Transformation function: return low 32 bits.
  93   return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
  94 }]>;
  95
  96 def HI32 : SDNodeXForm<imm, [{
  97   // Transformation function: return bits 32-63.
  98   return getI32Imm(N->getZExtValue() >> 32);
  99 }]>;
 100
 101 def i64ll16 : PatLeaf<(imm), [{
 102   // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
 103   // bits set.
 104   return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
 105 }], LL16>;
 106
 107 def i64lh16 : PatLeaf<(imm), [{
 108   // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
 109   return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
 110 }], LH16>;
 111
 112 def i64hl16 : PatLeaf<(i64 imm), [{
 113   // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
 114   return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
 115 }], HL16>;
 116
 117 def i64hh16 : PatLeaf<(i64 imm), [{
 118   // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
 119   return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
 120 }], HH16>;
 121
 122 def immSExt16 : PatLeaf<(imm), [{
 123   // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
 124   // field.
 125   if (N->getValueType(0) == MVT::i64) {
 126     uint64_t val = N->getZExtValue();
 127     return ((int64_t)val == (int16_t)val);
 128   } else if (N->getValueType(0) == MVT::i32) {
 129     uint32_t val = N->getZExtValue();
 130     return ((int32_t)val == (int16_t)val);
 131   }
 132
 133   return false;
 134 }]>;
 135
 136 def immSExt32 : PatLeaf<(i64 imm), [{
 137   // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
 138   // field.
 139   uint64_t val = N->getZExtValue();
 140   return ((int64_t)val == (int32_t)val);
 141 }]>;
 142
 143 def i64lo32 : PatLeaf<(i64 imm), [{
 144   // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
 145   // bits set.
 146   return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
 147 }], LO32>;
 148
 149 def i64hi32 : PatLeaf<(i64 imm), [{
 150   // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
 151   return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
 152 }], HI32>;
 153
 154 def i32immSExt8  : PatLeaf<(i32 imm), [{
 155   // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
 156   // sign extended field.
 157   return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
 158 }]>;
 159
 160 def i32immSExt16 : PatLeaf<(i32 imm), [{
 161   // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
 162   // sign extended field.
 163   return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
 164 }]>;
 165
 166 def i64immSExt32 : PatLeaf<(i64 imm), [{
 167   // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 168   // sign extended field.
 169   return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
 170 }]>;
 171
 172 def i64immZExt32 : PatLeaf<(i64 imm), [{
 173   // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 174   // zero extended field.
 175   return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
 176 }]>;
 177
 178 // extloads
 179 def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8  node:$ptr))>;
 180 def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
 181 def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8  node:$ptr))>;
 182 def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
 183 def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
 184
 185 def sextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (sextloadi8  node:$ptr))>;
 186 def sextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
 187 def sextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (sextloadi8  node:$ptr))>;
 188 def sextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
 189 def sextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
 190
 191 def zextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (zextloadi8  node:$ptr))>;
 192 def zextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
 193 def zextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (zextloadi8  node:$ptr))>;
 194 def zextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
 195 def zextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
 196
 197 // A couple of more descriptive operand definitions.
 198 // 32-bits but only 8 bits are significant.
 199 def i32i8imm  : Operand<i32>;
 200 // 32-bits but only 16 bits are significant.
 201 def i32i16imm : Operand<i32>;
 202 // 64-bits but only 32 bits are significant.
 203 def i64i32imm : Operand<i64>;
 204 // Branch targets have OtherVT type.
 205 def brtarget : Operand<OtherVT>;
 206
 207 //===----------------------------------------------------------------------===//
 208 // SystemZ Operand Definitions.
 209 //===----------------------------------------------------------------------===//
 210
 211 // Address operands
 212
 213 // riaddr := reg + imm
 214 def riaddr32 : Operand<i32>,
 215                ComplexPattern<i32, 2, "SelectAddrRI", []> {
 216   let PrintMethod = "printRIAddrOperand";
 217   let MIOperandInfo = (ops ADDR32:$base, i32imm:$disp);
 218 }
 219
 220 def riaddr : Operand<i64>,
 221              ComplexPattern<i64, 2, "SelectAddrRI", []> {
 222   let PrintMethod = "printRIAddrOperand";
 223   let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp);
 224 }
 225
 226 //===----------------------------------------------------------------------===//
 227
 228 // rriaddr := reg + reg + imm
 229 def rriaddr : Operand<i64>,
 230               ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
 231   let PrintMethod = "printRRIAddrOperand";
 232   let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index);
 233 }
 234 def laaddr : Operand<i64>,
 235              ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> {
 236   let PrintMethod = "printRRIAddrOperand";
 237   let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index);
 238 }
 239
 240 //===----------------------------------------------------------------------===//
 241 // Instruction list..
 242
 243 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
 244                               "#ADJCALLSTACKDOWN",
 245                               [(SystemZcallseq_start timm:$amt)]>;
 246 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
 247                               "#ADJCALLSTACKUP",
 248                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
 249
 250 let usesCustomDAGSchedInserter = 1 in {
 251   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
 252                         "# Select32 PSEUDO",
 253                         [(set GR32:$dst,
 254                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
 255   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
 256                         "# Select64 PSEUDO",
 257                         [(set GR64:$dst,
 258                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
 259 }
 260
 261
 262 //===----------------------------------------------------------------------===//
 263 //  Control Flow Instructions...
 264 //
 265
 266 // FIXME: Provide proper encoding!
 267 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
 268   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
 269 }
 270
 271 let isBranch = 1, isTerminator = 1 in {
 272   let Uses = [PSW] in {
 273     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 274                      "je\t$dst",
 275                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 276     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 277                      "jne\t$dst",
 278                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 279     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 280                      "jh\t$dst",
 281                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 282     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 283                      "jl\t$dst",
 284                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 285     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 286                      "jhe\t$dst",
 287                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 288     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 289                      "jle\t$dst",
 290                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 291
 292   } // Uses = [PSW]
 293 } // isBranch = 1
 294
 295 //===----------------------------------------------------------------------===//
 296 //  Call Instructions...
 297 //
 298
 299 let isCall = 1 in
 300   // All calls clobber the non-callee saved registers (except R14 which we
 301   // handle separately). Uses for argument registers are added manually.
 302   let Defs = [R0D, R1D, R3D, R4D, R5D] in {
 303     def CALLi     : Pseudo<(outs), (ins i64imm:$dst, variable_ops),
 304                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 305     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 306                            "brasl\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 307   }
 308
 309 //===----------------------------------------------------------------------===//
 310 //  Miscellaneous Instructions.
 311 //
 312
 313 let isReMaterializable = 1 in
 314 // FIXME: Provide imm12 variant
 315 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 316                     "lay\t{$dst, $src}",
 317                     [(set GR64:$dst, laaddr:$src)]>;
 318
 319 let neverHasSideEffects = 1 in
 320 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 321
 322 //===----------------------------------------------------------------------===//
 323 // Move Instructions
 324
 325 // FIXME: Provide proper encoding!
 326 let neverHasSideEffects = 1 in {
 327 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 328                      "lr\t{$dst, $src}",
 329                      []>;
 330 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 331                      "lgr\t{$dst, $src}",
 332                      []>;
 333 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 334                      "# MOV128 PSEUDO!"
 335                      "lgr\t{$dst:subreg_odd, $src:subreg_odd}\n"
 336                      "lgr\t{$dst:subreg_even, $src:subreg_even}",
 337                      []>;
 338 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 339                      "# MOV64P PSEUDO!"
 340                      "lr\t{$dst:subreg_odd, $src:subreg_odd}\n"
 341                      "lr\t{$dst:subreg_even, $src:subreg_even}",
 342                      []>;
 343 }
 344
 345 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 346                          "lgfr\t{$dst, $src}",
 347                          [(set GR64:$dst, (sext GR32:$src))]>;
 348 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 349                          "llgfr\t{$dst, $src}",
 350                          [(set GR64:$dst, (zext GR32:$src))]>;
 351
 352 // FIXME: Provide proper encoding!
 353 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 354 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins i32imm:$src),
 355                        "lhi\t{$dst, $src}",
 356                        [(set GR32:$dst, immSExt16:$src)]>;
 357 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 358                        "lghi\t{$dst, $src}",
 359                        [(set GR64:$dst, immSExt16:$src)]>;
 360
 361 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 362                          "llill\t{$dst, $src}",
 363                          [(set GR64:$dst, i64ll16:$src)]>;
 364 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 365                          "llilh\t{$dst, $src}",
 366                          [(set GR64:$dst, i64lh16:$src)]>;
 367 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 368                          "llihl\t{$dst, $src}",
 369                          [(set GR64:$dst, i64hl16:$src)]>;
 370 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 371                          "llihh\t{$dst, $src}",
 372                          [(set GR64:$dst, i64hh16:$src)]>;
 373 // FIXME: these 3 instructions seem to require extimm facility
 374 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 375                        "lgfi\t{$dst, $src}",
 376                        [(set GR64:$dst, immSExt32:$src)]>;
 377 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 378                          "llilf\t{$dst, $src}",
 379                          [(set GR64:$dst, i64lo32:$src)]>;
 380 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 381                          "llihf\t{$dst, $src}",
 382                          [(set GR64:$dst, i64hi32:$src)]>;
 383 }
 384
 385 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 386 def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 387                      "lg\t{$dst, $src}",
 388                      [(set GR64:$dst, (load rriaddr:$src))]>;
 389
 390 }
 391
 392 def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 393                      "stg\t{$src, $dst}",
 394                      [(store GR64:$src, rriaddr:$dst)]>;
 395
 396 // FIXME: displacements here are really 12 bit, not 20!
 397 def MOV8mi    : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 398                        "mvi\t{$dst, $src}",
 399                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 400 def MOV16mi   : Pseudo<(outs), (ins riaddr:$dst, i32i16imm:$src),
 401                        "mvhhi\t{$dst, $src}",
 402                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>;
 403 def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, i32imm:$src),
 404                        "mvhi\t{$dst, $src}",
 405                        [(store (i32 immSExt16:$src), riaddr:$dst)]>;
 406 def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, i64imm:$src),
 407                        "mvghi\t{$dst, $src}",
 408                        [(store (i64 immSExt16:$src), riaddr:$dst)]>;
 409
 410 // extloads
 411 def MOVSX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 412                          "lb\t{$dst, $src}",
 413                          [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 414 def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 415                          "lhy\t{$dst, $src}",
 416                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 417 def MOVSX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 418                          "lgb\t{$dst, $src}",
 419                          [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 420 def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 421                          "lgh\t{$dst, $src}",
 422                          [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 423 def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 424                          "lgf\t{$dst, $src}",
 425                          [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 426
 427 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 428                          "llc\t{$dst, $src}",
 429                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 430 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 431                          "llh\t{$dst, $src}",
 432                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 433 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 434                          "llgc\t{$dst, $src}",
 435                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 436 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 437                          "llgh\t{$dst, $src}",
 438                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 439 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 440                          "llgf\t{$dst, $src}",
 441                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 442
 443 // truncstores
 444 // FIXME: Implement 12-bit displacement stuff someday
 445 def MOV32m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 446                        "stcy\t{$src, $dst}",
 447                        [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 448
 449 def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 450                        "sthy\t{$src, $dst}",
 451                        [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 452
 453 def MOV64m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 454                        "stcy\t{$src, $dst}",
 455                        [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 456
 457 def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 458                        "sthy\t{$src, $dst}",
 459                        [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 460
 461 def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 462                        "sty\t{$src, $dst}",
 463                        [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 464
 465 // multiple regs moves
 466 // FIXME: should we use multiple arg nodes?
 467 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 468                        "stmy\t{$from, $to, $dst}",
 469                        []>;
 470 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 471                        "stmg\t{$from, $to, $dst}",
 472                        []>;
 473 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 474                        "lmy\t{$from, $to, $dst}",
 475                        []>;
 476 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 477                        "lmg\t{$from, $to, $dst}",
 478                        []>;
 479
 480
 481 //===----------------------------------------------------------------------===//
 482 // Arithmetic Instructions
 483
 484 let isTwoAddress = 1 in {
 485
 486 let Defs = [PSW] in {
 487
 488 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 489 // FIXME: Provide proper encoding!
 490 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 491                      "ar\t{$dst, $src2}",
 492                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 493                       (implicit PSW)]>;
 494 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 495                      "agr\t{$dst, $src2}",
 496                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 497                       (implicit PSW)]>;
 498 }
 499
 500 // FIXME: Provide proper encoding!
 501 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 502                        "ahi\t{$dst, $src2}",
 503                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 504                         (implicit PSW)]>;
 505 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 506                        "afi\t{$dst, $src2}",
 507                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 508                         (implicit PSW)]>;
 509 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 510                        "aghi\t{$dst, $src2}",
 511                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 512                         (implicit PSW)]>;
 513 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 514                        "agfi\t{$dst, $src2}",
 515                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 516                         (implicit PSW)]>;
 517
 518 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 519 // FIXME: Provide proper encoding!
 520 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 521                      "nr\t{$dst, $src2}",
 522                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 523 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 524                      "ngr\t{$dst, $src2}",
 525                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 526 }
 527
 528 // FIXME: Provide proper encoding!
 529 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 530                          "nill\t{$dst, $src2}",
 531                          [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>;
 532 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 533                          "nilh\t{$dst, $src2}",
 534                          [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>;
 535 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 536                          "nihl\t{$dst, $src2}",
 537                          [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>;
 538 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 539                          "nihh\t{$dst, $src2}",
 540                          [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>;
 541 // FIXME: these 2 instructions seem to require extimm facility
 542 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 543                          "nilf\t{$dst, $src2}",
 544                          [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>;
 545 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 546                          "nihf\t{$dst, $src2}",
 547                          [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>;
 548
 549 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 550 // FIXME: Provide proper encoding!
 551 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 552                     "or\t{$dst, $src2}",
 553                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 554 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 555                     "ogr\t{$dst, $src2}",
 556                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 557 }
 558
 559 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
 560                       "oill\t{$dst, $src2}",
 561                       [(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>;
 562 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
 563                       "oilh\t{$dst, $src2}",
 564                       [(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>;
 565 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 566                     "oilf\t{$dst, $src2}",
 567                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 568
 569 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 570                         "oill\t{$dst, $src2}",
 571                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 572 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 573                         "oilh\t{$dst, $src2}",
 574                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 575 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 576                         "oihl\t{$dst, $src2}",
 577                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 578 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 579                         "oihh\t{$dst, $src2}",
 580                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 581 // FIXME: these 2 instructions seem to require extimm facility
 582 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 583                         "oilf\t{$dst, $src2}",
 584                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 585 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 586                         "oihf\t{$dst, $src2}",
 587                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 588
 589 // FIXME: Provide proper encoding!
 590 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 591                      "sr\t{$dst, $src2}",
 592                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 593 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 594                      "sgr\t{$dst, $src2}",
 595                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 596
 597
 598 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 599 // FIXME: Provide proper encoding!
 600 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 601                      "xr\t{$dst, $src2}",
 602                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 603 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 604                      "xgr\t{$dst, $src2}",
 605                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 606 }
 607
 608 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 609                      "xilf\t{$dst, $src2}",
 610                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 611
 612 // FIXME: these 2 instructions seem to require extimm facility
 613 def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 614                          "xilf\t{$dst, $src2}",
 615                          [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>;
 616 def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 617                          "xihf\t{$dst, $src2}",
 618                          [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>;
 619
 620 } // Defs = [PSW]
 621
 622 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 623 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 624                      "msr\t{$dst, $src2}",
 625                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 626 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 627                      "msgr\t{$dst, $src2}",
 628                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 629
 630 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 631                         "mr\t{$dst, $src2}",
 632                         []>;
 633 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 634                          "mlr\t{$dst, $src2}",
 635                          []>;
 636 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 637                         "mlgr\t{$dst, $src2}",
 638                         []>;
 639 }
 640
 641
 642 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32i16imm:$src2),
 643                          "mhi\t{$dst, $src2}",
 644                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 645 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 646                          "msfi\t{$dst, $src2}",
 647                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
 648 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 649                          "mghi\t{$dst, $src2}",
 650                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 651 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
 652                          "msgfi\t{$dst, $src2}",
 653                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
 654
 655 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 656                      "msy\t{$dst, $src2}",
 657                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 658 def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 659                      "msgy\t{$dst, $src2}",
 660                      [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 661
 662 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 663                          "msgfr\t{$dst, $src2}",
 664                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 665
 666 def SDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 667                            "dr\t{$dst, $src2}",
 668                            []>;
 669
 670 def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 671                            "dsgr\t{$dst, $src2}",
 672                            []>;
 673
 674 def UDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 675                            "dlr\t{$dst, $src2}",
 676                            []>;
 677
 678 def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 679                            "dlgr\t{$dst, $src2}",
 680                            []>;
 681
 682 } // isTwoAddress = 1
 683
 684 //===----------------------------------------------------------------------===//
 685 // Shifts
 686
 687 let isTwoAddress = 1 in
 688 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 689                       "srl\t{$src, $amt}",
 690                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 691 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 692                       "srlg\t{$dst, $src, $amt}",
 693                       [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 694 def SRLA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 695                       "srlg\t{$dst, $src, $amt}",
 696                       [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
 697
 698 let isTwoAddress = 1 in
 699 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 700                       "sll\t{$src, $amt}",
 701                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 702 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 703                       "sllg\t{$dst, $src, $amt}",
 704                       [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 705 def SHL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 706                       "sllg\t{$dst, $src, $amt}",
 707                       [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
 708
 709
 710 let Defs = [PSW] in {
 711 let isTwoAddress = 1 in
 712 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 713                       "sra\t{$src, $amt}",
 714                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 715                        (implicit PSW)]>;
 716 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 717                       "srag\t{$dst, $src, $amt}",
 718                       [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
 719                        (implicit PSW)]>;
 720 def SRA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 721                       "srag\t{$dst, $src, $amt}",
 722                       [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
 723                        (implicit PSW)]>;
 724 } // Defs = [PSW]
 725
 726 //===----------------------------------------------------------------------===//
 727 // Test instructions (like AND but do not produce any result
 728
 729 // Integer comparisons
 730 let Defs = [PSW] in {
 731 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 732                      "cr\t$src1, $src2",
 733                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 734 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 735                      "cgr\t$src1, $src2",
 736                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 737
 738 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 739                        "cfi\t$src1, $src2",
 740                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 741 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 742                        "cgfi\t$src1, $src2",
 743                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 744                         (implicit PSW)]>;
 745
 746 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 747                      "cy\t$src1, $src2",
 748                      [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 749                       (implicit PSW)]>;
 750 def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 751                      "cg\t$src1, $src2",
 752                      [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 753                       (implicit PSW)]>;
 754
 755 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 756                       "clr\t$src1, $src2",
 757                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 758 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 759                       "clgr\t$src1, $src2",
 760                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 761
 762 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 763                         "clfi\t$src1, $src2",
 764                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 765 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 766                         "clgfi\t$src1, $src2",
 767                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 768                          (implicit PSW)]>;
 769
 770 def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 771                       "cly\t$src1, $src2",
 772                       [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 773                        (implicit PSW)]>;
 774 def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 775                       "clg\t$src1, $src2",
 776                       [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 777                        (implicit PSW)]>;
 778
 779 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 780                           "cgfr\t$src1, $src2",
 781                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 782                            (implicit PSW)]>;
 783 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 784                           "clgfr\t$src1, $src2",
 785                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 786                            (implicit PSW)]>;
 787
 788 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 789                            "cgf\t$src1, $src2",
 790                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 791                             (implicit PSW)]>;
 792 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 793                            "clgf\t$src1, $src2",
 794                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 795                             (implicit PSW)]>;
 796
 797 // FIXME: Add other crazy ucmp forms
 798
 799 } // Defs = [PSW]
 800
 801 //===----------------------------------------------------------------------===//
 802 // Non-Instruction Patterns.
 803 //===----------------------------------------------------------------------===//
 804
 805 // anyext
 806 def : Pat<(i64 (anyext GR32:$src)),
 807           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 808
 809 //===----------------------------------------------------------------------===//
 810 // Peepholes.
 811 //===----------------------------------------------------------------------===//
 812
 813 // FIXME: use add/sub tricks with 32678/-32768
 814
 815 // trunc patterns
 816 def : Pat<(i32 (trunc GR64:$src)),
 817           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 818
 819 // sext_inreg patterns
 820 def : Pat<(sext_inreg GR64:$src, i32),
 821           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 822
 823 // extload patterns
 824 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 825 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 826 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 827 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 828 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 829
 830 // calls
 831 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)),
 832           (CALLi tglobaladdr:$dst)>;
 833 def : Pat<(SystemZcall (i64 texternalsym:$dst)),
 834           (CALLi texternalsym:$dst)>;
 835
 836 // muls
 837 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 838           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 839                                                    GR32:$src1, subreg_odd),
 840                                     GR32:$src2),
 841                           subreg_even)>;
 842
 843 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 844           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 845                                                     GR32:$src1, subreg_odd),
 846                                      GR32:$src2),
 847                           subreg_even)>;
 848 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 849           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 850                                                      GR64:$src1, subreg_odd),
 851                                       GR64:$src2),
 852                           subreg_even)>;
 853
 854 // divs
 855 // FIXME: Add memory versions
 856 def : Pat<(sdiv GR32:$src1, GR32:$src2),
 857           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 858                                                        GR32:$src1, subreg_odd),
 859                                          GR32:$src2),
 860                           subreg_odd)>;
 861 def : Pat<(sdiv GR64:$src1, GR64:$src2),
 862           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 863                                                         GR64:$src1, subreg_odd),
 864                                          GR64:$src2),
 865                           subreg_odd)>;
 866 def : Pat<(udiv GR32:$src1, GR32:$src2),
 867           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 868                                                        GR32:$src1, subreg_odd),
 869                                          GR32:$src2),
 870                           subreg_odd)>;
 871 def : Pat<(udiv GR64:$src1, GR64:$src2),
 872           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 873                                                         GR64:$src1, subreg_odd),
 874                                          GR64:$src2),
 875                           subreg_odd)>;
 876
 877 // rems
 878 // FIXME: Add memory versions
 879 def : Pat<(srem GR32:$src1, GR32:$src2),
 880           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 881                                                        GR32:$src1, subreg_odd),
 882                                          GR32:$src2),
 883                           subreg_even)>;
 884 def : Pat<(srem GR64:$src1, GR64:$src2),
 885           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 886                                                         GR64:$src1, subreg_odd),
 887                                          GR64:$src2),
 888                           subreg_even)>;
 889 def : Pat<(urem GR32:$src1, GR32:$src2),
 890           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 891                                                        GR32:$src1, subreg_odd),
 892                                          GR32:$src2),
 893                           subreg_even)>;
 894 def : Pat<(urem GR64:$src1, GR64:$src2),
 895           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 896                                                         GR64:$src1, subreg_odd),
 897                                          GR64:$src2),
 898                           subreg_even)>;