1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let neverHasSideEffects = 1 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction (br %r14).
36 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37 def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
39 // Unconditional branches. R1 is the condition-code mask (all 1s).
40 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
41 let isIndirectBranch = 1 in
42 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43 "br\t$R2", [(brind ADDR64:$R2)]>;
45 // An assembler extended mnemonic for BRC.
46 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
49 // An assembler extended mnemonic for BRCL. (The extension is "G"
50 // rather than "L" because "JL" is "Jump if Less".)
51 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
54 // Conditional branches. It's easier for LLVM to handle these branches
55 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
56 // the first operand. It seems friendlier to use mnemonic forms like
57 // JE and JLH when writing out the assembly though.
58 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
59 let isCodeGenOnly = 1, CCMaskFirst = 1 in {
60 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
61 brtarget16:$I2), "j$R1\t$I2",
62 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
63 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
64 brtarget32:$I2), "jg$R1\t$I2", []>;
66 def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
68 def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
69 "brcl\t$R1, $I2", []>;
72 // Fused compare-and-branch instructions. As for normal branches,
73 // we handle these instructions internally in their raw CRJ-like form,
74 // but use assembly macros like CRJE when writing them out.
76 // These instructions do not use or clobber the condition codes.
77 // We nevertheless pretend that they clobber CC, so that we can lower
78 // them to separate comparisons and BRCLs if the branch ends up being
80 multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
81 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
82 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
84 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
85 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
87 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
88 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
90 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
91 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
93 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
94 def LRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
96 "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
97 def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
99 "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
100 def LIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
102 "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
103 def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
105 "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
108 let isCodeGenOnly = 1 in
109 defm C : CompareBranches<cond4, "$M3", "">;
110 defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
112 // Define AsmParser mnemonics for each general condition-code mask
113 // (integer or floating-point)
114 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
116 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
117 "j"##name##"\t$I2", []>;
118 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
119 "jg"##name##"\t$I2", []>;
121 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
122 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
123 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
124 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
125 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
126 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
128 defm AsmO : CondExtendedMnemonic<1, "o">;
129 defm AsmH : CondExtendedMnemonic<2, "h">;
130 defm AsmNLE : CondExtendedMnemonic<3, "nle">;
131 defm AsmL : CondExtendedMnemonic<4, "l">;
132 defm AsmNHE : CondExtendedMnemonic<5, "nhe">;
133 defm AsmLH : CondExtendedMnemonic<6, "lh">;
134 defm AsmNE : CondExtendedMnemonic<7, "ne">;
135 defm AsmE : CondExtendedMnemonic<8, "e">;
136 defm AsmNLH : CondExtendedMnemonic<9, "nlh">;
137 defm AsmHE : CondExtendedMnemonic<10, "he">;
138 defm AsmNL : CondExtendedMnemonic<11, "nl">;
139 defm AsmLE : CondExtendedMnemonic<12, "le">;
140 defm AsmNH : CondExtendedMnemonic<13, "nh">;
141 defm AsmNO : CondExtendedMnemonic<14, "no">;
143 // Define AsmParser mnemonics for each integer condition-code mask.
144 // This is like the list above, except that condition 3 is not possible
145 // and that the low bit of the mask is therefore always 0. This means
146 // that each condition has two names. Conditions "o" and "no" are not used.
148 // We don't make one of the two names an alias of the other because
149 // we need the custom parsing routines to select the correct register class.
150 multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
152 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
154 "crj"##name##"\t$R1, $R2, $RI4", []>;
155 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
157 "cgrj"##name##"\t$R1, $R2, $RI4", []>;
158 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
160 "cij"##name##"\t$R1, $I2, $RI4", []>;
161 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
163 "cgij"##name##"\t$R1, $I2, $RI4", []>;
164 def CLR : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
166 "clrj"##name##"\t$R1, $R2, $RI4", []>;
167 def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
169 "clgrj"##name##"\t$R1, $R2, $RI4", []>;
170 def CLI : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
172 "clij"##name##"\t$R1, $I2, $RI4", []>;
173 def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
175 "clgij"##name##"\t$R1, $I2, $RI4", []>;
178 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
179 : IntCondExtendedMnemonicA<ccmask, name1> {
180 let isAsmParserOnly = 1 in
181 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
183 defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">;
184 defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">;
185 defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">;
186 defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">;
187 defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">;
188 defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">;
190 // Decrement a register and branch if it is nonzero. These don't clobber CC,
191 // but we might need to split long branches into sequences that do.
193 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>;
194 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
197 //===----------------------------------------------------------------------===//
198 // Select instructions
199 //===----------------------------------------------------------------------===//
201 def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
202 def Select32 : SelectWrapper<GR32>;
203 def Select64 : SelectWrapper<GR64>;
205 defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8,
206 nonvolatile_anyextloadi8, bdxaddr20only>;
207 defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,
208 nonvolatile_anyextloadi16, bdxaddr20only>;
209 defm CondStore32 : CondStores<GR32, nonvolatile_store,
210 nonvolatile_load, bdxaddr20only>;
212 defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
213 nonvolatile_anyextloadi8, bdxaddr20only>;
214 defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
215 nonvolatile_anyextloadi16, bdxaddr20only>;
216 defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
217 nonvolatile_anyextloadi32, bdxaddr20only>;
218 defm CondStore64 : CondStores<GR64, nonvolatile_store,
219 nonvolatile_load, bdxaddr20only>;
221 //===----------------------------------------------------------------------===//
223 //===----------------------------------------------------------------------===//
225 // The definitions here are for the call-clobbered registers.
226 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
227 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC] in {
228 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
229 [(z_call pcrel32:$I2)]>;
230 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
231 [(z_call ADDR64:$R2)]>;
234 // Sibling calls. Indirect sibling calls must be via R1, since R2 upwards
235 // are argument registers and since branching to R0 is a no-op.
236 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
237 def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
238 [(z_sibcall pcrel32:$I2)]>;
240 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
243 // Define the general form of the call instructions for the asm parser.
244 // These instructions don't hard-code %r14 as the return address register.
245 def BRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
246 "bras\t$R1, $I2", []>;
247 def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
248 "brasl\t$R1, $I2", []>;
249 def BASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
250 "basr\t$R1, $R2", []>;
252 //===----------------------------------------------------------------------===//
254 //===----------------------------------------------------------------------===//
257 let neverHasSideEffects = 1 in {
258 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
259 def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
260 Requires<[FeatureHighWord]>;
261 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>;
262 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
264 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
265 def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>;
266 def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
269 // Move on condition.
270 let isCodeGenOnly = 1, Uses = [CC] in {
271 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
272 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
275 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
276 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
280 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
281 isReMaterializable = 1 in {
282 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
283 // deopending on the choice of register.
284 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
285 Requires<[FeatureHighWord]>;
286 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
287 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
289 // Other 16-bit immediates.
290 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
291 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
292 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
293 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
295 // 32-bit immediates.
296 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
297 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
298 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
302 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
303 // Expands to L, LY or LFH, depending on the choice of register.
304 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
305 Requires<[FeatureHighWord]>;
306 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
307 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
308 Requires<[FeatureHighWord]>;
309 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
311 // These instructions are split after register allocation, so we don't
312 // want a custom inserter.
313 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
314 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
315 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
318 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
319 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>;
320 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
323 let canFoldAsLoad = 1 in {
324 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
325 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
328 // Load on condition.
329 let isCodeGenOnly = 1, Uses = [CC] in {
330 def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>;
331 def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
334 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
335 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
339 let SimpleBDXStore = 1 in {
340 // Expands to ST, STY or STFH, depending on the choice of register.
341 def STMux : StoreRXYPseudo<store, GRX32, 4>,
342 Requires<[FeatureHighWord]>;
343 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
344 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
345 Requires<[FeatureHighWord]>;
346 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
348 // These instructions are split after register allocation, so we don't
349 // want a custom inserter.
350 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
351 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
352 [(store GR128:$src, bdxaddr20only128:$dst)]>;
355 def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
356 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
358 // Store on condition.
359 let isCodeGenOnly = 1, Uses = [CC] in {
360 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
361 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
364 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
365 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
368 // 8-bit immediate stores to 8-bit fields.
369 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
371 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
372 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
373 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
374 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
376 // Memory-to-memory moves.
377 let mayLoad = 1, mayStore = 1 in
378 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
381 let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
382 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
384 //===----------------------------------------------------------------------===//
386 //===----------------------------------------------------------------------===//
388 // Note that putting these before zero extensions mean that we will prefer
389 // them for anyextload*. There's not really much to choose between the two
390 // either way, but signed-extending loads have a short LH and a long LHY,
391 // while zero-extending loads have only the long LLH.
393 //===----------------------------------------------------------------------===//
395 // 32-bit extensions from registers.
396 let neverHasSideEffects = 1 in {
397 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
398 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
401 // 64-bit extensions from registers.
402 let neverHasSideEffects = 1 in {
403 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
404 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
405 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
407 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
408 def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
410 // Match 32-to-64-bit sign extensions in which the source is already
411 // in a 64-bit register.
412 def : Pat<(sext_inreg GR64:$src, i32),
413 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
415 // 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH,
416 // depending on the choice of register.
417 def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
418 Requires<[FeatureHighWord]>;
419 def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
420 def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
421 Requires<[FeatureHighWord]>;
423 // 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,
424 // depending on the choice of register.
425 def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
426 Requires<[FeatureHighWord]>;
427 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
428 def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
429 Requires<[FeatureHighWord]>;
430 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
432 // 64-bit extensions from memory.
433 def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>;
434 def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
435 def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
436 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
437 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
438 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
439 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
441 //===----------------------------------------------------------------------===//
443 //===----------------------------------------------------------------------===//
445 // 32-bit extensions from registers.
446 let neverHasSideEffects = 1 in {
447 // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
448 def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
449 Requires<[FeatureHighWord]>;
450 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
451 // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
452 def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
453 Requires<[FeatureHighWord]>;
454 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
457 // 64-bit extensions from registers.
458 let neverHasSideEffects = 1 in {
459 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
460 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
461 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
464 // Match 32-to-64-bit zero extensions in which the source is already
465 // in a 64-bit register.
466 def : Pat<(and GR64:$src, 0xffffffff),
467 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
469 // 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH,
470 // depending on the choice of register.
471 def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
472 Requires<[FeatureHighWord]>;
473 def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
474 def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GR32, 1>,
475 Requires<[FeatureHighWord]>;
477 // 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH,
478 // depending on the choice of register.
479 def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
480 Requires<[FeatureHighWord]>;
481 def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
482 def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GR32, 2>,
483 Requires<[FeatureHighWord]>;
484 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
486 // 64-bit extensions from memory.
487 def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>;
488 def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
489 def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
490 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
491 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
493 //===----------------------------------------------------------------------===//
495 //===----------------------------------------------------------------------===//
497 // Truncations of 64-bit registers to 32-bit registers.
498 def : Pat<(i32 (trunc GR64:$src)),
499 (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
501 // Truncations of 32-bit registers to 8-bit memory. STCMux expands to
502 // STC, STCY or STCH, depending on the choice of register.
503 def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
504 Requires<[FeatureHighWord]>;
505 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
506 def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
507 Requires<[FeatureHighWord]>;
509 // Truncations of 32-bit registers to 16-bit memory. STHMux expands to
510 // STH, STHY or STHH, depending on the choice of register.
511 def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
512 Requires<[FeatureHighWord]>;
513 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
514 def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
515 Requires<[FeatureHighWord]>;
516 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
518 // Truncations of 64-bit registers to memory.
519 defm : StoreGR64Pair<STC, STCY, truncstorei8>;
520 defm : StoreGR64Pair<STH, STHY, truncstorei16>;
521 def : StoreGR64PC<STHRL, aligned_truncstorei16>;
522 defm : StoreGR64Pair<ST, STY, truncstorei32>;
523 def : StoreGR64PC<STRL, aligned_truncstorei32>;
525 //===----------------------------------------------------------------------===//
526 // Multi-register moves
527 //===----------------------------------------------------------------------===//
529 // Multi-register loads.
530 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
532 // Multi-register stores.
533 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
535 //===----------------------------------------------------------------------===//
537 //===----------------------------------------------------------------------===//
539 // Byte-swapping register moves.
540 let neverHasSideEffects = 1 in {
541 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
542 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
545 // Byte-swapping loads. Unlike normal loads, these instructions are
546 // allowed to access storage more than once.
547 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
548 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
550 // Likewise byte-swapping stores.
551 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
552 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
555 //===----------------------------------------------------------------------===//
556 // Load address instructions
557 //===----------------------------------------------------------------------===//
559 // Load BDX-style addresses.
560 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
562 let DispSize = "12" in
563 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
565 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
566 let DispSize = "20" in
567 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
569 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
572 // Load a PC-relative address. There's no version of this instruction
573 // with a 16-bit offset, so there's no relaxation.
574 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
575 isReMaterializable = 1 in {
576 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
578 [(set GR64:$R1, pcrel32:$I2)]>;
581 //===----------------------------------------------------------------------===//
582 // Absolute and Negation
583 //===----------------------------------------------------------------------===//
586 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
587 def LPR : UnaryRR <"lp", 0x10, z_iabs32, GR32, GR32>;
588 def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs64, GR64, GR64>;
590 let CCValues = 0xE, CompareZeroCCMask = 0xE in
591 def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
593 defm : SXU<z_iabs64, LPGFR>;
596 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
597 def LNR : UnaryRR <"ln", 0x11, z_inegabs32, GR32, GR32>;
598 def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs64, GR64, GR64>;
600 let CCValues = 0xE, CompareZeroCCMask = 0xE in
601 def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
603 defm : SXU<z_inegabs64, LNGFR>;
606 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
607 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
608 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
610 let CCValues = 0xE, CompareZeroCCMask = 0xE in
611 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
613 defm : SXU<ineg, LCGFR>;
615 //===----------------------------------------------------------------------===//
617 //===----------------------------------------------------------------------===//
619 let isCodeGenOnly = 1 in
620 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
621 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
623 defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>;
624 defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
626 defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>;
627 defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
629 // Insertions of a 16-bit immediate, leaving other bits unaffected.
630 // We don't have or_as_insert equivalents of these operations because
631 // OI is available instead.
633 // IIxMux expands to II[LH]x, depending on the choice of register.
634 def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
635 Requires<[FeatureHighWord]>;
636 def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
637 Requires<[FeatureHighWord]>;
638 def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
639 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
640 def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
641 def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
642 def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
643 def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
644 def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
645 def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
647 // ...likewise for 32-bit immediates. For GR32s this is a general
648 // full-width move. (We use IILF rather than something like LLILF
649 // for 32-bit moves because IILF leaves the upper 32 bits of the
651 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
652 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
653 Requires<[FeatureHighWord]>;
654 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
655 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
657 def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
658 def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
660 // An alternative model of inserthf, with the first operand being
661 // a zero-extended value.
662 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
663 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
666 //===----------------------------------------------------------------------===//
668 //===----------------------------------------------------------------------===//
671 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
672 // Addition of a register.
673 let isCommutable = 1 in {
674 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
675 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
677 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
679 // Addition of signed 16-bit immediates.
680 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>;
681 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
683 // Addition of signed 32-bit immediates.
684 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
685 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
687 // Addition of memory.
688 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
689 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>;
690 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
691 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>;
693 // Addition to memory.
694 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
695 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
697 defm : SXB<add, GR64, AGFR>;
699 // Addition producing a carry.
701 // Addition of a register.
702 let isCommutable = 1 in {
703 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
704 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
706 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
708 // Addition of signed 16-bit immediates.
709 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>,
710 Requires<[FeatureDistinctOps]>;
711 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
712 Requires<[FeatureDistinctOps]>;
714 // Addition of unsigned 32-bit immediates.
715 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
716 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
718 // Addition of memory.
719 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
720 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
721 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>;
723 defm : ZXB<addc, GR64, ALGFR>;
725 // Addition producing and using a carry.
726 let Defs = [CC], Uses = [CC] in {
727 // Addition of a register.
728 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>;
729 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
731 // Addition of memory.
732 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>;
733 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
736 //===----------------------------------------------------------------------===//
738 //===----------------------------------------------------------------------===//
740 // Plain substraction. Although immediate forms exist, we use the
741 // add-immediate instruction instead.
742 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
743 // Subtraction of a register.
744 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
745 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
746 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
748 // Subtraction of memory.
749 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
750 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
751 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
752 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>;
754 defm : SXB<sub, GR64, SGFR>;
756 // Subtraction producing a carry.
758 // Subtraction of a register.
759 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
760 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
761 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
763 // Subtraction of unsigned 32-bit immediates. These don't match
764 // subc because we prefer addc for constants.
765 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
766 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
768 // Subtraction of memory.
769 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
770 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
771 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
773 defm : ZXB<subc, GR64, SLGFR>;
775 // Subtraction producing and using a carry.
776 let Defs = [CC], Uses = [CC] in {
777 // Subtraction of a register.
778 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
779 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
781 // Subtraction of memory.
782 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
783 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
786 //===----------------------------------------------------------------------===//
788 //===----------------------------------------------------------------------===//
791 // ANDs of a register.
792 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
793 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
794 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
797 let isConvertibleToThreeAddress = 1 in {
798 // ANDs of a 16-bit immediate, leaving other bits unaffected.
799 // The CC result only reflects the 16-bit field, not the full register.
801 // NIxMux expands to NI[LH]x, depending on the choice of register.
802 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
803 Requires<[FeatureHighWord]>;
804 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
805 Requires<[FeatureHighWord]>;
806 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
807 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
808 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
809 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
810 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
811 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
812 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
813 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
815 // ANDs of a 32-bit immediate, leaving other bits unaffected.
816 // The CC result only reflects the 32-bit field, which means we can
817 // use it as a zero indicator for i32 operations but not otherwise.
818 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
819 // Expands to NILF or NIHF, depending on the choice of register.
820 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
821 Requires<[FeatureHighWord]>;
822 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
823 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
825 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
826 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
830 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
831 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
832 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
836 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
839 let mayLoad = 1, mayStore = 1 in
840 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
842 defm : RMWIByte<and, bdaddr12pair, NI>;
843 defm : RMWIByte<and, bdaddr20pair, NIY>;
845 //===----------------------------------------------------------------------===//
847 //===----------------------------------------------------------------------===//
850 // ORs of a register.
851 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
852 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
853 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
856 // ORs of a 16-bit immediate, leaving other bits unaffected.
857 // The CC result only reflects the 16-bit field, not the full register.
859 // OIxMux expands to OI[LH]x, depending on the choice of register.
860 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,
861 Requires<[FeatureHighWord]>;
862 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,
863 Requires<[FeatureHighWord]>;
864 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
865 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
866 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;
867 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;
868 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
869 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
870 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;
871 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;
873 // ORs of a 32-bit immediate, leaving other bits unaffected.
874 // The CC result only reflects the 32-bit field, which means we can
875 // use it as a zero indicator for i32 operations but not otherwise.
876 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
877 // Expands to OILF or OIHF, depending on the choice of register.
878 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,
879 Requires<[FeatureHighWord]>;
880 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
881 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;
883 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
884 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;
887 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
888 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
889 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
893 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
896 let mayLoad = 1, mayStore = 1 in
897 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
899 defm : RMWIByte<or, bdaddr12pair, OI>;
900 defm : RMWIByte<or, bdaddr20pair, OIY>;
902 //===----------------------------------------------------------------------===//
904 //===----------------------------------------------------------------------===//
907 // XORs of a register.
908 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
909 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
910 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
913 // XORs of a 32-bit immediate, leaving other bits unaffected.
914 // The CC result only reflects the 32-bit field, which means we can
915 // use it as a zero indicator for i32 operations but not otherwise.
916 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
917 // Expands to XILF or XIHF, depending on the choice of register.
918 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
919 Requires<[FeatureHighWord]>;
920 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
921 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
923 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
924 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
927 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
928 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
929 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
933 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
936 let mayLoad = 1, mayStore = 1 in
937 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
939 defm : RMWIByte<xor, bdaddr12pair, XI>;
940 defm : RMWIByte<xor, bdaddr20pair, XIY>;
942 //===----------------------------------------------------------------------===//
944 //===----------------------------------------------------------------------===//
946 // Multiplication of a register.
947 let isCommutable = 1 in {
948 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>;
949 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
951 def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
952 defm : SXB<mul, GR64, MSGFR>;
954 // Multiplication of a signed 16-bit immediate.
955 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
956 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
958 // Multiplication of a signed 32-bit immediate.
959 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
960 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
962 // Multiplication of memory.
963 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
964 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
965 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
966 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
968 // Multiplication of a register, producing two results.
969 def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
971 // Multiplication of memory, producing two results.
972 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
974 //===----------------------------------------------------------------------===//
975 // Division and remainder
976 //===----------------------------------------------------------------------===//
978 // Division and remainder, from registers.
979 def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
980 def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>;
981 def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
982 def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
984 // Division and remainder, from memory.
985 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
986 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>;
987 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>;
988 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
990 //===----------------------------------------------------------------------===//
992 //===----------------------------------------------------------------------===//
995 let neverHasSideEffects = 1 in {
996 defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
997 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
1000 // Logical shift right.
1001 let neverHasSideEffects = 1 in {
1002 defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
1003 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
1006 // Arithmetic shift right.
1007 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
1008 defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
1009 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
1013 let neverHasSideEffects = 1 in {
1014 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>;
1015 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
1018 // Rotate second operand left and inserted selected bits into first operand.
1019 // These can act like 32-bit operands provided that the constant start and
1020 // end bits (operands 2 and 3) are in the range [32, 64).
1021 let Defs = [CC] in {
1022 let isCodeGenOnly = 1 in
1023 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
1024 let CCValues = 0xE, CompareZeroCCMask = 0xE in
1025 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
1028 // Forms of RISBG that only affect one word of the destination register.
1029 // They do not set CC.
1030 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>, Requires<[FeatureHighWord]>;
1031 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>, Requires<[FeatureHighWord]>;
1032 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>, Requires<[FeatureHighWord]>;
1033 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>, Requires<[FeatureHighWord]>;
1034 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>, Requires<[FeatureHighWord]>;
1035 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>,
1036 Requires<[FeatureHighWord]>;
1037 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>,
1038 Requires<[FeatureHighWord]>;
1040 // Rotate second operand left and perform a logical operation with selected
1041 // bits of the first operand. The CC result only describes the selected bits,
1042 // so isn't useful for a full comparison against zero.
1043 let Defs = [CC] in {
1044 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
1045 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
1046 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
1049 //===----------------------------------------------------------------------===//
1051 //===----------------------------------------------------------------------===//
1053 // Signed comparisons. We put these before the unsigned comparisons because
1054 // some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1055 // of the unsigned forms do.
1056 let Defs = [CC], CCValues = 0xE in {
1057 // Comparison with a register.
1058 def CR : CompareRR <"c", 0x19, z_scmp, GR32, GR32>;
1059 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
1060 def CGR : CompareRRE<"cg", 0xB920, z_scmp, GR64, GR64>;
1062 // Comparison with a signed 16-bit immediate.
1063 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>;
1064 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1066 // Comparison with a signed 32-bit immediate.
1067 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>;
1068 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1070 // Comparison with memory.
1071 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1072 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>;
1073 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1074 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1075 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>;
1076 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>;
1077 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>;
1078 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1079 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1080 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>;
1082 // Comparison between memory and a signed 16-bit immediate.
1083 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1084 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>;
1085 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1087 defm : SXB<z_scmp, GR64, CGFR>;
1089 // Unsigned comparisons.
1090 let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1091 // Comparison with a register.
1092 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>;
1093 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1094 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>;
1096 // Comparison with a signed 32-bit immediate.
1097 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
1098 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1100 // Comparison with memory.
1101 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1102 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1103 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>;
1104 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
1105 aligned_azextloadi16>;
1106 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
1108 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1109 aligned_azextloadi16>;
1110 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1111 aligned_azextloadi32>;
1112 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
1115 // Comparison between memory and an unsigned 8-bit immediate.
1116 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1118 // Comparison between memory and an unsigned 16-bit immediate.
1119 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1120 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1121 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1123 defm : ZXB<z_ucmp, GR64, CLGFR>;
1125 // Memory-to-memory comparison.
1126 let mayLoad = 1, Defs = [CC] in
1127 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1129 // String comparison.
1130 let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1131 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1134 let Defs = [CC] in {
1135 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1136 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1138 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>;
1139 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>;
1141 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1143 def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16>;
1144 def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16>;
1146 //===----------------------------------------------------------------------===//
1148 //===----------------------------------------------------------------------===//
1150 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1151 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1153 //===----------------------------------------------------------------------===//
1154 // Atomic operations
1155 //===----------------------------------------------------------------------===//
1157 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
1158 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
1159 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
1161 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1162 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1163 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
1164 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1165 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1166 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
1167 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1168 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1170 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1171 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1172 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1174 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1175 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1176 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
1177 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
1178 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
1179 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1180 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
1181 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
1182 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
1183 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
1184 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
1185 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
1186 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
1188 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1189 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1190 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
1191 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1192 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1193 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1194 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
1195 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1196 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1197 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1198 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1199 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1200 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1202 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1203 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1204 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1205 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1206 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1207 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1208 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1210 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1211 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1213 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1214 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32,
1216 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32,
1218 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1219 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1220 def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1222 def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1224 def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1226 def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1228 def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1230 def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1233 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1234 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
1235 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
1237 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1238 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
1239 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
1241 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1242 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1243 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1245 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1246 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1247 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1249 def ATOMIC_CMP_SWAPW
1250 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1251 ADDR32:$bitshift, ADDR32:$negbitshift,
1254 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1255 ADDR32:$bitshift, ADDR32:$negbitshift,
1256 uimm32:$bitsize))]> {
1260 let usesCustomInserter = 1;
1263 let Defs = [CC] in {
1264 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1265 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1268 //===----------------------------------------------------------------------===//
1269 // Miscellaneous Instructions.
1270 //===----------------------------------------------------------------------===//
1272 // Extract CC into bits 29 and 28 of a register.
1274 def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1276 // Read a 32-bit access register into a GR32. As with all GR32 operations,
1277 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1278 // when a 64-bit address is stored in a pair of access registers.
1279 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1281 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1283 // Find leftmost one, AKA count leading zeros. The instruction actually
1284 // returns a pair of GR64s, the first giving the number of leading zeros
1285 // and the second giving a copy of the source with the leftmost one bit
1286 // cleared. We only use the first result here.
1287 let Defs = [CC] in {
1288 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1290 def : Pat<(ctlz GR64:$src),
1291 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1293 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1294 def : Pat<(i64 (anyext GR32:$src)),
1295 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1297 // Extend GR32s and GR64s to GR128s.
1298 let usesCustomInserter = 1 in {
1299 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1300 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1301 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1304 // Search a block of memory for a character.
1305 let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1306 defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1308 //===----------------------------------------------------------------------===//
1310 //===----------------------------------------------------------------------===//
1312 // Use AL* for GR64 additions of unsigned 32-bit values.
1313 defm : ZXB<add, GR64, ALGFR>;
1314 def : Pat<(add GR64:$src1, imm64zx32:$src2),
1315 (ALGFI GR64:$src1, imm64zx32:$src2)>;
1316 def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1317 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1319 // Use SL* for GR64 subtractions of unsigned 32-bit values.
1320 defm : ZXB<sub, GR64, SLGFR>;
1321 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
1322 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1323 def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1324 (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1326 // Optimize sign-extended 1/0 selects to -1/0 selects. This is important
1327 // for vector legalization.
1328 def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
1331 (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1332 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
1336 (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1338 // Peepholes for turning scalar operations into block operations.
1339 defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1341 defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1343 defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1345 defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1346 OCSequence, XCSequence, 1>;
1347 defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1349 defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1351 defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,