1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let neverHasSideEffects = 1 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction. R1 is the condition-code mask (all 1s)
36 // and R2 is the target address, which is always stored in %r14.
37 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
42 // Unconditional branches. R1 is the condition-code mask (all 1s).
43 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
44 let isIndirectBranch = 1 in
45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
46 "br\t$R2", [(brind ADDR64:$R2)]>;
48 // An assembler extended mnemonic for BRC.
49 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
52 // An assembler extended mnemonic for BRCL. (The extension is "G"
53 // rather than "L" because "JL" is "Jump if Less".)
54 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
57 // Conditional branches. It's easier for LLVM to handle these branches
58 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
59 // the first operand. It seems friendlier to use mnemonic forms like
60 // JE and JLH when writing out the assembly though.
61 multiclass CondBranches<Operand imm, string short, string long> {
62 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
63 def "" : InstRI<0xA74, (outs), (ins imm:$R1, brtarget16:$I2), short, []>;
64 def L : InstRIL<0xC04, (outs), (ins imm:$R1, brtarget32:$I2), long, []>;
67 let isCodeGenOnly = 1 in
68 defm BRC : CondBranches<cond4, "j$R1\t$I2", "jg$R1\t$I2">;
69 defm AsmBRC : CondBranches<uimm8zx4, "brc\t$R1, $I2", "brcl\t$R1, $I2">;
71 def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRC cond4:$cond, bb:$dst)>;
73 // Define AsmParser mnemonics for each condition code.
74 multiclass CondExtendedMnemonic<bits<4> Cond, string name> {
76 def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2),
77 "j"##name##"\t$I2", []>;
78 def L : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
79 "jg"##name##"\t$I2", []>;
82 defm AsmJO : CondExtendedMnemonic<1, "o">;
83 defm AsmJH : CondExtendedMnemonic<2, "h">;
84 defm AsmJNLE : CondExtendedMnemonic<3, "nle">;
85 defm AsmJL : CondExtendedMnemonic<4, "l">;
86 defm AsmJNHE : CondExtendedMnemonic<5, "nhe">;
87 defm AsmJLH : CondExtendedMnemonic<6, "lh">;
88 defm AsmJNE : CondExtendedMnemonic<7, "ne">;
89 defm AsmJE : CondExtendedMnemonic<8, "e">;
90 defm AsmJNLH : CondExtendedMnemonic<9, "nlh">;
91 defm AsmJHE : CondExtendedMnemonic<10, "he">;
92 defm AsmJNL : CondExtendedMnemonic<11, "nl">;
93 defm AsmJLE : CondExtendedMnemonic<12, "le">;
94 defm AsmJNH : CondExtendedMnemonic<13, "nh">;
95 defm AsmJNO : CondExtendedMnemonic<14, "no">;
97 def Select32 : SelectWrapper<GR32>;
98 def Select64 : SelectWrapper<GR64>;
100 //===----------------------------------------------------------------------===//
102 //===----------------------------------------------------------------------===//
104 // The definitions here are for the call-clobbered registers.
105 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
106 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D],
107 R1 = 14, isCodeGenOnly = 1 in {
108 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops),
109 "bras\t%r14, $I2", []>;
110 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops),
111 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>;
112 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops),
113 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
116 // Define the general form of the call instructions for the asm parser.
117 // These instructions don't hard-code %r14 as the return address register.
118 def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
119 "bras\t$R1, $I2", []>;
120 def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
121 "brasl\t$R1, $I2", []>;
122 def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
123 "basr\t$R1, $R2", []>;
125 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
130 let neverHasSideEffects = 1 in {
131 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
132 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
136 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
137 // 16-bit sign-extended immediates.
138 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
139 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
141 // Other 16-bit immediates.
142 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
143 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
144 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
145 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
147 // 32-bit immediates.
148 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
149 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
150 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
154 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
155 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>;
156 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
158 def LG : UnaryRXY<"lg", 0xE304, load, GR64>;
159 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
161 // These instructions are split after register allocation, so we don't
162 // want a custom inserter.
163 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
164 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
165 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
170 let SimpleBDXStore = 1 in {
171 let isCodeGenOnly = 1 in {
172 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32>;
173 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
176 def STG : StoreRXY<"stg", 0xE324, store, GR64>;
177 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
179 // These instructions are split after register allocation, so we don't
180 // want a custom inserter.
181 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
182 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
183 [(store GR128:$src, bdxaddr20only128:$dst)]>;
187 // 8-bit immediate stores to 8-bit fields.
188 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
190 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
191 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
192 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
193 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
195 //===----------------------------------------------------------------------===//
197 //===----------------------------------------------------------------------===//
199 // 32-bit extensions from registers.
200 let neverHasSideEffects = 1 in {
201 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>;
202 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
205 // 64-bit extensions from registers.
206 let neverHasSideEffects = 1 in {
207 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>;
208 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
209 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
212 // Match 32-to-64-bit sign extensions in which the source is already
213 // in a 64-bit register.
214 def : Pat<(sext_inreg GR64:$src, i32),
215 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
217 // 32-bit extensions from memory.
218 def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32>;
219 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32>;
220 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>;
222 // 64-bit extensions from memory.
223 def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64>;
224 def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64>;
225 def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64>;
226 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>;
227 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>;
229 // If the sign of a load-extend operation doesn't matter, use the signed ones.
230 // There's not really much to choose between the sign and zero extensions,
231 // but LH is more compact than LLH for small offsets.
232 def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>;
233 def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>;
234 def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>;
236 def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>;
237 def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>;
238 def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>;
240 //===----------------------------------------------------------------------===//
242 //===----------------------------------------------------------------------===//
244 // 32-bit extensions from registers.
245 let neverHasSideEffects = 1 in {
246 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;
247 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
250 // 64-bit extensions from registers.
251 let neverHasSideEffects = 1 in {
252 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>;
253 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
254 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
257 // Match 32-to-64-bit zero extensions in which the source is already
258 // in a 64-bit register.
259 def : Pat<(and GR64:$src, 0xffffffff),
260 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
262 // 32-bit extensions from memory.
263 def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32>;
264 def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32>;
265 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>;
267 // 64-bit extensions from memory.
268 def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64>;
269 def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64>;
270 def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64>;
271 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>;
272 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>;
274 //===----------------------------------------------------------------------===//
276 //===----------------------------------------------------------------------===//
278 // Truncations of 64-bit registers to 32-bit registers.
279 def : Pat<(i32 (trunc GR64:$src)),
280 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
282 // Truncations of 32-bit registers to memory.
283 let isCodeGenOnly = 1 in {
284 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32>;
285 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32>;
286 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
289 // Truncations of 64-bit registers to memory.
290 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64>;
291 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64>;
292 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
293 defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64>;
294 def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;
296 //===----------------------------------------------------------------------===//
297 // Multi-register moves
298 //===----------------------------------------------------------------------===//
300 // Multi-register loads.
301 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
303 // Multi-register stores.
304 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
306 //===----------------------------------------------------------------------===//
308 //===----------------------------------------------------------------------===//
310 // Byte-swapping register moves.
311 let neverHasSideEffects = 1 in {
312 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>;
313 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
316 // Byte-swapping loads.
317 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap>, GR32>;
318 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap>, GR64>;
320 // Byte-swapping stores.
321 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap>, GR32>;
322 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap>, GR64>;
324 //===----------------------------------------------------------------------===//
325 // Load address instructions
326 //===----------------------------------------------------------------------===//
328 // Load BDX-style addresses.
329 let neverHasSideEffects = 1, Function = "la" in {
330 let PairType = "12" in
331 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
333 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
334 let PairType = "20" in
335 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
337 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
340 // Load a PC-relative address. There's no version of this instruction
341 // with a 16-bit offset, so there's no relaxation.
342 let neverHasSideEffects = 1 in {
343 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
345 [(set GR64:$R1, pcrel32:$I2)]>;
348 //===----------------------------------------------------------------------===//
350 //===----------------------------------------------------------------------===//
353 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;
354 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;
355 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
357 defm : SXU<ineg, LCGFR>;
359 //===----------------------------------------------------------------------===//
361 //===----------------------------------------------------------------------===//
363 let isCodeGenOnly = 1 in
364 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8>;
365 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8>;
367 defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>;
368 defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>;
370 defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>;
371 defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>;
373 // Insertions of a 16-bit immediate, leaving other bits unaffected.
374 // We don't have or_as_insert equivalents of these operations because
375 // OI is available instead.
376 let isCodeGenOnly = 1 in {
377 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
378 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
380 def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>;
381 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>;
382 def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
383 def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
385 // ...likewise for 32-bit immediates. For GR32s this is a general
386 // full-width move. (We use IILF rather than something like LLILF
387 // for 32-bit moves because IILF leaves the upper 32 bits of the
389 let isCodeGenOnly = 1 in {
390 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
392 def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
393 def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
395 // An alternative model of inserthf, with the first operand being
396 // a zero-extended value.
397 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
398 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit),
401 //===----------------------------------------------------------------------===//
403 //===----------------------------------------------------------------------===//
407 // Addition of a register.
408 let isCommutable = 1 in {
409 def AR : BinaryRR <"ar", 0x1A, add, GR32, GR32>;
410 def AGR : BinaryRRE<"agr", 0xB908, add, GR64, GR64>;
412 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;
414 // Addition of signed 16-bit immediates.
415 def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>;
416 def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>;
418 // Addition of signed 32-bit immediates.
419 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
420 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
422 // Addition of memory.
423 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16>;
424 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load>;
425 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32>;
426 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load>;
428 // Addition to memory.
429 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
430 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
432 defm : SXB<add, GR64, AGFR>;
434 // Addition producing a carry.
436 // Addition of a register.
437 let isCommutable = 1 in {
438 def ALR : BinaryRR <"alr", 0x1E, addc, GR32, GR32>;
439 def ALGR : BinaryRRE<"algr", 0xB90A, addc, GR64, GR64>;
441 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>;
443 // Addition of unsigned 32-bit immediates.
444 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
445 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
447 // Addition of memory.
448 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load>;
449 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32>;
450 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load>;
452 defm : ZXB<addc, GR64, ALGFR>;
454 // Addition producing and using a carry.
455 let Defs = [CC], Uses = [CC] in {
456 // Addition of a register.
457 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>;
458 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>;
460 // Addition of memory.
461 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load>;
462 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load>;
465 //===----------------------------------------------------------------------===//
467 //===----------------------------------------------------------------------===//
469 // Plain substraction. Although immediate forms exist, we use the
470 // add-immediate instruction instead.
472 // Subtraction of a register.
473 def SR : BinaryRR <"sr", 0x1B, sub, GR32, GR32>;
474 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;
475 def SGR : BinaryRRE<"sgr", 0xB909, sub, GR64, GR64>;
477 // Subtraction of memory.
478 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16>;
479 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load>;
480 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32>;
481 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load>;
483 defm : SXB<sub, GR64, SGFR>;
485 // Subtraction producing a carry.
487 // Subtraction of a register.
488 def SLR : BinaryRR <"slr", 0x1F, subc, GR32, GR32>;
489 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
490 def SLGR : BinaryRRE<"slgr", 0xB90B, subc, GR64, GR64>;
492 // Subtraction of unsigned 32-bit immediates. These don't match
493 // subc because we prefer addc for constants.
494 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
495 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
497 // Subtraction of memory.
498 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load>;
499 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32>;
500 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load>;
502 defm : ZXB<subc, GR64, SLGFR>;
504 // Subtraction producing and using a carry.
505 let Defs = [CC], Uses = [CC] in {
506 // Subtraction of a register.
507 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>;
508 def SLGBR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>;
510 // Subtraction of memory.
511 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load>;
512 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load>;
515 //===----------------------------------------------------------------------===//
517 //===----------------------------------------------------------------------===//
520 // ANDs of a register.
521 let isCommutable = 1 in {
522 def NR : BinaryRR <"nr", 0x14, and, GR32, GR32>;
523 def NGR : BinaryRRE<"ngr", 0xB980, and, GR64, GR64>;
526 // ANDs of a 16-bit immediate, leaving other bits unaffected.
527 let isCodeGenOnly = 1 in {
528 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
529 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
531 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
532 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
533 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
534 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
536 // ANDs of a 32-bit immediate, leaving other bits unaffected.
537 let isCodeGenOnly = 1 in
538 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
539 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
540 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
543 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load>;
544 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load>;
547 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
549 defm : RMWIByte<and, bdaddr12pair, NI>;
550 defm : RMWIByte<and, bdaddr20pair, NIY>;
552 //===----------------------------------------------------------------------===//
554 //===----------------------------------------------------------------------===//
557 // ORs of a register.
558 let isCommutable = 1 in {
559 def OR : BinaryRR <"or", 0x16, or, GR32, GR32>;
560 def OGR : BinaryRRE<"ogr", 0xB981, or, GR64, GR64>;
563 // ORs of a 16-bit immediate, leaving other bits unaffected.
564 let isCodeGenOnly = 1 in {
565 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
566 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
568 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>;
569 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>;
570 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
571 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
573 // ORs of a 32-bit immediate, leaving other bits unaffected.
574 let isCodeGenOnly = 1 in
575 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
576 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>;
577 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
580 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load>;
581 def OG : BinaryRXY<"og", 0xE381, or, GR64, load>;
584 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
586 defm : RMWIByte<or, bdaddr12pair, OI>;
587 defm : RMWIByte<or, bdaddr20pair, OIY>;
589 //===----------------------------------------------------------------------===//
591 //===----------------------------------------------------------------------===//
594 // XORs of a register.
595 let isCommutable = 1 in {
596 def XR : BinaryRR <"xr", 0x17, xor, GR32, GR32>;
597 def XGR : BinaryRRE<"xgr", 0xB982, xor, GR64, GR64>;
600 // XORs of a 32-bit immediate, leaving other bits unaffected.
601 let isCodeGenOnly = 1 in
602 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
603 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>;
604 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
607 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load>;
608 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load>;
611 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
613 defm : RMWIByte<xor, bdaddr12pair, XI>;
614 defm : RMWIByte<xor, bdaddr20pair, XIY>;
616 //===----------------------------------------------------------------------===//
618 //===----------------------------------------------------------------------===//
620 // Multiplication of a register.
621 let isCommutable = 1 in {
622 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>;
623 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>;
625 def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>;
626 defm : SXB<mul, GR64, MSGFR>;
628 // Multiplication of a signed 16-bit immediate.
629 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
630 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
632 // Multiplication of a signed 32-bit immediate.
633 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
634 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
636 // Multiplication of memory.
637 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16>;
638 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load>;
639 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32>;
640 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load>;
642 // Multiplication of a register, producing two results.
643 def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>;
645 // Multiplication of memory, producing two results.
646 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load>;
648 //===----------------------------------------------------------------------===//
649 // Division and remainder
650 //===----------------------------------------------------------------------===//
652 // Division and remainder, from registers.
653 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>;
654 def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>;
655 def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>;
656 def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>;
657 defm : SXB<z_sdivrem64, GR128, DSGFR>;
659 // Division and remainder, from memory.
660 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem64, GR128, sextloadi32>;
661 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load>;
662 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load>;
663 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load>;
665 //===----------------------------------------------------------------------===//
667 //===----------------------------------------------------------------------===//
670 let neverHasSideEffects = 1 in {
671 def SLL : ShiftRS <"sll", 0x89, shl, GR32, shift12only>;
672 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64, shift20only>;
675 // Logical shift right.
676 let neverHasSideEffects = 1 in {
677 def SRL : ShiftRS <"srl", 0x88, srl, GR32, shift12only>;
678 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64, shift20only>;
681 // Arithmetic shift right.
683 def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>;
684 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>;
688 let neverHasSideEffects = 1 in {
689 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32, shift20only>;
690 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64, shift20only>;
693 // Rotate second operand left and inserted selected bits into first operand.
694 // These can act like 32-bit operands provided that the constant start and
695 // end bits (operands 2 and 3) are in the range [32, 64)
697 let isCodeGenOnly = 1 in
698 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
699 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
702 //===----------------------------------------------------------------------===//
704 //===----------------------------------------------------------------------===//
706 // Signed comparisons.
708 // Comparison with a register.
709 def CR : CompareRR <"cr", 0x19, z_cmp, GR32, GR32>;
710 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;
711 def CGR : CompareRRE<"cgr", 0xB920, z_cmp, GR64, GR64>;
713 // Comparison with a signed 16-bit immediate.
714 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>;
715 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>;
717 // Comparison with a signed 32-bit immediate.
718 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>;
719 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>;
721 // Comparison with memory.
722 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16>;
723 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load>;
724 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16>;
725 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32>;
726 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load>;
727 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>;
728 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>;
729 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>;
730 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>;
731 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>;
733 // Comparison between memory and a signed 16-bit immediate.
734 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>;
735 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>;
736 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>;
738 defm : SXB<z_cmp, GR64, CGFR>;
740 // Unsigned comparisons.
742 // Comparison with a register.
743 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>;
744 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;
745 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>;
747 // Comparison with a signed 32-bit immediate.
748 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
749 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
751 // Comparison with memory.
752 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load>;
753 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32>;
754 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load>;
755 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
756 aligned_zextloadi16>;
757 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
759 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
760 aligned_zextloadi16>;
761 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
762 aligned_zextloadi32>;
763 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
766 // Comparison between memory and an unsigned 8-bit immediate.
767 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>;
769 // Comparison between memory and an unsigned 16-bit immediate.
770 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>;
771 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
772 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
774 defm : ZXB<z_ucmp, GR64, CLGFR>;
776 //===----------------------------------------------------------------------===//
778 //===----------------------------------------------------------------------===//
780 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
781 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
782 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
784 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
785 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
786 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
787 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
788 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
789 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
790 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
791 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
793 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
794 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
795 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
797 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
798 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
799 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
800 def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
801 def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
802 def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
803 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
804 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
805 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
806 def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
807 def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
808 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
809 def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
811 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
812 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
813 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
814 def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
815 def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
816 def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
817 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
818 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
819 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
820 def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
821 def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
822 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
823 def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
825 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
826 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
827 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
828 def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
829 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
830 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
831 def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
833 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
834 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
836 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
837 def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
839 def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
841 def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
842 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
843 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
845 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
847 def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
849 def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
851 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
853 def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
856 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
857 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
858 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
860 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
861 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
862 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
864 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
865 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
866 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
868 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
869 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
870 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
873 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
874 ADDR32:$bitshift, ADDR32:$negbitshift,
877 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
878 ADDR32:$bitshift, ADDR32:$negbitshift,
879 uimm32:$bitsize))]> {
883 let usesCustomInserter = 1;
887 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
888 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
891 //===----------------------------------------------------------------------===//
892 // Miscellaneous Instructions.
893 //===----------------------------------------------------------------------===//
895 // Read a 32-bit access register into a GR32. As with all GR32 operations,
896 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
897 // when a 64-bit address is stored in a pair of access registers.
898 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
900 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
902 // Find leftmost one, AKA count leading zeros. The instruction actually
903 // returns a pair of GR64s, the first giving the number of leading zeros
904 // and the second giving a copy of the source with the leftmost one bit
905 // cleared. We only use the first result here.
907 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;
909 def : Pat<(ctlz GR64:$src),
910 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>;
912 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
913 def : Pat<(i64 (anyext GR32:$src)),
914 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
916 // There are no 32-bit equivalents of LLILL and LLILH, so use a full
917 // 64-bit move followed by a subreg. This preserves the invariant that
918 // all GR32 operations only modify the low 32 bits.
919 def : Pat<(i32 imm32ll16:$src),
920 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>;
921 def : Pat<(i32 imm32lh16:$src),
922 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>;
924 // Extend GR32s and GR64s to GR128s.
925 let usesCustomInserter = 1 in {
926 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
927 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
928 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
931 //===----------------------------------------------------------------------===//
933 //===----------------------------------------------------------------------===//
935 // Use AL* for GR64 additions of unsigned 32-bit values.
936 defm : ZXB<add, GR64, ALGFR>;
937 def : Pat<(add GR64:$src1, imm64zx32:$src2),
938 (ALGFI GR64:$src1, imm64zx32:$src2)>;
939 def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
940 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
942 // Use SL* for GR64 subtractions of unsigned 32-bit values.
943 defm : ZXB<sub, GR64, SLGFR>;
944 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
945 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
946 def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
947 (SLGF GR64:$src1, bdxaddr20only:$addr)>;