lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // SystemZ Instruction Predicate Definitions.
  16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
  17
  18 include "SystemZInstrFormats.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Type Constraints.
  22 //===----------------------------------------------------------------------===//
  23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Type Profiles.
  30 //===----------------------------------------------------------------------===//
  31 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  33 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  34 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  35 def SDT_BrCond              : SDTypeProfile<0, 2,
  36                                            [SDTCisVT<0, OtherVT>,
  37                                             SDTCisI8<1>]>;
  38 def SDT_SelectCC            : SDTypeProfile<1, 3,
  39                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  40                                             SDTCisI8<3>]>;
  41 def SDT_Address             : SDTypeProfile<1, 1,
  42                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  43
  44 //===----------------------------------------------------------------------===//
  45 // SystemZ Specific Node Definitions.
  46 //===----------------------------------------------------------------------===//
  47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  48                      [SDNPHasChain, SDNPOptInFlag]>;
  49 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  50                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  51 def SystemZcallseq_start :
  52                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  53                         [SDNPHasChain, SDNPOutFlag]>;
  54 def SystemZcallseq_end :
  55                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  56                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  57 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  58 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  59 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  60                             [SDNPHasChain, SDNPInFlag]>;
  61 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  63
  64
  65 include "SystemZOperands.td"
  66
  67 //===----------------------------------------------------------------------===//
  68 // Instruction list..
  69
  70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
  71                               "#ADJCALLSTACKDOWN",
  72                               [(SystemZcallseq_start timm:$amt)]>;
  73 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
  74                               "#ADJCALLSTACKUP",
  75                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
  76
  77 let usesCustomDAGSchedInserter = 1 in {
  78   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
  79                         "# Select32 PSEUDO",
  80                         [(set GR32:$dst,
  81                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
  82   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
  83                         "# Select64 PSEUDO",
  84                         [(set GR64:$dst,
  85                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
  86 }
  87
  88
  89 //===----------------------------------------------------------------------===//
  90 //  Control Flow Instructions...
  91 //
  92
  93 // FIXME: Provide proper encoding!
  94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
  95   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
  96 }
  97
  98 let isBranch = 1, isTerminator = 1 in {
  99   let isBarrier = 1 in {
 100     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 101
 102     let isIndirectBranch = 1 in
 103       def JMPr   : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
 104   }
 105
 106   let Uses = [PSW] in {
 107     def JO  : Pseudo<(outs), (ins brtarget:$dst),
 108                      "jo\t$dst",
 109                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O)]>;
 110     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 111                      "jh\t$dst",
 112                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 113     def JNLE: Pseudo<(outs), (ins brtarget:$dst),
 114                      "jnle\t$dst",
 115                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE)]>;
 116     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 117                      "jl\t$dst",
 118                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 119     def JNHE: Pseudo<(outs), (ins brtarget:$dst),
 120                      "jnhe\t$dst",
 121                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE)]>;
 122     def JLH : Pseudo<(outs), (ins brtarget:$dst),
 123                      "jlh\t$dst",
 124                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH)]>;
 125     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 126                      "jne\t$dst",
 127                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 128     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 129                      "je\t$dst",
 130                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 131     def JNLH: Pseudo<(outs), (ins brtarget:$dst),
 132                      "jnlh\t$dst",
 133                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH)]>;
 134     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 135                      "jhe\t$dst",
 136                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 137     def JNL : Pseudo<(outs), (ins brtarget:$dst),
 138                      "jnl\t$dst",
 139                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL)]>;
 140     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 141                      "jle\t$dst",
 142                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 143     def JNH : Pseudo<(outs), (ins brtarget:$dst),
 144                      "jnh\t$dst",
 145                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH)]>;
 146     def JNO : Pseudo<(outs), (ins brtarget:$dst),
 147                      "jno\t$dst",
 148                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO)]>;
 149   } // Uses = [PSW]
 150 } // isBranch = 1
 151
 152 //===----------------------------------------------------------------------===//
 153 //  Call Instructions...
 154 //
 155
 156 let isCall = 1 in
 157   // All calls clobber the non-callee saved registers. Uses for argument
 158   // registers are added manually.
 159   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
 160               F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L] in {
 161     def CALLi     : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops),
 162                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 163     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 164                            "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 165   }
 166
 167 //===----------------------------------------------------------------------===//
 168 //  Miscellaneous Instructions.
 169 //
 170
 171 let isReMaterializable = 1 in
 172 // FIXME: Provide imm12 variant
 173 // FIXME: Address should be halfword aligned...
 174 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 175                     "lay\t{$dst, $src}",
 176                     [(set GR64:$dst, laaddr:$src)]>;
 177 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 178                     "larl\t{$dst, $src}",
 179                     [(set GR64:$dst,
 180                           (SystemZpcrelwrapper tglobaladdr:$src))]>;
 181
 182 let neverHasSideEffects = 1 in
 183 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 184
 185 //===----------------------------------------------------------------------===//
 186 // Move Instructions
 187
 188 // FIXME: Provide proper encoding!
 189 let neverHasSideEffects = 1 in {
 190 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 191                      "lr\t{$dst, $src}",
 192                      []>;
 193 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 194                      "lgr\t{$dst, $src}",
 195                      []>;
 196 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 197                      "# MOV128 PSEUDO!\n"
 198                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 199                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 200                      []>;
 201 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 202                      "# MOV64P PSEUDO!\n"
 203                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 204                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 205                      []>;
 206 }
 207
 208 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 209                          "lgfr\t{$dst, $src}",
 210                          [(set GR64:$dst, (sext GR32:$src))]>;
 211 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 212                          "llgfr\t{$dst, $src}",
 213                          [(set GR64:$dst, (zext GR32:$src))]>;
 214
 215 // FIXME: Provide proper encoding!
 216 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 217 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src),
 218                        "lhi\t{$dst, $src}",
 219                        [(set GR32:$dst, immSExt16:$src)]>;
 220 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src),
 221                        "lghi\t{$dst, $src}",
 222                        [(set GR64:$dst, immSExt16:$src)]>;
 223
 224 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 225                          "llill\t{$dst, $src}",
 226                          [(set GR64:$dst, i64ll16:$src)]>;
 227 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 228                          "llilh\t{$dst, $src}",
 229                          [(set GR64:$dst, i64lh16:$src)]>;
 230 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 231                          "llihl\t{$dst, $src}",
 232                          [(set GR64:$dst, i64hl16:$src)]>;
 233 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 234                          "llihh\t{$dst, $src}",
 235                          [(set GR64:$dst, i64hh16:$src)]>;
 236
 237 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
 238                        "lgfi\t{$dst, $src}",
 239                        [(set GR64:$dst, immSExt32:$src)]>;
 240 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 241                          "llilf\t{$dst, $src}",
 242                          [(set GR64:$dst, i64lo32:$src)]>;
 243 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 244                          "llihf\t{$dst, $src}",
 245                          [(set GR64:$dst, i64hi32:$src)]>;
 246 }
 247
 248 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 249 def MOV32rm  : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
 250                       "l\t{$dst, $src}",
 251                       [(set GR32:$dst, (load rriaddr12:$src))]>;
 252 def MOV32rmy : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 253                       "ly\t{$dst, $src}",
 254                       [(set GR32:$dst, (load rriaddr:$src))]>;
 255 def MOV64rm  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 256                       "lg\t{$dst, $src}",
 257                       [(set GR64:$dst, (load rriaddr:$src))]>;
 258 def MOV64Prm : Pseudo<(outs GR64P:$dst), (ins rriaddr12:$src),
 259                       "# MOV64P PSEUDO!\n"
 260                       "\tl\t${dst:subreg_odd},  $src\n"
 261                       "\tl\t${dst:subreg_even}, 4+$src",
 262                       [(set GR64P:$dst, (load rriaddr12:$src))]>;
 263 def MOV64Prmy : Pseudo<(outs GR64P:$dst), (ins rriaddr:$src),
 264                        "# MOV64P PSEUDO!\n"
 265                        "\tly\t${dst:subreg_odd},  $src\n"
 266                        "\tly\t${dst:subreg_even}, 4+$src",
 267                        [(set GR64P:$dst, (load rriaddr:$src))]>;
 268 def MOV128rm : Pseudo<(outs GR128:$dst), (ins rriaddr:$src),
 269                       "# MOV128 PSEUDO!\n"
 270                       "\tlg\t${dst:subreg_odd},  $src\n"
 271                       "\tlg\t${dst:subreg_even}, 8+$src",
 272                       [(set GR128:$dst, (load rriaddr:$src))]>;
 273 }
 274
 275 def MOV32mr  : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 276                       "st\t{$src, $dst}",
 277                       [(store GR32:$src, rriaddr12:$dst)]>;
 278 def MOV32mry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 279                       "sty\t{$src, $dst}",
 280                       [(store GR32:$src, rriaddr:$dst)]>;
 281 def MOV64mr  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 282                       "stg\t{$src, $dst}",
 283                       [(store GR64:$src, rriaddr:$dst)]>;
 284 def MOV64Pmr : Pseudo<(outs), (ins rriaddr12:$dst, GR64P:$src),
 285                       "# MOV64P PSEUDO!\n"
 286                       "\tst\t${src:subreg_odd}, $dst\n"
 287                       "\tst\t${src:subreg_even}, 4+$dst",
 288                       [(store GR64P:$src, rriaddr12:$dst)]>;
 289 def MOV64Pmry : Pseudo<(outs), (ins rriaddr:$dst, GR64P:$src),
 290                        "# MOV64P PSEUDO!\n"
 291                        "\tsty\t${src:subreg_odd}, $dst\n"
 292                        "\tsty\t${src:subreg_even}, 4+$dst",
 293                        [(store GR64P:$src, rriaddr:$dst)]>;
 294 def MOV128mr : Pseudo<(outs), (ins rriaddr:$dst, GR128:$src),
 295                       "# MOV128 PSEUDO!\n"
 296                       "\tstg\t${src:subreg_odd}, $dst\n"
 297                       "\tstg\t${src:subreg_even}, 8+$dst",
 298                       [(store GR128:$src, rriaddr:$dst)]>;
 299
 300 def MOV8mi    : Pseudo<(outs), (ins riaddr12:$dst, i32i8imm:$src),
 301                        "mvi\t{$dst, $src}",
 302                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
 303 def MOV8miy   : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 304                        "mviy\t{$dst, $src}",
 305                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 306
 307 def MOV16mi   : Pseudo<(outs), (ins riaddr12:$dst, s16imm:$src),
 308                        "mvhhi\t{$dst, $src}",
 309                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
 310                        Requires<[IsZ10]>;
 311 def MOV32mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm:$src),
 312                        "mvhi\t{$dst, $src}",
 313                        [(store (i32 immSExt16:$src), riaddr12:$dst)]>,
 314                        Requires<[IsZ10]>;
 315 def MOV64mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm64:$src),
 316                        "mvghi\t{$dst, $src}",
 317                        [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
 318                        Requires<[IsZ10]>;
 319
 320 // sexts
 321 def MOVSX32rr8  : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 322                          "lbr\t{$dst, $src}",
 323                          [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 324 def MOVSX64rr8  : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 325                          "lgbr\t{$dst, $src}",
 326                          [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 327 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 328                          "lhr\t{$dst, $src}",
 329                          [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 330 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 331                          "lghr\t{$dst, $src}",
 332                          [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 333
 334 // extloads
 335 def MOVSX32rm8   : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 336                           "lb\t{$dst, $src}",
 337                           [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 338 def MOVSX32rm16  : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
 339                           "lh\t{$dst, $src}",
 340                           [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
 341 def MOVSX32rm16y : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 342                          "lhy\t{$dst, $src}",
 343                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 344 def MOVSX64rm8   : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 345                           "lgb\t{$dst, $src}",
 346                           [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 347 def MOVSX64rm16  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 348                           "lgh\t{$dst, $src}",
 349                           [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 350 def MOVSX64rm32  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 351                           "lgf\t{$dst, $src}",
 352                           [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 353
 354 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 355                          "llc\t{$dst, $src}",
 356                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 357 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 358                          "llh\t{$dst, $src}",
 359                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 360 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 361                          "llgc\t{$dst, $src}",
 362                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 363 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 364                          "llgh\t{$dst, $src}",
 365                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 366 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 367                          "llgf\t{$dst, $src}",
 368                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 369
 370 // truncstores
 371 def MOV32m8r   : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 372                         "stc\t{$src, $dst}",
 373                         [(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
 374
 375 def MOV32m8ry  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 376                         "stcy\t{$src, $dst}",
 377                         [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 378
 379 def MOV32m16r  : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 380                         "sth\t{$src, $dst}",
 381                         [(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
 382
 383 def MOV32m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 384                         "sthy\t{$src, $dst}",
 385                         [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 386
 387 def MOV64m8r   : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 388                         "stc\t{$src, $dst}",
 389                         [(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
 390
 391 def MOV64m8ry  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 392                         "stcy\t{$src, $dst}",
 393                         [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 394
 395 def MOV64m16r  : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 396                         "sth\t{$src, $dst}",
 397                         [(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
 398
 399 def MOV64m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 400                         "sthy\t{$src, $dst}",
 401                         [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 402
 403 def MOV64m32r  : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 404                         "st\t{$src, $dst}",
 405                         [(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
 406
 407 def MOV64m32ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 408                         "sty\t{$src, $dst}",
 409                         [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 410
 411 // multiple regs moves
 412 // FIXME: should we use multiple arg nodes?
 413 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 414                        "stmy\t{$from, $to, $dst}",
 415                        []>;
 416 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 417                        "stmg\t{$from, $to, $dst}",
 418                        []>;
 419 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 420                        "lmy\t{$from, $to, $dst}",
 421                        []>;
 422 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 423                        "lmg\t{$from, $to, $dst}",
 424                        []>;
 425
 426 let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
 427 def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 428                            "lhi\t${dst:subreg_even}, 0",
 429                            []>;
 430 def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 431                            "lghi\t${dst:subreg_even}, 0",
 432                            []>;
 433 }
 434
 435 // Byte swaps
 436 def BSWAP32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 437                        "lrvr\t{$dst, $src}",
 438                        [(set GR32:$dst, (bswap GR32:$src))]>;
 439 def BSWAP64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 440                        "lrvgr\t{$dst, $src}",
 441                        [(set GR64:$dst, (bswap GR64:$src))]>;
 442
 443 def BSWAP16rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 444                        "lrvh\t{$dst, $src}",
 445                        [(set GR32:$dst, (bswap (extloadi32i16 rriaddr:$src)))]>;
 446 def BSWAP32rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 447                        "lrv\t{$dst, $src}",
 448                        [(set GR32:$dst, (bswap (load rriaddr:$src)))]>;
 449 def BSWAP64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 450                        "lrvg\t{$dst, $src}",
 451                        [(set GR64:$dst, (bswap (load rriaddr:$src)))]>;
 452
 453 //===----------------------------------------------------------------------===//
 454 // Arithmetic Instructions
 455
 456 let Defs = [PSW] in {
 457 def NEG32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 458                      "lcr\t{$dst, $src}",
 459                      [(set GR32:$dst, (ineg GR32:$src)),
 460                       (implicit PSW)]>;
 461 def NEG64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 462                      "lcgr\t{$dst, $src}",
 463                      [(set GR64:$dst, (ineg GR64:$src)),
 464                       (implicit PSW)]>;
 465 def NEG64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 466                        "lcgfr\t{$dst, $src}",
 467                        [(set GR64:$dst, (ineg (sext GR32:$src))),
 468                         (implicit PSW)]>;
 469 }
 470
 471 let isTwoAddress = 1 in {
 472
 473 let Defs = [PSW] in {
 474
 475 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 476 // FIXME: Provide proper encoding!
 477 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 478                      "ar\t{$dst, $src2}",
 479                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 480                       (implicit PSW)]>;
 481 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 482                      "agr\t{$dst, $src2}",
 483                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 484                       (implicit PSW)]>;
 485 }
 486
 487 // FIXME: Provide proper encoding!
 488 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 489                        "ahi\t{$dst, $src2}",
 490                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 491                         (implicit PSW)]>;
 492 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 493                        "afi\t{$dst, $src2}",
 494                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 495                         (implicit PSW)]>;
 496 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 497                        "aghi\t{$dst, $src2}",
 498                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 499                         (implicit PSW)]>;
 500 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 501                        "agfi\t{$dst, $src2}",
 502                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 503                         (implicit PSW)]>;
 504
 505 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 506 // FIXME: Provide proper encoding!
 507 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 508                      "nr\t{$dst, $src2}",
 509                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 510 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 511                      "ngr\t{$dst, $src2}",
 512                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 513 }
 514
 515 // FIXME: Provide proper encoding!
 516 // FIXME: Compute masked bits properly!
 517 def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 518                          "nill\t{$dst, $src2}",
 519                         [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
 520 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 521                          "nill\t{$dst, $src2}",
 522                          [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
 523
 524 def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 525                          "nilh\t{$dst, $src2}",
 526                          [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
 527 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 528                          "nilh\t{$dst, $src2}",
 529                          [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
 530
 531 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 532                          "nihl\t{$dst, $src2}",
 533                          [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
 534 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 535                          "nihh\t{$dst, $src2}",
 536                          [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
 537
 538 def AND32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 539                          "nilf\t{$dst, $src2}",
 540                          [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
 541 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 542                          "nilf\t{$dst, $src2}",
 543                          [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
 544 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 545                          "nihf\t{$dst, $src2}",
 546                          [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
 547
 548 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 549 // FIXME: Provide proper encoding!
 550 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 551                     "or\t{$dst, $src2}",
 552                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 553 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 554                     "ogr\t{$dst, $src2}",
 555                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 556 }
 557
 558 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 559                       "oill\t{$dst, $src2}",
 560                       [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
 561 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 562                       "oilh\t{$dst, $src2}",
 563                       [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
 564 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 565                     "oilf\t{$dst, $src2}",
 566                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 567
 568 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 569                         "oill\t{$dst, $src2}",
 570                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 571 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 572                         "oilh\t{$dst, $src2}",
 573                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 574 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 575                         "oihl\t{$dst, $src2}",
 576                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 577 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 578                         "oihh\t{$dst, $src2}",
 579                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 580
 581 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 582                         "oilf\t{$dst, $src2}",
 583                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 584 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 585                         "oihf\t{$dst, $src2}",
 586                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 587
 588 // FIXME: Provide proper encoding!
 589 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 590                      "sr\t{$dst, $src2}",
 591                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 592 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 593                      "sgr\t{$dst, $src2}",
 594                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 595
 596
 597 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 598 // FIXME: Provide proper encoding!
 599 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 600                      "xr\t{$dst, $src2}",
 601                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 602 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 603                      "xgr\t{$dst, $src2}",
 604                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 605 }
 606
 607 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 608                      "xilf\t{$dst, $src2}",
 609                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 610
 611 } // Defs = [PSW]
 612
 613 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 614 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 615                      "msr\t{$dst, $src2}",
 616                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 617 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 618                      "msgr\t{$dst, $src2}",
 619                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 620 }
 621
 622 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 623                         "mr\t{$dst, $src2}",
 624                         []>;
 625 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 626                          "mlr\t{$dst, $src2}",
 627                          []>;
 628 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 629                         "mlgr\t{$dst, $src2}",
 630                         []>;
 631
 632 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 633                          "mhi\t{$dst, $src2}",
 634                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 635 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 636                          "mghi\t{$dst, $src2}",
 637                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 638
 639 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 640                          "msfi\t{$dst, $src2}",
 641                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
 642                          Requires<[IsZ10]>;
 643 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 644                          "msgfi\t{$dst, $src2}",
 645                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
 646                          Requires<[IsZ10]>;
 647
 648 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 649                      "ms\t{$dst, $src2}",
 650                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
 651 def MUL32rmy : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 652                       "msy\t{$dst, $src2}",
 653                       [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 654 def MUL64rm  : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 655                       "msg\t{$dst, $src2}",
 656                       [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 657
 658 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 659                          "msgfr\t{$dst, $src2}",
 660                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 661
 662 def SDIVREM32r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR32:$src2),
 663                         "dsgfr\t{$dst, $src2}",
 664                         []>;
 665 def SDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 666                         "dsgr\t{$dst, $src2}",
 667                         []>;
 668
 669 def UDIVREM32r : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 670                         "dlr\t{$dst, $src2}",
 671                         []>;
 672 def UDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 673                         "dlgr\t{$dst, $src2}",
 674                         []>;
 675 let mayLoad = 1 in {
 676 def SDIVREM32m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 677                         "dsgf\t{$dst, $src2}",
 678                         []>;
 679 def SDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 680                         "dsg\t{$dst, $src2}",
 681                         []>;
 682
 683 def UDIVREM32m : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
 684                         "dl\t{$dst, $src2}",
 685                         []>;
 686 def UDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 687                         "dlg\t{$dst, $src2}",
 688                         []>;
 689 } // mayLoad
 690 } // isTwoAddress = 1
 691
 692 //===----------------------------------------------------------------------===//
 693 // Shifts
 694
 695 let isTwoAddress = 1 in
 696 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 697                       "srl\t{$src, $amt}",
 698                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 699 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 700                       "srlg\t{$dst, $src, $amt}",
 701                       [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>;
 702
 703 let isTwoAddress = 1 in
 704 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 705                       "sll\t{$src, $amt}",
 706                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 707 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 708                       "sllg\t{$dst, $src, $amt}",
 709                       [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>;
 710
 711 let Defs = [PSW] in {
 712 let isTwoAddress = 1 in
 713 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 714                       "sra\t{$src, $amt}",
 715                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 716                        (implicit PSW)]>;
 717
 718 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 719                       "srag\t{$dst, $src, $amt}",
 720                       [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)),
 721                        (implicit PSW)]>;
 722 } // Defs = [PSW]
 723
 724 def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 725                        "rll\t{$dst, $src, $amt}",
 726                        [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
 727 def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 728                        "rllg\t{$dst, $src, $amt}",
 729                        [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>;
 730
 731 //===----------------------------------------------------------------------===//
 732 // Test instructions (like AND but do not produce any result)
 733
 734 // Integer comparisons
 735 let Defs = [PSW] in {
 736 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 737                      "cr\t$src1, $src2",
 738                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 739 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 740                      "cgr\t$src1, $src2",
 741                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 742
 743 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2),
 744                        "cfi\t$src1, $src2",
 745                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 746 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
 747                        "cgfi\t$src1, $src2",
 748                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 749                         (implicit PSW)]>;
 750
 751 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
 752                      "c\t$src1, $src2",
 753                      [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
 754                       (implicit PSW)]>;
 755 def CMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 756                       "cy\t$src1, $src2",
 757                       [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 758                        (implicit PSW)]>;
 759 def CMP64rm  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 760                       "cg\t$src1, $src2",
 761                       [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 762                        (implicit PSW)]>;
 763
 764 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 765                       "clr\t$src1, $src2",
 766                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 767 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 768                       "clgr\t$src1, $src2",
 769                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 770
 771 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 772                         "clfi\t$src1, $src2",
 773                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 774 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 775                         "clgfi\t$src1, $src2",
 776                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 777                          (implicit PSW)]>;
 778
 779 def UCMP32rm  : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
 780                        "cl\t$src1, $src2",
 781                        [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
 782                         (implicit PSW)]>;
 783 def UCMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 784                        "cly\t$src1, $src2",
 785                        [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 786                         (implicit PSW)]>;
 787 def UCMP64rm  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 788                        "clg\t$src1, $src2",
 789                        [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 790                         (implicit PSW)]>;
 791
 792 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 793                           "cgfr\t$src1, $src2",
 794                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 795                            (implicit PSW)]>;
 796 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 797                           "clgfr\t$src1, $src2",
 798                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 799                            (implicit PSW)]>;
 800
 801 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 802                            "cgf\t$src1, $src2",
 803                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 804                             (implicit PSW)]>;
 805 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 806                            "clgf\t$src1, $src2",
 807                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 808                             (implicit PSW)]>;
 809
 810 // FIXME: Add other crazy ucmp forms
 811
 812 } // Defs = [PSW]
 813
 814 //===----------------------------------------------------------------------===//
 815 // Non-Instruction Patterns.
 816 //===----------------------------------------------------------------------===//
 817
 818 // ConstPools, JumpTables
 819 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
 820 def : Pat<(SystemZpcrelwrapper tconstpool:$src), (LA64rm tconstpool:$src)>;
 821
 822 // anyext
 823 def : Pat<(i64 (anyext GR32:$src)),
 824           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 825
 826 // calls
 827 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
 828 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
 829
 830 //===----------------------------------------------------------------------===//
 831 // Peepholes.
 832 //===----------------------------------------------------------------------===//
 833
 834 // FIXME: use add/sub tricks with 32678/-32768
 835
 836 // Arbitrary immediate support.
 837 def : Pat<(i32 imm:$src),
 838           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;
 839
 840 // Implement in terms of LLIHF/OILF.
 841 def : Pat<(i64 imm:$imm),
 842           (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
 843
 844 // trunc patterns
 845 def : Pat<(i32 (trunc GR64:$src)),
 846           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 847
 848 // sext_inreg patterns
 849 def : Pat<(sext_inreg GR64:$src, i32),
 850           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 851
 852 // extload patterns
 853 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 854 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 855 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 856 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 857 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 858
 859 // muls
 860 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 861           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
 862                                                    GR32:$src1, subreg_odd32),
 863                                     GR32:$src2),
 864                           subreg_even32)>;
 865
 866 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 867           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
 868                                                     GR32:$src1, subreg_odd32),
 869                                      GR32:$src2),
 870                           subreg_even32)>;
 871 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 872           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
 873                                                      GR64:$src1, subreg_odd),
 874                                       GR64:$src2),
 875                           subreg_even)>;