1 //===- SystemZInstrInfo.h - SystemZ Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/ADT/IndexedMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
24 class SystemZTargetMachine;
26 /// SystemZII - This namespace holds all of the target specific flags that
27 /// instruction info tracks.
31 //===------------------------------------------------------------------===//
32 // SystemZ Specific MachineOperand flags.
36 /// MO_GOTENT - On a symbol operand this indicates that the immediate is
37 /// the offset to the location of the symbol name from the base of the GOT.
39 /// SYMBOL_LABEL @GOTENT
42 /// MO_PLT - On a symbol operand this indicates that the immediate is
43 /// offset to the PLT entry of symbol name from the current code location.
50 class SystemZInstrInfo : public TargetInstrInfoImpl {
51 const SystemZRegisterInfo RI;
52 SystemZTargetMachine &TM;
53 IndexedMap<unsigned> RegSpillOffsets;
55 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
57 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
58 /// such, whenever a client has an instance of instruction info, it should
59 /// always be able to get register info as well (through this method).
61 virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
63 bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
64 unsigned DestReg, unsigned SrcReg,
65 const TargetRegisterClass *DestRC,
66 const TargetRegisterClass *SrcRC,
69 bool isMoveInstr(const MachineInstr& MI,
70 unsigned &SrcReg, unsigned &DstReg,
71 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
72 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
73 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
75 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator MI,
77 unsigned SrcReg, bool isKill,
79 const TargetRegisterClass *RC,
80 const TargetRegisterInfo *TRI) const;
81 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MI,
83 unsigned DestReg, int FrameIdx,
84 const TargetRegisterClass *RC,
85 const TargetRegisterInfo *TRI) const;
87 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MI,
89 const std::vector<CalleeSavedInfo> &CSI,
90 const TargetRegisterInfo *TRI) const;
91 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 const std::vector<CalleeSavedInfo> &CSI,
94 const TargetRegisterInfo *TRI) const;
96 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
97 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
98 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
99 MachineBasicBlock *&TBB,
100 MachineBasicBlock *&FBB,
101 SmallVectorImpl<MachineOperand> &Cond,
102 bool AllowModify) const;
103 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
104 MachineBasicBlock *FBB,
105 const SmallVectorImpl<MachineOperand> &Cond,
107 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
109 SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
110 SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
111 const TargetInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
112 const TargetInstrDesc& getLongDispOpc(unsigned Opc) const;
114 const TargetInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const {
115 if (Offset < 0 || Offset >= 4096)
116 return getLongDispOpc(Opc);