1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
36 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
37 // accesses (LARL). Operand 0 is the address.
40 // Signed integer and floating-point comparisons. The operands are the
41 // two values to compare.
44 // Likewise unsigned integer comparison.
47 // Branches if a condition is true. Operand 0 is the chain operand;
48 // operand 1 is the 4-bit condition-code mask, with bit N in
49 // big-endian order meaning "branch if CC=N"; operand 2 is the
50 // target block and operand 3 is the flag operand.
53 // Selects between operand 0 and operand 1. Operand 2 is the
54 // mask of condition-code values for which operand 0 should be
55 // chosen over operand 1; it has the same form as BR_CCMASK.
56 // Operand 3 is the flag operand.
59 // Evaluates to the gap between the stack pointer and the
60 // base of the dynamically-allocatable area.
63 // Extracts the value of a 32-bit access register. Operand 0 is
64 // the number of the register.
67 // Wrappers around the ISD opcodes of the same name. The output and
68 // first input operands are GR128s. The trailing numbers are the
69 // widths of the second operand in bits.
75 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
78 // Operand 0: the address of the containing 32-bit-aligned field
79 // Operand 1: the second operand of <op>, in the high bits of an i32
80 // for everything except ATOMIC_SWAPW
81 // Operand 2: how many bits to rotate the i32 left to bring the first
82 // operand into the high bits
83 // Operand 3: the negative of operand 2, for rotating the other way
84 // Operand 4: the width of the field in bits (8 or 16)
85 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
97 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
99 // Operand 0: the address of the containing 32-bit-aligned field
100 // Operand 1: the compare value, in the low bits of an i32
101 // Operand 2: the swap value, in the low bits of an i32
102 // Operand 3: how many bits to rotate the i32 left to bring the first
103 // operand into the high bits
104 // Operand 4: the negative of operand 2, for rotating the other way
105 // Operand 5: the width of the field in bits (8 or 16)
110 class SystemZSubtarget;
111 class SystemZTargetMachine;
113 class SystemZTargetLowering : public TargetLowering {
115 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
117 // Override TargetLowering.
118 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
121 virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
124 virtual bool isFMAFasterThanMulAndAdd(EVT) const LLVM_OVERRIDE {
127 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
128 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
129 virtual std::pair<unsigned, const TargetRegisterClass *>
130 getRegForInlineAsmConstraint(const std::string &Constraint,
131 EVT VT) const LLVM_OVERRIDE;
132 virtual TargetLowering::ConstraintType
133 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
134 virtual TargetLowering::ConstraintWeight
135 getSingleConstraintMatchWeight(AsmOperandInfo &info,
136 const char *constraint) const LLVM_OVERRIDE;
138 LowerAsmOperandForConstraint(SDValue Op,
139 std::string &Constraint,
140 std::vector<SDValue> &Ops,
141 SelectionDAG &DAG) const LLVM_OVERRIDE;
142 virtual MachineBasicBlock *
143 EmitInstrWithCustomInserter(MachineInstr *MI,
144 MachineBasicBlock *BB) const LLVM_OVERRIDE;
145 virtual SDValue LowerOperation(SDValue Op,
146 SelectionDAG &DAG) const LLVM_OVERRIDE;
148 LowerFormalArguments(SDValue Chain,
149 CallingConv::ID CallConv, bool isVarArg,
150 const SmallVectorImpl<ISD::InputArg> &Ins,
151 SDLoc DL, SelectionDAG &DAG,
152 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
154 LowerCall(CallLoweringInfo &CLI,
155 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
158 LowerReturn(SDValue Chain,
159 CallingConv::ID CallConv, bool IsVarArg,
160 const SmallVectorImpl<ISD::OutputArg> &Outs,
161 const SmallVectorImpl<SDValue> &OutVals,
162 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
165 const SystemZSubtarget &Subtarget;
166 const SystemZTargetMachine &TM;
168 // Implement LowerOperation for individual opcodes.
169 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
170 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
171 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
172 SelectionDAG &DAG) const;
173 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
174 SelectionDAG &DAG) const;
175 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
176 SelectionDAG &DAG) const;
177 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
178 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
179 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
180 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
181 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
182 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
183 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
184 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
185 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
186 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
187 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
188 unsigned Opcode) const;
189 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
190 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
191 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
193 // If the last instruction before MBBI in MBB was some form of COMPARE,
194 // try to replace it with a COMPARE AND BRANCH just before MBBI.
195 // CCMask and Target are the BRC-like operands for the branch.
196 // Return true if the change was made.
197 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
198 MachineBasicBlock::iterator MBBI,
200 MachineBasicBlock *Target) const;
202 // Implement EmitInstrWithCustomInserter for individual operation types.
203 MachineBasicBlock *emitSelect(MachineInstr *MI,
204 MachineBasicBlock *BB) const;
205 MachineBasicBlock *emitExt128(MachineInstr *MI,
206 MachineBasicBlock *MBB,
207 bool ClearEven, unsigned SubReg) const;
208 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
209 MachineBasicBlock *BB,
210 unsigned BinOpcode, unsigned BitSize,
211 bool Invert = false) const;
212 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
213 MachineBasicBlock *MBB,
214 unsigned CompareOpcode,
215 unsigned KeepOldMask,
216 unsigned BitSize) const;
217 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
218 MachineBasicBlock *BB) const;
220 } // end namespace llvm
222 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H