1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 // Represents a sequence for extracting a 0/1 value from an IPM result:
32 // (((X ^ XORValue) + AddValue) >> Bit)
33 struct IPMConversion {
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
42 // Represents information about a comparison.
44 Comparison(SDValue Op0In, SDValue Op1In)
45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
47 // The operands to the comparison.
50 // The opcode that should be used to compare Op0 and Op1.
53 // A SystemZICMP value. Only used for integer comparisons.
56 // The mask of CC values that Opcode can produce.
59 // The mask of CC values for which the original condition is true.
64 // Classify VT as either 32 or 64 bit.
65 static bool is32Bit(EVT VT) {
66 switch (VT.getSimpleVT().SimpleTy) {
72 llvm_unreachable("Unsupported type");
76 // Return a version of MachineOperand that can be safely used before the
78 static MachineOperand earlyUseOperand(MachineOperand Op) {
84 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
85 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
86 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
87 MVT PtrVT = getPointerTy();
89 // Set up the register classes.
90 if (Subtarget.hasHighWord())
91 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
93 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
94 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
95 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
96 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
97 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
99 // Compute derived properties from the register classes
100 computeRegisterProperties();
102 // Set up special registers.
103 setExceptionPointerRegister(SystemZ::R6D);
104 setExceptionSelectorRegister(SystemZ::R7D);
105 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
107 // TODO: It may be better to default to latency-oriented scheduling, however
108 // LLVM's current latency-oriented scheduler can't handle physreg definitions
109 // such as SystemZ has with CC, so set this to the register-pressure
110 // scheduler, because it can.
111 setSchedulingPreference(Sched::RegPressure);
113 setBooleanContents(ZeroOrOneBooleanContent);
114 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
116 // Instructions are strings of 2-byte aligned 2-byte values.
117 setMinFunctionAlignment(2);
119 // Handle operations that are handled in a similar way for all types.
120 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
121 I <= MVT::LAST_FP_VALUETYPE;
123 MVT VT = MVT::SimpleValueType(I);
124 if (isTypeLegal(VT)) {
125 // Lower SET_CC into an IPM-based sequence.
126 setOperationAction(ISD::SETCC, VT, Custom);
128 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
129 setOperationAction(ISD::SELECT, VT, Expand);
131 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
132 setOperationAction(ISD::SELECT_CC, VT, Custom);
133 setOperationAction(ISD::BR_CC, VT, Custom);
137 // Expand jump table branches as address arithmetic followed by an
139 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
141 // Expand BRCOND into a BR_CC (see above).
142 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
144 // Handle integer types.
145 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
146 I <= MVT::LAST_INTEGER_VALUETYPE;
148 MVT VT = MVT::SimpleValueType(I);
149 if (isTypeLegal(VT)) {
150 // Expand individual DIV and REMs into DIVREMs.
151 setOperationAction(ISD::SDIV, VT, Expand);
152 setOperationAction(ISD::UDIV, VT, Expand);
153 setOperationAction(ISD::SREM, VT, Expand);
154 setOperationAction(ISD::UREM, VT, Expand);
155 setOperationAction(ISD::SDIVREM, VT, Custom);
156 setOperationAction(ISD::UDIVREM, VT, Custom);
158 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
159 // stores, putting a serialization instruction after the stores.
160 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
161 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
163 // No special instructions for these.
164 setOperationAction(ISD::CTPOP, VT, Expand);
165 setOperationAction(ISD::CTTZ, VT, Expand);
166 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
167 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
168 setOperationAction(ISD::ROTR, VT, Expand);
170 // Use *MUL_LOHI where possible instead of MULH*.
171 setOperationAction(ISD::MULHS, VT, Expand);
172 setOperationAction(ISD::MULHU, VT, Expand);
173 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
174 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
176 // We have instructions for signed but not unsigned FP conversion.
177 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
181 // Type legalization will convert 8- and 16-bit atomic operations into
182 // forms that operate on i32s (but still keeping the original memory VT).
183 // Lower them into full i32 operations.
184 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
185 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
186 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
187 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
188 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
189 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
190 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
191 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
192 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
193 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
194 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
195 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
197 // We have instructions for signed but not unsigned FP conversion.
198 // Handle unsigned 32-bit types as signed 64-bit types.
199 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
200 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
202 // We have native support for a 64-bit CTLZ, via FLOGR.
203 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
204 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
206 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
207 setOperationAction(ISD::OR, MVT::i64, Custom);
209 // FIXME: Can we support these natively?
210 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
211 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
212 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
214 // We have native instructions for i8, i16 and i32 extensions, but not i1.
215 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
216 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
217 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
220 // Handle the various types of symbolic address.
221 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
222 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
223 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
224 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
225 setOperationAction(ISD::JumpTable, PtrVT, Custom);
227 // We need to handle dynamic allocations specially because of the
228 // 160-byte area at the bottom of the stack.
229 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
231 // Use custom expanders so that we can force the function to use
233 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
234 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
236 // Handle prefetches with PFD or PFDRL.
237 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
239 // Handle floating-point types.
240 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
241 I <= MVT::LAST_FP_VALUETYPE;
243 MVT VT = MVT::SimpleValueType(I);
244 if (isTypeLegal(VT)) {
245 // We can use FI for FRINT.
246 setOperationAction(ISD::FRINT, VT, Legal);
248 // We can use the extended form of FI for other rounding operations.
249 if (Subtarget.hasFPExtension()) {
250 setOperationAction(ISD::FNEARBYINT, VT, Legal);
251 setOperationAction(ISD::FFLOOR, VT, Legal);
252 setOperationAction(ISD::FCEIL, VT, Legal);
253 setOperationAction(ISD::FTRUNC, VT, Legal);
254 setOperationAction(ISD::FROUND, VT, Legal);
257 // No special instructions for these.
258 setOperationAction(ISD::FSIN, VT, Expand);
259 setOperationAction(ISD::FCOS, VT, Expand);
260 setOperationAction(ISD::FREM, VT, Expand);
264 // We have fused multiply-addition for f32 and f64 but not f128.
265 setOperationAction(ISD::FMA, MVT::f32, Legal);
266 setOperationAction(ISD::FMA, MVT::f64, Legal);
267 setOperationAction(ISD::FMA, MVT::f128, Expand);
269 // Needed so that we don't try to implement f128 constant loads using
270 // a load-and-extend of a f80 constant (in cases where the constant
271 // would fit in an f80).
272 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
274 // Floating-point truncation and stores need to be done separately.
275 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
276 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
277 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
279 // We have 64-bit FPR<->GPR moves, but need special handling for
281 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
282 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
284 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
285 // structure, but VAEND is a no-op.
286 setOperationAction(ISD::VASTART, MVT::Other, Custom);
287 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
288 setOperationAction(ISD::VAEND, MVT::Other, Expand);
290 // We want to use MVC in preference to even a single load/store pair.
291 MaxStoresPerMemcpy = 0;
292 MaxStoresPerMemcpyOptSize = 0;
294 // The main memset sequence is a byte store followed by an MVC.
295 // Two STC or MV..I stores win over that, but the kind of fused stores
296 // generated by target-independent code don't when the byte value is
297 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
298 // than "STC;MVC". Handle the choice in target-specific code instead.
299 MaxStoresPerMemset = 0;
300 MaxStoresPerMemsetOptSize = 0;
303 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
306 return VT.changeVectorElementTypeToInteger();
309 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
310 VT = VT.getScalarType();
315 switch (VT.getSimpleVT().SimpleTy) {
328 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
329 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
330 return Imm.isZero() || Imm.isNegZero();
333 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
335 // Unaligned accesses should never be slower than the expanded version.
336 // We check specifically for aligned accesses in the few cases where
337 // they are required.
343 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
345 // Punt on globals for now, although they can be used in limited
346 // RELATIVE LONG cases.
350 // Require a 20-bit signed offset.
351 if (!isInt<20>(AM.BaseOffs))
354 // Indexing is OK but no scale factor can be applied.
355 return AM.Scale == 0 || AM.Scale == 1;
358 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
359 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
361 unsigned FromBits = FromType->getPrimitiveSizeInBits();
362 unsigned ToBits = ToType->getPrimitiveSizeInBits();
363 return FromBits > ToBits;
366 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
367 if (!FromVT.isInteger() || !ToVT.isInteger())
369 unsigned FromBits = FromVT.getSizeInBits();
370 unsigned ToBits = ToVT.getSizeInBits();
371 return FromBits > ToBits;
374 //===----------------------------------------------------------------------===//
375 // Inline asm support
376 //===----------------------------------------------------------------------===//
378 TargetLowering::ConstraintType
379 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
380 if (Constraint.size() == 1) {
381 switch (Constraint[0]) {
382 case 'a': // Address register
383 case 'd': // Data register (equivalent to 'r')
384 case 'f': // Floating-point register
385 case 'h': // High-part register
386 case 'r': // General-purpose register
387 return C_RegisterClass;
389 case 'Q': // Memory with base and unsigned 12-bit displacement
390 case 'R': // Likewise, plus an index
391 case 'S': // Memory with base and signed 20-bit displacement
392 case 'T': // Likewise, plus an index
393 case 'm': // Equivalent to 'T'.
396 case 'I': // Unsigned 8-bit constant
397 case 'J': // Unsigned 12-bit constant
398 case 'K': // Signed 16-bit constant
399 case 'L': // Signed 20-bit displacement (on all targets we support)
400 case 'M': // 0x7fffffff
407 return TargetLowering::getConstraintType(Constraint);
410 TargetLowering::ConstraintWeight SystemZTargetLowering::
411 getSingleConstraintMatchWeight(AsmOperandInfo &info,
412 const char *constraint) const {
413 ConstraintWeight weight = CW_Invalid;
414 Value *CallOperandVal = info.CallOperandVal;
415 // If we don't have a value, we can't do a match,
416 // but allow it at the lowest weight.
417 if (CallOperandVal == NULL)
419 Type *type = CallOperandVal->getType();
420 // Look at the constraint type.
421 switch (*constraint) {
423 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
426 case 'a': // Address register
427 case 'd': // Data register (equivalent to 'r')
428 case 'h': // High-part register
429 case 'r': // General-purpose register
430 if (CallOperandVal->getType()->isIntegerTy())
431 weight = CW_Register;
434 case 'f': // Floating-point register
435 if (type->isFloatingPointTy())
436 weight = CW_Register;
439 case 'I': // Unsigned 8-bit constant
440 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
441 if (isUInt<8>(C->getZExtValue()))
442 weight = CW_Constant;
445 case 'J': // Unsigned 12-bit constant
446 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
447 if (isUInt<12>(C->getZExtValue()))
448 weight = CW_Constant;
451 case 'K': // Signed 16-bit constant
452 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
453 if (isInt<16>(C->getSExtValue()))
454 weight = CW_Constant;
457 case 'L': // Signed 20-bit displacement (on all targets we support)
458 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
459 if (isInt<20>(C->getSExtValue()))
460 weight = CW_Constant;
463 case 'M': // 0x7fffffff
464 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
465 if (C->getZExtValue() == 0x7fffffff)
466 weight = CW_Constant;
472 // Parse a "{tNNN}" register constraint for which the register type "t"
473 // has already been verified. MC is the class associated with "t" and
474 // Map maps 0-based register numbers to LLVM register numbers.
475 static std::pair<unsigned, const TargetRegisterClass *>
476 parseRegisterNumber(const std::string &Constraint,
477 const TargetRegisterClass *RC, const unsigned *Map) {
478 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
479 if (isdigit(Constraint[2])) {
480 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
481 unsigned Index = atoi(Suffix.c_str());
482 if (Index < 16 && Map[Index])
483 return std::make_pair(Map[Index], RC);
485 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
488 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
489 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
490 if (Constraint.size() == 1) {
491 // GCC Constraint Letters
492 switch (Constraint[0]) {
494 case 'd': // Data register (equivalent to 'r')
495 case 'r': // General-purpose register
497 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
498 else if (VT == MVT::i128)
499 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
500 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
502 case 'a': // Address register
504 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
505 else if (VT == MVT::i128)
506 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
507 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
509 case 'h': // High-part register (an LLVM extension)
510 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
512 case 'f': // Floating-point register
514 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
515 else if (VT == MVT::f128)
516 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
517 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
520 if (Constraint[0] == '{') {
521 // We need to override the default register parsing for GPRs and FPRs
522 // because the interpretation depends on VT. The internal names of
523 // the registers are also different from the external names
524 // (F0D and F0S instead of F0, etc.).
525 if (Constraint[1] == 'r') {
527 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
528 SystemZMC::GR32Regs);
530 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
531 SystemZMC::GR128Regs);
532 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
533 SystemZMC::GR64Regs);
535 if (Constraint[1] == 'f') {
537 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
538 SystemZMC::FP32Regs);
540 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
541 SystemZMC::FP128Regs);
542 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
543 SystemZMC::FP64Regs);
546 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
549 void SystemZTargetLowering::
550 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
551 std::vector<SDValue> &Ops,
552 SelectionDAG &DAG) const {
553 // Only support length 1 constraints for now.
554 if (Constraint.length() == 1) {
555 switch (Constraint[0]) {
556 case 'I': // Unsigned 8-bit constant
557 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
558 if (isUInt<8>(C->getZExtValue()))
559 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
563 case 'J': // Unsigned 12-bit constant
564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
565 if (isUInt<12>(C->getZExtValue()))
566 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
570 case 'K': // Signed 16-bit constant
571 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
572 if (isInt<16>(C->getSExtValue()))
573 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
577 case 'L': // Signed 20-bit displacement (on all targets we support)
578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
579 if (isInt<20>(C->getSExtValue()))
580 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
584 case 'M': // 0x7fffffff
585 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
586 if (C->getZExtValue() == 0x7fffffff)
587 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
592 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
595 //===----------------------------------------------------------------------===//
596 // Calling conventions
597 //===----------------------------------------------------------------------===//
599 #include "SystemZGenCallingConv.inc"
601 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
602 Type *ToType) const {
603 return isTruncateFree(FromType, ToType);
606 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
607 if (!CI->isTailCall())
612 // Value is a value that has been passed to us in the location described by VA
613 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
614 // any loads onto Chain.
615 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
616 CCValAssign &VA, SDValue Chain,
618 // If the argument has been promoted from a smaller type, insert an
619 // assertion to capture this.
620 if (VA.getLocInfo() == CCValAssign::SExt)
621 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
622 DAG.getValueType(VA.getValVT()));
623 else if (VA.getLocInfo() == CCValAssign::ZExt)
624 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
625 DAG.getValueType(VA.getValVT()));
628 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
629 else if (VA.getLocInfo() == CCValAssign::Indirect)
630 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
631 MachinePointerInfo(), false, false, false, 0);
633 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
637 // Value is a value of type VA.getValVT() that we need to copy into
638 // the location described by VA. Return a copy of Value converted to
639 // VA.getValVT(). The caller is responsible for handling indirect values.
640 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
641 CCValAssign &VA, SDValue Value) {
642 switch (VA.getLocInfo()) {
643 case CCValAssign::SExt:
644 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
645 case CCValAssign::ZExt:
646 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
647 case CCValAssign::AExt:
648 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
649 case CCValAssign::Full:
652 llvm_unreachable("Unhandled getLocInfo()");
656 SDValue SystemZTargetLowering::
657 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
658 const SmallVectorImpl<ISD::InputArg> &Ins,
659 SDLoc DL, SelectionDAG &DAG,
660 SmallVectorImpl<SDValue> &InVals) const {
661 MachineFunction &MF = DAG.getMachineFunction();
662 MachineFrameInfo *MFI = MF.getFrameInfo();
663 MachineRegisterInfo &MRI = MF.getRegInfo();
664 SystemZMachineFunctionInfo *FuncInfo =
665 MF.getInfo<SystemZMachineFunctionInfo>();
666 const SystemZFrameLowering *TFL =
667 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
669 // Assign locations to all of the incoming arguments.
670 SmallVector<CCValAssign, 16> ArgLocs;
671 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
672 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
674 unsigned NumFixedGPRs = 0;
675 unsigned NumFixedFPRs = 0;
676 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
678 CCValAssign &VA = ArgLocs[I];
679 EVT LocVT = VA.getLocVT();
681 // Arguments passed in registers
682 const TargetRegisterClass *RC;
683 switch (LocVT.getSimpleVT().SimpleTy) {
685 // Integers smaller than i64 should be promoted to i64.
686 llvm_unreachable("Unexpected argument type");
689 RC = &SystemZ::GR32BitRegClass;
693 RC = &SystemZ::GR64BitRegClass;
697 RC = &SystemZ::FP32BitRegClass;
701 RC = &SystemZ::FP64BitRegClass;
705 unsigned VReg = MRI.createVirtualRegister(RC);
706 MRI.addLiveIn(VA.getLocReg(), VReg);
707 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
709 assert(VA.isMemLoc() && "Argument not register or memory");
711 // Create the frame index object for this incoming parameter.
712 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
713 VA.getLocMemOffset(), true);
715 // Create the SelectionDAG nodes corresponding to a load
716 // from this parameter. Unpromoted ints and floats are
717 // passed as right-justified 8-byte values.
718 EVT PtrVT = getPointerTy();
719 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
720 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
721 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
722 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
723 MachinePointerInfo::getFixedStack(FI),
724 false, false, false, 0);
727 // Convert the value of the argument register into the value that's
729 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
733 // Save the number of non-varargs registers for later use by va_start, etc.
734 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
735 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
737 // Likewise the address (in the form of a frame index) of where the
738 // first stack vararg would be. The 1-byte size here is arbitrary.
739 int64_t StackSize = CCInfo.getNextStackOffset();
740 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
742 // ...and a similar frame index for the caller-allocated save area
743 // that will be used to store the incoming registers.
744 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
745 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
746 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
748 // Store the FPR varargs in the reserved frame slots. (We store the
749 // GPRs as part of the prologue.)
750 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
751 SDValue MemOps[SystemZ::NumArgFPRs];
752 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
753 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
754 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
755 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
756 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
757 &SystemZ::FP64BitRegClass);
758 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
759 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
760 MachinePointerInfo::getFixedStack(FI),
764 // Join the stores, which are independent of one another.
765 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
766 &MemOps[NumFixedFPRs],
767 SystemZ::NumArgFPRs - NumFixedFPRs);
774 static bool canUseSiblingCall(CCState ArgCCInfo,
775 SmallVectorImpl<CCValAssign> &ArgLocs) {
776 // Punt if there are any indirect or stack arguments, or if the call
777 // needs the call-saved argument register R6.
778 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
779 CCValAssign &VA = ArgLocs[I];
780 if (VA.getLocInfo() == CCValAssign::Indirect)
784 unsigned Reg = VA.getLocReg();
785 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
792 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
793 SmallVectorImpl<SDValue> &InVals) const {
794 SelectionDAG &DAG = CLI.DAG;
796 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
797 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
798 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
799 SDValue Chain = CLI.Chain;
800 SDValue Callee = CLI.Callee;
801 bool &IsTailCall = CLI.IsTailCall;
802 CallingConv::ID CallConv = CLI.CallConv;
803 bool IsVarArg = CLI.IsVarArg;
804 MachineFunction &MF = DAG.getMachineFunction();
805 EVT PtrVT = getPointerTy();
807 // Analyze the operands of the call, assigning locations to each operand.
808 SmallVector<CCValAssign, 16> ArgLocs;
809 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
810 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
812 // We don't support GuaranteedTailCallOpt, only automatically-detected
814 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
817 // Get a count of how many bytes are to be pushed on the stack.
818 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
820 // Mark the start of the call.
822 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
825 // Copy argument values to their designated locations.
826 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
827 SmallVector<SDValue, 8> MemOpChains;
829 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
830 CCValAssign &VA = ArgLocs[I];
831 SDValue ArgValue = OutVals[I];
833 if (VA.getLocInfo() == CCValAssign::Indirect) {
834 // Store the argument in a stack slot and pass its address.
835 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
836 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
837 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
838 MachinePointerInfo::getFixedStack(FI),
840 ArgValue = SpillSlot;
842 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
845 // Queue up the argument copies and emit them at the end.
846 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
848 assert(VA.isMemLoc() && "Argument not register or memory");
850 // Work out the address of the stack slot. Unpromoted ints and
851 // floats are passed as right-justified 8-byte values.
852 if (!StackPtr.getNode())
853 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
854 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
855 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
857 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
858 DAG.getIntPtrConstant(Offset));
861 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
862 MachinePointerInfo(),
867 // Join the stores, which are independent of one another.
868 if (!MemOpChains.empty())
869 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
870 &MemOpChains[0], MemOpChains.size());
872 // Accept direct calls by converting symbolic call addresses to the
873 // associated Target* opcodes. Force %r1 to be used for indirect
876 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
877 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
878 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
879 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
880 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
881 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
882 } else if (IsTailCall) {
883 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
884 Glue = Chain.getValue(1);
885 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
888 // Build a sequence of copy-to-reg nodes, chained and glued together.
889 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
890 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
891 RegsToPass[I].second, Glue);
892 Glue = Chain.getValue(1);
895 // The first call operand is the chain and the second is the target address.
896 SmallVector<SDValue, 8> Ops;
897 Ops.push_back(Chain);
898 Ops.push_back(Callee);
900 // Add argument registers to the end of the list so that they are
901 // known live into the call.
902 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
903 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
904 RegsToPass[I].second.getValueType()));
906 // Glue the call to the argument copies, if any.
911 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
913 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
914 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
915 Glue = Chain.getValue(1);
917 // Mark the end of the call, which is glued to the call itself.
918 Chain = DAG.getCALLSEQ_END(Chain,
919 DAG.getConstant(NumBytes, PtrVT, true),
920 DAG.getConstant(0, PtrVT, true),
922 Glue = Chain.getValue(1);
924 // Assign locations to each value returned by this call.
925 SmallVector<CCValAssign, 16> RetLocs;
926 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
927 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
929 // Copy all of the result registers out of their specified physreg.
930 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
931 CCValAssign &VA = RetLocs[I];
933 // Copy the value out, gluing the copy to the end of the call sequence.
934 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
935 VA.getLocVT(), Glue);
936 Chain = RetValue.getValue(1);
937 Glue = RetValue.getValue(2);
939 // Convert the value of the return register into the value that's
941 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
948 SystemZTargetLowering::LowerReturn(SDValue Chain,
949 CallingConv::ID CallConv, bool IsVarArg,
950 const SmallVectorImpl<ISD::OutputArg> &Outs,
951 const SmallVectorImpl<SDValue> &OutVals,
952 SDLoc DL, SelectionDAG &DAG) const {
953 MachineFunction &MF = DAG.getMachineFunction();
955 // Assign locations to each returned value.
956 SmallVector<CCValAssign, 16> RetLocs;
957 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
958 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
960 // Quick exit for void returns
962 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
964 // Copy the result values into the output registers.
966 SmallVector<SDValue, 4> RetOps;
967 RetOps.push_back(Chain);
968 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
969 CCValAssign &VA = RetLocs[I];
970 SDValue RetValue = OutVals[I];
972 // Make the return register live on exit.
973 assert(VA.isRegLoc() && "Can only return in registers!");
975 // Promote the value as required.
976 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
978 // Chain and glue the copies together.
979 unsigned Reg = VA.getLocReg();
980 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
981 Glue = Chain.getValue(1);
982 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
985 // Update chain and glue.
988 RetOps.push_back(Glue);
990 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
991 RetOps.data(), RetOps.size());
994 SDValue SystemZTargetLowering::
995 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
996 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
999 // CC is a comparison that will be implemented using an integer or
1000 // floating-point comparison. Return the condition code mask for
1001 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1002 // unsigned comparisons and clear for signed ones. In the floating-point
1003 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1004 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1006 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1007 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1008 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1012 llvm_unreachable("Invalid integer condition!");
1021 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1022 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1027 // Return a sequence for getting a 1 from an IPM result when CC has a
1028 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1029 // The handling of CC values outside CCValid doesn't matter.
1030 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1031 // Deal with cases where the result can be taken directly from a bit
1032 // of the IPM result.
1033 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1034 return IPMConversion(0, 0, SystemZ::IPM_CC);
1035 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1036 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1038 // Deal with cases where we can add a value to force the sign bit
1039 // to contain the right value. Putting the bit in 31 means we can
1040 // use SRL rather than RISBG(L), and also makes it easier to get a
1041 // 0/-1 value, so it has priority over the other tests below.
1043 // These sequences rely on the fact that the upper two bits of the
1044 // IPM result are zero.
1045 uint64_t TopBit = uint64_t(1) << 31;
1046 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1047 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1048 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1049 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1050 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1052 | SystemZ::CCMASK_2)))
1053 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1054 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1055 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1056 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1058 | SystemZ::CCMASK_3)))
1059 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1061 // Next try inverting the value and testing a bit. 0/1 could be
1062 // handled this way too, but we dealt with that case above.
1063 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1064 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1066 // Handle cases where adding a value forces a non-sign bit to contain
1068 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1069 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1070 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1071 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1073 // The remaing cases are 1, 2, 0/1/3 and 0/2/3. All these are
1074 // can be done by inverting the low CC bit and applying one of the
1075 // sign-based extractions above.
1076 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1077 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1078 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1079 return IPMConversion(1 << SystemZ::IPM_CC,
1080 TopBit - (3 << SystemZ::IPM_CC), 31);
1081 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1083 | SystemZ::CCMASK_3)))
1084 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1085 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1087 | SystemZ::CCMASK_3)))
1088 return IPMConversion(1 << SystemZ::IPM_CC,
1089 TopBit - (1 << SystemZ::IPM_CC), 31);
1091 llvm_unreachable("Unexpected CC combination");
1094 // If C can be converted to a comparison against zero, adjust the operands
1096 static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
1097 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1100 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1104 int64_t Value = ConstOp1->getSExtValue();
1105 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1106 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1107 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1108 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1109 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1110 C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
1114 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1115 // adjust the operands as necessary.
1116 static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
1117 // For us to make any changes, it must a comparison between a single-use
1118 // load and a constant.
1119 if (!C.Op0.hasOneUse() ||
1120 C.Op0.getOpcode() != ISD::LOAD ||
1121 C.Op1.getOpcode() != ISD::Constant)
1124 // We must have an 8- or 16-bit load.
1125 LoadSDNode *Load = cast<LoadSDNode>(C.Op0);
1126 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1127 if (NumBits != 8 && NumBits != 16)
1130 // The load must be an extending one and the constant must be within the
1131 // range of the unextended value.
1132 ConstantSDNode *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1133 uint64_t Value = ConstOp1->getZExtValue();
1134 uint64_t Mask = (1 << NumBits) - 1;
1135 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1136 // Make sure that ConstOp1 is in range of C.Op0.
1137 int64_t SignedValue = ConstOp1->getSExtValue();
1138 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1140 if (C.ICmpType != SystemZICMP::SignedOnly) {
1141 // Unsigned comparison between two sign-extended values is equivalent
1142 // to unsigned comparison between two zero-extended values.
1144 } else if (NumBits == 8) {
1145 // Try to treat the comparison as unsigned, so that we can use CLI.
1146 // Adjust CCMask and Value as necessary.
1147 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1148 // Test whether the high bit of the byte is set.
1149 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1150 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1151 // Test whether the high bit of the byte is clear.
1152 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1154 // No instruction exists for this combination.
1156 C.ICmpType = SystemZICMP::UnsignedOnly;
1158 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1161 assert(C.ICmpType == SystemZICMP::Any &&
1162 "Signedness shouldn't matter here.");
1166 // Make sure that the first operand is an i32 of the right extension type.
1167 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1170 if (C.Op0.getValueType() != MVT::i32 ||
1171 Load->getExtensionType() != ExtType)
1172 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1173 Load->getChain(), Load->getBasePtr(),
1174 Load->getPointerInfo(), Load->getMemoryVT(),
1175 Load->isVolatile(), Load->isNonTemporal(),
1176 Load->getAlignment());
1178 // Make sure that the second operand is an i32 with the right value.
1179 if (C.Op1.getValueType() != MVT::i32 ||
1180 Value != ConstOp1->getZExtValue())
1181 C.Op1 = DAG.getConstant(Value, MVT::i32);
1184 // Return true if Op is either an unextended load, or a load suitable
1185 // for integer register-memory comparisons of type ICmpType.
1186 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1187 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op.getNode());
1189 // There are no instructions to compare a register with a memory byte.
1190 if (Load->getMemoryVT() == MVT::i8)
1192 // Otherwise decide on extension type.
1193 switch (Load->getExtensionType()) {
1194 case ISD::NON_EXTLOAD:
1197 return ICmpType != SystemZICMP::UnsignedOnly;
1199 return ICmpType != SystemZICMP::SignedOnly;
1207 // Return true if it is better to swap the operands of C.
1208 static bool shouldSwapCmpOperands(const Comparison &C) {
1209 // Leave f128 comparisons alone, since they have no memory forms.
1210 if (C.Op0.getValueType() == MVT::f128)
1213 // Always keep a floating-point constant second, since comparisons with
1214 // zero can use LOAD TEST and comparisons with other constants make a
1215 // natural memory operand.
1216 if (isa<ConstantFPSDNode>(C.Op1))
1219 // Never swap comparisons with zero since there are many ways to optimize
1221 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1222 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1225 // Also keep natural memory operands second if the loaded value is
1226 // only used here. Several comparisons have memory forms.
1227 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1230 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1231 // In that case we generally prefer the memory to be second.
1232 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1233 // The only exceptions are when the second operand is a constant and
1234 // we can use things like CHHSI.
1237 // The unsigned memory-immediate instructions can handle 16-bit
1238 // unsigned integers.
1239 if (C.ICmpType != SystemZICMP::SignedOnly &&
1240 isUInt<16>(ConstOp1->getZExtValue()))
1242 // The signed memory-immediate instructions can handle 16-bit
1244 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1245 isInt<16>(ConstOp1->getSExtValue()))
1250 // Try to promote the use of CGFR and CLGFR.
1251 unsigned Opcode0 = C.Op0.getOpcode();
1252 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1254 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1256 if (C.ICmpType != SystemZICMP::SignedOnly &&
1257 Opcode0 == ISD::AND &&
1258 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1259 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1265 // Return a version of comparison CC mask CCMask in which the LT and GT
1266 // actions are swapped.
1267 static unsigned reverseCCMask(unsigned CCMask) {
1268 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1269 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1270 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1271 (CCMask & SystemZ::CCMASK_CMP_UO));
1274 // Check whether C tests for equality between X and Y and whether X - Y
1275 // or Y - X is also computed. In that case it's better to compare the
1276 // result of the subtraction against zero.
1277 static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
1278 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1279 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1280 for (SDNode::use_iterator I = C.Op0->use_begin(), E = C.Op0->use_end();
1283 if (N->getOpcode() == ISD::SUB &&
1284 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1285 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1286 C.Op0 = SDValue(N, 0);
1287 C.Op1 = DAG.getConstant(0, N->getValueType(0));
1294 // Check whether C compares a floating-point value with zero and if that
1295 // floating-point value is also negated. In this case we can use the
1296 // negation to set CC, so avoiding separate LOAD AND TEST and
1297 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1298 static void adjustForFNeg(Comparison &C) {
1299 ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1300 if (C1 && C1->isZero()) {
1301 for (SDNode::use_iterator I = C.Op0->use_begin(), E = C.Op0->use_end();
1304 if (N->getOpcode() == ISD::FNEG) {
1305 C.Op0 = SDValue(N, 0);
1306 C.CCMask = reverseCCMask(C.CCMask);
1313 // Check whether C compares (shl X, 32) with 0 and whether X is
1314 // also sign-extended. In that case it is better to test the result
1315 // of the sign extension using LTGFR.
1317 // This case is important because InstCombine transforms a comparison
1318 // with (sext (trunc X)) into a comparison with (shl X, 32).
1319 static void adjustForLTGFR(Comparison &C) {
1320 // Check for a comparison between (shl X, 32) and 0.
1321 if (C.Op0.getOpcode() == ISD::SHL &&
1322 C.Op0.getValueType() == MVT::i64 &&
1323 C.Op1.getOpcode() == ISD::Constant &&
1324 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1325 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1326 if (C1 && C1->getZExtValue() == 32) {
1327 SDValue ShlOp0 = C.Op0.getOperand(0);
1328 // See whether X has any SIGN_EXTEND_INREG uses.
1329 for (SDNode::use_iterator I = ShlOp0->use_begin(), E = ShlOp0->use_end();
1332 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1333 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1334 C.Op0 = SDValue(N, 0);
1342 // If C compares the truncation of an extending load, try to compare
1343 // the untruncated value instead. This exposes more opportunities to
1345 static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
1346 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1347 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1348 C.Op1.getOpcode() == ISD::Constant &&
1349 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1350 LoadSDNode *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1351 if (L->getMemoryVT().getStoreSizeInBits()
1352 <= C.Op0.getValueType().getSizeInBits()) {
1353 unsigned Type = L->getExtensionType();
1354 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1355 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1356 C.Op0 = C.Op0.getOperand(0);
1357 C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
1363 // Return true if shift operation N has an in-range constant shift value.
1364 // Store it in ShiftVal if so.
1365 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1366 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1370 uint64_t Amount = Shift->getZExtValue();
1371 if (Amount >= N.getValueType().getSizeInBits())
1378 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1379 // instruction and whether the CC value is descriptive enough to handle
1380 // a comparison of type Opcode between the AND result and CmpVal.
1381 // CCMask says which comparison result is being tested and BitSize is
1382 // the number of bits in the operands. If TEST UNDER MASK can be used,
1383 // return the corresponding CC mask, otherwise return 0.
1384 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1385 uint64_t Mask, uint64_t CmpVal,
1386 unsigned ICmpType) {
1387 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1389 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1390 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1391 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1394 // Work out the masks for the lowest and highest bits.
1395 unsigned HighShift = 63 - countLeadingZeros(Mask);
1396 uint64_t High = uint64_t(1) << HighShift;
1397 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1399 // Signed ordered comparisons are effectively unsigned if the sign
1401 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1403 // Check for equality comparisons with 0, or the equivalent.
1405 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1406 return SystemZ::CCMASK_TM_ALL_0;
1407 if (CCMask == SystemZ::CCMASK_CMP_NE)
1408 return SystemZ::CCMASK_TM_SOME_1;
1410 if (EffectivelyUnsigned && CmpVal <= Low) {
1411 if (CCMask == SystemZ::CCMASK_CMP_LT)
1412 return SystemZ::CCMASK_TM_ALL_0;
1413 if (CCMask == SystemZ::CCMASK_CMP_GE)
1414 return SystemZ::CCMASK_TM_SOME_1;
1416 if (EffectivelyUnsigned && CmpVal < Low) {
1417 if (CCMask == SystemZ::CCMASK_CMP_LE)
1418 return SystemZ::CCMASK_TM_ALL_0;
1419 if (CCMask == SystemZ::CCMASK_CMP_GT)
1420 return SystemZ::CCMASK_TM_SOME_1;
1423 // Check for equality comparisons with the mask, or the equivalent.
1424 if (CmpVal == Mask) {
1425 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1426 return SystemZ::CCMASK_TM_ALL_1;
1427 if (CCMask == SystemZ::CCMASK_CMP_NE)
1428 return SystemZ::CCMASK_TM_SOME_0;
1430 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1431 if (CCMask == SystemZ::CCMASK_CMP_GT)
1432 return SystemZ::CCMASK_TM_ALL_1;
1433 if (CCMask == SystemZ::CCMASK_CMP_LE)
1434 return SystemZ::CCMASK_TM_SOME_0;
1436 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1437 if (CCMask == SystemZ::CCMASK_CMP_GE)
1438 return SystemZ::CCMASK_TM_ALL_1;
1439 if (CCMask == SystemZ::CCMASK_CMP_LT)
1440 return SystemZ::CCMASK_TM_SOME_0;
1443 // Check for ordered comparisons with the top bit.
1444 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1445 if (CCMask == SystemZ::CCMASK_CMP_LE)
1446 return SystemZ::CCMASK_TM_MSB_0;
1447 if (CCMask == SystemZ::CCMASK_CMP_GT)
1448 return SystemZ::CCMASK_TM_MSB_1;
1450 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1451 if (CCMask == SystemZ::CCMASK_CMP_LT)
1452 return SystemZ::CCMASK_TM_MSB_0;
1453 if (CCMask == SystemZ::CCMASK_CMP_GE)
1454 return SystemZ::CCMASK_TM_MSB_1;
1457 // If there are just two bits, we can do equality checks for Low and High
1459 if (Mask == Low + High) {
1460 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1461 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1462 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1463 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1464 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1465 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1466 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1467 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1470 // Looks like we've exhausted our options.
1474 // See whether C can be implemented as a TEST UNDER MASK instruction.
1475 // Update the arguments with the TM version if so.
1476 static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
1477 // Check that we have a comparison with a constant.
1478 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1481 uint64_t CmpVal = ConstOp1->getZExtValue();
1483 // Check whether the nonconstant input is an AND with a constant mask.
1486 ConstantSDNode *Mask = 0;
1487 if (C.Op0.getOpcode() == ISD::AND) {
1488 NewC.Op0 = C.Op0.getOperand(0);
1489 NewC.Op1 = C.Op0.getOperand(1);
1490 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
1493 MaskVal = Mask->getZExtValue();
1495 // There is no instruction to compare with a 64-bit immediate
1496 // so use TMHH instead if possible. We need an unsigned ordered
1497 // comparison with an i64 immediate.
1498 if (NewC.Op0.getValueType() != MVT::i64 ||
1499 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
1500 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
1501 NewC.ICmpType == SystemZICMP::SignedOnly)
1503 // Convert LE and GT comparisons into LT and GE.
1504 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
1505 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
1506 if (CmpVal == uint64_t(-1))
1509 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1511 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1512 // be masked off without changing the result.
1513 MaskVal = -(CmpVal & -CmpVal);
1514 NewC.ICmpType = SystemZICMP::UnsignedOnly;
1517 // Check whether the combination of mask, comparison value and comparison
1518 // type are suitable.
1519 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1520 unsigned NewCCMask, ShiftVal;
1521 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1522 NewC.Op0.getOpcode() == ISD::SHL &&
1523 isSimpleShift(NewC.Op0, ShiftVal) &&
1524 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1525 MaskVal >> ShiftVal,
1527 SystemZICMP::Any))) {
1528 NewC.Op0 = NewC.Op0.getOperand(0);
1529 MaskVal >>= ShiftVal;
1530 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1531 NewC.Op0.getOpcode() == ISD::SRL &&
1532 isSimpleShift(NewC.Op0, ShiftVal) &&
1533 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1534 MaskVal << ShiftVal,
1536 SystemZICMP::UnsignedOnly))) {
1537 NewC.Op0 = NewC.Op0.getOperand(0);
1538 MaskVal <<= ShiftVal;
1540 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
1546 // Go ahead and make the change.
1547 C.Opcode = SystemZISD::TM;
1549 if (Mask && Mask->getZExtValue() == MaskVal)
1550 C.Op1 = SDValue(Mask, 0);
1552 C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
1553 C.CCValid = SystemZ::CCMASK_TM;
1554 C.CCMask = NewCCMask;
1557 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
1558 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1559 ISD::CondCode Cond) {
1560 Comparison C(CmpOp0, CmpOp1);
1561 C.CCMask = CCMaskForCondCode(Cond);
1562 if (C.Op0.getValueType().isFloatingPoint()) {
1563 C.CCValid = SystemZ::CCMASK_FCMP;
1564 C.Opcode = SystemZISD::FCMP;
1567 C.CCValid = SystemZ::CCMASK_ICMP;
1568 C.Opcode = SystemZISD::ICMP;
1569 // Choose the type of comparison. Equality and inequality tests can
1570 // use either signed or unsigned comparisons. The choice also doesn't
1571 // matter if both sign bits are known to be clear. In those cases we
1572 // want to give the main isel code the freedom to choose whichever
1574 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1575 C.CCMask == SystemZ::CCMASK_CMP_NE ||
1576 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
1577 C.ICmpType = SystemZICMP::Any;
1578 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
1579 C.ICmpType = SystemZICMP::UnsignedOnly;
1581 C.ICmpType = SystemZICMP::SignedOnly;
1582 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
1583 adjustZeroCmp(DAG, C);
1584 adjustSubwordCmp(DAG, C);
1585 adjustForSubtraction(DAG, C);
1587 adjustICmpTruncate(DAG, C);
1590 if (shouldSwapCmpOperands(C)) {
1591 std::swap(C.Op0, C.Op1);
1592 C.CCMask = reverseCCMask(C.CCMask);
1595 adjustForTestUnderMask(DAG, C);
1599 // Emit the comparison instruction described by C.
1600 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1601 if (C.Opcode == SystemZISD::ICMP)
1602 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
1603 DAG.getConstant(C.ICmpType, MVT::i32));
1604 if (C.Opcode == SystemZISD::TM) {
1605 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
1606 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
1607 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
1608 DAG.getConstant(RegisterOnly, MVT::i32));
1610 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
1613 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1614 // 64 bits. Extend is the extension type to use. Store the high part
1615 // in Hi and the low part in Lo.
1616 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1617 unsigned Extend, SDValue Op0, SDValue Op1,
1618 SDValue &Hi, SDValue &Lo) {
1619 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1620 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1621 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1622 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1623 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1624 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1627 // Lower a binary operation that produces two VT results, one in each
1628 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1629 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1630 // on the extended Op0 and (unextended) Op1. Store the even register result
1631 // in Even and the odd register result in Odd.
1632 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1633 unsigned Extend, unsigned Opcode,
1634 SDValue Op0, SDValue Op1,
1635 SDValue &Even, SDValue &Odd) {
1636 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1637 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1638 SDValue(In128, 0), Op1);
1639 bool Is32Bit = is32Bit(VT);
1640 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
1641 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
1644 // Return an i32 value that is 1 if the CC value produced by Glue is
1645 // in the mask CCMask and 0 otherwise. CC is known to have a value
1646 // in CCValid, so other values can be ignored.
1647 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
1648 unsigned CCValid, unsigned CCMask) {
1649 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
1650 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
1652 if (Conversion.XORValue)
1653 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
1654 DAG.getConstant(Conversion.XORValue, MVT::i32));
1656 if (Conversion.AddValue)
1657 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
1658 DAG.getConstant(Conversion.AddValue, MVT::i32));
1660 // The SHR/AND sequence should get optimized to an RISBG.
1661 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
1662 DAG.getConstant(Conversion.Bit, MVT::i32));
1663 if (Conversion.Bit != 31)
1664 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
1665 DAG.getConstant(1, MVT::i32));
1669 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
1670 SelectionDAG &DAG) const {
1671 SDValue CmpOp0 = Op.getOperand(0);
1672 SDValue CmpOp1 = Op.getOperand(1);
1673 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1676 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1677 SDValue Glue = emitCmp(DAG, DL, C);
1678 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1681 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1682 SDValue Chain = Op.getOperand(0);
1683 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1684 SDValue CmpOp0 = Op.getOperand(2);
1685 SDValue CmpOp1 = Op.getOperand(3);
1686 SDValue Dest = Op.getOperand(4);
1689 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1690 SDValue Glue = emitCmp(DAG, DL, C);
1691 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1692 Chain, DAG.getConstant(C.CCValid, MVT::i32),
1693 DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
1696 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
1697 // allowing Pos and Neg to be wider than CmpOp.
1698 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
1699 return (Neg.getOpcode() == ISD::SUB &&
1700 Neg.getOperand(0).getOpcode() == ISD::Constant &&
1701 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
1702 Neg.getOperand(1) == Pos &&
1704 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
1705 Pos.getOperand(0) == CmpOp)));
1708 // Return the absolute or negative absolute of Op; IsNegative decides which.
1709 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
1711 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
1713 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
1714 DAG.getConstant(0, Op.getValueType()), Op);
1718 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1719 SelectionDAG &DAG) const {
1720 SDValue CmpOp0 = Op.getOperand(0);
1721 SDValue CmpOp1 = Op.getOperand(1);
1722 SDValue TrueOp = Op.getOperand(2);
1723 SDValue FalseOp = Op.getOperand(3);
1724 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1727 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1729 // Check for absolute and negative-absolute selections, including those
1730 // where the comparison value is sign-extended (for LPGFR and LNGFR).
1731 // This check supplements the one in DAGCombiner.
1732 if (C.Opcode == SystemZISD::ICMP &&
1733 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
1734 C.CCMask != SystemZ::CCMASK_CMP_NE &&
1735 C.Op1.getOpcode() == ISD::Constant &&
1736 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1737 if (isAbsolute(C.Op0, TrueOp, FalseOp))
1738 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
1739 if (isAbsolute(C.Op0, FalseOp, TrueOp))
1740 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
1743 SDValue Glue = emitCmp(DAG, DL, C);
1745 // Special case for handling -1/0 results. The shifts we use here
1746 // should get optimized with the IPM conversion sequence.
1747 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
1748 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
1749 if (TrueC && FalseC) {
1750 int64_t TrueVal = TrueC->getSExtValue();
1751 int64_t FalseVal = FalseC->getSExtValue();
1752 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
1753 // Invert the condition if we want -1 on false.
1755 C.CCMask ^= C.CCValid;
1756 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1757 EVT VT = Op.getValueType();
1758 // Extend the result to VT. Upper bits are ignored.
1760 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
1761 // Sign-extend from the low bit.
1762 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
1763 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
1764 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
1768 SmallVector<SDValue, 5> Ops;
1769 Ops.push_back(TrueOp);
1770 Ops.push_back(FalseOp);
1771 Ops.push_back(DAG.getConstant(C.CCValid, MVT::i32));
1772 Ops.push_back(DAG.getConstant(C.CCMask, MVT::i32));
1773 Ops.push_back(Glue);
1775 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1776 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1779 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1780 SelectionDAG &DAG) const {
1782 const GlobalValue *GV = Node->getGlobal();
1783 int64_t Offset = Node->getOffset();
1784 EVT PtrVT = getPointerTy();
1785 Reloc::Model RM = TM.getRelocationModel();
1786 CodeModel::Model CM = TM.getCodeModel();
1789 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1790 // Assign anchors at 1<<12 byte boundaries.
1791 uint64_t Anchor = Offset & ~uint64_t(0xfff);
1792 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
1793 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1795 // The offset can be folded into the address if it is aligned to a halfword.
1797 if (Offset != 0 && (Offset & 1) == 0) {
1798 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
1799 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
1803 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1804 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1805 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1806 MachinePointerInfo::getGOT(), false, false, false, 0);
1809 // If there was a non-zero offset that we didn't fold, create an explicit
1812 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1813 DAG.getConstant(Offset, PtrVT));
1818 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1819 SelectionDAG &DAG) const {
1821 const GlobalValue *GV = Node->getGlobal();
1822 EVT PtrVT = getPointerTy();
1823 TLSModel::Model model = TM.getTLSModel(GV);
1825 if (model != TLSModel::LocalExec)
1826 llvm_unreachable("only local-exec TLS mode supported");
1828 // The high part of the thread pointer is in access register 0.
1829 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1830 DAG.getConstant(0, MVT::i32));
1831 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1833 // The low part of the thread pointer is in access register 1.
1834 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1835 DAG.getConstant(1, MVT::i32));
1836 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1838 // Merge them into a single 64-bit address.
1839 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1840 DAG.getConstant(32, PtrVT));
1841 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1843 // Get the offset of GA from the thread pointer.
1844 SystemZConstantPoolValue *CPV =
1845 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1847 // Force the offset into the constant pool and load it from there.
1848 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1849 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1850 CPAddr, MachinePointerInfo::getConstantPool(),
1851 false, false, false, 0);
1853 // Add the base and offset together.
1854 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1857 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1858 SelectionDAG &DAG) const {
1860 const BlockAddress *BA = Node->getBlockAddress();
1861 int64_t Offset = Node->getOffset();
1862 EVT PtrVT = getPointerTy();
1864 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1865 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1869 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1870 SelectionDAG &DAG) const {
1872 EVT PtrVT = getPointerTy();
1873 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1875 // Use LARL to load the address of the table.
1876 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1879 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1880 SelectionDAG &DAG) const {
1882 EVT PtrVT = getPointerTy();
1885 if (CP->isMachineConstantPoolEntry())
1886 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1887 CP->getAlignment());
1889 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1890 CP->getAlignment(), CP->getOffset());
1892 // Use LARL to load the address of the constant pool entry.
1893 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1896 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1897 SelectionDAG &DAG) const {
1899 SDValue In = Op.getOperand(0);
1900 EVT InVT = In.getValueType();
1901 EVT ResVT = Op.getValueType();
1903 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1905 if (Subtarget.hasHighWord()) {
1906 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
1908 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1909 MVT::i64, SDValue(U64, 0), In);
1911 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1912 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
1913 DAG.getConstant(32, MVT::i64));
1915 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
1916 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
1917 DL, MVT::f32, Out64);
1919 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1920 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1921 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1922 MVT::f64, SDValue(U64, 0), In);
1923 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
1924 if (Subtarget.hasHighWord())
1925 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
1927 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
1928 DAG.getConstant(32, MVT::i64));
1929 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1931 llvm_unreachable("Unexpected bitcast combination");
1934 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1935 SelectionDAG &DAG) const {
1936 MachineFunction &MF = DAG.getMachineFunction();
1937 SystemZMachineFunctionInfo *FuncInfo =
1938 MF.getInfo<SystemZMachineFunctionInfo>();
1939 EVT PtrVT = getPointerTy();
1941 SDValue Chain = Op.getOperand(0);
1942 SDValue Addr = Op.getOperand(1);
1943 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1946 // The initial values of each field.
1947 const unsigned NumFields = 4;
1948 SDValue Fields[NumFields] = {
1949 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1950 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1951 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1952 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1955 // Store each field into its respective slot.
1956 SDValue MemOps[NumFields];
1957 unsigned Offset = 0;
1958 for (unsigned I = 0; I < NumFields; ++I) {
1959 SDValue FieldAddr = Addr;
1961 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1962 DAG.getIntPtrConstant(Offset));
1963 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1964 MachinePointerInfo(SV, Offset),
1968 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1971 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1972 SelectionDAG &DAG) const {
1973 SDValue Chain = Op.getOperand(0);
1974 SDValue DstPtr = Op.getOperand(1);
1975 SDValue SrcPtr = Op.getOperand(2);
1976 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1977 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1980 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1981 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1982 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1985 SDValue SystemZTargetLowering::
1986 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1987 SDValue Chain = Op.getOperand(0);
1988 SDValue Size = Op.getOperand(1);
1991 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1993 // Get a reference to the stack pointer.
1994 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
1996 // Get the new stack pointer value.
1997 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
1999 // Copy the new stack pointer back.
2000 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2002 // The allocated data lives above the 160 bytes allocated for the standard
2003 // frame, plus any outgoing stack arguments. We don't know how much that
2004 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2005 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2006 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2008 SDValue Ops[2] = { Result, Chain };
2009 return DAG.getMergeValues(Ops, 2, DL);
2012 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2013 SelectionDAG &DAG) const {
2014 EVT VT = Op.getValueType();
2018 // Just do a normal 64-bit multiplication and extract the results.
2019 // We define this so that it can be used for constant division.
2020 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2021 Op.getOperand(1), Ops[1], Ops[0]);
2023 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2025 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2027 // but using the fact that the upper halves are either all zeros
2030 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2032 // and grouping the right terms together since they are quicker than the
2035 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2036 SDValue C63 = DAG.getConstant(63, MVT::i64);
2037 SDValue LL = Op.getOperand(0);
2038 SDValue RL = Op.getOperand(1);
2039 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2040 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2041 // UMUL_LOHI64 returns the low result in the odd register and the high
2042 // result in the even register. SMUL_LOHI is defined to return the
2043 // low half first, so the results are in reverse order.
2044 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2045 LL, RL, Ops[1], Ops[0]);
2046 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2047 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2048 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2049 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2051 return DAG.getMergeValues(Ops, 2, DL);
2054 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2055 SelectionDAG &DAG) const {
2056 EVT VT = Op.getValueType();
2060 // Just do a normal 64-bit multiplication and extract the results.
2061 // We define this so that it can be used for constant division.
2062 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2063 Op.getOperand(1), Ops[1], Ops[0]);
2065 // UMUL_LOHI64 returns the low result in the odd register and the high
2066 // result in the even register. UMUL_LOHI is defined to return the
2067 // low half first, so the results are in reverse order.
2068 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2069 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2070 return DAG.getMergeValues(Ops, 2, DL);
2073 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2074 SelectionDAG &DAG) const {
2075 SDValue Op0 = Op.getOperand(0);
2076 SDValue Op1 = Op.getOperand(1);
2077 EVT VT = Op.getValueType();
2081 // We use DSGF for 32-bit division.
2083 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2084 Opcode = SystemZISD::SDIVREM32;
2085 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
2086 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
2087 Opcode = SystemZISD::SDIVREM32;
2089 Opcode = SystemZISD::SDIVREM64;
2091 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2092 // input is "don't care". The instruction returns the remainder in
2093 // the even register and the quotient in the odd register.
2095 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
2096 Op0, Op1, Ops[1], Ops[0]);
2097 return DAG.getMergeValues(Ops, 2, DL);
2100 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
2101 SelectionDAG &DAG) const {
2102 EVT VT = Op.getValueType();
2105 // DL(G) uses a double-width dividend, so we need to clear the even
2106 // register in the GR128 input. The instruction returns the remainder
2107 // in the even register and the quotient in the odd register.
2110 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
2111 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2113 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
2114 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2115 return DAG.getMergeValues(Ops, 2, DL);
2118 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
2119 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
2121 // Get the known-zero masks for each operand.
2122 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
2123 APInt KnownZero[2], KnownOne[2];
2124 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
2125 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
2127 // See if the upper 32 bits of one operand and the lower 32 bits of the
2128 // other are known zero. They are the low and high operands respectively.
2129 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
2130 KnownZero[1].getZExtValue() };
2132 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2134 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2139 SDValue LowOp = Ops[Low];
2140 SDValue HighOp = Ops[High];
2142 // If the high part is a constant, we're better off using IILH.
2143 if (HighOp.getOpcode() == ISD::Constant)
2146 // If the low part is a constant that is outside the range of LHI,
2147 // then we're better off using IILF.
2148 if (LowOp.getOpcode() == ISD::Constant) {
2149 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2150 if (!isInt<16>(Value))
2154 // Check whether the high part is an AND that doesn't change the
2155 // high 32 bits and just masks out low bits. We can skip it if so.
2156 if (HighOp.getOpcode() == ISD::AND &&
2157 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
2158 SDValue HighOp0 = HighOp.getOperand(0);
2159 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
2160 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
2164 // Take advantage of the fact that all GR32 operations only change the
2165 // low 32 bits by truncating Low to an i32 and inserting it directly
2166 // using a subreg. The interesting cases are those where the truncation
2169 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2170 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2171 MVT::i64, HighOp, Low32);
2174 // Op is an atomic load. Lower it into a normal volatile load.
2175 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
2176 SelectionDAG &DAG) const {
2177 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2178 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
2179 Node->getChain(), Node->getBasePtr(),
2180 Node->getMemoryVT(), Node->getMemOperand());
2183 // Op is an atomic store. Lower it into a normal volatile store followed
2184 // by a serialization.
2185 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
2186 SelectionDAG &DAG) const {
2187 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2188 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
2189 Node->getBasePtr(), Node->getMemoryVT(),
2190 Node->getMemOperand());
2191 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
2195 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
2196 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
2197 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
2199 unsigned Opcode) const {
2200 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2202 // 32-bit operations need no code outside the main loop.
2203 EVT NarrowVT = Node->getMemoryVT();
2204 EVT WideVT = MVT::i32;
2205 if (NarrowVT == WideVT)
2208 int64_t BitSize = NarrowVT.getSizeInBits();
2209 SDValue ChainIn = Node->getChain();
2210 SDValue Addr = Node->getBasePtr();
2211 SDValue Src2 = Node->getVal();
2212 MachineMemOperand *MMO = Node->getMemOperand();
2214 EVT PtrVT = Addr.getValueType();
2216 // Convert atomic subtracts of constants into additions.
2217 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
2218 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
2219 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
2220 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
2223 // Get the address of the containing word.
2224 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2225 DAG.getConstant(-4, PtrVT));
2227 // Get the number of bits that the word must be rotated left in order
2228 // to bring the field to the top bits of a GR32.
2229 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2230 DAG.getConstant(3, PtrVT));
2231 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2233 // Get the complementing shift amount, for rotating a field in the top
2234 // bits back to its proper position.
2235 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2236 DAG.getConstant(0, WideVT), BitShift);
2238 // Extend the source operand to 32 bits and prepare it for the inner loop.
2239 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
2240 // operations require the source to be shifted in advance. (This shift
2241 // can be folded if the source is constant.) For AND and NAND, the lower
2242 // bits must be set, while for other opcodes they should be left clear.
2243 if (Opcode != SystemZISD::ATOMIC_SWAPW)
2244 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
2245 DAG.getConstant(32 - BitSize, WideVT));
2246 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
2247 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
2248 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
2249 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
2251 // Construct the ATOMIC_LOADW_* node.
2252 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2253 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
2254 DAG.getConstant(BitSize, WideVT) };
2255 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
2256 array_lengthof(Ops),
2259 // Rotate the result of the final CS so that the field is in the lower
2260 // bits of a GR32, then truncate it.
2261 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
2262 DAG.getConstant(BitSize, WideVT));
2263 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
2265 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
2266 return DAG.getMergeValues(RetOps, 2, DL);
2269 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
2270 // into a fullword ATOMIC_CMP_SWAPW operation.
2271 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
2272 SelectionDAG &DAG) const {
2273 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2275 // We have native support for 32-bit compare and swap.
2276 EVT NarrowVT = Node->getMemoryVT();
2277 EVT WideVT = MVT::i32;
2278 if (NarrowVT == WideVT)
2281 int64_t BitSize = NarrowVT.getSizeInBits();
2282 SDValue ChainIn = Node->getOperand(0);
2283 SDValue Addr = Node->getOperand(1);
2284 SDValue CmpVal = Node->getOperand(2);
2285 SDValue SwapVal = Node->getOperand(3);
2286 MachineMemOperand *MMO = Node->getMemOperand();
2288 EVT PtrVT = Addr.getValueType();
2290 // Get the address of the containing word.
2291 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2292 DAG.getConstant(-4, PtrVT));
2294 // Get the number of bits that the word must be rotated left in order
2295 // to bring the field to the top bits of a GR32.
2296 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2297 DAG.getConstant(3, PtrVT));
2298 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2300 // Get the complementing shift amount, for rotating a field in the top
2301 // bits back to its proper position.
2302 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2303 DAG.getConstant(0, WideVT), BitShift);
2305 // Construct the ATOMIC_CMP_SWAPW node.
2306 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2307 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
2308 NegBitShift, DAG.getConstant(BitSize, WideVT) };
2309 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
2310 VTList, Ops, array_lengthof(Ops),
2315 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
2316 SelectionDAG &DAG) const {
2317 MachineFunction &MF = DAG.getMachineFunction();
2318 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2319 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
2320 SystemZ::R15D, Op.getValueType());
2323 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
2324 SelectionDAG &DAG) const {
2325 MachineFunction &MF = DAG.getMachineFunction();
2326 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2327 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
2328 SystemZ::R15D, Op.getOperand(1));
2331 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
2332 SelectionDAG &DAG) const {
2333 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2335 // Just preserve the chain.
2336 return Op.getOperand(0);
2338 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2339 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
2340 MemIntrinsicSDNode *Node = cast<MemIntrinsicSDNode>(Op.getNode());
2343 DAG.getConstant(Code, MVT::i32),
2346 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
2347 Node->getVTList(), Ops, array_lengthof(Ops),
2348 Node->getMemoryVT(), Node->getMemOperand());
2351 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
2352 SelectionDAG &DAG) const {
2353 switch (Op.getOpcode()) {
2355 return lowerBR_CC(Op, DAG);
2356 case ISD::SELECT_CC:
2357 return lowerSELECT_CC(Op, DAG);
2359 return lowerSETCC(Op, DAG);
2360 case ISD::GlobalAddress:
2361 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
2362 case ISD::GlobalTLSAddress:
2363 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
2364 case ISD::BlockAddress:
2365 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
2366 case ISD::JumpTable:
2367 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
2368 case ISD::ConstantPool:
2369 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
2371 return lowerBITCAST(Op, DAG);
2373 return lowerVASTART(Op, DAG);
2375 return lowerVACOPY(Op, DAG);
2376 case ISD::DYNAMIC_STACKALLOC:
2377 return lowerDYNAMIC_STACKALLOC(Op, DAG);
2378 case ISD::SMUL_LOHI:
2379 return lowerSMUL_LOHI(Op, DAG);
2380 case ISD::UMUL_LOHI:
2381 return lowerUMUL_LOHI(Op, DAG);
2383 return lowerSDIVREM(Op, DAG);
2385 return lowerUDIVREM(Op, DAG);
2387 return lowerOR(Op, DAG);
2388 case ISD::ATOMIC_SWAP:
2389 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
2390 case ISD::ATOMIC_STORE:
2391 return lowerATOMIC_STORE(Op, DAG);
2392 case ISD::ATOMIC_LOAD:
2393 return lowerATOMIC_LOAD(Op, DAG);
2394 case ISD::ATOMIC_LOAD_ADD:
2395 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
2396 case ISD::ATOMIC_LOAD_SUB:
2397 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
2398 case ISD::ATOMIC_LOAD_AND:
2399 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
2400 case ISD::ATOMIC_LOAD_OR:
2401 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
2402 case ISD::ATOMIC_LOAD_XOR:
2403 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
2404 case ISD::ATOMIC_LOAD_NAND:
2405 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
2406 case ISD::ATOMIC_LOAD_MIN:
2407 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
2408 case ISD::ATOMIC_LOAD_MAX:
2409 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
2410 case ISD::ATOMIC_LOAD_UMIN:
2411 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
2412 case ISD::ATOMIC_LOAD_UMAX:
2413 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
2414 case ISD::ATOMIC_CMP_SWAP:
2415 return lowerATOMIC_CMP_SWAP(Op, DAG);
2416 case ISD::STACKSAVE:
2417 return lowerSTACKSAVE(Op, DAG);
2418 case ISD::STACKRESTORE:
2419 return lowerSTACKRESTORE(Op, DAG);
2421 return lowerPREFETCH(Op, DAG);
2423 llvm_unreachable("Unexpected node to lower");
2427 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
2428 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
2433 OPCODE(PCREL_WRAPPER);
2434 OPCODE(PCREL_OFFSET);
2440 OPCODE(SELECT_CCMASK);
2441 OPCODE(ADJDYNALLOC);
2442 OPCODE(EXTRACT_ACCESS);
2443 OPCODE(UMUL_LOHI64);
2459 OPCODE(SEARCH_STRING);
2462 OPCODE(ATOMIC_SWAPW);
2463 OPCODE(ATOMIC_LOADW_ADD);
2464 OPCODE(ATOMIC_LOADW_SUB);
2465 OPCODE(ATOMIC_LOADW_AND);
2466 OPCODE(ATOMIC_LOADW_OR);
2467 OPCODE(ATOMIC_LOADW_XOR);
2468 OPCODE(ATOMIC_LOADW_NAND);
2469 OPCODE(ATOMIC_LOADW_MIN);
2470 OPCODE(ATOMIC_LOADW_MAX);
2471 OPCODE(ATOMIC_LOADW_UMIN);
2472 OPCODE(ATOMIC_LOADW_UMAX);
2473 OPCODE(ATOMIC_CMP_SWAPW);
2480 //===----------------------------------------------------------------------===//
2482 //===----------------------------------------------------------------------===//
2484 // Create a new basic block after MBB.
2485 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
2486 MachineFunction &MF = *MBB->getParent();
2487 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2488 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
2492 // Split MBB after MI and return the new block (the one that contains
2493 // instructions after MI).
2494 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
2495 MachineBasicBlock *MBB) {
2496 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2497 NewMBB->splice(NewMBB->begin(), MBB,
2498 llvm::next(MachineBasicBlock::iterator(MI)),
2500 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2504 // Split MBB before MI and return the new block (the one that contains MI).
2505 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
2506 MachineBasicBlock *MBB) {
2507 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2508 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2509 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2513 // Force base value Base into a register before MI. Return the register.
2514 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
2515 const SystemZInstrInfo *TII) {
2517 return Base.getReg();
2519 MachineBasicBlock *MBB = MI->getParent();
2520 MachineFunction &MF = *MBB->getParent();
2521 MachineRegisterInfo &MRI = MF.getRegInfo();
2523 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2524 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2525 .addOperand(Base).addImm(0).addReg(0);
2529 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
2531 SystemZTargetLowering::emitSelect(MachineInstr *MI,
2532 MachineBasicBlock *MBB) const {
2533 const SystemZInstrInfo *TII = TM.getInstrInfo();
2535 unsigned DestReg = MI->getOperand(0).getReg();
2536 unsigned TrueReg = MI->getOperand(1).getReg();
2537 unsigned FalseReg = MI->getOperand(2).getReg();
2538 unsigned CCValid = MI->getOperand(3).getImm();
2539 unsigned CCMask = MI->getOperand(4).getImm();
2540 DebugLoc DL = MI->getDebugLoc();
2542 MachineBasicBlock *StartMBB = MBB;
2543 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2544 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2547 // BRC CCMask, JoinMBB
2548 // # fallthrough to FalseMBB
2550 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2551 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2552 MBB->addSuccessor(JoinMBB);
2553 MBB->addSuccessor(FalseMBB);
2556 // # fallthrough to JoinMBB
2558 MBB->addSuccessor(JoinMBB);
2561 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2564 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2565 .addReg(TrueReg).addMBB(StartMBB)
2566 .addReg(FalseReg).addMBB(FalseMBB);
2568 MI->eraseFromParent();
2572 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2573 // StoreOpcode is the store to use and Invert says whether the store should
2574 // happen when the condition is false rather than true. If a STORE ON
2575 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2577 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2578 MachineBasicBlock *MBB,
2579 unsigned StoreOpcode, unsigned STOCOpcode,
2580 bool Invert) const {
2581 const SystemZInstrInfo *TII = TM.getInstrInfo();
2583 unsigned SrcReg = MI->getOperand(0).getReg();
2584 MachineOperand Base = MI->getOperand(1);
2585 int64_t Disp = MI->getOperand(2).getImm();
2586 unsigned IndexReg = MI->getOperand(3).getReg();
2587 unsigned CCValid = MI->getOperand(4).getImm();
2588 unsigned CCMask = MI->getOperand(5).getImm();
2589 DebugLoc DL = MI->getDebugLoc();
2591 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2593 // Use STOCOpcode if possible. We could use different store patterns in
2594 // order to avoid matching the index register, but the performance trade-offs
2595 // might be more complicated in that case.
2596 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
2599 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2600 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2601 .addImm(CCValid).addImm(CCMask);
2602 MI->eraseFromParent();
2606 // Get the condition needed to branch around the store.
2610 MachineBasicBlock *StartMBB = MBB;
2611 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2612 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2615 // BRC CCMask, JoinMBB
2616 // # fallthrough to FalseMBB
2618 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2619 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2620 MBB->addSuccessor(JoinMBB);
2621 MBB->addSuccessor(FalseMBB);
2624 // store %SrcReg, %Disp(%Index,%Base)
2625 // # fallthrough to JoinMBB
2627 BuildMI(MBB, DL, TII->get(StoreOpcode))
2628 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2629 MBB->addSuccessor(JoinMBB);
2631 MI->eraseFromParent();
2635 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
2636 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
2637 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
2638 // BitSize is the width of the field in bits, or 0 if this is a partword
2639 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
2640 // is one of the operands. Invert says whether the field should be
2641 // inverted after performing BinOpcode (e.g. for NAND).
2643 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
2644 MachineBasicBlock *MBB,
2647 bool Invert) const {
2648 const SystemZInstrInfo *TII = TM.getInstrInfo();
2649 MachineFunction &MF = *MBB->getParent();
2650 MachineRegisterInfo &MRI = MF.getRegInfo();
2651 bool IsSubWord = (BitSize < 32);
2653 // Extract the operands. Base can be a register or a frame index.
2654 // Src2 can be a register or immediate.
2655 unsigned Dest = MI->getOperand(0).getReg();
2656 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2657 int64_t Disp = MI->getOperand(2).getImm();
2658 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
2659 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2660 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2661 DebugLoc DL = MI->getDebugLoc();
2663 BitSize = MI->getOperand(6).getImm();
2665 // Subword operations use 32-bit registers.
2666 const TargetRegisterClass *RC = (BitSize <= 32 ?
2667 &SystemZ::GR32BitRegClass :
2668 &SystemZ::GR64BitRegClass);
2669 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2670 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2672 // Get the right opcodes for the displacement.
2673 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2674 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2675 assert(LOpcode && CSOpcode && "Displacement out of range");
2677 // Create virtual registers for temporary results.
2678 unsigned OrigVal = MRI.createVirtualRegister(RC);
2679 unsigned OldVal = MRI.createVirtualRegister(RC);
2680 unsigned NewVal = (BinOpcode || IsSubWord ?
2681 MRI.createVirtualRegister(RC) : Src2.getReg());
2682 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2683 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2685 // Insert a basic block for the main loop.
2686 MachineBasicBlock *StartMBB = MBB;
2687 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2688 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2692 // %OrigVal = L Disp(%Base)
2693 // # fall through to LoopMMB
2695 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2696 .addOperand(Base).addImm(Disp).addReg(0);
2697 MBB->addSuccessor(LoopMBB);
2700 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
2701 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2702 // %RotatedNewVal = OP %RotatedOldVal, %Src2
2703 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2704 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2706 // # fall through to DoneMMB
2708 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2709 .addReg(OrigVal).addMBB(StartMBB)
2710 .addReg(Dest).addMBB(LoopMBB);
2712 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2713 .addReg(OldVal).addReg(BitShift).addImm(0);
2715 // Perform the operation normally and then invert every bit of the field.
2716 unsigned Tmp = MRI.createVirtualRegister(RC);
2717 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
2718 .addReg(RotatedOldVal).addOperand(Src2);
2720 // XILF with the upper BitSize bits set.
2721 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2722 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
2723 else if (BitSize == 32)
2724 // XILF with every bit set.
2725 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2726 .addReg(Tmp).addImm(~uint32_t(0));
2728 // Use LCGR and add -1 to the result, which is more compact than
2729 // an XILF, XILH pair.
2730 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2731 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2732 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2733 .addReg(Tmp2).addImm(-1);
2735 } else if (BinOpcode)
2736 // A simply binary operation.
2737 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2738 .addReg(RotatedOldVal).addOperand(Src2);
2740 // Use RISBG to rotate Src2 into position and use it to replace the
2741 // field in RotatedOldVal.
2742 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2743 .addReg(RotatedOldVal).addReg(Src2.getReg())
2744 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2746 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2747 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2748 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2749 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2750 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2751 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2752 MBB->addSuccessor(LoopMBB);
2753 MBB->addSuccessor(DoneMBB);
2755 MI->eraseFromParent();
2759 // Implement EmitInstrWithCustomInserter for pseudo
2760 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2761 // instruction that should be used to compare the current field with the
2762 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2763 // for when the current field should be kept. BitSize is the width of
2764 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2766 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2767 MachineBasicBlock *MBB,
2768 unsigned CompareOpcode,
2769 unsigned KeepOldMask,
2770 unsigned BitSize) const {
2771 const SystemZInstrInfo *TII = TM.getInstrInfo();
2772 MachineFunction &MF = *MBB->getParent();
2773 MachineRegisterInfo &MRI = MF.getRegInfo();
2774 bool IsSubWord = (BitSize < 32);
2776 // Extract the operands. Base can be a register or a frame index.
2777 unsigned Dest = MI->getOperand(0).getReg();
2778 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2779 int64_t Disp = MI->getOperand(2).getImm();
2780 unsigned Src2 = MI->getOperand(3).getReg();
2781 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2782 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2783 DebugLoc DL = MI->getDebugLoc();
2785 BitSize = MI->getOperand(6).getImm();
2787 // Subword operations use 32-bit registers.
2788 const TargetRegisterClass *RC = (BitSize <= 32 ?
2789 &SystemZ::GR32BitRegClass :
2790 &SystemZ::GR64BitRegClass);
2791 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2792 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2794 // Get the right opcodes for the displacement.
2795 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2796 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2797 assert(LOpcode && CSOpcode && "Displacement out of range");
2799 // Create virtual registers for temporary results.
2800 unsigned OrigVal = MRI.createVirtualRegister(RC);
2801 unsigned OldVal = MRI.createVirtualRegister(RC);
2802 unsigned NewVal = MRI.createVirtualRegister(RC);
2803 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2804 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2805 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2807 // Insert 3 basic blocks for the loop.
2808 MachineBasicBlock *StartMBB = MBB;
2809 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2810 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2811 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2812 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2816 // %OrigVal = L Disp(%Base)
2817 // # fall through to LoopMMB
2819 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2820 .addOperand(Base).addImm(Disp).addReg(0);
2821 MBB->addSuccessor(LoopMBB);
2824 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2825 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2826 // CompareOpcode %RotatedOldVal, %Src2
2827 // BRC KeepOldMask, UpdateMBB
2829 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2830 .addReg(OrigVal).addMBB(StartMBB)
2831 .addReg(Dest).addMBB(UpdateMBB);
2833 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2834 .addReg(OldVal).addReg(BitShift).addImm(0);
2835 BuildMI(MBB, DL, TII->get(CompareOpcode))
2836 .addReg(RotatedOldVal).addReg(Src2);
2837 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2838 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2839 MBB->addSuccessor(UpdateMBB);
2840 MBB->addSuccessor(UseAltMBB);
2843 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2844 // # fall through to UpdateMMB
2847 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2848 .addReg(RotatedOldVal).addReg(Src2)
2849 .addImm(32).addImm(31 + BitSize).addImm(0);
2850 MBB->addSuccessor(UpdateMBB);
2853 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2854 // [ %RotatedAltVal, UseAltMBB ]
2855 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2856 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2858 // # fall through to DoneMMB
2860 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2861 .addReg(RotatedOldVal).addMBB(LoopMBB)
2862 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2864 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2865 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2866 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2867 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2868 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2869 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2870 MBB->addSuccessor(LoopMBB);
2871 MBB->addSuccessor(DoneMBB);
2873 MI->eraseFromParent();
2877 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2880 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2881 MachineBasicBlock *MBB) const {
2882 const SystemZInstrInfo *TII = TM.getInstrInfo();
2883 MachineFunction &MF = *MBB->getParent();
2884 MachineRegisterInfo &MRI = MF.getRegInfo();
2886 // Extract the operands. Base can be a register or a frame index.
2887 unsigned Dest = MI->getOperand(0).getReg();
2888 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2889 int64_t Disp = MI->getOperand(2).getImm();
2890 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2891 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2892 unsigned BitShift = MI->getOperand(5).getReg();
2893 unsigned NegBitShift = MI->getOperand(6).getReg();
2894 int64_t BitSize = MI->getOperand(7).getImm();
2895 DebugLoc DL = MI->getDebugLoc();
2897 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2899 // Get the right opcodes for the displacement.
2900 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2901 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2902 assert(LOpcode && CSOpcode && "Displacement out of range");
2904 // Create virtual registers for temporary results.
2905 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2906 unsigned OldVal = MRI.createVirtualRegister(RC);
2907 unsigned CmpVal = MRI.createVirtualRegister(RC);
2908 unsigned SwapVal = MRI.createVirtualRegister(RC);
2909 unsigned StoreVal = MRI.createVirtualRegister(RC);
2910 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2911 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2912 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2914 // Insert 2 basic blocks for the loop.
2915 MachineBasicBlock *StartMBB = MBB;
2916 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2917 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2918 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2922 // %OrigOldVal = L Disp(%Base)
2923 // # fall through to LoopMMB
2925 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
2926 .addOperand(Base).addImm(Disp).addReg(0);
2927 MBB->addSuccessor(LoopMBB);
2930 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
2931 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
2932 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
2933 // %Dest = RLL %OldVal, BitSize(%BitShift)
2934 // ^^ The low BitSize bits contain the field
2936 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
2937 // ^^ Replace the upper 32-BitSize bits of the
2938 // comparison value with those that we loaded,
2939 // so that we can use a full word comparison.
2940 // CR %Dest, %RetryCmpVal
2942 // # Fall through to SetMBB
2944 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2945 .addReg(OrigOldVal).addMBB(StartMBB)
2946 .addReg(RetryOldVal).addMBB(SetMBB);
2947 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
2948 .addReg(OrigCmpVal).addMBB(StartMBB)
2949 .addReg(RetryCmpVal).addMBB(SetMBB);
2950 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
2951 .addReg(OrigSwapVal).addMBB(StartMBB)
2952 .addReg(RetrySwapVal).addMBB(SetMBB);
2953 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
2954 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
2955 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
2956 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2957 BuildMI(MBB, DL, TII->get(SystemZ::CR))
2958 .addReg(Dest).addReg(RetryCmpVal);
2959 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2960 .addImm(SystemZ::CCMASK_ICMP)
2961 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
2962 MBB->addSuccessor(DoneMBB);
2963 MBB->addSuccessor(SetMBB);
2966 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
2967 // ^^ Replace the upper 32-BitSize bits of the new
2968 // value with those that we loaded.
2969 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
2970 // ^^ Rotate the new field to its proper position.
2971 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
2973 // # fall through to ExitMMB
2975 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
2976 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2977 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
2978 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
2979 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
2980 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2981 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2982 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2983 MBB->addSuccessor(LoopMBB);
2984 MBB->addSuccessor(DoneMBB);
2986 MI->eraseFromParent();
2990 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
2991 // if the high register of the GR128 value must be cleared or false if
2992 // it's "don't care". SubReg is subreg_l32 when extending a GR32
2993 // and subreg_l64 when extending a GR64.
2995 SystemZTargetLowering::emitExt128(MachineInstr *MI,
2996 MachineBasicBlock *MBB,
2997 bool ClearEven, unsigned SubReg) const {
2998 const SystemZInstrInfo *TII = TM.getInstrInfo();
2999 MachineFunction &MF = *MBB->getParent();
3000 MachineRegisterInfo &MRI = MF.getRegInfo();
3001 DebugLoc DL = MI->getDebugLoc();
3003 unsigned Dest = MI->getOperand(0).getReg();
3004 unsigned Src = MI->getOperand(1).getReg();
3005 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3007 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
3009 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3010 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
3012 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
3014 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
3015 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
3018 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
3019 .addReg(In128).addReg(Src).addImm(SubReg);
3021 MI->eraseFromParent();
3026 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
3027 MachineBasicBlock *MBB,
3028 unsigned Opcode) const {
3029 const SystemZInstrInfo *TII = TM.getInstrInfo();
3030 MachineFunction &MF = *MBB->getParent();
3031 MachineRegisterInfo &MRI = MF.getRegInfo();
3032 DebugLoc DL = MI->getDebugLoc();
3034 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
3035 uint64_t DestDisp = MI->getOperand(1).getImm();
3036 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
3037 uint64_t SrcDisp = MI->getOperand(3).getImm();
3038 uint64_t Length = MI->getOperand(4).getImm();
3040 // When generating more than one CLC, all but the last will need to
3041 // branch to the end when a difference is found.
3042 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
3043 splitBlockAfter(MI, MBB) : 0);
3045 // Check for the loop form, in which operand 5 is the trip count.
3046 if (MI->getNumExplicitOperands() > 5) {
3047 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
3049 uint64_t StartCountReg = MI->getOperand(5).getReg();
3050 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
3051 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
3052 forceReg(MI, DestBase, TII));
3054 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
3055 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
3056 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
3057 MRI.createVirtualRegister(RC));
3058 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
3059 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
3060 MRI.createVirtualRegister(RC));
3062 RC = &SystemZ::GR64BitRegClass;
3063 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
3064 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
3066 MachineBasicBlock *StartMBB = MBB;
3067 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3068 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3069 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
3072 // # fall through to LoopMMB
3073 MBB->addSuccessor(LoopMBB);
3076 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
3077 // [ %NextDestReg, NextMBB ]
3078 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
3079 // [ %NextSrcReg, NextMBB ]
3080 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
3081 // [ %NextCountReg, NextMBB ]
3082 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
3083 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
3086 // The prefetch is used only for MVC. The JLH is used only for CLC.
3089 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
3090 .addReg(StartDestReg).addMBB(StartMBB)
3091 .addReg(NextDestReg).addMBB(NextMBB);
3092 if (!HaveSingleBase)
3093 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
3094 .addReg(StartSrcReg).addMBB(StartMBB)
3095 .addReg(NextSrcReg).addMBB(NextMBB);
3096 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
3097 .addReg(StartCountReg).addMBB(StartMBB)
3098 .addReg(NextCountReg).addMBB(NextMBB);
3099 if (Opcode == SystemZ::MVC)
3100 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
3101 .addImm(SystemZ::PFD_WRITE)
3102 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
3103 BuildMI(MBB, DL, TII->get(Opcode))
3104 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
3105 .addReg(ThisSrcReg).addImm(SrcDisp);
3107 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3108 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3110 MBB->addSuccessor(EndMBB);
3111 MBB->addSuccessor(NextMBB);
3115 // %NextDestReg = LA 256(%ThisDestReg)
3116 // %NextSrcReg = LA 256(%ThisSrcReg)
3117 // %NextCountReg = AGHI %ThisCountReg, -1
3118 // CGHI %NextCountReg, 0
3120 // # fall through to DoneMMB
3122 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
3125 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
3126 .addReg(ThisDestReg).addImm(256).addReg(0);
3127 if (!HaveSingleBase)
3128 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
3129 .addReg(ThisSrcReg).addImm(256).addReg(0);
3130 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
3131 .addReg(ThisCountReg).addImm(-1);
3132 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
3133 .addReg(NextCountReg).addImm(0);
3134 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3135 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3137 MBB->addSuccessor(LoopMBB);
3138 MBB->addSuccessor(DoneMBB);
3140 DestBase = MachineOperand::CreateReg(NextDestReg, false);
3141 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
3145 // Handle any remaining bytes with straight-line code.
3146 while (Length > 0) {
3147 uint64_t ThisLength = std::min(Length, uint64_t(256));
3148 // The previous iteration might have created out-of-range displacements.
3149 // Apply them using LAY if so.
3150 if (!isUInt<12>(DestDisp)) {
3151 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3152 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3153 .addOperand(DestBase).addImm(DestDisp).addReg(0);
3154 DestBase = MachineOperand::CreateReg(Reg, false);
3157 if (!isUInt<12>(SrcDisp)) {
3158 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3159 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3160 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
3161 SrcBase = MachineOperand::CreateReg(Reg, false);
3164 BuildMI(*MBB, MI, DL, TII->get(Opcode))
3165 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
3166 .addOperand(SrcBase).addImm(SrcDisp);
3167 DestDisp += ThisLength;
3168 SrcDisp += ThisLength;
3169 Length -= ThisLength;
3170 // If there's another CLC to go, branch to the end if a difference
3172 if (EndMBB && Length > 0) {
3173 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
3174 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3175 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3177 MBB->addSuccessor(EndMBB);
3178 MBB->addSuccessor(NextMBB);
3183 MBB->addSuccessor(EndMBB);
3185 MBB->addLiveIn(SystemZ::CC);
3188 MI->eraseFromParent();
3192 // Decompose string pseudo-instruction MI into a loop that continually performs
3193 // Opcode until CC != 3.
3195 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
3196 MachineBasicBlock *MBB,
3197 unsigned Opcode) const {
3198 const SystemZInstrInfo *TII = TM.getInstrInfo();
3199 MachineFunction &MF = *MBB->getParent();
3200 MachineRegisterInfo &MRI = MF.getRegInfo();
3201 DebugLoc DL = MI->getDebugLoc();
3203 uint64_t End1Reg = MI->getOperand(0).getReg();
3204 uint64_t Start1Reg = MI->getOperand(1).getReg();
3205 uint64_t Start2Reg = MI->getOperand(2).getReg();
3206 uint64_t CharReg = MI->getOperand(3).getReg();
3208 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
3209 uint64_t This1Reg = MRI.createVirtualRegister(RC);
3210 uint64_t This2Reg = MRI.createVirtualRegister(RC);
3211 uint64_t End2Reg = MRI.createVirtualRegister(RC);
3213 MachineBasicBlock *StartMBB = MBB;
3214 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3215 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3218 // # fall through to LoopMMB
3219 MBB->addSuccessor(LoopMBB);
3222 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
3223 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
3225 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
3227 // # fall through to DoneMMB
3229 // The load of R0L can be hoisted by post-RA LICM.
3232 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
3233 .addReg(Start1Reg).addMBB(StartMBB)
3234 .addReg(End1Reg).addMBB(LoopMBB);
3235 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
3236 .addReg(Start2Reg).addMBB(StartMBB)
3237 .addReg(End2Reg).addMBB(LoopMBB);
3238 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
3239 BuildMI(MBB, DL, TII->get(Opcode))
3240 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
3241 .addReg(This1Reg).addReg(This2Reg);
3242 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3243 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
3244 MBB->addSuccessor(LoopMBB);
3245 MBB->addSuccessor(DoneMBB);
3247 DoneMBB->addLiveIn(SystemZ::CC);
3249 MI->eraseFromParent();
3253 MachineBasicBlock *SystemZTargetLowering::
3254 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
3255 switch (MI->getOpcode()) {
3256 case SystemZ::Select32Mux:
3257 case SystemZ::Select32:
3258 case SystemZ::SelectF32:
3259 case SystemZ::Select64:
3260 case SystemZ::SelectF64:
3261 case SystemZ::SelectF128:
3262 return emitSelect(MI, MBB);
3264 case SystemZ::CondStore8Mux:
3265 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
3266 case SystemZ::CondStore8MuxInv:
3267 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
3268 case SystemZ::CondStore16Mux:
3269 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
3270 case SystemZ::CondStore16MuxInv:
3271 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
3272 case SystemZ::CondStore8:
3273 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
3274 case SystemZ::CondStore8Inv:
3275 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
3276 case SystemZ::CondStore16:
3277 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
3278 case SystemZ::CondStore16Inv:
3279 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
3280 case SystemZ::CondStore32:
3281 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
3282 case SystemZ::CondStore32Inv:
3283 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
3284 case SystemZ::CondStore64:
3285 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
3286 case SystemZ::CondStore64Inv:
3287 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
3288 case SystemZ::CondStoreF32:
3289 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
3290 case SystemZ::CondStoreF32Inv:
3291 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
3292 case SystemZ::CondStoreF64:
3293 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
3294 case SystemZ::CondStoreF64Inv:
3295 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
3297 case SystemZ::AEXT128_64:
3298 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
3299 case SystemZ::ZEXT128_32:
3300 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
3301 case SystemZ::ZEXT128_64:
3302 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
3304 case SystemZ::ATOMIC_SWAPW:
3305 return emitAtomicLoadBinary(MI, MBB, 0, 0);
3306 case SystemZ::ATOMIC_SWAP_32:
3307 return emitAtomicLoadBinary(MI, MBB, 0, 32);
3308 case SystemZ::ATOMIC_SWAP_64:
3309 return emitAtomicLoadBinary(MI, MBB, 0, 64);
3311 case SystemZ::ATOMIC_LOADW_AR:
3312 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
3313 case SystemZ::ATOMIC_LOADW_AFI:
3314 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
3315 case SystemZ::ATOMIC_LOAD_AR:
3316 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
3317 case SystemZ::ATOMIC_LOAD_AHI:
3318 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
3319 case SystemZ::ATOMIC_LOAD_AFI:
3320 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
3321 case SystemZ::ATOMIC_LOAD_AGR:
3322 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
3323 case SystemZ::ATOMIC_LOAD_AGHI:
3324 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
3325 case SystemZ::ATOMIC_LOAD_AGFI:
3326 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
3328 case SystemZ::ATOMIC_LOADW_SR:
3329 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
3330 case SystemZ::ATOMIC_LOAD_SR:
3331 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
3332 case SystemZ::ATOMIC_LOAD_SGR:
3333 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
3335 case SystemZ::ATOMIC_LOADW_NR:
3336 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
3337 case SystemZ::ATOMIC_LOADW_NILH:
3338 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
3339 case SystemZ::ATOMIC_LOAD_NR:
3340 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
3341 case SystemZ::ATOMIC_LOAD_NILL:
3342 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
3343 case SystemZ::ATOMIC_LOAD_NILH:
3344 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
3345 case SystemZ::ATOMIC_LOAD_NILF:
3346 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
3347 case SystemZ::ATOMIC_LOAD_NGR:
3348 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
3349 case SystemZ::ATOMIC_LOAD_NILL64:
3350 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
3351 case SystemZ::ATOMIC_LOAD_NILH64:
3352 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
3353 case SystemZ::ATOMIC_LOAD_NIHL64:
3354 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
3355 case SystemZ::ATOMIC_LOAD_NIHH64:
3356 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
3357 case SystemZ::ATOMIC_LOAD_NILF64:
3358 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
3359 case SystemZ::ATOMIC_LOAD_NIHF64:
3360 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
3362 case SystemZ::ATOMIC_LOADW_OR:
3363 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
3364 case SystemZ::ATOMIC_LOADW_OILH:
3365 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
3366 case SystemZ::ATOMIC_LOAD_OR:
3367 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
3368 case SystemZ::ATOMIC_LOAD_OILL:
3369 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
3370 case SystemZ::ATOMIC_LOAD_OILH:
3371 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
3372 case SystemZ::ATOMIC_LOAD_OILF:
3373 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
3374 case SystemZ::ATOMIC_LOAD_OGR:
3375 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
3376 case SystemZ::ATOMIC_LOAD_OILL64:
3377 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
3378 case SystemZ::ATOMIC_LOAD_OILH64:
3379 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
3380 case SystemZ::ATOMIC_LOAD_OIHL64:
3381 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
3382 case SystemZ::ATOMIC_LOAD_OIHH64:
3383 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
3384 case SystemZ::ATOMIC_LOAD_OILF64:
3385 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
3386 case SystemZ::ATOMIC_LOAD_OIHF64:
3387 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
3389 case SystemZ::ATOMIC_LOADW_XR:
3390 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
3391 case SystemZ::ATOMIC_LOADW_XILF:
3392 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
3393 case SystemZ::ATOMIC_LOAD_XR:
3394 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
3395 case SystemZ::ATOMIC_LOAD_XILF:
3396 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
3397 case SystemZ::ATOMIC_LOAD_XGR:
3398 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
3399 case SystemZ::ATOMIC_LOAD_XILF64:
3400 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
3401 case SystemZ::ATOMIC_LOAD_XIHF64:
3402 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
3404 case SystemZ::ATOMIC_LOADW_NRi:
3405 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
3406 case SystemZ::ATOMIC_LOADW_NILHi:
3407 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
3408 case SystemZ::ATOMIC_LOAD_NRi:
3409 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
3410 case SystemZ::ATOMIC_LOAD_NILLi:
3411 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
3412 case SystemZ::ATOMIC_LOAD_NILHi:
3413 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
3414 case SystemZ::ATOMIC_LOAD_NILFi:
3415 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
3416 case SystemZ::ATOMIC_LOAD_NGRi:
3417 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
3418 case SystemZ::ATOMIC_LOAD_NILL64i:
3419 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
3420 case SystemZ::ATOMIC_LOAD_NILH64i:
3421 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
3422 case SystemZ::ATOMIC_LOAD_NIHL64i:
3423 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
3424 case SystemZ::ATOMIC_LOAD_NIHH64i:
3425 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
3426 case SystemZ::ATOMIC_LOAD_NILF64i:
3427 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
3428 case SystemZ::ATOMIC_LOAD_NIHF64i:
3429 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
3431 case SystemZ::ATOMIC_LOADW_MIN:
3432 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3433 SystemZ::CCMASK_CMP_LE, 0);
3434 case SystemZ::ATOMIC_LOAD_MIN_32:
3435 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3436 SystemZ::CCMASK_CMP_LE, 32);
3437 case SystemZ::ATOMIC_LOAD_MIN_64:
3438 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3439 SystemZ::CCMASK_CMP_LE, 64);
3441 case SystemZ::ATOMIC_LOADW_MAX:
3442 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3443 SystemZ::CCMASK_CMP_GE, 0);
3444 case SystemZ::ATOMIC_LOAD_MAX_32:
3445 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3446 SystemZ::CCMASK_CMP_GE, 32);
3447 case SystemZ::ATOMIC_LOAD_MAX_64:
3448 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3449 SystemZ::CCMASK_CMP_GE, 64);
3451 case SystemZ::ATOMIC_LOADW_UMIN:
3452 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3453 SystemZ::CCMASK_CMP_LE, 0);
3454 case SystemZ::ATOMIC_LOAD_UMIN_32:
3455 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3456 SystemZ::CCMASK_CMP_LE, 32);
3457 case SystemZ::ATOMIC_LOAD_UMIN_64:
3458 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3459 SystemZ::CCMASK_CMP_LE, 64);
3461 case SystemZ::ATOMIC_LOADW_UMAX:
3462 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3463 SystemZ::CCMASK_CMP_GE, 0);
3464 case SystemZ::ATOMIC_LOAD_UMAX_32:
3465 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3466 SystemZ::CCMASK_CMP_GE, 32);
3467 case SystemZ::ATOMIC_LOAD_UMAX_64:
3468 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3469 SystemZ::CCMASK_CMP_GE, 64);
3471 case SystemZ::ATOMIC_CMP_SWAPW:
3472 return emitAtomicCmpSwapW(MI, MBB);
3473 case SystemZ::MVCSequence:
3474 case SystemZ::MVCLoop:
3475 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
3476 case SystemZ::NCSequence:
3477 case SystemZ::NCLoop:
3478 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
3479 case SystemZ::OCSequence:
3480 case SystemZ::OCLoop:
3481 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
3482 case SystemZ::XCSequence:
3483 case SystemZ::XCLoop:
3484 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
3485 case SystemZ::CLCSequence:
3486 case SystemZ::CLCLoop:
3487 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
3488 case SystemZ::CLSTLoop:
3489 return emitStringWrapper(MI, MBB, SystemZ::CLST);
3490 case SystemZ::MVSTLoop:
3491 return emitStringWrapper(MI, MBB, SystemZ::MVST);
3492 case SystemZ::SRSTLoop:
3493 return emitStringWrapper(MI, MBB, SystemZ::SRST);
3495 llvm_unreachable("Unexpected instr type to insert");