1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/VectorExtras.h"
39 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
40 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
42 RegInfo = TM.getRegisterInfo();
44 // Set up the register classes.
45 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
46 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
47 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
48 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
51 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
52 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
54 addLegalFPImmediate(APFloat(+0.0)); // lzer
55 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
56 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
57 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set shifts properties
64 setShiftAmountFlavor(Extend);
65 setShiftAmountType(MVT::i64);
67 // Provide all sorts of operation actions
68 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
69 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
72 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
74 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
76 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
78 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
80 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
81 setSchedulingPreference(SchedulingForLatency);
82 setBooleanContents(ZeroOrOneBooleanContent);
84 setOperationAction(ISD::RET, MVT::Other, Custom);
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
88 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
89 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
91 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
93 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
94 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
95 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
96 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
98 setOperationAction(ISD::SDIV, MVT::i32, Expand);
99 setOperationAction(ISD::UDIV, MVT::i32, Expand);
100 setOperationAction(ISD::SDIV, MVT::i64, Expand);
101 setOperationAction(ISD::UDIV, MVT::i64, Expand);
102 setOperationAction(ISD::SREM, MVT::i32, Expand);
103 setOperationAction(ISD::UREM, MVT::i32, Expand);
104 setOperationAction(ISD::SREM, MVT::i64, Expand);
105 setOperationAction(ISD::UREM, MVT::i64, Expand);
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
109 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
110 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
111 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
112 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
113 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
114 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
116 // FIXME: Can we lower these 2 efficiently?
117 setOperationAction(ISD::SETCC, MVT::i32, Expand);
118 setOperationAction(ISD::SETCC, MVT::i64, Expand);
119 setOperationAction(ISD::SETCC, MVT::f32, Expand);
120 setOperationAction(ISD::SETCC, MVT::f64, Expand);
121 setOperationAction(ISD::SELECT, MVT::i32, Expand);
122 setOperationAction(ISD::SELECT, MVT::i64, Expand);
123 setOperationAction(ISD::SELECT, MVT::f32, Expand);
124 setOperationAction(ISD::SELECT, MVT::f64, Expand);
125 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
126 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
130 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
132 setOperationAction(ISD::MULHS, MVT::i64, Expand);
133 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
135 // Lower some FP stuff
136 setOperationAction(ISD::FSIN, MVT::f32, Expand);
137 setOperationAction(ISD::FSIN, MVT::f64, Expand);
138 setOperationAction(ISD::FCOS, MVT::f32, Expand);
139 setOperationAction(ISD::FCOS, MVT::f64, Expand);
141 // We have only 64-bit bitconverts
142 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
143 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
145 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
146 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
147 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
148 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
153 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
154 switch (Op.getOpcode()) {
155 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
156 case ISD::RET: return LowerRET(Op, DAG);
157 case ISD::CALL: return LowerCALL(Op, DAG);
158 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
159 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
160 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
161 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
162 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
164 assert(0 && "unimplemented operand");
169 //===----------------------------------------------------------------------===//
170 // Calling Convention Implementation
171 //===----------------------------------------------------------------------===//
173 #include "SystemZGenCallingConv.inc"
175 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
177 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
180 assert(0 && "Unsupported calling convention");
182 case CallingConv::Fast:
183 return LowerCCCArguments(Op, DAG);
187 SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
188 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
189 unsigned CallingConv = TheCall->getCallingConv();
190 switch (CallingConv) {
192 assert(0 && "Unsupported calling convention");
193 case CallingConv::Fast:
195 return LowerCCCCallTo(Op, DAG, CallingConv);
199 /// LowerCCCArguments - transform physical registers into virtual registers and
200 /// generate load operations for arguments places on the stack.
201 // FIXME: struct return stuff
203 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
205 MachineFunction &MF = DAG.getMachineFunction();
206 MachineFrameInfo *MFI = MF.getFrameInfo();
207 MachineRegisterInfo &RegInfo = MF.getRegInfo();
208 SDValue Root = Op.getOperand(0);
209 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
210 unsigned CC = MF.getFunction()->getCallingConv();
211 DebugLoc dl = Op.getDebugLoc();
213 // Assign locations to all of the incoming arguments.
214 SmallVector<CCValAssign, 16> ArgLocs;
215 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
216 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
218 assert(!isVarArg && "Varargs not supported yet");
220 SmallVector<SDValue, 16> ArgValues;
221 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
223 CCValAssign &VA = ArgLocs[i];
224 MVT LocVT = VA.getLocVT();
226 // Arguments passed in registers
227 TargetRegisterClass *RC;
228 switch (LocVT.getSimpleVT()) {
230 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
231 << LocVT.getSimpleVT()
235 RC = SystemZ::GR64RegisterClass;
238 RC = SystemZ::FP32RegisterClass;
241 RC = SystemZ::FP64RegisterClass;
245 unsigned VReg = RegInfo.createVirtualRegister(RC);
246 RegInfo.addLiveIn(VA.getLocReg(), VReg);
247 ArgValue = DAG.getCopyFromReg(Root, dl, VReg, LocVT);
250 assert(VA.isMemLoc());
252 // Create the nodes corresponding to a load from this parameter slot.
253 // Create the frame index object for this incoming parameter...
254 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
255 VA.getLocMemOffset());
257 // Create the SelectionDAG nodes corresponding to a load
258 // from this parameter
259 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
260 ArgValue = DAG.getLoad(LocVT, dl, Root, FIN,
261 PseudoSourceValue::getFixedStack(FI), 0);
264 // If this is an 8/16/32-bit value, it is really passed promoted to 64
265 // bits. Insert an assert[sz]ext to capture this, then truncate to the
267 if (VA.getLocInfo() == CCValAssign::SExt)
268 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
269 DAG.getValueType(VA.getValVT()));
270 else if (VA.getLocInfo() == CCValAssign::ZExt)
271 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
272 DAG.getValueType(VA.getValVT()));
274 if (VA.getLocInfo() != CCValAssign::Full)
275 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
277 ArgValues.push_back(ArgValue);
280 ArgValues.push_back(Root);
282 // Return the new list of results.
283 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
284 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
287 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
288 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
290 SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
292 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
293 SDValue Chain = TheCall->getChain();
294 SDValue Callee = TheCall->getCallee();
295 bool isVarArg = TheCall->isVarArg();
296 DebugLoc dl = Op.getDebugLoc();
297 MachineFunction &MF = DAG.getMachineFunction();
299 // Offset to first argument stack slot.
300 const unsigned FirstArgOffset = 160;
302 // Analyze operands of the call, assigning locations to each operand.
303 SmallVector<CCValAssign, 16> ArgLocs;
304 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
306 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
308 // Get a count of how many bytes are to be pushed on the stack.
309 unsigned NumBytes = CCInfo.getNextStackOffset();
311 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
312 getPointerTy(), true));
314 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
315 SmallVector<SDValue, 12> MemOpChains;
318 // Walk the register/memloc assignments, inserting copies/loads.
319 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
320 CCValAssign &VA = ArgLocs[i];
322 // Arguments start after the 5 first operands of ISD::CALL
323 SDValue Arg = TheCall->getArg(i);
325 // Promote the value if needed.
326 switch (VA.getLocInfo()) {
327 default: assert(0 && "Unknown loc info!");
328 case CCValAssign::Full: break;
329 case CCValAssign::SExt:
330 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
332 case CCValAssign::ZExt:
333 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
335 case CCValAssign::AExt:
336 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
340 // Arguments that can be passed on register must be kept at RegsToPass
343 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
345 assert(VA.isMemLoc());
347 if (StackPtr.getNode() == 0)
349 DAG.getCopyFromReg(Chain, dl,
350 (RegInfo->hasFP(MF) ?
351 SystemZ::R11D : SystemZ::R15D),
354 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
355 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
357 DAG.getIntPtrConstant(Offset));
359 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
360 PseudoSourceValue::getStack(), Offset));
364 // Transform all store nodes into one single node because all store nodes are
365 // independent of each other.
366 if (!MemOpChains.empty())
367 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
368 &MemOpChains[0], MemOpChains.size());
370 // Build a sequence of copy-to-reg nodes chained together with token chain and
371 // flag operands which copy the outgoing args into registers. The InFlag in
372 // necessary since all emited instructions must be stuck together.
374 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
375 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
376 RegsToPass[i].second, InFlag);
377 InFlag = Chain.getValue(1);
380 // If the callee is a GlobalAddress node (quite common, every direct call is)
381 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
382 // Likewise ExternalSymbol -> TargetExternalSymbol.
383 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
384 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
385 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
386 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
388 // Returns a chain & a flag for retval copy to use.
389 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
390 SmallVector<SDValue, 8> Ops;
391 Ops.push_back(Chain);
392 Ops.push_back(Callee);
394 // Add argument registers to the end of the list so that they are
395 // known live into the call.
396 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
397 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
398 RegsToPass[i].second.getValueType()));
400 if (InFlag.getNode())
401 Ops.push_back(InFlag);
403 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
404 InFlag = Chain.getValue(1);
406 // Create the CALLSEQ_END node.
407 Chain = DAG.getCALLSEQ_END(Chain,
408 DAG.getConstant(NumBytes, getPointerTy(), true),
409 DAG.getConstant(0, getPointerTy(), true),
411 InFlag = Chain.getValue(1);
413 // Handle result values, copying them out of physregs into vregs that we
415 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
419 /// LowerCallResult - Lower the result values of an ISD::CALL into the
420 /// appropriate copies out of appropriate physical registers. This assumes that
421 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
422 /// being lowered. Returns a SDNode with the same number of values as the
425 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
427 unsigned CallingConv,
429 bool isVarArg = TheCall->isVarArg();
430 DebugLoc dl = TheCall->getDebugLoc();
432 // Assign locations to each value returned by this call.
433 SmallVector<CCValAssign, 16> RVLocs;
434 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs,
437 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
438 SmallVector<SDValue, 8> ResultVals;
440 // Copy all of the result registers out of their specified physreg.
441 for (unsigned i = 0; i != RVLocs.size(); ++i) {
442 CCValAssign &VA = RVLocs[i];
444 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
445 VA.getLocVT(), InFlag).getValue(1);
446 SDValue RetValue = Chain.getValue(0);
447 InFlag = Chain.getValue(2);
449 // If this is an 8/16/32-bit value, it is really passed promoted to 64
450 // bits. Insert an assert[sz]ext to capture this, then truncate to the
452 if (VA.getLocInfo() == CCValAssign::SExt)
453 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
454 DAG.getValueType(VA.getValVT()));
455 else if (VA.getLocInfo() == CCValAssign::ZExt)
456 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
457 DAG.getValueType(VA.getValVT()));
459 if (VA.getLocInfo() != CCValAssign::Full)
460 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
462 ResultVals.push_back(RetValue);
465 ResultVals.push_back(Chain);
467 // Merge everything together with a MERGE_VALUES node.
468 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
469 &ResultVals[0], ResultVals.size()).getNode();
473 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
474 // CCValAssign - represent the assignment of the return value to a location
475 SmallVector<CCValAssign, 16> RVLocs;
476 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
477 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
478 DebugLoc dl = Op.getDebugLoc();
480 // CCState - Info about the registers and stack slot.
481 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
483 // Analize return values of ISD::RET
484 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
486 // If this is the first return lowered for this function, add the regs to the
487 // liveout set for the function.
488 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
489 for (unsigned i = 0; i != RVLocs.size(); ++i)
490 if (RVLocs[i].isRegLoc())
491 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
494 // The chain is always operand #0
495 SDValue Chain = Op.getOperand(0);
498 // Copy the result values into the output registers.
499 for (unsigned i = 0; i != RVLocs.size(); ++i) {
500 CCValAssign &VA = RVLocs[i];
501 SDValue ResValue = Op.getOperand(i*2+1);
502 assert(VA.isRegLoc() && "Can only return in registers!");
504 // If this is an 8/16/32-bit value, it is really should be passed promoted
506 if (VA.getLocInfo() == CCValAssign::SExt)
507 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
508 else if (VA.getLocInfo() == CCValAssign::ZExt)
509 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
510 else if (VA.getLocInfo() == CCValAssign::AExt)
511 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
513 // ISD::RET => ret chain, (regnum1,val1), ...
514 // So i*2+1 index only the regnums
515 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
517 // Guarantee that all emitted copies are stuck together,
518 // avoiding something bad.
519 Flag = Chain.getValue(1);
523 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
526 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
529 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
530 ISD::CondCode CC, SDValue &SystemZCC,
532 // FIXME: Emit a test if RHS is zero
534 bool isUnsigned = false;
535 SystemZCC::CondCodes TCC;
537 default: assert(0 && "Invalid integer condition!");
543 TCC = SystemZCC::NLH;
559 if (LHS.getValueType().isFloatingPoint()) {
563 isUnsigned = true; // FALLTHROUGH
569 if (LHS.getValueType().isFloatingPoint()) {
573 isUnsigned = true; // FALLTHROUGH
579 if (LHS.getValueType().isFloatingPoint()) {
580 TCC = SystemZCC::NLE;
583 isUnsigned = true; // FALLTHROUGH
589 if (LHS.getValueType().isFloatingPoint()) {
590 TCC = SystemZCC::NHE;
593 isUnsigned = true; // FALLTHROUGH
600 SystemZCC = DAG.getConstant(TCC, MVT::i32);
602 DebugLoc dl = LHS.getDebugLoc();
603 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
604 dl, MVT::Flag, LHS, RHS);
608 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
609 SDValue Chain = Op.getOperand(0);
610 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
611 SDValue LHS = Op.getOperand(2);
612 SDValue RHS = Op.getOperand(3);
613 SDValue Dest = Op.getOperand(4);
614 DebugLoc dl = Op.getDebugLoc();
617 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
618 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
619 Chain, Dest, SystemZCC, Flag);
622 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
623 SDValue LHS = Op.getOperand(0);
624 SDValue RHS = Op.getOperand(1);
625 SDValue TrueV = Op.getOperand(2);
626 SDValue FalseV = Op.getOperand(3);
627 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
628 DebugLoc dl = Op.getDebugLoc();
631 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
633 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
634 SmallVector<SDValue, 4> Ops;
635 Ops.push_back(TrueV);
636 Ops.push_back(FalseV);
637 Ops.push_back(SystemZCC);
640 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
643 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
645 DebugLoc dl = Op.getDebugLoc();
646 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
647 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
649 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
650 bool ExtraLoadRequired =
651 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
654 if (!IsPic && !ExtraLoadRequired) {
655 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
658 unsigned char OpFlags = 0;
659 if (ExtraLoadRequired)
660 OpFlags = SystemZII::MO_GOTENT;
662 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
665 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
666 getPointerTy(), Result);
668 if (ExtraLoadRequired)
669 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
670 PseudoSourceValue::getGOT(), 0);
672 // If there was a non-zero offset that we didn't fold, create an explicit
675 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
676 DAG.getConstant(Offset, getPointerTy()));
682 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
684 DebugLoc dl = Op.getDebugLoc();
685 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
686 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
688 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
693 // FIXME: This is just dirty hack. We need to lower cpool properly
694 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
696 DebugLoc dl = Op.getDebugLoc();
697 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
699 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
703 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
706 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
708 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
709 case SystemZISD::CALL: return "SystemZISD::CALL";
710 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
711 case SystemZISD::CMP: return "SystemZISD::CMP";
712 case SystemZISD::UCMP: return "SystemZISD::UCMP";
713 case SystemZISD::SELECT: return "SystemZISD::SELECT";
714 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
715 default: return NULL;
719 //===----------------------------------------------------------------------===//
720 // Other Lowering Code
721 //===----------------------------------------------------------------------===//
724 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
725 MachineBasicBlock *BB) const {
726 const SystemZInstrInfo &TII = *TM.getInstrInfo();
727 DebugLoc dl = MI->getDebugLoc();
728 assert((MI->getOpcode() == SystemZ::Select32 ||
729 MI->getOpcode() == SystemZ::SelectF32 ||
730 MI->getOpcode() == SystemZ::Select64 ||
731 MI->getOpcode() == SystemZ::SelectF64) &&
732 "Unexpected instr type to insert");
734 // To "insert" a SELECT instruction, we actually have to insert the diamond
735 // control-flow pattern. The incoming instruction knows the destination vreg
736 // to set, the condition code register to branch on, the true/false values to
737 // select between, and a branch opcode to use.
738 const BasicBlock *LLVM_BB = BB->getBasicBlock();
739 MachineFunction::iterator I = BB;
747 // fallthrough --> copy0MBB
748 MachineBasicBlock *thisMBB = BB;
749 MachineFunction *F = BB->getParent();
750 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
751 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
752 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
753 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
754 F->insert(I, copy0MBB);
755 F->insert(I, copy1MBB);
756 // Update machine-CFG edges by transferring all successors of the current
757 // block to the new block which will contain the Phi node for the select.
758 copy1MBB->transferSuccessors(BB);
759 // Next, add the true and fallthrough blocks as its successors.
760 BB->addSuccessor(copy0MBB);
761 BB->addSuccessor(copy1MBB);
765 // # fallthrough to copy1MBB
768 // Update machine-CFG edges
769 BB->addSuccessor(copy1MBB);
772 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
775 BuildMI(BB, dl, TII.get(SystemZ::PHI),
776 MI->getOperand(0).getReg())
777 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
778 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
780 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.